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Merge remote-tracking branch 'regulator/topic/da9063' into regulator-next
[deliverable/linux.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
079d88cc
WF		 9 *
10 * Authors:
11 * Wu Fengguang <wfg@linux.intel.com>
12 *
13 * Maintained by:
14 * Wu Fengguang <wfg@linux.intel.com>
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the Free
18 * Software Foundation; either version 2 of the License, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful, but
22 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
23 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 * for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software Foundation,
28 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
84eb01be
TI		 31#include <linux/init.h>
32#include <linux/delay.h>
33#include <linux/slab.h>
65a77217 34#include <linux/module.h>
84eb01be 35#include <sound/core.h>
07acecc1 36#include <sound/jack.h>
433968da 37#include <sound/asoundef.h>
d45e6889 38#include <sound/tlv.h>
84eb01be
TI		 39#include "hda_codec.h"
40#include "hda_local.h"
1835a0f9 41#include "hda_jack.h"
84eb01be 42
0ebaa24c
TI		 43static bool static_hdmi_pcm;
44module_param(static_hdmi_pcm, bool, 0644);
45MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
46
fb87fa3a
ML		 47#define is_haswell(codec) ((codec)->vendor_id == 0x80862807)
48
384a48d7
SW		 49struct hdmi_spec_per_cvt {
50 hda_nid_t cvt_nid;
51 int assigned;
52 unsigned int channels_min;
53 unsigned int channels_max;
54 u32 rates;
55 u64 formats;
56 unsigned int maxbps;
57};
079d88cc 58
4eea3091
TI		 59/* max. connections to a widget */
60#define HDA_MAX_CONNECTIONS 32
61
384a48d7
SW		 62struct hdmi_spec_per_pin {
63 hda_nid_t pin_nid;
64 int num_mux_nids;
65 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
744626da
WF		 66
67 struct hda_codec *codec;
384a48d7 68 struct hdmi_eld sink_eld;
744626da 69 struct delayed_work work;
92c69e79 70 struct snd_kcontrol *eld_ctl;
c6e8453e 71 int repoll_count;
b054087d
TI		 72 bool setup; /* the stream has been set up by prepare callback */
73 int channels; /* current number of channels */
1a6003b5 74 bool non_pcm;
d45e6889
TI		 75 bool chmap_set; /* channel-map override by ALSA API? */
76 unsigned char chmap[8]; /* ALSA API channel-map */
bce0d2a8 77 char pcm_name[8]; /* filled in build_pcm callbacks */
384a48d7 78};
079d88cc 79
384a48d7
SW		 80struct hdmi_spec {
81 int num_cvts;
bce0d2a8
TI		 82 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
83 hda_nid_t cvt_nids[4]; /* only for haswell fix */
079d88cc 84
384a48d7 85 int num_pins;
bce0d2a8
TI		 86 struct snd_array pins; /* struct hdmi_spec_per_pin */
87 struct snd_array pcm_rec; /* struct hda_pcm */
d45e6889 88 unsigned int channels_max; /* max over all cvts */
079d88cc 89
4bd038f9 90 struct hdmi_eld temp_eld;
079d88cc 91 /*
384a48d7 92 * Non-generic ATI/NVIDIA specific
079d88cc
WF		 93 */
94 struct hda_multi_out multiout;
d0b1252d 95 struct hda_pcm_stream pcm_playback;
079d88cc
WF		 96};
97
98
99struct hdmi_audio_infoframe {
100 u8 type; /* 0x84 */
101 u8 ver; /* 0x01 */
102 u8 len; /* 0x0a */
103
53d7d69d
WF		 104 u8 checksum;
105
079d88cc
WF		 106 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
107 u8 SS01_SF24;
108 u8 CXT04;
109 u8 CA;
110 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 111};
112
113struct dp_audio_infoframe {
114 u8 type; /* 0x84 */
115 u8 len; /* 0x1b */
116 u8 ver; /* 0x11 << 2 */
117
118 u8 CC02_CT47; /* match with HDMI infoframe from this on */
119 u8 SS01_SF24;
120 u8 CXT04;
121 u8 CA;
122 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 123};
124
2b203dbb
TI		 125union audio_infoframe {
126 struct hdmi_audio_infoframe hdmi;
127 struct dp_audio_infoframe dp;
128 u8 bytes[0];
129};
130
079d88cc
WF		 131/*
132 * CEA speaker placement:
133 *
134 * FLH FCH FRH
135 * FLW FL FLC FC FRC FR FRW
136 *
137 * LFE
138 * TC
139 *
140 * RL RLC RC RRC RR
141 *
142 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
143 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
144 */
145enum cea_speaker_placement {
146 FL = (1 << 0), /* Front Left */
147 FC = (1 << 1), /* Front Center */
148 FR = (1 << 2), /* Front Right */
149 FLC = (1 << 3), /* Front Left Center */
150 FRC = (1 << 4), /* Front Right Center */
151 RL = (1 << 5), /* Rear Left */
152 RC = (1 << 6), /* Rear Center */
153 RR = (1 << 7), /* Rear Right */
154 RLC = (1 << 8), /* Rear Left Center */
155 RRC = (1 << 9), /* Rear Right Center */
156 LFE = (1 << 10), /* Low Frequency Effect */
157 FLW = (1 << 11), /* Front Left Wide */
158 FRW = (1 << 12), /* Front Right Wide */
159 FLH = (1 << 13), /* Front Left High */
160 FCH = (1 << 14), /* Front Center High */
161 FRH = (1 << 15), /* Front Right High */
162 TC = (1 << 16), /* Top Center */
163};
164
165/*
166 * ELD SA bits in the CEA Speaker Allocation data block
167 */
168static int eld_speaker_allocation_bits[] = {
169 [0] = FL | FR,
170 [1] = LFE,
171 [2] = FC,
172 [3] = RL | RR,
173 [4] = RC,
174 [5] = FLC | FRC,
175 [6] = RLC | RRC,
176 /* the following are not defined in ELD yet */
177 [7] = FLW | FRW,
178 [8] = FLH | FRH,
179 [9] = TC,
180 [10] = FCH,
181};
182
183struct cea_channel_speaker_allocation {
184 int ca_index;
185 int speakers[8];
186
187 /* derived values, just for convenience */
188 int channels;
189 int spk_mask;
190};
191
192/*
193 * ALSA sequence is:
194 *
195 * surround40 surround41 surround50 surround51 surround71
196 * ch0 front left = = = =
197 * ch1 front right = = = =
198 * ch2 rear left = = = =
199 * ch3 rear right = = = =
200 * ch4 LFE center center center
201 * ch5 LFE LFE
202 * ch6 side left
203 * ch7 side right
204 *
205 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
206 */
207static int hdmi_channel_mapping[0x32][8] = {
208 /* stereo */
209 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
210 /* 2.1 */
211 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
212 /* Dolby Surround */
213 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
214 /* surround40 */
215 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
216 /* 4ch */
217 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
218 /* surround41 */
9396d317 219 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
079d88cc
WF		 220 /* surround50 */
221 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
222 /* surround51 */
223 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
224 /* 7.1 */
225 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
226};
227
228/*
229 * This is an ordered list!
230 *
231 * The preceding ones have better chances to be selected by
53d7d69d 232 * hdmi_channel_allocation().
079d88cc
WF		 233 */
234static struct cea_channel_speaker_allocation channel_allocations[] = {
235/* channel: 7 6 5 4 3 2 1 0 */
236{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
237 /* 2.1 */
238{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
239 /* Dolby Surround */
240{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
241 /* surround40 */
242{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
243 /* surround41 */
244{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
245 /* surround50 */
246{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
247 /* surround51 */
248{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
249 /* 6.1 */
250{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
251 /* surround71 */
252{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
253
254{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
255{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
256{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
257{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
258{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
259{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
260{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
261{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
262{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
263{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
264{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
265{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
266{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
267{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
268{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
269{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
270{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
271{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
272{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
273{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
274{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
275{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
276{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
277{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
278{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
279{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
280{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
281{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
282{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
283{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
284{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
285{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
286{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
287{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
288{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
289{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
290{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
291{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
292{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
293{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
294{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
295};
296
297
298/*
299 * HDMI routines
300 */
301
bce0d2a8
TI		 302#define get_pin(spec, idx) \
303 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
304#define get_cvt(spec, idx) \
305 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
306#define get_pcm_rec(spec, idx) \
307 ((struct hda_pcm *)snd_array_elem(&spec->pcm_rec, idx))
308
384a48d7 309static int pin_nid_to_pin_index(struct hdmi_spec *spec, hda_nid_t pin_nid)
079d88cc 310{
384a48d7 311 int pin_idx;
079d88cc 312
384a48d7 313 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 314 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
384a48d7 315 return pin_idx;
079d88cc 316
384a48d7
SW		 317 snd_printk(KERN_WARNING "HDMI: pin nid %d not registered\n", pin_nid);
318 return -EINVAL;
319}
320
321static int hinfo_to_pin_index(struct hdmi_spec *spec,
322 struct hda_pcm_stream *hinfo)
323{
324 int pin_idx;
325
326 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 327 if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
384a48d7
SW		 328 return pin_idx;
329
330 snd_printk(KERN_WARNING "HDMI: hinfo %p not registered\n", hinfo);
331 return -EINVAL;
332}
333
334static int cvt_nid_to_cvt_index(struct hdmi_spec *spec, hda_nid_t cvt_nid)
335{
336 int cvt_idx;
337
338 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
bce0d2a8 339 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
384a48d7
SW		 340 return cvt_idx;
341
342 snd_printk(KERN_WARNING "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 343 return -EINVAL;
344}
345
14bc52b8
PLB		 346static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
347 struct snd_ctl_elem_info *uinfo)
348{
349 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9
DH		 350 struct hdmi_spec *spec = codec->spec;
351 struct hdmi_eld *eld;
14bc52b8
PLB		 352 int pin_idx;
353
14bc52b8
PLB		 354 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
355
356 pin_idx = kcontrol->private_value;
bce0d2a8 357 eld = &get_pin(spec, pin_idx)->sink_eld;
68e03de9 358
4bd038f9 359 mutex_lock(&eld->lock);
68e03de9 360 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
4bd038f9 361 mutex_unlock(&eld->lock);
14bc52b8
PLB		 362
363 return 0;
364}
365
366static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
367 struct snd_ctl_elem_value *ucontrol)
368{
369 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9
DH		 370 struct hdmi_spec *spec = codec->spec;
371 struct hdmi_eld *eld;
14bc52b8
PLB		 372 int pin_idx;
373
14bc52b8 374 pin_idx = kcontrol->private_value;
bce0d2a8 375 eld = &get_pin(spec, pin_idx)->sink_eld;
68e03de9 376
4bd038f9 377 mutex_lock(&eld->lock);
68e03de9 378 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) {
4bd038f9 379 mutex_unlock(&eld->lock);
68e03de9
DH		 380 snd_BUG();
381 return -EINVAL;
382 }
383
384 memset(ucontrol->value.bytes.data, 0,
385 ARRAY_SIZE(ucontrol->value.bytes.data));
386 if (eld->eld_valid)
387 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
388 eld->eld_size);
4bd038f9 389 mutex_unlock(&eld->lock);
14bc52b8
PLB		 390
391 return 0;
392}
393
394static struct snd_kcontrol_new eld_bytes_ctl = {
395 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
396 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
397 .name = "ELD",
398 .info = hdmi_eld_ctl_info,
399 .get = hdmi_eld_ctl_get,
400};
401
402static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
403 int device)
404{
405 struct snd_kcontrol *kctl;
406 struct hdmi_spec *spec = codec->spec;
407 int err;
408
409 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
410 if (!kctl)
411 return -ENOMEM;
412 kctl->private_value = pin_idx;
413 kctl->id.device = device;
414
bce0d2a8 415 err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
14bc52b8
PLB		 416 if (err < 0)
417 return err;
418
bce0d2a8 419 get_pin(spec, pin_idx)->eld_ctl = kctl;
14bc52b8
PLB		 420 return 0;
421}
422
079d88cc
WF		 423#ifdef BE_PARANOID
424static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
425 int *packet_index, int *byte_index)
426{
427 int val;
428
429 val = snd_hda_codec_read(codec, pin_nid, 0,
430 AC_VERB_GET_HDMI_DIP_INDEX, 0);
431
432 *packet_index = val >> 5;
433 *byte_index = val & 0x1f;
434}
435#endif
436
437static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
438 int packet_index, int byte_index)
439{
440 int val;
441
442 val = (packet_index << 5) | (byte_index & 0x1f);
443
444 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
445}
446
447static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
448 unsigned char val)
449{
450 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
451}
452
384a48d7 453static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc
WF		 454{
455 /* Unmute */
456 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
457 snd_hda_codec_write(codec, pin_nid, 0,
458 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
6169b673
TI		 459 /* Enable pin out: some machines with GM965 gets broken output when
460 * the pin is disabled or changed while using with HDMI
461 */
079d88cc 462 snd_hda_codec_write(codec, pin_nid, 0,
6169b673 463 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
079d88cc
WF		 464}
465
384a48d7 466static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc 467{
384a48d7 468 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
079d88cc
WF		 469 AC_VERB_GET_CVT_CHAN_COUNT, 0);
470}
471
472static void hdmi_set_channel_count(struct hda_codec *codec,
384a48d7 473 hda_nid_t cvt_nid, int chs)
079d88cc 474{
384a48d7
SW		 475 if (chs != hdmi_get_channel_count(codec, cvt_nid))
476 snd_hda_codec_write(codec, cvt_nid, 0,
079d88cc
WF		 477 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
478}
479
480
481/*
482 * Channel mapping routines
483 */
484
485/*
486 * Compute derived values in channel_allocations[].
487 */
488static void init_channel_allocations(void)
489{
490 int i, j;
491 struct cea_channel_speaker_allocation *p;
492
493 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
494 p = channel_allocations + i;
495 p->channels = 0;
496 p->spk_mask = 0;
497 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
498 if (p->speakers[j]) {
499 p->channels++;
500 p->spk_mask |= p->speakers[j];
501 }
502 }
503}
504
72357c78
WX		 505static int get_channel_allocation_order(int ca)
506{
507 int i;
508
509 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
510 if (channel_allocations[i].ca_index == ca)
511 break;
512 }
513 return i;
514}
515
079d88cc
WF		 516/*
517 * The transformation takes two steps:
518 *
519 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
520 * spk_mask => (channel_allocations[]) => ai->CA
521 *
522 * TODO: it could select the wrong CA from multiple candidates.
523*/
384a48d7 524static int hdmi_channel_allocation(struct hdmi_eld *eld, int channels)
079d88cc 525{
079d88cc 526 int i;
53d7d69d 527 int ca = 0;
079d88cc 528 int spk_mask = 0;
079d88cc
WF		 529 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
530
531 /*
532 * CA defaults to 0 for basic stereo audio
533 */
534 if (channels <= 2)
535 return 0;
536
079d88cc
WF		 537 /*
538 * expand ELD's speaker allocation mask
539 *
540 * ELD tells the speaker mask in a compact(paired) form,
541 * expand ELD's notions to match the ones used by Audio InfoFrame.
542 */
543 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
1613d6b4 544 if (eld->info.spk_alloc & (1 << i))
079d88cc
WF		 545 spk_mask |= eld_speaker_allocation_bits[i];
546 }
547
548 /* search for the first working match in the CA table */
549 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
550 if (channels == channel_allocations[i].channels &&
551 (spk_mask & channel_allocations[i].spk_mask) ==
552 channel_allocations[i].spk_mask) {
53d7d69d 553 ca = channel_allocations[i].ca_index;
079d88cc
WF		 554 break;
555 }
556 }
557
18e39186
AH		 558 if (!ca) {
559 /* if there was no match, select the regular ALSA channel
560 * allocation with the matching number of channels */
561 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
562 if (channels == channel_allocations[i].channels) {
563 ca = channel_allocations[i].ca_index;
564 break;
565 }
566 }
567 }
568
1613d6b4 569 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
2abbf439 570 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
53d7d69d 571 ca, channels, buf);
079d88cc 572
53d7d69d 573 return ca;
079d88cc
WF		 574}
575
576static void hdmi_debug_channel_mapping(struct hda_codec *codec,
577 hda_nid_t pin_nid)
578{
579#ifdef CONFIG_SND_DEBUG_VERBOSE
580 int i;
581 int slot;
582
583 for (i = 0; i < 8; i++) {
584 slot = snd_hda_codec_read(codec, pin_nid, 0,
585 AC_VERB_GET_HDMI_CHAN_SLOT, i);
586 printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n",
587 slot >> 4, slot & 0xf);
588 }
589#endif
590}
591
592
d45e6889 593static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
079d88cc 594 hda_nid_t pin_nid,
433968da 595 bool non_pcm,
53d7d69d 596 int ca)
079d88cc
WF		 597{
598 int i;
079d88cc 599 int err;
72357c78 600 int order;
433968da 601 int non_pcm_mapping[8];
079d88cc 602
72357c78 603 order = get_channel_allocation_order(ca);
433968da 604
079d88cc 605 if (hdmi_channel_mapping[ca][1] == 0) {
72357c78 606 for (i = 0; i < channel_allocations[order].channels; i++)
079d88cc
WF		 607 hdmi_channel_mapping[ca][i] = i | (i << 4);
608 for (; i < 8; i++)
609 hdmi_channel_mapping[ca][i] = 0xf | (i << 4);
610 }
611
433968da
WX		 612 if (non_pcm) {
613 for (i = 0; i < channel_allocations[order].channels; i++)
614 non_pcm_mapping[i] = i | (i << 4);
615 for (; i < 8; i++)
616 non_pcm_mapping[i] = 0xf | (i << 4);
617 }
618
079d88cc
WF		 619 for (i = 0; i < 8; i++) {
620 err = snd_hda_codec_write(codec, pin_nid, 0,
621 AC_VERB_SET_HDMI_CHAN_SLOT,
433968da 622 non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i]);
079d88cc 623 if (err) {
2abbf439
WF		 624 snd_printdd(KERN_NOTICE
625 "HDMI: channel mapping failed\n");
079d88cc
WF		 626 break;
627 }
628 }
629
630 hdmi_debug_channel_mapping(codec, pin_nid);
631}
632
d45e6889
TI		 633struct channel_map_table {
634 unsigned char map; /* ALSA API channel map position */
635 unsigned char cea_slot; /* CEA slot value */
636 int spk_mask; /* speaker position bit mask */
637};
638
639static struct channel_map_table map_tables[] = {
640 { SNDRV_CHMAP_FL, 0x00, FL },
641 { SNDRV_CHMAP_FR, 0x01, FR },
642 { SNDRV_CHMAP_RL, 0x04, RL },
643 { SNDRV_CHMAP_RR, 0x05, RR },
644 { SNDRV_CHMAP_LFE, 0x02, LFE },
645 { SNDRV_CHMAP_FC, 0x03, FC },
646 { SNDRV_CHMAP_RLC, 0x06, RLC },
647 { SNDRV_CHMAP_RRC, 0x07, RRC },
648 {} /* terminator */
649};
650
651/* from ALSA API channel position to speaker bit mask */
652static int to_spk_mask(unsigned char c)
653{
654 struct channel_map_table *t = map_tables;
655 for (; t->map; t++) {
656 if (t->map == c)
657 return t->spk_mask;
658 }
659 return 0;
660}
661
662/* from ALSA API channel position to CEA slot */
663static int to_cea_slot(unsigned char c)
664{
665 struct channel_map_table *t = map_tables;
666 for (; t->map; t++) {
667 if (t->map == c)
668 return t->cea_slot;
669 }
670 return 0x0f;
671}
672
673/* from CEA slot to ALSA API channel position */
674static int from_cea_slot(unsigned char c)
675{
676 struct channel_map_table *t = map_tables;
677 for (; t->map; t++) {
678 if (t->cea_slot == c)
679 return t->map;
680 }
681 return 0;
682}
683
684/* from speaker bit mask to ALSA API channel position */
685static int spk_to_chmap(int spk)
686{
687 struct channel_map_table *t = map_tables;
688 for (; t->map; t++) {
689 if (t->spk_mask == spk)
690 return t->map;
691 }
692 return 0;
693}
694
695/* get the CA index corresponding to the given ALSA API channel map */
696static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
697{
698 int i, spks = 0, spk_mask = 0;
699
700 for (i = 0; i < chs; i++) {
701 int mask = to_spk_mask(map[i]);
702 if (mask) {
703 spk_mask |= mask;
704 spks++;
705 }
706 }
707
708 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
709 if ((chs == channel_allocations[i].channels ||
710 spks == channel_allocations[i].channels) &&
711 (spk_mask & channel_allocations[i].spk_mask) ==
712 channel_allocations[i].spk_mask)
713 return channel_allocations[i].ca_index;
714 }
715 return -1;
716}
717
718/* set up the channel slots for the given ALSA API channel map */
719static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
720 hda_nid_t pin_nid,
721 int chs, unsigned char *map)
722{
723 int i;
724 for (i = 0; i < 8; i++) {
725 int val, err;
726 if (i < chs)
727 val = to_cea_slot(map[i]);
728 else
729 val = 0xf;
730 val |= (i << 4);
731 err = snd_hda_codec_write(codec, pin_nid, 0,
732 AC_VERB_SET_HDMI_CHAN_SLOT, val);
733 if (err)
734 return -EINVAL;
735 }
736 return 0;
737}
738
739/* store ALSA API channel map from the current default map */
740static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
741{
742 int i;
743 for (i = 0; i < 8; i++) {
744 if (i < channel_allocations[ca].channels)
745 map[i] = from_cea_slot((hdmi_channel_mapping[ca][i] >> 4) & 0x0f);
746 else
747 map[i] = 0;
748 }
749}
750
751static void hdmi_setup_channel_mapping(struct hda_codec *codec,
752 hda_nid_t pin_nid, bool non_pcm, int ca,
20608731
AH		 753 int channels, unsigned char *map,
754 bool chmap_set)
d45e6889 755{
20608731 756 if (!non_pcm && chmap_set) {
d45e6889
TI		 757 hdmi_manual_setup_channel_mapping(codec, pin_nid,
758 channels, map);
759 } else {
760 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
761 hdmi_setup_fake_chmap(map, ca);
762 }
763}
079d88cc
WF		 764
765/*
766 * Audio InfoFrame routines
767 */
768
769/*
770 * Enable Audio InfoFrame Transmission
771 */
772static void hdmi_start_infoframe_trans(struct hda_codec *codec,
773 hda_nid_t pin_nid)
774{
775 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
776 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
777 AC_DIPXMIT_BEST);
778}
779
780/*
781 * Disable Audio InfoFrame Transmission
782 */
783static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
784 hda_nid_t pin_nid)
785{
786 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
787 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
788 AC_DIPXMIT_DISABLE);
789}
790
791static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
792{
793#ifdef CONFIG_SND_DEBUG_VERBOSE
794 int i;
795 int size;
796
797 size = snd_hdmi_get_eld_size(codec, pin_nid);
798 printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size);
799
800 for (i = 0; i < 8; i++) {
801 size = snd_hda_codec_read(codec, pin_nid, 0,
802 AC_VERB_GET_HDMI_DIP_SIZE, i);
803 printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size);
804 }
805#endif
806}
807
808static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
809{
810#ifdef BE_PARANOID
811 int i, j;
812 int size;
813 int pi, bi;
814 for (i = 0; i < 8; i++) {
815 size = snd_hda_codec_read(codec, pin_nid, 0,
816 AC_VERB_GET_HDMI_DIP_SIZE, i);
817 if (size == 0)
818 continue;
819
820 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
821 for (j = 1; j < 1000; j++) {
822 hdmi_write_dip_byte(codec, pin_nid, 0x0);
823 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
824 if (pi != i)
825 snd_printd(KERN_INFO "dip index %d: %d != %d\n",
826 bi, pi, i);
827 if (bi == 0) /* byte index wrapped around */
828 break;
829 }
830 snd_printd(KERN_INFO
831 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
832 i, size, j);
833 }
834#endif
835}
836
53d7d69d 837static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 838{
53d7d69d 839 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 840 u8 sum = 0;
841 int i;
842
53d7d69d 843 hdmi_ai->checksum = 0;
079d88cc 844
53d7d69d 845 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 846 sum += bytes[i];
847
53d7d69d 848 hdmi_ai->checksum = -sum;
079d88cc
WF		 849}
850
851static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
852 hda_nid_t pin_nid,
53d7d69d 853 u8 *dip, int size)
079d88cc 854{
079d88cc
WF		 855 int i;
856
857 hdmi_debug_dip_size(codec, pin_nid);
858 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
859
079d88cc 860 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 861 for (i = 0; i < size; i++)
862 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 863}
864
865static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 866 u8 *dip, int size)
079d88cc 867{
079d88cc
WF		 868 u8 val;
869 int i;
870
871 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
872 != AC_DIPXMIT_BEST)
873 return false;
874
875 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 876 for (i = 0; i < size; i++) {
079d88cc
WF		 877 val = snd_hda_codec_read(codec, pin_nid, 0,
878 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 879 if (val != dip[i])
079d88cc
WF		 880 return false;
881 }
882
883 return true;
884}
885
b054087d
TI		 886static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
887 struct hdmi_spec_per_pin *per_pin,
888 bool non_pcm)
079d88cc 889{
384a48d7 890 hda_nid_t pin_nid = per_pin->pin_nid;
b054087d 891 int channels = per_pin->channels;
384a48d7 892 struct hdmi_eld *eld;
53d7d69d 893 int ca;
2b203dbb 894 union audio_infoframe ai;
079d88cc 895
b054087d
TI		 896 if (!channels)
897 return;
898
58f7d28d
ML		 899 if (is_haswell(codec))
900 snd_hda_codec_write(codec, pin_nid, 0,
901 AC_VERB_SET_AMP_GAIN_MUTE,
902 AMP_OUT_UNMUTE);
903
bce0d2a8 904 eld = &per_pin->sink_eld;
384a48d7
SW		 905 if (!eld->monitor_present)
906 return;
079d88cc 907
d45e6889
TI		 908 if (!non_pcm && per_pin->chmap_set)
909 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
910 else
911 ca = hdmi_channel_allocation(eld, channels);
912 if (ca < 0)
913 ca = 0;
384a48d7
SW		 914
915 memset(&ai, 0, sizeof(ai));
1613d6b4 916 if (eld->info.conn_type == 0) { /* HDMI */
384a48d7
SW		 917 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
918
919 hdmi_ai->type = 0x84;
920 hdmi_ai->ver = 0x01;
921 hdmi_ai->len = 0x0a;
922 hdmi_ai->CC02_CT47 = channels - 1;
923 hdmi_ai->CA = ca;
924 hdmi_checksum_audio_infoframe(hdmi_ai);
1613d6b4 925 } else if (eld->info.conn_type == 1) { /* DisplayPort */
384a48d7
SW		 926 struct dp_audio_infoframe *dp_ai = &ai.dp;
927
928 dp_ai->type = 0x84;
929 dp_ai->len = 0x1b;
930 dp_ai->ver = 0x11 << 2;
931 dp_ai->CC02_CT47 = channels - 1;
932 dp_ai->CA = ca;
933 } else {
934 snd_printd("HDMI: unknown connection type at pin %d\n",
935 pin_nid);
936 return;
937 }
53d7d69d 938
39edac70
AH		 939 /*
940 * always configure channel mapping, it may have been changed by the
941 * user in the meantime
942 */
943 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
944 channels, per_pin->chmap,
945 per_pin->chmap_set);
946
384a48d7
SW		 947 /*
948 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
949 * sizeof(*dp_ai) to avoid partial match/update problems when
950 * the user switches between HDMI/DP monitors.
951 */
952 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
953 sizeof(ai))) {
954 snd_printdd("hdmi_setup_audio_infoframe: "
955 "pin=%d channels=%d\n",
956 pin_nid,
957 channels);
384a48d7
SW		 958 hdmi_stop_infoframe_trans(codec, pin_nid);
959 hdmi_fill_audio_infoframe(codec, pin_nid,
960 ai.bytes, sizeof(ai));
961 hdmi_start_infoframe_trans(codec, pin_nid);
079d88cc 962 }
433968da 963
1a6003b5 964 per_pin->non_pcm = non_pcm;
079d88cc
WF		 965}
966
967
968/*
969 * Unsolicited events
970 */
971
c6e8453e 972static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
38faddb1 973
079d88cc
WF		 974static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
975{
976 struct hdmi_spec *spec = codec->spec;
3a93897e
TI		 977 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
978 int pin_nid;
384a48d7 979 int pin_idx;
3a93897e 980 struct hda_jack_tbl *jack;
2e59e5ab 981 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
3a93897e
TI		 982
983 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
984 if (!jack)
985 return;
986 pin_nid = jack->nid;
987 jack->jack_dirty = 1;
079d88cc 988
fae3d88a 989 _snd_printd(SND_PR_VERBOSE,
2e59e5ab
ML		 990 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
991 codec->addr, pin_nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
fae3d88a 992 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
079d88cc 993
384a48d7
SW		 994 pin_idx = pin_nid_to_pin_index(spec, pin_nid);
995 if (pin_idx < 0)
079d88cc
WF		 996 return;
997
bce0d2a8 998 hdmi_present_sense(get_pin(spec, pin_idx), 1);
01a61e12 999 snd_hda_jack_report_sync(codec);
079d88cc
WF		 1000}
1001
1002static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
1003{
1004 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1005 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1006 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
1007 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
1008
1009 printk(KERN_INFO
e9ea8e8f 1010 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
384a48d7 1011 codec->addr,
079d88cc
WF		 1012 tag,
1013 subtag,
1014 cp_state,
1015 cp_ready);
1016
1017 /* TODO */
1018 if (cp_state)
1019 ;
1020 if (cp_ready)
1021 ;
1022}
1023
1024
1025static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1026{
079d88cc
WF		 1027 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1028 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1029
3a93897e 1030 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
079d88cc
WF		 1031 snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag);
1032 return;
1033 }
1034
1035 if (subtag == 0)
1036 hdmi_intrinsic_event(codec, res);
1037 else
1038 hdmi_non_intrinsic_event(codec, res);
1039}
1040
58f7d28d 1041static void haswell_verify_D0(struct hda_codec *codec,
53b434f0 1042 hda_nid_t cvt_nid, hda_nid_t nid)
83f26ad2 1043{
58f7d28d 1044 int pwr;
83f26ad2 1045
53b434f0
WX		 1046 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1047 * thus pins could only choose converter 0 for use. Make sure the
1048 * converters are in correct power state */
fd678cac 1049 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
53b434f0
WX		 1050 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1051
fd678cac 1052 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
83f26ad2
DH		 1053 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1054 AC_PWRST_D0);
1055 msleep(40);
1056 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1057 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
1058 snd_printd("Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
1059 }
83f26ad2
DH		 1060}
1061
079d88cc
WF		 1062/*
1063 * Callbacks
1064 */
1065
92f10b3f
TI		 1066/* HBR should be Non-PCM, 8 channels */
1067#define is_hbr_format(format) \
1068 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1069
384a48d7
SW		 1070static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1071 hda_nid_t pin_nid, u32 stream_tag, int format)
079d88cc 1072{
ea87d1c4
AH		 1073 int pinctl;
1074 int new_pinctl = 0;
ea87d1c4 1075
fb87fa3a 1076 if (is_haswell(codec))
58f7d28d 1077 haswell_verify_D0(codec, cvt_nid, pin_nid);
83f26ad2 1078
384a48d7
SW		 1079 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1080 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 1081 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1082
1083 new_pinctl = pinctl & ~AC_PINCTL_EPT;
92f10b3f 1084 if (is_hbr_format(format))
ea87d1c4
AH		 1085 new_pinctl |= AC_PINCTL_EPT_HBR;
1086 else
1087 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1088
1089 snd_printdd("hdmi_setup_stream: "
1090 "NID=0x%x, %spinctl=0x%x\n",
384a48d7 1091 pin_nid,
ea87d1c4
AH		 1092 pinctl == new_pinctl ? "" : "new-",
1093 new_pinctl);
1094
1095 if (pinctl != new_pinctl)
384a48d7 1096 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 1097 AC_VERB_SET_PIN_WIDGET_CONTROL,
1098 new_pinctl);
ea87d1c4 1099
384a48d7 1100 }
92f10b3f 1101 if (is_hbr_format(format) && !new_pinctl) {
ea87d1c4
AH		 1102 snd_printdd("hdmi_setup_stream: HBR is not supported\n");
1103 return -EINVAL;
1104 }
079d88cc 1105
384a48d7 1106 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 1107 return 0;
079d88cc
WF		 1108}
1109
7ef166b8
WX		 1110static int hdmi_choose_cvt(struct hda_codec *codec,
1111 int pin_idx, int *cvt_id, int *mux_id)
bbbe3390
TI		 1112{
1113 struct hdmi_spec *spec = codec->spec;
384a48d7 1114 struct hdmi_spec_per_pin *per_pin;
384a48d7 1115 struct hdmi_spec_per_cvt *per_cvt = NULL;
7ef166b8 1116 int cvt_idx, mux_idx = 0;
bbbe3390 1117
bce0d2a8 1118 per_pin = get_pin(spec, pin_idx);
384a48d7
SW		 1119
1120 /* Dynamically assign converter to stream */
1121 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
bce0d2a8 1122 per_cvt = get_cvt(spec, cvt_idx);
bbbe3390 1123
384a48d7
SW		 1124 /* Must not already be assigned */
1125 if (per_cvt->assigned)
1126 continue;
1127 /* Must be in pin's mux's list of converters */
1128 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1129 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1130 break;
1131 /* Not in mux list */
1132 if (mux_idx == per_pin->num_mux_nids)
1133 continue;
1134 break;
1135 }
7ef166b8 1136
384a48d7
SW		 1137 /* No free converters */
1138 if (cvt_idx == spec->num_cvts)
1139 return -ENODEV;
1140
7ef166b8
WX		 1141 if (cvt_id)
1142 *cvt_id = cvt_idx;
1143 if (mux_id)
1144 *mux_id = mux_idx;
1145
1146 return 0;
1147}
1148
1149static void haswell_config_cvts(struct hda_codec *codec,
f82d7d16 1150 hda_nid_t pin_nid, int mux_idx)
7ef166b8
WX		 1151{
1152 struct hdmi_spec *spec = codec->spec;
f82d7d16
ML		 1153 hda_nid_t nid, end_nid;
1154 int cvt_idx, curr;
1155 struct hdmi_spec_per_cvt *per_cvt;
7ef166b8 1156
f82d7d16
ML		 1157 /* configure all pins, including "no physical connection" ones */
1158 end_nid = codec->start_nid + codec->num_nodes;
1159 for (nid = codec->start_nid; nid < end_nid; nid++) {
1160 unsigned int wid_caps = get_wcaps(codec, nid);
1161 unsigned int wid_type = get_wcaps_type(wid_caps);
1162
1163 if (wid_type != AC_WID_PIN)
1164 continue;
7ef166b8 1165
f82d7d16 1166 if (nid == pin_nid)
7ef166b8
WX		 1167 continue;
1168
f82d7d16 1169 curr = snd_hda_codec_read(codec, nid, 0,
7ef166b8 1170 AC_VERB_GET_CONNECT_SEL, 0);
f82d7d16
ML		 1171 if (curr != mux_idx)
1172 continue;
7ef166b8 1173
f82d7d16
ML		 1174 /* choose an unassigned converter. The conveters in the
1175 * connection list are in the same order as in the codec.
1176 */
1177 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1178 per_cvt = get_cvt(spec, cvt_idx);
1179 if (!per_cvt->assigned) {
1180 snd_printdd("choose cvt %d for pin nid %d\n",
1181 cvt_idx, nid);
1182 snd_hda_codec_write_cache(codec, nid, 0,
7ef166b8 1183 AC_VERB_SET_CONNECT_SEL,
f82d7d16
ML		 1184 cvt_idx);
1185 break;
1186 }
7ef166b8
WX		 1187 }
1188 }
1189}
1190
1191/*
1192 * HDA PCM callbacks
1193 */
1194static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1195 struct hda_codec *codec,
1196 struct snd_pcm_substream *substream)
1197{
1198 struct hdmi_spec *spec = codec->spec;
1199 struct snd_pcm_runtime *runtime = substream->runtime;
1200 int pin_idx, cvt_idx, mux_idx = 0;
1201 struct hdmi_spec_per_pin *per_pin;
1202 struct hdmi_eld *eld;
1203 struct hdmi_spec_per_cvt *per_cvt = NULL;
1204 int err;
1205
1206 /* Validate hinfo */
1207 pin_idx = hinfo_to_pin_index(spec, hinfo);
1208 if (snd_BUG_ON(pin_idx < 0))
1209 return -EINVAL;
1210 per_pin = get_pin(spec, pin_idx);
1211 eld = &per_pin->sink_eld;
1212
1213 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1214 if (err < 0)
1215 return err;
1216
1217 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1218 /* Claim converter */
1219 per_cvt->assigned = 1;
1220 hinfo->nid = per_cvt->cvt_nid;
1221
bddee96b 1222 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
384a48d7
SW		 1223 AC_VERB_SET_CONNECT_SEL,
1224 mux_idx);
7ef166b8
WX		 1225
1226 /* configure unused pins to choose other converters */
fb87fa3a 1227 if (is_haswell(codec))
f82d7d16 1228 haswell_config_cvts(codec, per_pin->pin_nid, mux_idx);
7ef166b8 1229
384a48d7 1230 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
bbbe3390 1231
2def8172 1232 /* Initially set the converter's capabilities */
384a48d7
SW		 1233 hinfo->channels_min = per_cvt->channels_min;
1234 hinfo->channels_max = per_cvt->channels_max;
1235 hinfo->rates = per_cvt->rates;
1236 hinfo->formats = per_cvt->formats;
1237 hinfo->maxbps = per_cvt->maxbps;
2def8172 1238
384a48d7 1239 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 1240 if (!static_hdmi_pcm && eld->eld_valid) {
1613d6b4 1241 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
bbbe3390 1242 if (hinfo->channels_min > hinfo->channels_max ||
2ad779b7
TI		 1243 !hinfo->rates || !hinfo->formats) {
1244 per_cvt->assigned = 0;
1245 hinfo->nid = 0;
1246 snd_hda_spdif_ctls_unassign(codec, pin_idx);
bbbe3390 1247 return -ENODEV;
2ad779b7 1248 }
bbbe3390 1249 }
2def8172
SW		 1250
1251 /* Store the updated parameters */
639cef0e
TI		 1252 runtime->hw.channels_min = hinfo->channels_min;
1253 runtime->hw.channels_max = hinfo->channels_max;
1254 runtime->hw.formats = hinfo->formats;
1255 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 1256
1257 snd_pcm_hw_constraint_step(substream->runtime, 0,
1258 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
bbbe3390
TI		 1259 return 0;
1260}
1261
079d88cc
WF		 1262/*
1263 * HDA/HDMI auto parsing
1264 */
384a48d7 1265static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 1266{
1267 struct hdmi_spec *spec = codec->spec;
bce0d2a8 1268 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1269 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 1270
1271 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1272 snd_printk(KERN_WARNING
1273 "HDMI: pin %d wcaps %#x "
1274 "does not support connection list\n",
1275 pin_nid, get_wcaps(codec, pin_nid));
1276 return -EINVAL;
1277 }
1278
384a48d7
SW		 1279 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1280 per_pin->mux_nids,
1281 HDA_MAX_CONNECTIONS);
079d88cc
WF		 1282
1283 return 0;
1284}
1285
c6e8453e 1286static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
079d88cc 1287{
744626da 1288 struct hda_codec *codec = per_pin->codec;
4bd038f9
DH		 1289 struct hdmi_spec *spec = codec->spec;
1290 struct hdmi_eld *eld = &spec->temp_eld;
1291 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
744626da 1292 hda_nid_t pin_nid = per_pin->pin_nid;
5d44f927
SW		 1293 /*
1294 * Always execute a GetPinSense verb here, even when called from
1295 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1296 * response's PD bit is not the real PD value, but indicates that
1297 * the real PD value changed. An older version of the HD-audio
1298 * specification worked this way. Hence, we just ignore the data in
1299 * the unsolicited response to avoid custom WARs.
1300 */
079d88cc 1301 int present = snd_hda_pin_sense(codec, pin_nid);
4bd038f9
DH		 1302 bool update_eld = false;
1303 bool eld_changed = false;
079d88cc 1304
4bd038f9
DH		 1305 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1306 if (pin_eld->monitor_present)
1307 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1308 else
1309 eld->eld_valid = false;
079d88cc 1310
fae3d88a 1311 _snd_printd(SND_PR_VERBOSE,
384a48d7 1312 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
10250911 1313 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
5d44f927 1314
4bd038f9 1315 if (eld->eld_valid) {
1613d6b4
DH		 1316 if (snd_hdmi_get_eld(codec, pin_nid, eld->eld_buffer,
1317 &eld->eld_size) < 0)
4bd038f9 1318 eld->eld_valid = false;
1613d6b4
DH		 1319 else {
1320 memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
1321 if (snd_hdmi_parse_eld(&eld->info, eld->eld_buffer,
1322 eld->eld_size) < 0)
4bd038f9 1323 eld->eld_valid = false;
1613d6b4
DH		 1324 }
1325
4bd038f9 1326 if (eld->eld_valid) {
1613d6b4 1327 snd_hdmi_show_eld(&eld->info);
4bd038f9 1328 update_eld = true;
1613d6b4 1329 }
c6e8453e 1330 else if (repoll) {
744626da
WF		 1331 queue_delayed_work(codec->bus->workq,
1332 &per_pin->work,
1333 msecs_to_jiffies(300));
4bd038f9 1334 return;
744626da
WF		 1335 }
1336 }
4bd038f9
DH		 1337
1338 mutex_lock(&pin_eld->lock);
92c69e79 1339 if (pin_eld->eld_valid && !eld->eld_valid) {
4bd038f9 1340 update_eld = true;
92c69e79
DH		 1341 eld_changed = true;
1342 }
4bd038f9 1343 if (update_eld) {
b054087d 1344 bool old_eld_valid = pin_eld->eld_valid;
4bd038f9 1345 pin_eld->eld_valid = eld->eld_valid;
92c69e79
DH		 1346 eld_changed = pin_eld->eld_size != eld->eld_size ||
1347 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
4bd038f9
DH		 1348 eld->eld_size) != 0;
1349 if (eld_changed)
1350 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1351 eld->eld_size);
1352 pin_eld->eld_size = eld->eld_size;
1353 pin_eld->info = eld->info;
b054087d
TI		 1354
1355 /* Haswell-specific workaround: re-setup when the transcoder is
1356 * changed during the stream playback
1357 */
fb87fa3a 1358 if (is_haswell(codec) &&
58f7d28d 1359 eld->eld_valid && !old_eld_valid && per_pin->setup)
b054087d
TI		 1360 hdmi_setup_audio_infoframe(codec, per_pin,
1361 per_pin->non_pcm);
4bd038f9
DH		 1362 }
1363 mutex_unlock(&pin_eld->lock);
92c69e79
DH		 1364
1365 if (eld_changed)
1366 snd_ctl_notify(codec->bus->card,
1367 SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO,
1368 &per_pin->eld_ctl->id);
079d88cc
WF		 1369}
1370
744626da
WF		 1371static void hdmi_repoll_eld(struct work_struct *work)
1372{
1373 struct hdmi_spec_per_pin *per_pin =
1374 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1375
c6e8453e
WF		 1376 if (per_pin->repoll_count++ > 6)
1377 per_pin->repoll_count = 0;
1378
1379 hdmi_present_sense(per_pin, per_pin->repoll_count);
744626da
WF		 1380}
1381
c88d4e84
TI		 1382static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1383 hda_nid_t nid);
1384
079d88cc
WF		 1385static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1386{
1387 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1388 unsigned int caps, config;
1389 int pin_idx;
1390 struct hdmi_spec_per_pin *per_pin;
07acecc1 1391 int err;
079d88cc 1392
efc2f8de 1393 caps = snd_hda_query_pin_caps(codec, pin_nid);
384a48d7
SW		 1394 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1395 return 0;
1396
efc2f8de 1397 config = snd_hda_codec_get_pincfg(codec, pin_nid);
384a48d7
SW		 1398 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1399 return 0;
1400
fb87fa3a 1401 if (is_haswell(codec))
c88d4e84
TI		 1402 intel_haswell_fixup_connect_list(codec, pin_nid);
1403
384a48d7 1404 pin_idx = spec->num_pins;
bce0d2a8
TI		 1405 per_pin = snd_array_new(&spec->pins);
1406 if (!per_pin)
1407 return -ENOMEM;
384a48d7
SW		 1408
1409 per_pin->pin_nid = pin_nid;
1a6003b5 1410 per_pin->non_pcm = false;
079d88cc 1411
384a48d7
SW		 1412 err = hdmi_read_pin_conn(codec, pin_idx);
1413 if (err < 0)
1414 return err;
079d88cc 1415
079d88cc
WF		 1416 spec->num_pins++;
1417
384a48d7 1418 return 0;
079d88cc
WF		 1419}
1420
384a48d7 1421static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 1422{
1423 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1424 struct hdmi_spec_per_cvt *per_cvt;
1425 unsigned int chans;
1426 int err;
079d88cc 1427
384a48d7
SW		 1428 chans = get_wcaps(codec, cvt_nid);
1429 chans = get_wcaps_channels(chans);
1430
bce0d2a8
TI		 1431 per_cvt = snd_array_new(&spec->cvts);
1432 if (!per_cvt)
1433 return -ENOMEM;
384a48d7
SW		 1434
1435 per_cvt->cvt_nid = cvt_nid;
1436 per_cvt->channels_min = 2;
d45e6889 1437 if (chans <= 16) {
384a48d7 1438 per_cvt->channels_max = chans;
d45e6889
TI		 1439 if (chans > spec->channels_max)
1440 spec->channels_max = chans;
1441 }
384a48d7
SW		 1442
1443 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1444 &per_cvt->rates,
1445 &per_cvt->formats,
1446 &per_cvt->maxbps);
1447 if (err < 0)
1448 return err;
1449
bce0d2a8
TI		 1450 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1451 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1452 spec->num_cvts++;
079d88cc
WF		 1453
1454 return 0;
1455}
1456
1457static int hdmi_parse_codec(struct hda_codec *codec)
1458{
1459 hda_nid_t nid;
1460 int i, nodes;
1461
1462 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
1463 if (!nid || nodes < 0) {
1464 snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n");
1465 return -EINVAL;
1466 }
1467
1468 for (i = 0; i < nodes; i++, nid++) {
1469 unsigned int caps;
1470 unsigned int type;
1471
efc2f8de 1472 caps = get_wcaps(codec, nid);
079d88cc
WF		 1473 type = get_wcaps_type(caps);
1474
1475 if (!(caps & AC_WCAP_DIGITAL))
1476 continue;
1477
1478 switch (type) {
1479 case AC_WID_AUD_OUT:
384a48d7 1480 hdmi_add_cvt(codec, nid);
079d88cc
WF		 1481 break;
1482 case AC_WID_PIN:
3eaead57 1483 hdmi_add_pin(codec, nid);
079d88cc
WF		 1484 break;
1485 }
1486 }
1487
c9adeefd
DH		 1488#ifdef CONFIG_PM
1489 /* We're seeing some problems with unsolicited hot plug events on
1490 * PantherPoint after S3, if this is not enabled */
1491 if (codec->vendor_id == 0x80862806)
1492 codec->bus->power_keep_link_on = 1;
079d88cc
WF		 1493 /*
1494 * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event
1495 * can be lost and presence sense verb will become inaccurate if the
1496 * HDA link is powered off at hot plug or hw initialization time.
1497 */
c9adeefd 1498 else if (!(snd_hda_param_read(codec, codec->afg, AC_PAR_POWER_STATE) &
079d88cc
WF		 1499 AC_PWRST_EPSS))
1500 codec->bus->power_keep_link_on = 1;
1501#endif
1502
1503 return 0;
1504}
1505
84eb01be
TI		 1506/*
1507 */
1a6003b5
TI		 1508static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1509{
1510 struct hda_spdif_out *spdif;
1511 bool non_pcm;
1512
1513 mutex_lock(&codec->spdif_mutex);
1514 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1515 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1516 mutex_unlock(&codec->spdif_mutex);
1517 return non_pcm;
1518}
1519
1520
84eb01be
TI		 1521/*
1522 * HDMI callbacks
1523 */
1524
1525static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1526 struct hda_codec *codec,
1527 unsigned int stream_tag,
1528 unsigned int format,
1529 struct snd_pcm_substream *substream)
1530{
384a48d7
SW		 1531 hda_nid_t cvt_nid = hinfo->nid;
1532 struct hdmi_spec *spec = codec->spec;
1533 int pin_idx = hinfo_to_pin_index(spec, hinfo);
b054087d
TI		 1534 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1535 hda_nid_t pin_nid = per_pin->pin_nid;
1a6003b5
TI		 1536 bool non_pcm;
1537
1538 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
b054087d
TI		 1539 per_pin->channels = substream->runtime->channels;
1540 per_pin->setup = true;
384a48d7
SW		 1541
1542 hdmi_set_channel_count(codec, cvt_nid, substream->runtime->channels);
84eb01be 1543
b054087d 1544 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
84eb01be 1545
384a48d7 1546 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
84eb01be
TI		 1547}
1548
8dfaa573
TI		 1549static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1550 struct hda_codec *codec,
1551 struct snd_pcm_substream *substream)
1552{
1553 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1554 return 0;
1555}
1556
f2ad24fa
TI		 1557static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1558 struct hda_codec *codec,
1559 struct snd_pcm_substream *substream)
384a48d7
SW		 1560{
1561 struct hdmi_spec *spec = codec->spec;
1562 int cvt_idx, pin_idx;
1563 struct hdmi_spec_per_cvt *per_cvt;
1564 struct hdmi_spec_per_pin *per_pin;
384a48d7 1565
384a48d7
SW		 1566 if (hinfo->nid) {
1567 cvt_idx = cvt_nid_to_cvt_index(spec, hinfo->nid);
1568 if (snd_BUG_ON(cvt_idx < 0))
1569 return -EINVAL;
bce0d2a8 1570 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1571
1572 snd_BUG_ON(!per_cvt->assigned);
1573 per_cvt->assigned = 0;
1574 hinfo->nid = 0;
1575
1576 pin_idx = hinfo_to_pin_index(spec, hinfo);
1577 if (snd_BUG_ON(pin_idx < 0))
1578 return -EINVAL;
bce0d2a8 1579 per_pin = get_pin(spec, pin_idx);
384a48d7 1580
384a48d7 1581 snd_hda_spdif_ctls_unassign(codec, pin_idx);
d45e6889
TI		 1582 per_pin->chmap_set = false;
1583 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
b054087d
TI		 1584
1585 per_pin->setup = false;
1586 per_pin->channels = 0;
384a48d7 1587 }
d45e6889 1588
384a48d7
SW		 1589 return 0;
1590}
1591
1592static const struct hda_pcm_ops generic_ops = {
1593 .open = hdmi_pcm_open,
f2ad24fa 1594 .close = hdmi_pcm_close,
384a48d7 1595 .prepare = generic_hdmi_playback_pcm_prepare,
8dfaa573 1596 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 1597};
1598
d45e6889
TI		 1599/*
1600 * ALSA API channel-map control callbacks
1601 */
1602static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1603 struct snd_ctl_elem_info *uinfo)
1604{
1605 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1606 struct hda_codec *codec = info->private_data;
1607 struct hdmi_spec *spec = codec->spec;
1608 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1609 uinfo->count = spec->channels_max;
1610 uinfo->value.integer.min = 0;
1611 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1612 return 0;
1613}
1614
1615static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
1616 unsigned int size, unsigned int __user *tlv)
1617{
1618 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1619 struct hda_codec *codec = info->private_data;
1620 struct hdmi_spec *spec = codec->spec;
1621 const unsigned int valid_mask =
1622 FL | FR | RL | RR | LFE | FC | RLC | RRC;
1623 unsigned int __user *dst;
1624 int chs, count = 0;
1625
1626 if (size < 8)
1627 return -ENOMEM;
1628 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
1629 return -EFAULT;
1630 size -= 8;
1631 dst = tlv + 2;
498dab3a 1632 for (chs = 2; chs <= spec->channels_max; chs++) {
d45e6889
TI		 1633 int i, c;
1634 struct cea_channel_speaker_allocation *cap;
1635 cap = channel_allocations;
1636 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
1637 int chs_bytes = chs * 4;
1638 if (cap->channels != chs)
1639 continue;
1640 if (cap->spk_mask & ~valid_mask)
1641 continue;
1642 if (size < 8)
1643 return -ENOMEM;
1644 if (put_user(SNDRV_CTL_TLVT_CHMAP_VAR, dst) ||
1645 put_user(chs_bytes, dst + 1))
1646 return -EFAULT;
1647 dst += 2;
1648 size -= 8;
1649 count += 8;
1650 if (size < chs_bytes)
1651 return -ENOMEM;
1652 size -= chs_bytes;
1653 count += chs_bytes;
1654 for (c = 7; c >= 0; c--) {
1655 int spk = cap->speakers[c];
1656 if (!spk)
1657 continue;
1658 if (put_user(spk_to_chmap(spk), dst))
1659 return -EFAULT;
1660 dst++;
1661 }
1662 }
1663 }
1664 if (put_user(count, tlv + 1))
1665 return -EFAULT;
1666 return 0;
1667}
1668
1669static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
1670 struct snd_ctl_elem_value *ucontrol)
1671{
1672 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1673 struct hda_codec *codec = info->private_data;
1674 struct hdmi_spec *spec = codec->spec;
1675 int pin_idx = kcontrol->private_value;
bce0d2a8 1676 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 1677 int i;
1678
1679 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
1680 ucontrol->value.integer.value[i] = per_pin->chmap[i];
1681 return 0;
1682}
1683
1684static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
1685 struct snd_ctl_elem_value *ucontrol)
1686{
1687 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1688 struct hda_codec *codec = info->private_data;
1689 struct hdmi_spec *spec = codec->spec;
1690 int pin_idx = kcontrol->private_value;
bce0d2a8 1691 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 1692 unsigned int ctl_idx;
1693 struct snd_pcm_substream *substream;
1694 unsigned char chmap[8];
1695 int i, ca, prepared = 0;
1696
1697 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
1698 substream = snd_pcm_chmap_substream(info, ctl_idx);
1699 if (!substream || !substream->runtime)
6f54c361 1700 return 0; /* just for avoiding error from alsactl restore */
d45e6889
TI		 1701 switch (substream->runtime->status->state) {
1702 case SNDRV_PCM_STATE_OPEN:
1703 case SNDRV_PCM_STATE_SETUP:
1704 break;
1705 case SNDRV_PCM_STATE_PREPARED:
1706 prepared = 1;
1707 break;
1708 default:
1709 return -EBUSY;
1710 }
1711 memset(chmap, 0, sizeof(chmap));
1712 for (i = 0; i < ARRAY_SIZE(chmap); i++)
1713 chmap[i] = ucontrol->value.integer.value[i];
1714 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
1715 return 0;
1716 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
1717 if (ca < 0)
1718 return -EINVAL;
1719 per_pin->chmap_set = true;
1720 memcpy(per_pin->chmap, chmap, sizeof(chmap));
1721 if (prepared)
b054087d 1722 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
d45e6889
TI		 1723
1724 return 0;
1725}
1726
84eb01be
TI		 1727static int generic_hdmi_build_pcms(struct hda_codec *codec)
1728{
1729 struct hdmi_spec *spec = codec->spec;
384a48d7 1730 int pin_idx;
84eb01be 1731
384a48d7
SW		 1732 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1733 struct hda_pcm *info;
84eb01be 1734 struct hda_pcm_stream *pstr;
bce0d2a8
TI		 1735 struct hdmi_spec_per_pin *per_pin;
1736
1737 per_pin = get_pin(spec, pin_idx);
1738 sprintf(per_pin->pcm_name, "HDMI %d", pin_idx);
1739 info = snd_array_new(&spec->pcm_rec);
1740 if (!info)
1741 return -ENOMEM;
1742 info->name = per_pin->pcm_name;
84eb01be 1743 info->pcm_type = HDA_PCM_TYPE_HDMI;
d45e6889 1744 info->own_chmap = true;
384a48d7 1745
84eb01be 1746 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 1747 pstr->substreams = 1;
1748 pstr->ops = generic_ops;
1749 /* other pstr fields are set in open */
84eb01be
TI		 1750 }
1751
384a48d7 1752 codec->num_pcms = spec->num_pins;
bce0d2a8 1753 codec->pcm_info = spec->pcm_rec.list;
384a48d7 1754
84eb01be
TI		 1755 return 0;
1756}
1757
0b6c49b5
DH		 1758static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
1759{
31ef2257 1760 char hdmi_str[32] = "HDMI/DP";
0b6c49b5 1761 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 1762 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1763 int pcmdev = get_pcm_rec(spec, pin_idx)->device;
0b6c49b5 1764
31ef2257
TI		 1765 if (pcmdev > 0)
1766 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
30efd8de
DH		 1767 if (!is_jack_detectable(codec, per_pin->pin_nid))
1768 strncat(hdmi_str, " Phantom",
1769 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
0b6c49b5 1770
31ef2257 1771 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 0);
0b6c49b5
DH		 1772}
1773
84eb01be
TI		 1774static int generic_hdmi_build_controls(struct hda_codec *codec)
1775{
1776 struct hdmi_spec *spec = codec->spec;
1777 int err;
384a48d7 1778 int pin_idx;
84eb01be 1779
384a48d7 1780 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1781 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
0b6c49b5
DH		 1782
1783 err = generic_hdmi_build_jack(codec, pin_idx);
1784 if (err < 0)
1785 return err;
1786
dcda5806
TI		 1787 err = snd_hda_create_dig_out_ctls(codec,
1788 per_pin->pin_nid,
1789 per_pin->mux_nids[0],
1790 HDA_PCM_TYPE_HDMI);
84eb01be
TI		 1791 if (err < 0)
1792 return err;
384a48d7 1793 snd_hda_spdif_ctls_unassign(codec, pin_idx);
14bc52b8
PLB		 1794
1795 /* add control for ELD Bytes */
bce0d2a8
TI		 1796 err = hdmi_create_eld_ctl(codec, pin_idx,
1797 get_pcm_rec(spec, pin_idx)->device);
14bc52b8
PLB		 1798
1799 if (err < 0)
1800 return err;
31ef2257 1801
82b1d73f 1802 hdmi_present_sense(per_pin, 0);
84eb01be
TI		 1803 }
1804
d45e6889
TI		 1805 /* add channel maps */
1806 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1807 struct snd_pcm_chmap *chmap;
1808 struct snd_kcontrol *kctl;
1809 int i;
2ca320e2
TI		 1810
1811 if (!codec->pcm_info[pin_idx].pcm)
1812 break;
d45e6889
TI		 1813 err = snd_pcm_add_chmap_ctls(codec->pcm_info[pin_idx].pcm,
1814 SNDRV_PCM_STREAM_PLAYBACK,
1815 NULL, 0, pin_idx, &chmap);
1816 if (err < 0)
1817 return err;
1818 /* override handlers */
1819 chmap->private_data = codec;
1820 kctl = chmap->kctl;
1821 for (i = 0; i < kctl->count; i++)
1822 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
1823 kctl->info = hdmi_chmap_ctl_info;
1824 kctl->get = hdmi_chmap_ctl_get;
1825 kctl->put = hdmi_chmap_ctl_put;
1826 kctl->tlv.c = hdmi_chmap_ctl_tlv;
1827 }
1828
84eb01be
TI		 1829 return 0;
1830}
1831
8b8d654b 1832static int generic_hdmi_init_per_pins(struct hda_codec *codec)
84eb01be
TI		 1833{
1834 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1835 int pin_idx;
1836
1837 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1838 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1839 struct hdmi_eld *eld = &per_pin->sink_eld;
84eb01be 1840
744626da 1841 per_pin->codec = codec;
4bd038f9 1842 mutex_init(&eld->lock);
744626da 1843 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
384a48d7 1844 snd_hda_eld_proc_new(codec, eld, pin_idx);
84eb01be 1845 }
8b8d654b
TI		 1846 return 0;
1847}
1848
1849static int generic_hdmi_init(struct hda_codec *codec)
1850{
1851 struct hdmi_spec *spec = codec->spec;
1852 int pin_idx;
1853
1854 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1855 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
8b8d654b
TI		 1856 hda_nid_t pin_nid = per_pin->pin_nid;
1857
1858 hdmi_init_pin(codec, pin_nid);
1859 snd_hda_jack_detect_enable(codec, pin_nid, pin_nid);
1860 }
84eb01be
TI		 1861 return 0;
1862}
1863
bce0d2a8
TI		 1864static void hdmi_array_init(struct hdmi_spec *spec, int nums)
1865{
1866 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
1867 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
1868 snd_array_init(&spec->pcm_rec, sizeof(struct hda_pcm), nums);
1869}
1870
1871static void hdmi_array_free(struct hdmi_spec *spec)
1872{
1873 snd_array_free(&spec->pins);
1874 snd_array_free(&spec->cvts);
1875 snd_array_free(&spec->pcm_rec);
1876}
1877
84eb01be
TI		 1878static void generic_hdmi_free(struct hda_codec *codec)
1879{
1880 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1881 int pin_idx;
1882
1883 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1884 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1885 struct hdmi_eld *eld = &per_pin->sink_eld;
84eb01be 1886
744626da 1887 cancel_delayed_work(&per_pin->work);
384a48d7
SW		 1888 snd_hda_eld_proc_free(codec, eld);
1889 }
84eb01be 1890
744626da 1891 flush_workqueue(codec->bus->workq);
bce0d2a8 1892 hdmi_array_free(spec);
84eb01be
TI		 1893 kfree(spec);
1894}
1895
28cb72e5
WX		 1896#ifdef CONFIG_PM
1897static int generic_hdmi_resume(struct hda_codec *codec)
1898{
1899 struct hdmi_spec *spec = codec->spec;
1900 int pin_idx;
1901
1902 generic_hdmi_init(codec);
1903 snd_hda_codec_resume_amp(codec);
1904 snd_hda_codec_resume_cache(codec);
1905
1906 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1907 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1908 hdmi_present_sense(per_pin, 1);
1909 }
1910 return 0;
1911}
1912#endif
1913
fb79e1e0 1914static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 1915 .init = generic_hdmi_init,
1916 .free = generic_hdmi_free,
1917 .build_pcms = generic_hdmi_build_pcms,
1918 .build_controls = generic_hdmi_build_controls,
1919 .unsol_event = hdmi_unsol_event,
28cb72e5
WX		 1920#ifdef CONFIG_PM
1921 .resume = generic_hdmi_resume,
1922#endif
84eb01be
TI		 1923};
1924
6ffe168f 1925
c88d4e84
TI		 1926static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1927 hda_nid_t nid)
1928{
1929 struct hdmi_spec *spec = codec->spec;
1930 hda_nid_t conns[4];
1931 int nconns;
6ffe168f 1932
c88d4e84
TI		 1933 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
1934 if (nconns == spec->num_cvts &&
1935 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
6ffe168f
ML		 1936 return;
1937
c88d4e84
TI		 1938 /* override pins connection list */
1939 snd_printdd("hdmi: haswell: override pin connection 0x%x\n", nid);
1940 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
6ffe168f
ML		 1941}
1942
1611a9c9
ML		 1943#define INTEL_VENDOR_NID 0x08
1944#define INTEL_GET_VENDOR_VERB 0xf81
1945#define INTEL_SET_VENDOR_VERB 0x781
1946#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
1947#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
1948
1949static void intel_haswell_enable_all_pins(struct hda_codec *codec,
17df3f55 1950 bool update_tree)
1611a9c9
ML		 1951{
1952 unsigned int vendor_param;
1953
1611a9c9
ML		 1954 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
1955 INTEL_GET_VENDOR_VERB, 0);
1956 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
1957 return;
1958
1959 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
1960 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
1961 INTEL_SET_VENDOR_VERB, vendor_param);
1962 if (vendor_param == -1)
1963 return;
1964
17df3f55
TI		 1965 if (update_tree)
1966 snd_hda_codec_update_widgets(codec);
1611a9c9
ML		 1967}
1968
c88d4e84
TI		 1969static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
1970{
1971 unsigned int vendor_param;
1972
1973 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
1974 INTEL_GET_VENDOR_VERB, 0);
1975 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
1976 return;
1977
1978 /* enable DP1.2 mode */
1979 vendor_param |= INTEL_EN_DP12;
1980 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
1981 INTEL_SET_VENDOR_VERB, vendor_param);
1982}
1983
17df3f55
TI		 1984/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
1985 * Otherwise you may get severe h/w communication errors.
1986 */
1987static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
1988 unsigned int power_state)
1989{
1990 if (power_state == AC_PWRST_D0) {
1991 intel_haswell_enable_all_pins(codec, false);
1992 intel_haswell_fixup_enable_dp12(codec);
1993 }
c88d4e84 1994
17df3f55
TI		 1995 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
1996 snd_hda_codec_set_power_to_all(codec, fg, power_state);
1997}
6ffe168f 1998
84eb01be
TI		 1999static int patch_generic_hdmi(struct hda_codec *codec)
2000{
2001 struct hdmi_spec *spec;
84eb01be
TI		 2002
2003 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2004 if (spec == NULL)
2005 return -ENOMEM;
2006
2007 codec->spec = spec;
bce0d2a8 2008 hdmi_array_init(spec, 4);
6ffe168f 2009
fb87fa3a 2010 if (is_haswell(codec)) {
17df3f55 2011 intel_haswell_enable_all_pins(codec, true);
c88d4e84 2012 intel_haswell_fixup_enable_dp12(codec);
17df3f55 2013 }
6ffe168f 2014
84eb01be
TI		 2015 if (hdmi_parse_codec(codec) < 0) {
2016 codec->spec = NULL;
2017 kfree(spec);
2018 return -EINVAL;
2019 }
2020 codec->patch_ops = generic_hdmi_patch_ops;
fb87fa3a 2021 if (is_haswell(codec)) {
17df3f55 2022 codec->patch_ops.set_power_state = haswell_set_power_state;
5dc989bd
ML		 2023 codec->dp_mst = true;
2024 }
17df3f55 2025
8b8d654b 2026 generic_hdmi_init_per_pins(codec);
84eb01be 2027
84eb01be
TI		 2028 init_channel_allocations();
2029
2030 return 0;
2031}
2032
3aaf8980
SW		 2033/*
2034 * Shared non-generic implementations
2035 */
2036
2037static int simple_playback_build_pcms(struct hda_codec *codec)
2038{
2039 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2040 struct hda_pcm *info;
8ceb332d
TI		 2041 unsigned int chans;
2042 struct hda_pcm_stream *pstr;
bce0d2a8 2043 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2044
bce0d2a8
TI		 2045 per_cvt = get_cvt(spec, 0);
2046 chans = get_wcaps(codec, per_cvt->cvt_nid);
8ceb332d 2047 chans = get_wcaps_channels(chans);
3aaf8980 2048
bce0d2a8
TI		 2049 info = snd_array_new(&spec->pcm_rec);
2050 if (!info)
2051 return -ENOMEM;
2052 info->name = get_pin(spec, 0)->pcm_name;
2053 sprintf(info->name, "HDMI 0");
8ceb332d
TI		 2054 info->pcm_type = HDA_PCM_TYPE_HDMI;
2055 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2056 *pstr = spec->pcm_playback;
bce0d2a8 2057 pstr->nid = per_cvt->cvt_nid;
8ceb332d
TI		 2058 if (pstr->channels_max <= 2 && chans && chans <= 16)
2059 pstr->channels_max = chans;
3aaf8980 2060
bce0d2a8
TI		 2061 codec->num_pcms = 1;
2062 codec->pcm_info = info;
2063
3aaf8980
SW		 2064 return 0;
2065}
2066
4b6ace9e
TI		 2067/* unsolicited event for jack sensing */
2068static void simple_hdmi_unsol_event(struct hda_codec *codec,
2069 unsigned int res)
2070{
9dd8cf12 2071 snd_hda_jack_set_dirty_all(codec);
4b6ace9e
TI		 2072 snd_hda_jack_report_sync(codec);
2073}
2074
2075/* generic_hdmi_build_jack can be used for simple_hdmi, too,
2076 * as long as spec->pins[] is set correctly
2077 */
2078#define simple_hdmi_build_jack generic_hdmi_build_jack
2079
3aaf8980
SW		 2080static int simple_playback_build_controls(struct hda_codec *codec)
2081{
2082 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2083 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2084 int err;
3aaf8980 2085
bce0d2a8
TI		 2086 per_cvt = get_cvt(spec, 0);
2087 err = snd_hda_create_spdif_out_ctls(codec, per_cvt->cvt_nid,
2088 per_cvt->cvt_nid);
8ceb332d
TI		 2089 if (err < 0)
2090 return err;
2091 return simple_hdmi_build_jack(codec, 0);
3aaf8980
SW		 2092}
2093
4f0110ce
TI		 2094static int simple_playback_init(struct hda_codec *codec)
2095{
2096 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 2097 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2098 hda_nid_t pin = per_pin->pin_nid;
8ceb332d
TI		 2099
2100 snd_hda_codec_write(codec, pin, 0,
2101 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2102 /* some codecs require to unmute the pin */
2103 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2104 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2105 AMP_OUT_UNMUTE);
2106 snd_hda_jack_detect_enable(codec, pin, pin);
4f0110ce
TI		 2107 return 0;
2108}
2109
3aaf8980
SW		 2110static void simple_playback_free(struct hda_codec *codec)
2111{
2112 struct hdmi_spec *spec = codec->spec;
2113
bce0d2a8 2114 hdmi_array_free(spec);
3aaf8980
SW		 2115 kfree(spec);
2116}
2117
84eb01be
TI		 2118/*
2119 * Nvidia specific implementations
2120 */
2121
2122#define Nv_VERB_SET_Channel_Allocation 0xF79
2123#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2124#define Nv_VERB_SET_Audio_Protection_On 0xF98
2125#define Nv_VERB_SET_Audio_Protection_Off 0xF99
2126
2127#define nvhdmi_master_con_nid_7x 0x04
2128#define nvhdmi_master_pin_nid_7x 0x05
2129
fb79e1e0 2130static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 2131 /*front, rear, clfe, rear_surr */
2132 0x6, 0x8, 0xa, 0xc,
2133};
2134
ceaa86ba
TI		 2135static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2136 /* set audio protect on */
2137 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2138 /* enable digital output on pin widget */
2139 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2140 {} /* terminator */
2141};
2142
2143static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
84eb01be
TI		 2144 /* set audio protect on */
2145 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2146 /* enable digital output on pin widget */
2147 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2148 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2149 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2150 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2151 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2152 {} /* terminator */
2153};
2154
2155#ifdef LIMITED_RATE_FMT_SUPPORT
2156/* support only the safe format and rate */
2157#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2158#define SUPPORTED_MAXBPS 16
2159#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2160#else
2161/* support all rates and formats */
2162#define SUPPORTED_RATES \
2163 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2164 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2165 SNDRV_PCM_RATE_192000)
2166#define SUPPORTED_MAXBPS 24
2167#define SUPPORTED_FORMATS \
2168 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2169#endif
2170
ceaa86ba
TI		 2171static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2172{
2173 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2174 return 0;
2175}
2176
2177static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
84eb01be 2178{
ceaa86ba 2179 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
84eb01be
TI		 2180 return 0;
2181}
2182
393004b2
ND		 2183static unsigned int channels_2_6_8[] = {
2184 2, 6, 8
2185};
2186
2187static unsigned int channels_2_8[] = {
2188 2, 8
2189};
2190
2191static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2192 .count = ARRAY_SIZE(channels_2_6_8),
2193 .list = channels_2_6_8,
2194 .mask = 0,
2195};
2196
2197static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2198 .count = ARRAY_SIZE(channels_2_8),
2199 .list = channels_2_8,
2200 .mask = 0,
2201};
2202
84eb01be
TI		 2203static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2204 struct hda_codec *codec,
2205 struct snd_pcm_substream *substream)
2206{
2207 struct hdmi_spec *spec = codec->spec;
393004b2
ND		 2208 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2209
2210 switch (codec->preset->id) {
2211 case 0x10de0002:
2212 case 0x10de0003:
2213 case 0x10de0005:
2214 case 0x10de0006:
2215 hw_constraints_channels = &hw_constraints_2_8_channels;
2216 break;
2217 case 0x10de0007:
2218 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2219 break;
2220 default:
2221 break;
2222 }
2223
2224 if (hw_constraints_channels != NULL) {
2225 snd_pcm_hw_constraint_list(substream->runtime, 0,
2226 SNDRV_PCM_HW_PARAM_CHANNELS,
2227 hw_constraints_channels);
ad09fc9d
TI		 2228 } else {
2229 snd_pcm_hw_constraint_step(substream->runtime, 0,
2230 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 2231 }
2232
84eb01be
TI		 2233 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2234}
2235
2236static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2237 struct hda_codec *codec,
2238 struct snd_pcm_substream *substream)
2239{
2240 struct hdmi_spec *spec = codec->spec;
2241 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2242}
2243
2244static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2245 struct hda_codec *codec,
2246 unsigned int stream_tag,
2247 unsigned int format,
2248 struct snd_pcm_substream *substream)
2249{
2250 struct hdmi_spec *spec = codec->spec;
2251 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2252 stream_tag, format, substream);
2253}
2254
d0b1252d
TI		 2255static const struct hda_pcm_stream simple_pcm_playback = {
2256 .substreams = 1,
2257 .channels_min = 2,
2258 .channels_max = 2,
2259 .ops = {
2260 .open = simple_playback_pcm_open,
2261 .close = simple_playback_pcm_close,
2262 .prepare = simple_playback_pcm_prepare
2263 },
2264};
2265
2266static const struct hda_codec_ops simple_hdmi_patch_ops = {
2267 .build_controls = simple_playback_build_controls,
2268 .build_pcms = simple_playback_build_pcms,
2269 .init = simple_playback_init,
2270 .free = simple_playback_free,
250e41ac 2271 .unsol_event = simple_hdmi_unsol_event,
d0b1252d
TI		 2272};
2273
2274static int patch_simple_hdmi(struct hda_codec *codec,
2275 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2276{
2277 struct hdmi_spec *spec;
bce0d2a8
TI		 2278 struct hdmi_spec_per_cvt *per_cvt;
2279 struct hdmi_spec_per_pin *per_pin;
d0b1252d
TI		 2280
2281 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2282 if (!spec)
2283 return -ENOMEM;
2284
2285 codec->spec = spec;
bce0d2a8 2286 hdmi_array_init(spec, 1);
d0b1252d
TI		 2287
2288 spec->multiout.num_dacs = 0; /* no analog */
2289 spec->multiout.max_channels = 2;
2290 spec->multiout.dig_out_nid = cvt_nid;
2291 spec->num_cvts = 1;
2292 spec->num_pins = 1;
bce0d2a8
TI		 2293 per_pin = snd_array_new(&spec->pins);
2294 per_cvt = snd_array_new(&spec->cvts);
2295 if (!per_pin || !per_cvt) {
2296 simple_playback_free(codec);
2297 return -ENOMEM;
2298 }
2299 per_cvt->cvt_nid = cvt_nid;
2300 per_pin->pin_nid = pin_nid;
d0b1252d
TI		 2301 spec->pcm_playback = simple_pcm_playback;
2302
2303 codec->patch_ops = simple_hdmi_patch_ops;
2304
2305 return 0;
2306}
2307
1f348522
AP		 2308static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2309 int channels)
2310{
2311 unsigned int chanmask;
2312 int chan = channels ? (channels - 1) : 1;
2313
2314 switch (channels) {
2315 default:
2316 case 0:
2317 case 2:
2318 chanmask = 0x00;
2319 break;
2320 case 4:
2321 chanmask = 0x08;
2322 break;
2323 case 6:
2324 chanmask = 0x0b;
2325 break;
2326 case 8:
2327 chanmask = 0x13;
2328 break;
2329 }
2330
2331 /* Set the audio infoframe channel allocation and checksum fields. The
2332 * channel count is computed implicitly by the hardware. */
2333 snd_hda_codec_write(codec, 0x1, 0,
2334 Nv_VERB_SET_Channel_Allocation, chanmask);
2335
2336 snd_hda_codec_write(codec, 0x1, 0,
2337 Nv_VERB_SET_Info_Frame_Checksum,
2338 (0x71 - chan - chanmask));
2339}
2340
84eb01be
TI		 2341static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2342 struct hda_codec *codec,
2343 struct snd_pcm_substream *substream)
2344{
2345 struct hdmi_spec *spec = codec->spec;
2346 int i;
2347
2348 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2349 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2350 for (i = 0; i < 4; i++) {
2351 /* set the stream id */
2352 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2353 AC_VERB_SET_CHANNEL_STREAMID, 0);
2354 /* set the stream format */
2355 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2356 AC_VERB_SET_STREAM_FORMAT, 0);
2357 }
2358
1f348522
AP		 2359 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2360 * streams are disabled. */
2361 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2362
84eb01be
TI		 2363 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2364}
2365
2366static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2367 struct hda_codec *codec,
2368 unsigned int stream_tag,
2369 unsigned int format,
2370 struct snd_pcm_substream *substream)
2371{
2372 int chs;
112daa7a 2373 unsigned int dataDCC2, channel_id;
84eb01be 2374 int i;
7c935976 2375 struct hdmi_spec *spec = codec->spec;
e3245cdd 2376 struct hda_spdif_out *spdif;
bce0d2a8 2377 struct hdmi_spec_per_cvt *per_cvt;
84eb01be
TI		 2378
2379 mutex_lock(&codec->spdif_mutex);
bce0d2a8
TI		 2380 per_cvt = get_cvt(spec, 0);
2381 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
84eb01be
TI		 2382
2383 chs = substream->runtime->channels;
84eb01be 2384
84eb01be
TI		 2385 dataDCC2 = 0x2;
2386
84eb01be 2387 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 2388 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2389 snd_hda_codec_write(codec,
2390 nvhdmi_master_con_nid_7x,
2391 0,
2392 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2393 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2394
2395 /* set the stream id */
2396 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2397 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2398
2399 /* set the stream format */
2400 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2401 AC_VERB_SET_STREAM_FORMAT, format);
2402
2403 /* turn on again (if needed) */
2404 /* enable and set the channel status audio/data flag */
7c935976 2405 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2406 snd_hda_codec_write(codec,
2407 nvhdmi_master_con_nid_7x,
2408 0,
2409 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2410 spdif->ctls & 0xff);
84eb01be
TI		 2411 snd_hda_codec_write(codec,
2412 nvhdmi_master_con_nid_7x,
2413 0,
2414 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2415 }
2416
2417 for (i = 0; i < 4; i++) {
2418 if (chs == 2)
2419 channel_id = 0;
2420 else
2421 channel_id = i * 2;
2422
2423 /* turn off SPDIF once;
2424 *otherwise the IEC958 bits won't be updated
2425 */
2426 if (codec->spdif_status_reset &&
7c935976 2427 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2428 snd_hda_codec_write(codec,
2429 nvhdmi_con_nids_7x[i],
2430 0,
2431 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2432 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2433 /* set the stream id */
2434 snd_hda_codec_write(codec,
2435 nvhdmi_con_nids_7x[i],
2436 0,
2437 AC_VERB_SET_CHANNEL_STREAMID,
2438 (stream_tag << 4) | channel_id);
2439 /* set the stream format */
2440 snd_hda_codec_write(codec,
2441 nvhdmi_con_nids_7x[i],
2442 0,
2443 AC_VERB_SET_STREAM_FORMAT,
2444 format);
2445 /* turn on again (if needed) */
2446 /* enable and set the channel status audio/data flag */
2447 if (codec->spdif_status_reset &&
7c935976 2448 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2449 snd_hda_codec_write(codec,
2450 nvhdmi_con_nids_7x[i],
2451 0,
2452 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2453 spdif->ctls & 0xff);
84eb01be
TI		 2454 snd_hda_codec_write(codec,
2455 nvhdmi_con_nids_7x[i],
2456 0,
2457 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2458 }
2459 }
2460
1f348522 2461 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 2462
2463 mutex_unlock(&codec->spdif_mutex);
2464 return 0;
2465}
2466
fb79e1e0 2467static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 2468 .substreams = 1,
2469 .channels_min = 2,
2470 .channels_max = 8,
2471 .nid = nvhdmi_master_con_nid_7x,
2472 .rates = SUPPORTED_RATES,
2473 .maxbps = SUPPORTED_MAXBPS,
2474 .formats = SUPPORTED_FORMATS,
2475 .ops = {
2476 .open = simple_playback_pcm_open,
2477 .close = nvhdmi_8ch_7x_pcm_close,
2478 .prepare = nvhdmi_8ch_7x_pcm_prepare
2479 },
2480};
2481
84eb01be
TI		 2482static int patch_nvhdmi_2ch(struct hda_codec *codec)
2483{
2484 struct hdmi_spec *spec;
d0b1252d
TI		 2485 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2486 nvhdmi_master_pin_nid_7x);
2487 if (err < 0)
2488 return err;
84eb01be 2489
ceaa86ba 2490 codec->patch_ops.init = nvhdmi_7x_init_2ch;
d0b1252d
TI		 2491 /* override the PCM rates, etc, as the codec doesn't give full list */
2492 spec = codec->spec;
2493 spec->pcm_playback.rates = SUPPORTED_RATES;
2494 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2495 spec->pcm_playback.formats = SUPPORTED_FORMATS;
84eb01be
TI		 2496 return 0;
2497}
2498
53775b0d
TI		 2499static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2500{
2501 struct hdmi_spec *spec = codec->spec;
2502 int err = simple_playback_build_pcms(codec);
bce0d2a8
TI		 2503 if (!err) {
2504 struct hda_pcm *info = get_pcm_rec(spec, 0);
2505 info->own_chmap = true;
2506 }
53775b0d
TI		 2507 return err;
2508}
2509
2510static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2511{
2512 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2513 struct hda_pcm *info;
53775b0d
TI		 2514 struct snd_pcm_chmap *chmap;
2515 int err;
2516
2517 err = simple_playback_build_controls(codec);
2518 if (err < 0)
2519 return err;
2520
2521 /* add channel maps */
bce0d2a8
TI		 2522 info = get_pcm_rec(spec, 0);
2523 err = snd_pcm_add_chmap_ctls(info->pcm,
53775b0d
TI		 2524 SNDRV_PCM_STREAM_PLAYBACK,
2525 snd_pcm_alt_chmaps, 8, 0, &chmap);
2526 if (err < 0)
2527 return err;
2528 switch (codec->preset->id) {
2529 case 0x10de0002:
2530 case 0x10de0003:
2531 case 0x10de0005:
2532 case 0x10de0006:
2533 chmap->channel_mask = (1U << 2) | (1U << 8);
2534 break;
2535 case 0x10de0007:
2536 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2537 }
2538 return 0;
2539}
2540
84eb01be
TI		 2541static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2542{
2543 struct hdmi_spec *spec;
2544 int err = patch_nvhdmi_2ch(codec);
84eb01be
TI		 2545 if (err < 0)
2546 return err;
2547 spec = codec->spec;
2548 spec->multiout.max_channels = 8;
d0b1252d 2549 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
ceaa86ba 2550 codec->patch_ops.init = nvhdmi_7x_init_8ch;
53775b0d
TI		 2551 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2552 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
1f348522
AP		 2553
2554 /* Initialize the audio infoframe channel mask and checksum to something
2555 * valid */
2556 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2557
84eb01be
TI		 2558 return 0;
2559}
2560
2561/*
2562 * ATI-specific implementations
2563 *
2564 * FIXME: we may omit the whole this and use the generic code once after
2565 * it's confirmed to work.
2566 */
2567
2568#define ATIHDMI_CVT_NID 0x02 /* audio converter */
2569#define ATIHDMI_PIN_NID 0x03 /* HDMI output pin */
2570
2571static int atihdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2572 struct hda_codec *codec,
2573 unsigned int stream_tag,
2574 unsigned int format,
2575 struct snd_pcm_substream *substream)
2576{
2577 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2578 struct hdmi_spec_per_cvt *per_cvt = get_cvt(spec, 0);
84eb01be
TI		 2579 int chans = substream->runtime->channels;
2580 int i, err;
2581
2582 err = simple_playback_pcm_prepare(hinfo, codec, stream_tag, format,
2583 substream);
2584 if (err < 0)
2585 return err;
bce0d2a8 2586 snd_hda_codec_write(codec, per_cvt->cvt_nid, 0,
384a48d7 2587 AC_VERB_SET_CVT_CHAN_COUNT, chans - 1);
84eb01be
TI		 2588 /* FIXME: XXX */
2589 for (i = 0; i < chans; i++) {
bce0d2a8 2590 snd_hda_codec_write(codec, per_cvt->cvt_nid, 0,
84eb01be
TI		 2591 AC_VERB_SET_HDMI_CHAN_SLOT,
2592 (i << 4) | i);
2593 }
2594 return 0;
2595}
2596
84eb01be
TI		 2597static int patch_atihdmi(struct hda_codec *codec)
2598{
2599 struct hdmi_spec *spec;
d0b1252d
TI		 2600 int err = patch_simple_hdmi(codec, ATIHDMI_CVT_NID, ATIHDMI_PIN_NID);
2601 if (err < 0)
2602 return err;
2603 spec = codec->spec;
2604 spec->pcm_playback.ops.prepare = atihdmi_playback_pcm_prepare;
84eb01be
TI		 2605 return 0;
2606}
2607
3de5ff88
AL		 2608/* VIA HDMI Implementation */
2609#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
2610#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
2611
3de5ff88
AL		 2612static int patch_via_hdmi(struct hda_codec *codec)
2613{
250e41ac 2614 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3de5ff88 2615}
84eb01be
TI		 2616
2617/*
2618 * patch entries
2619 */
fb79e1e0 2620static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
84eb01be
TI		 2621{ .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
2622{ .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
2623{ .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
36e9c135 2624{ .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 2625{ .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
2626{ .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
2627{ .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
2628{ .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2629{ .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2630{ .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2631{ .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2632{ .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
5d44f927
SW		 2633{ .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_generic_hdmi },
2634{ .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_generic_hdmi },
2635{ .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_generic_hdmi },
2636{ .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_generic_hdmi },
2637{ .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_generic_hdmi },
2638{ .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_generic_hdmi },
2639{ .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_generic_hdmi },
2640{ .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_generic_hdmi },
2641{ .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_generic_hdmi },
2642{ .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_generic_hdmi },
2643{ .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_generic_hdmi },
c8900a0f 2644/* 17 is known to be absent */
5d44f927
SW		 2645{ .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_generic_hdmi },
2646{ .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_generic_hdmi },
2647{ .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_generic_hdmi },
2648{ .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_generic_hdmi },
2649{ .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_generic_hdmi },
2650{ .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_generic_hdmi },
2651{ .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_generic_hdmi },
2652{ .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_generic_hdmi },
2653{ .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_generic_hdmi },
2654{ .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_generic_hdmi },
7ae48b56 2655{ .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_generic_hdmi },
d52392b1 2656{ .id = 0x10de0060, .name = "GPU 60 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 2657{ .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
2658{ .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
3de5ff88
AL		 2659{ .id = 0x11069f80, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
2660{ .id = 0x11069f81, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
2661{ .id = 0x11069f84, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
2662{ .id = 0x11069f85, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 2663{ .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
2664{ .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
2665{ .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
2666{ .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
2667{ .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
2668{ .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
591e610d 2669{ .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
1c76684d 2670{ .id = 0x80862807, .name = "Haswell HDMI", .patch = patch_generic_hdmi },
6edc59e6 2671{ .id = 0x80862880, .name = "CedarTrail HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 2672{ .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
2673{} /* terminator */
2674};
2675
2676MODULE_ALIAS("snd-hda-codec-id:1002793c");
2677MODULE_ALIAS("snd-hda-codec-id:10027919");
2678MODULE_ALIAS("snd-hda-codec-id:1002791a");
2679MODULE_ALIAS("snd-hda-codec-id:1002aa01");
2680MODULE_ALIAS("snd-hda-codec-id:10951390");
2681MODULE_ALIAS("snd-hda-codec-id:10951392");
2682MODULE_ALIAS("snd-hda-codec-id:10de0002");
2683MODULE_ALIAS("snd-hda-codec-id:10de0003");
2684MODULE_ALIAS("snd-hda-codec-id:10de0005");
2685MODULE_ALIAS("snd-hda-codec-id:10de0006");
2686MODULE_ALIAS("snd-hda-codec-id:10de0007");
2687MODULE_ALIAS("snd-hda-codec-id:10de000a");
2688MODULE_ALIAS("snd-hda-codec-id:10de000b");
2689MODULE_ALIAS("snd-hda-codec-id:10de000c");
2690MODULE_ALIAS("snd-hda-codec-id:10de000d");
2691MODULE_ALIAS("snd-hda-codec-id:10de0010");
2692MODULE_ALIAS("snd-hda-codec-id:10de0011");
2693MODULE_ALIAS("snd-hda-codec-id:10de0012");
2694MODULE_ALIAS("snd-hda-codec-id:10de0013");
2695MODULE_ALIAS("snd-hda-codec-id:10de0014");
c8900a0f
RS		 2696MODULE_ALIAS("snd-hda-codec-id:10de0015");
2697MODULE_ALIAS("snd-hda-codec-id:10de0016");
84eb01be
TI		 2698MODULE_ALIAS("snd-hda-codec-id:10de0018");
2699MODULE_ALIAS("snd-hda-codec-id:10de0019");
2700MODULE_ALIAS("snd-hda-codec-id:10de001a");
2701MODULE_ALIAS("snd-hda-codec-id:10de001b");
2702MODULE_ALIAS("snd-hda-codec-id:10de001c");
2703MODULE_ALIAS("snd-hda-codec-id:10de0040");
2704MODULE_ALIAS("snd-hda-codec-id:10de0041");
2705MODULE_ALIAS("snd-hda-codec-id:10de0042");
2706MODULE_ALIAS("snd-hda-codec-id:10de0043");
2707MODULE_ALIAS("snd-hda-codec-id:10de0044");
7ae48b56 2708MODULE_ALIAS("snd-hda-codec-id:10de0051");
d52392b1 2709MODULE_ALIAS("snd-hda-codec-id:10de0060");
84eb01be
TI		 2710MODULE_ALIAS("snd-hda-codec-id:10de0067");
2711MODULE_ALIAS("snd-hda-codec-id:10de8001");
3de5ff88
AL		 2712MODULE_ALIAS("snd-hda-codec-id:11069f80");
2713MODULE_ALIAS("snd-hda-codec-id:11069f81");
2714MODULE_ALIAS("snd-hda-codec-id:11069f84");
2715MODULE_ALIAS("snd-hda-codec-id:11069f85");
84eb01be
TI		 2716MODULE_ALIAS("snd-hda-codec-id:17e80047");
2717MODULE_ALIAS("snd-hda-codec-id:80860054");
2718MODULE_ALIAS("snd-hda-codec-id:80862801");
2719MODULE_ALIAS("snd-hda-codec-id:80862802");
2720MODULE_ALIAS("snd-hda-codec-id:80862803");
2721MODULE_ALIAS("snd-hda-codec-id:80862804");
2722MODULE_ALIAS("snd-hda-codec-id:80862805");
591e610d 2723MODULE_ALIAS("snd-hda-codec-id:80862806");
1c76684d 2724MODULE_ALIAS("snd-hda-codec-id:80862807");
6edc59e6 2725MODULE_ALIAS("snd-hda-codec-id:80862880");
84eb01be
TI		 2726MODULE_ALIAS("snd-hda-codec-id:808629fb");
2727
2728MODULE_LICENSE("GPL");
2729MODULE_DESCRIPTION("HDMI HD-audio codec");
2730MODULE_ALIAS("snd-hda-codec-intelhdmi");
2731MODULE_ALIAS("snd-hda-codec-nvhdmi");
2732MODULE_ALIAS("snd-hda-codec-atihdmi");
2733
2734static struct hda_codec_preset_list intel_list = {
2735 .preset = snd_hda_preset_hdmi,
2736 .owner = THIS_MODULE,
2737};
2738
2739static int __init patch_hdmi_init(void)
2740{
2741 return snd_hda_add_codec_preset(&intel_list);
2742}
2743
2744static void __exit patch_hdmi_exit(void)
2745{
2746 snd_hda_delete_codec_preset(&intel_list);
2747}
2748
2749module_init(patch_hdmi_init)
2750module_exit(patch_hdmi_exit)
Linux kernel - Deliverables
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