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Merge branch 'fix/hda' into topic/hda
[deliverable/linux.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
079d88cc
WF		 9 *
10 * Authors:
11 * Wu Fengguang <wfg@linux.intel.com>
12 *
13 * Maintained by:
14 * Wu Fengguang <wfg@linux.intel.com>
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the Free
18 * Software Foundation; either version 2 of the License, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful, but
22 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
23 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 * for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software Foundation,
28 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
84eb01be
TI		 31#include <linux/init.h>
32#include <linux/delay.h>
33#include <linux/slab.h>
34#include <sound/core.h>
35#include "hda_codec.h"
36#include "hda_local.h"
37
38/*
39 * The HDMI/DisplayPort configuration can be highly dynamic. A graphics device
40 * could support two independent pipes, each of them can be connected to one or
41 * more ports (DVI, HDMI or DisplayPort).
42 *
43 * The HDA correspondence of pipes/ports are converter/pin nodes.
44 */
45#define MAX_HDMI_CVTS 3
46#define MAX_HDMI_PINS 3
079d88cc
WF		 47
48struct hdmi_spec {
49 int num_cvts;
50 int num_pins;
51 hda_nid_t cvt[MAX_HDMI_CVTS+1]; /* audio sources */
52 hda_nid_t pin[MAX_HDMI_PINS+1]; /* audio sinks */
53
54 /*
55 * source connection for each pin
56 */
57 hda_nid_t pin_cvt[MAX_HDMI_PINS+1];
58
59 /*
60 * HDMI sink attached to each pin
61 */
62 struct hdmi_eld sink_eld[MAX_HDMI_PINS];
63
64 /*
65 * export one pcm per pipe
66 */
67 struct hda_pcm pcm_rec[MAX_HDMI_CVTS];
bbbe3390 68 struct hda_pcm_stream codec_pcm_pars[MAX_HDMI_CVTS];
079d88cc
WF		 69
70 /*
84eb01be 71 * ati/nvhdmi specific
079d88cc
WF		 72 */
73 struct hda_multi_out multiout;
84eb01be 74 struct hda_pcm_stream *pcm_playback;
38faddb1
TI		 75
76 /* misc flags */
77 /* PD bit indicates only the update, not the current state */
78 unsigned int old_pin_detect:1;
079d88cc
WF		 79};
80
81
82struct hdmi_audio_infoframe {
83 u8 type; /* 0x84 */
84 u8 ver; /* 0x01 */
85 u8 len; /* 0x0a */
86
53d7d69d
WF		 87 u8 checksum;
88
079d88cc
WF		 89 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
90 u8 SS01_SF24;
91 u8 CXT04;
92 u8 CA;
93 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 94};
95
96struct dp_audio_infoframe {
97 u8 type; /* 0x84 */
98 u8 len; /* 0x1b */
99 u8 ver; /* 0x11 << 2 */
100
101 u8 CC02_CT47; /* match with HDMI infoframe from this on */
102 u8 SS01_SF24;
103 u8 CXT04;
104 u8 CA;
105 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 106};
107
108/*
109 * CEA speaker placement:
110 *
111 * FLH FCH FRH
112 * FLW FL FLC FC FRC FR FRW
113 *
114 * LFE
115 * TC
116 *
117 * RL RLC RC RRC RR
118 *
119 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
120 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
121 */
122enum cea_speaker_placement {
123 FL = (1 << 0), /* Front Left */
124 FC = (1 << 1), /* Front Center */
125 FR = (1 << 2), /* Front Right */
126 FLC = (1 << 3), /* Front Left Center */
127 FRC = (1 << 4), /* Front Right Center */
128 RL = (1 << 5), /* Rear Left */
129 RC = (1 << 6), /* Rear Center */
130 RR = (1 << 7), /* Rear Right */
131 RLC = (1 << 8), /* Rear Left Center */
132 RRC = (1 << 9), /* Rear Right Center */
133 LFE = (1 << 10), /* Low Frequency Effect */
134 FLW = (1 << 11), /* Front Left Wide */
135 FRW = (1 << 12), /* Front Right Wide */
136 FLH = (1 << 13), /* Front Left High */
137 FCH = (1 << 14), /* Front Center High */
138 FRH = (1 << 15), /* Front Right High */
139 TC = (1 << 16), /* Top Center */
140};
141
142/*
143 * ELD SA bits in the CEA Speaker Allocation data block
144 */
145static int eld_speaker_allocation_bits[] = {
146 [0] = FL | FR,
147 [1] = LFE,
148 [2] = FC,
149 [3] = RL | RR,
150 [4] = RC,
151 [5] = FLC | FRC,
152 [6] = RLC | RRC,
153 /* the following are not defined in ELD yet */
154 [7] = FLW | FRW,
155 [8] = FLH | FRH,
156 [9] = TC,
157 [10] = FCH,
158};
159
160struct cea_channel_speaker_allocation {
161 int ca_index;
162 int speakers[8];
163
164 /* derived values, just for convenience */
165 int channels;
166 int spk_mask;
167};
168
169/*
170 * ALSA sequence is:
171 *
172 * surround40 surround41 surround50 surround51 surround71
173 * ch0 front left = = = =
174 * ch1 front right = = = =
175 * ch2 rear left = = = =
176 * ch3 rear right = = = =
177 * ch4 LFE center center center
178 * ch5 LFE LFE
179 * ch6 side left
180 * ch7 side right
181 *
182 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
183 */
184static int hdmi_channel_mapping[0x32][8] = {
185 /* stereo */
186 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
187 /* 2.1 */
188 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
189 /* Dolby Surround */
190 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
191 /* surround40 */
192 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
193 /* 4ch */
194 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
195 /* surround41 */
9396d317 196 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
079d88cc
WF		 197 /* surround50 */
198 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
199 /* surround51 */
200 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
201 /* 7.1 */
202 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
203};
204
205/*
206 * This is an ordered list!
207 *
208 * The preceding ones have better chances to be selected by
53d7d69d 209 * hdmi_channel_allocation().
079d88cc
WF		 210 */
211static struct cea_channel_speaker_allocation channel_allocations[] = {
212/* channel: 7 6 5 4 3 2 1 0 */
213{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
214 /* 2.1 */
215{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
216 /* Dolby Surround */
217{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
218 /* surround40 */
219{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
220 /* surround41 */
221{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
222 /* surround50 */
223{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
224 /* surround51 */
225{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
226 /* 6.1 */
227{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
228 /* surround71 */
229{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
230
231{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
232{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
233{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
234{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
235{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
236{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
237{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
238{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
239{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
240{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
241{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
242{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
243{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
244{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
245{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
246{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
247{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
248{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
249{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
250{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
251{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
252{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
253{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
254{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
255{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
256{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
257{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
258{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
259{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
260{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
261{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
262{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
263{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
264{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
265{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
266{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
267{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
268{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
269{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
270{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
271{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
272};
273
274
275/*
276 * HDMI routines
277 */
278
279static int hda_node_index(hda_nid_t *nids, hda_nid_t nid)
280{
281 int i;
282
283 for (i = 0; nids[i]; i++)
284 if (nids[i] == nid)
285 return i;
286
287 snd_printk(KERN_WARNING "HDMI: nid %d not registered\n", nid);
288 return -EINVAL;
289}
290
291static void hdmi_get_show_eld(struct hda_codec *codec, hda_nid_t pin_nid,
292 struct hdmi_eld *eld)
293{
294 if (!snd_hdmi_get_eld(eld, codec, pin_nid))
295 snd_hdmi_show_eld(eld);
296}
297
298#ifdef BE_PARANOID
299static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
300 int *packet_index, int *byte_index)
301{
302 int val;
303
304 val = snd_hda_codec_read(codec, pin_nid, 0,
305 AC_VERB_GET_HDMI_DIP_INDEX, 0);
306
307 *packet_index = val >> 5;
308 *byte_index = val & 0x1f;
309}
310#endif
311
312static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
313 int packet_index, int byte_index)
314{
315 int val;
316
317 val = (packet_index << 5) | (byte_index & 0x1f);
318
319 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
320}
321
322static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
323 unsigned char val)
324{
325 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
326}
327
328static void hdmi_enable_output(struct hda_codec *codec, hda_nid_t pin_nid)
329{
330 /* Unmute */
331 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
332 snd_hda_codec_write(codec, pin_nid, 0,
333 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
334 /* Enable pin out */
335 snd_hda_codec_write(codec, pin_nid, 0,
336 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
337}
338
339static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t nid)
340{
341 return 1 + snd_hda_codec_read(codec, nid, 0,
342 AC_VERB_GET_CVT_CHAN_COUNT, 0);
343}
344
345static void hdmi_set_channel_count(struct hda_codec *codec,
346 hda_nid_t nid, int chs)
347{
348 if (chs != hdmi_get_channel_count(codec, nid))
349 snd_hda_codec_write(codec, nid, 0,
350 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
351}
352
353
354/*
355 * Channel mapping routines
356 */
357
358/*
359 * Compute derived values in channel_allocations[].
360 */
361static void init_channel_allocations(void)
362{
363 int i, j;
364 struct cea_channel_speaker_allocation *p;
365
366 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
367 p = channel_allocations + i;
368 p->channels = 0;
369 p->spk_mask = 0;
370 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
371 if (p->speakers[j]) {
372 p->channels++;
373 p->spk_mask |= p->speakers[j];
374 }
375 }
376}
377
378/*
379 * The transformation takes two steps:
380 *
381 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
382 * spk_mask => (channel_allocations[]) => ai->CA
383 *
384 * TODO: it could select the wrong CA from multiple candidates.
385*/
53d7d69d
WF		 386static int hdmi_channel_allocation(struct hda_codec *codec, hda_nid_t nid,
387 int channels)
079d88cc
WF		 388{
389 struct hdmi_spec *spec = codec->spec;
390 struct hdmi_eld *eld;
391 int i;
53d7d69d 392 int ca = 0;
079d88cc 393 int spk_mask = 0;
079d88cc
WF		 394 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
395
396 /*
397 * CA defaults to 0 for basic stereo audio
398 */
399 if (channels <= 2)
400 return 0;
401
402 i = hda_node_index(spec->pin_cvt, nid);
403 if (i < 0)
404 return 0;
405 eld = &spec->sink_eld[i];
406
407 /*
408 * HDMI sink's ELD info cannot always be retrieved for now, e.g.
409 * in console or for audio devices. Assume the highest speakers
410 * configuration, to _not_ prohibit multi-channel audio playback.
411 */
412 if (!eld->spk_alloc)
413 eld->spk_alloc = 0xffff;
414
415 /*
416 * expand ELD's speaker allocation mask
417 *
418 * ELD tells the speaker mask in a compact(paired) form,
419 * expand ELD's notions to match the ones used by Audio InfoFrame.
420 */
421 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
422 if (eld->spk_alloc & (1 << i))
423 spk_mask |= eld_speaker_allocation_bits[i];
424 }
425
426 /* search for the first working match in the CA table */
427 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
428 if (channels == channel_allocations[i].channels &&
429 (spk_mask & channel_allocations[i].spk_mask) ==
430 channel_allocations[i].spk_mask) {
53d7d69d 431 ca = channel_allocations[i].ca_index;
079d88cc
WF		 432 break;
433 }
434 }
435
436 snd_print_channel_allocation(eld->spk_alloc, buf, sizeof(buf));
2abbf439 437 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
53d7d69d 438 ca, channels, buf);
079d88cc 439
53d7d69d 440 return ca;
079d88cc
WF		 441}
442
443static void hdmi_debug_channel_mapping(struct hda_codec *codec,
444 hda_nid_t pin_nid)
445{
446#ifdef CONFIG_SND_DEBUG_VERBOSE
447 int i;
448 int slot;
449
450 for (i = 0; i < 8; i++) {
451 slot = snd_hda_codec_read(codec, pin_nid, 0,
452 AC_VERB_GET_HDMI_CHAN_SLOT, i);
453 printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n",
454 slot >> 4, slot & 0xf);
455 }
456#endif
457}
458
459
460static void hdmi_setup_channel_mapping(struct hda_codec *codec,
461 hda_nid_t pin_nid,
53d7d69d 462 int ca)
079d88cc
WF		 463{
464 int i;
079d88cc
WF		 465 int err;
466
467 if (hdmi_channel_mapping[ca][1] == 0) {
468 for (i = 0; i < channel_allocations[ca].channels; i++)
469 hdmi_channel_mapping[ca][i] = i | (i << 4);
470 for (; i < 8; i++)
471 hdmi_channel_mapping[ca][i] = 0xf | (i << 4);
472 }
473
474 for (i = 0; i < 8; i++) {
475 err = snd_hda_codec_write(codec, pin_nid, 0,
476 AC_VERB_SET_HDMI_CHAN_SLOT,
477 hdmi_channel_mapping[ca][i]);
478 if (err) {
2abbf439
WF		 479 snd_printdd(KERN_NOTICE
480 "HDMI: channel mapping failed\n");
079d88cc
WF		 481 break;
482 }
483 }
484
485 hdmi_debug_channel_mapping(codec, pin_nid);
486}
487
488
489/*
490 * Audio InfoFrame routines
491 */
492
493/*
494 * Enable Audio InfoFrame Transmission
495 */
496static void hdmi_start_infoframe_trans(struct hda_codec *codec,
497 hda_nid_t pin_nid)
498{
499 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
500 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
501 AC_DIPXMIT_BEST);
502}
503
504/*
505 * Disable Audio InfoFrame Transmission
506 */
507static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
508 hda_nid_t pin_nid)
509{
510 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
511 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
512 AC_DIPXMIT_DISABLE);
513}
514
515static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
516{
517#ifdef CONFIG_SND_DEBUG_VERBOSE
518 int i;
519 int size;
520
521 size = snd_hdmi_get_eld_size(codec, pin_nid);
522 printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size);
523
524 for (i = 0; i < 8; i++) {
525 size = snd_hda_codec_read(codec, pin_nid, 0,
526 AC_VERB_GET_HDMI_DIP_SIZE, i);
527 printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size);
528 }
529#endif
530}
531
532static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
533{
534#ifdef BE_PARANOID
535 int i, j;
536 int size;
537 int pi, bi;
538 for (i = 0; i < 8; i++) {
539 size = snd_hda_codec_read(codec, pin_nid, 0,
540 AC_VERB_GET_HDMI_DIP_SIZE, i);
541 if (size == 0)
542 continue;
543
544 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
545 for (j = 1; j < 1000; j++) {
546 hdmi_write_dip_byte(codec, pin_nid, 0x0);
547 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
548 if (pi != i)
549 snd_printd(KERN_INFO "dip index %d: %d != %d\n",
550 bi, pi, i);
551 if (bi == 0) /* byte index wrapped around */
552 break;
553 }
554 snd_printd(KERN_INFO
555 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
556 i, size, j);
557 }
558#endif
559}
560
53d7d69d 561static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 562{
53d7d69d 563 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 564 u8 sum = 0;
565 int i;
566
53d7d69d 567 hdmi_ai->checksum = 0;
079d88cc 568
53d7d69d 569 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 570 sum += bytes[i];
571
53d7d69d 572 hdmi_ai->checksum = -sum;
079d88cc
WF		 573}
574
575static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
576 hda_nid_t pin_nid,
53d7d69d 577 u8 *dip, int size)
079d88cc 578{
079d88cc
WF		 579 int i;
580
581 hdmi_debug_dip_size(codec, pin_nid);
582 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
583
079d88cc 584 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 585 for (i = 0; i < size; i++)
586 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 587}
588
589static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 590 u8 *dip, int size)
079d88cc 591{
079d88cc
WF		 592 u8 val;
593 int i;
594
595 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
596 != AC_DIPXMIT_BEST)
597 return false;
598
599 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 600 for (i = 0; i < size; i++) {
079d88cc
WF		 601 val = snd_hda_codec_read(codec, pin_nid, 0,
602 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 603 if (val != dip[i])
079d88cc
WF		 604 return false;
605 }
606
607 return true;
608}
609
610static void hdmi_setup_audio_infoframe(struct hda_codec *codec, hda_nid_t nid,
611 struct snd_pcm_substream *substream)
612{
613 struct hdmi_spec *spec = codec->spec;
614 hda_nid_t pin_nid;
53d7d69d
WF		 615 int channels = substream->runtime->channels;
616 int ca;
079d88cc 617 int i;
53d7d69d
WF		 618 u8 ai[max(sizeof(struct hdmi_audio_infoframe),
619 sizeof(struct dp_audio_infoframe))];
079d88cc 620
53d7d69d 621 ca = hdmi_channel_allocation(codec, nid, channels);
079d88cc
WF		 622
623 for (i = 0; i < spec->num_pins; i++) {
624 if (spec->pin_cvt[i] != nid)
625 continue;
626 if (!spec->sink_eld[i].monitor_present)
627 continue;
628
629 pin_nid = spec->pin[i];
53d7d69d
WF		 630
631 memset(ai, 0, sizeof(ai));
632 if (spec->sink_eld[i].conn_type == 0) { /* HDMI */
633 struct hdmi_audio_infoframe *hdmi_ai;
634
635 hdmi_ai = (struct hdmi_audio_infoframe *)ai;
636 hdmi_ai->type = 0x84;
637 hdmi_ai->ver = 0x01;
638 hdmi_ai->len = 0x0a;
639 hdmi_ai->CC02_CT47 = channels - 1;
640 hdmi_checksum_audio_infoframe(hdmi_ai);
641 } else if (spec->sink_eld[i].conn_type == 1) { /* DisplayPort */
642 struct dp_audio_infoframe *dp_ai;
643
644 dp_ai = (struct dp_audio_infoframe *)ai;
645 dp_ai->type = 0x84;
646 dp_ai->len = 0x1b;
647 dp_ai->ver = 0x11 << 2;
648 dp_ai->CC02_CT47 = channels - 1;
649 } else {
650 snd_printd("HDMI: unknown connection type at pin %d\n",
651 pin_nid);
652 continue;
653 }
654
655 /*
656 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
657 * sizeof(*dp_ai) to avoid partial match/update problems when
658 * the user switches between HDMI/DP monitors.
659 */
660 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai, sizeof(ai))) {
2abbf439
WF		 661 snd_printdd("hdmi_setup_audio_infoframe: "
662 "cvt=%d pin=%d channels=%d\n",
663 nid, pin_nid,
53d7d69d
WF		 664 channels);
665 hdmi_setup_channel_mapping(codec, pin_nid, ca);
079d88cc 666 hdmi_stop_infoframe_trans(codec, pin_nid);
53d7d69d
WF		 667 hdmi_fill_audio_infoframe(codec, pin_nid,
668 ai, sizeof(ai));
079d88cc
WF		 669 hdmi_start_infoframe_trans(codec, pin_nid);
670 }
671 }
672}
673
674
675/*
676 * Unsolicited events
677 */
678
38faddb1
TI		 679static void hdmi_present_sense(struct hda_codec *codec, hda_nid_t pin_nid,
680 struct hdmi_eld *eld);
681
079d88cc
WF		 682static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
683{
684 struct hdmi_spec *spec = codec->spec;
685 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
686 int pind = !!(res & AC_UNSOL_RES_PD);
687 int eldv = !!(res & AC_UNSOL_RES_ELDV);
688 int index;
689
690 printk(KERN_INFO
691 "HDMI hot plug event: Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
692 tag, pind, eldv);
693
694 index = hda_node_index(spec->pin, tag);
695 if (index < 0)
696 return;
697
38faddb1
TI		 698 if (spec->old_pin_detect) {
699 if (pind)
700 hdmi_present_sense(codec, tag, &spec->sink_eld[index]);
701 pind = spec->sink_eld[index].monitor_present;
702 }
703
079d88cc
WF		 704 spec->sink_eld[index].monitor_present = pind;
705 spec->sink_eld[index].eld_valid = eldv;
706
707 if (pind && eldv) {
708 hdmi_get_show_eld(codec, spec->pin[index],
709 &spec->sink_eld[index]);
710 /* TODO: do real things about ELD */
711 }
712}
713
714static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
715{
716 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
717 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
718 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
719 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
720
721 printk(KERN_INFO
722 "HDMI CP event: PIN=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
723 tag,
724 subtag,
725 cp_state,
726 cp_ready);
727
728 /* TODO */
729 if (cp_state)
730 ;
731 if (cp_ready)
732 ;
733}
734
735
736static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
737{
738 struct hdmi_spec *spec = codec->spec;
739 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
740 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
741
742 if (hda_node_index(spec->pin, tag) < 0) {
743 snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag);
744 return;
745 }
746
747 if (subtag == 0)
748 hdmi_intrinsic_event(codec, res);
749 else
750 hdmi_non_intrinsic_event(codec, res);
751}
752
753/*
754 * Callbacks
755 */
756
92f10b3f
TI		 757/* HBR should be Non-PCM, 8 channels */
758#define is_hbr_format(format) \
759 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
760
ea87d1c4 761static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t nid,
079d88cc
WF		 762 u32 stream_tag, int format)
763{
ea87d1c4 764 struct hdmi_spec *spec = codec->spec;
ea87d1c4
AH		 765 int pinctl;
766 int new_pinctl = 0;
767 int i;
768
769 for (i = 0; i < spec->num_pins; i++) {
770 if (spec->pin_cvt[i] != nid)
771 continue;
772 if (!(snd_hda_query_pin_caps(codec, spec->pin[i]) & AC_PINCAP_HBR))
773 continue;
774
775 pinctl = snd_hda_codec_read(codec, spec->pin[i], 0,
776 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
777
778 new_pinctl = pinctl & ~AC_PINCTL_EPT;
92f10b3f 779 if (is_hbr_format(format))
ea87d1c4
AH		 780 new_pinctl |= AC_PINCTL_EPT_HBR;
781 else
782 new_pinctl |= AC_PINCTL_EPT_NATIVE;
783
784 snd_printdd("hdmi_setup_stream: "
785 "NID=0x%x, %spinctl=0x%x\n",
786 spec->pin[i],
787 pinctl == new_pinctl ? "" : "new-",
788 new_pinctl);
789
790 if (pinctl != new_pinctl)
791 snd_hda_codec_write(codec, spec->pin[i], 0,
792 AC_VERB_SET_PIN_WIDGET_CONTROL,
793 new_pinctl);
794 }
795
92f10b3f 796 if (is_hbr_format(format) && !new_pinctl) {
ea87d1c4
AH		 797 snd_printdd("hdmi_setup_stream: HBR is not supported\n");
798 return -EINVAL;
799 }
079d88cc 800
4f347607 801 snd_hda_codec_setup_stream(codec, nid, stream_tag, 0, format);
ea87d1c4 802 return 0;
079d88cc
WF		 803}
804
bbbe3390
TI		 805/*
806 * HDA PCM callbacks
807 */
808static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
809 struct hda_codec *codec,
810 struct snd_pcm_substream *substream)
811{
812 struct hdmi_spec *spec = codec->spec;
813 struct hdmi_eld *eld;
814 struct hda_pcm_stream *codec_pars;
815 unsigned int idx;
816
817 for (idx = 0; idx < spec->num_cvts; idx++)
818 if (hinfo->nid == spec->cvt[idx])
819 break;
820 if (snd_BUG_ON(idx >= spec->num_cvts) ||
821 snd_BUG_ON(idx >= spec->num_pins))
822 return -EINVAL;
823
824 /* save the PCM info the codec provides */
825 codec_pars = &spec->codec_pcm_pars[idx];
826 if (!codec_pars->rates)
827 *codec_pars = *hinfo;
828
829 eld = &spec->sink_eld[idx];
830 if (eld->sad_count > 0) {
831 hdmi_eld_update_pcm_info(eld, hinfo, codec_pars);
832 if (hinfo->channels_min > hinfo->channels_max ||
833 !hinfo->rates || !hinfo->formats)
834 return -ENODEV;
835 } else {
836 /* fallback to the codec default */
bbbe3390
TI		 837 hinfo->channels_max = codec_pars->channels_max;
838 hinfo->rates = codec_pars->rates;
839 hinfo->formats = codec_pars->formats;
840 hinfo->maxbps = codec_pars->maxbps;
841 }
842 return 0;
843}
844
079d88cc
WF		 845/*
846 * HDA/HDMI auto parsing
847 */
079d88cc
WF		 848static int hdmi_read_pin_conn(struct hda_codec *codec, hda_nid_t pin_nid)
849{
850 struct hdmi_spec *spec = codec->spec;
851 hda_nid_t conn_list[HDA_MAX_CONNECTIONS];
852 int conn_len, curr;
853 int index;
854
855 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
856 snd_printk(KERN_WARNING
857 "HDMI: pin %d wcaps %#x "
858 "does not support connection list\n",
859 pin_nid, get_wcaps(codec, pin_nid));
860 return -EINVAL;
861 }
862
863 conn_len = snd_hda_get_connections(codec, pin_nid, conn_list,
864 HDA_MAX_CONNECTIONS);
865 if (conn_len > 1)
866 curr = snd_hda_codec_read(codec, pin_nid, 0,
867 AC_VERB_GET_CONNECT_SEL, 0);
868 else
869 curr = 0;
870
871 index = hda_node_index(spec->pin, pin_nid);
872 if (index < 0)
873 return -EINVAL;
874
875 spec->pin_cvt[index] = conn_list[curr];
876
877 return 0;
878}
879
880static void hdmi_present_sense(struct hda_codec *codec, hda_nid_t pin_nid,
881 struct hdmi_eld *eld)
882{
883 int present = snd_hda_pin_sense(codec, pin_nid);
884
885 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
886 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
887
888 if (present & AC_PINSENSE_ELDV)
889 hdmi_get_show_eld(codec, pin_nid, eld);
890}
891
892static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
893{
894 struct hdmi_spec *spec = codec->spec;
895
896 if (spec->num_pins >= MAX_HDMI_PINS) {
897 snd_printk(KERN_WARNING
898 "HDMI: no space for pin %d\n", pin_nid);
3eaead57 899 return -E2BIG;
079d88cc
WF		 900 }
901
902 hdmi_present_sense(codec, pin_nid, &spec->sink_eld[spec->num_pins]);
903
904 spec->pin[spec->num_pins] = pin_nid;
905 spec->num_pins++;
906
907 /*
908 * It is assumed that converter nodes come first in the node list and
909 * hence have been registered and usable now.
910 */
911 return hdmi_read_pin_conn(codec, pin_nid);
912}
913
914static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t nid)
915{
916 struct hdmi_spec *spec = codec->spec;
917
918 if (spec->num_cvts >= MAX_HDMI_CVTS) {
919 snd_printk(KERN_WARNING
920 "HDMI: no space for converter %d\n", nid);
3eaead57 921 return -E2BIG;
079d88cc
WF		 922 }
923
924 spec->cvt[spec->num_cvts] = nid;
925 spec->num_cvts++;
926
927 return 0;
928}
929
930static int hdmi_parse_codec(struct hda_codec *codec)
931{
932 hda_nid_t nid;
933 int i, nodes;
934
935 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
936 if (!nid || nodes < 0) {
937 snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n");
938 return -EINVAL;
939 }
940
941 for (i = 0; i < nodes; i++, nid++) {
942 unsigned int caps;
943 unsigned int type;
944
945 caps = snd_hda_param_read(codec, nid, AC_PAR_AUDIO_WIDGET_CAP);
946 type = get_wcaps_type(caps);
947
948 if (!(caps & AC_WCAP_DIGITAL))
949 continue;
950
951 switch (type) {
952 case AC_WID_AUD_OUT:
3eaead57 953 hdmi_add_cvt(codec, nid);
079d88cc
WF		 954 break;
955 case AC_WID_PIN:
956 caps = snd_hda_param_read(codec, nid, AC_PAR_PIN_CAP);
957 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
958 continue;
3eaead57 959 hdmi_add_pin(codec, nid);
079d88cc
WF		 960 break;
961 }
962 }
963
964 /*
965 * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event
966 * can be lost and presence sense verb will become inaccurate if the
967 * HDA link is powered off at hot plug or hw initialization time.
968 */
969#ifdef CONFIG_SND_HDA_POWER_SAVE
970 if (!(snd_hda_param_read(codec, codec->afg, AC_PAR_POWER_STATE) &
971 AC_PWRST_EPSS))
972 codec->bus->power_keep_link_on = 1;
973#endif
974
975 return 0;
976}
977
84eb01be
TI		 978/*
979 */
980static char *generic_hdmi_pcm_names[MAX_HDMI_CVTS] = {
981 "HDMI 0",
982 "HDMI 1",
983 "HDMI 2",
984};
985
986/*
987 * HDMI callbacks
988 */
989
990static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
991 struct hda_codec *codec,
992 unsigned int stream_tag,
993 unsigned int format,
994 struct snd_pcm_substream *substream)
995{
996 hdmi_set_channel_count(codec, hinfo->nid,
997 substream->runtime->channels);
998
999 hdmi_setup_audio_infoframe(codec, hinfo->nid, substream);
1000
1001 return hdmi_setup_stream(codec, hinfo->nid, stream_tag, format);
1002}
1003
1004static struct hda_pcm_stream generic_hdmi_pcm_playback = {
1005 .substreams = 1,
1006 .channels_min = 2,
1007 .ops = {
1008 .open = hdmi_pcm_open,
1009 .prepare = generic_hdmi_playback_pcm_prepare,
1010 },
1011};
1012
1013static int generic_hdmi_build_pcms(struct hda_codec *codec)
1014{
1015 struct hdmi_spec *spec = codec->spec;
1016 struct hda_pcm *info = spec->pcm_rec;
1017 int i;
1018
1019 codec->num_pcms = spec->num_cvts;
1020 codec->pcm_info = info;
1021
1022 for (i = 0; i < codec->num_pcms; i++, info++) {
1023 unsigned int chans;
1024 struct hda_pcm_stream *pstr;
1025
1026 chans = get_wcaps(codec, spec->cvt[i]);
1027 chans = get_wcaps_channels(chans);
1028
1029 info->name = generic_hdmi_pcm_names[i];
1030 info->pcm_type = HDA_PCM_TYPE_HDMI;
1031 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
1032 if (spec->pcm_playback)
1033 *pstr = *spec->pcm_playback;
1034 else
1035 *pstr = generic_hdmi_pcm_playback;
1036 pstr->nid = spec->cvt[i];
1037 if (pstr->channels_max <= 2 && chans && chans <= 16)
1038 pstr->channels_max = chans;
1039 }
1040
1041 return 0;
1042}
1043
1044static int generic_hdmi_build_controls(struct hda_codec *codec)
1045{
1046 struct hdmi_spec *spec = codec->spec;
1047 int err;
1048 int i;
1049
1050 for (i = 0; i < codec->num_pcms; i++) {
1051 err = snd_hda_create_spdif_out_ctls(codec, spec->cvt[i]);
1052 if (err < 0)
1053 return err;
1054 }
1055
1056 return 0;
1057}
1058
1059static int generic_hdmi_init(struct hda_codec *codec)
1060{
1061 struct hdmi_spec *spec = codec->spec;
1062 int i;
1063
1064 for (i = 0; spec->pin[i]; i++) {
1065 hdmi_enable_output(codec, spec->pin[i]);
1066 snd_hda_codec_write(codec, spec->pin[i], 0,
1067 AC_VERB_SET_UNSOLICITED_ENABLE,
1068 AC_USRSP_EN | spec->pin[i]);
1069 }
1070 return 0;
1071}
1072
1073static void generic_hdmi_free(struct hda_codec *codec)
1074{
1075 struct hdmi_spec *spec = codec->spec;
1076 int i;
1077
1078 for (i = 0; i < spec->num_pins; i++)
1079 snd_hda_eld_proc_free(codec, &spec->sink_eld[i]);
1080
1081 kfree(spec);
1082}
1083
1084static struct hda_codec_ops generic_hdmi_patch_ops = {
1085 .init = generic_hdmi_init,
1086 .free = generic_hdmi_free,
1087 .build_pcms = generic_hdmi_build_pcms,
1088 .build_controls = generic_hdmi_build_controls,
1089 .unsol_event = hdmi_unsol_event,
1090};
1091
1092static int patch_generic_hdmi(struct hda_codec *codec)
1093{
1094 struct hdmi_spec *spec;
1095 int i;
1096
1097 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1098 if (spec == NULL)
1099 return -ENOMEM;
1100
1101 codec->spec = spec;
1102 if (hdmi_parse_codec(codec) < 0) {
1103 codec->spec = NULL;
1104 kfree(spec);
1105 return -EINVAL;
1106 }
1107 codec->patch_ops = generic_hdmi_patch_ops;
1108
1109 for (i = 0; i < spec->num_pins; i++)
1110 snd_hda_eld_proc_new(codec, &spec->sink_eld[i], i);
1111
1112 init_channel_allocations();
1113
1114 return 0;
1115}
1116
1117/*
1118 * Nvidia specific implementations
1119 */
1120
1121#define Nv_VERB_SET_Channel_Allocation 0xF79
1122#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
1123#define Nv_VERB_SET_Audio_Protection_On 0xF98
1124#define Nv_VERB_SET_Audio_Protection_Off 0xF99
1125
1126#define nvhdmi_master_con_nid_7x 0x04
1127#define nvhdmi_master_pin_nid_7x 0x05
1128
1129static hda_nid_t nvhdmi_con_nids_7x[4] = {
1130 /*front, rear, clfe, rear_surr */
1131 0x6, 0x8, 0xa, 0xc,
1132};
1133
1134static struct hda_verb nvhdmi_basic_init_7x[] = {
1135 /* set audio protect on */
1136 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
1137 /* enable digital output on pin widget */
1138 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1139 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1140 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1141 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1142 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1143 {} /* terminator */
1144};
1145
1146#ifdef LIMITED_RATE_FMT_SUPPORT
1147/* support only the safe format and rate */
1148#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
1149#define SUPPORTED_MAXBPS 16
1150#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1151#else
1152/* support all rates and formats */
1153#define SUPPORTED_RATES \
1154 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
1155 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
1156 SNDRV_PCM_RATE_192000)
1157#define SUPPORTED_MAXBPS 24
1158#define SUPPORTED_FORMATS \
1159 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
1160#endif
1161
1162static int nvhdmi_7x_init(struct hda_codec *codec)
1163{
1164 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x);
1165 return 0;
1166}
1167
1168static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
1169 struct hda_codec *codec,
1170 struct snd_pcm_substream *substream)
1171{
1172 struct hdmi_spec *spec = codec->spec;
1173 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
1174}
1175
1176static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
1177 struct hda_codec *codec,
1178 struct snd_pcm_substream *substream)
1179{
1180 struct hdmi_spec *spec = codec->spec;
1181 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
1182}
1183
1184static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1185 struct hda_codec *codec,
1186 unsigned int stream_tag,
1187 unsigned int format,
1188 struct snd_pcm_substream *substream)
1189{
1190 struct hdmi_spec *spec = codec->spec;
1191 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
1192 stream_tag, format, substream);
1193}
1194
1195static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
1196 struct hda_codec *codec,
1197 struct snd_pcm_substream *substream)
1198{
1199 struct hdmi_spec *spec = codec->spec;
1200 int i;
1201
1202 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
1203 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
1204 for (i = 0; i < 4; i++) {
1205 /* set the stream id */
1206 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
1207 AC_VERB_SET_CHANNEL_STREAMID, 0);
1208 /* set the stream format */
1209 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
1210 AC_VERB_SET_STREAM_FORMAT, 0);
1211 }
1212
1213 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
1214}
1215
1216static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
1217 struct hda_codec *codec,
1218 unsigned int stream_tag,
1219 unsigned int format,
1220 struct snd_pcm_substream *substream)
1221{
1222 int chs;
1223 unsigned int dataDCC1, dataDCC2, chan, chanmask, channel_id;
1224 int i;
1225
1226 mutex_lock(&codec->spdif_mutex);
1227
1228 chs = substream->runtime->channels;
1229 chan = chs ? (chs - 1) : 1;
1230
1231 switch (chs) {
1232 default:
1233 case 0:
1234 case 2:
1235 chanmask = 0x00;
1236 break;
1237 case 4:
1238 chanmask = 0x08;
1239 break;
1240 case 6:
1241 chanmask = 0x0b;
1242 break;
1243 case 8:
1244 chanmask = 0x13;
1245 break;
1246 }
1247 dataDCC1 = AC_DIG1_ENABLE | AC_DIG1_COPYRIGHT;
1248 dataDCC2 = 0x2;
1249
1250 /* set the Audio InforFrame Channel Allocation */
1251 snd_hda_codec_write(codec, 0x1, 0,
1252 Nv_VERB_SET_Channel_Allocation, chanmask);
1253
1254 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
1255 if (codec->spdif_status_reset && (codec->spdif_ctls & AC_DIG1_ENABLE))
1256 snd_hda_codec_write(codec,
1257 nvhdmi_master_con_nid_7x,
1258 0,
1259 AC_VERB_SET_DIGI_CONVERT_1,
1260 codec->spdif_ctls & ~AC_DIG1_ENABLE & 0xff);
1261
1262 /* set the stream id */
1263 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
1264 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
1265
1266 /* set the stream format */
1267 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
1268 AC_VERB_SET_STREAM_FORMAT, format);
1269
1270 /* turn on again (if needed) */
1271 /* enable and set the channel status audio/data flag */
1272 if (codec->spdif_status_reset && (codec->spdif_ctls & AC_DIG1_ENABLE)) {
1273 snd_hda_codec_write(codec,
1274 nvhdmi_master_con_nid_7x,
1275 0,
1276 AC_VERB_SET_DIGI_CONVERT_1,
1277 codec->spdif_ctls & 0xff);
1278 snd_hda_codec_write(codec,
1279 nvhdmi_master_con_nid_7x,
1280 0,
1281 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
1282 }
1283
1284 for (i = 0; i < 4; i++) {
1285 if (chs == 2)
1286 channel_id = 0;
1287 else
1288 channel_id = i * 2;
1289
1290 /* turn off SPDIF once;
1291 *otherwise the IEC958 bits won't be updated
1292 */
1293 if (codec->spdif_status_reset &&
1294 (codec->spdif_ctls & AC_DIG1_ENABLE))
1295 snd_hda_codec_write(codec,
1296 nvhdmi_con_nids_7x[i],
1297 0,
1298 AC_VERB_SET_DIGI_CONVERT_1,
1299 codec->spdif_ctls & ~AC_DIG1_ENABLE & 0xff);
1300 /* set the stream id */
1301 snd_hda_codec_write(codec,
1302 nvhdmi_con_nids_7x[i],
1303 0,
1304 AC_VERB_SET_CHANNEL_STREAMID,
1305 (stream_tag << 4) | channel_id);
1306 /* set the stream format */
1307 snd_hda_codec_write(codec,
1308 nvhdmi_con_nids_7x[i],
1309 0,
1310 AC_VERB_SET_STREAM_FORMAT,
1311 format);
1312 /* turn on again (if needed) */
1313 /* enable and set the channel status audio/data flag */
1314 if (codec->spdif_status_reset &&
1315 (codec->spdif_ctls & AC_DIG1_ENABLE)) {
1316 snd_hda_codec_write(codec,
1317 nvhdmi_con_nids_7x[i],
1318 0,
1319 AC_VERB_SET_DIGI_CONVERT_1,
1320 codec->spdif_ctls & 0xff);
1321 snd_hda_codec_write(codec,
1322 nvhdmi_con_nids_7x[i],
1323 0,
1324 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
1325 }
1326 }
1327
1328 /* set the Audio Info Frame Checksum */
1329 snd_hda_codec_write(codec, 0x1, 0,
1330 Nv_VERB_SET_Info_Frame_Checksum,
1331 (0x71 - chan - chanmask));
1332
1333 mutex_unlock(&codec->spdif_mutex);
1334 return 0;
1335}
1336
1337static struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
1338 .substreams = 1,
1339 .channels_min = 2,
1340 .channels_max = 8,
1341 .nid = nvhdmi_master_con_nid_7x,
1342 .rates = SUPPORTED_RATES,
1343 .maxbps = SUPPORTED_MAXBPS,
1344 .formats = SUPPORTED_FORMATS,
1345 .ops = {
1346 .open = simple_playback_pcm_open,
1347 .close = nvhdmi_8ch_7x_pcm_close,
1348 .prepare = nvhdmi_8ch_7x_pcm_prepare
1349 },
1350};
1351
1352static struct hda_pcm_stream nvhdmi_pcm_playback_2ch = {
1353 .substreams = 1,
1354 .channels_min = 2,
1355 .channels_max = 2,
1356 .nid = nvhdmi_master_con_nid_7x,
1357 .rates = SUPPORTED_RATES,
1358 .maxbps = SUPPORTED_MAXBPS,
1359 .formats = SUPPORTED_FORMATS,
1360 .ops = {
1361 .open = simple_playback_pcm_open,
1362 .close = simple_playback_pcm_close,
1363 .prepare = simple_playback_pcm_prepare
1364 },
1365};
1366
1367static struct hda_codec_ops nvhdmi_patch_ops_8ch_7x = {
1368 .build_controls = generic_hdmi_build_controls,
1369 .build_pcms = generic_hdmi_build_pcms,
1370 .init = nvhdmi_7x_init,
1371 .free = generic_hdmi_free,
1372};
1373
1374static struct hda_codec_ops nvhdmi_patch_ops_2ch = {
1375 .build_controls = generic_hdmi_build_controls,
1376 .build_pcms = generic_hdmi_build_pcms,
1377 .init = nvhdmi_7x_init,
1378 .free = generic_hdmi_free,
1379};
1380
1381static int patch_nvhdmi_8ch_89(struct hda_codec *codec)
1382{
1383 struct hdmi_spec *spec;
1384 int err = patch_generic_hdmi(codec);
1385
1386 if (err < 0)
1387 return err;
1388 spec = codec->spec;
1389 spec->old_pin_detect = 1;
1390 return 0;
1391}
1392
1393static int patch_nvhdmi_2ch(struct hda_codec *codec)
1394{
1395 struct hdmi_spec *spec;
1396
1397 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1398 if (spec == NULL)
1399 return -ENOMEM;
1400
1401 codec->spec = spec;
1402
1403 spec->multiout.num_dacs = 0; /* no analog */
1404 spec->multiout.max_channels = 2;
1405 spec->multiout.dig_out_nid = nvhdmi_master_con_nid_7x;
1406 spec->old_pin_detect = 1;
1407 spec->num_cvts = 1;
1408 spec->cvt[0] = nvhdmi_master_con_nid_7x;
1409 spec->pcm_playback = &nvhdmi_pcm_playback_2ch;
1410
1411 codec->patch_ops = nvhdmi_patch_ops_2ch;
1412
1413 return 0;
1414}
1415
1416static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
1417{
1418 struct hdmi_spec *spec;
1419 int err = patch_nvhdmi_2ch(codec);
1420
1421 if (err < 0)
1422 return err;
1423 spec = codec->spec;
1424 spec->multiout.max_channels = 8;
1425 spec->pcm_playback = &nvhdmi_pcm_playback_8ch_7x;
1426 codec->patch_ops = nvhdmi_patch_ops_8ch_7x;
1427 return 0;
1428}
1429
1430/*
1431 * ATI-specific implementations
1432 *
1433 * FIXME: we may omit the whole this and use the generic code once after
1434 * it's confirmed to work.
1435 */
1436
1437#define ATIHDMI_CVT_NID 0x02 /* audio converter */
1438#define ATIHDMI_PIN_NID 0x03 /* HDMI output pin */
1439
1440static int atihdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1441 struct hda_codec *codec,
1442 unsigned int stream_tag,
1443 unsigned int format,
1444 struct snd_pcm_substream *substream)
1445{
1446 struct hdmi_spec *spec = codec->spec;
1447 int chans = substream->runtime->channels;
1448 int i, err;
1449
1450 err = simple_playback_pcm_prepare(hinfo, codec, stream_tag, format,
1451 substream);
1452 if (err < 0)
1453 return err;
1454 snd_hda_codec_write(codec, spec->cvt[0], 0, AC_VERB_SET_CVT_CHAN_COUNT,
1455 chans - 1);
1456 /* FIXME: XXX */
1457 for (i = 0; i < chans; i++) {
1458 snd_hda_codec_write(codec, spec->cvt[0], 0,
1459 AC_VERB_SET_HDMI_CHAN_SLOT,
1460 (i << 4) | i);
1461 }
1462 return 0;
1463}
1464
1465static struct hda_pcm_stream atihdmi_pcm_digital_playback = {
1466 .substreams = 1,
1467 .channels_min = 2,
1468 .channels_max = 2,
1469 .nid = ATIHDMI_CVT_NID,
1470 .ops = {
1471 .open = simple_playback_pcm_open,
1472 .close = simple_playback_pcm_close,
1473 .prepare = atihdmi_playback_pcm_prepare
1474 },
1475};
1476
1477static struct hda_verb atihdmi_basic_init[] = {
1478 /* enable digital output on pin widget */
1479 { 0x03, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT },
1480 {} /* terminator */
1481};
1482
1483static int atihdmi_init(struct hda_codec *codec)
1484{
1485 struct hdmi_spec *spec = codec->spec;
1486
1487 snd_hda_sequence_write(codec, atihdmi_basic_init);
1488 /* SI codec requires to unmute the pin */
1489 if (get_wcaps(codec, spec->pin[0]) & AC_WCAP_OUT_AMP)
1490 snd_hda_codec_write(codec, spec->pin[0], 0,
1491 AC_VERB_SET_AMP_GAIN_MUTE,
1492 AMP_OUT_UNMUTE);
1493 return 0;
1494}
1495
1496static struct hda_codec_ops atihdmi_patch_ops = {
1497 .build_controls = generic_hdmi_build_controls,
1498 .build_pcms = generic_hdmi_build_pcms,
1499 .init = atihdmi_init,
1500 .free = generic_hdmi_free,
1501};
1502
1503
1504static int patch_atihdmi(struct hda_codec *codec)
1505{
1506 struct hdmi_spec *spec;
1507
1508 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1509 if (spec == NULL)
1510 return -ENOMEM;
1511
1512 codec->spec = spec;
1513
1514 spec->multiout.num_dacs = 0; /* no analog */
1515 spec->multiout.max_channels = 2;
1516 spec->multiout.dig_out_nid = ATIHDMI_CVT_NID;
1517 spec->num_cvts = 1;
1518 spec->cvt[0] = ATIHDMI_CVT_NID;
1519 spec->pin[0] = ATIHDMI_PIN_NID;
1520 spec->pcm_playback = &atihdmi_pcm_digital_playback;
1521
1522 codec->patch_ops = atihdmi_patch_ops;
1523
1524 return 0;
1525}
1526
1527
1528/*
1529 * patch entries
1530 */
1531static struct hda_codec_preset snd_hda_preset_hdmi[] = {
1532{ .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
1533{ .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
1534{ .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
36e9c135 1535{ .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 1536{ .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
1537{ .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
1538{ .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
1539{ .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1540{ .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1541{ .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1542{ .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1543{ .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
1544{ .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1545{ .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1546{ .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_nvhdmi_8ch_89 },
1547{ .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1548{ .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1549{ .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1550{ .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1551{ .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1552{ .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1553{ .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1554{ .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1555{ .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1556{ .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1557{ .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1558{ .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1559{ .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1560{ .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1561{ .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1562{ .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1563{ .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
1564{ .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
1565{ .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
1566{ .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
1567{ .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
1568{ .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
1569{ .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
1570{ .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
1571{ .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
1572{} /* terminator */
1573};
1574
1575MODULE_ALIAS("snd-hda-codec-id:1002793c");
1576MODULE_ALIAS("snd-hda-codec-id:10027919");
1577MODULE_ALIAS("snd-hda-codec-id:1002791a");
1578MODULE_ALIAS("snd-hda-codec-id:1002aa01");
1579MODULE_ALIAS("snd-hda-codec-id:10951390");
1580MODULE_ALIAS("snd-hda-codec-id:10951392");
1581MODULE_ALIAS("snd-hda-codec-id:10de0002");
1582MODULE_ALIAS("snd-hda-codec-id:10de0003");
1583MODULE_ALIAS("snd-hda-codec-id:10de0005");
1584MODULE_ALIAS("snd-hda-codec-id:10de0006");
1585MODULE_ALIAS("snd-hda-codec-id:10de0007");
1586MODULE_ALIAS("snd-hda-codec-id:10de000a");
1587MODULE_ALIAS("snd-hda-codec-id:10de000b");
1588MODULE_ALIAS("snd-hda-codec-id:10de000c");
1589MODULE_ALIAS("snd-hda-codec-id:10de000d");
1590MODULE_ALIAS("snd-hda-codec-id:10de0010");
1591MODULE_ALIAS("snd-hda-codec-id:10de0011");
1592MODULE_ALIAS("snd-hda-codec-id:10de0012");
1593MODULE_ALIAS("snd-hda-codec-id:10de0013");
1594MODULE_ALIAS("snd-hda-codec-id:10de0014");
1595MODULE_ALIAS("snd-hda-codec-id:10de0018");
1596MODULE_ALIAS("snd-hda-codec-id:10de0019");
1597MODULE_ALIAS("snd-hda-codec-id:10de001a");
1598MODULE_ALIAS("snd-hda-codec-id:10de001b");
1599MODULE_ALIAS("snd-hda-codec-id:10de001c");
1600MODULE_ALIAS("snd-hda-codec-id:10de0040");
1601MODULE_ALIAS("snd-hda-codec-id:10de0041");
1602MODULE_ALIAS("snd-hda-codec-id:10de0042");
1603MODULE_ALIAS("snd-hda-codec-id:10de0043");
1604MODULE_ALIAS("snd-hda-codec-id:10de0044");
1605MODULE_ALIAS("snd-hda-codec-id:10de0067");
1606MODULE_ALIAS("snd-hda-codec-id:10de8001");
1607MODULE_ALIAS("snd-hda-codec-id:17e80047");
1608MODULE_ALIAS("snd-hda-codec-id:80860054");
1609MODULE_ALIAS("snd-hda-codec-id:80862801");
1610MODULE_ALIAS("snd-hda-codec-id:80862802");
1611MODULE_ALIAS("snd-hda-codec-id:80862803");
1612MODULE_ALIAS("snd-hda-codec-id:80862804");
1613MODULE_ALIAS("snd-hda-codec-id:80862805");
1614MODULE_ALIAS("snd-hda-codec-id:808629fb");
1615
1616MODULE_LICENSE("GPL");
1617MODULE_DESCRIPTION("HDMI HD-audio codec");
1618MODULE_ALIAS("snd-hda-codec-intelhdmi");
1619MODULE_ALIAS("snd-hda-codec-nvhdmi");
1620MODULE_ALIAS("snd-hda-codec-atihdmi");
1621
1622static struct hda_codec_preset_list intel_list = {
1623 .preset = snd_hda_preset_hdmi,
1624 .owner = THIS_MODULE,
1625};
1626
1627static int __init patch_hdmi_init(void)
1628{
1629 return snd_hda_add_codec_preset(&intel_list);
1630}
1631
1632static void __exit patch_hdmi_exit(void)
1633{
1634 snd_hda_delete_codec_preset(&intel_list);
1635}
1636
1637module_init(patch_hdmi_init)
1638module_exit(patch_hdmi_exit)
Linux kernel - Deliverables
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