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ALSA: hda - Add inverted digital mic fixup for Acer Aspire One
[deliverable/linux.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
079d88cc
WF		 9 *
10 * Authors:
11 * Wu Fengguang <wfg@linux.intel.com>
12 *
13 * Maintained by:
14 * Wu Fengguang <wfg@linux.intel.com>
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the Free
18 * Software Foundation; either version 2 of the License, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful, but
22 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
23 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 * for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software Foundation,
28 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
84eb01be
TI		 31#include <linux/init.h>
32#include <linux/delay.h>
33#include <linux/slab.h>
65a77217 34#include <linux/module.h>
84eb01be 35#include <sound/core.h>
07acecc1 36#include <sound/jack.h>
433968da 37#include <sound/asoundef.h>
d45e6889 38#include <sound/tlv.h>
84eb01be
TI		 39#include "hda_codec.h"
40#include "hda_local.h"
1835a0f9 41#include "hda_jack.h"
84eb01be 42
0ebaa24c
TI		 43static bool static_hdmi_pcm;
44module_param(static_hdmi_pcm, bool, 0644);
45MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
46
384a48d7
SW		 47struct hdmi_spec_per_cvt {
48 hda_nid_t cvt_nid;
49 int assigned;
50 unsigned int channels_min;
51 unsigned int channels_max;
52 u32 rates;
53 u64 formats;
54 unsigned int maxbps;
55};
079d88cc 56
4eea3091
TI		 57/* max. connections to a widget */
58#define HDA_MAX_CONNECTIONS 32
59
384a48d7
SW		 60struct hdmi_spec_per_pin {
61 hda_nid_t pin_nid;
62 int num_mux_nids;
63 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
744626da
WF		 64
65 struct hda_codec *codec;
384a48d7 66 struct hdmi_eld sink_eld;
744626da 67 struct delayed_work work;
92c69e79 68 struct snd_kcontrol *eld_ctl;
c6e8453e 69 int repoll_count;
1a6003b5 70 bool non_pcm;
d45e6889
TI		 71 bool chmap_set; /* channel-map override by ALSA API? */
72 unsigned char chmap[8]; /* ALSA API channel-map */
bce0d2a8 73 char pcm_name[8]; /* filled in build_pcm callbacks */
384a48d7 74};
079d88cc 75
384a48d7
SW		 76struct hdmi_spec {
77 int num_cvts;
bce0d2a8
TI		 78 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
79 hda_nid_t cvt_nids[4]; /* only for haswell fix */
079d88cc 80
384a48d7 81 int num_pins;
bce0d2a8
TI		 82 struct snd_array pins; /* struct hdmi_spec_per_pin */
83 struct snd_array pcm_rec; /* struct hda_pcm */
d45e6889 84 unsigned int channels_max; /* max over all cvts */
079d88cc 85
4bd038f9 86 struct hdmi_eld temp_eld;
079d88cc 87 /*
384a48d7 88 * Non-generic ATI/NVIDIA specific
079d88cc
WF		 89 */
90 struct hda_multi_out multiout;
d0b1252d 91 struct hda_pcm_stream pcm_playback;
079d88cc
WF		 92};
93
94
95struct hdmi_audio_infoframe {
96 u8 type; /* 0x84 */
97 u8 ver; /* 0x01 */
98 u8 len; /* 0x0a */
99
53d7d69d
WF		 100 u8 checksum;
101
079d88cc
WF		 102 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
103 u8 SS01_SF24;
104 u8 CXT04;
105 u8 CA;
106 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 107};
108
109struct dp_audio_infoframe {
110 u8 type; /* 0x84 */
111 u8 len; /* 0x1b */
112 u8 ver; /* 0x11 << 2 */
113
114 u8 CC02_CT47; /* match with HDMI infoframe from this on */
115 u8 SS01_SF24;
116 u8 CXT04;
117 u8 CA;
118 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 119};
120
2b203dbb
TI		 121union audio_infoframe {
122 struct hdmi_audio_infoframe hdmi;
123 struct dp_audio_infoframe dp;
124 u8 bytes[0];
125};
126
079d88cc
WF		 127/*
128 * CEA speaker placement:
129 *
130 * FLH FCH FRH
131 * FLW FL FLC FC FRC FR FRW
132 *
133 * LFE
134 * TC
135 *
136 * RL RLC RC RRC RR
137 *
138 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
139 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
140 */
141enum cea_speaker_placement {
142 FL = (1 << 0), /* Front Left */
143 FC = (1 << 1), /* Front Center */
144 FR = (1 << 2), /* Front Right */
145 FLC = (1 << 3), /* Front Left Center */
146 FRC = (1 << 4), /* Front Right Center */
147 RL = (1 << 5), /* Rear Left */
148 RC = (1 << 6), /* Rear Center */
149 RR = (1 << 7), /* Rear Right */
150 RLC = (1 << 8), /* Rear Left Center */
151 RRC = (1 << 9), /* Rear Right Center */
152 LFE = (1 << 10), /* Low Frequency Effect */
153 FLW = (1 << 11), /* Front Left Wide */
154 FRW = (1 << 12), /* Front Right Wide */
155 FLH = (1 << 13), /* Front Left High */
156 FCH = (1 << 14), /* Front Center High */
157 FRH = (1 << 15), /* Front Right High */
158 TC = (1 << 16), /* Top Center */
159};
160
161/*
162 * ELD SA bits in the CEA Speaker Allocation data block
163 */
164static int eld_speaker_allocation_bits[] = {
165 [0] = FL | FR,
166 [1] = LFE,
167 [2] = FC,
168 [3] = RL | RR,
169 [4] = RC,
170 [5] = FLC | FRC,
171 [6] = RLC | RRC,
172 /* the following are not defined in ELD yet */
173 [7] = FLW | FRW,
174 [8] = FLH | FRH,
175 [9] = TC,
176 [10] = FCH,
177};
178
179struct cea_channel_speaker_allocation {
180 int ca_index;
181 int speakers[8];
182
183 /* derived values, just for convenience */
184 int channels;
185 int spk_mask;
186};
187
188/*
189 * ALSA sequence is:
190 *
191 * surround40 surround41 surround50 surround51 surround71
192 * ch0 front left = = = =
193 * ch1 front right = = = =
194 * ch2 rear left = = = =
195 * ch3 rear right = = = =
196 * ch4 LFE center center center
197 * ch5 LFE LFE
198 * ch6 side left
199 * ch7 side right
200 *
201 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
202 */
203static int hdmi_channel_mapping[0x32][8] = {
204 /* stereo */
205 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
206 /* 2.1 */
207 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
208 /* Dolby Surround */
209 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
210 /* surround40 */
211 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
212 /* 4ch */
213 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
214 /* surround41 */
9396d317 215 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
079d88cc
WF		 216 /* surround50 */
217 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
218 /* surround51 */
219 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
220 /* 7.1 */
221 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
222};
223
224/*
225 * This is an ordered list!
226 *
227 * The preceding ones have better chances to be selected by
53d7d69d 228 * hdmi_channel_allocation().
079d88cc
WF		 229 */
230static struct cea_channel_speaker_allocation channel_allocations[] = {
231/* channel: 7 6 5 4 3 2 1 0 */
232{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
233 /* 2.1 */
234{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
235 /* Dolby Surround */
236{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
237 /* surround40 */
238{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
239 /* surround41 */
240{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
241 /* surround50 */
242{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
243 /* surround51 */
244{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
245 /* 6.1 */
246{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
247 /* surround71 */
248{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
249
250{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
251{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
252{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
253{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
254{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
255{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
256{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
257{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
258{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
259{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
260{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
261{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
262{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
263{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
264{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
265{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
266{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
267{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
268{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
269{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
270{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
271{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
272{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
273{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
274{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
275{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
276{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
277{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
278{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
279{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
280{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
281{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
282{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
283{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
284{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
285{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
286{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
287{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
288{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
289{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
290{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
291};
292
293
294/*
295 * HDMI routines
296 */
297
bce0d2a8
TI		 298#define get_pin(spec, idx) \
299 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
300#define get_cvt(spec, idx) \
301 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
302#define get_pcm_rec(spec, idx) \
303 ((struct hda_pcm *)snd_array_elem(&spec->pcm_rec, idx))
304
384a48d7 305static int pin_nid_to_pin_index(struct hdmi_spec *spec, hda_nid_t pin_nid)
079d88cc 306{
384a48d7 307 int pin_idx;
079d88cc 308
384a48d7 309 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 310 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
384a48d7 311 return pin_idx;
079d88cc 312
384a48d7
SW		 313 snd_printk(KERN_WARNING "HDMI: pin nid %d not registered\n", pin_nid);
314 return -EINVAL;
315}
316
317static int hinfo_to_pin_index(struct hdmi_spec *spec,
318 struct hda_pcm_stream *hinfo)
319{
320 int pin_idx;
321
322 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 323 if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
384a48d7
SW		 324 return pin_idx;
325
326 snd_printk(KERN_WARNING "HDMI: hinfo %p not registered\n", hinfo);
327 return -EINVAL;
328}
329
330static int cvt_nid_to_cvt_index(struct hdmi_spec *spec, hda_nid_t cvt_nid)
331{
332 int cvt_idx;
333
334 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
bce0d2a8 335 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
384a48d7
SW		 336 return cvt_idx;
337
338 snd_printk(KERN_WARNING "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 339 return -EINVAL;
340}
341
14bc52b8
PLB		 342static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
343 struct snd_ctl_elem_info *uinfo)
344{
345 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9
DH		 346 struct hdmi_spec *spec = codec->spec;
347 struct hdmi_eld *eld;
14bc52b8
PLB		 348 int pin_idx;
349
14bc52b8
PLB		 350 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
351
352 pin_idx = kcontrol->private_value;
bce0d2a8 353 eld = &get_pin(spec, pin_idx)->sink_eld;
68e03de9 354
4bd038f9 355 mutex_lock(&eld->lock);
68e03de9 356 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
4bd038f9 357 mutex_unlock(&eld->lock);
14bc52b8
PLB		 358
359 return 0;
360}
361
362static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
363 struct snd_ctl_elem_value *ucontrol)
364{
365 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9
DH		 366 struct hdmi_spec *spec = codec->spec;
367 struct hdmi_eld *eld;
14bc52b8
PLB		 368 int pin_idx;
369
14bc52b8 370 pin_idx = kcontrol->private_value;
bce0d2a8 371 eld = &get_pin(spec, pin_idx)->sink_eld;
68e03de9 372
4bd038f9 373 mutex_lock(&eld->lock);
68e03de9 374 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) {
4bd038f9 375 mutex_unlock(&eld->lock);
68e03de9
DH		 376 snd_BUG();
377 return -EINVAL;
378 }
379
380 memset(ucontrol->value.bytes.data, 0,
381 ARRAY_SIZE(ucontrol->value.bytes.data));
382 if (eld->eld_valid)
383 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
384 eld->eld_size);
4bd038f9 385 mutex_unlock(&eld->lock);
14bc52b8
PLB		 386
387 return 0;
388}
389
390static struct snd_kcontrol_new eld_bytes_ctl = {
391 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
392 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
393 .name = "ELD",
394 .info = hdmi_eld_ctl_info,
395 .get = hdmi_eld_ctl_get,
396};
397
398static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
399 int device)
400{
401 struct snd_kcontrol *kctl;
402 struct hdmi_spec *spec = codec->spec;
403 int err;
404
405 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
406 if (!kctl)
407 return -ENOMEM;
408 kctl->private_value = pin_idx;
409 kctl->id.device = device;
410
bce0d2a8 411 err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
14bc52b8
PLB		 412 if (err < 0)
413 return err;
414
bce0d2a8 415 get_pin(spec, pin_idx)->eld_ctl = kctl;
14bc52b8
PLB		 416 return 0;
417}
418
079d88cc
WF		 419#ifdef BE_PARANOID
420static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
421 int *packet_index, int *byte_index)
422{
423 int val;
424
425 val = snd_hda_codec_read(codec, pin_nid, 0,
426 AC_VERB_GET_HDMI_DIP_INDEX, 0);
427
428 *packet_index = val >> 5;
429 *byte_index = val & 0x1f;
430}
431#endif
432
433static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
434 int packet_index, int byte_index)
435{
436 int val;
437
438 val = (packet_index << 5) | (byte_index & 0x1f);
439
440 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
441}
442
443static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
444 unsigned char val)
445{
446 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
447}
448
384a48d7 449static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc
WF		 450{
451 /* Unmute */
452 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
453 snd_hda_codec_write(codec, pin_nid, 0,
454 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
6169b673
TI		 455 /* Enable pin out: some machines with GM965 gets broken output when
456 * the pin is disabled or changed while using with HDMI
457 */
079d88cc 458 snd_hda_codec_write(codec, pin_nid, 0,
6169b673 459 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
079d88cc
WF		 460}
461
384a48d7 462static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc 463{
384a48d7 464 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
079d88cc
WF		 465 AC_VERB_GET_CVT_CHAN_COUNT, 0);
466}
467
468static void hdmi_set_channel_count(struct hda_codec *codec,
384a48d7 469 hda_nid_t cvt_nid, int chs)
079d88cc 470{
384a48d7
SW		 471 if (chs != hdmi_get_channel_count(codec, cvt_nid))
472 snd_hda_codec_write(codec, cvt_nid, 0,
079d88cc
WF		 473 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
474}
475
476
477/*
478 * Channel mapping routines
479 */
480
481/*
482 * Compute derived values in channel_allocations[].
483 */
484static void init_channel_allocations(void)
485{
486 int i, j;
487 struct cea_channel_speaker_allocation *p;
488
489 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
490 p = channel_allocations + i;
491 p->channels = 0;
492 p->spk_mask = 0;
493 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
494 if (p->speakers[j]) {
495 p->channels++;
496 p->spk_mask |= p->speakers[j];
497 }
498 }
499}
500
72357c78
WX		 501static int get_channel_allocation_order(int ca)
502{
503 int i;
504
505 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
506 if (channel_allocations[i].ca_index == ca)
507 break;
508 }
509 return i;
510}
511
079d88cc
WF		 512/*
513 * The transformation takes two steps:
514 *
515 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
516 * spk_mask => (channel_allocations[]) => ai->CA
517 *
518 * TODO: it could select the wrong CA from multiple candidates.
519*/
384a48d7 520static int hdmi_channel_allocation(struct hdmi_eld *eld, int channels)
079d88cc 521{
079d88cc 522 int i;
53d7d69d 523 int ca = 0;
079d88cc 524 int spk_mask = 0;
079d88cc
WF		 525 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
526
527 /*
528 * CA defaults to 0 for basic stereo audio
529 */
530 if (channels <= 2)
531 return 0;
532
079d88cc
WF		 533 /*
534 * expand ELD's speaker allocation mask
535 *
536 * ELD tells the speaker mask in a compact(paired) form,
537 * expand ELD's notions to match the ones used by Audio InfoFrame.
538 */
539 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
1613d6b4 540 if (eld->info.spk_alloc & (1 << i))
079d88cc
WF		 541 spk_mask |= eld_speaker_allocation_bits[i];
542 }
543
544 /* search for the first working match in the CA table */
545 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
546 if (channels == channel_allocations[i].channels &&
547 (spk_mask & channel_allocations[i].spk_mask) ==
548 channel_allocations[i].spk_mask) {
53d7d69d 549 ca = channel_allocations[i].ca_index;
079d88cc
WF		 550 break;
551 }
552 }
553
1613d6b4 554 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
2abbf439 555 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
53d7d69d 556 ca, channels, buf);
079d88cc 557
53d7d69d 558 return ca;
079d88cc
WF		 559}
560
561static void hdmi_debug_channel_mapping(struct hda_codec *codec,
562 hda_nid_t pin_nid)
563{
564#ifdef CONFIG_SND_DEBUG_VERBOSE
565 int i;
566 int slot;
567
568 for (i = 0; i < 8; i++) {
569 slot = snd_hda_codec_read(codec, pin_nid, 0,
570 AC_VERB_GET_HDMI_CHAN_SLOT, i);
571 printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n",
572 slot >> 4, slot & 0xf);
573 }
574#endif
575}
576
577
d45e6889 578static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
079d88cc 579 hda_nid_t pin_nid,
433968da 580 bool non_pcm,
53d7d69d 581 int ca)
079d88cc
WF		 582{
583 int i;
079d88cc 584 int err;
72357c78 585 int order;
433968da 586 int non_pcm_mapping[8];
079d88cc 587
72357c78 588 order = get_channel_allocation_order(ca);
433968da 589
079d88cc 590 if (hdmi_channel_mapping[ca][1] == 0) {
72357c78 591 for (i = 0; i < channel_allocations[order].channels; i++)
079d88cc
WF		 592 hdmi_channel_mapping[ca][i] = i | (i << 4);
593 for (; i < 8; i++)
594 hdmi_channel_mapping[ca][i] = 0xf | (i << 4);
595 }
596
433968da
WX		 597 if (non_pcm) {
598 for (i = 0; i < channel_allocations[order].channels; i++)
599 non_pcm_mapping[i] = i | (i << 4);
600 for (; i < 8; i++)
601 non_pcm_mapping[i] = 0xf | (i << 4);
602 }
603
079d88cc
WF		 604 for (i = 0; i < 8; i++) {
605 err = snd_hda_codec_write(codec, pin_nid, 0,
606 AC_VERB_SET_HDMI_CHAN_SLOT,
433968da 607 non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i]);
079d88cc 608 if (err) {
2abbf439
WF		 609 snd_printdd(KERN_NOTICE
610 "HDMI: channel mapping failed\n");
079d88cc
WF		 611 break;
612 }
613 }
614
615 hdmi_debug_channel_mapping(codec, pin_nid);
616}
617
d45e6889
TI		 618struct channel_map_table {
619 unsigned char map; /* ALSA API channel map position */
620 unsigned char cea_slot; /* CEA slot value */
621 int spk_mask; /* speaker position bit mask */
622};
623
624static struct channel_map_table map_tables[] = {
625 { SNDRV_CHMAP_FL, 0x00, FL },
626 { SNDRV_CHMAP_FR, 0x01, FR },
627 { SNDRV_CHMAP_RL, 0x04, RL },
628 { SNDRV_CHMAP_RR, 0x05, RR },
629 { SNDRV_CHMAP_LFE, 0x02, LFE },
630 { SNDRV_CHMAP_FC, 0x03, FC },
631 { SNDRV_CHMAP_RLC, 0x06, RLC },
632 { SNDRV_CHMAP_RRC, 0x07, RRC },
633 {} /* terminator */
634};
635
636/* from ALSA API channel position to speaker bit mask */
637static int to_spk_mask(unsigned char c)
638{
639 struct channel_map_table *t = map_tables;
640 for (; t->map; t++) {
641 if (t->map == c)
642 return t->spk_mask;
643 }
644 return 0;
645}
646
647/* from ALSA API channel position to CEA slot */
648static int to_cea_slot(unsigned char c)
649{
650 struct channel_map_table *t = map_tables;
651 for (; t->map; t++) {
652 if (t->map == c)
653 return t->cea_slot;
654 }
655 return 0x0f;
656}
657
658/* from CEA slot to ALSA API channel position */
659static int from_cea_slot(unsigned char c)
660{
661 struct channel_map_table *t = map_tables;
662 for (; t->map; t++) {
663 if (t->cea_slot == c)
664 return t->map;
665 }
666 return 0;
667}
668
669/* from speaker bit mask to ALSA API channel position */
670static int spk_to_chmap(int spk)
671{
672 struct channel_map_table *t = map_tables;
673 for (; t->map; t++) {
674 if (t->spk_mask == spk)
675 return t->map;
676 }
677 return 0;
678}
679
680/* get the CA index corresponding to the given ALSA API channel map */
681static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
682{
683 int i, spks = 0, spk_mask = 0;
684
685 for (i = 0; i < chs; i++) {
686 int mask = to_spk_mask(map[i]);
687 if (mask) {
688 spk_mask |= mask;
689 spks++;
690 }
691 }
692
693 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
694 if ((chs == channel_allocations[i].channels ||
695 spks == channel_allocations[i].channels) &&
696 (spk_mask & channel_allocations[i].spk_mask) ==
697 channel_allocations[i].spk_mask)
698 return channel_allocations[i].ca_index;
699 }
700 return -1;
701}
702
703/* set up the channel slots for the given ALSA API channel map */
704static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
705 hda_nid_t pin_nid,
706 int chs, unsigned char *map)
707{
708 int i;
709 for (i = 0; i < 8; i++) {
710 int val, err;
711 if (i < chs)
712 val = to_cea_slot(map[i]);
713 else
714 val = 0xf;
715 val |= (i << 4);
716 err = snd_hda_codec_write(codec, pin_nid, 0,
717 AC_VERB_SET_HDMI_CHAN_SLOT, val);
718 if (err)
719 return -EINVAL;
720 }
721 return 0;
722}
723
724/* store ALSA API channel map from the current default map */
725static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
726{
727 int i;
728 for (i = 0; i < 8; i++) {
729 if (i < channel_allocations[ca].channels)
730 map[i] = from_cea_slot((hdmi_channel_mapping[ca][i] >> 4) & 0x0f);
731 else
732 map[i] = 0;
733 }
734}
735
736static void hdmi_setup_channel_mapping(struct hda_codec *codec,
737 hda_nid_t pin_nid, bool non_pcm, int ca,
20608731
AH		 738 int channels, unsigned char *map,
739 bool chmap_set)
d45e6889 740{
20608731 741 if (!non_pcm && chmap_set) {
d45e6889
TI		 742 hdmi_manual_setup_channel_mapping(codec, pin_nid,
743 channels, map);
744 } else {
745 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
746 hdmi_setup_fake_chmap(map, ca);
747 }
748}
079d88cc
WF		 749
750/*
751 * Audio InfoFrame routines
752 */
753
754/*
755 * Enable Audio InfoFrame Transmission
756 */
757static void hdmi_start_infoframe_trans(struct hda_codec *codec,
758 hda_nid_t pin_nid)
759{
760 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
761 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
762 AC_DIPXMIT_BEST);
763}
764
765/*
766 * Disable Audio InfoFrame Transmission
767 */
768static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
769 hda_nid_t pin_nid)
770{
771 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
772 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
773 AC_DIPXMIT_DISABLE);
774}
775
776static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
777{
778#ifdef CONFIG_SND_DEBUG_VERBOSE
779 int i;
780 int size;
781
782 size = snd_hdmi_get_eld_size(codec, pin_nid);
783 printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size);
784
785 for (i = 0; i < 8; i++) {
786 size = snd_hda_codec_read(codec, pin_nid, 0,
787 AC_VERB_GET_HDMI_DIP_SIZE, i);
788 printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size);
789 }
790#endif
791}
792
793static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
794{
795#ifdef BE_PARANOID
796 int i, j;
797 int size;
798 int pi, bi;
799 for (i = 0; i < 8; i++) {
800 size = snd_hda_codec_read(codec, pin_nid, 0,
801 AC_VERB_GET_HDMI_DIP_SIZE, i);
802 if (size == 0)
803 continue;
804
805 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
806 for (j = 1; j < 1000; j++) {
807 hdmi_write_dip_byte(codec, pin_nid, 0x0);
808 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
809 if (pi != i)
810 snd_printd(KERN_INFO "dip index %d: %d != %d\n",
811 bi, pi, i);
812 if (bi == 0) /* byte index wrapped around */
813 break;
814 }
815 snd_printd(KERN_INFO
816 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
817 i, size, j);
818 }
819#endif
820}
821
53d7d69d 822static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 823{
53d7d69d 824 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 825 u8 sum = 0;
826 int i;
827
53d7d69d 828 hdmi_ai->checksum = 0;
079d88cc 829
53d7d69d 830 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 831 sum += bytes[i];
832
53d7d69d 833 hdmi_ai->checksum = -sum;
079d88cc
WF		 834}
835
836static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
837 hda_nid_t pin_nid,
53d7d69d 838 u8 *dip, int size)
079d88cc 839{
079d88cc
WF		 840 int i;
841
842 hdmi_debug_dip_size(codec, pin_nid);
843 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
844
079d88cc 845 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 846 for (i = 0; i < size; i++)
847 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 848}
849
850static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 851 u8 *dip, int size)
079d88cc 852{
079d88cc
WF		 853 u8 val;
854 int i;
855
856 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
857 != AC_DIPXMIT_BEST)
858 return false;
859
860 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 861 for (i = 0; i < size; i++) {
079d88cc
WF		 862 val = snd_hda_codec_read(codec, pin_nid, 0,
863 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 864 if (val != dip[i])
079d88cc
WF		 865 return false;
866 }
867
868 return true;
869}
870
384a48d7 871static void hdmi_setup_audio_infoframe(struct hda_codec *codec, int pin_idx,
1a6003b5
TI		 872 bool non_pcm,
873 struct snd_pcm_substream *substream)
079d88cc
WF		 874{
875 struct hdmi_spec *spec = codec->spec;
bce0d2a8 876 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 877 hda_nid_t pin_nid = per_pin->pin_nid;
53d7d69d 878 int channels = substream->runtime->channels;
384a48d7 879 struct hdmi_eld *eld;
53d7d69d 880 int ca;
2b203dbb 881 union audio_infoframe ai;
079d88cc 882
bce0d2a8 883 eld = &per_pin->sink_eld;
384a48d7
SW		 884 if (!eld->monitor_present)
885 return;
079d88cc 886
d45e6889
TI		 887 if (!non_pcm && per_pin->chmap_set)
888 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
889 else
890 ca = hdmi_channel_allocation(eld, channels);
891 if (ca < 0)
892 ca = 0;
384a48d7
SW		 893
894 memset(&ai, 0, sizeof(ai));
1613d6b4 895 if (eld->info.conn_type == 0) { /* HDMI */
384a48d7
SW		 896 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
897
898 hdmi_ai->type = 0x84;
899 hdmi_ai->ver = 0x01;
900 hdmi_ai->len = 0x0a;
901 hdmi_ai->CC02_CT47 = channels - 1;
902 hdmi_ai->CA = ca;
903 hdmi_checksum_audio_infoframe(hdmi_ai);
1613d6b4 904 } else if (eld->info.conn_type == 1) { /* DisplayPort */
384a48d7
SW		 905 struct dp_audio_infoframe *dp_ai = &ai.dp;
906
907 dp_ai->type = 0x84;
908 dp_ai->len = 0x1b;
909 dp_ai->ver = 0x11 << 2;
910 dp_ai->CC02_CT47 = channels - 1;
911 dp_ai->CA = ca;
912 } else {
913 snd_printd("HDMI: unknown connection type at pin %d\n",
914 pin_nid);
915 return;
916 }
53d7d69d 917
384a48d7
SW		 918 /*
919 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
920 * sizeof(*dp_ai) to avoid partial match/update problems when
921 * the user switches between HDMI/DP monitors.
922 */
923 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
924 sizeof(ai))) {
925 snd_printdd("hdmi_setup_audio_infoframe: "
926 "pin=%d channels=%d\n",
927 pin_nid,
928 channels);
d45e6889 929 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
20608731
AH		 930 channels, per_pin->chmap,
931 per_pin->chmap_set);
384a48d7
SW		 932 hdmi_stop_infoframe_trans(codec, pin_nid);
933 hdmi_fill_audio_infoframe(codec, pin_nid,
934 ai.bytes, sizeof(ai));
935 hdmi_start_infoframe_trans(codec, pin_nid);
2d7e887c
WX		 936 } else {
937 /* For non-pcm audio switch, setup new channel mapping
938 * accordingly */
1a6003b5 939 if (per_pin->non_pcm != non_pcm)
d45e6889 940 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
20608731
AH		 941 channels, per_pin->chmap,
942 per_pin->chmap_set);
079d88cc 943 }
433968da 944
1a6003b5 945 per_pin->non_pcm = non_pcm;
079d88cc
WF		 946}
947
948
949/*
950 * Unsolicited events
951 */
952
c6e8453e 953static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
38faddb1 954
079d88cc
WF		 955static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
956{
957 struct hdmi_spec *spec = codec->spec;
3a93897e
TI		 958 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
959 int pin_nid;
384a48d7 960 int pin_idx;
3a93897e
TI		 961 struct hda_jack_tbl *jack;
962
963 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
964 if (!jack)
965 return;
966 pin_nid = jack->nid;
967 jack->jack_dirty = 1;
079d88cc 968
fae3d88a 969 _snd_printd(SND_PR_VERBOSE,
384a48d7 970 "HDMI hot plug event: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
fae3d88a
FW		 971 codec->addr, pin_nid,
972 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
079d88cc 973
384a48d7
SW		 974 pin_idx = pin_nid_to_pin_index(spec, pin_nid);
975 if (pin_idx < 0)
079d88cc
WF		 976 return;
977
bce0d2a8 978 hdmi_present_sense(get_pin(spec, pin_idx), 1);
01a61e12 979 snd_hda_jack_report_sync(codec);
079d88cc
WF		 980}
981
982static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
983{
984 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
985 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
986 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
987 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
988
989 printk(KERN_INFO
e9ea8e8f 990 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
384a48d7 991 codec->addr,
079d88cc
WF		 992 tag,
993 subtag,
994 cp_state,
995 cp_ready);
996
997 /* TODO */
998 if (cp_state)
999 ;
1000 if (cp_ready)
1001 ;
1002}
1003
1004
1005static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1006{
079d88cc
WF		 1007 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1008 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1009
3a93897e 1010 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
079d88cc
WF		 1011 snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag);
1012 return;
1013 }
1014
1015 if (subtag == 0)
1016 hdmi_intrinsic_event(codec, res);
1017 else
1018 hdmi_non_intrinsic_event(codec, res);
1019}
1020
53b434f0
WX		 1021static void haswell_verify_pin_D0(struct hda_codec *codec,
1022 hda_nid_t cvt_nid, hda_nid_t nid)
83f26ad2
DH		 1023{
1024 int pwr, lamp, ramp;
1025
53b434f0
WX		 1026 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1027 * thus pins could only choose converter 0 for use. Make sure the
1028 * converters are in correct power state */
fd678cac 1029 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
53b434f0
WX		 1030 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1031
fd678cac 1032 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
83f26ad2
DH		 1033 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1034 AC_PWRST_D0);
1035 msleep(40);
1036 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1037 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
1038 snd_printd("Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
1039 }
1040
1041 lamp = snd_hda_codec_read(codec, nid, 0,
1042 AC_VERB_GET_AMP_GAIN_MUTE,
1043 AC_AMP_GET_LEFT | AC_AMP_GET_OUTPUT);
1044 ramp = snd_hda_codec_read(codec, nid, 0,
1045 AC_VERB_GET_AMP_GAIN_MUTE,
1046 AC_AMP_GET_RIGHT | AC_AMP_GET_OUTPUT);
1047 if (lamp != ramp) {
1048 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_AMP_GAIN_MUTE,
1049 AC_AMP_SET_RIGHT | AC_AMP_SET_OUTPUT | lamp);
1050
1051 lamp = snd_hda_codec_read(codec, nid, 0,
1052 AC_VERB_GET_AMP_GAIN_MUTE,
1053 AC_AMP_GET_LEFT | AC_AMP_GET_OUTPUT);
1054 ramp = snd_hda_codec_read(codec, nid, 0,
1055 AC_VERB_GET_AMP_GAIN_MUTE,
1056 AC_AMP_GET_RIGHT | AC_AMP_GET_OUTPUT);
1057 snd_printd("Haswell HDMI audio: Mute after set on pin 0x%x: [0x%x 0x%x]\n", nid, lamp, ramp);
1058 }
1059}
1060
079d88cc
WF		 1061/*
1062 * Callbacks
1063 */
1064
92f10b3f
TI		 1065/* HBR should be Non-PCM, 8 channels */
1066#define is_hbr_format(format) \
1067 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1068
384a48d7
SW		 1069static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1070 hda_nid_t pin_nid, u32 stream_tag, int format)
079d88cc 1071{
ea87d1c4
AH		 1072 int pinctl;
1073 int new_pinctl = 0;
ea87d1c4 1074
83f26ad2 1075 if (codec->vendor_id == 0x80862807)
53b434f0 1076 haswell_verify_pin_D0(codec, cvt_nid, pin_nid);
83f26ad2 1077
384a48d7
SW		 1078 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1079 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 1080 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1081
1082 new_pinctl = pinctl & ~AC_PINCTL_EPT;
92f10b3f 1083 if (is_hbr_format(format))
ea87d1c4
AH		 1084 new_pinctl |= AC_PINCTL_EPT_HBR;
1085 else
1086 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1087
1088 snd_printdd("hdmi_setup_stream: "
1089 "NID=0x%x, %spinctl=0x%x\n",
384a48d7 1090 pin_nid,
ea87d1c4
AH		 1091 pinctl == new_pinctl ? "" : "new-",
1092 new_pinctl);
1093
1094 if (pinctl != new_pinctl)
384a48d7 1095 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 1096 AC_VERB_SET_PIN_WIDGET_CONTROL,
1097 new_pinctl);
ea87d1c4 1098
384a48d7 1099 }
92f10b3f 1100 if (is_hbr_format(format) && !new_pinctl) {
ea87d1c4
AH		 1101 snd_printdd("hdmi_setup_stream: HBR is not supported\n");
1102 return -EINVAL;
1103 }
079d88cc 1104
384a48d7 1105 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 1106 return 0;
079d88cc
WF		 1107}
1108
7ef166b8
WX		 1109static int hdmi_choose_cvt(struct hda_codec *codec,
1110 int pin_idx, int *cvt_id, int *mux_id)
bbbe3390
TI		 1111{
1112 struct hdmi_spec *spec = codec->spec;
384a48d7 1113 struct hdmi_spec_per_pin *per_pin;
384a48d7 1114 struct hdmi_spec_per_cvt *per_cvt = NULL;
7ef166b8 1115 int cvt_idx, mux_idx = 0;
bbbe3390 1116
bce0d2a8 1117 per_pin = get_pin(spec, pin_idx);
384a48d7
SW		 1118
1119 /* Dynamically assign converter to stream */
1120 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
bce0d2a8 1121 per_cvt = get_cvt(spec, cvt_idx);
bbbe3390 1122
384a48d7
SW		 1123 /* Must not already be assigned */
1124 if (per_cvt->assigned)
1125 continue;
1126 /* Must be in pin's mux's list of converters */
1127 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1128 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1129 break;
1130 /* Not in mux list */
1131 if (mux_idx == per_pin->num_mux_nids)
1132 continue;
1133 break;
1134 }
7ef166b8 1135
384a48d7
SW		 1136 /* No free converters */
1137 if (cvt_idx == spec->num_cvts)
1138 return -ENODEV;
1139
7ef166b8
WX		 1140 if (cvt_id)
1141 *cvt_id = cvt_idx;
1142 if (mux_id)
1143 *mux_id = mux_idx;
1144
1145 return 0;
1146}
1147
1148static void haswell_config_cvts(struct hda_codec *codec,
1149 int pin_id, int mux_id)
1150{
1151 struct hdmi_spec *spec = codec->spec;
1152 struct hdmi_spec_per_pin *per_pin;
1153 int pin_idx, mux_idx;
1154 int curr;
1155 int err;
1156
1157 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1158 per_pin = get_pin(spec, pin_idx);
1159
1160 if (pin_idx == pin_id)
1161 continue;
1162
1163 curr = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1164 AC_VERB_GET_CONNECT_SEL, 0);
1165
1166 /* Choose another unused converter */
1167 if (curr == mux_id) {
1168 err = hdmi_choose_cvt(codec, pin_idx, NULL, &mux_idx);
1169 if (err < 0)
1170 return;
1171 snd_printdd("HDMI: choose converter %d for pin %d\n", mux_idx, pin_idx);
1172 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1173 AC_VERB_SET_CONNECT_SEL,
1174 mux_idx);
1175 }
1176 }
1177}
1178
1179/*
1180 * HDA PCM callbacks
1181 */
1182static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1183 struct hda_codec *codec,
1184 struct snd_pcm_substream *substream)
1185{
1186 struct hdmi_spec *spec = codec->spec;
1187 struct snd_pcm_runtime *runtime = substream->runtime;
1188 int pin_idx, cvt_idx, mux_idx = 0;
1189 struct hdmi_spec_per_pin *per_pin;
1190 struct hdmi_eld *eld;
1191 struct hdmi_spec_per_cvt *per_cvt = NULL;
1192 int err;
1193
1194 /* Validate hinfo */
1195 pin_idx = hinfo_to_pin_index(spec, hinfo);
1196 if (snd_BUG_ON(pin_idx < 0))
1197 return -EINVAL;
1198 per_pin = get_pin(spec, pin_idx);
1199 eld = &per_pin->sink_eld;
1200
1201 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1202 if (err < 0)
1203 return err;
1204
1205 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1206 /* Claim converter */
1207 per_cvt->assigned = 1;
1208 hinfo->nid = per_cvt->cvt_nid;
1209
bddee96b 1210 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
384a48d7
SW		 1211 AC_VERB_SET_CONNECT_SEL,
1212 mux_idx);
7ef166b8
WX		 1213
1214 /* configure unused pins to choose other converters */
1215 if (codec->vendor_id == 0x80862807)
1216 haswell_config_cvts(codec, pin_idx, mux_idx);
1217
384a48d7 1218 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
bbbe3390 1219
2def8172 1220 /* Initially set the converter's capabilities */
384a48d7
SW		 1221 hinfo->channels_min = per_cvt->channels_min;
1222 hinfo->channels_max = per_cvt->channels_max;
1223 hinfo->rates = per_cvt->rates;
1224 hinfo->formats = per_cvt->formats;
1225 hinfo->maxbps = per_cvt->maxbps;
2def8172 1226
384a48d7 1227 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 1228 if (!static_hdmi_pcm && eld->eld_valid) {
1613d6b4 1229 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
bbbe3390 1230 if (hinfo->channels_min > hinfo->channels_max ||
2ad779b7
TI		 1231 !hinfo->rates || !hinfo->formats) {
1232 per_cvt->assigned = 0;
1233 hinfo->nid = 0;
1234 snd_hda_spdif_ctls_unassign(codec, pin_idx);
bbbe3390 1235 return -ENODEV;
2ad779b7 1236 }
bbbe3390 1237 }
2def8172
SW		 1238
1239 /* Store the updated parameters */
639cef0e
TI		 1240 runtime->hw.channels_min = hinfo->channels_min;
1241 runtime->hw.channels_max = hinfo->channels_max;
1242 runtime->hw.formats = hinfo->formats;
1243 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 1244
1245 snd_pcm_hw_constraint_step(substream->runtime, 0,
1246 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
bbbe3390
TI		 1247 return 0;
1248}
1249
079d88cc
WF		 1250/*
1251 * HDA/HDMI auto parsing
1252 */
384a48d7 1253static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 1254{
1255 struct hdmi_spec *spec = codec->spec;
bce0d2a8 1256 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1257 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 1258
1259 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1260 snd_printk(KERN_WARNING
1261 "HDMI: pin %d wcaps %#x "
1262 "does not support connection list\n",
1263 pin_nid, get_wcaps(codec, pin_nid));
1264 return -EINVAL;
1265 }
1266
384a48d7
SW		 1267 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1268 per_pin->mux_nids,
1269 HDA_MAX_CONNECTIONS);
079d88cc
WF		 1270
1271 return 0;
1272}
1273
c6e8453e 1274static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
079d88cc 1275{
744626da 1276 struct hda_codec *codec = per_pin->codec;
4bd038f9
DH		 1277 struct hdmi_spec *spec = codec->spec;
1278 struct hdmi_eld *eld = &spec->temp_eld;
1279 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
744626da 1280 hda_nid_t pin_nid = per_pin->pin_nid;
5d44f927
SW		 1281 /*
1282 * Always execute a GetPinSense verb here, even when called from
1283 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1284 * response's PD bit is not the real PD value, but indicates that
1285 * the real PD value changed. An older version of the HD-audio
1286 * specification worked this way. Hence, we just ignore the data in
1287 * the unsolicited response to avoid custom WARs.
1288 */
079d88cc 1289 int present = snd_hda_pin_sense(codec, pin_nid);
4bd038f9
DH		 1290 bool update_eld = false;
1291 bool eld_changed = false;
079d88cc 1292
4bd038f9
DH		 1293 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1294 if (pin_eld->monitor_present)
1295 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1296 else
1297 eld->eld_valid = false;
079d88cc 1298
fae3d88a 1299 _snd_printd(SND_PR_VERBOSE,
384a48d7 1300 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
10250911 1301 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
5d44f927 1302
4bd038f9 1303 if (eld->eld_valid) {
1613d6b4
DH		 1304 if (snd_hdmi_get_eld(codec, pin_nid, eld->eld_buffer,
1305 &eld->eld_size) < 0)
4bd038f9 1306 eld->eld_valid = false;
1613d6b4
DH		 1307 else {
1308 memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
1309 if (snd_hdmi_parse_eld(&eld->info, eld->eld_buffer,
1310 eld->eld_size) < 0)
4bd038f9 1311 eld->eld_valid = false;
1613d6b4
DH		 1312 }
1313
4bd038f9 1314 if (eld->eld_valid) {
1613d6b4 1315 snd_hdmi_show_eld(&eld->info);
4bd038f9 1316 update_eld = true;
1613d6b4 1317 }
c6e8453e 1318 else if (repoll) {
744626da
WF		 1319 queue_delayed_work(codec->bus->workq,
1320 &per_pin->work,
1321 msecs_to_jiffies(300));
4bd038f9 1322 return;
744626da
WF		 1323 }
1324 }
4bd038f9
DH		 1325
1326 mutex_lock(&pin_eld->lock);
92c69e79 1327 if (pin_eld->eld_valid && !eld->eld_valid) {
4bd038f9 1328 update_eld = true;
92c69e79
DH		 1329 eld_changed = true;
1330 }
4bd038f9
DH		 1331 if (update_eld) {
1332 pin_eld->eld_valid = eld->eld_valid;
92c69e79
DH		 1333 eld_changed = pin_eld->eld_size != eld->eld_size ||
1334 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
4bd038f9
DH		 1335 eld->eld_size) != 0;
1336 if (eld_changed)
1337 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1338 eld->eld_size);
1339 pin_eld->eld_size = eld->eld_size;
1340 pin_eld->info = eld->info;
1341 }
1342 mutex_unlock(&pin_eld->lock);
92c69e79
DH		 1343
1344 if (eld_changed)
1345 snd_ctl_notify(codec->bus->card,
1346 SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO,
1347 &per_pin->eld_ctl->id);
079d88cc
WF		 1348}
1349
744626da
WF		 1350static void hdmi_repoll_eld(struct work_struct *work)
1351{
1352 struct hdmi_spec_per_pin *per_pin =
1353 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1354
c6e8453e
WF		 1355 if (per_pin->repoll_count++ > 6)
1356 per_pin->repoll_count = 0;
1357
1358 hdmi_present_sense(per_pin, per_pin->repoll_count);
744626da
WF		 1359}
1360
c88d4e84
TI		 1361static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1362 hda_nid_t nid);
1363
079d88cc
WF		 1364static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1365{
1366 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1367 unsigned int caps, config;
1368 int pin_idx;
1369 struct hdmi_spec_per_pin *per_pin;
07acecc1 1370 int err;
079d88cc 1371
efc2f8de 1372 caps = snd_hda_query_pin_caps(codec, pin_nid);
384a48d7
SW		 1373 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1374 return 0;
1375
efc2f8de 1376 config = snd_hda_codec_get_pincfg(codec, pin_nid);
384a48d7
SW		 1377 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1378 return 0;
1379
c88d4e84
TI		 1380 if (codec->vendor_id == 0x80862807)
1381 intel_haswell_fixup_connect_list(codec, pin_nid);
1382
384a48d7 1383 pin_idx = spec->num_pins;
bce0d2a8
TI		 1384 per_pin = snd_array_new(&spec->pins);
1385 if (!per_pin)
1386 return -ENOMEM;
384a48d7
SW		 1387
1388 per_pin->pin_nid = pin_nid;
1a6003b5 1389 per_pin->non_pcm = false;
079d88cc 1390
384a48d7
SW		 1391 err = hdmi_read_pin_conn(codec, pin_idx);
1392 if (err < 0)
1393 return err;
079d88cc 1394
079d88cc
WF		 1395 spec->num_pins++;
1396
384a48d7 1397 return 0;
079d88cc
WF		 1398}
1399
384a48d7 1400static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 1401{
1402 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1403 struct hdmi_spec_per_cvt *per_cvt;
1404 unsigned int chans;
1405 int err;
079d88cc 1406
384a48d7
SW		 1407 chans = get_wcaps(codec, cvt_nid);
1408 chans = get_wcaps_channels(chans);
1409
bce0d2a8
TI		 1410 per_cvt = snd_array_new(&spec->cvts);
1411 if (!per_cvt)
1412 return -ENOMEM;
384a48d7
SW		 1413
1414 per_cvt->cvt_nid = cvt_nid;
1415 per_cvt->channels_min = 2;
d45e6889 1416 if (chans <= 16) {
384a48d7 1417 per_cvt->channels_max = chans;
d45e6889
TI		 1418 if (chans > spec->channels_max)
1419 spec->channels_max = chans;
1420 }
384a48d7
SW		 1421
1422 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1423 &per_cvt->rates,
1424 &per_cvt->formats,
1425 &per_cvt->maxbps);
1426 if (err < 0)
1427 return err;
1428
bce0d2a8
TI		 1429 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1430 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1431 spec->num_cvts++;
079d88cc
WF		 1432
1433 return 0;
1434}
1435
1436static int hdmi_parse_codec(struct hda_codec *codec)
1437{
1438 hda_nid_t nid;
1439 int i, nodes;
1440
1441 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
1442 if (!nid || nodes < 0) {
1443 snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n");
1444 return -EINVAL;
1445 }
1446
1447 for (i = 0; i < nodes; i++, nid++) {
1448 unsigned int caps;
1449 unsigned int type;
1450
efc2f8de 1451 caps = get_wcaps(codec, nid);
079d88cc
WF		 1452 type = get_wcaps_type(caps);
1453
1454 if (!(caps & AC_WCAP_DIGITAL))
1455 continue;
1456
1457 switch (type) {
1458 case AC_WID_AUD_OUT:
384a48d7 1459 hdmi_add_cvt(codec, nid);
079d88cc
WF		 1460 break;
1461 case AC_WID_PIN:
3eaead57 1462 hdmi_add_pin(codec, nid);
079d88cc
WF		 1463 break;
1464 }
1465 }
1466
c9adeefd
DH		 1467#ifdef CONFIG_PM
1468 /* We're seeing some problems with unsolicited hot plug events on
1469 * PantherPoint after S3, if this is not enabled */
1470 if (codec->vendor_id == 0x80862806)
1471 codec->bus->power_keep_link_on = 1;
079d88cc
WF		 1472 /*
1473 * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event
1474 * can be lost and presence sense verb will become inaccurate if the
1475 * HDA link is powered off at hot plug or hw initialization time.
1476 */
c9adeefd 1477 else if (!(snd_hda_param_read(codec, codec->afg, AC_PAR_POWER_STATE) &
079d88cc
WF		 1478 AC_PWRST_EPSS))
1479 codec->bus->power_keep_link_on = 1;
1480#endif
1481
1482 return 0;
1483}
1484
84eb01be
TI		 1485/*
1486 */
1a6003b5
TI		 1487static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1488{
1489 struct hda_spdif_out *spdif;
1490 bool non_pcm;
1491
1492 mutex_lock(&codec->spdif_mutex);
1493 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1494 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1495 mutex_unlock(&codec->spdif_mutex);
1496 return non_pcm;
1497}
1498
1499
84eb01be
TI		 1500/*
1501 * HDMI callbacks
1502 */
1503
1504static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1505 struct hda_codec *codec,
1506 unsigned int stream_tag,
1507 unsigned int format,
1508 struct snd_pcm_substream *substream)
1509{
384a48d7
SW		 1510 hda_nid_t cvt_nid = hinfo->nid;
1511 struct hdmi_spec *spec = codec->spec;
1512 int pin_idx = hinfo_to_pin_index(spec, hinfo);
bce0d2a8 1513 hda_nid_t pin_nid = get_pin(spec, pin_idx)->pin_nid;
1a6003b5
TI		 1514 bool non_pcm;
1515
1516 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
384a48d7
SW		 1517
1518 hdmi_set_channel_count(codec, cvt_nid, substream->runtime->channels);
84eb01be 1519
1a6003b5 1520 hdmi_setup_audio_infoframe(codec, pin_idx, non_pcm, substream);
84eb01be 1521
384a48d7 1522 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
84eb01be
TI		 1523}
1524
8dfaa573
TI		 1525static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1526 struct hda_codec *codec,
1527 struct snd_pcm_substream *substream)
1528{
1529 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1530 return 0;
1531}
1532
f2ad24fa
TI		 1533static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1534 struct hda_codec *codec,
1535 struct snd_pcm_substream *substream)
384a48d7
SW		 1536{
1537 struct hdmi_spec *spec = codec->spec;
1538 int cvt_idx, pin_idx;
1539 struct hdmi_spec_per_cvt *per_cvt;
1540 struct hdmi_spec_per_pin *per_pin;
384a48d7 1541
384a48d7
SW		 1542 if (hinfo->nid) {
1543 cvt_idx = cvt_nid_to_cvt_index(spec, hinfo->nid);
1544 if (snd_BUG_ON(cvt_idx < 0))
1545 return -EINVAL;
bce0d2a8 1546 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1547
1548 snd_BUG_ON(!per_cvt->assigned);
1549 per_cvt->assigned = 0;
1550 hinfo->nid = 0;
1551
1552 pin_idx = hinfo_to_pin_index(spec, hinfo);
1553 if (snd_BUG_ON(pin_idx < 0))
1554 return -EINVAL;
bce0d2a8 1555 per_pin = get_pin(spec, pin_idx);
384a48d7 1556
384a48d7 1557 snd_hda_spdif_ctls_unassign(codec, pin_idx);
d45e6889
TI		 1558 per_pin->chmap_set = false;
1559 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
384a48d7 1560 }
d45e6889 1561
384a48d7
SW		 1562 return 0;
1563}
1564
1565static const struct hda_pcm_ops generic_ops = {
1566 .open = hdmi_pcm_open,
f2ad24fa 1567 .close = hdmi_pcm_close,
384a48d7 1568 .prepare = generic_hdmi_playback_pcm_prepare,
8dfaa573 1569 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 1570};
1571
d45e6889
TI		 1572/*
1573 * ALSA API channel-map control callbacks
1574 */
1575static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1576 struct snd_ctl_elem_info *uinfo)
1577{
1578 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1579 struct hda_codec *codec = info->private_data;
1580 struct hdmi_spec *spec = codec->spec;
1581 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1582 uinfo->count = spec->channels_max;
1583 uinfo->value.integer.min = 0;
1584 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1585 return 0;
1586}
1587
1588static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
1589 unsigned int size, unsigned int __user *tlv)
1590{
1591 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1592 struct hda_codec *codec = info->private_data;
1593 struct hdmi_spec *spec = codec->spec;
1594 const unsigned int valid_mask =
1595 FL | FR | RL | RR | LFE | FC | RLC | RRC;
1596 unsigned int __user *dst;
1597 int chs, count = 0;
1598
1599 if (size < 8)
1600 return -ENOMEM;
1601 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
1602 return -EFAULT;
1603 size -= 8;
1604 dst = tlv + 2;
498dab3a 1605 for (chs = 2; chs <= spec->channels_max; chs++) {
d45e6889
TI		 1606 int i, c;
1607 struct cea_channel_speaker_allocation *cap;
1608 cap = channel_allocations;
1609 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
1610 int chs_bytes = chs * 4;
1611 if (cap->channels != chs)
1612 continue;
1613 if (cap->spk_mask & ~valid_mask)
1614 continue;
1615 if (size < 8)
1616 return -ENOMEM;
1617 if (put_user(SNDRV_CTL_TLVT_CHMAP_VAR, dst) ||
1618 put_user(chs_bytes, dst + 1))
1619 return -EFAULT;
1620 dst += 2;
1621 size -= 8;
1622 count += 8;
1623 if (size < chs_bytes)
1624 return -ENOMEM;
1625 size -= chs_bytes;
1626 count += chs_bytes;
1627 for (c = 7; c >= 0; c--) {
1628 int spk = cap->speakers[c];
1629 if (!spk)
1630 continue;
1631 if (put_user(spk_to_chmap(spk), dst))
1632 return -EFAULT;
1633 dst++;
1634 }
1635 }
1636 }
1637 if (put_user(count, tlv + 1))
1638 return -EFAULT;
1639 return 0;
1640}
1641
1642static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
1643 struct snd_ctl_elem_value *ucontrol)
1644{
1645 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1646 struct hda_codec *codec = info->private_data;
1647 struct hdmi_spec *spec = codec->spec;
1648 int pin_idx = kcontrol->private_value;
bce0d2a8 1649 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 1650 int i;
1651
1652 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
1653 ucontrol->value.integer.value[i] = per_pin->chmap[i];
1654 return 0;
1655}
1656
1657static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
1658 struct snd_ctl_elem_value *ucontrol)
1659{
1660 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1661 struct hda_codec *codec = info->private_data;
1662 struct hdmi_spec *spec = codec->spec;
1663 int pin_idx = kcontrol->private_value;
bce0d2a8 1664 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 1665 unsigned int ctl_idx;
1666 struct snd_pcm_substream *substream;
1667 unsigned char chmap[8];
1668 int i, ca, prepared = 0;
1669
1670 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
1671 substream = snd_pcm_chmap_substream(info, ctl_idx);
1672 if (!substream || !substream->runtime)
6f54c361 1673 return 0; /* just for avoiding error from alsactl restore */
d45e6889
TI		 1674 switch (substream->runtime->status->state) {
1675 case SNDRV_PCM_STATE_OPEN:
1676 case SNDRV_PCM_STATE_SETUP:
1677 break;
1678 case SNDRV_PCM_STATE_PREPARED:
1679 prepared = 1;
1680 break;
1681 default:
1682 return -EBUSY;
1683 }
1684 memset(chmap, 0, sizeof(chmap));
1685 for (i = 0; i < ARRAY_SIZE(chmap); i++)
1686 chmap[i] = ucontrol->value.integer.value[i];
1687 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
1688 return 0;
1689 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
1690 if (ca < 0)
1691 return -EINVAL;
1692 per_pin->chmap_set = true;
1693 memcpy(per_pin->chmap, chmap, sizeof(chmap));
1694 if (prepared)
1695 hdmi_setup_audio_infoframe(codec, pin_idx, per_pin->non_pcm,
1696 substream);
1697
1698 return 0;
1699}
1700
84eb01be
TI		 1701static int generic_hdmi_build_pcms(struct hda_codec *codec)
1702{
1703 struct hdmi_spec *spec = codec->spec;
384a48d7 1704 int pin_idx;
84eb01be 1705
384a48d7
SW		 1706 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1707 struct hda_pcm *info;
84eb01be 1708 struct hda_pcm_stream *pstr;
bce0d2a8
TI		 1709 struct hdmi_spec_per_pin *per_pin;
1710
1711 per_pin = get_pin(spec, pin_idx);
1712 sprintf(per_pin->pcm_name, "HDMI %d", pin_idx);
1713 info = snd_array_new(&spec->pcm_rec);
1714 if (!info)
1715 return -ENOMEM;
1716 info->name = per_pin->pcm_name;
84eb01be 1717 info->pcm_type = HDA_PCM_TYPE_HDMI;
d45e6889 1718 info->own_chmap = true;
384a48d7 1719
84eb01be 1720 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 1721 pstr->substreams = 1;
1722 pstr->ops = generic_ops;
1723 /* other pstr fields are set in open */
84eb01be
TI		 1724 }
1725
384a48d7 1726 codec->num_pcms = spec->num_pins;
bce0d2a8 1727 codec->pcm_info = spec->pcm_rec.list;
384a48d7 1728
84eb01be
TI		 1729 return 0;
1730}
1731
0b6c49b5
DH		 1732static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
1733{
31ef2257 1734 char hdmi_str[32] = "HDMI/DP";
0b6c49b5 1735 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 1736 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1737 int pcmdev = get_pcm_rec(spec, pin_idx)->device;
0b6c49b5 1738
31ef2257
TI		 1739 if (pcmdev > 0)
1740 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
30efd8de
DH		 1741 if (!is_jack_detectable(codec, per_pin->pin_nid))
1742 strncat(hdmi_str, " Phantom",
1743 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
0b6c49b5 1744
31ef2257 1745 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 0);
0b6c49b5
DH		 1746}
1747
84eb01be
TI		 1748static int generic_hdmi_build_controls(struct hda_codec *codec)
1749{
1750 struct hdmi_spec *spec = codec->spec;
1751 int err;
384a48d7 1752 int pin_idx;
84eb01be 1753
384a48d7 1754 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1755 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
0b6c49b5
DH		 1756
1757 err = generic_hdmi_build_jack(codec, pin_idx);
1758 if (err < 0)
1759 return err;
1760
dcda5806
TI		 1761 err = snd_hda_create_dig_out_ctls(codec,
1762 per_pin->pin_nid,
1763 per_pin->mux_nids[0],
1764 HDA_PCM_TYPE_HDMI);
84eb01be
TI		 1765 if (err < 0)
1766 return err;
384a48d7 1767 snd_hda_spdif_ctls_unassign(codec, pin_idx);
14bc52b8
PLB		 1768
1769 /* add control for ELD Bytes */
bce0d2a8
TI		 1770 err = hdmi_create_eld_ctl(codec, pin_idx,
1771 get_pcm_rec(spec, pin_idx)->device);
14bc52b8
PLB		 1772
1773 if (err < 0)
1774 return err;
31ef2257 1775
82b1d73f 1776 hdmi_present_sense(per_pin, 0);
84eb01be
TI		 1777 }
1778
d45e6889
TI		 1779 /* add channel maps */
1780 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1781 struct snd_pcm_chmap *chmap;
1782 struct snd_kcontrol *kctl;
1783 int i;
1784 err = snd_pcm_add_chmap_ctls(codec->pcm_info[pin_idx].pcm,
1785 SNDRV_PCM_STREAM_PLAYBACK,
1786 NULL, 0, pin_idx, &chmap);
1787 if (err < 0)
1788 return err;
1789 /* override handlers */
1790 chmap->private_data = codec;
1791 kctl = chmap->kctl;
1792 for (i = 0; i < kctl->count; i++)
1793 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
1794 kctl->info = hdmi_chmap_ctl_info;
1795 kctl->get = hdmi_chmap_ctl_get;
1796 kctl->put = hdmi_chmap_ctl_put;
1797 kctl->tlv.c = hdmi_chmap_ctl_tlv;
1798 }
1799
84eb01be
TI		 1800 return 0;
1801}
1802
8b8d654b 1803static int generic_hdmi_init_per_pins(struct hda_codec *codec)
84eb01be
TI		 1804{
1805 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1806 int pin_idx;
1807
1808 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1809 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1810 struct hdmi_eld *eld = &per_pin->sink_eld;
84eb01be 1811
744626da 1812 per_pin->codec = codec;
4bd038f9 1813 mutex_init(&eld->lock);
744626da 1814 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
384a48d7 1815 snd_hda_eld_proc_new(codec, eld, pin_idx);
84eb01be 1816 }
8b8d654b
TI		 1817 return 0;
1818}
1819
1820static int generic_hdmi_init(struct hda_codec *codec)
1821{
1822 struct hdmi_spec *spec = codec->spec;
1823 int pin_idx;
1824
1825 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1826 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
8b8d654b
TI		 1827 hda_nid_t pin_nid = per_pin->pin_nid;
1828
1829 hdmi_init_pin(codec, pin_nid);
1830 snd_hda_jack_detect_enable(codec, pin_nid, pin_nid);
1831 }
84eb01be
TI		 1832 return 0;
1833}
1834
bce0d2a8
TI		 1835static void hdmi_array_init(struct hdmi_spec *spec, int nums)
1836{
1837 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
1838 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
1839 snd_array_init(&spec->pcm_rec, sizeof(struct hda_pcm), nums);
1840}
1841
1842static void hdmi_array_free(struct hdmi_spec *spec)
1843{
1844 snd_array_free(&spec->pins);
1845 snd_array_free(&spec->cvts);
1846 snd_array_free(&spec->pcm_rec);
1847}
1848
84eb01be
TI		 1849static void generic_hdmi_free(struct hda_codec *codec)
1850{
1851 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1852 int pin_idx;
1853
1854 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1855 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1856 struct hdmi_eld *eld = &per_pin->sink_eld;
84eb01be 1857
744626da 1858 cancel_delayed_work(&per_pin->work);
384a48d7
SW		 1859 snd_hda_eld_proc_free(codec, eld);
1860 }
84eb01be 1861
744626da 1862 flush_workqueue(codec->bus->workq);
bce0d2a8 1863 hdmi_array_free(spec);
84eb01be
TI		 1864 kfree(spec);
1865}
1866
28cb72e5
WX		 1867#ifdef CONFIG_PM
1868static int generic_hdmi_resume(struct hda_codec *codec)
1869{
1870 struct hdmi_spec *spec = codec->spec;
1871 int pin_idx;
1872
1873 generic_hdmi_init(codec);
1874 snd_hda_codec_resume_amp(codec);
1875 snd_hda_codec_resume_cache(codec);
1876
1877 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1878 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1879 hdmi_present_sense(per_pin, 1);
1880 }
1881 return 0;
1882}
1883#endif
1884
fb79e1e0 1885static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 1886 .init = generic_hdmi_init,
1887 .free = generic_hdmi_free,
1888 .build_pcms = generic_hdmi_build_pcms,
1889 .build_controls = generic_hdmi_build_controls,
1890 .unsol_event = hdmi_unsol_event,
28cb72e5
WX		 1891#ifdef CONFIG_PM
1892 .resume = generic_hdmi_resume,
1893#endif
84eb01be
TI		 1894};
1895
6ffe168f 1896
c88d4e84
TI		 1897static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1898 hda_nid_t nid)
1899{
1900 struct hdmi_spec *spec = codec->spec;
1901 hda_nid_t conns[4];
1902 int nconns;
6ffe168f 1903
c88d4e84
TI		 1904 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
1905 if (nconns == spec->num_cvts &&
1906 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
6ffe168f
ML		 1907 return;
1908
c88d4e84
TI		 1909 /* override pins connection list */
1910 snd_printdd("hdmi: haswell: override pin connection 0x%x\n", nid);
1911 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
6ffe168f
ML		 1912}
1913
1611a9c9
ML		 1914#define INTEL_VENDOR_NID 0x08
1915#define INTEL_GET_VENDOR_VERB 0xf81
1916#define INTEL_SET_VENDOR_VERB 0x781
1917#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
1918#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
1919
1920static void intel_haswell_enable_all_pins(struct hda_codec *codec,
17df3f55 1921 bool update_tree)
1611a9c9
ML		 1922{
1923 unsigned int vendor_param;
1924
1611a9c9
ML		 1925 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
1926 INTEL_GET_VENDOR_VERB, 0);
1927 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
1928 return;
1929
1930 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
1931 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
1932 INTEL_SET_VENDOR_VERB, vendor_param);
1933 if (vendor_param == -1)
1934 return;
1935
17df3f55
TI		 1936 if (update_tree)
1937 snd_hda_codec_update_widgets(codec);
1611a9c9
ML		 1938}
1939
c88d4e84
TI		 1940static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
1941{
1942 unsigned int vendor_param;
1943
1944 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
1945 INTEL_GET_VENDOR_VERB, 0);
1946 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
1947 return;
1948
1949 /* enable DP1.2 mode */
1950 vendor_param |= INTEL_EN_DP12;
1951 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
1952 INTEL_SET_VENDOR_VERB, vendor_param);
1953}
1954
17df3f55
TI		 1955/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
1956 * Otherwise you may get severe h/w communication errors.
1957 */
1958static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
1959 unsigned int power_state)
1960{
1961 if (power_state == AC_PWRST_D0) {
1962 intel_haswell_enable_all_pins(codec, false);
1963 intel_haswell_fixup_enable_dp12(codec);
1964 }
c88d4e84 1965
17df3f55
TI		 1966 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
1967 snd_hda_codec_set_power_to_all(codec, fg, power_state);
1968}
6ffe168f 1969
84eb01be
TI		 1970static int patch_generic_hdmi(struct hda_codec *codec)
1971{
1972 struct hdmi_spec *spec;
84eb01be
TI		 1973
1974 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1975 if (spec == NULL)
1976 return -ENOMEM;
1977
1978 codec->spec = spec;
bce0d2a8 1979 hdmi_array_init(spec, 4);
6ffe168f 1980
17df3f55
TI		 1981 if (codec->vendor_id == 0x80862807) {
1982 intel_haswell_enable_all_pins(codec, true);
c88d4e84 1983 intel_haswell_fixup_enable_dp12(codec);
17df3f55 1984 }
6ffe168f 1985
84eb01be
TI		 1986 if (hdmi_parse_codec(codec) < 0) {
1987 codec->spec = NULL;
1988 kfree(spec);
1989 return -EINVAL;
1990 }
1991 codec->patch_ops = generic_hdmi_patch_ops;
17df3f55
TI		 1992 if (codec->vendor_id == 0x80862807)
1993 codec->patch_ops.set_power_state = haswell_set_power_state;
1994
8b8d654b 1995 generic_hdmi_init_per_pins(codec);
84eb01be 1996
84eb01be
TI		 1997 init_channel_allocations();
1998
1999 return 0;
2000}
2001
3aaf8980
SW		 2002/*
2003 * Shared non-generic implementations
2004 */
2005
2006static int simple_playback_build_pcms(struct hda_codec *codec)
2007{
2008 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2009 struct hda_pcm *info;
8ceb332d
TI		 2010 unsigned int chans;
2011 struct hda_pcm_stream *pstr;
bce0d2a8 2012 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2013
bce0d2a8
TI		 2014 per_cvt = get_cvt(spec, 0);
2015 chans = get_wcaps(codec, per_cvt->cvt_nid);
8ceb332d 2016 chans = get_wcaps_channels(chans);
3aaf8980 2017
bce0d2a8
TI		 2018 info = snd_array_new(&spec->pcm_rec);
2019 if (!info)
2020 return -ENOMEM;
2021 info->name = get_pin(spec, 0)->pcm_name;
2022 sprintf(info->name, "HDMI 0");
8ceb332d
TI		 2023 info->pcm_type = HDA_PCM_TYPE_HDMI;
2024 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2025 *pstr = spec->pcm_playback;
bce0d2a8 2026 pstr->nid = per_cvt->cvt_nid;
8ceb332d
TI		 2027 if (pstr->channels_max <= 2 && chans && chans <= 16)
2028 pstr->channels_max = chans;
3aaf8980 2029
bce0d2a8
TI		 2030 codec->num_pcms = 1;
2031 codec->pcm_info = info;
2032
3aaf8980
SW		 2033 return 0;
2034}
2035
4b6ace9e
TI		 2036/* unsolicited event for jack sensing */
2037static void simple_hdmi_unsol_event(struct hda_codec *codec,
2038 unsigned int res)
2039{
9dd8cf12 2040 snd_hda_jack_set_dirty_all(codec);
4b6ace9e
TI		 2041 snd_hda_jack_report_sync(codec);
2042}
2043
2044/* generic_hdmi_build_jack can be used for simple_hdmi, too,
2045 * as long as spec->pins[] is set correctly
2046 */
2047#define simple_hdmi_build_jack generic_hdmi_build_jack
2048
3aaf8980
SW		 2049static int simple_playback_build_controls(struct hda_codec *codec)
2050{
2051 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2052 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2053 int err;
3aaf8980 2054
bce0d2a8
TI		 2055 per_cvt = get_cvt(spec, 0);
2056 err = snd_hda_create_spdif_out_ctls(codec, per_cvt->cvt_nid,
2057 per_cvt->cvt_nid);
8ceb332d
TI		 2058 if (err < 0)
2059 return err;
2060 return simple_hdmi_build_jack(codec, 0);
3aaf8980
SW		 2061}
2062
4f0110ce
TI		 2063static int simple_playback_init(struct hda_codec *codec)
2064{
2065 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 2066 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2067 hda_nid_t pin = per_pin->pin_nid;
8ceb332d
TI		 2068
2069 snd_hda_codec_write(codec, pin, 0,
2070 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2071 /* some codecs require to unmute the pin */
2072 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2073 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2074 AMP_OUT_UNMUTE);
2075 snd_hda_jack_detect_enable(codec, pin, pin);
4f0110ce
TI		 2076 return 0;
2077}
2078
3aaf8980
SW		 2079static void simple_playback_free(struct hda_codec *codec)
2080{
2081 struct hdmi_spec *spec = codec->spec;
2082
bce0d2a8 2083 hdmi_array_free(spec);
3aaf8980
SW		 2084 kfree(spec);
2085}
2086
84eb01be
TI		 2087/*
2088 * Nvidia specific implementations
2089 */
2090
2091#define Nv_VERB_SET_Channel_Allocation 0xF79
2092#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2093#define Nv_VERB_SET_Audio_Protection_On 0xF98
2094#define Nv_VERB_SET_Audio_Protection_Off 0xF99
2095
2096#define nvhdmi_master_con_nid_7x 0x04
2097#define nvhdmi_master_pin_nid_7x 0x05
2098
fb79e1e0 2099static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 2100 /*front, rear, clfe, rear_surr */
2101 0x6, 0x8, 0xa, 0xc,
2102};
2103
ceaa86ba
TI		 2104static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2105 /* set audio protect on */
2106 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2107 /* enable digital output on pin widget */
2108 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2109 {} /* terminator */
2110};
2111
2112static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
84eb01be
TI		 2113 /* set audio protect on */
2114 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2115 /* enable digital output on pin widget */
2116 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2117 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2118 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2119 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2120 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2121 {} /* terminator */
2122};
2123
2124#ifdef LIMITED_RATE_FMT_SUPPORT
2125/* support only the safe format and rate */
2126#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2127#define SUPPORTED_MAXBPS 16
2128#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2129#else
2130/* support all rates and formats */
2131#define SUPPORTED_RATES \
2132 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2133 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2134 SNDRV_PCM_RATE_192000)
2135#define SUPPORTED_MAXBPS 24
2136#define SUPPORTED_FORMATS \
2137 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2138#endif
2139
ceaa86ba
TI		 2140static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2141{
2142 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2143 return 0;
2144}
2145
2146static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
84eb01be 2147{
ceaa86ba 2148 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
84eb01be
TI		 2149 return 0;
2150}
2151
393004b2
ND		 2152static unsigned int channels_2_6_8[] = {
2153 2, 6, 8
2154};
2155
2156static unsigned int channels_2_8[] = {
2157 2, 8
2158};
2159
2160static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2161 .count = ARRAY_SIZE(channels_2_6_8),
2162 .list = channels_2_6_8,
2163 .mask = 0,
2164};
2165
2166static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2167 .count = ARRAY_SIZE(channels_2_8),
2168 .list = channels_2_8,
2169 .mask = 0,
2170};
2171
84eb01be
TI		 2172static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2173 struct hda_codec *codec,
2174 struct snd_pcm_substream *substream)
2175{
2176 struct hdmi_spec *spec = codec->spec;
393004b2
ND		 2177 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2178
2179 switch (codec->preset->id) {
2180 case 0x10de0002:
2181 case 0x10de0003:
2182 case 0x10de0005:
2183 case 0x10de0006:
2184 hw_constraints_channels = &hw_constraints_2_8_channels;
2185 break;
2186 case 0x10de0007:
2187 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2188 break;
2189 default:
2190 break;
2191 }
2192
2193 if (hw_constraints_channels != NULL) {
2194 snd_pcm_hw_constraint_list(substream->runtime, 0,
2195 SNDRV_PCM_HW_PARAM_CHANNELS,
2196 hw_constraints_channels);
ad09fc9d
TI		 2197 } else {
2198 snd_pcm_hw_constraint_step(substream->runtime, 0,
2199 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 2200 }
2201
84eb01be
TI		 2202 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2203}
2204
2205static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2206 struct hda_codec *codec,
2207 struct snd_pcm_substream *substream)
2208{
2209 struct hdmi_spec *spec = codec->spec;
2210 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2211}
2212
2213static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2214 struct hda_codec *codec,
2215 unsigned int stream_tag,
2216 unsigned int format,
2217 struct snd_pcm_substream *substream)
2218{
2219 struct hdmi_spec *spec = codec->spec;
2220 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2221 stream_tag, format, substream);
2222}
2223
d0b1252d
TI		 2224static const struct hda_pcm_stream simple_pcm_playback = {
2225 .substreams = 1,
2226 .channels_min = 2,
2227 .channels_max = 2,
2228 .ops = {
2229 .open = simple_playback_pcm_open,
2230 .close = simple_playback_pcm_close,
2231 .prepare = simple_playback_pcm_prepare
2232 },
2233};
2234
2235static const struct hda_codec_ops simple_hdmi_patch_ops = {
2236 .build_controls = simple_playback_build_controls,
2237 .build_pcms = simple_playback_build_pcms,
2238 .init = simple_playback_init,
2239 .free = simple_playback_free,
250e41ac 2240 .unsol_event = simple_hdmi_unsol_event,
d0b1252d
TI		 2241};
2242
2243static int patch_simple_hdmi(struct hda_codec *codec,
2244 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2245{
2246 struct hdmi_spec *spec;
bce0d2a8
TI		 2247 struct hdmi_spec_per_cvt *per_cvt;
2248 struct hdmi_spec_per_pin *per_pin;
d0b1252d
TI		 2249
2250 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2251 if (!spec)
2252 return -ENOMEM;
2253
2254 codec->spec = spec;
bce0d2a8 2255 hdmi_array_init(spec, 1);
d0b1252d
TI		 2256
2257 spec->multiout.num_dacs = 0; /* no analog */
2258 spec->multiout.max_channels = 2;
2259 spec->multiout.dig_out_nid = cvt_nid;
2260 spec->num_cvts = 1;
2261 spec->num_pins = 1;
bce0d2a8
TI		 2262 per_pin = snd_array_new(&spec->pins);
2263 per_cvt = snd_array_new(&spec->cvts);
2264 if (!per_pin || !per_cvt) {
2265 simple_playback_free(codec);
2266 return -ENOMEM;
2267 }
2268 per_cvt->cvt_nid = cvt_nid;
2269 per_pin->pin_nid = pin_nid;
d0b1252d
TI		 2270 spec->pcm_playback = simple_pcm_playback;
2271
2272 codec->patch_ops = simple_hdmi_patch_ops;
2273
2274 return 0;
2275}
2276
1f348522
AP		 2277static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2278 int channels)
2279{
2280 unsigned int chanmask;
2281 int chan = channels ? (channels - 1) : 1;
2282
2283 switch (channels) {
2284 default:
2285 case 0:
2286 case 2:
2287 chanmask = 0x00;
2288 break;
2289 case 4:
2290 chanmask = 0x08;
2291 break;
2292 case 6:
2293 chanmask = 0x0b;
2294 break;
2295 case 8:
2296 chanmask = 0x13;
2297 break;
2298 }
2299
2300 /* Set the audio infoframe channel allocation and checksum fields. The
2301 * channel count is computed implicitly by the hardware. */
2302 snd_hda_codec_write(codec, 0x1, 0,
2303 Nv_VERB_SET_Channel_Allocation, chanmask);
2304
2305 snd_hda_codec_write(codec, 0x1, 0,
2306 Nv_VERB_SET_Info_Frame_Checksum,
2307 (0x71 - chan - chanmask));
2308}
2309
84eb01be
TI		 2310static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2311 struct hda_codec *codec,
2312 struct snd_pcm_substream *substream)
2313{
2314 struct hdmi_spec *spec = codec->spec;
2315 int i;
2316
2317 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2318 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2319 for (i = 0; i < 4; i++) {
2320 /* set the stream id */
2321 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2322 AC_VERB_SET_CHANNEL_STREAMID, 0);
2323 /* set the stream format */
2324 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2325 AC_VERB_SET_STREAM_FORMAT, 0);
2326 }
2327
1f348522
AP		 2328 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2329 * streams are disabled. */
2330 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2331
84eb01be
TI		 2332 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2333}
2334
2335static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2336 struct hda_codec *codec,
2337 unsigned int stream_tag,
2338 unsigned int format,
2339 struct snd_pcm_substream *substream)
2340{
2341 int chs;
112daa7a 2342 unsigned int dataDCC2, channel_id;
84eb01be 2343 int i;
7c935976 2344 struct hdmi_spec *spec = codec->spec;
e3245cdd 2345 struct hda_spdif_out *spdif;
bce0d2a8 2346 struct hdmi_spec_per_cvt *per_cvt;
84eb01be
TI		 2347
2348 mutex_lock(&codec->spdif_mutex);
bce0d2a8
TI		 2349 per_cvt = get_cvt(spec, 0);
2350 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
84eb01be
TI		 2351
2352 chs = substream->runtime->channels;
84eb01be 2353
84eb01be
TI		 2354 dataDCC2 = 0x2;
2355
84eb01be 2356 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 2357 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2358 snd_hda_codec_write(codec,
2359 nvhdmi_master_con_nid_7x,
2360 0,
2361 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2362 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2363
2364 /* set the stream id */
2365 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2366 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2367
2368 /* set the stream format */
2369 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2370 AC_VERB_SET_STREAM_FORMAT, format);
2371
2372 /* turn on again (if needed) */
2373 /* enable and set the channel status audio/data flag */
7c935976 2374 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2375 snd_hda_codec_write(codec,
2376 nvhdmi_master_con_nid_7x,
2377 0,
2378 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2379 spdif->ctls & 0xff);
84eb01be
TI		 2380 snd_hda_codec_write(codec,
2381 nvhdmi_master_con_nid_7x,
2382 0,
2383 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2384 }
2385
2386 for (i = 0; i < 4; i++) {
2387 if (chs == 2)
2388 channel_id = 0;
2389 else
2390 channel_id = i * 2;
2391
2392 /* turn off SPDIF once;
2393 *otherwise the IEC958 bits won't be updated
2394 */
2395 if (codec->spdif_status_reset &&
7c935976 2396 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2397 snd_hda_codec_write(codec,
2398 nvhdmi_con_nids_7x[i],
2399 0,
2400 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2401 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2402 /* set the stream id */
2403 snd_hda_codec_write(codec,
2404 nvhdmi_con_nids_7x[i],
2405 0,
2406 AC_VERB_SET_CHANNEL_STREAMID,
2407 (stream_tag << 4) | channel_id);
2408 /* set the stream format */
2409 snd_hda_codec_write(codec,
2410 nvhdmi_con_nids_7x[i],
2411 0,
2412 AC_VERB_SET_STREAM_FORMAT,
2413 format);
2414 /* turn on again (if needed) */
2415 /* enable and set the channel status audio/data flag */
2416 if (codec->spdif_status_reset &&
7c935976 2417 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2418 snd_hda_codec_write(codec,
2419 nvhdmi_con_nids_7x[i],
2420 0,
2421 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2422 spdif->ctls & 0xff);
84eb01be
TI		 2423 snd_hda_codec_write(codec,
2424 nvhdmi_con_nids_7x[i],
2425 0,
2426 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2427 }
2428 }
2429
1f348522 2430 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 2431
2432 mutex_unlock(&codec->spdif_mutex);
2433 return 0;
2434}
2435
fb79e1e0 2436static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 2437 .substreams = 1,
2438 .channels_min = 2,
2439 .channels_max = 8,
2440 .nid = nvhdmi_master_con_nid_7x,
2441 .rates = SUPPORTED_RATES,
2442 .maxbps = SUPPORTED_MAXBPS,
2443 .formats = SUPPORTED_FORMATS,
2444 .ops = {
2445 .open = simple_playback_pcm_open,
2446 .close = nvhdmi_8ch_7x_pcm_close,
2447 .prepare = nvhdmi_8ch_7x_pcm_prepare
2448 },
2449};
2450
84eb01be
TI		 2451static int patch_nvhdmi_2ch(struct hda_codec *codec)
2452{
2453 struct hdmi_spec *spec;
d0b1252d
TI		 2454 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2455 nvhdmi_master_pin_nid_7x);
2456 if (err < 0)
2457 return err;
84eb01be 2458
ceaa86ba 2459 codec->patch_ops.init = nvhdmi_7x_init_2ch;
d0b1252d
TI		 2460 /* override the PCM rates, etc, as the codec doesn't give full list */
2461 spec = codec->spec;
2462 spec->pcm_playback.rates = SUPPORTED_RATES;
2463 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2464 spec->pcm_playback.formats = SUPPORTED_FORMATS;
84eb01be
TI		 2465 return 0;
2466}
2467
53775b0d
TI		 2468static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2469{
2470 struct hdmi_spec *spec = codec->spec;
2471 int err = simple_playback_build_pcms(codec);
bce0d2a8
TI		 2472 if (!err) {
2473 struct hda_pcm *info = get_pcm_rec(spec, 0);
2474 info->own_chmap = true;
2475 }
53775b0d
TI		 2476 return err;
2477}
2478
2479static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2480{
2481 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2482 struct hda_pcm *info;
53775b0d
TI		 2483 struct snd_pcm_chmap *chmap;
2484 int err;
2485
2486 err = simple_playback_build_controls(codec);
2487 if (err < 0)
2488 return err;
2489
2490 /* add channel maps */
bce0d2a8
TI		 2491 info = get_pcm_rec(spec, 0);
2492 err = snd_pcm_add_chmap_ctls(info->pcm,
53775b0d
TI		 2493 SNDRV_PCM_STREAM_PLAYBACK,
2494 snd_pcm_alt_chmaps, 8, 0, &chmap);
2495 if (err < 0)
2496 return err;
2497 switch (codec->preset->id) {
2498 case 0x10de0002:
2499 case 0x10de0003:
2500 case 0x10de0005:
2501 case 0x10de0006:
2502 chmap->channel_mask = (1U << 2) | (1U << 8);
2503 break;
2504 case 0x10de0007:
2505 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2506 }
2507 return 0;
2508}
2509
84eb01be
TI		 2510static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2511{
2512 struct hdmi_spec *spec;
2513 int err = patch_nvhdmi_2ch(codec);
84eb01be
TI		 2514 if (err < 0)
2515 return err;
2516 spec = codec->spec;
2517 spec->multiout.max_channels = 8;
d0b1252d 2518 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
ceaa86ba 2519 codec->patch_ops.init = nvhdmi_7x_init_8ch;
53775b0d
TI		 2520 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2521 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
1f348522
AP		 2522
2523 /* Initialize the audio infoframe channel mask and checksum to something
2524 * valid */
2525 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2526
84eb01be
TI		 2527 return 0;
2528}
2529
2530/*
2531 * ATI-specific implementations
2532 *
2533 * FIXME: we may omit the whole this and use the generic code once after
2534 * it's confirmed to work.
2535 */
2536
2537#define ATIHDMI_CVT_NID 0x02 /* audio converter */
2538#define ATIHDMI_PIN_NID 0x03 /* HDMI output pin */
2539
2540static int atihdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2541 struct hda_codec *codec,
2542 unsigned int stream_tag,
2543 unsigned int format,
2544 struct snd_pcm_substream *substream)
2545{
2546 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2547 struct hdmi_spec_per_cvt *per_cvt = get_cvt(spec, 0);
84eb01be
TI		 2548 int chans = substream->runtime->channels;
2549 int i, err;
2550
2551 err = simple_playback_pcm_prepare(hinfo, codec, stream_tag, format,
2552 substream);
2553 if (err < 0)
2554 return err;
bce0d2a8 2555 snd_hda_codec_write(codec, per_cvt->cvt_nid, 0,
384a48d7 2556 AC_VERB_SET_CVT_CHAN_COUNT, chans - 1);
84eb01be
TI		 2557 /* FIXME: XXX */
2558 for (i = 0; i < chans; i++) {
bce0d2a8 2559 snd_hda_codec_write(codec, per_cvt->cvt_nid, 0,
84eb01be
TI		 2560 AC_VERB_SET_HDMI_CHAN_SLOT,
2561 (i << 4) | i);
2562 }
2563 return 0;
2564}
2565
84eb01be
TI		 2566static int patch_atihdmi(struct hda_codec *codec)
2567{
2568 struct hdmi_spec *spec;
d0b1252d
TI		 2569 int err = patch_simple_hdmi(codec, ATIHDMI_CVT_NID, ATIHDMI_PIN_NID);
2570 if (err < 0)
2571 return err;
2572 spec = codec->spec;
2573 spec->pcm_playback.ops.prepare = atihdmi_playback_pcm_prepare;
84eb01be
TI		 2574 return 0;
2575}
2576
3de5ff88
AL		 2577/* VIA HDMI Implementation */
2578#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
2579#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
2580
3de5ff88
AL		 2581static int patch_via_hdmi(struct hda_codec *codec)
2582{
250e41ac 2583 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3de5ff88 2584}
84eb01be
TI		 2585
2586/*
2587 * patch entries
2588 */
fb79e1e0 2589static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
84eb01be
TI		 2590{ .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
2591{ .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
2592{ .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
36e9c135 2593{ .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 2594{ .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
2595{ .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
2596{ .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
2597{ .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2598{ .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2599{ .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2600{ .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2601{ .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
5d44f927
SW		 2602{ .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_generic_hdmi },
2603{ .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_generic_hdmi },
2604{ .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_generic_hdmi },
2605{ .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_generic_hdmi },
2606{ .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_generic_hdmi },
2607{ .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_generic_hdmi },
2608{ .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_generic_hdmi },
2609{ .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_generic_hdmi },
2610{ .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_generic_hdmi },
2611{ .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_generic_hdmi },
2612{ .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_generic_hdmi },
c8900a0f 2613/* 17 is known to be absent */
5d44f927
SW		 2614{ .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_generic_hdmi },
2615{ .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_generic_hdmi },
2616{ .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_generic_hdmi },
2617{ .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_generic_hdmi },
2618{ .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_generic_hdmi },
2619{ .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_generic_hdmi },
2620{ .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_generic_hdmi },
2621{ .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_generic_hdmi },
2622{ .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_generic_hdmi },
2623{ .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_generic_hdmi },
7ae48b56 2624{ .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_generic_hdmi },
d52392b1 2625{ .id = 0x10de0060, .name = "GPU 60 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 2626{ .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
2627{ .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
3de5ff88
AL		 2628{ .id = 0x11069f80, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
2629{ .id = 0x11069f81, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
2630{ .id = 0x11069f84, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
2631{ .id = 0x11069f85, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 2632{ .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
2633{ .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
2634{ .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
2635{ .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
2636{ .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
2637{ .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
591e610d 2638{ .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
1c76684d 2639{ .id = 0x80862807, .name = "Haswell HDMI", .patch = patch_generic_hdmi },
6edc59e6 2640{ .id = 0x80862880, .name = "CedarTrail HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 2641{ .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
2642{} /* terminator */
2643};
2644
2645MODULE_ALIAS("snd-hda-codec-id:1002793c");
2646MODULE_ALIAS("snd-hda-codec-id:10027919");
2647MODULE_ALIAS("snd-hda-codec-id:1002791a");
2648MODULE_ALIAS("snd-hda-codec-id:1002aa01");
2649MODULE_ALIAS("snd-hda-codec-id:10951390");
2650MODULE_ALIAS("snd-hda-codec-id:10951392");
2651MODULE_ALIAS("snd-hda-codec-id:10de0002");
2652MODULE_ALIAS("snd-hda-codec-id:10de0003");
2653MODULE_ALIAS("snd-hda-codec-id:10de0005");
2654MODULE_ALIAS("snd-hda-codec-id:10de0006");
2655MODULE_ALIAS("snd-hda-codec-id:10de0007");
2656MODULE_ALIAS("snd-hda-codec-id:10de000a");
2657MODULE_ALIAS("snd-hda-codec-id:10de000b");
2658MODULE_ALIAS("snd-hda-codec-id:10de000c");
2659MODULE_ALIAS("snd-hda-codec-id:10de000d");
2660MODULE_ALIAS("snd-hda-codec-id:10de0010");
2661MODULE_ALIAS("snd-hda-codec-id:10de0011");
2662MODULE_ALIAS("snd-hda-codec-id:10de0012");
2663MODULE_ALIAS("snd-hda-codec-id:10de0013");
2664MODULE_ALIAS("snd-hda-codec-id:10de0014");
c8900a0f
RS		 2665MODULE_ALIAS("snd-hda-codec-id:10de0015");
2666MODULE_ALIAS("snd-hda-codec-id:10de0016");
84eb01be
TI		 2667MODULE_ALIAS("snd-hda-codec-id:10de0018");
2668MODULE_ALIAS("snd-hda-codec-id:10de0019");
2669MODULE_ALIAS("snd-hda-codec-id:10de001a");
2670MODULE_ALIAS("snd-hda-codec-id:10de001b");
2671MODULE_ALIAS("snd-hda-codec-id:10de001c");
2672MODULE_ALIAS("snd-hda-codec-id:10de0040");
2673MODULE_ALIAS("snd-hda-codec-id:10de0041");
2674MODULE_ALIAS("snd-hda-codec-id:10de0042");
2675MODULE_ALIAS("snd-hda-codec-id:10de0043");
2676MODULE_ALIAS("snd-hda-codec-id:10de0044");
7ae48b56 2677MODULE_ALIAS("snd-hda-codec-id:10de0051");
d52392b1 2678MODULE_ALIAS("snd-hda-codec-id:10de0060");
84eb01be
TI		 2679MODULE_ALIAS("snd-hda-codec-id:10de0067");
2680MODULE_ALIAS("snd-hda-codec-id:10de8001");
3de5ff88
AL		 2681MODULE_ALIAS("snd-hda-codec-id:11069f80");
2682MODULE_ALIAS("snd-hda-codec-id:11069f81");
2683MODULE_ALIAS("snd-hda-codec-id:11069f84");
2684MODULE_ALIAS("snd-hda-codec-id:11069f85");
84eb01be
TI		 2685MODULE_ALIAS("snd-hda-codec-id:17e80047");
2686MODULE_ALIAS("snd-hda-codec-id:80860054");
2687MODULE_ALIAS("snd-hda-codec-id:80862801");
2688MODULE_ALIAS("snd-hda-codec-id:80862802");
2689MODULE_ALIAS("snd-hda-codec-id:80862803");
2690MODULE_ALIAS("snd-hda-codec-id:80862804");
2691MODULE_ALIAS("snd-hda-codec-id:80862805");
591e610d 2692MODULE_ALIAS("snd-hda-codec-id:80862806");
1c76684d 2693MODULE_ALIAS("snd-hda-codec-id:80862807");
6edc59e6 2694MODULE_ALIAS("snd-hda-codec-id:80862880");
84eb01be
TI		 2695MODULE_ALIAS("snd-hda-codec-id:808629fb");
2696
2697MODULE_LICENSE("GPL");
2698MODULE_DESCRIPTION("HDMI HD-audio codec");
2699MODULE_ALIAS("snd-hda-codec-intelhdmi");
2700MODULE_ALIAS("snd-hda-codec-nvhdmi");
2701MODULE_ALIAS("snd-hda-codec-atihdmi");
2702
2703static struct hda_codec_preset_list intel_list = {
2704 .preset = snd_hda_preset_hdmi,
2705 .owner = THIS_MODULE,
2706};
2707
2708static int __init patch_hdmi_init(void)
2709{
2710 return snd_hda_add_codec_preset(&intel_list);
2711}
2712
2713static void __exit patch_hdmi_exit(void)
2714{
2715 snd_hda_delete_codec_preset(&intel_list);
2716}
2717
2718module_init(patch_hdmi_init)
2719module_exit(patch_hdmi_exit)
Linux kernel - Deliverables
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