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ALSA: compress: change the way sample rates are sent to kernel
[deliverable/linux.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
5a613584 9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
079d88cc
WF		 10 *
11 * Authors:
12 * Wu Fengguang <wfg@linux.intel.com>
13 *
14 * Maintained by:
15 * Wu Fengguang <wfg@linux.intel.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 * for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
84eb01be
TI		 32#include <linux/init.h>
33#include <linux/delay.h>
34#include <linux/slab.h>
65a77217 35#include <linux/module.h>
84eb01be 36#include <sound/core.h>
07acecc1 37#include <sound/jack.h>
433968da 38#include <sound/asoundef.h>
d45e6889 39#include <sound/tlv.h>
84eb01be
TI		 40#include "hda_codec.h"
41#include "hda_local.h"
1835a0f9 42#include "hda_jack.h"
84eb01be 43
0ebaa24c
TI		 44static bool static_hdmi_pcm;
45module_param(static_hdmi_pcm, bool, 0644);
46MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
47
fb87fa3a 48#define is_haswell(codec) ((codec)->vendor_id == 0x80862807)
02383854 49#define is_valleyview(codec) ((codec)->vendor_id == 0x80862882)
fb87fa3a 50
384a48d7
SW		 51struct hdmi_spec_per_cvt {
52 hda_nid_t cvt_nid;
53 int assigned;
54 unsigned int channels_min;
55 unsigned int channels_max;
56 u32 rates;
57 u64 formats;
58 unsigned int maxbps;
59};
079d88cc 60
4eea3091
TI		 61/* max. connections to a widget */
62#define HDA_MAX_CONNECTIONS 32
63
384a48d7
SW		 64struct hdmi_spec_per_pin {
65 hda_nid_t pin_nid;
66 int num_mux_nids;
67 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
1df5a06a 68 hda_nid_t cvt_nid;
744626da
WF		 69
70 struct hda_codec *codec;
384a48d7 71 struct hdmi_eld sink_eld;
a4e9a38b 72 struct mutex lock;
744626da 73 struct delayed_work work;
92c69e79 74 struct snd_kcontrol *eld_ctl;
c6e8453e 75 int repoll_count;
b054087d
TI		 76 bool setup; /* the stream has been set up by prepare callback */
77 int channels; /* current number of channels */
1a6003b5 78 bool non_pcm;
d45e6889
TI		 79 bool chmap_set; /* channel-map override by ALSA API? */
80 unsigned char chmap[8]; /* ALSA API channel-map */
bce0d2a8 81 char pcm_name[8]; /* filled in build_pcm callbacks */
a4e9a38b
TI		 82#ifdef CONFIG_PROC_FS
83 struct snd_info_entry *proc_entry;
84#endif
384a48d7 85};
079d88cc 86
307229d2
AH		 87struct cea_channel_speaker_allocation;
88
89/* operations used by generic code that can be overridden by patches */
90struct hdmi_ops {
91 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
92 unsigned char *buf, int *eld_size);
93
94 /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */
95 int (*pin_get_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
96 int asp_slot);
97 int (*pin_set_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
98 int asp_slot, int channel);
99
100 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
101 int ca, int active_channels, int conn_type);
102
103 /* enable/disable HBR (HD passthrough) */
104 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
105
106 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
107 hda_nid_t pin_nid, u32 stream_tag, int format);
108
109 /* Helpers for producing the channel map TLVs. These can be overridden
110 * for devices that have non-standard mapping requirements. */
111 int (*chmap_cea_alloc_validate_get_type)(struct cea_channel_speaker_allocation *cap,
112 int channels);
113 void (*cea_alloc_to_tlv_chmap)(struct cea_channel_speaker_allocation *cap,
114 unsigned int *chmap, int channels);
115
116 /* check that the user-given chmap is supported */
117 int (*chmap_validate)(int ca, int channels, unsigned char *chmap);
118};
119
384a48d7
SW		 120struct hdmi_spec {
121 int num_cvts;
bce0d2a8
TI		 122 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
123 hda_nid_t cvt_nids[4]; /* only for haswell fix */
079d88cc 124
384a48d7 125 int num_pins;
bce0d2a8
TI		 126 struct snd_array pins; /* struct hdmi_spec_per_pin */
127 struct snd_array pcm_rec; /* struct hda_pcm */
d45e6889 128 unsigned int channels_max; /* max over all cvts */
079d88cc 129
4bd038f9 130 struct hdmi_eld temp_eld;
307229d2 131 struct hdmi_ops ops;
079d88cc 132 /*
5a613584 133 * Non-generic VIA/NVIDIA specific
079d88cc
WF		 134 */
135 struct hda_multi_out multiout;
d0b1252d 136 struct hda_pcm_stream pcm_playback;
079d88cc
WF		 137};
138
139
140struct hdmi_audio_infoframe {
141 u8 type; /* 0x84 */
142 u8 ver; /* 0x01 */
143 u8 len; /* 0x0a */
144
53d7d69d
WF		 145 u8 checksum;
146
079d88cc
WF		 147 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
148 u8 SS01_SF24;
149 u8 CXT04;
150 u8 CA;
151 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 152};
153
154struct dp_audio_infoframe {
155 u8 type; /* 0x84 */
156 u8 len; /* 0x1b */
157 u8 ver; /* 0x11 << 2 */
158
159 u8 CC02_CT47; /* match with HDMI infoframe from this on */
160 u8 SS01_SF24;
161 u8 CXT04;
162 u8 CA;
163 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 164};
165
2b203dbb
TI		 166union audio_infoframe {
167 struct hdmi_audio_infoframe hdmi;
168 struct dp_audio_infoframe dp;
169 u8 bytes[0];
170};
171
079d88cc
WF		 172/*
173 * CEA speaker placement:
174 *
175 * FLH FCH FRH
176 * FLW FL FLC FC FRC FR FRW
177 *
178 * LFE
179 * TC
180 *
181 * RL RLC RC RRC RR
182 *
183 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
184 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
185 */
186enum cea_speaker_placement {
187 FL = (1 << 0), /* Front Left */
188 FC = (1 << 1), /* Front Center */
189 FR = (1 << 2), /* Front Right */
190 FLC = (1 << 3), /* Front Left Center */
191 FRC = (1 << 4), /* Front Right Center */
192 RL = (1 << 5), /* Rear Left */
193 RC = (1 << 6), /* Rear Center */
194 RR = (1 << 7), /* Rear Right */
195 RLC = (1 << 8), /* Rear Left Center */
196 RRC = (1 << 9), /* Rear Right Center */
197 LFE = (1 << 10), /* Low Frequency Effect */
198 FLW = (1 << 11), /* Front Left Wide */
199 FRW = (1 << 12), /* Front Right Wide */
200 FLH = (1 << 13), /* Front Left High */
201 FCH = (1 << 14), /* Front Center High */
202 FRH = (1 << 15), /* Front Right High */
203 TC = (1 << 16), /* Top Center */
204};
205
206/*
207 * ELD SA bits in the CEA Speaker Allocation data block
208 */
209static int eld_speaker_allocation_bits[] = {
210 [0] = FL | FR,
211 [1] = LFE,
212 [2] = FC,
213 [3] = RL | RR,
214 [4] = RC,
215 [5] = FLC | FRC,
216 [6] = RLC | RRC,
217 /* the following are not defined in ELD yet */
218 [7] = FLW | FRW,
219 [8] = FLH | FRH,
220 [9] = TC,
221 [10] = FCH,
222};
223
224struct cea_channel_speaker_allocation {
225 int ca_index;
226 int speakers[8];
227
228 /* derived values, just for convenience */
229 int channels;
230 int spk_mask;
231};
232
233/*
234 * ALSA sequence is:
235 *
236 * surround40 surround41 surround50 surround51 surround71
237 * ch0 front left = = = =
238 * ch1 front right = = = =
239 * ch2 rear left = = = =
240 * ch3 rear right = = = =
241 * ch4 LFE center center center
242 * ch5 LFE LFE
243 * ch6 side left
244 * ch7 side right
245 *
246 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
247 */
248static int hdmi_channel_mapping[0x32][8] = {
249 /* stereo */
250 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
251 /* 2.1 */
252 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
253 /* Dolby Surround */
254 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
255 /* surround40 */
256 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
257 /* 4ch */
258 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
259 /* surround41 */
9396d317 260 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
079d88cc
WF		 261 /* surround50 */
262 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
263 /* surround51 */
264 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
265 /* 7.1 */
266 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
267};
268
269/*
270 * This is an ordered list!
271 *
272 * The preceding ones have better chances to be selected by
53d7d69d 273 * hdmi_channel_allocation().
079d88cc
WF		 274 */
275static struct cea_channel_speaker_allocation channel_allocations[] = {
276/* channel: 7 6 5 4 3 2 1 0 */
277{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
278 /* 2.1 */
279{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
280 /* Dolby Surround */
281{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
282 /* surround40 */
283{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
284 /* surround41 */
285{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
286 /* surround50 */
287{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
288 /* surround51 */
289{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
290 /* 6.1 */
291{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
292 /* surround71 */
293{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
294
295{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
296{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
297{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
298{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
299{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
300{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
301{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
302{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
303{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
304{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
305{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
306{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
307{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
308{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
309{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
310{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
311{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
312{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
313{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
314{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
315{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
316{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
317{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
318{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
319{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
320{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
321{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
322{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
323{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
324{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
325{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
326{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
327{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
328{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
329{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
330{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
331{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
332{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
333{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
334{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
335{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
336};
337
338
339/*
340 * HDMI routines
341 */
342
bce0d2a8
TI		 343#define get_pin(spec, idx) \
344 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
345#define get_cvt(spec, idx) \
346 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
347#define get_pcm_rec(spec, idx) \
348 ((struct hda_pcm *)snd_array_elem(&spec->pcm_rec, idx))
349
384a48d7 350static int pin_nid_to_pin_index(struct hdmi_spec *spec, hda_nid_t pin_nid)
079d88cc 351{
384a48d7 352 int pin_idx;
079d88cc 353
384a48d7 354 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 355 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
384a48d7 356 return pin_idx;
079d88cc 357
384a48d7
SW		 358 snd_printk(KERN_WARNING "HDMI: pin nid %d not registered\n", pin_nid);
359 return -EINVAL;
360}
361
362static int hinfo_to_pin_index(struct hdmi_spec *spec,
363 struct hda_pcm_stream *hinfo)
364{
365 int pin_idx;
366
367 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 368 if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
384a48d7
SW		 369 return pin_idx;
370
371 snd_printk(KERN_WARNING "HDMI: hinfo %p not registered\n", hinfo);
372 return -EINVAL;
373}
374
375static int cvt_nid_to_cvt_index(struct hdmi_spec *spec, hda_nid_t cvt_nid)
376{
377 int cvt_idx;
378
379 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
bce0d2a8 380 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
384a48d7
SW		 381 return cvt_idx;
382
383 snd_printk(KERN_WARNING "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 384 return -EINVAL;
385}
386
14bc52b8
PLB		 387static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
388 struct snd_ctl_elem_info *uinfo)
389{
390 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 391 struct hdmi_spec *spec = codec->spec;
a4e9a38b 392 struct hdmi_spec_per_pin *per_pin;
68e03de9 393 struct hdmi_eld *eld;
14bc52b8
PLB		 394 int pin_idx;
395
14bc52b8
PLB		 396 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
397
398 pin_idx = kcontrol->private_value;
a4e9a38b
TI		 399 per_pin = get_pin(spec, pin_idx);
400 eld = &per_pin->sink_eld;
68e03de9 401
a4e9a38b 402 mutex_lock(&per_pin->lock);
68e03de9 403 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
a4e9a38b 404 mutex_unlock(&per_pin->lock);
14bc52b8
PLB		 405
406 return 0;
407}
408
409static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
410 struct snd_ctl_elem_value *ucontrol)
411{
412 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 413 struct hdmi_spec *spec = codec->spec;
a4e9a38b 414 struct hdmi_spec_per_pin *per_pin;
68e03de9 415 struct hdmi_eld *eld;
14bc52b8
PLB		 416 int pin_idx;
417
14bc52b8 418 pin_idx = kcontrol->private_value;
a4e9a38b
TI		 419 per_pin = get_pin(spec, pin_idx);
420 eld = &per_pin->sink_eld;
68e03de9 421
a4e9a38b 422 mutex_lock(&per_pin->lock);
68e03de9 423 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) {
a4e9a38b 424 mutex_unlock(&per_pin->lock);
68e03de9
DH		 425 snd_BUG();
426 return -EINVAL;
427 }
428
429 memset(ucontrol->value.bytes.data, 0,
430 ARRAY_SIZE(ucontrol->value.bytes.data));
431 if (eld->eld_valid)
432 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
433 eld->eld_size);
a4e9a38b 434 mutex_unlock(&per_pin->lock);
14bc52b8
PLB		 435
436 return 0;
437}
438
439static struct snd_kcontrol_new eld_bytes_ctl = {
440 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
441 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
442 .name = "ELD",
443 .info = hdmi_eld_ctl_info,
444 .get = hdmi_eld_ctl_get,
445};
446
447static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
448 int device)
449{
450 struct snd_kcontrol *kctl;
451 struct hdmi_spec *spec = codec->spec;
452 int err;
453
454 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
455 if (!kctl)
456 return -ENOMEM;
457 kctl->private_value = pin_idx;
458 kctl->id.device = device;
459
bce0d2a8 460 err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
14bc52b8
PLB		 461 if (err < 0)
462 return err;
463
bce0d2a8 464 get_pin(spec, pin_idx)->eld_ctl = kctl;
14bc52b8
PLB		 465 return 0;
466}
467
079d88cc
WF		 468#ifdef BE_PARANOID
469static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
470 int *packet_index, int *byte_index)
471{
472 int val;
473
474 val = snd_hda_codec_read(codec, pin_nid, 0,
475 AC_VERB_GET_HDMI_DIP_INDEX, 0);
476
477 *packet_index = val >> 5;
478 *byte_index = val & 0x1f;
479}
480#endif
481
482static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
483 int packet_index, int byte_index)
484{
485 int val;
486
487 val = (packet_index << 5) | (byte_index & 0x1f);
488
489 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
490}
491
492static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
493 unsigned char val)
494{
495 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
496}
497
384a48d7 498static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc
WF		 499{
500 /* Unmute */
501 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
502 snd_hda_codec_write(codec, pin_nid, 0,
503 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
6169b673
TI		 504 /* Enable pin out: some machines with GM965 gets broken output when
505 * the pin is disabled or changed while using with HDMI
506 */
079d88cc 507 snd_hda_codec_write(codec, pin_nid, 0,
6169b673 508 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
079d88cc
WF		 509}
510
384a48d7 511static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc 512{
384a48d7 513 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
079d88cc
WF		 514 AC_VERB_GET_CVT_CHAN_COUNT, 0);
515}
516
517static void hdmi_set_channel_count(struct hda_codec *codec,
384a48d7 518 hda_nid_t cvt_nid, int chs)
079d88cc 519{
384a48d7
SW		 520 if (chs != hdmi_get_channel_count(codec, cvt_nid))
521 snd_hda_codec_write(codec, cvt_nid, 0,
079d88cc
WF		 522 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
523}
524
a4e9a38b
TI		 525/*
526 * ELD proc files
527 */
528
529#ifdef CONFIG_PROC_FS
530static void print_eld_info(struct snd_info_entry *entry,
531 struct snd_info_buffer *buffer)
532{
533 struct hdmi_spec_per_pin *per_pin = entry->private_data;
534
535 mutex_lock(&per_pin->lock);
536 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
537 mutex_unlock(&per_pin->lock);
538}
539
540static void write_eld_info(struct snd_info_entry *entry,
541 struct snd_info_buffer *buffer)
542{
543 struct hdmi_spec_per_pin *per_pin = entry->private_data;
544
545 mutex_lock(&per_pin->lock);
546 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
547 mutex_unlock(&per_pin->lock);
548}
549
550static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
551{
552 char name[32];
553 struct hda_codec *codec = per_pin->codec;
554 struct snd_info_entry *entry;
555 int err;
556
557 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
558 err = snd_card_proc_new(codec->bus->card, name, &entry);
559 if (err < 0)
560 return err;
561
562 snd_info_set_text_ops(entry, per_pin, print_eld_info);
563 entry->c.text.write = write_eld_info;
564 entry->mode |= S_IWUSR;
565 per_pin->proc_entry = entry;
566
567 return 0;
568}
569
570static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
571{
572 if (!per_pin->codec->bus->shutdown && per_pin->proc_entry) {
573 snd_device_free(per_pin->codec->bus->card, per_pin->proc_entry);
574 per_pin->proc_entry = NULL;
575 }
576}
577#else
b55447a7
TI		 578static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
579 int index)
a4e9a38b
TI		 580{
581 return 0;
582}
b55447a7 583static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
a4e9a38b
TI		 584{
585}
586#endif
079d88cc
WF		 587
588/*
589 * Channel mapping routines
590 */
591
592/*
593 * Compute derived values in channel_allocations[].
594 */
595static void init_channel_allocations(void)
596{
597 int i, j;
598 struct cea_channel_speaker_allocation *p;
599
600 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
601 p = channel_allocations + i;
602 p->channels = 0;
603 p->spk_mask = 0;
604 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
605 if (p->speakers[j]) {
606 p->channels++;
607 p->spk_mask |= p->speakers[j];
608 }
609 }
610}
611
72357c78
WX		 612static int get_channel_allocation_order(int ca)
613{
614 int i;
615
616 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
617 if (channel_allocations[i].ca_index == ca)
618 break;
619 }
620 return i;
621}
622
079d88cc
WF		 623/*
624 * The transformation takes two steps:
625 *
626 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
627 * spk_mask => (channel_allocations[]) => ai->CA
628 *
629 * TODO: it could select the wrong CA from multiple candidates.
630*/
384a48d7 631static int hdmi_channel_allocation(struct hdmi_eld *eld, int channels)
079d88cc 632{
079d88cc 633 int i;
53d7d69d 634 int ca = 0;
079d88cc 635 int spk_mask = 0;
079d88cc
WF		 636 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
637
638 /*
639 * CA defaults to 0 for basic stereo audio
640 */
641 if (channels <= 2)
642 return 0;
643
079d88cc
WF		 644 /*
645 * expand ELD's speaker allocation mask
646 *
647 * ELD tells the speaker mask in a compact(paired) form,
648 * expand ELD's notions to match the ones used by Audio InfoFrame.
649 */
650 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
1613d6b4 651 if (eld->info.spk_alloc & (1 << i))
079d88cc
WF		 652 spk_mask |= eld_speaker_allocation_bits[i];
653 }
654
655 /* search for the first working match in the CA table */
656 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
657 if (channels == channel_allocations[i].channels &&
658 (spk_mask & channel_allocations[i].spk_mask) ==
659 channel_allocations[i].spk_mask) {
53d7d69d 660 ca = channel_allocations[i].ca_index;
079d88cc
WF		 661 break;
662 }
663 }
664
18e39186
AH		 665 if (!ca) {
666 /* if there was no match, select the regular ALSA channel
667 * allocation with the matching number of channels */
668 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
669 if (channels == channel_allocations[i].channels) {
670 ca = channel_allocations[i].ca_index;
671 break;
672 }
673 }
674 }
675
1613d6b4 676 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
2abbf439 677 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
53d7d69d 678 ca, channels, buf);
079d88cc 679
53d7d69d 680 return ca;
079d88cc
WF		 681}
682
683static void hdmi_debug_channel_mapping(struct hda_codec *codec,
684 hda_nid_t pin_nid)
685{
686#ifdef CONFIG_SND_DEBUG_VERBOSE
307229d2 687 struct hdmi_spec *spec = codec->spec;
079d88cc 688 int i;
307229d2 689 int channel;
079d88cc
WF		 690
691 for (i = 0; i < 8; i++) {
307229d2 692 channel = spec->ops.pin_get_slot_channel(codec, pin_nid, i);
079d88cc 693 printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n",
307229d2 694 channel, i);
079d88cc
WF		 695 }
696#endif
697}
698
d45e6889 699static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
079d88cc 700 hda_nid_t pin_nid,
433968da 701 bool non_pcm,
53d7d69d 702 int ca)
079d88cc 703{
307229d2 704 struct hdmi_spec *spec = codec->spec;
90f28002 705 struct cea_channel_speaker_allocation *ch_alloc;
079d88cc 706 int i;
079d88cc 707 int err;
72357c78 708 int order;
433968da 709 int non_pcm_mapping[8];
079d88cc 710
72357c78 711 order = get_channel_allocation_order(ca);
90f28002 712 ch_alloc = &channel_allocations[order];
433968da 713
079d88cc 714 if (hdmi_channel_mapping[ca][1] == 0) {
90f28002
AH		 715 int hdmi_slot = 0;
716 /* fill actual channel mappings in ALSA channel (i) order */
717 for (i = 0; i < ch_alloc->channels; i++) {
718 while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
719 hdmi_slot++; /* skip zero slots */
720
721 hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
722 }
723 /* fill the rest of the slots with ALSA channel 0xf */
724 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
725 if (!ch_alloc->speakers[7 - hdmi_slot])
726 hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
079d88cc
WF		 727 }
728
433968da 729 if (non_pcm) {
90f28002 730 for (i = 0; i < ch_alloc->channels; i++)
11f7c52d 731 non_pcm_mapping[i] = (i << 4) | i;
433968da 732 for (; i < 8; i++)
11f7c52d 733 non_pcm_mapping[i] = (0xf << 4) | i;
433968da
WX		 734 }
735
079d88cc 736 for (i = 0; i < 8; i++) {
307229d2
AH		 737 int slotsetup = non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i];
738 int hdmi_slot = slotsetup & 0x0f;
739 int channel = (slotsetup & 0xf0) >> 4;
740 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, channel);
079d88cc 741 if (err) {
2abbf439
WF		 742 snd_printdd(KERN_NOTICE
743 "HDMI: channel mapping failed\n");
079d88cc
WF		 744 break;
745 }
746 }
079d88cc
WF		 747}
748
d45e6889
TI		 749struct channel_map_table {
750 unsigned char map; /* ALSA API channel map position */
d45e6889
TI		 751 int spk_mask; /* speaker position bit mask */
752};
753
754static struct channel_map_table map_tables[] = {
a5b7d510
AH		 755 { SNDRV_CHMAP_FL, FL },
756 { SNDRV_CHMAP_FR, FR },
757 { SNDRV_CHMAP_RL, RL },
758 { SNDRV_CHMAP_RR, RR },
759 { SNDRV_CHMAP_LFE, LFE },
760 { SNDRV_CHMAP_FC, FC },
761 { SNDRV_CHMAP_RLC, RLC },
762 { SNDRV_CHMAP_RRC, RRC },
763 { SNDRV_CHMAP_RC, RC },
764 { SNDRV_CHMAP_FLC, FLC },
765 { SNDRV_CHMAP_FRC, FRC },
94908a39
AH		 766 { SNDRV_CHMAP_TFL, FLH },
767 { SNDRV_CHMAP_TFR, FRH },
a5b7d510
AH		 768 { SNDRV_CHMAP_FLW, FLW },
769 { SNDRV_CHMAP_FRW, FRW },
770 { SNDRV_CHMAP_TC, TC },
94908a39 771 { SNDRV_CHMAP_TFC, FCH },
d45e6889
TI		 772 {} /* terminator */
773};
774
775/* from ALSA API channel position to speaker bit mask */
776static int to_spk_mask(unsigned char c)
777{
778 struct channel_map_table *t = map_tables;
779 for (; t->map; t++) {
780 if (t->map == c)
781 return t->spk_mask;
782 }
783 return 0;
784}
785
786/* from ALSA API channel position to CEA slot */
a5b7d510 787static int to_cea_slot(int ordered_ca, unsigned char pos)
d45e6889 788{
a5b7d510
AH		 789 int mask = to_spk_mask(pos);
790 int i;
d45e6889 791
a5b7d510
AH		 792 if (mask) {
793 for (i = 0; i < 8; i++) {
794 if (channel_allocations[ordered_ca].speakers[7 - i] == mask)
795 return i;
796 }
d45e6889 797 }
a5b7d510
AH		 798
799 return -1;
d45e6889
TI		 800}
801
802/* from speaker bit mask to ALSA API channel position */
803static int spk_to_chmap(int spk)
804{
805 struct channel_map_table *t = map_tables;
806 for (; t->map; t++) {
807 if (t->spk_mask == spk)
808 return t->map;
809 }
810 return 0;
811}
812
a5b7d510
AH		 813/* from CEA slot to ALSA API channel position */
814static int from_cea_slot(int ordered_ca, unsigned char slot)
815{
816 int mask = channel_allocations[ordered_ca].speakers[7 - slot];
817
818 return spk_to_chmap(mask);
819}
820
d45e6889
TI		 821/* get the CA index corresponding to the given ALSA API channel map */
822static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
823{
824 int i, spks = 0, spk_mask = 0;
825
826 for (i = 0; i < chs; i++) {
827 int mask = to_spk_mask(map[i]);
828 if (mask) {
829 spk_mask |= mask;
830 spks++;
831 }
832 }
833
834 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
835 if ((chs == channel_allocations[i].channels ||
836 spks == channel_allocations[i].channels) &&
837 (spk_mask & channel_allocations[i].spk_mask) ==
838 channel_allocations[i].spk_mask)
839 return channel_allocations[i].ca_index;
840 }
841 return -1;
842}
843
844/* set up the channel slots for the given ALSA API channel map */
845static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
846 hda_nid_t pin_nid,
a5b7d510
AH		 847 int chs, unsigned char *map,
848 int ca)
d45e6889 849{
307229d2 850 struct hdmi_spec *spec = codec->spec;
a5b7d510 851 int ordered_ca = get_channel_allocation_order(ca);
11f7c52d
AH		 852 int alsa_pos, hdmi_slot;
853 int assignments[8] = {[0 ... 7] = 0xf};
854
855 for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) {
856
a5b7d510 857 hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]);
11f7c52d
AH		 858
859 if (hdmi_slot < 0)
860 continue; /* unassigned channel */
861
862 assignments[hdmi_slot] = alsa_pos;
863 }
864
865 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) {
307229d2 866 int err;
11f7c52d 867
307229d2
AH		 868 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot,
869 assignments[hdmi_slot]);
d45e6889
TI		 870 if (err)
871 return -EINVAL;
872 }
873 return 0;
874}
875
876/* store ALSA API channel map from the current default map */
877static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
878{
879 int i;
56cac413 880 int ordered_ca = get_channel_allocation_order(ca);
d45e6889 881 for (i = 0; i < 8; i++) {
56cac413 882 if (i < channel_allocations[ordered_ca].channels)
a5b7d510 883 map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f);
d45e6889
TI		 884 else
885 map[i] = 0;
886 }
887}
888
889static void hdmi_setup_channel_mapping(struct hda_codec *codec,
890 hda_nid_t pin_nid, bool non_pcm, int ca,
20608731
AH		 891 int channels, unsigned char *map,
892 bool chmap_set)
d45e6889 893{
20608731 894 if (!non_pcm && chmap_set) {
d45e6889 895 hdmi_manual_setup_channel_mapping(codec, pin_nid,
a5b7d510 896 channels, map, ca);
d45e6889
TI		 897 } else {
898 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
899 hdmi_setup_fake_chmap(map, ca);
900 }
980b2495
AH		 901
902 hdmi_debug_channel_mapping(codec, pin_nid);
d45e6889 903}
079d88cc 904
307229d2
AH		 905static int hdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
906 int asp_slot, int channel)
907{
908 return snd_hda_codec_write(codec, pin_nid, 0,
909 AC_VERB_SET_HDMI_CHAN_SLOT,
910 (channel << 4) | asp_slot);
911}
912
913static int hdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
914 int asp_slot)
915{
916 return (snd_hda_codec_read(codec, pin_nid, 0,
917 AC_VERB_GET_HDMI_CHAN_SLOT,
918 asp_slot) & 0xf0) >> 4;
919}
920
079d88cc
WF		 921/*
922 * Audio InfoFrame routines
923 */
924
925/*
926 * Enable Audio InfoFrame Transmission
927 */
928static void hdmi_start_infoframe_trans(struct hda_codec *codec,
929 hda_nid_t pin_nid)
930{
931 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
932 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
933 AC_DIPXMIT_BEST);
934}
935
936/*
937 * Disable Audio InfoFrame Transmission
938 */
939static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
940 hda_nid_t pin_nid)
941{
942 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
943 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
944 AC_DIPXMIT_DISABLE);
945}
946
947static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
948{
949#ifdef CONFIG_SND_DEBUG_VERBOSE
950 int i;
951 int size;
952
953 size = snd_hdmi_get_eld_size(codec, pin_nid);
954 printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size);
955
956 for (i = 0; i < 8; i++) {
957 size = snd_hda_codec_read(codec, pin_nid, 0,
958 AC_VERB_GET_HDMI_DIP_SIZE, i);
959 printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size);
960 }
961#endif
962}
963
964static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
965{
966#ifdef BE_PARANOID
967 int i, j;
968 int size;
969 int pi, bi;
970 for (i = 0; i < 8; i++) {
971 size = snd_hda_codec_read(codec, pin_nid, 0,
972 AC_VERB_GET_HDMI_DIP_SIZE, i);
973 if (size == 0)
974 continue;
975
976 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
977 for (j = 1; j < 1000; j++) {
978 hdmi_write_dip_byte(codec, pin_nid, 0x0);
979 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
980 if (pi != i)
981 snd_printd(KERN_INFO "dip index %d: %d != %d\n",
982 bi, pi, i);
983 if (bi == 0) /* byte index wrapped around */
984 break;
985 }
986 snd_printd(KERN_INFO
987 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
988 i, size, j);
989 }
990#endif
991}
992
53d7d69d 993static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 994{
53d7d69d 995 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 996 u8 sum = 0;
997 int i;
998
53d7d69d 999 hdmi_ai->checksum = 0;
079d88cc 1000
53d7d69d 1001 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 1002 sum += bytes[i];
1003
53d7d69d 1004 hdmi_ai->checksum = -sum;
079d88cc
WF		 1005}
1006
1007static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
1008 hda_nid_t pin_nid,
53d7d69d 1009 u8 *dip, int size)
079d88cc 1010{
079d88cc
WF		 1011 int i;
1012
1013 hdmi_debug_dip_size(codec, pin_nid);
1014 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
1015
079d88cc 1016 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 1017 for (i = 0; i < size; i++)
1018 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 1019}
1020
1021static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 1022 u8 *dip, int size)
079d88cc 1023{
079d88cc
WF		 1024 u8 val;
1025 int i;
1026
1027 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
1028 != AC_DIPXMIT_BEST)
1029 return false;
1030
1031 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 1032 for (i = 0; i < size; i++) {
079d88cc
WF		 1033 val = snd_hda_codec_read(codec, pin_nid, 0,
1034 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 1035 if (val != dip[i])
079d88cc
WF		 1036 return false;
1037 }
1038
1039 return true;
1040}
1041
307229d2
AH		 1042static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
1043 hda_nid_t pin_nid,
1044 int ca, int active_channels,
1045 int conn_type)
1046{
1047 union audio_infoframe ai;
1048
1049 if (conn_type == 0) { /* HDMI */
1050 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
1051
1052 hdmi_ai->type = 0x84;
1053 hdmi_ai->ver = 0x01;
1054 hdmi_ai->len = 0x0a;
1055 hdmi_ai->CC02_CT47 = active_channels - 1;
1056 hdmi_ai->CA = ca;
1057 hdmi_checksum_audio_infoframe(hdmi_ai);
1058 } else if (conn_type == 1) { /* DisplayPort */
1059 struct dp_audio_infoframe *dp_ai = &ai.dp;
1060
1061 dp_ai->type = 0x84;
1062 dp_ai->len = 0x1b;
1063 dp_ai->ver = 0x11 << 2;
1064 dp_ai->CC02_CT47 = active_channels - 1;
1065 dp_ai->CA = ca;
1066 } else {
1067 snd_printd("HDMI: unknown connection type at pin %d\n",
1068 pin_nid);
1069 return;
1070 }
1071
1072 /*
1073 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
1074 * sizeof(*dp_ai) to avoid partial match/update problems when
1075 * the user switches between HDMI/DP monitors.
1076 */
1077 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
1078 sizeof(ai))) {
1079 snd_printdd("hdmi_pin_setup_infoframe: "
1080 "pin=%d channels=%d ca=0x%02x\n",
1081 pin_nid,
1082 active_channels, ca);
1083 hdmi_stop_infoframe_trans(codec, pin_nid);
1084 hdmi_fill_audio_infoframe(codec, pin_nid,
1085 ai.bytes, sizeof(ai));
1086 hdmi_start_infoframe_trans(codec, pin_nid);
1087 }
1088}
1089
b054087d
TI		 1090static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
1091 struct hdmi_spec_per_pin *per_pin,
1092 bool non_pcm)
079d88cc 1093{
307229d2 1094 struct hdmi_spec *spec = codec->spec;
384a48d7 1095 hda_nid_t pin_nid = per_pin->pin_nid;
b054087d 1096 int channels = per_pin->channels;
1df5a06a 1097 int active_channels;
384a48d7 1098 struct hdmi_eld *eld;
1df5a06a 1099 int ca, ordered_ca;
079d88cc 1100
b054087d
TI		 1101 if (!channels)
1102 return;
1103
58f7d28d
ML		 1104 if (is_haswell(codec))
1105 snd_hda_codec_write(codec, pin_nid, 0,
1106 AC_VERB_SET_AMP_GAIN_MUTE,
1107 AMP_OUT_UNMUTE);
1108
bce0d2a8 1109 eld = &per_pin->sink_eld;
384a48d7
SW		 1110 if (!eld->monitor_present)
1111 return;
079d88cc 1112
d45e6889
TI		 1113 if (!non_pcm && per_pin->chmap_set)
1114 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
1115 else
1116 ca = hdmi_channel_allocation(eld, channels);
1117 if (ca < 0)
1118 ca = 0;
384a48d7 1119
1df5a06a
AH		 1120 ordered_ca = get_channel_allocation_order(ca);
1121 active_channels = channel_allocations[ordered_ca].channels;
1122
1123 hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels);
1124
39edac70
AH		 1125 /*
1126 * always configure channel mapping, it may have been changed by the
1127 * user in the meantime
1128 */
1129 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
1130 channels, per_pin->chmap,
1131 per_pin->chmap_set);
1132
307229d2
AH		 1133 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
1134 eld->info.conn_type);
433968da 1135
1a6003b5 1136 per_pin->non_pcm = non_pcm;
079d88cc
WF		 1137}
1138
079d88cc
WF		 1139/*
1140 * Unsolicited events
1141 */
1142
efe47108 1143static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
38faddb1 1144
20ce9029 1145static void jack_callback(struct hda_codec *codec, struct hda_jack_tbl *jack)
079d88cc
WF		 1146{
1147 struct hdmi_spec *spec = codec->spec;
20ce9029
DH		 1148 int pin_idx = pin_nid_to_pin_index(spec, jack->nid);
1149 if (pin_idx < 0)
1150 return;
1151
1152 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
1153 snd_hda_jack_report_sync(codec);
1154}
1155
1156static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
1157{
3a93897e 1158 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
3a93897e 1159 struct hda_jack_tbl *jack;
2e59e5ab 1160 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
3a93897e
TI		 1161
1162 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
1163 if (!jack)
1164 return;
3a93897e 1165 jack->jack_dirty = 1;
079d88cc 1166
fae3d88a 1167 _snd_printd(SND_PR_VERBOSE,
2e59e5ab 1168 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
20ce9029 1169 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
fae3d88a 1170 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
079d88cc 1171
20ce9029 1172 jack_callback(codec, jack);
079d88cc
WF		 1173}
1174
1175static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
1176{
1177 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1178 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1179 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
1180 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
1181
1182 printk(KERN_INFO
e9ea8e8f 1183 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
384a48d7 1184 codec->addr,
079d88cc
WF		 1185 tag,
1186 subtag,
1187 cp_state,
1188 cp_ready);
1189
1190 /* TODO */
1191 if (cp_state)
1192 ;
1193 if (cp_ready)
1194 ;
1195}
1196
1197
1198static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1199{
079d88cc
WF		 1200 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1201 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1202
3a93897e 1203 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
079d88cc
WF		 1204 snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag);
1205 return;
1206 }
1207
1208 if (subtag == 0)
1209 hdmi_intrinsic_event(codec, res);
1210 else
1211 hdmi_non_intrinsic_event(codec, res);
1212}
1213
58f7d28d 1214static void haswell_verify_D0(struct hda_codec *codec,
53b434f0 1215 hda_nid_t cvt_nid, hda_nid_t nid)
83f26ad2 1216{
58f7d28d 1217 int pwr;
83f26ad2 1218
53b434f0
WX		 1219 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1220 * thus pins could only choose converter 0 for use. Make sure the
1221 * converters are in correct power state */
fd678cac 1222 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
53b434f0
WX		 1223 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1224
fd678cac 1225 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
83f26ad2
DH		 1226 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1227 AC_PWRST_D0);
1228 msleep(40);
1229 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1230 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
1231 snd_printd("Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
1232 }
83f26ad2
DH		 1233}
1234
079d88cc
WF		 1235/*
1236 * Callbacks
1237 */
1238
92f10b3f
TI		 1239/* HBR should be Non-PCM, 8 channels */
1240#define is_hbr_format(format) \
1241 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1242
307229d2
AH		 1243static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
1244 bool hbr)
079d88cc 1245{
307229d2 1246 int pinctl, new_pinctl;
83f26ad2 1247
384a48d7
SW		 1248 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1249 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 1250 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1251
13122e6e
AH		 1252 if (pinctl < 0)
1253 return hbr ? -EINVAL : 0;
1254
ea87d1c4 1255 new_pinctl = pinctl & ~AC_PINCTL_EPT;
307229d2 1256 if (hbr)
ea87d1c4
AH		 1257 new_pinctl |= AC_PINCTL_EPT_HBR;
1258 else
1259 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1260
307229d2 1261 snd_printdd("hdmi_pin_hbr_setup: "
ea87d1c4 1262 "NID=0x%x, %spinctl=0x%x\n",
384a48d7 1263 pin_nid,
ea87d1c4
AH		 1264 pinctl == new_pinctl ? "" : "new-",
1265 new_pinctl);
1266
1267 if (pinctl != new_pinctl)
384a48d7 1268 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 1269 AC_VERB_SET_PIN_WIDGET_CONTROL,
1270 new_pinctl);
307229d2
AH		 1271 } else if (hbr)
1272 return -EINVAL;
ea87d1c4 1273
307229d2
AH		 1274 return 0;
1275}
1276
1277static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1278 hda_nid_t pin_nid, u32 stream_tag, int format)
1279{
1280 struct hdmi_spec *spec = codec->spec;
1281 int err;
1282
1283 if (is_haswell(codec))
1284 haswell_verify_D0(codec, cvt_nid, pin_nid);
1285
1286 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
1287
1288 if (err) {
ea87d1c4 1289 snd_printdd("hdmi_setup_stream: HBR is not supported\n");
307229d2 1290 return err;
ea87d1c4 1291 }
079d88cc 1292
384a48d7 1293 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 1294 return 0;
079d88cc
WF		 1295}
1296
7ef166b8
WX		 1297static int hdmi_choose_cvt(struct hda_codec *codec,
1298 int pin_idx, int *cvt_id, int *mux_id)
bbbe3390
TI		 1299{
1300 struct hdmi_spec *spec = codec->spec;
384a48d7 1301 struct hdmi_spec_per_pin *per_pin;
384a48d7 1302 struct hdmi_spec_per_cvt *per_cvt = NULL;
7ef166b8 1303 int cvt_idx, mux_idx = 0;
bbbe3390 1304
bce0d2a8 1305 per_pin = get_pin(spec, pin_idx);
384a48d7
SW		 1306
1307 /* Dynamically assign converter to stream */
1308 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
bce0d2a8 1309 per_cvt = get_cvt(spec, cvt_idx);
bbbe3390 1310
384a48d7
SW		 1311 /* Must not already be assigned */
1312 if (per_cvt->assigned)
1313 continue;
1314 /* Must be in pin's mux's list of converters */
1315 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1316 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1317 break;
1318 /* Not in mux list */
1319 if (mux_idx == per_pin->num_mux_nids)
1320 continue;
1321 break;
1322 }
7ef166b8 1323
384a48d7
SW		 1324 /* No free converters */
1325 if (cvt_idx == spec->num_cvts)
1326 return -ENODEV;
1327
7ef166b8
WX		 1328 if (cvt_id)
1329 *cvt_id = cvt_idx;
1330 if (mux_id)
1331 *mux_id = mux_idx;
1332
1333 return 0;
1334}
1335
300016b9
ML		 1336/* Intel HDMI workaround to fix audio routing issue:
1337 * For some Intel display codecs, pins share the same connection list.
1338 * So a conveter can be selected by multiple pins and playback on any of these
1339 * pins will generate sound on the external display, because audio flows from
1340 * the same converter to the display pipeline. Also muting one pin may make
1341 * other pins have no sound output.
1342 * So this function assures that an assigned converter for a pin is not selected
1343 * by any other pins.
1344 */
1345static void intel_not_share_assigned_cvt(struct hda_codec *codec,
f82d7d16 1346 hda_nid_t pin_nid, int mux_idx)
7ef166b8
WX		 1347{
1348 struct hdmi_spec *spec = codec->spec;
f82d7d16
ML		 1349 hda_nid_t nid, end_nid;
1350 int cvt_idx, curr;
1351 struct hdmi_spec_per_cvt *per_cvt;
7ef166b8 1352
f82d7d16
ML		 1353 /* configure all pins, including "no physical connection" ones */
1354 end_nid = codec->start_nid + codec->num_nodes;
1355 for (nid = codec->start_nid; nid < end_nid; nid++) {
1356 unsigned int wid_caps = get_wcaps(codec, nid);
1357 unsigned int wid_type = get_wcaps_type(wid_caps);
1358
1359 if (wid_type != AC_WID_PIN)
1360 continue;
7ef166b8 1361
f82d7d16 1362 if (nid == pin_nid)
7ef166b8
WX		 1363 continue;
1364
f82d7d16 1365 curr = snd_hda_codec_read(codec, nid, 0,
7ef166b8 1366 AC_VERB_GET_CONNECT_SEL, 0);
f82d7d16
ML		 1367 if (curr != mux_idx)
1368 continue;
7ef166b8 1369
f82d7d16
ML		 1370 /* choose an unassigned converter. The conveters in the
1371 * connection list are in the same order as in the codec.
1372 */
1373 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1374 per_cvt = get_cvt(spec, cvt_idx);
1375 if (!per_cvt->assigned) {
1376 snd_printdd("choose cvt %d for pin nid %d\n",
1377 cvt_idx, nid);
1378 snd_hda_codec_write_cache(codec, nid, 0,
7ef166b8 1379 AC_VERB_SET_CONNECT_SEL,
f82d7d16
ML		 1380 cvt_idx);
1381 break;
1382 }
7ef166b8
WX		 1383 }
1384 }
1385}
1386
1387/*
1388 * HDA PCM callbacks
1389 */
1390static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1391 struct hda_codec *codec,
1392 struct snd_pcm_substream *substream)
1393{
1394 struct hdmi_spec *spec = codec->spec;
1395 struct snd_pcm_runtime *runtime = substream->runtime;
1396 int pin_idx, cvt_idx, mux_idx = 0;
1397 struct hdmi_spec_per_pin *per_pin;
1398 struct hdmi_eld *eld;
1399 struct hdmi_spec_per_cvt *per_cvt = NULL;
1400 int err;
1401
1402 /* Validate hinfo */
1403 pin_idx = hinfo_to_pin_index(spec, hinfo);
1404 if (snd_BUG_ON(pin_idx < 0))
1405 return -EINVAL;
1406 per_pin = get_pin(spec, pin_idx);
1407 eld = &per_pin->sink_eld;
1408
1409 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1410 if (err < 0)
1411 return err;
1412
1413 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1414 /* Claim converter */
1415 per_cvt->assigned = 1;
1df5a06a 1416 per_pin->cvt_nid = per_cvt->cvt_nid;
384a48d7
SW		 1417 hinfo->nid = per_cvt->cvt_nid;
1418
bddee96b 1419 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
384a48d7
SW		 1420 AC_VERB_SET_CONNECT_SEL,
1421 mux_idx);
7ef166b8
WX		 1422
1423 /* configure unused pins to choose other converters */
02383854 1424 if (is_haswell(codec) || is_valleyview(codec))
300016b9 1425 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx);
7ef166b8 1426
384a48d7 1427 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
bbbe3390 1428
2def8172 1429 /* Initially set the converter's capabilities */
384a48d7
SW		 1430 hinfo->channels_min = per_cvt->channels_min;
1431 hinfo->channels_max = per_cvt->channels_max;
1432 hinfo->rates = per_cvt->rates;
1433 hinfo->formats = per_cvt->formats;
1434 hinfo->maxbps = per_cvt->maxbps;
2def8172 1435
384a48d7 1436 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 1437 if (!static_hdmi_pcm && eld->eld_valid) {
1613d6b4 1438 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
bbbe3390 1439 if (hinfo->channels_min > hinfo->channels_max ||
2ad779b7
TI		 1440 !hinfo->rates || !hinfo->formats) {
1441 per_cvt->assigned = 0;
1442 hinfo->nid = 0;
1443 snd_hda_spdif_ctls_unassign(codec, pin_idx);
bbbe3390 1444 return -ENODEV;
2ad779b7 1445 }
bbbe3390 1446 }
2def8172
SW		 1447
1448 /* Store the updated parameters */
639cef0e
TI		 1449 runtime->hw.channels_min = hinfo->channels_min;
1450 runtime->hw.channels_max = hinfo->channels_max;
1451 runtime->hw.formats = hinfo->formats;
1452 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 1453
1454 snd_pcm_hw_constraint_step(substream->runtime, 0,
1455 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
bbbe3390
TI		 1456 return 0;
1457}
1458
079d88cc
WF		 1459/*
1460 * HDA/HDMI auto parsing
1461 */
384a48d7 1462static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 1463{
1464 struct hdmi_spec *spec = codec->spec;
bce0d2a8 1465 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1466 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 1467
1468 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1469 snd_printk(KERN_WARNING
1470 "HDMI: pin %d wcaps %#x "
1471 "does not support connection list\n",
1472 pin_nid, get_wcaps(codec, pin_nid));
1473 return -EINVAL;
1474 }
1475
384a48d7
SW		 1476 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1477 per_pin->mux_nids,
1478 HDA_MAX_CONNECTIONS);
079d88cc
WF		 1479
1480 return 0;
1481}
1482
efe47108 1483static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
079d88cc 1484{
464837a7 1485 struct hda_jack_tbl *jack;
744626da 1486 struct hda_codec *codec = per_pin->codec;
4bd038f9
DH		 1487 struct hdmi_spec *spec = codec->spec;
1488 struct hdmi_eld *eld = &spec->temp_eld;
1489 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
744626da 1490 hda_nid_t pin_nid = per_pin->pin_nid;
5d44f927
SW		 1491 /*
1492 * Always execute a GetPinSense verb here, even when called from
1493 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1494 * response's PD bit is not the real PD value, but indicates that
1495 * the real PD value changed. An older version of the HD-audio
1496 * specification worked this way. Hence, we just ignore the data in
1497 * the unsolicited response to avoid custom WARs.
1498 */
079d88cc 1499 int present = snd_hda_pin_sense(codec, pin_nid);
4bd038f9
DH		 1500 bool update_eld = false;
1501 bool eld_changed = false;
efe47108 1502 bool ret;
079d88cc 1503
a4e9a38b 1504 mutex_lock(&per_pin->lock);
4bd038f9
DH		 1505 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1506 if (pin_eld->monitor_present)
1507 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1508 else
1509 eld->eld_valid = false;
079d88cc 1510
fae3d88a 1511 _snd_printd(SND_PR_VERBOSE,
384a48d7 1512 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
10250911 1513 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
5d44f927 1514
4bd038f9 1515 if (eld->eld_valid) {
307229d2 1516 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1613d6b4 1517 &eld->eld_size) < 0)
4bd038f9 1518 eld->eld_valid = false;
1613d6b4
DH		 1519 else {
1520 memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
1521 if (snd_hdmi_parse_eld(&eld->info, eld->eld_buffer,
1522 eld->eld_size) < 0)
4bd038f9 1523 eld->eld_valid = false;
1613d6b4
DH		 1524 }
1525
4bd038f9 1526 if (eld->eld_valid) {
1613d6b4 1527 snd_hdmi_show_eld(&eld->info);
4bd038f9 1528 update_eld = true;
1613d6b4 1529 }
c6e8453e 1530 else if (repoll) {
744626da
WF		 1531 queue_delayed_work(codec->bus->workq,
1532 &per_pin->work,
1533 msecs_to_jiffies(300));
cbbaa603 1534 goto unlock;
744626da
WF		 1535 }
1536 }
4bd038f9 1537
92c69e79 1538 if (pin_eld->eld_valid && !eld->eld_valid) {
4bd038f9 1539 update_eld = true;
92c69e79
DH		 1540 eld_changed = true;
1541 }
4bd038f9 1542 if (update_eld) {
b054087d 1543 bool old_eld_valid = pin_eld->eld_valid;
4bd038f9 1544 pin_eld->eld_valid = eld->eld_valid;
92c69e79
DH		 1545 eld_changed = pin_eld->eld_size != eld->eld_size ||
1546 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
4bd038f9
DH		 1547 eld->eld_size) != 0;
1548 if (eld_changed)
1549 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1550 eld->eld_size);
1551 pin_eld->eld_size = eld->eld_size;
1552 pin_eld->info = eld->info;
b054087d 1553
7342017f
AH		 1554 /*
1555 * Re-setup pin and infoframe. This is needed e.g. when
1556 * - sink is first plugged-in (infoframe is not set up if !monitor_present)
1557 * - transcoder can change during stream playback on Haswell
b054087d 1558 */
7342017f 1559 if (eld->eld_valid && !old_eld_valid && per_pin->setup)
b054087d
TI		 1560 hdmi_setup_audio_infoframe(codec, per_pin,
1561 per_pin->non_pcm);
4bd038f9 1562 }
92c69e79
DH		 1563
1564 if (eld_changed)
1565 snd_ctl_notify(codec->bus->card,
1566 SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO,
1567 &per_pin->eld_ctl->id);
cbbaa603 1568 unlock:
aff747eb 1569 ret = !repoll || !pin_eld->monitor_present || pin_eld->eld_valid;
464837a7
DH		 1570
1571 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1572 if (jack)
1573 jack->block_report = !ret;
1574
a4e9a38b 1575 mutex_unlock(&per_pin->lock);
efe47108 1576 return ret;
079d88cc
WF		 1577}
1578
744626da
WF		 1579static void hdmi_repoll_eld(struct work_struct *work)
1580{
1581 struct hdmi_spec_per_pin *per_pin =
1582 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1583
c6e8453e
WF		 1584 if (per_pin->repoll_count++ > 6)
1585 per_pin->repoll_count = 0;
1586
efe47108
TI		 1587 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1588 snd_hda_jack_report_sync(per_pin->codec);
744626da
WF		 1589}
1590
c88d4e84
TI		 1591static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1592 hda_nid_t nid);
1593
079d88cc
WF		 1594static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1595{
1596 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1597 unsigned int caps, config;
1598 int pin_idx;
1599 struct hdmi_spec_per_pin *per_pin;
07acecc1 1600 int err;
079d88cc 1601
efc2f8de 1602 caps = snd_hda_query_pin_caps(codec, pin_nid);
384a48d7
SW		 1603 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1604 return 0;
1605
efc2f8de 1606 config = snd_hda_codec_get_pincfg(codec, pin_nid);
384a48d7
SW		 1607 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1608 return 0;
1609
fb87fa3a 1610 if (is_haswell(codec))
c88d4e84
TI		 1611 intel_haswell_fixup_connect_list(codec, pin_nid);
1612
384a48d7 1613 pin_idx = spec->num_pins;
bce0d2a8
TI		 1614 per_pin = snd_array_new(&spec->pins);
1615 if (!per_pin)
1616 return -ENOMEM;
384a48d7
SW		 1617
1618 per_pin->pin_nid = pin_nid;
1a6003b5 1619 per_pin->non_pcm = false;
079d88cc 1620
384a48d7
SW		 1621 err = hdmi_read_pin_conn(codec, pin_idx);
1622 if (err < 0)
1623 return err;
079d88cc 1624
079d88cc
WF		 1625 spec->num_pins++;
1626
384a48d7 1627 return 0;
079d88cc
WF		 1628}
1629
384a48d7 1630static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 1631{
1632 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1633 struct hdmi_spec_per_cvt *per_cvt;
1634 unsigned int chans;
1635 int err;
079d88cc 1636
384a48d7
SW		 1637 chans = get_wcaps(codec, cvt_nid);
1638 chans = get_wcaps_channels(chans);
1639
bce0d2a8
TI		 1640 per_cvt = snd_array_new(&spec->cvts);
1641 if (!per_cvt)
1642 return -ENOMEM;
384a48d7
SW		 1643
1644 per_cvt->cvt_nid = cvt_nid;
1645 per_cvt->channels_min = 2;
d45e6889 1646 if (chans <= 16) {
384a48d7 1647 per_cvt->channels_max = chans;
d45e6889
TI		 1648 if (chans > spec->channels_max)
1649 spec->channels_max = chans;
1650 }
384a48d7
SW		 1651
1652 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1653 &per_cvt->rates,
1654 &per_cvt->formats,
1655 &per_cvt->maxbps);
1656 if (err < 0)
1657 return err;
1658
bce0d2a8
TI		 1659 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1660 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1661 spec->num_cvts++;
079d88cc
WF		 1662
1663 return 0;
1664}
1665
1666static int hdmi_parse_codec(struct hda_codec *codec)
1667{
1668 hda_nid_t nid;
1669 int i, nodes;
1670
1671 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
1672 if (!nid || nodes < 0) {
1673 snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n");
1674 return -EINVAL;
1675 }
1676
1677 for (i = 0; i < nodes; i++, nid++) {
1678 unsigned int caps;
1679 unsigned int type;
1680
efc2f8de 1681 caps = get_wcaps(codec, nid);
079d88cc
WF		 1682 type = get_wcaps_type(caps);
1683
1684 if (!(caps & AC_WCAP_DIGITAL))
1685 continue;
1686
1687 switch (type) {
1688 case AC_WID_AUD_OUT:
384a48d7 1689 hdmi_add_cvt(codec, nid);
079d88cc
WF		 1690 break;
1691 case AC_WID_PIN:
3eaead57 1692 hdmi_add_pin(codec, nid);
079d88cc
WF		 1693 break;
1694 }
1695 }
1696
079d88cc
WF		 1697 return 0;
1698}
1699
84eb01be
TI		 1700/*
1701 */
1a6003b5
TI		 1702static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1703{
1704 struct hda_spdif_out *spdif;
1705 bool non_pcm;
1706
1707 mutex_lock(&codec->spdif_mutex);
1708 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1709 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1710 mutex_unlock(&codec->spdif_mutex);
1711 return non_pcm;
1712}
1713
1714
84eb01be
TI		 1715/*
1716 * HDMI callbacks
1717 */
1718
1719static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1720 struct hda_codec *codec,
1721 unsigned int stream_tag,
1722 unsigned int format,
1723 struct snd_pcm_substream *substream)
1724{
384a48d7
SW		 1725 hda_nid_t cvt_nid = hinfo->nid;
1726 struct hdmi_spec *spec = codec->spec;
1727 int pin_idx = hinfo_to_pin_index(spec, hinfo);
b054087d
TI		 1728 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1729 hda_nid_t pin_nid = per_pin->pin_nid;
1a6003b5
TI		 1730 bool non_pcm;
1731
1732 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
a4e9a38b 1733 mutex_lock(&per_pin->lock);
b054087d
TI		 1734 per_pin->channels = substream->runtime->channels;
1735 per_pin->setup = true;
384a48d7 1736
b054087d 1737 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
a4e9a38b 1738 mutex_unlock(&per_pin->lock);
84eb01be 1739
307229d2 1740 return spec->ops.setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
84eb01be
TI		 1741}
1742
8dfaa573
TI		 1743static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1744 struct hda_codec *codec,
1745 struct snd_pcm_substream *substream)
1746{
1747 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1748 return 0;
1749}
1750
f2ad24fa
TI		 1751static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1752 struct hda_codec *codec,
1753 struct snd_pcm_substream *substream)
384a48d7
SW		 1754{
1755 struct hdmi_spec *spec = codec->spec;
1756 int cvt_idx, pin_idx;
1757 struct hdmi_spec_per_cvt *per_cvt;
1758 struct hdmi_spec_per_pin *per_pin;
384a48d7 1759
384a48d7
SW		 1760 if (hinfo->nid) {
1761 cvt_idx = cvt_nid_to_cvt_index(spec, hinfo->nid);
1762 if (snd_BUG_ON(cvt_idx < 0))
1763 return -EINVAL;
bce0d2a8 1764 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1765
1766 snd_BUG_ON(!per_cvt->assigned);
1767 per_cvt->assigned = 0;
1768 hinfo->nid = 0;
1769
1770 pin_idx = hinfo_to_pin_index(spec, hinfo);
1771 if (snd_BUG_ON(pin_idx < 0))
1772 return -EINVAL;
bce0d2a8 1773 per_pin = get_pin(spec, pin_idx);
384a48d7 1774
384a48d7 1775 snd_hda_spdif_ctls_unassign(codec, pin_idx);
cbbaa603 1776
a4e9a38b 1777 mutex_lock(&per_pin->lock);
d45e6889
TI		 1778 per_pin->chmap_set = false;
1779 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
b054087d
TI		 1780
1781 per_pin->setup = false;
1782 per_pin->channels = 0;
a4e9a38b 1783 mutex_unlock(&per_pin->lock);
384a48d7 1784 }
d45e6889 1785
384a48d7
SW		 1786 return 0;
1787}
1788
1789static const struct hda_pcm_ops generic_ops = {
1790 .open = hdmi_pcm_open,
f2ad24fa 1791 .close = hdmi_pcm_close,
384a48d7 1792 .prepare = generic_hdmi_playback_pcm_prepare,
8dfaa573 1793 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 1794};
1795
d45e6889
TI		 1796/*
1797 * ALSA API channel-map control callbacks
1798 */
1799static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1800 struct snd_ctl_elem_info *uinfo)
1801{
1802 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1803 struct hda_codec *codec = info->private_data;
1804 struct hdmi_spec *spec = codec->spec;
1805 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1806 uinfo->count = spec->channels_max;
1807 uinfo->value.integer.min = 0;
1808 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1809 return 0;
1810}
1811
307229d2
AH		 1812static int hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
1813 int channels)
1814{
1815 /* If the speaker allocation matches the channel count, it is OK.*/
1816 if (cap->channels != channels)
1817 return -1;
1818
1819 /* all channels are remappable freely */
1820 return SNDRV_CTL_TLVT_CHMAP_VAR;
1821}
1822
1823static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
1824 unsigned int *chmap, int channels)
1825{
1826 int count = 0;
1827 int c;
1828
1829 for (c = 7; c >= 0; c--) {
1830 int spk = cap->speakers[c];
1831 if (!spk)
1832 continue;
1833
1834 chmap[count++] = spk_to_chmap(spk);
1835 }
1836
1837 WARN_ON(count != channels);
1838}
1839
d45e6889
TI		 1840static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
1841 unsigned int size, unsigned int __user *tlv)
1842{
1843 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1844 struct hda_codec *codec = info->private_data;
1845 struct hdmi_spec *spec = codec->spec;
d45e6889
TI		 1846 unsigned int __user *dst;
1847 int chs, count = 0;
1848
1849 if (size < 8)
1850 return -ENOMEM;
1851 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
1852 return -EFAULT;
1853 size -= 8;
1854 dst = tlv + 2;
498dab3a 1855 for (chs = 2; chs <= spec->channels_max; chs++) {
307229d2 1856 int i;
d45e6889
TI		 1857 struct cea_channel_speaker_allocation *cap;
1858 cap = channel_allocations;
1859 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
1860 int chs_bytes = chs * 4;
307229d2
AH		 1861 int type = spec->ops.chmap_cea_alloc_validate_get_type(cap, chs);
1862 unsigned int tlv_chmap[8];
1863
1864 if (type < 0)
d45e6889 1865 continue;
d45e6889
TI		 1866 if (size < 8)
1867 return -ENOMEM;
307229d2 1868 if (put_user(type, dst) ||
d45e6889
TI		 1869 put_user(chs_bytes, dst + 1))
1870 return -EFAULT;
1871 dst += 2;
1872 size -= 8;
1873 count += 8;
1874 if (size < chs_bytes)
1875 return -ENOMEM;
1876 size -= chs_bytes;
1877 count += chs_bytes;
307229d2
AH		 1878 spec->ops.cea_alloc_to_tlv_chmap(cap, tlv_chmap, chs);
1879 if (copy_to_user(dst, tlv_chmap, chs_bytes))
1880 return -EFAULT;
1881 dst += chs;
d45e6889
TI		 1882 }
1883 }
1884 if (put_user(count, tlv + 1))
1885 return -EFAULT;
1886 return 0;
1887}
1888
1889static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
1890 struct snd_ctl_elem_value *ucontrol)
1891{
1892 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1893 struct hda_codec *codec = info->private_data;
1894 struct hdmi_spec *spec = codec->spec;
1895 int pin_idx = kcontrol->private_value;
bce0d2a8 1896 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 1897 int i;
1898
1899 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
1900 ucontrol->value.integer.value[i] = per_pin->chmap[i];
1901 return 0;
1902}
1903
1904static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
1905 struct snd_ctl_elem_value *ucontrol)
1906{
1907 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1908 struct hda_codec *codec = info->private_data;
1909 struct hdmi_spec *spec = codec->spec;
1910 int pin_idx = kcontrol->private_value;
bce0d2a8 1911 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 1912 unsigned int ctl_idx;
1913 struct snd_pcm_substream *substream;
1914 unsigned char chmap[8];
307229d2 1915 int i, err, ca, prepared = 0;
d45e6889
TI		 1916
1917 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
1918 substream = snd_pcm_chmap_substream(info, ctl_idx);
1919 if (!substream || !substream->runtime)
6f54c361 1920 return 0; /* just for avoiding error from alsactl restore */
d45e6889
TI		 1921 switch (substream->runtime->status->state) {
1922 case SNDRV_PCM_STATE_OPEN:
1923 case SNDRV_PCM_STATE_SETUP:
1924 break;
1925 case SNDRV_PCM_STATE_PREPARED:
1926 prepared = 1;
1927 break;
1928 default:
1929 return -EBUSY;
1930 }
1931 memset(chmap, 0, sizeof(chmap));
1932 for (i = 0; i < ARRAY_SIZE(chmap); i++)
1933 chmap[i] = ucontrol->value.integer.value[i];
1934 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
1935 return 0;
1936 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
1937 if (ca < 0)
1938 return -EINVAL;
307229d2
AH		 1939 if (spec->ops.chmap_validate) {
1940 err = spec->ops.chmap_validate(ca, ARRAY_SIZE(chmap), chmap);
1941 if (err)
1942 return err;
1943 }
a4e9a38b 1944 mutex_lock(&per_pin->lock);
d45e6889
TI		 1945 per_pin->chmap_set = true;
1946 memcpy(per_pin->chmap, chmap, sizeof(chmap));
1947 if (prepared)
b054087d 1948 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
a4e9a38b 1949 mutex_unlock(&per_pin->lock);
d45e6889
TI		 1950
1951 return 0;
1952}
1953
84eb01be
TI		 1954static int generic_hdmi_build_pcms(struct hda_codec *codec)
1955{
1956 struct hdmi_spec *spec = codec->spec;
384a48d7 1957 int pin_idx;
84eb01be 1958
384a48d7
SW		 1959 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1960 struct hda_pcm *info;
84eb01be 1961 struct hda_pcm_stream *pstr;
bce0d2a8
TI		 1962 struct hdmi_spec_per_pin *per_pin;
1963
1964 per_pin = get_pin(spec, pin_idx);
1965 sprintf(per_pin->pcm_name, "HDMI %d", pin_idx);
1966 info = snd_array_new(&spec->pcm_rec);
1967 if (!info)
1968 return -ENOMEM;
1969 info->name = per_pin->pcm_name;
84eb01be 1970 info->pcm_type = HDA_PCM_TYPE_HDMI;
d45e6889 1971 info->own_chmap = true;
384a48d7 1972
84eb01be 1973 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 1974 pstr->substreams = 1;
1975 pstr->ops = generic_ops;
1976 /* other pstr fields are set in open */
84eb01be
TI		 1977 }
1978
384a48d7 1979 codec->num_pcms = spec->num_pins;
bce0d2a8 1980 codec->pcm_info = spec->pcm_rec.list;
384a48d7 1981
84eb01be
TI		 1982 return 0;
1983}
1984
0b6c49b5
DH		 1985static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
1986{
31ef2257 1987 char hdmi_str[32] = "HDMI/DP";
0b6c49b5 1988 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 1989 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1990 int pcmdev = get_pcm_rec(spec, pin_idx)->device;
0b6c49b5 1991
31ef2257
TI		 1992 if (pcmdev > 0)
1993 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
30efd8de
DH		 1994 if (!is_jack_detectable(codec, per_pin->pin_nid))
1995 strncat(hdmi_str, " Phantom",
1996 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
0b6c49b5 1997
31ef2257 1998 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 0);
0b6c49b5
DH		 1999}
2000
84eb01be
TI		 2001static int generic_hdmi_build_controls(struct hda_codec *codec)
2002{
2003 struct hdmi_spec *spec = codec->spec;
2004 int err;
384a48d7 2005 int pin_idx;
84eb01be 2006
384a48d7 2007 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2008 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
0b6c49b5
DH		 2009
2010 err = generic_hdmi_build_jack(codec, pin_idx);
2011 if (err < 0)
2012 return err;
2013
dcda5806
TI		 2014 err = snd_hda_create_dig_out_ctls(codec,
2015 per_pin->pin_nid,
2016 per_pin->mux_nids[0],
2017 HDA_PCM_TYPE_HDMI);
84eb01be
TI		 2018 if (err < 0)
2019 return err;
384a48d7 2020 snd_hda_spdif_ctls_unassign(codec, pin_idx);
14bc52b8
PLB		 2021
2022 /* add control for ELD Bytes */
bce0d2a8
TI		 2023 err = hdmi_create_eld_ctl(codec, pin_idx,
2024 get_pcm_rec(spec, pin_idx)->device);
14bc52b8
PLB		 2025
2026 if (err < 0)
2027 return err;
31ef2257 2028
82b1d73f 2029 hdmi_present_sense(per_pin, 0);
84eb01be
TI		 2030 }
2031
d45e6889
TI		 2032 /* add channel maps */
2033 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2034 struct snd_pcm_chmap *chmap;
2035 struct snd_kcontrol *kctl;
2036 int i;
2ca320e2
TI		 2037
2038 if (!codec->pcm_info[pin_idx].pcm)
2039 break;
d45e6889
TI		 2040 err = snd_pcm_add_chmap_ctls(codec->pcm_info[pin_idx].pcm,
2041 SNDRV_PCM_STREAM_PLAYBACK,
2042 NULL, 0, pin_idx, &chmap);
2043 if (err < 0)
2044 return err;
2045 /* override handlers */
2046 chmap->private_data = codec;
2047 kctl = chmap->kctl;
2048 for (i = 0; i < kctl->count; i++)
2049 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
2050 kctl->info = hdmi_chmap_ctl_info;
2051 kctl->get = hdmi_chmap_ctl_get;
2052 kctl->put = hdmi_chmap_ctl_put;
2053 kctl->tlv.c = hdmi_chmap_ctl_tlv;
2054 }
2055
84eb01be
TI		 2056 return 0;
2057}
2058
8b8d654b 2059static int generic_hdmi_init_per_pins(struct hda_codec *codec)
84eb01be
TI		 2060{
2061 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2062 int pin_idx;
2063
2064 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2065 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
84eb01be 2066
744626da 2067 per_pin->codec = codec;
a4e9a38b 2068 mutex_init(&per_pin->lock);
744626da 2069 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
a4e9a38b 2070 eld_proc_new(per_pin, pin_idx);
84eb01be 2071 }
8b8d654b
TI		 2072 return 0;
2073}
2074
2075static int generic_hdmi_init(struct hda_codec *codec)
2076{
2077 struct hdmi_spec *spec = codec->spec;
2078 int pin_idx;
2079
2080 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2081 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
8b8d654b
TI		 2082 hda_nid_t pin_nid = per_pin->pin_nid;
2083
2084 hdmi_init_pin(codec, pin_nid);
20ce9029
DH		 2085 snd_hda_jack_detect_enable_callback(codec, pin_nid, pin_nid,
2086 codec->jackpoll_interval > 0 ? jack_callback : NULL);
8b8d654b 2087 }
84eb01be
TI		 2088 return 0;
2089}
2090
bce0d2a8
TI		 2091static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2092{
2093 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2094 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2095 snd_array_init(&spec->pcm_rec, sizeof(struct hda_pcm), nums);
2096}
2097
2098static void hdmi_array_free(struct hdmi_spec *spec)
2099{
2100 snd_array_free(&spec->pins);
2101 snd_array_free(&spec->cvts);
2102 snd_array_free(&spec->pcm_rec);
2103}
2104
84eb01be
TI		 2105static void generic_hdmi_free(struct hda_codec *codec)
2106{
2107 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2108 int pin_idx;
2109
2110 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2111 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
84eb01be 2112
744626da 2113 cancel_delayed_work(&per_pin->work);
a4e9a38b 2114 eld_proc_free(per_pin);
384a48d7 2115 }
84eb01be 2116
744626da 2117 flush_workqueue(codec->bus->workq);
bce0d2a8 2118 hdmi_array_free(spec);
84eb01be
TI		 2119 kfree(spec);
2120}
2121
28cb72e5
WX		 2122#ifdef CONFIG_PM
2123static int generic_hdmi_resume(struct hda_codec *codec)
2124{
2125 struct hdmi_spec *spec = codec->spec;
2126 int pin_idx;
2127
2128 generic_hdmi_init(codec);
2129 snd_hda_codec_resume_amp(codec);
2130 snd_hda_codec_resume_cache(codec);
2131
2132 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2133 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2134 hdmi_present_sense(per_pin, 1);
2135 }
2136 return 0;
2137}
2138#endif
2139
fb79e1e0 2140static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 2141 .init = generic_hdmi_init,
2142 .free = generic_hdmi_free,
2143 .build_pcms = generic_hdmi_build_pcms,
2144 .build_controls = generic_hdmi_build_controls,
2145 .unsol_event = hdmi_unsol_event,
28cb72e5
WX		 2146#ifdef CONFIG_PM
2147 .resume = generic_hdmi_resume,
2148#endif
84eb01be
TI		 2149};
2150
307229d2
AH		 2151static const struct hdmi_ops generic_standard_hdmi_ops = {
2152 .pin_get_eld = snd_hdmi_get_eld,
2153 .pin_get_slot_channel = hdmi_pin_get_slot_channel,
2154 .pin_set_slot_channel = hdmi_pin_set_slot_channel,
2155 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2156 .pin_hbr_setup = hdmi_pin_hbr_setup,
2157 .setup_stream = hdmi_setup_stream,
2158 .chmap_cea_alloc_validate_get_type = hdmi_chmap_cea_alloc_validate_get_type,
2159 .cea_alloc_to_tlv_chmap = hdmi_cea_alloc_to_tlv_chmap,
2160};
2161
6ffe168f 2162
c88d4e84
TI		 2163static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2164 hda_nid_t nid)
2165{
2166 struct hdmi_spec *spec = codec->spec;
2167 hda_nid_t conns[4];
2168 int nconns;
6ffe168f 2169
c88d4e84
TI		 2170 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2171 if (nconns == spec->num_cvts &&
2172 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
6ffe168f
ML		 2173 return;
2174
c88d4e84
TI		 2175 /* override pins connection list */
2176 snd_printdd("hdmi: haswell: override pin connection 0x%x\n", nid);
2177 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
6ffe168f
ML		 2178}
2179
1611a9c9
ML		 2180#define INTEL_VENDOR_NID 0x08
2181#define INTEL_GET_VENDOR_VERB 0xf81
2182#define INTEL_SET_VENDOR_VERB 0x781
2183#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2184#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2185
2186static void intel_haswell_enable_all_pins(struct hda_codec *codec,
17df3f55 2187 bool update_tree)
1611a9c9
ML		 2188{
2189 unsigned int vendor_param;
2190
1611a9c9
ML		 2191 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2192 INTEL_GET_VENDOR_VERB, 0);
2193 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2194 return;
2195
2196 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2197 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2198 INTEL_SET_VENDOR_VERB, vendor_param);
2199 if (vendor_param == -1)
2200 return;
2201
17df3f55
TI		 2202 if (update_tree)
2203 snd_hda_codec_update_widgets(codec);
1611a9c9
ML		 2204}
2205
c88d4e84
TI		 2206static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2207{
2208 unsigned int vendor_param;
2209
2210 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2211 INTEL_GET_VENDOR_VERB, 0);
2212 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2213 return;
2214
2215 /* enable DP1.2 mode */
2216 vendor_param |= INTEL_EN_DP12;
2217 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2218 INTEL_SET_VENDOR_VERB, vendor_param);
2219}
2220
17df3f55
TI		 2221/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2222 * Otherwise you may get severe h/w communication errors.
2223 */
2224static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2225 unsigned int power_state)
2226{
2227 if (power_state == AC_PWRST_D0) {
2228 intel_haswell_enable_all_pins(codec, false);
2229 intel_haswell_fixup_enable_dp12(codec);
2230 }
c88d4e84 2231
17df3f55
TI		 2232 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2233 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2234}
6ffe168f 2235
84eb01be
TI		 2236static int patch_generic_hdmi(struct hda_codec *codec)
2237{
2238 struct hdmi_spec *spec;
84eb01be
TI		 2239
2240 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2241 if (spec == NULL)
2242 return -ENOMEM;
2243
307229d2 2244 spec->ops = generic_standard_hdmi_ops;
84eb01be 2245 codec->spec = spec;
bce0d2a8 2246 hdmi_array_init(spec, 4);
6ffe168f 2247
fb87fa3a 2248 if (is_haswell(codec)) {
17df3f55 2249 intel_haswell_enable_all_pins(codec, true);
c88d4e84 2250 intel_haswell_fixup_enable_dp12(codec);
17df3f55 2251 }
6ffe168f 2252
5b8620bb
ML		 2253 if (is_haswell(codec) || is_valleyview(codec)) {
2254 codec->depop_delay = 0;
2255 }
2256
84eb01be
TI		 2257 if (hdmi_parse_codec(codec) < 0) {
2258 codec->spec = NULL;
2259 kfree(spec);
2260 return -EINVAL;
2261 }
2262 codec->patch_ops = generic_hdmi_patch_ops;
fb87fa3a 2263 if (is_haswell(codec)) {
17df3f55 2264 codec->patch_ops.set_power_state = haswell_set_power_state;
5dc989bd
ML		 2265 codec->dp_mst = true;
2266 }
17df3f55 2267
8b8d654b 2268 generic_hdmi_init_per_pins(codec);
84eb01be 2269
84eb01be
TI		 2270 init_channel_allocations();
2271
2272 return 0;
2273}
2274
3aaf8980
SW		 2275/*
2276 * Shared non-generic implementations
2277 */
2278
2279static int simple_playback_build_pcms(struct hda_codec *codec)
2280{
2281 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2282 struct hda_pcm *info;
8ceb332d
TI		 2283 unsigned int chans;
2284 struct hda_pcm_stream *pstr;
bce0d2a8 2285 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2286
bce0d2a8
TI		 2287 per_cvt = get_cvt(spec, 0);
2288 chans = get_wcaps(codec, per_cvt->cvt_nid);
8ceb332d 2289 chans = get_wcaps_channels(chans);
3aaf8980 2290
bce0d2a8
TI		 2291 info = snd_array_new(&spec->pcm_rec);
2292 if (!info)
2293 return -ENOMEM;
2294 info->name = get_pin(spec, 0)->pcm_name;
2295 sprintf(info->name, "HDMI 0");
8ceb332d
TI		 2296 info->pcm_type = HDA_PCM_TYPE_HDMI;
2297 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2298 *pstr = spec->pcm_playback;
bce0d2a8 2299 pstr->nid = per_cvt->cvt_nid;
8ceb332d
TI		 2300 if (pstr->channels_max <= 2 && chans && chans <= 16)
2301 pstr->channels_max = chans;
3aaf8980 2302
bce0d2a8
TI		 2303 codec->num_pcms = 1;
2304 codec->pcm_info = info;
2305
3aaf8980
SW		 2306 return 0;
2307}
2308
4b6ace9e
TI		 2309/* unsolicited event for jack sensing */
2310static void simple_hdmi_unsol_event(struct hda_codec *codec,
2311 unsigned int res)
2312{
9dd8cf12 2313 snd_hda_jack_set_dirty_all(codec);
4b6ace9e
TI		 2314 snd_hda_jack_report_sync(codec);
2315}
2316
2317/* generic_hdmi_build_jack can be used for simple_hdmi, too,
2318 * as long as spec->pins[] is set correctly
2319 */
2320#define simple_hdmi_build_jack generic_hdmi_build_jack
2321
3aaf8980
SW		 2322static int simple_playback_build_controls(struct hda_codec *codec)
2323{
2324 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2325 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2326 int err;
3aaf8980 2327
bce0d2a8 2328 per_cvt = get_cvt(spec, 0);
c9a6338a
AH		 2329 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2330 per_cvt->cvt_nid,
2331 HDA_PCM_TYPE_HDMI);
8ceb332d
TI		 2332 if (err < 0)
2333 return err;
2334 return simple_hdmi_build_jack(codec, 0);
3aaf8980
SW		 2335}
2336
4f0110ce
TI		 2337static int simple_playback_init(struct hda_codec *codec)
2338{
2339 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 2340 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2341 hda_nid_t pin = per_pin->pin_nid;
8ceb332d
TI		 2342
2343 snd_hda_codec_write(codec, pin, 0,
2344 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2345 /* some codecs require to unmute the pin */
2346 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2347 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2348 AMP_OUT_UNMUTE);
2349 snd_hda_jack_detect_enable(codec, pin, pin);
4f0110ce
TI		 2350 return 0;
2351}
2352
3aaf8980
SW		 2353static void simple_playback_free(struct hda_codec *codec)
2354{
2355 struct hdmi_spec *spec = codec->spec;
2356
bce0d2a8 2357 hdmi_array_free(spec);
3aaf8980
SW		 2358 kfree(spec);
2359}
2360
84eb01be
TI		 2361/*
2362 * Nvidia specific implementations
2363 */
2364
2365#define Nv_VERB_SET_Channel_Allocation 0xF79
2366#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2367#define Nv_VERB_SET_Audio_Protection_On 0xF98
2368#define Nv_VERB_SET_Audio_Protection_Off 0xF99
2369
2370#define nvhdmi_master_con_nid_7x 0x04
2371#define nvhdmi_master_pin_nid_7x 0x05
2372
fb79e1e0 2373static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 2374 /*front, rear, clfe, rear_surr */
2375 0x6, 0x8, 0xa, 0xc,
2376};
2377
ceaa86ba
TI		 2378static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2379 /* set audio protect on */
2380 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2381 /* enable digital output on pin widget */
2382 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2383 {} /* terminator */
2384};
2385
2386static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
84eb01be
TI		 2387 /* set audio protect on */
2388 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2389 /* enable digital output on pin widget */
2390 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2391 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2392 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2393 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2394 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2395 {} /* terminator */
2396};
2397
2398#ifdef LIMITED_RATE_FMT_SUPPORT
2399/* support only the safe format and rate */
2400#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2401#define SUPPORTED_MAXBPS 16
2402#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2403#else
2404/* support all rates and formats */
2405#define SUPPORTED_RATES \
2406 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2407 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2408 SNDRV_PCM_RATE_192000)
2409#define SUPPORTED_MAXBPS 24
2410#define SUPPORTED_FORMATS \
2411 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2412#endif
2413
ceaa86ba
TI		 2414static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2415{
2416 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2417 return 0;
2418}
2419
2420static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
84eb01be 2421{
ceaa86ba 2422 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
84eb01be
TI		 2423 return 0;
2424}
2425
393004b2
ND		 2426static unsigned int channels_2_6_8[] = {
2427 2, 6, 8
2428};
2429
2430static unsigned int channels_2_8[] = {
2431 2, 8
2432};
2433
2434static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2435 .count = ARRAY_SIZE(channels_2_6_8),
2436 .list = channels_2_6_8,
2437 .mask = 0,
2438};
2439
2440static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2441 .count = ARRAY_SIZE(channels_2_8),
2442 .list = channels_2_8,
2443 .mask = 0,
2444};
2445
84eb01be
TI		 2446static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2447 struct hda_codec *codec,
2448 struct snd_pcm_substream *substream)
2449{
2450 struct hdmi_spec *spec = codec->spec;
393004b2
ND		 2451 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2452
2453 switch (codec->preset->id) {
2454 case 0x10de0002:
2455 case 0x10de0003:
2456 case 0x10de0005:
2457 case 0x10de0006:
2458 hw_constraints_channels = &hw_constraints_2_8_channels;
2459 break;
2460 case 0x10de0007:
2461 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2462 break;
2463 default:
2464 break;
2465 }
2466
2467 if (hw_constraints_channels != NULL) {
2468 snd_pcm_hw_constraint_list(substream->runtime, 0,
2469 SNDRV_PCM_HW_PARAM_CHANNELS,
2470 hw_constraints_channels);
ad09fc9d
TI		 2471 } else {
2472 snd_pcm_hw_constraint_step(substream->runtime, 0,
2473 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 2474 }
2475
84eb01be
TI		 2476 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2477}
2478
2479static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2480 struct hda_codec *codec,
2481 struct snd_pcm_substream *substream)
2482{
2483 struct hdmi_spec *spec = codec->spec;
2484 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2485}
2486
2487static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2488 struct hda_codec *codec,
2489 unsigned int stream_tag,
2490 unsigned int format,
2491 struct snd_pcm_substream *substream)
2492{
2493 struct hdmi_spec *spec = codec->spec;
2494 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2495 stream_tag, format, substream);
2496}
2497
d0b1252d
TI		 2498static const struct hda_pcm_stream simple_pcm_playback = {
2499 .substreams = 1,
2500 .channels_min = 2,
2501 .channels_max = 2,
2502 .ops = {
2503 .open = simple_playback_pcm_open,
2504 .close = simple_playback_pcm_close,
2505 .prepare = simple_playback_pcm_prepare
2506 },
2507};
2508
2509static const struct hda_codec_ops simple_hdmi_patch_ops = {
2510 .build_controls = simple_playback_build_controls,
2511 .build_pcms = simple_playback_build_pcms,
2512 .init = simple_playback_init,
2513 .free = simple_playback_free,
250e41ac 2514 .unsol_event = simple_hdmi_unsol_event,
d0b1252d
TI		 2515};
2516
2517static int patch_simple_hdmi(struct hda_codec *codec,
2518 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2519{
2520 struct hdmi_spec *spec;
bce0d2a8
TI		 2521 struct hdmi_spec_per_cvt *per_cvt;
2522 struct hdmi_spec_per_pin *per_pin;
d0b1252d
TI		 2523
2524 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2525 if (!spec)
2526 return -ENOMEM;
2527
2528 codec->spec = spec;
bce0d2a8 2529 hdmi_array_init(spec, 1);
d0b1252d
TI		 2530
2531 spec->multiout.num_dacs = 0; /* no analog */
2532 spec->multiout.max_channels = 2;
2533 spec->multiout.dig_out_nid = cvt_nid;
2534 spec->num_cvts = 1;
2535 spec->num_pins = 1;
bce0d2a8
TI		 2536 per_pin = snd_array_new(&spec->pins);
2537 per_cvt = snd_array_new(&spec->cvts);
2538 if (!per_pin || !per_cvt) {
2539 simple_playback_free(codec);
2540 return -ENOMEM;
2541 }
2542 per_cvt->cvt_nid = cvt_nid;
2543 per_pin->pin_nid = pin_nid;
d0b1252d
TI		 2544 spec->pcm_playback = simple_pcm_playback;
2545
2546 codec->patch_ops = simple_hdmi_patch_ops;
2547
2548 return 0;
2549}
2550
1f348522
AP		 2551static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2552 int channels)
2553{
2554 unsigned int chanmask;
2555 int chan = channels ? (channels - 1) : 1;
2556
2557 switch (channels) {
2558 default:
2559 case 0:
2560 case 2:
2561 chanmask = 0x00;
2562 break;
2563 case 4:
2564 chanmask = 0x08;
2565 break;
2566 case 6:
2567 chanmask = 0x0b;
2568 break;
2569 case 8:
2570 chanmask = 0x13;
2571 break;
2572 }
2573
2574 /* Set the audio infoframe channel allocation and checksum fields. The
2575 * channel count is computed implicitly by the hardware. */
2576 snd_hda_codec_write(codec, 0x1, 0,
2577 Nv_VERB_SET_Channel_Allocation, chanmask);
2578
2579 snd_hda_codec_write(codec, 0x1, 0,
2580 Nv_VERB_SET_Info_Frame_Checksum,
2581 (0x71 - chan - chanmask));
2582}
2583
84eb01be
TI		 2584static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2585 struct hda_codec *codec,
2586 struct snd_pcm_substream *substream)
2587{
2588 struct hdmi_spec *spec = codec->spec;
2589 int i;
2590
2591 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2592 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2593 for (i = 0; i < 4; i++) {
2594 /* set the stream id */
2595 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2596 AC_VERB_SET_CHANNEL_STREAMID, 0);
2597 /* set the stream format */
2598 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2599 AC_VERB_SET_STREAM_FORMAT, 0);
2600 }
2601
1f348522
AP		 2602 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2603 * streams are disabled. */
2604 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2605
84eb01be
TI		 2606 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2607}
2608
2609static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2610 struct hda_codec *codec,
2611 unsigned int stream_tag,
2612 unsigned int format,
2613 struct snd_pcm_substream *substream)
2614{
2615 int chs;
112daa7a 2616 unsigned int dataDCC2, channel_id;
84eb01be 2617 int i;
7c935976 2618 struct hdmi_spec *spec = codec->spec;
e3245cdd 2619 struct hda_spdif_out *spdif;
bce0d2a8 2620 struct hdmi_spec_per_cvt *per_cvt;
84eb01be
TI		 2621
2622 mutex_lock(&codec->spdif_mutex);
bce0d2a8
TI		 2623 per_cvt = get_cvt(spec, 0);
2624 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
84eb01be
TI		 2625
2626 chs = substream->runtime->channels;
84eb01be 2627
84eb01be
TI		 2628 dataDCC2 = 0x2;
2629
84eb01be 2630 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 2631 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2632 snd_hda_codec_write(codec,
2633 nvhdmi_master_con_nid_7x,
2634 0,
2635 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2636 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2637
2638 /* set the stream id */
2639 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2640 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2641
2642 /* set the stream format */
2643 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2644 AC_VERB_SET_STREAM_FORMAT, format);
2645
2646 /* turn on again (if needed) */
2647 /* enable and set the channel status audio/data flag */
7c935976 2648 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2649 snd_hda_codec_write(codec,
2650 nvhdmi_master_con_nid_7x,
2651 0,
2652 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2653 spdif->ctls & 0xff);
84eb01be
TI		 2654 snd_hda_codec_write(codec,
2655 nvhdmi_master_con_nid_7x,
2656 0,
2657 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2658 }
2659
2660 for (i = 0; i < 4; i++) {
2661 if (chs == 2)
2662 channel_id = 0;
2663 else
2664 channel_id = i * 2;
2665
2666 /* turn off SPDIF once;
2667 *otherwise the IEC958 bits won't be updated
2668 */
2669 if (codec->spdif_status_reset &&
7c935976 2670 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2671 snd_hda_codec_write(codec,
2672 nvhdmi_con_nids_7x[i],
2673 0,
2674 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2675 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2676 /* set the stream id */
2677 snd_hda_codec_write(codec,
2678 nvhdmi_con_nids_7x[i],
2679 0,
2680 AC_VERB_SET_CHANNEL_STREAMID,
2681 (stream_tag << 4) | channel_id);
2682 /* set the stream format */
2683 snd_hda_codec_write(codec,
2684 nvhdmi_con_nids_7x[i],
2685 0,
2686 AC_VERB_SET_STREAM_FORMAT,
2687 format);
2688 /* turn on again (if needed) */
2689 /* enable and set the channel status audio/data flag */
2690 if (codec->spdif_status_reset &&
7c935976 2691 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2692 snd_hda_codec_write(codec,
2693 nvhdmi_con_nids_7x[i],
2694 0,
2695 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2696 spdif->ctls & 0xff);
84eb01be
TI		 2697 snd_hda_codec_write(codec,
2698 nvhdmi_con_nids_7x[i],
2699 0,
2700 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2701 }
2702 }
2703
1f348522 2704 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 2705
2706 mutex_unlock(&codec->spdif_mutex);
2707 return 0;
2708}
2709
fb79e1e0 2710static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 2711 .substreams = 1,
2712 .channels_min = 2,
2713 .channels_max = 8,
2714 .nid = nvhdmi_master_con_nid_7x,
2715 .rates = SUPPORTED_RATES,
2716 .maxbps = SUPPORTED_MAXBPS,
2717 .formats = SUPPORTED_FORMATS,
2718 .ops = {
2719 .open = simple_playback_pcm_open,
2720 .close = nvhdmi_8ch_7x_pcm_close,
2721 .prepare = nvhdmi_8ch_7x_pcm_prepare
2722 },
2723};
2724
84eb01be
TI		 2725static int patch_nvhdmi_2ch(struct hda_codec *codec)
2726{
2727 struct hdmi_spec *spec;
d0b1252d
TI		 2728 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2729 nvhdmi_master_pin_nid_7x);
2730 if (err < 0)
2731 return err;
84eb01be 2732
ceaa86ba 2733 codec->patch_ops.init = nvhdmi_7x_init_2ch;
d0b1252d
TI		 2734 /* override the PCM rates, etc, as the codec doesn't give full list */
2735 spec = codec->spec;
2736 spec->pcm_playback.rates = SUPPORTED_RATES;
2737 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2738 spec->pcm_playback.formats = SUPPORTED_FORMATS;
84eb01be
TI		 2739 return 0;
2740}
2741
53775b0d
TI		 2742static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2743{
2744 struct hdmi_spec *spec = codec->spec;
2745 int err = simple_playback_build_pcms(codec);
bce0d2a8
TI		 2746 if (!err) {
2747 struct hda_pcm *info = get_pcm_rec(spec, 0);
2748 info->own_chmap = true;
2749 }
53775b0d
TI		 2750 return err;
2751}
2752
2753static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2754{
2755 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2756 struct hda_pcm *info;
53775b0d
TI		 2757 struct snd_pcm_chmap *chmap;
2758 int err;
2759
2760 err = simple_playback_build_controls(codec);
2761 if (err < 0)
2762 return err;
2763
2764 /* add channel maps */
bce0d2a8
TI		 2765 info = get_pcm_rec(spec, 0);
2766 err = snd_pcm_add_chmap_ctls(info->pcm,
53775b0d
TI		 2767 SNDRV_PCM_STREAM_PLAYBACK,
2768 snd_pcm_alt_chmaps, 8, 0, &chmap);
2769 if (err < 0)
2770 return err;
2771 switch (codec->preset->id) {
2772 case 0x10de0002:
2773 case 0x10de0003:
2774 case 0x10de0005:
2775 case 0x10de0006:
2776 chmap->channel_mask = (1U << 2) | (1U << 8);
2777 break;
2778 case 0x10de0007:
2779 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2780 }
2781 return 0;
2782}
2783
84eb01be
TI		 2784static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2785{
2786 struct hdmi_spec *spec;
2787 int err = patch_nvhdmi_2ch(codec);
84eb01be
TI		 2788 if (err < 0)
2789 return err;
2790 spec = codec->spec;
2791 spec->multiout.max_channels = 8;
d0b1252d 2792 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
ceaa86ba 2793 codec->patch_ops.init = nvhdmi_7x_init_8ch;
53775b0d
TI		 2794 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2795 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
1f348522
AP		 2796
2797 /* Initialize the audio infoframe channel mask and checksum to something
2798 * valid */
2799 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2800
84eb01be
TI		 2801 return 0;
2802}
2803
611885bc
AH		 2804/*
2805 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
2806 * - 0x10de0015
2807 * - 0x10de0040
2808 */
2809static int nvhdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
2810 int channels)
2811{
2812 if (cap->ca_index == 0x00 && channels == 2)
2813 return SNDRV_CTL_TLVT_CHMAP_FIXED;
2814
2815 return hdmi_chmap_cea_alloc_validate_get_type(cap, channels);
2816}
2817
2818static int nvhdmi_chmap_validate(int ca, int chs, unsigned char *map)
2819{
2820 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
2821 return -EINVAL;
2822
2823 return 0;
2824}
2825
2826static int patch_nvhdmi(struct hda_codec *codec)
2827{
2828 struct hdmi_spec *spec;
2829 int err;
2830
2831 err = patch_generic_hdmi(codec);
2832 if (err)
2833 return err;
2834
2835 spec = codec->spec;
2836
2837 spec->ops.chmap_cea_alloc_validate_get_type =
2838 nvhdmi_chmap_cea_alloc_validate_get_type;
2839 spec->ops.chmap_validate = nvhdmi_chmap_validate;
2840
2841 return 0;
2842}
2843
84eb01be 2844/*
5a613584 2845 * ATI/AMD-specific implementations
84eb01be
TI		 2846 */
2847
5a613584
AH		 2848#define is_amdhdmi_rev3_or_later(codec) \
2849 ((codec)->vendor_id == 0x1002aa01 && ((codec)->revision_id & 0xff00) >= 0x0300)
2850#define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
2851
2852/* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
2853#define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
2854#define ATI_VERB_SET_DOWNMIX_INFO 0x772
2855#define ATI_VERB_SET_MULTICHANNEL_01 0x777
2856#define ATI_VERB_SET_MULTICHANNEL_23 0x778
2857#define ATI_VERB_SET_MULTICHANNEL_45 0x779
2858#define ATI_VERB_SET_MULTICHANNEL_67 0x77a
461cf6b3 2859#define ATI_VERB_SET_HBR_CONTROL 0x77c
5a613584
AH		 2860#define ATI_VERB_SET_MULTICHANNEL_1 0x785
2861#define ATI_VERB_SET_MULTICHANNEL_3 0x786
2862#define ATI_VERB_SET_MULTICHANNEL_5 0x787
2863#define ATI_VERB_SET_MULTICHANNEL_7 0x788
2864#define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
2865#define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
2866#define ATI_VERB_GET_DOWNMIX_INFO 0xf72
2867#define ATI_VERB_GET_MULTICHANNEL_01 0xf77
2868#define ATI_VERB_GET_MULTICHANNEL_23 0xf78
2869#define ATI_VERB_GET_MULTICHANNEL_45 0xf79
2870#define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
461cf6b3 2871#define ATI_VERB_GET_HBR_CONTROL 0xf7c
5a613584
AH		 2872#define ATI_VERB_GET_MULTICHANNEL_1 0xf85
2873#define ATI_VERB_GET_MULTICHANNEL_3 0xf86
2874#define ATI_VERB_GET_MULTICHANNEL_5 0xf87
2875#define ATI_VERB_GET_MULTICHANNEL_7 0xf88
2876#define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
2877
84d69e79
AH		 2878/* AMD specific HDA cvt verbs */
2879#define ATI_VERB_SET_RAMP_RATE 0x770
2880#define ATI_VERB_GET_RAMP_RATE 0xf70
2881
5a613584
AH		 2882#define ATI_OUT_ENABLE 0x1
2883
2884#define ATI_MULTICHANNEL_MODE_PAIRED 0
2885#define ATI_MULTICHANNEL_MODE_SINGLE 1
2886
461cf6b3
AH		 2887#define ATI_HBR_CAPABLE 0x01
2888#define ATI_HBR_ENABLE 0x10
2889
89250f84
AH		 2890static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
2891 unsigned char *buf, int *eld_size)
2892{
2893 /* call hda_eld.c ATI/AMD-specific function */
2894 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
2895 is_amdhdmi_rev3_or_later(codec));
2896}
2897
5a613584
AH		 2898static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
2899 int active_channels, int conn_type)
2900{
2901 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
2902}
2903
2904static int atihdmi_paired_swap_fc_lfe(int pos)
2905{
2906 /*
2907 * ATI/AMD have automatic FC/LFE swap built-in
2908 * when in pairwise mapping mode.
2909 */
2910
2911 switch (pos) {
2912 /* see channel_allocations[].speakers[] */
2913 case 2: return 3;
2914 case 3: return 2;
2915 default: break;
2916 }
2917
2918 return pos;
2919}
2920
2921static int atihdmi_paired_chmap_validate(int ca, int chs, unsigned char *map)
2922{
2923 struct cea_channel_speaker_allocation *cap;
2924 int i, j;
2925
2926 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
2927
2928 cap = &channel_allocations[get_channel_allocation_order(ca)];
2929 for (i = 0; i < chs; ++i) {
2930 int mask = to_spk_mask(map[i]);
2931 bool ok = false;
2932 bool companion_ok = false;
2933
2934 if (!mask)
2935 continue;
2936
2937 for (j = 0 + i % 2; j < 8; j += 2) {
2938 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
2939 if (cap->speakers[chan_idx] == mask) {
2940 /* channel is in a supported position */
2941 ok = true;
2942
2943 if (i % 2 == 0 && i + 1 < chs) {
2944 /* even channel, check the odd companion */
2945 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
2946 int comp_mask_req = to_spk_mask(map[i+1]);
2947 int comp_mask_act = cap->speakers[comp_chan_idx];
2948
2949 if (comp_mask_req == comp_mask_act)
2950 companion_ok = true;
2951 else
2952 return -EINVAL;
2953 }
2954 break;
2955 }
2956 }
2957
2958 if (!ok)
2959 return -EINVAL;
2960
2961 if (companion_ok)
2962 i++; /* companion channel already checked */
2963 }
2964
2965 return 0;
2966}
2967
2968static int atihdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
2969 int hdmi_slot, int stream_channel)
2970{
2971 int verb;
2972 int ati_channel_setup = 0;
2973
2974 if (hdmi_slot > 7)
2975 return -EINVAL;
2976
2977 if (!has_amd_full_remap_support(codec)) {
2978 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
2979
2980 /* In case this is an odd slot but without stream channel, do not
2981 * disable the slot since the corresponding even slot could have a
2982 * channel. In case neither have a channel, the slot pair will be
2983 * disabled when this function is called for the even slot. */
2984 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
2985 return 0;
2986
2987 hdmi_slot -= hdmi_slot % 2;
2988
2989 if (stream_channel != 0xf)
2990 stream_channel -= stream_channel % 2;
2991 }
2992
2993 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
2994
2995 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
2996
2997 if (stream_channel != 0xf)
2998 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
2999
3000 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3001}
3002
3003static int atihdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3004 int asp_slot)
3005{
3006 bool was_odd = false;
3007 int ati_asp_slot = asp_slot;
3008 int verb;
3009 int ati_channel_setup;
3010
3011 if (asp_slot > 7)
3012 return -EINVAL;
3013
3014 if (!has_amd_full_remap_support(codec)) {
3015 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3016 if (ati_asp_slot % 2 != 0) {
3017 ati_asp_slot -= 1;
3018 was_odd = true;
3019 }
3020 }
3021
3022 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3023
3024 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3025
3026 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3027 return 0xf;
3028
3029 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3030}
84eb01be 3031
5a613584
AH		 3032static int atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
3033 int channels)
3034{
3035 int c;
3036
3037 /*
3038 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3039 * we need to take that into account (a single channel may take 2
3040 * channel slots if we need to carry a silent channel next to it).
3041 * On Rev3+ AMD codecs this function is not used.
3042 */
3043 int chanpairs = 0;
3044
3045 /* We only produce even-numbered channel count TLVs */
3046 if ((channels % 2) != 0)
3047 return -1;
3048
3049 for (c = 0; c < 7; c += 2) {
3050 if (cap->speakers[c] || cap->speakers[c+1])
3051 chanpairs++;
3052 }
3053
3054 if (chanpairs * 2 != channels)
3055 return -1;
3056
3057 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3058}
3059
3060static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
3061 unsigned int *chmap, int channels)
3062{
3063 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3064 int count = 0;
3065 int c;
3066
3067 for (c = 7; c >= 0; c--) {
3068 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3069 int spk = cap->speakers[chan];
3070 if (!spk) {
3071 /* add N/A channel if the companion channel is occupied */
3072 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3073 chmap[count++] = SNDRV_CHMAP_NA;
3074
3075 continue;
3076 }
3077
3078 chmap[count++] = spk_to_chmap(spk);
3079 }
3080
3081 WARN_ON(count != channels);
3082}
3083
461cf6b3
AH		 3084static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3085 bool hbr)
3086{
3087 int hbr_ctl, hbr_ctl_new;
3088
3089 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
13122e6e 3090 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
461cf6b3
AH		 3091 if (hbr)
3092 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3093 else
3094 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3095
3096 snd_printdd("atihdmi_pin_hbr_setup: "
3097 "NID=0x%x, %shbr-ctl=0x%x\n",
3098 pin_nid,
3099 hbr_ctl == hbr_ctl_new ? "" : "new-",
3100 hbr_ctl_new);
3101
3102 if (hbr_ctl != hbr_ctl_new)
3103 snd_hda_codec_write(codec, pin_nid, 0,
3104 ATI_VERB_SET_HBR_CONTROL,
3105 hbr_ctl_new);
3106
3107 } else if (hbr)
3108 return -EINVAL;
3109
3110 return 0;
3111}
3112
84d69e79
AH		 3113static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3114 hda_nid_t pin_nid, u32 stream_tag, int format)
3115{
3116
3117 if (is_amdhdmi_rev3_or_later(codec)) {
3118 int ramp_rate = 180; /* default as per AMD spec */
3119 /* disable ramp-up/down for non-pcm as per AMD spec */
3120 if (format & AC_FMT_TYPE_NON_PCM)
3121 ramp_rate = 0;
3122
3123 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3124 }
3125
3126 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3127}
3128
3129
5a613584 3130static int atihdmi_init(struct hda_codec *codec)
84eb01be
TI		 3131{
3132 struct hdmi_spec *spec = codec->spec;
5a613584 3133 int pin_idx, err;
84eb01be 3134
5a613584
AH		 3135 err = generic_hdmi_init(codec);
3136
3137 if (err)
84eb01be 3138 return err;
5a613584
AH		 3139
3140 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3141 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3142
3143 /* make sure downmix information in infoframe is zero */
3144 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3145
3146 /* enable channel-wise remap mode if supported */
3147 if (has_amd_full_remap_support(codec))
3148 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3149 ATI_VERB_SET_MULTICHANNEL_MODE,
3150 ATI_MULTICHANNEL_MODE_SINGLE);
84eb01be 3151 }
5a613584 3152
84eb01be
TI		 3153 return 0;
3154}
3155
84eb01be
TI		 3156static int patch_atihdmi(struct hda_codec *codec)
3157{
3158 struct hdmi_spec *spec;
5a613584
AH		 3159 struct hdmi_spec_per_cvt *per_cvt;
3160 int err, cvt_idx;
3161
3162 err = patch_generic_hdmi(codec);
3163
3164 if (err)
d0b1252d 3165 return err;
5a613584
AH		 3166
3167 codec->patch_ops.init = atihdmi_init;
3168
d0b1252d 3169 spec = codec->spec;
5a613584 3170
89250f84 3171 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
5a613584
AH		 3172 spec->ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3173 spec->ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3174 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
461cf6b3 3175 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
84d69e79 3176 spec->ops.setup_stream = atihdmi_setup_stream;
5a613584
AH		 3177
3178 if (!has_amd_full_remap_support(codec)) {
3179 /* override to ATI/AMD-specific versions with pairwise mapping */
3180 spec->ops.chmap_cea_alloc_validate_get_type =
3181 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3182 spec->ops.cea_alloc_to_tlv_chmap = atihdmi_paired_cea_alloc_to_tlv_chmap;
3183 spec->ops.chmap_validate = atihdmi_paired_chmap_validate;
3184 }
3185
3186 /* ATI/AMD converters do not advertise all of their capabilities */
3187 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3188 per_cvt = get_cvt(spec, cvt_idx);
3189 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3190 per_cvt->rates |= SUPPORTED_RATES;
3191 per_cvt->formats |= SUPPORTED_FORMATS;
3192 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3193 }
3194
3195 spec->channels_max = max(spec->channels_max, 8u);
3196
84eb01be
TI		 3197 return 0;
3198}
3199
3de5ff88
AL		 3200/* VIA HDMI Implementation */
3201#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3202#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3203
3de5ff88
AL		 3204static int patch_via_hdmi(struct hda_codec *codec)
3205{
250e41ac 3206 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3de5ff88 3207}
84eb01be 3208
f0639272
TI		 3209/*
3210 * called from hda_codec.c for generic HDMI support
3211 */
3212int snd_hda_parse_hdmi_codec(struct hda_codec *codec)
3213{
3214 return patch_generic_hdmi(codec);
3215}
3216EXPORT_SYMBOL_HDA(snd_hda_parse_hdmi_codec);
3217
84eb01be
TI		 3218/*
3219 * patch entries
3220 */
fb79e1e0 3221static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
84eb01be
TI		 3222{ .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
3223{ .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
3224{ .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
5a613584 3225{ .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_atihdmi },
84eb01be
TI		 3226{ .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
3227{ .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
3228{ .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
3229{ .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3230{ .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3231{ .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3232{ .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3233{ .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
611885bc
AH		 3234{ .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_nvhdmi },
3235{ .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_nvhdmi },
3236{ .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_nvhdmi },
3237{ .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_nvhdmi },
3238{ .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_nvhdmi },
3239{ .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_nvhdmi },
3240{ .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_nvhdmi },
3241{ .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_nvhdmi },
3242{ .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_nvhdmi },
3243{ .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_nvhdmi },
3244{ .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_nvhdmi },
c8900a0f 3245/* 17 is known to be absent */
611885bc
AH		 3246{ .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_nvhdmi },
3247{ .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_nvhdmi },
3248{ .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_nvhdmi },
3249{ .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_nvhdmi },
3250{ .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_nvhdmi },
3251{ .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_nvhdmi },
3252{ .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_nvhdmi },
3253{ .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_nvhdmi },
3254{ .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_nvhdmi },
3255{ .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_nvhdmi },
3256{ .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_nvhdmi },
3257{ .id = 0x10de0060, .name = "GPU 60 HDMI/DP", .patch = patch_nvhdmi },
84eb01be
TI		 3258{ .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
3259{ .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
3de5ff88
AL		 3260{ .id = 0x11069f80, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
3261{ .id = 0x11069f81, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
3262{ .id = 0x11069f84, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
3263{ .id = 0x11069f85, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 3264{ .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
3265{ .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
3266{ .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
3267{ .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
3268{ .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
3269{ .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
591e610d 3270{ .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
1c76684d 3271{ .id = 0x80862807, .name = "Haswell HDMI", .patch = patch_generic_hdmi },
6edc59e6 3272{ .id = 0x80862880, .name = "CedarTrail HDMI", .patch = patch_generic_hdmi },
cc1a95d9 3273{ .id = 0x80862882, .name = "Valleyview2 HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 3274{ .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
3275{} /* terminator */
3276};
3277
3278MODULE_ALIAS("snd-hda-codec-id:1002793c");
3279MODULE_ALIAS("snd-hda-codec-id:10027919");
3280MODULE_ALIAS("snd-hda-codec-id:1002791a");
3281MODULE_ALIAS("snd-hda-codec-id:1002aa01");
3282MODULE_ALIAS("snd-hda-codec-id:10951390");
3283MODULE_ALIAS("snd-hda-codec-id:10951392");
3284MODULE_ALIAS("snd-hda-codec-id:10de0002");
3285MODULE_ALIAS("snd-hda-codec-id:10de0003");
3286MODULE_ALIAS("snd-hda-codec-id:10de0005");
3287MODULE_ALIAS("snd-hda-codec-id:10de0006");
3288MODULE_ALIAS("snd-hda-codec-id:10de0007");
3289MODULE_ALIAS("snd-hda-codec-id:10de000a");
3290MODULE_ALIAS("snd-hda-codec-id:10de000b");
3291MODULE_ALIAS("snd-hda-codec-id:10de000c");
3292MODULE_ALIAS("snd-hda-codec-id:10de000d");
3293MODULE_ALIAS("snd-hda-codec-id:10de0010");
3294MODULE_ALIAS("snd-hda-codec-id:10de0011");
3295MODULE_ALIAS("snd-hda-codec-id:10de0012");
3296MODULE_ALIAS("snd-hda-codec-id:10de0013");
3297MODULE_ALIAS("snd-hda-codec-id:10de0014");
c8900a0f
RS		 3298MODULE_ALIAS("snd-hda-codec-id:10de0015");
3299MODULE_ALIAS("snd-hda-codec-id:10de0016");
84eb01be
TI		 3300MODULE_ALIAS("snd-hda-codec-id:10de0018");
3301MODULE_ALIAS("snd-hda-codec-id:10de0019");
3302MODULE_ALIAS("snd-hda-codec-id:10de001a");
3303MODULE_ALIAS("snd-hda-codec-id:10de001b");
3304MODULE_ALIAS("snd-hda-codec-id:10de001c");
3305MODULE_ALIAS("snd-hda-codec-id:10de0040");
3306MODULE_ALIAS("snd-hda-codec-id:10de0041");
3307MODULE_ALIAS("snd-hda-codec-id:10de0042");
3308MODULE_ALIAS("snd-hda-codec-id:10de0043");
3309MODULE_ALIAS("snd-hda-codec-id:10de0044");
7ae48b56 3310MODULE_ALIAS("snd-hda-codec-id:10de0051");
d52392b1 3311MODULE_ALIAS("snd-hda-codec-id:10de0060");
84eb01be
TI		 3312MODULE_ALIAS("snd-hda-codec-id:10de0067");
3313MODULE_ALIAS("snd-hda-codec-id:10de8001");
3de5ff88
AL		 3314MODULE_ALIAS("snd-hda-codec-id:11069f80");
3315MODULE_ALIAS("snd-hda-codec-id:11069f81");
3316MODULE_ALIAS("snd-hda-codec-id:11069f84");
3317MODULE_ALIAS("snd-hda-codec-id:11069f85");
84eb01be
TI		 3318MODULE_ALIAS("snd-hda-codec-id:17e80047");
3319MODULE_ALIAS("snd-hda-codec-id:80860054");
3320MODULE_ALIAS("snd-hda-codec-id:80862801");
3321MODULE_ALIAS("snd-hda-codec-id:80862802");
3322MODULE_ALIAS("snd-hda-codec-id:80862803");
3323MODULE_ALIAS("snd-hda-codec-id:80862804");
3324MODULE_ALIAS("snd-hda-codec-id:80862805");
591e610d 3325MODULE_ALIAS("snd-hda-codec-id:80862806");
1c76684d 3326MODULE_ALIAS("snd-hda-codec-id:80862807");
6edc59e6 3327MODULE_ALIAS("snd-hda-codec-id:80862880");
cc1a95d9 3328MODULE_ALIAS("snd-hda-codec-id:80862882");
84eb01be
TI		 3329MODULE_ALIAS("snd-hda-codec-id:808629fb");
3330
3331MODULE_LICENSE("GPL");
3332MODULE_DESCRIPTION("HDMI HD-audio codec");
3333MODULE_ALIAS("snd-hda-codec-intelhdmi");
3334MODULE_ALIAS("snd-hda-codec-nvhdmi");
3335MODULE_ALIAS("snd-hda-codec-atihdmi");
3336
3337static struct hda_codec_preset_list intel_list = {
3338 .preset = snd_hda_preset_hdmi,
3339 .owner = THIS_MODULE,
3340};
3341
3342static int __init patch_hdmi_init(void)
3343{
3344 return snd_hda_add_codec_preset(&intel_list);
3345}
3346
3347static void __exit patch_hdmi_exit(void)
3348{
3349 snd_hda_delete_codec_preset(&intel_list);
3350}
3351
3352module_init(patch_hdmi_init)
3353module_exit(patch_hdmi_exit)
Linux kernel - Deliverables
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