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Revert "ALSA: emu10k1: Fix warning: "CCR" redefined"
[deliverable/linux.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
5a613584 9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
079d88cc
WF		 10 *
11 * Authors:
12 * Wu Fengguang <wfg@linux.intel.com>
13 *
14 * Maintained by:
15 * Wu Fengguang <wfg@linux.intel.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 * for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
84eb01be
TI		 32#include <linux/init.h>
33#include <linux/delay.h>
34#include <linux/slab.h>
65a77217 35#include <linux/module.h>
84eb01be 36#include <sound/core.h>
07acecc1 37#include <sound/jack.h>
433968da 38#include <sound/asoundef.h>
d45e6889 39#include <sound/tlv.h>
84eb01be
TI		 40#include "hda_codec.h"
41#include "hda_local.h"
1835a0f9 42#include "hda_jack.h"
84eb01be 43
0ebaa24c
TI		 44static bool static_hdmi_pcm;
45module_param(static_hdmi_pcm, bool, 0644);
46MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
47
fb87fa3a 48#define is_haswell(codec) ((codec)->vendor_id == 0x80862807)
75dcbe4d
ML		 49#define is_broadwell(codec) ((codec)->vendor_id == 0x80862808)
50#define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec))
51
02383854 52#define is_valleyview(codec) ((codec)->vendor_id == 0x80862882)
fb87fa3a 53
384a48d7
SW		 54struct hdmi_spec_per_cvt {
55 hda_nid_t cvt_nid;
56 int assigned;
57 unsigned int channels_min;
58 unsigned int channels_max;
59 u32 rates;
60 u64 formats;
61 unsigned int maxbps;
62};
079d88cc 63
4eea3091
TI		 64/* max. connections to a widget */
65#define HDA_MAX_CONNECTIONS 32
66
384a48d7
SW		 67struct hdmi_spec_per_pin {
68 hda_nid_t pin_nid;
69 int num_mux_nids;
70 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
1df5a06a 71 hda_nid_t cvt_nid;
744626da
WF		 72
73 struct hda_codec *codec;
384a48d7 74 struct hdmi_eld sink_eld;
a4e9a38b 75 struct mutex lock;
744626da 76 struct delayed_work work;
92c69e79 77 struct snd_kcontrol *eld_ctl;
c6e8453e 78 int repoll_count;
b054087d
TI		 79 bool setup; /* the stream has been set up by prepare callback */
80 int channels; /* current number of channels */
1a6003b5 81 bool non_pcm;
d45e6889
TI		 82 bool chmap_set; /* channel-map override by ALSA API? */
83 unsigned char chmap[8]; /* ALSA API channel-map */
bce0d2a8 84 char pcm_name[8]; /* filled in build_pcm callbacks */
a4e9a38b
TI		 85#ifdef CONFIG_PROC_FS
86 struct snd_info_entry *proc_entry;
87#endif
384a48d7 88};
079d88cc 89
307229d2
AH		 90struct cea_channel_speaker_allocation;
91
92/* operations used by generic code that can be overridden by patches */
93struct hdmi_ops {
94 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
95 unsigned char *buf, int *eld_size);
96
97 /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */
98 int (*pin_get_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
99 int asp_slot);
100 int (*pin_set_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
101 int asp_slot, int channel);
102
103 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
104 int ca, int active_channels, int conn_type);
105
106 /* enable/disable HBR (HD passthrough) */
107 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
108
109 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
110 hda_nid_t pin_nid, u32 stream_tag, int format);
111
112 /* Helpers for producing the channel map TLVs. These can be overridden
113 * for devices that have non-standard mapping requirements. */
114 int (*chmap_cea_alloc_validate_get_type)(struct cea_channel_speaker_allocation *cap,
115 int channels);
116 void (*cea_alloc_to_tlv_chmap)(struct cea_channel_speaker_allocation *cap,
117 unsigned int *chmap, int channels);
118
119 /* check that the user-given chmap is supported */
120 int (*chmap_validate)(int ca, int channels, unsigned char *chmap);
121};
122
384a48d7
SW		 123struct hdmi_spec {
124 int num_cvts;
bce0d2a8
TI		 125 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
126 hda_nid_t cvt_nids[4]; /* only for haswell fix */
079d88cc 127
384a48d7 128 int num_pins;
bce0d2a8
TI		 129 struct snd_array pins; /* struct hdmi_spec_per_pin */
130 struct snd_array pcm_rec; /* struct hda_pcm */
d45e6889 131 unsigned int channels_max; /* max over all cvts */
079d88cc 132
4bd038f9 133 struct hdmi_eld temp_eld;
307229d2 134 struct hdmi_ops ops;
75fae117
SW		 135
136 bool dyn_pin_out;
137
079d88cc 138 /*
5a613584 139 * Non-generic VIA/NVIDIA specific
079d88cc
WF		 140 */
141 struct hda_multi_out multiout;
d0b1252d 142 struct hda_pcm_stream pcm_playback;
079d88cc
WF		 143};
144
145
146struct hdmi_audio_infoframe {
147 u8 type; /* 0x84 */
148 u8 ver; /* 0x01 */
149 u8 len; /* 0x0a */
150
53d7d69d
WF		 151 u8 checksum;
152
079d88cc
WF		 153 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
154 u8 SS01_SF24;
155 u8 CXT04;
156 u8 CA;
157 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 158};
159
160struct dp_audio_infoframe {
161 u8 type; /* 0x84 */
162 u8 len; /* 0x1b */
163 u8 ver; /* 0x11 << 2 */
164
165 u8 CC02_CT47; /* match with HDMI infoframe from this on */
166 u8 SS01_SF24;
167 u8 CXT04;
168 u8 CA;
169 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 170};
171
2b203dbb
TI		 172union audio_infoframe {
173 struct hdmi_audio_infoframe hdmi;
174 struct dp_audio_infoframe dp;
175 u8 bytes[0];
176};
177
079d88cc
WF		 178/*
179 * CEA speaker placement:
180 *
181 * FLH FCH FRH
182 * FLW FL FLC FC FRC FR FRW
183 *
184 * LFE
185 * TC
186 *
187 * RL RLC RC RRC RR
188 *
189 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
190 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
191 */
192enum cea_speaker_placement {
193 FL = (1 << 0), /* Front Left */
194 FC = (1 << 1), /* Front Center */
195 FR = (1 << 2), /* Front Right */
196 FLC = (1 << 3), /* Front Left Center */
197 FRC = (1 << 4), /* Front Right Center */
198 RL = (1 << 5), /* Rear Left */
199 RC = (1 << 6), /* Rear Center */
200 RR = (1 << 7), /* Rear Right */
201 RLC = (1 << 8), /* Rear Left Center */
202 RRC = (1 << 9), /* Rear Right Center */
203 LFE = (1 << 10), /* Low Frequency Effect */
204 FLW = (1 << 11), /* Front Left Wide */
205 FRW = (1 << 12), /* Front Right Wide */
206 FLH = (1 << 13), /* Front Left High */
207 FCH = (1 << 14), /* Front Center High */
208 FRH = (1 << 15), /* Front Right High */
209 TC = (1 << 16), /* Top Center */
210};
211
212/*
213 * ELD SA bits in the CEA Speaker Allocation data block
214 */
215static int eld_speaker_allocation_bits[] = {
216 [0] = FL | FR,
217 [1] = LFE,
218 [2] = FC,
219 [3] = RL | RR,
220 [4] = RC,
221 [5] = FLC | FRC,
222 [6] = RLC | RRC,
223 /* the following are not defined in ELD yet */
224 [7] = FLW | FRW,
225 [8] = FLH | FRH,
226 [9] = TC,
227 [10] = FCH,
228};
229
230struct cea_channel_speaker_allocation {
231 int ca_index;
232 int speakers[8];
233
234 /* derived values, just for convenience */
235 int channels;
236 int spk_mask;
237};
238
239/*
240 * ALSA sequence is:
241 *
242 * surround40 surround41 surround50 surround51 surround71
243 * ch0 front left = = = =
244 * ch1 front right = = = =
245 * ch2 rear left = = = =
246 * ch3 rear right = = = =
247 * ch4 LFE center center center
248 * ch5 LFE LFE
249 * ch6 side left
250 * ch7 side right
251 *
252 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
253 */
254static int hdmi_channel_mapping[0x32][8] = {
255 /* stereo */
256 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
257 /* 2.1 */
258 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
259 /* Dolby Surround */
260 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
261 /* surround40 */
262 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
263 /* 4ch */
264 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
265 /* surround41 */
9396d317 266 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
079d88cc
WF		 267 /* surround50 */
268 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
269 /* surround51 */
270 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
271 /* 7.1 */
272 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
273};
274
275/*
276 * This is an ordered list!
277 *
278 * The preceding ones have better chances to be selected by
53d7d69d 279 * hdmi_channel_allocation().
079d88cc
WF		 280 */
281static struct cea_channel_speaker_allocation channel_allocations[] = {
282/* channel: 7 6 5 4 3 2 1 0 */
283{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
284 /* 2.1 */
285{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
286 /* Dolby Surround */
287{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
288 /* surround40 */
289{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
290 /* surround41 */
291{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
292 /* surround50 */
293{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
294 /* surround51 */
295{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
296 /* 6.1 */
297{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
298 /* surround71 */
299{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
300
301{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
302{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
303{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
304{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
305{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
306{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
307{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
308{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
309{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
310{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
311{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
312{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
313{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
314{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
315{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
316{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
317{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
318{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
319{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
320{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
321{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
322{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
323{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
324{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
325{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
326{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
327{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
328{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
329{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
330{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
331{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
332{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
333{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
334{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
335{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
336{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
337{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
338{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
339{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
340{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
341{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
342};
343
344
345/*
346 * HDMI routines
347 */
348
bce0d2a8
TI		 349#define get_pin(spec, idx) \
350 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
351#define get_cvt(spec, idx) \
352 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
353#define get_pcm_rec(spec, idx) \
354 ((struct hda_pcm *)snd_array_elem(&spec->pcm_rec, idx))
355
4e76a883 356static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc 357{
4e76a883 358 struct hdmi_spec *spec = codec->spec;
384a48d7 359 int pin_idx;
079d88cc 360
384a48d7 361 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 362 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
384a48d7 363 return pin_idx;
079d88cc 364
4e76a883 365 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
384a48d7
SW		 366 return -EINVAL;
367}
368
4e76a883 369static int hinfo_to_pin_index(struct hda_codec *codec,
384a48d7
SW		 370 struct hda_pcm_stream *hinfo)
371{
4e76a883 372 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 373 int pin_idx;
374
375 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 376 if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
384a48d7
SW		 377 return pin_idx;
378
4e76a883 379 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
384a48d7
SW		 380 return -EINVAL;
381}
382
4e76a883 383static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
384a48d7 384{
4e76a883 385 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 386 int cvt_idx;
387
388 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
bce0d2a8 389 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
384a48d7
SW		 390 return cvt_idx;
391
4e76a883 392 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 393 return -EINVAL;
394}
395
14bc52b8
PLB		 396static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
397 struct snd_ctl_elem_info *uinfo)
398{
399 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 400 struct hdmi_spec *spec = codec->spec;
a4e9a38b 401 struct hdmi_spec_per_pin *per_pin;
68e03de9 402 struct hdmi_eld *eld;
14bc52b8
PLB		 403 int pin_idx;
404
14bc52b8
PLB		 405 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
406
407 pin_idx = kcontrol->private_value;
a4e9a38b
TI		 408 per_pin = get_pin(spec, pin_idx);
409 eld = &per_pin->sink_eld;
68e03de9 410
a4e9a38b 411 mutex_lock(&per_pin->lock);
68e03de9 412 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
a4e9a38b 413 mutex_unlock(&per_pin->lock);
14bc52b8
PLB		 414
415 return 0;
416}
417
418static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
419 struct snd_ctl_elem_value *ucontrol)
420{
421 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 422 struct hdmi_spec *spec = codec->spec;
a4e9a38b 423 struct hdmi_spec_per_pin *per_pin;
68e03de9 424 struct hdmi_eld *eld;
14bc52b8
PLB		 425 int pin_idx;
426
14bc52b8 427 pin_idx = kcontrol->private_value;
a4e9a38b
TI		 428 per_pin = get_pin(spec, pin_idx);
429 eld = &per_pin->sink_eld;
68e03de9 430
a4e9a38b 431 mutex_lock(&per_pin->lock);
68e03de9 432 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) {
a4e9a38b 433 mutex_unlock(&per_pin->lock);
68e03de9
DH		 434 snd_BUG();
435 return -EINVAL;
436 }
437
438 memset(ucontrol->value.bytes.data, 0,
439 ARRAY_SIZE(ucontrol->value.bytes.data));
440 if (eld->eld_valid)
441 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
442 eld->eld_size);
a4e9a38b 443 mutex_unlock(&per_pin->lock);
14bc52b8
PLB		 444
445 return 0;
446}
447
448static struct snd_kcontrol_new eld_bytes_ctl = {
449 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
450 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
451 .name = "ELD",
452 .info = hdmi_eld_ctl_info,
453 .get = hdmi_eld_ctl_get,
454};
455
456static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
457 int device)
458{
459 struct snd_kcontrol *kctl;
460 struct hdmi_spec *spec = codec->spec;
461 int err;
462
463 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
464 if (!kctl)
465 return -ENOMEM;
466 kctl->private_value = pin_idx;
467 kctl->id.device = device;
468
bce0d2a8 469 err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
14bc52b8
PLB		 470 if (err < 0)
471 return err;
472
bce0d2a8 473 get_pin(spec, pin_idx)->eld_ctl = kctl;
14bc52b8
PLB		 474 return 0;
475}
476
079d88cc
WF		 477#ifdef BE_PARANOID
478static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
479 int *packet_index, int *byte_index)
480{
481 int val;
482
483 val = snd_hda_codec_read(codec, pin_nid, 0,
484 AC_VERB_GET_HDMI_DIP_INDEX, 0);
485
486 *packet_index = val >> 5;
487 *byte_index = val & 0x1f;
488}
489#endif
490
491static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
492 int packet_index, int byte_index)
493{
494 int val;
495
496 val = (packet_index << 5) | (byte_index & 0x1f);
497
498 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
499}
500
501static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
502 unsigned char val)
503{
504 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
505}
506
384a48d7 507static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc 508{
75fae117
SW		 509 struct hdmi_spec *spec = codec->spec;
510 int pin_out;
511
079d88cc
WF		 512 /* Unmute */
513 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
514 snd_hda_codec_write(codec, pin_nid, 0,
515 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
75fae117
SW		 516
517 if (spec->dyn_pin_out)
518 /* Disable pin out until stream is active */
519 pin_out = 0;
520 else
521 /* Enable pin out: some machines with GM965 gets broken output
522 * when the pin is disabled or changed while using with HDMI
523 */
524 pin_out = PIN_OUT;
525
079d88cc 526 snd_hda_codec_write(codec, pin_nid, 0,
75fae117 527 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
079d88cc
WF		 528}
529
384a48d7 530static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc 531{
384a48d7 532 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
079d88cc
WF		 533 AC_VERB_GET_CVT_CHAN_COUNT, 0);
534}
535
536static void hdmi_set_channel_count(struct hda_codec *codec,
384a48d7 537 hda_nid_t cvt_nid, int chs)
079d88cc 538{
384a48d7
SW		 539 if (chs != hdmi_get_channel_count(codec, cvt_nid))
540 snd_hda_codec_write(codec, cvt_nid, 0,
079d88cc
WF		 541 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
542}
543
a4e9a38b
TI		 544/*
545 * ELD proc files
546 */
547
548#ifdef CONFIG_PROC_FS
549static void print_eld_info(struct snd_info_entry *entry,
550 struct snd_info_buffer *buffer)
551{
552 struct hdmi_spec_per_pin *per_pin = entry->private_data;
553
554 mutex_lock(&per_pin->lock);
555 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
556 mutex_unlock(&per_pin->lock);
557}
558
559static void write_eld_info(struct snd_info_entry *entry,
560 struct snd_info_buffer *buffer)
561{
562 struct hdmi_spec_per_pin *per_pin = entry->private_data;
563
564 mutex_lock(&per_pin->lock);
565 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
566 mutex_unlock(&per_pin->lock);
567}
568
569static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
570{
571 char name[32];
572 struct hda_codec *codec = per_pin->codec;
573 struct snd_info_entry *entry;
574 int err;
575
576 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
577 err = snd_card_proc_new(codec->bus->card, name, &entry);
578 if (err < 0)
579 return err;
580
581 snd_info_set_text_ops(entry, per_pin, print_eld_info);
582 entry->c.text.write = write_eld_info;
583 entry->mode |= S_IWUSR;
584 per_pin->proc_entry = entry;
585
586 return 0;
587}
588
589static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
590{
591 if (!per_pin->codec->bus->shutdown && per_pin->proc_entry) {
592 snd_device_free(per_pin->codec->bus->card, per_pin->proc_entry);
593 per_pin->proc_entry = NULL;
594 }
595}
596#else
b55447a7
TI		 597static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
598 int index)
a4e9a38b
TI		 599{
600 return 0;
601}
b55447a7 602static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
a4e9a38b
TI		 603{
604}
605#endif
079d88cc
WF		 606
607/*
608 * Channel mapping routines
609 */
610
611/*
612 * Compute derived values in channel_allocations[].
613 */
614static void init_channel_allocations(void)
615{
616 int i, j;
617 struct cea_channel_speaker_allocation *p;
618
619 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
620 p = channel_allocations + i;
621 p->channels = 0;
622 p->spk_mask = 0;
623 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
624 if (p->speakers[j]) {
625 p->channels++;
626 p->spk_mask |= p->speakers[j];
627 }
628 }
629}
630
72357c78
WX		 631static int get_channel_allocation_order(int ca)
632{
633 int i;
634
635 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
636 if (channel_allocations[i].ca_index == ca)
637 break;
638 }
639 return i;
640}
641
079d88cc
WF		 642/*
643 * The transformation takes two steps:
644 *
645 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
646 * spk_mask => (channel_allocations[]) => ai->CA
647 *
648 * TODO: it could select the wrong CA from multiple candidates.
649*/
384a48d7 650static int hdmi_channel_allocation(struct hdmi_eld *eld, int channels)
079d88cc 651{
079d88cc 652 int i;
53d7d69d 653 int ca = 0;
079d88cc 654 int spk_mask = 0;
079d88cc
WF		 655 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
656
657 /*
658 * CA defaults to 0 for basic stereo audio
659 */
660 if (channels <= 2)
661 return 0;
662
079d88cc
WF		 663 /*
664 * expand ELD's speaker allocation mask
665 *
666 * ELD tells the speaker mask in a compact(paired) form,
667 * expand ELD's notions to match the ones used by Audio InfoFrame.
668 */
669 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
1613d6b4 670 if (eld->info.spk_alloc & (1 << i))
079d88cc
WF		 671 spk_mask |= eld_speaker_allocation_bits[i];
672 }
673
674 /* search for the first working match in the CA table */
675 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
676 if (channels == channel_allocations[i].channels &&
677 (spk_mask & channel_allocations[i].spk_mask) ==
678 channel_allocations[i].spk_mask) {
53d7d69d 679 ca = channel_allocations[i].ca_index;
079d88cc
WF		 680 break;
681 }
682 }
683
18e39186
AH		 684 if (!ca) {
685 /* if there was no match, select the regular ALSA channel
686 * allocation with the matching number of channels */
687 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
688 if (channels == channel_allocations[i].channels) {
689 ca = channel_allocations[i].ca_index;
690 break;
691 }
692 }
693 }
694
1613d6b4 695 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
2abbf439 696 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
53d7d69d 697 ca, channels, buf);
079d88cc 698
53d7d69d 699 return ca;
079d88cc
WF		 700}
701
702static void hdmi_debug_channel_mapping(struct hda_codec *codec,
703 hda_nid_t pin_nid)
704{
705#ifdef CONFIG_SND_DEBUG_VERBOSE
307229d2 706 struct hdmi_spec *spec = codec->spec;
079d88cc 707 int i;
307229d2 708 int channel;
079d88cc
WF		 709
710 for (i = 0; i < 8; i++) {
307229d2 711 channel = spec->ops.pin_get_slot_channel(codec, pin_nid, i);
4e76a883 712 codec_dbg(codec, "HDMI: ASP channel %d => slot %d\n",
307229d2 713 channel, i);
079d88cc
WF		 714 }
715#endif
716}
717
d45e6889 718static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
079d88cc 719 hda_nid_t pin_nid,
433968da 720 bool non_pcm,
53d7d69d 721 int ca)
079d88cc 722{
307229d2 723 struct hdmi_spec *spec = codec->spec;
90f28002 724 struct cea_channel_speaker_allocation *ch_alloc;
079d88cc 725 int i;
079d88cc 726 int err;
72357c78 727 int order;
433968da 728 int non_pcm_mapping[8];
079d88cc 729
72357c78 730 order = get_channel_allocation_order(ca);
90f28002 731 ch_alloc = &channel_allocations[order];
433968da 732
079d88cc 733 if (hdmi_channel_mapping[ca][1] == 0) {
90f28002
AH		 734 int hdmi_slot = 0;
735 /* fill actual channel mappings in ALSA channel (i) order */
736 for (i = 0; i < ch_alloc->channels; i++) {
737 while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
738 hdmi_slot++; /* skip zero slots */
739
740 hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
741 }
742 /* fill the rest of the slots with ALSA channel 0xf */
743 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
744 if (!ch_alloc->speakers[7 - hdmi_slot])
745 hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
079d88cc
WF		 746 }
747
433968da 748 if (non_pcm) {
90f28002 749 for (i = 0; i < ch_alloc->channels; i++)
11f7c52d 750 non_pcm_mapping[i] = (i << 4) | i;
433968da 751 for (; i < 8; i++)
11f7c52d 752 non_pcm_mapping[i] = (0xf << 4) | i;
433968da
WX		 753 }
754
079d88cc 755 for (i = 0; i < 8; i++) {
307229d2
AH		 756 int slotsetup = non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i];
757 int hdmi_slot = slotsetup & 0x0f;
758 int channel = (slotsetup & 0xf0) >> 4;
759 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, channel);
079d88cc 760 if (err) {
4e76a883 761 codec_dbg(codec, "HDMI: channel mapping failed\n");
079d88cc
WF		 762 break;
763 }
764 }
079d88cc
WF		 765}
766
d45e6889
TI		 767struct channel_map_table {
768 unsigned char map; /* ALSA API channel map position */
d45e6889
TI		 769 int spk_mask; /* speaker position bit mask */
770};
771
772static struct channel_map_table map_tables[] = {
a5b7d510
AH		 773 { SNDRV_CHMAP_FL, FL },
774 { SNDRV_CHMAP_FR, FR },
775 { SNDRV_CHMAP_RL, RL },
776 { SNDRV_CHMAP_RR, RR },
777 { SNDRV_CHMAP_LFE, LFE },
778 { SNDRV_CHMAP_FC, FC },
779 { SNDRV_CHMAP_RLC, RLC },
780 { SNDRV_CHMAP_RRC, RRC },
781 { SNDRV_CHMAP_RC, RC },
782 { SNDRV_CHMAP_FLC, FLC },
783 { SNDRV_CHMAP_FRC, FRC },
94908a39
AH		 784 { SNDRV_CHMAP_TFL, FLH },
785 { SNDRV_CHMAP_TFR, FRH },
a5b7d510
AH		 786 { SNDRV_CHMAP_FLW, FLW },
787 { SNDRV_CHMAP_FRW, FRW },
788 { SNDRV_CHMAP_TC, TC },
94908a39 789 { SNDRV_CHMAP_TFC, FCH },
d45e6889
TI		 790 {} /* terminator */
791};
792
793/* from ALSA API channel position to speaker bit mask */
794static int to_spk_mask(unsigned char c)
795{
796 struct channel_map_table *t = map_tables;
797 for (; t->map; t++) {
798 if (t->map == c)
799 return t->spk_mask;
800 }
801 return 0;
802}
803
804/* from ALSA API channel position to CEA slot */
a5b7d510 805static int to_cea_slot(int ordered_ca, unsigned char pos)
d45e6889 806{
a5b7d510
AH		 807 int mask = to_spk_mask(pos);
808 int i;
d45e6889 809
a5b7d510
AH		 810 if (mask) {
811 for (i = 0; i < 8; i++) {
812 if (channel_allocations[ordered_ca].speakers[7 - i] == mask)
813 return i;
814 }
d45e6889 815 }
a5b7d510
AH		 816
817 return -1;
d45e6889
TI		 818}
819
820/* from speaker bit mask to ALSA API channel position */
821static int spk_to_chmap(int spk)
822{
823 struct channel_map_table *t = map_tables;
824 for (; t->map; t++) {
825 if (t->spk_mask == spk)
826 return t->map;
827 }
828 return 0;
829}
830
a5b7d510
AH		 831/* from CEA slot to ALSA API channel position */
832static int from_cea_slot(int ordered_ca, unsigned char slot)
833{
834 int mask = channel_allocations[ordered_ca].speakers[7 - slot];
835
836 return spk_to_chmap(mask);
837}
838
d45e6889
TI		 839/* get the CA index corresponding to the given ALSA API channel map */
840static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
841{
842 int i, spks = 0, spk_mask = 0;
843
844 for (i = 0; i < chs; i++) {
845 int mask = to_spk_mask(map[i]);
846 if (mask) {
847 spk_mask |= mask;
848 spks++;
849 }
850 }
851
852 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
853 if ((chs == channel_allocations[i].channels ||
854 spks == channel_allocations[i].channels) &&
855 (spk_mask & channel_allocations[i].spk_mask) ==
856 channel_allocations[i].spk_mask)
857 return channel_allocations[i].ca_index;
858 }
859 return -1;
860}
861
862/* set up the channel slots for the given ALSA API channel map */
863static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
864 hda_nid_t pin_nid,
a5b7d510
AH		 865 int chs, unsigned char *map,
866 int ca)
d45e6889 867{
307229d2 868 struct hdmi_spec *spec = codec->spec;
a5b7d510 869 int ordered_ca = get_channel_allocation_order(ca);
11f7c52d
AH		 870 int alsa_pos, hdmi_slot;
871 int assignments[8] = {[0 ... 7] = 0xf};
872
873 for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) {
874
a5b7d510 875 hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]);
11f7c52d
AH		 876
877 if (hdmi_slot < 0)
878 continue; /* unassigned channel */
879
880 assignments[hdmi_slot] = alsa_pos;
881 }
882
883 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) {
307229d2 884 int err;
11f7c52d 885
307229d2
AH		 886 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot,
887 assignments[hdmi_slot]);
d45e6889
TI		 888 if (err)
889 return -EINVAL;
890 }
891 return 0;
892}
893
894/* store ALSA API channel map from the current default map */
895static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
896{
897 int i;
56cac413 898 int ordered_ca = get_channel_allocation_order(ca);
d45e6889 899 for (i = 0; i < 8; i++) {
56cac413 900 if (i < channel_allocations[ordered_ca].channels)
a5b7d510 901 map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f);
d45e6889
TI		 902 else
903 map[i] = 0;
904 }
905}
906
907static void hdmi_setup_channel_mapping(struct hda_codec *codec,
908 hda_nid_t pin_nid, bool non_pcm, int ca,
20608731
AH		 909 int channels, unsigned char *map,
910 bool chmap_set)
d45e6889 911{
20608731 912 if (!non_pcm && chmap_set) {
d45e6889 913 hdmi_manual_setup_channel_mapping(codec, pin_nid,
a5b7d510 914 channels, map, ca);
d45e6889
TI		 915 } else {
916 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
917 hdmi_setup_fake_chmap(map, ca);
918 }
980b2495
AH		 919
920 hdmi_debug_channel_mapping(codec, pin_nid);
d45e6889 921}
079d88cc 922
307229d2
AH		 923static int hdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
924 int asp_slot, int channel)
925{
926 return snd_hda_codec_write(codec, pin_nid, 0,
927 AC_VERB_SET_HDMI_CHAN_SLOT,
928 (channel << 4) | asp_slot);
929}
930
931static int hdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
932 int asp_slot)
933{
934 return (snd_hda_codec_read(codec, pin_nid, 0,
935 AC_VERB_GET_HDMI_CHAN_SLOT,
936 asp_slot) & 0xf0) >> 4;
937}
938
079d88cc
WF		 939/*
940 * Audio InfoFrame routines
941 */
942
943/*
944 * Enable Audio InfoFrame Transmission
945 */
946static void hdmi_start_infoframe_trans(struct hda_codec *codec,
947 hda_nid_t pin_nid)
948{
949 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
950 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
951 AC_DIPXMIT_BEST);
952}
953
954/*
955 * Disable Audio InfoFrame Transmission
956 */
957static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
958 hda_nid_t pin_nid)
959{
960 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
961 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
962 AC_DIPXMIT_DISABLE);
963}
964
965static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
966{
967#ifdef CONFIG_SND_DEBUG_VERBOSE
968 int i;
969 int size;
970
971 size = snd_hdmi_get_eld_size(codec, pin_nid);
4e76a883 972 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
079d88cc
WF		 973
974 for (i = 0; i < 8; i++) {
975 size = snd_hda_codec_read(codec, pin_nid, 0,
976 AC_VERB_GET_HDMI_DIP_SIZE, i);
4e76a883 977 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
079d88cc
WF		 978 }
979#endif
980}
981
982static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
983{
984#ifdef BE_PARANOID
985 int i, j;
986 int size;
987 int pi, bi;
988 for (i = 0; i < 8; i++) {
989 size = snd_hda_codec_read(codec, pin_nid, 0,
990 AC_VERB_GET_HDMI_DIP_SIZE, i);
991 if (size == 0)
992 continue;
993
994 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
995 for (j = 1; j < 1000; j++) {
996 hdmi_write_dip_byte(codec, pin_nid, 0x0);
997 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
998 if (pi != i)
4e76a883 999 codec_dbg(codec, "dip index %d: %d != %d\n",
079d88cc
WF		 1000 bi, pi, i);
1001 if (bi == 0) /* byte index wrapped around */
1002 break;
1003 }
4e76a883 1004 codec_dbg(codec,
079d88cc
WF		 1005 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
1006 i, size, j);
1007 }
1008#endif
1009}
1010
53d7d69d 1011static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 1012{
53d7d69d 1013 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 1014 u8 sum = 0;
1015 int i;
1016
53d7d69d 1017 hdmi_ai->checksum = 0;
079d88cc 1018
53d7d69d 1019 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 1020 sum += bytes[i];
1021
53d7d69d 1022 hdmi_ai->checksum = -sum;
079d88cc
WF		 1023}
1024
1025static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
1026 hda_nid_t pin_nid,
53d7d69d 1027 u8 *dip, int size)
079d88cc 1028{
079d88cc
WF		 1029 int i;
1030
1031 hdmi_debug_dip_size(codec, pin_nid);
1032 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
1033
079d88cc 1034 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 1035 for (i = 0; i < size; i++)
1036 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 1037}
1038
1039static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 1040 u8 *dip, int size)
079d88cc 1041{
079d88cc
WF		 1042 u8 val;
1043 int i;
1044
1045 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
1046 != AC_DIPXMIT_BEST)
1047 return false;
1048
1049 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 1050 for (i = 0; i < size; i++) {
079d88cc
WF		 1051 val = snd_hda_codec_read(codec, pin_nid, 0,
1052 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 1053 if (val != dip[i])
079d88cc
WF		 1054 return false;
1055 }
1056
1057 return true;
1058}
1059
307229d2
AH		 1060static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
1061 hda_nid_t pin_nid,
1062 int ca, int active_channels,
1063 int conn_type)
1064{
1065 union audio_infoframe ai;
1066
1067 if (conn_type == 0) { /* HDMI */
1068 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
1069
1070 hdmi_ai->type = 0x84;
1071 hdmi_ai->ver = 0x01;
1072 hdmi_ai->len = 0x0a;
1073 hdmi_ai->CC02_CT47 = active_channels - 1;
1074 hdmi_ai->CA = ca;
1075 hdmi_checksum_audio_infoframe(hdmi_ai);
1076 } else if (conn_type == 1) { /* DisplayPort */
1077 struct dp_audio_infoframe *dp_ai = &ai.dp;
1078
1079 dp_ai->type = 0x84;
1080 dp_ai->len = 0x1b;
1081 dp_ai->ver = 0x11 << 2;
1082 dp_ai->CC02_CT47 = active_channels - 1;
1083 dp_ai->CA = ca;
1084 } else {
4e76a883 1085 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
307229d2
AH		 1086 pin_nid);
1087 return;
1088 }
1089
1090 /*
1091 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
1092 * sizeof(*dp_ai) to avoid partial match/update problems when
1093 * the user switches between HDMI/DP monitors.
1094 */
1095 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
1096 sizeof(ai))) {
4e76a883
TI		 1097 codec_dbg(codec,
1098 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
307229d2
AH		 1099 pin_nid,
1100 active_channels, ca);
1101 hdmi_stop_infoframe_trans(codec, pin_nid);
1102 hdmi_fill_audio_infoframe(codec, pin_nid,
1103 ai.bytes, sizeof(ai));
1104 hdmi_start_infoframe_trans(codec, pin_nid);
1105 }
1106}
1107
b054087d
TI		 1108static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
1109 struct hdmi_spec_per_pin *per_pin,
1110 bool non_pcm)
079d88cc 1111{
307229d2 1112 struct hdmi_spec *spec = codec->spec;
384a48d7 1113 hda_nid_t pin_nid = per_pin->pin_nid;
b054087d 1114 int channels = per_pin->channels;
1df5a06a 1115 int active_channels;
384a48d7 1116 struct hdmi_eld *eld;
1df5a06a 1117 int ca, ordered_ca;
079d88cc 1118
b054087d
TI		 1119 if (!channels)
1120 return;
1121
75dcbe4d 1122 if (is_haswell_plus(codec))
58f7d28d
ML		 1123 snd_hda_codec_write(codec, pin_nid, 0,
1124 AC_VERB_SET_AMP_GAIN_MUTE,
1125 AMP_OUT_UNMUTE);
1126
bce0d2a8 1127 eld = &per_pin->sink_eld;
384a48d7
SW		 1128 if (!eld->monitor_present)
1129 return;
079d88cc 1130
d45e6889
TI		 1131 if (!non_pcm && per_pin->chmap_set)
1132 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
1133 else
1134 ca = hdmi_channel_allocation(eld, channels);
1135 if (ca < 0)
1136 ca = 0;
384a48d7 1137
1df5a06a
AH		 1138 ordered_ca = get_channel_allocation_order(ca);
1139 active_channels = channel_allocations[ordered_ca].channels;
1140
1141 hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels);
1142
39edac70
AH		 1143 /*
1144 * always configure channel mapping, it may have been changed by the
1145 * user in the meantime
1146 */
1147 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
1148 channels, per_pin->chmap,
1149 per_pin->chmap_set);
1150
307229d2
AH		 1151 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
1152 eld->info.conn_type);
433968da 1153
1a6003b5 1154 per_pin->non_pcm = non_pcm;
079d88cc
WF		 1155}
1156
079d88cc
WF		 1157/*
1158 * Unsolicited events
1159 */
1160
efe47108 1161static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
38faddb1 1162
20ce9029 1163static void jack_callback(struct hda_codec *codec, struct hda_jack_tbl *jack)
079d88cc
WF		 1164{
1165 struct hdmi_spec *spec = codec->spec;
4e76a883 1166 int pin_idx = pin_nid_to_pin_index(codec, jack->nid);
20ce9029
DH		 1167 if (pin_idx < 0)
1168 return;
1169
1170 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
1171 snd_hda_jack_report_sync(codec);
1172}
1173
1174static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
1175{
3a93897e 1176 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
3a93897e 1177 struct hda_jack_tbl *jack;
2e59e5ab 1178 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
3a93897e
TI		 1179
1180 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
1181 if (!jack)
1182 return;
3a93897e 1183 jack->jack_dirty = 1;
079d88cc 1184
4e76a883 1185 codec_dbg(codec,
2e59e5ab 1186 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
20ce9029 1187 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
fae3d88a 1188 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
079d88cc 1189
20ce9029 1190 jack_callback(codec, jack);
079d88cc
WF		 1191}
1192
1193static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
1194{
1195 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1196 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1197 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
1198 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
1199
4e76a883 1200 codec_info(codec,
e9ea8e8f 1201 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
384a48d7 1202 codec->addr,
079d88cc
WF		 1203 tag,
1204 subtag,
1205 cp_state,
1206 cp_ready);
1207
1208 /* TODO */
1209 if (cp_state)
1210 ;
1211 if (cp_ready)
1212 ;
1213}
1214
1215
1216static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1217{
079d88cc
WF		 1218 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1219 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1220
3a93897e 1221 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
4e76a883 1222 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
079d88cc
WF		 1223 return;
1224 }
1225
1226 if (subtag == 0)
1227 hdmi_intrinsic_event(codec, res);
1228 else
1229 hdmi_non_intrinsic_event(codec, res);
1230}
1231
58f7d28d 1232static void haswell_verify_D0(struct hda_codec *codec,
53b434f0 1233 hda_nid_t cvt_nid, hda_nid_t nid)
83f26ad2 1234{
58f7d28d 1235 int pwr;
83f26ad2 1236
53b434f0
WX		 1237 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1238 * thus pins could only choose converter 0 for use. Make sure the
1239 * converters are in correct power state */
fd678cac 1240 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
53b434f0
WX		 1241 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1242
fd678cac 1243 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
83f26ad2
DH		 1244 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1245 AC_PWRST_D0);
1246 msleep(40);
1247 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1248 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
4e76a883 1249 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
83f26ad2 1250 }
83f26ad2
DH		 1251}
1252
079d88cc
WF		 1253/*
1254 * Callbacks
1255 */
1256
92f10b3f
TI		 1257/* HBR should be Non-PCM, 8 channels */
1258#define is_hbr_format(format) \
1259 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1260
307229d2
AH		 1261static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
1262 bool hbr)
079d88cc 1263{
307229d2 1264 int pinctl, new_pinctl;
83f26ad2 1265
384a48d7
SW		 1266 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1267 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 1268 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1269
13122e6e
AH		 1270 if (pinctl < 0)
1271 return hbr ? -EINVAL : 0;
1272
ea87d1c4 1273 new_pinctl = pinctl & ~AC_PINCTL_EPT;
307229d2 1274 if (hbr)
ea87d1c4
AH		 1275 new_pinctl |= AC_PINCTL_EPT_HBR;
1276 else
1277 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1278
4e76a883
TI		 1279 codec_dbg(codec,
1280 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
384a48d7 1281 pin_nid,
ea87d1c4
AH		 1282 pinctl == new_pinctl ? "" : "new-",
1283 new_pinctl);
1284
1285 if (pinctl != new_pinctl)
384a48d7 1286 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 1287 AC_VERB_SET_PIN_WIDGET_CONTROL,
1288 new_pinctl);
307229d2
AH		 1289 } else if (hbr)
1290 return -EINVAL;
ea87d1c4 1291
307229d2
AH		 1292 return 0;
1293}
1294
1295static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1296 hda_nid_t pin_nid, u32 stream_tag, int format)
1297{
1298 struct hdmi_spec *spec = codec->spec;
1299 int err;
1300
75dcbe4d 1301 if (is_haswell_plus(codec))
307229d2
AH		 1302 haswell_verify_D0(codec, cvt_nid, pin_nid);
1303
1304 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
1305
1306 if (err) {
4e76a883 1307 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
307229d2 1308 return err;
ea87d1c4 1309 }
079d88cc 1310
384a48d7 1311 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 1312 return 0;
079d88cc
WF		 1313}
1314
7ef166b8
WX		 1315static int hdmi_choose_cvt(struct hda_codec *codec,
1316 int pin_idx, int *cvt_id, int *mux_id)
bbbe3390
TI		 1317{
1318 struct hdmi_spec *spec = codec->spec;
384a48d7 1319 struct hdmi_spec_per_pin *per_pin;
384a48d7 1320 struct hdmi_spec_per_cvt *per_cvt = NULL;
7ef166b8 1321 int cvt_idx, mux_idx = 0;
bbbe3390 1322
bce0d2a8 1323 per_pin = get_pin(spec, pin_idx);
384a48d7
SW		 1324
1325 /* Dynamically assign converter to stream */
1326 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
bce0d2a8 1327 per_cvt = get_cvt(spec, cvt_idx);
bbbe3390 1328
384a48d7
SW		 1329 /* Must not already be assigned */
1330 if (per_cvt->assigned)
1331 continue;
1332 /* Must be in pin's mux's list of converters */
1333 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1334 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1335 break;
1336 /* Not in mux list */
1337 if (mux_idx == per_pin->num_mux_nids)
1338 continue;
1339 break;
1340 }
7ef166b8 1341
384a48d7
SW		 1342 /* No free converters */
1343 if (cvt_idx == spec->num_cvts)
1344 return -ENODEV;
1345
7ef166b8
WX		 1346 if (cvt_id)
1347 *cvt_id = cvt_idx;
1348 if (mux_id)
1349 *mux_id = mux_idx;
1350
1351 return 0;
1352}
1353
300016b9
ML		 1354/* Intel HDMI workaround to fix audio routing issue:
1355 * For some Intel display codecs, pins share the same connection list.
1356 * So a conveter can be selected by multiple pins and playback on any of these
1357 * pins will generate sound on the external display, because audio flows from
1358 * the same converter to the display pipeline. Also muting one pin may make
1359 * other pins have no sound output.
1360 * So this function assures that an assigned converter for a pin is not selected
1361 * by any other pins.
1362 */
1363static void intel_not_share_assigned_cvt(struct hda_codec *codec,
f82d7d16 1364 hda_nid_t pin_nid, int mux_idx)
7ef166b8
WX		 1365{
1366 struct hdmi_spec *spec = codec->spec;
f82d7d16
ML		 1367 hda_nid_t nid, end_nid;
1368 int cvt_idx, curr;
1369 struct hdmi_spec_per_cvt *per_cvt;
7ef166b8 1370
f82d7d16
ML		 1371 /* configure all pins, including "no physical connection" ones */
1372 end_nid = codec->start_nid + codec->num_nodes;
1373 for (nid = codec->start_nid; nid < end_nid; nid++) {
1374 unsigned int wid_caps = get_wcaps(codec, nid);
1375 unsigned int wid_type = get_wcaps_type(wid_caps);
1376
1377 if (wid_type != AC_WID_PIN)
1378 continue;
7ef166b8 1379
f82d7d16 1380 if (nid == pin_nid)
7ef166b8
WX		 1381 continue;
1382
f82d7d16 1383 curr = snd_hda_codec_read(codec, nid, 0,
7ef166b8 1384 AC_VERB_GET_CONNECT_SEL, 0);
f82d7d16
ML		 1385 if (curr != mux_idx)
1386 continue;
7ef166b8 1387
f82d7d16
ML		 1388 /* choose an unassigned converter. The conveters in the
1389 * connection list are in the same order as in the codec.
1390 */
1391 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1392 per_cvt = get_cvt(spec, cvt_idx);
1393 if (!per_cvt->assigned) {
4e76a883
TI		 1394 codec_dbg(codec,
1395 "choose cvt %d for pin nid %d\n",
f82d7d16
ML		 1396 cvt_idx, nid);
1397 snd_hda_codec_write_cache(codec, nid, 0,
7ef166b8 1398 AC_VERB_SET_CONNECT_SEL,
f82d7d16
ML		 1399 cvt_idx);
1400 break;
1401 }
7ef166b8
WX		 1402 }
1403 }
1404}
1405
1406/*
1407 * HDA PCM callbacks
1408 */
1409static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1410 struct hda_codec *codec,
1411 struct snd_pcm_substream *substream)
1412{
1413 struct hdmi_spec *spec = codec->spec;
1414 struct snd_pcm_runtime *runtime = substream->runtime;
1415 int pin_idx, cvt_idx, mux_idx = 0;
1416 struct hdmi_spec_per_pin *per_pin;
1417 struct hdmi_eld *eld;
1418 struct hdmi_spec_per_cvt *per_cvt = NULL;
1419 int err;
1420
1421 /* Validate hinfo */
4e76a883 1422 pin_idx = hinfo_to_pin_index(codec, hinfo);
7ef166b8
WX		 1423 if (snd_BUG_ON(pin_idx < 0))
1424 return -EINVAL;
1425 per_pin = get_pin(spec, pin_idx);
1426 eld = &per_pin->sink_eld;
1427
1428 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1429 if (err < 0)
1430 return err;
1431
1432 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1433 /* Claim converter */
1434 per_cvt->assigned = 1;
1df5a06a 1435 per_pin->cvt_nid = per_cvt->cvt_nid;
384a48d7
SW		 1436 hinfo->nid = per_cvt->cvt_nid;
1437
bddee96b 1438 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
384a48d7
SW		 1439 AC_VERB_SET_CONNECT_SEL,
1440 mux_idx);
7ef166b8
WX		 1441
1442 /* configure unused pins to choose other converters */
75dcbe4d 1443 if (is_haswell_plus(codec) || is_valleyview(codec))
300016b9 1444 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx);
7ef166b8 1445
384a48d7 1446 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
bbbe3390 1447
2def8172 1448 /* Initially set the converter's capabilities */
384a48d7
SW		 1449 hinfo->channels_min = per_cvt->channels_min;
1450 hinfo->channels_max = per_cvt->channels_max;
1451 hinfo->rates = per_cvt->rates;
1452 hinfo->formats = per_cvt->formats;
1453 hinfo->maxbps = per_cvt->maxbps;
2def8172 1454
384a48d7 1455 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 1456 if (!static_hdmi_pcm && eld->eld_valid) {
1613d6b4 1457 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
bbbe3390 1458 if (hinfo->channels_min > hinfo->channels_max ||
2ad779b7
TI		 1459 !hinfo->rates || !hinfo->formats) {
1460 per_cvt->assigned = 0;
1461 hinfo->nid = 0;
1462 snd_hda_spdif_ctls_unassign(codec, pin_idx);
bbbe3390 1463 return -ENODEV;
2ad779b7 1464 }
bbbe3390 1465 }
2def8172
SW		 1466
1467 /* Store the updated parameters */
639cef0e
TI		 1468 runtime->hw.channels_min = hinfo->channels_min;
1469 runtime->hw.channels_max = hinfo->channels_max;
1470 runtime->hw.formats = hinfo->formats;
1471 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 1472
1473 snd_pcm_hw_constraint_step(substream->runtime, 0,
1474 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
bbbe3390
TI		 1475 return 0;
1476}
1477
079d88cc
WF		 1478/*
1479 * HDA/HDMI auto parsing
1480 */
384a48d7 1481static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 1482{
1483 struct hdmi_spec *spec = codec->spec;
bce0d2a8 1484 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1485 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 1486
1487 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
4e76a883
TI		 1488 codec_warn(codec,
1489 "HDMI: pin %d wcaps %#x does not support connection list\n",
079d88cc
WF		 1490 pin_nid, get_wcaps(codec, pin_nid));
1491 return -EINVAL;
1492 }
1493
384a48d7
SW		 1494 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1495 per_pin->mux_nids,
1496 HDA_MAX_CONNECTIONS);
079d88cc
WF		 1497
1498 return 0;
1499}
1500
efe47108 1501static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
079d88cc 1502{
464837a7 1503 struct hda_jack_tbl *jack;
744626da 1504 struct hda_codec *codec = per_pin->codec;
4bd038f9
DH		 1505 struct hdmi_spec *spec = codec->spec;
1506 struct hdmi_eld *eld = &spec->temp_eld;
1507 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
744626da 1508 hda_nid_t pin_nid = per_pin->pin_nid;
5d44f927
SW		 1509 /*
1510 * Always execute a GetPinSense verb here, even when called from
1511 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1512 * response's PD bit is not the real PD value, but indicates that
1513 * the real PD value changed. An older version of the HD-audio
1514 * specification worked this way. Hence, we just ignore the data in
1515 * the unsolicited response to avoid custom WARs.
1516 */
da4a7a39 1517 int present;
4bd038f9
DH		 1518 bool update_eld = false;
1519 bool eld_changed = false;
efe47108 1520 bool ret;
079d88cc 1521
da4a7a39
DH		 1522 snd_hda_power_up(codec);
1523 present = snd_hda_pin_sense(codec, pin_nid);
1524
a4e9a38b 1525 mutex_lock(&per_pin->lock);
4bd038f9
DH		 1526 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1527 if (pin_eld->monitor_present)
1528 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1529 else
1530 eld->eld_valid = false;
079d88cc 1531
4e76a883 1532 codec_dbg(codec,
384a48d7 1533 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
10250911 1534 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
5d44f927 1535
4bd038f9 1536 if (eld->eld_valid) {
307229d2 1537 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1613d6b4 1538 &eld->eld_size) < 0)
4bd038f9 1539 eld->eld_valid = false;
1613d6b4
DH		 1540 else {
1541 memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
1542 if (snd_hdmi_parse_eld(&eld->info, eld->eld_buffer,
1543 eld->eld_size) < 0)
4bd038f9 1544 eld->eld_valid = false;
1613d6b4
DH		 1545 }
1546
4bd038f9 1547 if (eld->eld_valid) {
1613d6b4 1548 snd_hdmi_show_eld(&eld->info);
4bd038f9 1549 update_eld = true;
1613d6b4 1550 }
c6e8453e 1551 else if (repoll) {
744626da
WF		 1552 queue_delayed_work(codec->bus->workq,
1553 &per_pin->work,
1554 msecs_to_jiffies(300));
cbbaa603 1555 goto unlock;
744626da
WF		 1556 }
1557 }
4bd038f9 1558
92c69e79 1559 if (pin_eld->eld_valid && !eld->eld_valid) {
4bd038f9 1560 update_eld = true;
92c69e79
DH		 1561 eld_changed = true;
1562 }
4bd038f9 1563 if (update_eld) {
b054087d 1564 bool old_eld_valid = pin_eld->eld_valid;
4bd038f9 1565 pin_eld->eld_valid = eld->eld_valid;
92c69e79
DH		 1566 eld_changed = pin_eld->eld_size != eld->eld_size ||
1567 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
4bd038f9
DH		 1568 eld->eld_size) != 0;
1569 if (eld_changed)
1570 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1571 eld->eld_size);
1572 pin_eld->eld_size = eld->eld_size;
1573 pin_eld->info = eld->info;
b054087d 1574
7342017f
AH		 1575 /*
1576 * Re-setup pin and infoframe. This is needed e.g. when
1577 * - sink is first plugged-in (infoframe is not set up if !monitor_present)
1578 * - transcoder can change during stream playback on Haswell
b054087d 1579 */
7342017f 1580 if (eld->eld_valid && !old_eld_valid && per_pin->setup)
b054087d
TI		 1581 hdmi_setup_audio_infoframe(codec, per_pin,
1582 per_pin->non_pcm);
4bd038f9 1583 }
92c69e79
DH		 1584
1585 if (eld_changed)
1586 snd_ctl_notify(codec->bus->card,
1587 SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO,
1588 &per_pin->eld_ctl->id);
cbbaa603 1589 unlock:
aff747eb 1590 ret = !repoll || !pin_eld->monitor_present || pin_eld->eld_valid;
464837a7
DH		 1591
1592 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1593 if (jack)
1594 jack->block_report = !ret;
1595
a4e9a38b 1596 mutex_unlock(&per_pin->lock);
da4a7a39 1597 snd_hda_power_down(codec);
efe47108 1598 return ret;
079d88cc
WF		 1599}
1600
744626da
WF		 1601static void hdmi_repoll_eld(struct work_struct *work)
1602{
1603 struct hdmi_spec_per_pin *per_pin =
1604 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1605
c6e8453e
WF		 1606 if (per_pin->repoll_count++ > 6)
1607 per_pin->repoll_count = 0;
1608
efe47108
TI		 1609 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1610 snd_hda_jack_report_sync(per_pin->codec);
744626da
WF		 1611}
1612
c88d4e84
TI		 1613static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1614 hda_nid_t nid);
1615
079d88cc
WF		 1616static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1617{
1618 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1619 unsigned int caps, config;
1620 int pin_idx;
1621 struct hdmi_spec_per_pin *per_pin;
07acecc1 1622 int err;
079d88cc 1623
efc2f8de 1624 caps = snd_hda_query_pin_caps(codec, pin_nid);
384a48d7
SW		 1625 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1626 return 0;
1627
efc2f8de 1628 config = snd_hda_codec_get_pincfg(codec, pin_nid);
384a48d7
SW		 1629 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1630 return 0;
1631
75dcbe4d 1632 if (is_haswell_plus(codec))
c88d4e84
TI		 1633 intel_haswell_fixup_connect_list(codec, pin_nid);
1634
384a48d7 1635 pin_idx = spec->num_pins;
bce0d2a8
TI		 1636 per_pin = snd_array_new(&spec->pins);
1637 if (!per_pin)
1638 return -ENOMEM;
384a48d7
SW		 1639
1640 per_pin->pin_nid = pin_nid;
1a6003b5 1641 per_pin->non_pcm = false;
079d88cc 1642
384a48d7
SW		 1643 err = hdmi_read_pin_conn(codec, pin_idx);
1644 if (err < 0)
1645 return err;
079d88cc 1646
079d88cc
WF		 1647 spec->num_pins++;
1648
384a48d7 1649 return 0;
079d88cc
WF		 1650}
1651
384a48d7 1652static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 1653{
1654 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1655 struct hdmi_spec_per_cvt *per_cvt;
1656 unsigned int chans;
1657 int err;
079d88cc 1658
384a48d7
SW		 1659 chans = get_wcaps(codec, cvt_nid);
1660 chans = get_wcaps_channels(chans);
1661
bce0d2a8
TI		 1662 per_cvt = snd_array_new(&spec->cvts);
1663 if (!per_cvt)
1664 return -ENOMEM;
384a48d7
SW		 1665
1666 per_cvt->cvt_nid = cvt_nid;
1667 per_cvt->channels_min = 2;
d45e6889 1668 if (chans <= 16) {
384a48d7 1669 per_cvt->channels_max = chans;
d45e6889
TI		 1670 if (chans > spec->channels_max)
1671 spec->channels_max = chans;
1672 }
384a48d7
SW		 1673
1674 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1675 &per_cvt->rates,
1676 &per_cvt->formats,
1677 &per_cvt->maxbps);
1678 if (err < 0)
1679 return err;
1680
bce0d2a8
TI		 1681 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1682 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1683 spec->num_cvts++;
079d88cc
WF		 1684
1685 return 0;
1686}
1687
1688static int hdmi_parse_codec(struct hda_codec *codec)
1689{
1690 hda_nid_t nid;
1691 int i, nodes;
1692
1693 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
1694 if (!nid || nodes < 0) {
4e76a883 1695 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
079d88cc
WF		 1696 return -EINVAL;
1697 }
1698
1699 for (i = 0; i < nodes; i++, nid++) {
1700 unsigned int caps;
1701 unsigned int type;
1702
efc2f8de 1703 caps = get_wcaps(codec, nid);
079d88cc
WF		 1704 type = get_wcaps_type(caps);
1705
1706 if (!(caps & AC_WCAP_DIGITAL))
1707 continue;
1708
1709 switch (type) {
1710 case AC_WID_AUD_OUT:
384a48d7 1711 hdmi_add_cvt(codec, nid);
079d88cc
WF		 1712 break;
1713 case AC_WID_PIN:
3eaead57 1714 hdmi_add_pin(codec, nid);
079d88cc
WF		 1715 break;
1716 }
1717 }
1718
079d88cc
WF		 1719 return 0;
1720}
1721
84eb01be
TI		 1722/*
1723 */
1a6003b5
TI		 1724static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1725{
1726 struct hda_spdif_out *spdif;
1727 bool non_pcm;
1728
1729 mutex_lock(&codec->spdif_mutex);
1730 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1731 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1732 mutex_unlock(&codec->spdif_mutex);
1733 return non_pcm;
1734}
1735
1736
84eb01be
TI		 1737/*
1738 * HDMI callbacks
1739 */
1740
1741static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1742 struct hda_codec *codec,
1743 unsigned int stream_tag,
1744 unsigned int format,
1745 struct snd_pcm_substream *substream)
1746{
384a48d7
SW		 1747 hda_nid_t cvt_nid = hinfo->nid;
1748 struct hdmi_spec *spec = codec->spec;
4e76a883 1749 int pin_idx = hinfo_to_pin_index(codec, hinfo);
b054087d
TI		 1750 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1751 hda_nid_t pin_nid = per_pin->pin_nid;
1a6003b5 1752 bool non_pcm;
75fae117 1753 int pinctl;
1a6003b5
TI		 1754
1755 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
a4e9a38b 1756 mutex_lock(&per_pin->lock);
b054087d
TI		 1757 per_pin->channels = substream->runtime->channels;
1758 per_pin->setup = true;
384a48d7 1759
b054087d 1760 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
a4e9a38b 1761 mutex_unlock(&per_pin->lock);
84eb01be 1762
75fae117
SW		 1763 if (spec->dyn_pin_out) {
1764 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1765 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1766 snd_hda_codec_write(codec, pin_nid, 0,
1767 AC_VERB_SET_PIN_WIDGET_CONTROL,
1768 pinctl | PIN_OUT);
1769 }
1770
307229d2 1771 return spec->ops.setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
84eb01be
TI		 1772}
1773
8dfaa573
TI		 1774static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1775 struct hda_codec *codec,
1776 struct snd_pcm_substream *substream)
1777{
1778 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1779 return 0;
1780}
1781
f2ad24fa
TI		 1782static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1783 struct hda_codec *codec,
1784 struct snd_pcm_substream *substream)
384a48d7
SW		 1785{
1786 struct hdmi_spec *spec = codec->spec;
1787 int cvt_idx, pin_idx;
1788 struct hdmi_spec_per_cvt *per_cvt;
1789 struct hdmi_spec_per_pin *per_pin;
75fae117 1790 int pinctl;
384a48d7 1791
384a48d7 1792 if (hinfo->nid) {
4e76a883 1793 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
384a48d7
SW		 1794 if (snd_BUG_ON(cvt_idx < 0))
1795 return -EINVAL;
bce0d2a8 1796 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1797
1798 snd_BUG_ON(!per_cvt->assigned);
1799 per_cvt->assigned = 0;
1800 hinfo->nid = 0;
1801
4e76a883 1802 pin_idx = hinfo_to_pin_index(codec, hinfo);
384a48d7
SW		 1803 if (snd_BUG_ON(pin_idx < 0))
1804 return -EINVAL;
bce0d2a8 1805 per_pin = get_pin(spec, pin_idx);
384a48d7 1806
75fae117
SW		 1807 if (spec->dyn_pin_out) {
1808 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1809 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1810 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1811 AC_VERB_SET_PIN_WIDGET_CONTROL,
1812 pinctl & ~PIN_OUT);
1813 }
1814
384a48d7 1815 snd_hda_spdif_ctls_unassign(codec, pin_idx);
cbbaa603 1816
a4e9a38b 1817 mutex_lock(&per_pin->lock);
d45e6889
TI		 1818 per_pin->chmap_set = false;
1819 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
b054087d
TI		 1820
1821 per_pin->setup = false;
1822 per_pin->channels = 0;
a4e9a38b 1823 mutex_unlock(&per_pin->lock);
384a48d7 1824 }
d45e6889 1825
384a48d7
SW		 1826 return 0;
1827}
1828
1829static const struct hda_pcm_ops generic_ops = {
1830 .open = hdmi_pcm_open,
f2ad24fa 1831 .close = hdmi_pcm_close,
384a48d7 1832 .prepare = generic_hdmi_playback_pcm_prepare,
8dfaa573 1833 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 1834};
1835
d45e6889
TI		 1836/*
1837 * ALSA API channel-map control callbacks
1838 */
1839static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1840 struct snd_ctl_elem_info *uinfo)
1841{
1842 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1843 struct hda_codec *codec = info->private_data;
1844 struct hdmi_spec *spec = codec->spec;
1845 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1846 uinfo->count = spec->channels_max;
1847 uinfo->value.integer.min = 0;
1848 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1849 return 0;
1850}
1851
307229d2
AH		 1852static int hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
1853 int channels)
1854{
1855 /* If the speaker allocation matches the channel count, it is OK.*/
1856 if (cap->channels != channels)
1857 return -1;
1858
1859 /* all channels are remappable freely */
1860 return SNDRV_CTL_TLVT_CHMAP_VAR;
1861}
1862
1863static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
1864 unsigned int *chmap, int channels)
1865{
1866 int count = 0;
1867 int c;
1868
1869 for (c = 7; c >= 0; c--) {
1870 int spk = cap->speakers[c];
1871 if (!spk)
1872 continue;
1873
1874 chmap[count++] = spk_to_chmap(spk);
1875 }
1876
1877 WARN_ON(count != channels);
1878}
1879
d45e6889
TI		 1880static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
1881 unsigned int size, unsigned int __user *tlv)
1882{
1883 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1884 struct hda_codec *codec = info->private_data;
1885 struct hdmi_spec *spec = codec->spec;
d45e6889
TI		 1886 unsigned int __user *dst;
1887 int chs, count = 0;
1888
1889 if (size < 8)
1890 return -ENOMEM;
1891 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
1892 return -EFAULT;
1893 size -= 8;
1894 dst = tlv + 2;
498dab3a 1895 for (chs = 2; chs <= spec->channels_max; chs++) {
307229d2 1896 int i;
d45e6889
TI		 1897 struct cea_channel_speaker_allocation *cap;
1898 cap = channel_allocations;
1899 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
1900 int chs_bytes = chs * 4;
307229d2
AH		 1901 int type = spec->ops.chmap_cea_alloc_validate_get_type(cap, chs);
1902 unsigned int tlv_chmap[8];
1903
1904 if (type < 0)
d45e6889 1905 continue;
d45e6889
TI		 1906 if (size < 8)
1907 return -ENOMEM;
307229d2 1908 if (put_user(type, dst) ||
d45e6889
TI		 1909 put_user(chs_bytes, dst + 1))
1910 return -EFAULT;
1911 dst += 2;
1912 size -= 8;
1913 count += 8;
1914 if (size < chs_bytes)
1915 return -ENOMEM;
1916 size -= chs_bytes;
1917 count += chs_bytes;
307229d2
AH		 1918 spec->ops.cea_alloc_to_tlv_chmap(cap, tlv_chmap, chs);
1919 if (copy_to_user(dst, tlv_chmap, chs_bytes))
1920 return -EFAULT;
1921 dst += chs;
d45e6889
TI		 1922 }
1923 }
1924 if (put_user(count, tlv + 1))
1925 return -EFAULT;
1926 return 0;
1927}
1928
1929static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
1930 struct snd_ctl_elem_value *ucontrol)
1931{
1932 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1933 struct hda_codec *codec = info->private_data;
1934 struct hdmi_spec *spec = codec->spec;
1935 int pin_idx = kcontrol->private_value;
bce0d2a8 1936 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 1937 int i;
1938
1939 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
1940 ucontrol->value.integer.value[i] = per_pin->chmap[i];
1941 return 0;
1942}
1943
1944static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
1945 struct snd_ctl_elem_value *ucontrol)
1946{
1947 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1948 struct hda_codec *codec = info->private_data;
1949 struct hdmi_spec *spec = codec->spec;
1950 int pin_idx = kcontrol->private_value;
bce0d2a8 1951 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 1952 unsigned int ctl_idx;
1953 struct snd_pcm_substream *substream;
1954 unsigned char chmap[8];
307229d2 1955 int i, err, ca, prepared = 0;
d45e6889
TI		 1956
1957 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
1958 substream = snd_pcm_chmap_substream(info, ctl_idx);
1959 if (!substream || !substream->runtime)
6f54c361 1960 return 0; /* just for avoiding error from alsactl restore */
d45e6889
TI		 1961 switch (substream->runtime->status->state) {
1962 case SNDRV_PCM_STATE_OPEN:
1963 case SNDRV_PCM_STATE_SETUP:
1964 break;
1965 case SNDRV_PCM_STATE_PREPARED:
1966 prepared = 1;
1967 break;
1968 default:
1969 return -EBUSY;
1970 }
1971 memset(chmap, 0, sizeof(chmap));
1972 for (i = 0; i < ARRAY_SIZE(chmap); i++)
1973 chmap[i] = ucontrol->value.integer.value[i];
1974 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
1975 return 0;
1976 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
1977 if (ca < 0)
1978 return -EINVAL;
307229d2
AH		 1979 if (spec->ops.chmap_validate) {
1980 err = spec->ops.chmap_validate(ca, ARRAY_SIZE(chmap), chmap);
1981 if (err)
1982 return err;
1983 }
a4e9a38b 1984 mutex_lock(&per_pin->lock);
d45e6889
TI		 1985 per_pin->chmap_set = true;
1986 memcpy(per_pin->chmap, chmap, sizeof(chmap));
1987 if (prepared)
b054087d 1988 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
a4e9a38b 1989 mutex_unlock(&per_pin->lock);
d45e6889
TI		 1990
1991 return 0;
1992}
1993
84eb01be
TI		 1994static int generic_hdmi_build_pcms(struct hda_codec *codec)
1995{
1996 struct hdmi_spec *spec = codec->spec;
384a48d7 1997 int pin_idx;
84eb01be 1998
384a48d7
SW		 1999 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2000 struct hda_pcm *info;
84eb01be 2001 struct hda_pcm_stream *pstr;
bce0d2a8
TI		 2002 struct hdmi_spec_per_pin *per_pin;
2003
2004 per_pin = get_pin(spec, pin_idx);
2005 sprintf(per_pin->pcm_name, "HDMI %d", pin_idx);
2006 info = snd_array_new(&spec->pcm_rec);
2007 if (!info)
2008 return -ENOMEM;
2009 info->name = per_pin->pcm_name;
84eb01be 2010 info->pcm_type = HDA_PCM_TYPE_HDMI;
d45e6889 2011 info->own_chmap = true;
384a48d7 2012
84eb01be 2013 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 2014 pstr->substreams = 1;
2015 pstr->ops = generic_ops;
2016 /* other pstr fields are set in open */
84eb01be
TI		 2017 }
2018
384a48d7 2019 codec->num_pcms = spec->num_pins;
bce0d2a8 2020 codec->pcm_info = spec->pcm_rec.list;
384a48d7 2021
84eb01be
TI		 2022 return 0;
2023}
2024
0b6c49b5
DH		 2025static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
2026{
31ef2257 2027 char hdmi_str[32] = "HDMI/DP";
0b6c49b5 2028 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 2029 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2030 int pcmdev = get_pcm_rec(spec, pin_idx)->device;
0b6c49b5 2031
31ef2257
TI		 2032 if (pcmdev > 0)
2033 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
30efd8de
DH		 2034 if (!is_jack_detectable(codec, per_pin->pin_nid))
2035 strncat(hdmi_str, " Phantom",
2036 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
0b6c49b5 2037
31ef2257 2038 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 0);
0b6c49b5
DH		 2039}
2040
84eb01be
TI		 2041static int generic_hdmi_build_controls(struct hda_codec *codec)
2042{
2043 struct hdmi_spec *spec = codec->spec;
2044 int err;
384a48d7 2045 int pin_idx;
84eb01be 2046
384a48d7 2047 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2048 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
0b6c49b5
DH		 2049
2050 err = generic_hdmi_build_jack(codec, pin_idx);
2051 if (err < 0)
2052 return err;
2053
dcda5806
TI		 2054 err = snd_hda_create_dig_out_ctls(codec,
2055 per_pin->pin_nid,
2056 per_pin->mux_nids[0],
2057 HDA_PCM_TYPE_HDMI);
84eb01be
TI		 2058 if (err < 0)
2059 return err;
384a48d7 2060 snd_hda_spdif_ctls_unassign(codec, pin_idx);
14bc52b8
PLB		 2061
2062 /* add control for ELD Bytes */
bce0d2a8
TI		 2063 err = hdmi_create_eld_ctl(codec, pin_idx,
2064 get_pcm_rec(spec, pin_idx)->device);
14bc52b8
PLB		 2065
2066 if (err < 0)
2067 return err;
31ef2257 2068
82b1d73f 2069 hdmi_present_sense(per_pin, 0);
84eb01be
TI		 2070 }
2071
d45e6889
TI		 2072 /* add channel maps */
2073 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2074 struct snd_pcm_chmap *chmap;
2075 struct snd_kcontrol *kctl;
2076 int i;
2ca320e2
TI		 2077
2078 if (!codec->pcm_info[pin_idx].pcm)
2079 break;
d45e6889
TI		 2080 err = snd_pcm_add_chmap_ctls(codec->pcm_info[pin_idx].pcm,
2081 SNDRV_PCM_STREAM_PLAYBACK,
2082 NULL, 0, pin_idx, &chmap);
2083 if (err < 0)
2084 return err;
2085 /* override handlers */
2086 chmap->private_data = codec;
2087 kctl = chmap->kctl;
2088 for (i = 0; i < kctl->count; i++)
2089 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
2090 kctl->info = hdmi_chmap_ctl_info;
2091 kctl->get = hdmi_chmap_ctl_get;
2092 kctl->put = hdmi_chmap_ctl_put;
2093 kctl->tlv.c = hdmi_chmap_ctl_tlv;
2094 }
2095
84eb01be
TI		 2096 return 0;
2097}
2098
8b8d654b 2099static int generic_hdmi_init_per_pins(struct hda_codec *codec)
84eb01be
TI		 2100{
2101 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2102 int pin_idx;
2103
2104 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2105 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
84eb01be 2106
744626da 2107 per_pin->codec = codec;
a4e9a38b 2108 mutex_init(&per_pin->lock);
744626da 2109 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
a4e9a38b 2110 eld_proc_new(per_pin, pin_idx);
84eb01be 2111 }
8b8d654b
TI		 2112 return 0;
2113}
2114
2115static int generic_hdmi_init(struct hda_codec *codec)
2116{
2117 struct hdmi_spec *spec = codec->spec;
2118 int pin_idx;
2119
2120 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2121 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
8b8d654b
TI		 2122 hda_nid_t pin_nid = per_pin->pin_nid;
2123
2124 hdmi_init_pin(codec, pin_nid);
20ce9029
DH		 2125 snd_hda_jack_detect_enable_callback(codec, pin_nid, pin_nid,
2126 codec->jackpoll_interval > 0 ? jack_callback : NULL);
8b8d654b 2127 }
84eb01be
TI		 2128 return 0;
2129}
2130
bce0d2a8
TI		 2131static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2132{
2133 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2134 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2135 snd_array_init(&spec->pcm_rec, sizeof(struct hda_pcm), nums);
2136}
2137
2138static void hdmi_array_free(struct hdmi_spec *spec)
2139{
2140 snd_array_free(&spec->pins);
2141 snd_array_free(&spec->cvts);
2142 snd_array_free(&spec->pcm_rec);
2143}
2144
84eb01be
TI		 2145static void generic_hdmi_free(struct hda_codec *codec)
2146{
2147 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2148 int pin_idx;
2149
2150 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2151 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
84eb01be 2152
744626da 2153 cancel_delayed_work(&per_pin->work);
a4e9a38b 2154 eld_proc_free(per_pin);
384a48d7 2155 }
84eb01be 2156
744626da 2157 flush_workqueue(codec->bus->workq);
bce0d2a8 2158 hdmi_array_free(spec);
84eb01be
TI		 2159 kfree(spec);
2160}
2161
28cb72e5
WX		 2162#ifdef CONFIG_PM
2163static int generic_hdmi_resume(struct hda_codec *codec)
2164{
2165 struct hdmi_spec *spec = codec->spec;
2166 int pin_idx;
2167
2168 generic_hdmi_init(codec);
2169 snd_hda_codec_resume_amp(codec);
2170 snd_hda_codec_resume_cache(codec);
2171
2172 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2173 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2174 hdmi_present_sense(per_pin, 1);
2175 }
2176 return 0;
2177}
2178#endif
2179
fb79e1e0 2180static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 2181 .init = generic_hdmi_init,
2182 .free = generic_hdmi_free,
2183 .build_pcms = generic_hdmi_build_pcms,
2184 .build_controls = generic_hdmi_build_controls,
2185 .unsol_event = hdmi_unsol_event,
28cb72e5
WX		 2186#ifdef CONFIG_PM
2187 .resume = generic_hdmi_resume,
2188#endif
84eb01be
TI		 2189};
2190
307229d2
AH		 2191static const struct hdmi_ops generic_standard_hdmi_ops = {
2192 .pin_get_eld = snd_hdmi_get_eld,
2193 .pin_get_slot_channel = hdmi_pin_get_slot_channel,
2194 .pin_set_slot_channel = hdmi_pin_set_slot_channel,
2195 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2196 .pin_hbr_setup = hdmi_pin_hbr_setup,
2197 .setup_stream = hdmi_setup_stream,
2198 .chmap_cea_alloc_validate_get_type = hdmi_chmap_cea_alloc_validate_get_type,
2199 .cea_alloc_to_tlv_chmap = hdmi_cea_alloc_to_tlv_chmap,
2200};
2201
6ffe168f 2202
c88d4e84
TI		 2203static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2204 hda_nid_t nid)
2205{
2206 struct hdmi_spec *spec = codec->spec;
2207 hda_nid_t conns[4];
2208 int nconns;
6ffe168f 2209
c88d4e84
TI		 2210 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2211 if (nconns == spec->num_cvts &&
2212 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
6ffe168f
ML		 2213 return;
2214
c88d4e84 2215 /* override pins connection list */
4e76a883 2216 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
c88d4e84 2217 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
6ffe168f
ML		 2218}
2219
1611a9c9
ML		 2220#define INTEL_VENDOR_NID 0x08
2221#define INTEL_GET_VENDOR_VERB 0xf81
2222#define INTEL_SET_VENDOR_VERB 0x781
2223#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2224#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2225
2226static void intel_haswell_enable_all_pins(struct hda_codec *codec,
17df3f55 2227 bool update_tree)
1611a9c9
ML		 2228{
2229 unsigned int vendor_param;
2230
1611a9c9
ML		 2231 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2232 INTEL_GET_VENDOR_VERB, 0);
2233 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2234 return;
2235
2236 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2237 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2238 INTEL_SET_VENDOR_VERB, vendor_param);
2239 if (vendor_param == -1)
2240 return;
2241
17df3f55
TI		 2242 if (update_tree)
2243 snd_hda_codec_update_widgets(codec);
1611a9c9
ML		 2244}
2245
c88d4e84
TI		 2246static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2247{
2248 unsigned int vendor_param;
2249
2250 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2251 INTEL_GET_VENDOR_VERB, 0);
2252 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2253 return;
2254
2255 /* enable DP1.2 mode */
2256 vendor_param |= INTEL_EN_DP12;
2257 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2258 INTEL_SET_VENDOR_VERB, vendor_param);
2259}
2260
17df3f55
TI		 2261/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2262 * Otherwise you may get severe h/w communication errors.
2263 */
2264static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2265 unsigned int power_state)
2266{
2267 if (power_state == AC_PWRST_D0) {
2268 intel_haswell_enable_all_pins(codec, false);
2269 intel_haswell_fixup_enable_dp12(codec);
2270 }
c88d4e84 2271
17df3f55
TI		 2272 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2273 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2274}
6ffe168f 2275
84eb01be
TI		 2276static int patch_generic_hdmi(struct hda_codec *codec)
2277{
2278 struct hdmi_spec *spec;
84eb01be
TI		 2279
2280 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2281 if (spec == NULL)
2282 return -ENOMEM;
2283
307229d2 2284 spec->ops = generic_standard_hdmi_ops;
84eb01be 2285 codec->spec = spec;
bce0d2a8 2286 hdmi_array_init(spec, 4);
6ffe168f 2287
75dcbe4d 2288 if (is_haswell_plus(codec)) {
17df3f55 2289 intel_haswell_enable_all_pins(codec, true);
c88d4e84 2290 intel_haswell_fixup_enable_dp12(codec);
17df3f55 2291 }
6ffe168f 2292
5b8620bb
ML		 2293 if (is_haswell(codec) || is_valleyview(codec)) {
2294 codec->depop_delay = 0;
2295 }
2296
84eb01be
TI		 2297 if (hdmi_parse_codec(codec) < 0) {
2298 codec->spec = NULL;
2299 kfree(spec);
2300 return -EINVAL;
2301 }
2302 codec->patch_ops = generic_hdmi_patch_ops;
75dcbe4d 2303 if (is_haswell_plus(codec)) {
17df3f55 2304 codec->patch_ops.set_power_state = haswell_set_power_state;
5dc989bd
ML		 2305 codec->dp_mst = true;
2306 }
17df3f55 2307
8b8d654b 2308 generic_hdmi_init_per_pins(codec);
84eb01be 2309
84eb01be
TI		 2310 init_channel_allocations();
2311
2312 return 0;
2313}
2314
3aaf8980
SW		 2315/*
2316 * Shared non-generic implementations
2317 */
2318
2319static int simple_playback_build_pcms(struct hda_codec *codec)
2320{
2321 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2322 struct hda_pcm *info;
8ceb332d
TI		 2323 unsigned int chans;
2324 struct hda_pcm_stream *pstr;
bce0d2a8 2325 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2326
bce0d2a8
TI		 2327 per_cvt = get_cvt(spec, 0);
2328 chans = get_wcaps(codec, per_cvt->cvt_nid);
8ceb332d 2329 chans = get_wcaps_channels(chans);
3aaf8980 2330
bce0d2a8
TI		 2331 info = snd_array_new(&spec->pcm_rec);
2332 if (!info)
2333 return -ENOMEM;
2334 info->name = get_pin(spec, 0)->pcm_name;
2335 sprintf(info->name, "HDMI 0");
8ceb332d
TI		 2336 info->pcm_type = HDA_PCM_TYPE_HDMI;
2337 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2338 *pstr = spec->pcm_playback;
bce0d2a8 2339 pstr->nid = per_cvt->cvt_nid;
8ceb332d
TI		 2340 if (pstr->channels_max <= 2 && chans && chans <= 16)
2341 pstr->channels_max = chans;
3aaf8980 2342
bce0d2a8
TI		 2343 codec->num_pcms = 1;
2344 codec->pcm_info = info;
2345
3aaf8980
SW		 2346 return 0;
2347}
2348
4b6ace9e
TI		 2349/* unsolicited event for jack sensing */
2350static void simple_hdmi_unsol_event(struct hda_codec *codec,
2351 unsigned int res)
2352{
9dd8cf12 2353 snd_hda_jack_set_dirty_all(codec);
4b6ace9e
TI		 2354 snd_hda_jack_report_sync(codec);
2355}
2356
2357/* generic_hdmi_build_jack can be used for simple_hdmi, too,
2358 * as long as spec->pins[] is set correctly
2359 */
2360#define simple_hdmi_build_jack generic_hdmi_build_jack
2361
3aaf8980
SW		 2362static int simple_playback_build_controls(struct hda_codec *codec)
2363{
2364 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2365 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2366 int err;
3aaf8980 2367
bce0d2a8 2368 per_cvt = get_cvt(spec, 0);
c9a6338a
AH		 2369 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2370 per_cvt->cvt_nid,
2371 HDA_PCM_TYPE_HDMI);
8ceb332d
TI		 2372 if (err < 0)
2373 return err;
2374 return simple_hdmi_build_jack(codec, 0);
3aaf8980
SW		 2375}
2376
4f0110ce
TI		 2377static int simple_playback_init(struct hda_codec *codec)
2378{
2379 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 2380 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2381 hda_nid_t pin = per_pin->pin_nid;
8ceb332d
TI		 2382
2383 snd_hda_codec_write(codec, pin, 0,
2384 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2385 /* some codecs require to unmute the pin */
2386 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2387 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2388 AMP_OUT_UNMUTE);
2389 snd_hda_jack_detect_enable(codec, pin, pin);
4f0110ce
TI		 2390 return 0;
2391}
2392
3aaf8980
SW		 2393static void simple_playback_free(struct hda_codec *codec)
2394{
2395 struct hdmi_spec *spec = codec->spec;
2396
bce0d2a8 2397 hdmi_array_free(spec);
3aaf8980
SW		 2398 kfree(spec);
2399}
2400
84eb01be
TI		 2401/*
2402 * Nvidia specific implementations
2403 */
2404
2405#define Nv_VERB_SET_Channel_Allocation 0xF79
2406#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2407#define Nv_VERB_SET_Audio_Protection_On 0xF98
2408#define Nv_VERB_SET_Audio_Protection_Off 0xF99
2409
2410#define nvhdmi_master_con_nid_7x 0x04
2411#define nvhdmi_master_pin_nid_7x 0x05
2412
fb79e1e0 2413static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 2414 /*front, rear, clfe, rear_surr */
2415 0x6, 0x8, 0xa, 0xc,
2416};
2417
ceaa86ba
TI		 2418static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2419 /* set audio protect on */
2420 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2421 /* enable digital output on pin widget */
2422 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2423 {} /* terminator */
2424};
2425
2426static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
84eb01be
TI		 2427 /* set audio protect on */
2428 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2429 /* enable digital output on pin widget */
2430 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2431 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2432 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2433 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2434 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2435 {} /* terminator */
2436};
2437
2438#ifdef LIMITED_RATE_FMT_SUPPORT
2439/* support only the safe format and rate */
2440#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2441#define SUPPORTED_MAXBPS 16
2442#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2443#else
2444/* support all rates and formats */
2445#define SUPPORTED_RATES \
2446 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2447 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2448 SNDRV_PCM_RATE_192000)
2449#define SUPPORTED_MAXBPS 24
2450#define SUPPORTED_FORMATS \
2451 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2452#endif
2453
ceaa86ba
TI		 2454static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2455{
2456 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2457 return 0;
2458}
2459
2460static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
84eb01be 2461{
ceaa86ba 2462 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
84eb01be
TI		 2463 return 0;
2464}
2465
393004b2
ND		 2466static unsigned int channels_2_6_8[] = {
2467 2, 6, 8
2468};
2469
2470static unsigned int channels_2_8[] = {
2471 2, 8
2472};
2473
2474static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2475 .count = ARRAY_SIZE(channels_2_6_8),
2476 .list = channels_2_6_8,
2477 .mask = 0,
2478};
2479
2480static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2481 .count = ARRAY_SIZE(channels_2_8),
2482 .list = channels_2_8,
2483 .mask = 0,
2484};
2485
84eb01be
TI		 2486static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2487 struct hda_codec *codec,
2488 struct snd_pcm_substream *substream)
2489{
2490 struct hdmi_spec *spec = codec->spec;
393004b2
ND		 2491 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2492
2493 switch (codec->preset->id) {
2494 case 0x10de0002:
2495 case 0x10de0003:
2496 case 0x10de0005:
2497 case 0x10de0006:
2498 hw_constraints_channels = &hw_constraints_2_8_channels;
2499 break;
2500 case 0x10de0007:
2501 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2502 break;
2503 default:
2504 break;
2505 }
2506
2507 if (hw_constraints_channels != NULL) {
2508 snd_pcm_hw_constraint_list(substream->runtime, 0,
2509 SNDRV_PCM_HW_PARAM_CHANNELS,
2510 hw_constraints_channels);
ad09fc9d
TI		 2511 } else {
2512 snd_pcm_hw_constraint_step(substream->runtime, 0,
2513 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 2514 }
2515
84eb01be
TI		 2516 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2517}
2518
2519static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2520 struct hda_codec *codec,
2521 struct snd_pcm_substream *substream)
2522{
2523 struct hdmi_spec *spec = codec->spec;
2524 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2525}
2526
2527static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2528 struct hda_codec *codec,
2529 unsigned int stream_tag,
2530 unsigned int format,
2531 struct snd_pcm_substream *substream)
2532{
2533 struct hdmi_spec *spec = codec->spec;
2534 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2535 stream_tag, format, substream);
2536}
2537
d0b1252d
TI		 2538static const struct hda_pcm_stream simple_pcm_playback = {
2539 .substreams = 1,
2540 .channels_min = 2,
2541 .channels_max = 2,
2542 .ops = {
2543 .open = simple_playback_pcm_open,
2544 .close = simple_playback_pcm_close,
2545 .prepare = simple_playback_pcm_prepare
2546 },
2547};
2548
2549static const struct hda_codec_ops simple_hdmi_patch_ops = {
2550 .build_controls = simple_playback_build_controls,
2551 .build_pcms = simple_playback_build_pcms,
2552 .init = simple_playback_init,
2553 .free = simple_playback_free,
250e41ac 2554 .unsol_event = simple_hdmi_unsol_event,
d0b1252d
TI		 2555};
2556
2557static int patch_simple_hdmi(struct hda_codec *codec,
2558 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2559{
2560 struct hdmi_spec *spec;
bce0d2a8
TI		 2561 struct hdmi_spec_per_cvt *per_cvt;
2562 struct hdmi_spec_per_pin *per_pin;
d0b1252d
TI		 2563
2564 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2565 if (!spec)
2566 return -ENOMEM;
2567
2568 codec->spec = spec;
bce0d2a8 2569 hdmi_array_init(spec, 1);
d0b1252d
TI		 2570
2571 spec->multiout.num_dacs = 0; /* no analog */
2572 spec->multiout.max_channels = 2;
2573 spec->multiout.dig_out_nid = cvt_nid;
2574 spec->num_cvts = 1;
2575 spec->num_pins = 1;
bce0d2a8
TI		 2576 per_pin = snd_array_new(&spec->pins);
2577 per_cvt = snd_array_new(&spec->cvts);
2578 if (!per_pin || !per_cvt) {
2579 simple_playback_free(codec);
2580 return -ENOMEM;
2581 }
2582 per_cvt->cvt_nid = cvt_nid;
2583 per_pin->pin_nid = pin_nid;
d0b1252d
TI		 2584 spec->pcm_playback = simple_pcm_playback;
2585
2586 codec->patch_ops = simple_hdmi_patch_ops;
2587
2588 return 0;
2589}
2590
1f348522
AP		 2591static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2592 int channels)
2593{
2594 unsigned int chanmask;
2595 int chan = channels ? (channels - 1) : 1;
2596
2597 switch (channels) {
2598 default:
2599 case 0:
2600 case 2:
2601 chanmask = 0x00;
2602 break;
2603 case 4:
2604 chanmask = 0x08;
2605 break;
2606 case 6:
2607 chanmask = 0x0b;
2608 break;
2609 case 8:
2610 chanmask = 0x13;
2611 break;
2612 }
2613
2614 /* Set the audio infoframe channel allocation and checksum fields. The
2615 * channel count is computed implicitly by the hardware. */
2616 snd_hda_codec_write(codec, 0x1, 0,
2617 Nv_VERB_SET_Channel_Allocation, chanmask);
2618
2619 snd_hda_codec_write(codec, 0x1, 0,
2620 Nv_VERB_SET_Info_Frame_Checksum,
2621 (0x71 - chan - chanmask));
2622}
2623
84eb01be
TI		 2624static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2625 struct hda_codec *codec,
2626 struct snd_pcm_substream *substream)
2627{
2628 struct hdmi_spec *spec = codec->spec;
2629 int i;
2630
2631 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2632 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2633 for (i = 0; i < 4; i++) {
2634 /* set the stream id */
2635 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2636 AC_VERB_SET_CHANNEL_STREAMID, 0);
2637 /* set the stream format */
2638 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2639 AC_VERB_SET_STREAM_FORMAT, 0);
2640 }
2641
1f348522
AP		 2642 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2643 * streams are disabled. */
2644 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2645
84eb01be
TI		 2646 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2647}
2648
2649static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2650 struct hda_codec *codec,
2651 unsigned int stream_tag,
2652 unsigned int format,
2653 struct snd_pcm_substream *substream)
2654{
2655 int chs;
112daa7a 2656 unsigned int dataDCC2, channel_id;
84eb01be 2657 int i;
7c935976 2658 struct hdmi_spec *spec = codec->spec;
e3245cdd 2659 struct hda_spdif_out *spdif;
bce0d2a8 2660 struct hdmi_spec_per_cvt *per_cvt;
84eb01be
TI		 2661
2662 mutex_lock(&codec->spdif_mutex);
bce0d2a8
TI		 2663 per_cvt = get_cvt(spec, 0);
2664 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
84eb01be
TI		 2665
2666 chs = substream->runtime->channels;
84eb01be 2667
84eb01be
TI		 2668 dataDCC2 = 0x2;
2669
84eb01be 2670 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 2671 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2672 snd_hda_codec_write(codec,
2673 nvhdmi_master_con_nid_7x,
2674 0,
2675 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2676 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2677
2678 /* set the stream id */
2679 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2680 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2681
2682 /* set the stream format */
2683 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2684 AC_VERB_SET_STREAM_FORMAT, format);
2685
2686 /* turn on again (if needed) */
2687 /* enable and set the channel status audio/data flag */
7c935976 2688 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2689 snd_hda_codec_write(codec,
2690 nvhdmi_master_con_nid_7x,
2691 0,
2692 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2693 spdif->ctls & 0xff);
84eb01be
TI		 2694 snd_hda_codec_write(codec,
2695 nvhdmi_master_con_nid_7x,
2696 0,
2697 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2698 }
2699
2700 for (i = 0; i < 4; i++) {
2701 if (chs == 2)
2702 channel_id = 0;
2703 else
2704 channel_id = i * 2;
2705
2706 /* turn off SPDIF once;
2707 *otherwise the IEC958 bits won't be updated
2708 */
2709 if (codec->spdif_status_reset &&
7c935976 2710 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2711 snd_hda_codec_write(codec,
2712 nvhdmi_con_nids_7x[i],
2713 0,
2714 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2715 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2716 /* set the stream id */
2717 snd_hda_codec_write(codec,
2718 nvhdmi_con_nids_7x[i],
2719 0,
2720 AC_VERB_SET_CHANNEL_STREAMID,
2721 (stream_tag << 4) | channel_id);
2722 /* set the stream format */
2723 snd_hda_codec_write(codec,
2724 nvhdmi_con_nids_7x[i],
2725 0,
2726 AC_VERB_SET_STREAM_FORMAT,
2727 format);
2728 /* turn on again (if needed) */
2729 /* enable and set the channel status audio/data flag */
2730 if (codec->spdif_status_reset &&
7c935976 2731 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2732 snd_hda_codec_write(codec,
2733 nvhdmi_con_nids_7x[i],
2734 0,
2735 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2736 spdif->ctls & 0xff);
84eb01be
TI		 2737 snd_hda_codec_write(codec,
2738 nvhdmi_con_nids_7x[i],
2739 0,
2740 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2741 }
2742 }
2743
1f348522 2744 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 2745
2746 mutex_unlock(&codec->spdif_mutex);
2747 return 0;
2748}
2749
fb79e1e0 2750static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 2751 .substreams = 1,
2752 .channels_min = 2,
2753 .channels_max = 8,
2754 .nid = nvhdmi_master_con_nid_7x,
2755 .rates = SUPPORTED_RATES,
2756 .maxbps = SUPPORTED_MAXBPS,
2757 .formats = SUPPORTED_FORMATS,
2758 .ops = {
2759 .open = simple_playback_pcm_open,
2760 .close = nvhdmi_8ch_7x_pcm_close,
2761 .prepare = nvhdmi_8ch_7x_pcm_prepare
2762 },
2763};
2764
84eb01be
TI		 2765static int patch_nvhdmi_2ch(struct hda_codec *codec)
2766{
2767 struct hdmi_spec *spec;
d0b1252d
TI		 2768 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2769 nvhdmi_master_pin_nid_7x);
2770 if (err < 0)
2771 return err;
84eb01be 2772
ceaa86ba 2773 codec->patch_ops.init = nvhdmi_7x_init_2ch;
d0b1252d
TI		 2774 /* override the PCM rates, etc, as the codec doesn't give full list */
2775 spec = codec->spec;
2776 spec->pcm_playback.rates = SUPPORTED_RATES;
2777 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2778 spec->pcm_playback.formats = SUPPORTED_FORMATS;
84eb01be
TI		 2779 return 0;
2780}
2781
53775b0d
TI		 2782static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2783{
2784 struct hdmi_spec *spec = codec->spec;
2785 int err = simple_playback_build_pcms(codec);
bce0d2a8
TI		 2786 if (!err) {
2787 struct hda_pcm *info = get_pcm_rec(spec, 0);
2788 info->own_chmap = true;
2789 }
53775b0d
TI		 2790 return err;
2791}
2792
2793static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2794{
2795 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2796 struct hda_pcm *info;
53775b0d
TI		 2797 struct snd_pcm_chmap *chmap;
2798 int err;
2799
2800 err = simple_playback_build_controls(codec);
2801 if (err < 0)
2802 return err;
2803
2804 /* add channel maps */
bce0d2a8
TI		 2805 info = get_pcm_rec(spec, 0);
2806 err = snd_pcm_add_chmap_ctls(info->pcm,
53775b0d
TI		 2807 SNDRV_PCM_STREAM_PLAYBACK,
2808 snd_pcm_alt_chmaps, 8, 0, &chmap);
2809 if (err < 0)
2810 return err;
2811 switch (codec->preset->id) {
2812 case 0x10de0002:
2813 case 0x10de0003:
2814 case 0x10de0005:
2815 case 0x10de0006:
2816 chmap->channel_mask = (1U << 2) | (1U << 8);
2817 break;
2818 case 0x10de0007:
2819 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2820 }
2821 return 0;
2822}
2823
84eb01be
TI		 2824static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2825{
2826 struct hdmi_spec *spec;
2827 int err = patch_nvhdmi_2ch(codec);
84eb01be
TI		 2828 if (err < 0)
2829 return err;
2830 spec = codec->spec;
2831 spec->multiout.max_channels = 8;
d0b1252d 2832 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
ceaa86ba 2833 codec->patch_ops.init = nvhdmi_7x_init_8ch;
53775b0d
TI		 2834 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2835 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
1f348522
AP		 2836
2837 /* Initialize the audio infoframe channel mask and checksum to something
2838 * valid */
2839 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2840
84eb01be
TI		 2841 return 0;
2842}
2843
611885bc
AH		 2844/*
2845 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
2846 * - 0x10de0015
2847 * - 0x10de0040
2848 */
2849static int nvhdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
2850 int channels)
2851{
2852 if (cap->ca_index == 0x00 && channels == 2)
2853 return SNDRV_CTL_TLVT_CHMAP_FIXED;
2854
2855 return hdmi_chmap_cea_alloc_validate_get_type(cap, channels);
2856}
2857
2858static int nvhdmi_chmap_validate(int ca, int chs, unsigned char *map)
2859{
2860 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
2861 return -EINVAL;
2862
2863 return 0;
2864}
2865
2866static int patch_nvhdmi(struct hda_codec *codec)
2867{
2868 struct hdmi_spec *spec;
2869 int err;
2870
2871 err = patch_generic_hdmi(codec);
2872 if (err)
2873 return err;
2874
2875 spec = codec->spec;
75fae117 2876 spec->dyn_pin_out = true;
611885bc
AH		 2877
2878 spec->ops.chmap_cea_alloc_validate_get_type =
2879 nvhdmi_chmap_cea_alloc_validate_get_type;
2880 spec->ops.chmap_validate = nvhdmi_chmap_validate;
2881
2882 return 0;
2883}
2884
84eb01be 2885/*
5a613584 2886 * ATI/AMD-specific implementations
84eb01be
TI		 2887 */
2888
5a613584
AH		 2889#define is_amdhdmi_rev3_or_later(codec) \
2890 ((codec)->vendor_id == 0x1002aa01 && ((codec)->revision_id & 0xff00) >= 0x0300)
2891#define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
2892
2893/* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
2894#define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
2895#define ATI_VERB_SET_DOWNMIX_INFO 0x772
2896#define ATI_VERB_SET_MULTICHANNEL_01 0x777
2897#define ATI_VERB_SET_MULTICHANNEL_23 0x778
2898#define ATI_VERB_SET_MULTICHANNEL_45 0x779
2899#define ATI_VERB_SET_MULTICHANNEL_67 0x77a
461cf6b3 2900#define ATI_VERB_SET_HBR_CONTROL 0x77c
5a613584
AH		 2901#define ATI_VERB_SET_MULTICHANNEL_1 0x785
2902#define ATI_VERB_SET_MULTICHANNEL_3 0x786
2903#define ATI_VERB_SET_MULTICHANNEL_5 0x787
2904#define ATI_VERB_SET_MULTICHANNEL_7 0x788
2905#define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
2906#define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
2907#define ATI_VERB_GET_DOWNMIX_INFO 0xf72
2908#define ATI_VERB_GET_MULTICHANNEL_01 0xf77
2909#define ATI_VERB_GET_MULTICHANNEL_23 0xf78
2910#define ATI_VERB_GET_MULTICHANNEL_45 0xf79
2911#define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
461cf6b3 2912#define ATI_VERB_GET_HBR_CONTROL 0xf7c
5a613584
AH		 2913#define ATI_VERB_GET_MULTICHANNEL_1 0xf85
2914#define ATI_VERB_GET_MULTICHANNEL_3 0xf86
2915#define ATI_VERB_GET_MULTICHANNEL_5 0xf87
2916#define ATI_VERB_GET_MULTICHANNEL_7 0xf88
2917#define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
2918
84d69e79
AH		 2919/* AMD specific HDA cvt verbs */
2920#define ATI_VERB_SET_RAMP_RATE 0x770
2921#define ATI_VERB_GET_RAMP_RATE 0xf70
2922
5a613584
AH		 2923#define ATI_OUT_ENABLE 0x1
2924
2925#define ATI_MULTICHANNEL_MODE_PAIRED 0
2926#define ATI_MULTICHANNEL_MODE_SINGLE 1
2927
461cf6b3
AH		 2928#define ATI_HBR_CAPABLE 0x01
2929#define ATI_HBR_ENABLE 0x10
2930
89250f84
AH		 2931static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
2932 unsigned char *buf, int *eld_size)
2933{
2934 /* call hda_eld.c ATI/AMD-specific function */
2935 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
2936 is_amdhdmi_rev3_or_later(codec));
2937}
2938
5a613584
AH		 2939static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
2940 int active_channels, int conn_type)
2941{
2942 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
2943}
2944
2945static int atihdmi_paired_swap_fc_lfe(int pos)
2946{
2947 /*
2948 * ATI/AMD have automatic FC/LFE swap built-in
2949 * when in pairwise mapping mode.
2950 */
2951
2952 switch (pos) {
2953 /* see channel_allocations[].speakers[] */
2954 case 2: return 3;
2955 case 3: return 2;
2956 default: break;
2957 }
2958
2959 return pos;
2960}
2961
2962static int atihdmi_paired_chmap_validate(int ca, int chs, unsigned char *map)
2963{
2964 struct cea_channel_speaker_allocation *cap;
2965 int i, j;
2966
2967 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
2968
2969 cap = &channel_allocations[get_channel_allocation_order(ca)];
2970 for (i = 0; i < chs; ++i) {
2971 int mask = to_spk_mask(map[i]);
2972 bool ok = false;
2973 bool companion_ok = false;
2974
2975 if (!mask)
2976 continue;
2977
2978 for (j = 0 + i % 2; j < 8; j += 2) {
2979 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
2980 if (cap->speakers[chan_idx] == mask) {
2981 /* channel is in a supported position */
2982 ok = true;
2983
2984 if (i % 2 == 0 && i + 1 < chs) {
2985 /* even channel, check the odd companion */
2986 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
2987 int comp_mask_req = to_spk_mask(map[i+1]);
2988 int comp_mask_act = cap->speakers[comp_chan_idx];
2989
2990 if (comp_mask_req == comp_mask_act)
2991 companion_ok = true;
2992 else
2993 return -EINVAL;
2994 }
2995 break;
2996 }
2997 }
2998
2999 if (!ok)
3000 return -EINVAL;
3001
3002 if (companion_ok)
3003 i++; /* companion channel already checked */
3004 }
3005
3006 return 0;
3007}
3008
3009static int atihdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3010 int hdmi_slot, int stream_channel)
3011{
3012 int verb;
3013 int ati_channel_setup = 0;
3014
3015 if (hdmi_slot > 7)
3016 return -EINVAL;
3017
3018 if (!has_amd_full_remap_support(codec)) {
3019 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3020
3021 /* In case this is an odd slot but without stream channel, do not
3022 * disable the slot since the corresponding even slot could have a
3023 * channel. In case neither have a channel, the slot pair will be
3024 * disabled when this function is called for the even slot. */
3025 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3026 return 0;
3027
3028 hdmi_slot -= hdmi_slot % 2;
3029
3030 if (stream_channel != 0xf)
3031 stream_channel -= stream_channel % 2;
3032 }
3033
3034 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3035
3036 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3037
3038 if (stream_channel != 0xf)
3039 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3040
3041 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3042}
3043
3044static int atihdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3045 int asp_slot)
3046{
3047 bool was_odd = false;
3048 int ati_asp_slot = asp_slot;
3049 int verb;
3050 int ati_channel_setup;
3051
3052 if (asp_slot > 7)
3053 return -EINVAL;
3054
3055 if (!has_amd_full_remap_support(codec)) {
3056 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3057 if (ati_asp_slot % 2 != 0) {
3058 ati_asp_slot -= 1;
3059 was_odd = true;
3060 }
3061 }
3062
3063 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3064
3065 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3066
3067 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3068 return 0xf;
3069
3070 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3071}
84eb01be 3072
5a613584
AH		 3073static int atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
3074 int channels)
3075{
3076 int c;
3077
3078 /*
3079 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3080 * we need to take that into account (a single channel may take 2
3081 * channel slots if we need to carry a silent channel next to it).
3082 * On Rev3+ AMD codecs this function is not used.
3083 */
3084 int chanpairs = 0;
3085
3086 /* We only produce even-numbered channel count TLVs */
3087 if ((channels % 2) != 0)
3088 return -1;
3089
3090 for (c = 0; c < 7; c += 2) {
3091 if (cap->speakers[c] || cap->speakers[c+1])
3092 chanpairs++;
3093 }
3094
3095 if (chanpairs * 2 != channels)
3096 return -1;
3097
3098 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3099}
3100
3101static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
3102 unsigned int *chmap, int channels)
3103{
3104 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3105 int count = 0;
3106 int c;
3107
3108 for (c = 7; c >= 0; c--) {
3109 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3110 int spk = cap->speakers[chan];
3111 if (!spk) {
3112 /* add N/A channel if the companion channel is occupied */
3113 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3114 chmap[count++] = SNDRV_CHMAP_NA;
3115
3116 continue;
3117 }
3118
3119 chmap[count++] = spk_to_chmap(spk);
3120 }
3121
3122 WARN_ON(count != channels);
3123}
3124
461cf6b3
AH		 3125static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3126 bool hbr)
3127{
3128 int hbr_ctl, hbr_ctl_new;
3129
3130 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
13122e6e 3131 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
461cf6b3
AH		 3132 if (hbr)
3133 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3134 else
3135 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3136
4e76a883
TI		 3137 codec_dbg(codec,
3138 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
461cf6b3
AH		 3139 pin_nid,
3140 hbr_ctl == hbr_ctl_new ? "" : "new-",
3141 hbr_ctl_new);
3142
3143 if (hbr_ctl != hbr_ctl_new)
3144 snd_hda_codec_write(codec, pin_nid, 0,
3145 ATI_VERB_SET_HBR_CONTROL,
3146 hbr_ctl_new);
3147
3148 } else if (hbr)
3149 return -EINVAL;
3150
3151 return 0;
3152}
3153
84d69e79
AH		 3154static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3155 hda_nid_t pin_nid, u32 stream_tag, int format)
3156{
3157
3158 if (is_amdhdmi_rev3_or_later(codec)) {
3159 int ramp_rate = 180; /* default as per AMD spec */
3160 /* disable ramp-up/down for non-pcm as per AMD spec */
3161 if (format & AC_FMT_TYPE_NON_PCM)
3162 ramp_rate = 0;
3163
3164 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3165 }
3166
3167 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3168}
3169
3170
5a613584 3171static int atihdmi_init(struct hda_codec *codec)
84eb01be
TI		 3172{
3173 struct hdmi_spec *spec = codec->spec;
5a613584 3174 int pin_idx, err;
84eb01be 3175
5a613584
AH		 3176 err = generic_hdmi_init(codec);
3177
3178 if (err)
84eb01be 3179 return err;
5a613584
AH		 3180
3181 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3182 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3183
3184 /* make sure downmix information in infoframe is zero */
3185 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3186
3187 /* enable channel-wise remap mode if supported */
3188 if (has_amd_full_remap_support(codec))
3189 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3190 ATI_VERB_SET_MULTICHANNEL_MODE,
3191 ATI_MULTICHANNEL_MODE_SINGLE);
84eb01be 3192 }
5a613584 3193
84eb01be
TI		 3194 return 0;
3195}
3196
84eb01be
TI		 3197static int patch_atihdmi(struct hda_codec *codec)
3198{
3199 struct hdmi_spec *spec;
5a613584
AH		 3200 struct hdmi_spec_per_cvt *per_cvt;
3201 int err, cvt_idx;
3202
3203 err = patch_generic_hdmi(codec);
3204
3205 if (err)
d0b1252d 3206 return err;
5a613584
AH		 3207
3208 codec->patch_ops.init = atihdmi_init;
3209
d0b1252d 3210 spec = codec->spec;
5a613584 3211
89250f84 3212 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
5a613584
AH		 3213 spec->ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3214 spec->ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3215 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
461cf6b3 3216 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
84d69e79 3217 spec->ops.setup_stream = atihdmi_setup_stream;
5a613584
AH		 3218
3219 if (!has_amd_full_remap_support(codec)) {
3220 /* override to ATI/AMD-specific versions with pairwise mapping */
3221 spec->ops.chmap_cea_alloc_validate_get_type =
3222 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3223 spec->ops.cea_alloc_to_tlv_chmap = atihdmi_paired_cea_alloc_to_tlv_chmap;
3224 spec->ops.chmap_validate = atihdmi_paired_chmap_validate;
3225 }
3226
3227 /* ATI/AMD converters do not advertise all of their capabilities */
3228 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3229 per_cvt = get_cvt(spec, cvt_idx);
3230 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3231 per_cvt->rates |= SUPPORTED_RATES;
3232 per_cvt->formats |= SUPPORTED_FORMATS;
3233 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3234 }
3235
3236 spec->channels_max = max(spec->channels_max, 8u);
3237
84eb01be
TI		 3238 return 0;
3239}
3240
3de5ff88
AL		 3241/* VIA HDMI Implementation */
3242#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3243#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3244
3de5ff88
AL		 3245static int patch_via_hdmi(struct hda_codec *codec)
3246{
250e41ac 3247 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3de5ff88 3248}
84eb01be 3249
f0639272
TI		 3250/*
3251 * called from hda_codec.c for generic HDMI support
3252 */
3253int snd_hda_parse_hdmi_codec(struct hda_codec *codec)
3254{
3255 return patch_generic_hdmi(codec);
3256}
2698ea98 3257EXPORT_SYMBOL_GPL(snd_hda_parse_hdmi_codec);
f0639272 3258
84eb01be
TI		 3259/*
3260 * patch entries
3261 */
fb79e1e0 3262static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
84eb01be
TI		 3263{ .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
3264{ .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
3265{ .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
5a613584 3266{ .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_atihdmi },
84eb01be
TI		 3267{ .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
3268{ .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
3269{ .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
3270{ .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3271{ .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3272{ .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3273{ .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3274{ .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
611885bc
AH		 3275{ .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_nvhdmi },
3276{ .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_nvhdmi },
3277{ .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_nvhdmi },
3278{ .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_nvhdmi },
3279{ .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_nvhdmi },
3280{ .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_nvhdmi },
3281{ .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_nvhdmi },
3282{ .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_nvhdmi },
3283{ .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_nvhdmi },
3284{ .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_nvhdmi },
3285{ .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_nvhdmi },
c8900a0f 3286/* 17 is known to be absent */
611885bc
AH		 3287{ .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_nvhdmi },
3288{ .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_nvhdmi },
3289{ .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_nvhdmi },
3290{ .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_nvhdmi },
3291{ .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_nvhdmi },
3292{ .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_nvhdmi },
3293{ .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_nvhdmi },
3294{ .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_nvhdmi },
3295{ .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_nvhdmi },
3296{ .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_nvhdmi },
3297{ .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_nvhdmi },
3298{ .id = 0x10de0060, .name = "GPU 60 HDMI/DP", .patch = patch_nvhdmi },
84eb01be
TI		 3299{ .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
3300{ .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
3de5ff88
AL		 3301{ .id = 0x11069f80, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
3302{ .id = 0x11069f81, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
3303{ .id = 0x11069f84, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
3304{ .id = 0x11069f85, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 3305{ .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
3306{ .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
3307{ .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
3308{ .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
3309{ .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
3310{ .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
591e610d 3311{ .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
1c76684d 3312{ .id = 0x80862807, .name = "Haswell HDMI", .patch = patch_generic_hdmi },
3adadd28 3313{ .id = 0x80862808, .name = "Broadwell HDMI", .patch = patch_generic_hdmi },
6edc59e6 3314{ .id = 0x80862880, .name = "CedarTrail HDMI", .patch = patch_generic_hdmi },
cc1a95d9 3315{ .id = 0x80862882, .name = "Valleyview2 HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 3316{ .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
3317{} /* terminator */
3318};
3319
3320MODULE_ALIAS("snd-hda-codec-id:1002793c");
3321MODULE_ALIAS("snd-hda-codec-id:10027919");
3322MODULE_ALIAS("snd-hda-codec-id:1002791a");
3323MODULE_ALIAS("snd-hda-codec-id:1002aa01");
3324MODULE_ALIAS("snd-hda-codec-id:10951390");
3325MODULE_ALIAS("snd-hda-codec-id:10951392");
3326MODULE_ALIAS("snd-hda-codec-id:10de0002");
3327MODULE_ALIAS("snd-hda-codec-id:10de0003");
3328MODULE_ALIAS("snd-hda-codec-id:10de0005");
3329MODULE_ALIAS("snd-hda-codec-id:10de0006");
3330MODULE_ALIAS("snd-hda-codec-id:10de0007");
3331MODULE_ALIAS("snd-hda-codec-id:10de000a");
3332MODULE_ALIAS("snd-hda-codec-id:10de000b");
3333MODULE_ALIAS("snd-hda-codec-id:10de000c");
3334MODULE_ALIAS("snd-hda-codec-id:10de000d");
3335MODULE_ALIAS("snd-hda-codec-id:10de0010");
3336MODULE_ALIAS("snd-hda-codec-id:10de0011");
3337MODULE_ALIAS("snd-hda-codec-id:10de0012");
3338MODULE_ALIAS("snd-hda-codec-id:10de0013");
3339MODULE_ALIAS("snd-hda-codec-id:10de0014");
c8900a0f
RS		 3340MODULE_ALIAS("snd-hda-codec-id:10de0015");
3341MODULE_ALIAS("snd-hda-codec-id:10de0016");
84eb01be
TI		 3342MODULE_ALIAS("snd-hda-codec-id:10de0018");
3343MODULE_ALIAS("snd-hda-codec-id:10de0019");
3344MODULE_ALIAS("snd-hda-codec-id:10de001a");
3345MODULE_ALIAS("snd-hda-codec-id:10de001b");
3346MODULE_ALIAS("snd-hda-codec-id:10de001c");
3347MODULE_ALIAS("snd-hda-codec-id:10de0040");
3348MODULE_ALIAS("snd-hda-codec-id:10de0041");
3349MODULE_ALIAS("snd-hda-codec-id:10de0042");
3350MODULE_ALIAS("snd-hda-codec-id:10de0043");
3351MODULE_ALIAS("snd-hda-codec-id:10de0044");
7ae48b56 3352MODULE_ALIAS("snd-hda-codec-id:10de0051");
d52392b1 3353MODULE_ALIAS("snd-hda-codec-id:10de0060");
84eb01be
TI		 3354MODULE_ALIAS("snd-hda-codec-id:10de0067");
3355MODULE_ALIAS("snd-hda-codec-id:10de8001");
3de5ff88
AL		 3356MODULE_ALIAS("snd-hda-codec-id:11069f80");
3357MODULE_ALIAS("snd-hda-codec-id:11069f81");
3358MODULE_ALIAS("snd-hda-codec-id:11069f84");
3359MODULE_ALIAS("snd-hda-codec-id:11069f85");
84eb01be
TI		 3360MODULE_ALIAS("snd-hda-codec-id:17e80047");
3361MODULE_ALIAS("snd-hda-codec-id:80860054");
3362MODULE_ALIAS("snd-hda-codec-id:80862801");
3363MODULE_ALIAS("snd-hda-codec-id:80862802");
3364MODULE_ALIAS("snd-hda-codec-id:80862803");
3365MODULE_ALIAS("snd-hda-codec-id:80862804");
3366MODULE_ALIAS("snd-hda-codec-id:80862805");
591e610d 3367MODULE_ALIAS("snd-hda-codec-id:80862806");
1c76684d 3368MODULE_ALIAS("snd-hda-codec-id:80862807");
3adadd28 3369MODULE_ALIAS("snd-hda-codec-id:80862808");
6edc59e6 3370MODULE_ALIAS("snd-hda-codec-id:80862880");
cc1a95d9 3371MODULE_ALIAS("snd-hda-codec-id:80862882");
84eb01be
TI		 3372MODULE_ALIAS("snd-hda-codec-id:808629fb");
3373
3374MODULE_LICENSE("GPL");
3375MODULE_DESCRIPTION("HDMI HD-audio codec");
3376MODULE_ALIAS("snd-hda-codec-intelhdmi");
3377MODULE_ALIAS("snd-hda-codec-nvhdmi");
3378MODULE_ALIAS("snd-hda-codec-atihdmi");
3379
3380static struct hda_codec_preset_list intel_list = {
3381 .preset = snd_hda_preset_hdmi,
3382 .owner = THIS_MODULE,
3383};
3384
3385static int __init patch_hdmi_init(void)
3386{
3387 return snd_hda_add_codec_preset(&intel_list);
3388}
3389
3390static void __exit patch_hdmi_exit(void)
3391{
3392 snd_hda_delete_codec_preset(&intel_list);
3393}
3394
3395module_init(patch_hdmi_init)
3396module_exit(patch_hdmi_exit)
Linux kernel - Deliverables
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