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[ALSA] ASoC: Add support for 12 MHz MCLK in TLV320AIC3X
[deliverable/linux.git] / sound / pci / hda / patch_sigmatel.c
CommitLineData
2f2f4251
M		 1/*
2 * Universal Interface for Intel High Definition Audio Codec
3 *
4 * HD audio interface patch for SigmaTel STAC92xx
5 *
6 * Copyright (c) 2005 Embedded Alley Solutions, Inc.
403d1944 7 * Matt Porter <mporter@embeddedalley.com>
2f2f4251
M		 8 *
9 * Based on patch_cmedia.c and patch_realtek.c
10 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
11 *
12 * This driver is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This driver is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 */
26
2f2f4251
M		 27#include <linux/init.h>
28#include <linux/delay.h>
29#include <linux/slab.h>
30#include <linux/pci.h>
31#include <sound/core.h>
c7d4b2fa 32#include <sound/asoundef.h>
2f2f4251
M		 33#include "hda_codec.h"
34#include "hda_local.h"
35
4e55096e 36#define NUM_CONTROL_ALLOC 32
a64135a2
MR		 37#define STAC_PWR_EVENT 0x20
38#define STAC_HP_EVENT 0x30
4e55096e 39
f5fcc13c
TI		 40enum {
41 STAC_REF,
bf277785 42 STAC_9200_OQO,
dfe495d0
TI		 43 STAC_9200_DELL_D21,
44 STAC_9200_DELL_D22,
45 STAC_9200_DELL_D23,
46 STAC_9200_DELL_M21,
47 STAC_9200_DELL_M22,
48 STAC_9200_DELL_M23,
49 STAC_9200_DELL_M24,
50 STAC_9200_DELL_M25,
51 STAC_9200_DELL_M26,
52 STAC_9200_DELL_M27,
1194b5b7 53 STAC_9200_GATEWAY,
f5fcc13c
TI		 54 STAC_9200_MODELS
55};
56
57enum {
58 STAC_9205_REF,
dfe495d0 59 STAC_9205_DELL_M42,
ae0a8ed8
TD		 60 STAC_9205_DELL_M43,
61 STAC_9205_DELL_M44,
f5fcc13c
TI		 62 STAC_9205_MODELS
63};
64
e1f0d669
MR		 65enum {
66 STAC_92HD73XX_REF,
67 STAC_92HD73XX_MODELS
68};
69
e035b841
MR		 70enum {
71 STAC_92HD71BXX_REF,
72 STAC_92HD71BXX_MODELS
73};
74
8e21c34c
TD		 75enum {
76 STAC_925x_REF,
77 STAC_M2_2,
78 STAC_MA6,
2c11f955 79 STAC_PA6,
8e21c34c
TD		 80 STAC_925x_MODELS
81};
82
f5fcc13c
TI		 83enum {
84 STAC_D945_REF,
85 STAC_D945GTP3,
86 STAC_D945GTP5,
5d5d3bc3
IZ		 87 STAC_INTEL_MAC_V1,
88 STAC_INTEL_MAC_V2,
89 STAC_INTEL_MAC_V3,
90 STAC_INTEL_MAC_V4,
91 STAC_INTEL_MAC_V5,
dfe495d0 92 /* for backward compatibility */
f5fcc13c 93 STAC_MACMINI,
3fc24d85 94 STAC_MACBOOK,
6f0778d8
NB		 95 STAC_MACBOOK_PRO_V1,
96 STAC_MACBOOK_PRO_V2,
f16928fb 97 STAC_IMAC_INTEL,
0dae0f83 98 STAC_IMAC_INTEL_20,
dfe495d0
TI		 99 STAC_922X_DELL_D81,
100 STAC_922X_DELL_D82,
101 STAC_922X_DELL_M81,
102 STAC_922X_DELL_M82,
f5fcc13c
TI		 103 STAC_922X_MODELS
104};
105
106enum {
107 STAC_D965_REF,
108 STAC_D965_3ST,
109 STAC_D965_5ST,
4ff076e5 110 STAC_DELL_3ST,
8e9068b1 111 STAC_DELL_BIOS,
f5fcc13c
TI		 112 STAC_927X_MODELS
113};
403d1944 114
2f2f4251 115struct sigmatel_spec {
c8b6bf9b 116 struct snd_kcontrol_new *mixers[4];
c7d4b2fa
M		 117 unsigned int num_mixers;
118
403d1944 119 int board_config;
c7d4b2fa 120 unsigned int surr_switch: 1;
403d1944
MP		 121 unsigned int line_switch: 1;
122 unsigned int mic_switch: 1;
3cc08dc6 123 unsigned int alt_switch: 1;
82bc955f 124 unsigned int hp_detect: 1;
c7d4b2fa 125
4fe5195c
MR		 126 /* gpio lines */
127 unsigned int gpio_mask;
128 unsigned int gpio_dir;
129 unsigned int gpio_data;
130 unsigned int gpio_mute;
131
132 /* analog loopback */
e1f0d669
MR		 133 unsigned char aloopback_mask;
134 unsigned char aloopback_shift;
8259980e 135
a64135a2
MR		 136 /* power management */
137 unsigned int num_pwrs;
138 hda_nid_t *pwr_nids;
b76c850f 139 hda_nid_t *dac_list;
a64135a2 140
2f2f4251 141 /* playback */
b22b4821
MR		 142 struct hda_input_mux *mono_mux;
143 unsigned int cur_mmux;
2f2f4251 144 struct hda_multi_out multiout;
3cc08dc6 145 hda_nid_t dac_nids[5];
2f2f4251
M		 146
147 /* capture */
148 hda_nid_t *adc_nids;
2f2f4251 149 unsigned int num_adcs;
dabbed6f
M		 150 hda_nid_t *mux_nids;
151 unsigned int num_muxes;
8b65727b
MP		 152 hda_nid_t *dmic_nids;
153 unsigned int num_dmics;
e1f0d669 154 hda_nid_t *dmux_nids;
1697055e 155 unsigned int num_dmuxes;
dabbed6f 156 hda_nid_t dig_in_nid;
b22b4821 157 hda_nid_t mono_nid;
2f2f4251 158
2f2f4251
M		 159 /* pin widgets */
160 hda_nid_t *pin_nids;
161 unsigned int num_pins;
2f2f4251 162 unsigned int *pin_configs;
11b44bbd 163 unsigned int *bios_pin_configs;
2f2f4251
M		 164
165 /* codec specific stuff */
166 struct hda_verb *init;
c8b6bf9b 167 struct snd_kcontrol_new *mixer;
2f2f4251
M		 168
169 /* capture source */
8b65727b 170 struct hda_input_mux *dinput_mux;
e1f0d669 171 unsigned int cur_dmux[2];
c7d4b2fa 172 struct hda_input_mux *input_mux;
3cc08dc6 173 unsigned int cur_mux[3];
2f2f4251 174
403d1944
MP		 175 /* i/o switches */
176 unsigned int io_switch[2];
0fb87bb4 177 unsigned int clfe_swap;
5f10c4a9 178 unsigned int aloopback;
2f2f4251 179
c7d4b2fa
M		 180 struct hda_pcm pcm_rec[2]; /* PCM information */
181
182 /* dynamic controls and input_mux */
183 struct auto_pin_cfg autocfg;
184 unsigned int num_kctl_alloc, num_kctl_used;
c8b6bf9b 185 struct snd_kcontrol_new *kctl_alloc;
8b65727b 186 struct hda_input_mux private_dimux;
c7d4b2fa 187 struct hda_input_mux private_imux;
b22b4821 188 struct hda_input_mux private_mono_mux;
2f2f4251
M		 189};
190
191static hda_nid_t stac9200_adc_nids[1] = {
192 0x03,
193};
194
195static hda_nid_t stac9200_mux_nids[1] = {
196 0x0c,
197};
198
199static hda_nid_t stac9200_dac_nids[1] = {
200 0x02,
201};
202
a64135a2
MR		 203static hda_nid_t stac92hd73xx_pwr_nids[8] = {
204 0x0a, 0x0b, 0x0c, 0xd, 0x0e,
205 0x0f, 0x10, 0x11
206};
207
e1f0d669
MR		 208static hda_nid_t stac92hd73xx_adc_nids[2] = {
209 0x1a, 0x1b
210};
211
212#define STAC92HD73XX_NUM_DMICS 2
213static hda_nid_t stac92hd73xx_dmic_nids[STAC92HD73XX_NUM_DMICS + 1] = {
214 0x13, 0x14, 0
215};
216
217#define STAC92HD73_DAC_COUNT 5
218static hda_nid_t stac92hd73xx_dac_nids[STAC92HD73_DAC_COUNT] = {
219 0x15, 0x16, 0x17, 0x18, 0x19,
220};
221
222static hda_nid_t stac92hd73xx_mux_nids[4] = {
223 0x28, 0x29, 0x2a, 0x2b,
224};
225
226static hda_nid_t stac92hd73xx_dmux_nids[2] = {
227 0x20, 0x21,
228};
229
a64135a2
MR		 230static hda_nid_t stac92hd71bxx_pwr_nids[3] = {
231 0x0a, 0x0d, 0x0f
232};
233
e035b841
MR		 234static hda_nid_t stac92hd71bxx_adc_nids[2] = {
235 0x12, 0x13,
236};
237
238static hda_nid_t stac92hd71bxx_mux_nids[2] = {
239 0x1a, 0x1b
240};
241
e1f0d669
MR		 242static hda_nid_t stac92hd71bxx_dmux_nids[1] = {
243 0x1c,
244};
245
e035b841
MR		 246static hda_nid_t stac92hd71bxx_dac_nids[2] = {
247 0x10, /*0x11, */
248};
249
250#define STAC92HD71BXX_NUM_DMICS 2
251static hda_nid_t stac92hd71bxx_dmic_nids[STAC92HD71BXX_NUM_DMICS + 1] = {
252 0x18, 0x19, 0
253};
254
8e21c34c
TD		 255static hda_nid_t stac925x_adc_nids[1] = {
256 0x03,
257};
258
259static hda_nid_t stac925x_mux_nids[1] = {
260 0x0f,
261};
262
263static hda_nid_t stac925x_dac_nids[1] = {
264 0x02,
265};
266
f6e9852a
TI		 267#define STAC925X_NUM_DMICS 1
268static hda_nid_t stac925x_dmic_nids[STAC925X_NUM_DMICS + 1] = {
269 0x15, 0
2c11f955
TD		 270};
271
1697055e
TI		 272static hda_nid_t stac925x_dmux_nids[1] = {
273 0x14,
274};
275
2f2f4251
M		 276static hda_nid_t stac922x_adc_nids[2] = {
277 0x06, 0x07,
278};
279
280static hda_nid_t stac922x_mux_nids[2] = {
281 0x12, 0x13,
282};
283
3cc08dc6
MP		 284static hda_nid_t stac927x_adc_nids[3] = {
285 0x07, 0x08, 0x09
286};
287
288static hda_nid_t stac927x_mux_nids[3] = {
289 0x15, 0x16, 0x17
290};
291
b76c850f
MR		 292static hda_nid_t stac927x_dac_nids[6] = {
293 0x02, 0x03, 0x04, 0x05, 0x06, 0
294};
295
e1f0d669
MR		 296static hda_nid_t stac927x_dmux_nids[1] = {
297 0x1b,
298};
299
7f16859a
MR		 300#define STAC927X_NUM_DMICS 2
301static hda_nid_t stac927x_dmic_nids[STAC927X_NUM_DMICS + 1] = {
302 0x13, 0x14, 0
303};
304
f3302a59
MP		 305static hda_nid_t stac9205_adc_nids[2] = {
306 0x12, 0x13
307};
308
309static hda_nid_t stac9205_mux_nids[2] = {
310 0x19, 0x1a
311};
312
e1f0d669 313static hda_nid_t stac9205_dmux_nids[1] = {
1697055e 314 0x1d,
e1f0d669
MR		 315};
316
f6e9852a
TI		 317#define STAC9205_NUM_DMICS 2
318static hda_nid_t stac9205_dmic_nids[STAC9205_NUM_DMICS + 1] = {
319 0x17, 0x18, 0
8b65727b
MP		 320};
321
c7d4b2fa 322static hda_nid_t stac9200_pin_nids[8] = {
93ed1503
TD		 323 0x08, 0x09, 0x0d, 0x0e,
324 0x0f, 0x10, 0x11, 0x12,
2f2f4251
M		 325};
326
8e21c34c
TD		 327static hda_nid_t stac925x_pin_nids[8] = {
328 0x07, 0x08, 0x0a, 0x0b,
329 0x0c, 0x0d, 0x10, 0x11,
330};
331
2f2f4251
M		 332static hda_nid_t stac922x_pin_nids[10] = {
333 0x0a, 0x0b, 0x0c, 0x0d, 0x0e,
334 0x0f, 0x10, 0x11, 0x15, 0x1b,
335};
336
e1f0d669
MR		 337static hda_nid_t stac92hd73xx_pin_nids[12] = {
338 0x0a, 0x0b, 0x0c, 0x0d, 0x0e,
339 0x0f, 0x10, 0x11, 0x12, 0x13,
340 0x14, 0x22
341};
342
e035b841
MR		 343static hda_nid_t stac92hd71bxx_pin_nids[10] = {
344 0x0a, 0x0b, 0x0c, 0x0d, 0x0e,
345 0x0f, 0x14, 0x18, 0x19, 0x1e,
346};
347
3cc08dc6
MP		 348static hda_nid_t stac927x_pin_nids[14] = {
349 0x0a, 0x0b, 0x0c, 0x0d, 0x0e,
350 0x0f, 0x10, 0x11, 0x12, 0x13,
351 0x14, 0x21, 0x22, 0x23,
352};
353
f3302a59
MP		 354static hda_nid_t stac9205_pin_nids[12] = {
355 0x0a, 0x0b, 0x0c, 0x0d, 0x0e,
356 0x0f, 0x14, 0x16, 0x17, 0x18,
357 0x21, 0x22,
f3302a59
MP		 358};
359
8b65727b
MP		 360static int stac92xx_dmux_enum_info(struct snd_kcontrol *kcontrol,
361 struct snd_ctl_elem_info *uinfo)
362{
363 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
364 struct sigmatel_spec *spec = codec->spec;
365 return snd_hda_input_mux_info(spec->dinput_mux, uinfo);
366}
367
368static int stac92xx_dmux_enum_get(struct snd_kcontrol *kcontrol,
369 struct snd_ctl_elem_value *ucontrol)
370{
371 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
372 struct sigmatel_spec *spec = codec->spec;
e1f0d669 373 unsigned int dmux_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
8b65727b 374
e1f0d669 375 ucontrol->value.enumerated.item[0] = spec->cur_dmux[dmux_idx];
8b65727b
MP		 376 return 0;
377}
378
379static int stac92xx_dmux_enum_put(struct snd_kcontrol *kcontrol,
380 struct snd_ctl_elem_value *ucontrol)
381{
382 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
383 struct sigmatel_spec *spec = codec->spec;
e1f0d669 384 unsigned int dmux_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
8b65727b
MP		 385
386 return snd_hda_input_mux_put(codec, spec->dinput_mux, ucontrol,
e1f0d669 387 spec->dmux_nids[dmux_idx], &spec->cur_dmux[dmux_idx]);
8b65727b
MP		 388}
389
c8b6bf9b 390static int stac92xx_mux_enum_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2f2f4251
M		 391{
392 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
393 struct sigmatel_spec *spec = codec->spec;
c7d4b2fa 394 return snd_hda_input_mux_info(spec->input_mux, uinfo);
2f2f4251
M		 395}
396
c8b6bf9b 397static int stac92xx_mux_enum_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2f2f4251
M		 398{
399 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
400 struct sigmatel_spec *spec = codec->spec;
401 unsigned int adc_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
402
403 ucontrol->value.enumerated.item[0] = spec->cur_mux[adc_idx];
404 return 0;
405}
406
c8b6bf9b 407static int stac92xx_mux_enum_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2f2f4251
M		 408{
409 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
410 struct sigmatel_spec *spec = codec->spec;
411 unsigned int adc_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
412
c7d4b2fa 413 return snd_hda_input_mux_put(codec, spec->input_mux, ucontrol,
2f2f4251
M		 414 spec->mux_nids[adc_idx], &spec->cur_mux[adc_idx]);
415}
416
b22b4821
MR		 417static int stac92xx_mono_mux_enum_info(struct snd_kcontrol *kcontrol,
418 struct snd_ctl_elem_info *uinfo)
419{
420 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
421 struct sigmatel_spec *spec = codec->spec;
422 return snd_hda_input_mux_info(spec->mono_mux, uinfo);
423}
424
425static int stac92xx_mono_mux_enum_get(struct snd_kcontrol *kcontrol,
426 struct snd_ctl_elem_value *ucontrol)
427{
428 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
429 struct sigmatel_spec *spec = codec->spec;
430
431 ucontrol->value.enumerated.item[0] = spec->cur_mmux;
432 return 0;
433}
434
435static int stac92xx_mono_mux_enum_put(struct snd_kcontrol *kcontrol,
436 struct snd_ctl_elem_value *ucontrol)
437{
438 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
439 struct sigmatel_spec *spec = codec->spec;
440
441 return snd_hda_input_mux_put(codec, spec->mono_mux, ucontrol,
442 spec->mono_nid, &spec->cur_mmux);
443}
444
5f10c4a9
ML		 445#define stac92xx_aloopback_info snd_ctl_boolean_mono_info
446
447static int stac92xx_aloopback_get(struct snd_kcontrol *kcontrol,
448 struct snd_ctl_elem_value *ucontrol)
449{
450 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
e1f0d669 451 unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
5f10c4a9
ML		 452 struct sigmatel_spec *spec = codec->spec;
453
e1f0d669
MR		 454 ucontrol->value.integer.value[0] = !!(spec->aloopback &
455 (spec->aloopback_mask << idx));
5f10c4a9
ML		 456 return 0;
457}
458
459static int stac92xx_aloopback_put(struct snd_kcontrol *kcontrol,
460 struct snd_ctl_elem_value *ucontrol)
461{
462 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
463 struct sigmatel_spec *spec = codec->spec;
e1f0d669 464 unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
5f10c4a9 465 unsigned int dac_mode;
e1f0d669 466 unsigned int val, idx_val;
5f10c4a9 467
e1f0d669
MR		 468 idx_val = spec->aloopback_mask << idx;
469 if (ucontrol->value.integer.value[0])
470 val = spec->aloopback | idx_val;
471 else
472 val = spec->aloopback & ~idx_val;
68ea7b2f 473 if (spec->aloopback == val)
5f10c4a9
ML		 474 return 0;
475
68ea7b2f 476 spec->aloopback = val;
5f10c4a9 477
e1f0d669
MR		 478 /* Only return the bits defined by the shift value of the
479 * first two bytes of the mask
480 */
5f10c4a9 481 dac_mode = snd_hda_codec_read(codec, codec->afg, 0,
e1f0d669
MR		 482 kcontrol->private_value & 0xFFFF, 0x0);
483 dac_mode >>= spec->aloopback_shift;
5f10c4a9 484
e1f0d669 485 if (spec->aloopback & idx_val) {
5f10c4a9 486 snd_hda_power_up(codec);
e1f0d669 487 dac_mode |= idx_val;
5f10c4a9
ML		 488 } else {
489 snd_hda_power_down(codec);
e1f0d669 490 dac_mode &= ~idx_val;
5f10c4a9
ML		 491 }
492
493 snd_hda_codec_write_cache(codec, codec->afg, 0,
494 kcontrol->private_value >> 16, dac_mode);
495
496 return 1;
497}
498
c7d4b2fa 499static struct hda_verb stac9200_core_init[] = {
2f2f4251 500 /* set dac0mux for dac converter */
c7d4b2fa 501 { 0x07, AC_VERB_SET_CONNECT_SEL, 0x00},
2f2f4251
M		 502 {}
503};
504
1194b5b7
TI		 505static struct hda_verb stac9200_eapd_init[] = {
506 /* set dac0mux for dac converter */
507 {0x07, AC_VERB_SET_CONNECT_SEL, 0x00},
508 {0x08, AC_VERB_SET_EAPD_BTLENABLE, 0x02},
509 {}
510};
511
e1f0d669
MR		 512static struct hda_verb stac92hd73xx_6ch_core_init[] = {
513 /* set master volume and direct control */
514 { 0x1f, AC_VERB_SET_VOLUME_KNOB_CONTROL, 0xff},
515 /* setup audio connections */
516 { 0x0f, AC_VERB_SET_CONNECT_SEL, 0x00},
517 { 0x10, AC_VERB_SET_CONNECT_SEL, 0x01},
518 { 0x11, AC_VERB_SET_CONNECT_SEL, 0x02},
519 /* setup adcs to point to mixer */
520 { 0x20, AC_VERB_SET_CONNECT_SEL, 0x0b},
521 { 0x21, AC_VERB_SET_CONNECT_SEL, 0x0b},
e1f0d669
MR		 522 { 0x0f, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT},
523 { 0x10, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT},
524 { 0x11, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT},
525 /* setup import muxs */
526 { 0x28, AC_VERB_SET_CONNECT_SEL, 0x01},
527 { 0x29, AC_VERB_SET_CONNECT_SEL, 0x01},
528 { 0x2a, AC_VERB_SET_CONNECT_SEL, 0x01},
529 { 0x2b, AC_VERB_SET_CONNECT_SEL, 0x00},
530 {}
531};
532
533static struct hda_verb stac92hd73xx_8ch_core_init[] = {
534 /* set master volume and direct control */
535 { 0x1f, AC_VERB_SET_VOLUME_KNOB_CONTROL, 0xff},
536 /* setup audio connections */
537 { 0x0f, AC_VERB_SET_CONNECT_SEL, 0x00},
538 { 0x10, AC_VERB_SET_CONNECT_SEL, 0x01},
539 { 0x11, AC_VERB_SET_CONNECT_SEL, 0x02},
540 /* connect hp ports to dac3 */
541 { 0x0a, AC_VERB_SET_CONNECT_SEL, 0x03},
542 { 0x0d, AC_VERB_SET_CONNECT_SEL, 0x03},
543 /* setup adcs to point to mixer */
544 { 0x20, AC_VERB_SET_CONNECT_SEL, 0x0b},
545 { 0x21, AC_VERB_SET_CONNECT_SEL, 0x0b},
e1f0d669
MR		 546 { 0x0f, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT},
547 { 0x10, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT},
548 { 0x11, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT},
549 /* setup import muxs */
550 { 0x28, AC_VERB_SET_CONNECT_SEL, 0x01},
551 { 0x29, AC_VERB_SET_CONNECT_SEL, 0x01},
552 { 0x2a, AC_VERB_SET_CONNECT_SEL, 0x01},
553 { 0x2b, AC_VERB_SET_CONNECT_SEL, 0x03},
554 {}
555};
556
557static struct hda_verb stac92hd73xx_10ch_core_init[] = {
558 /* set master volume and direct control */
559 { 0x1f, AC_VERB_SET_VOLUME_KNOB_CONTROL, 0xff},
560 /* setup audio connections */
561 { 0x0f, AC_VERB_SET_CONNECT_SEL, 0x00 },
562 { 0x10, AC_VERB_SET_CONNECT_SEL, 0x01 },
563 { 0x11, AC_VERB_SET_CONNECT_SEL, 0x02 },
564 /* dac3 is connected to import3 mux */
565 { 0x18, AC_VERB_SET_AMP_GAIN_MUTE, 0xb07f},
566 /* connect hp ports to dac4 */
567 { 0x0a, AC_VERB_SET_CONNECT_SEL, 0x04},
568 { 0x0d, AC_VERB_SET_CONNECT_SEL, 0x04},
569 /* setup adcs to point to mixer */
570 { 0x20, AC_VERB_SET_CONNECT_SEL, 0x0b},
571 { 0x21, AC_VERB_SET_CONNECT_SEL, 0x0b},
e1f0d669
MR		 572 { 0x0f, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT},
573 { 0x10, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT},
574 { 0x11, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT},
575 /* setup import muxs */
576 { 0x28, AC_VERB_SET_CONNECT_SEL, 0x01},
577 { 0x29, AC_VERB_SET_CONNECT_SEL, 0x01},
578 { 0x2a, AC_VERB_SET_CONNECT_SEL, 0x01},
579 { 0x2b, AC_VERB_SET_CONNECT_SEL, 0x03},
580 {}
581};
582
e035b841 583static struct hda_verb stac92hd71bxx_core_init[] = {
541eee87
MR		 584 /* set master volume and direct control */
585 { 0x28, AC_VERB_SET_VOLUME_KNOB_CONTROL, 0xff},
586 /* connect headphone jack to dac1 */
587 { 0x0a, AC_VERB_SET_CONNECT_SEL, 0x01},
588 { 0x0f, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT}, /* Speaker */
589 /* unmute right and left channels for nodes 0x0a, 0xd, 0x0f */
590 { 0x0a, AC_VERB_SET_AMP_GAIN_MUTE, AMP_IN_UNMUTE(0)},
591 { 0x0d, AC_VERB_SET_AMP_GAIN_MUTE, AMP_IN_UNMUTE(0)},
592 { 0x0f, AC_VERB_SET_AMP_GAIN_MUTE, AMP_IN_UNMUTE(0)},
541eee87
MR		 593};
594
595static struct hda_verb stac92hd71bxx_analog_core_init[] = {
e035b841
MR		 596 /* set master volume and direct control */
597 { 0x28, AC_VERB_SET_VOLUME_KNOB_CONTROL, 0xff},
598 /* connect headphone jack to dac1 */
599 { 0x0a, AC_VERB_SET_CONNECT_SEL, 0x01},
9b35947f
MR		 600 /* connect ports 0d and 0f to audio mixer */
601 { 0x0d, AC_VERB_SET_CONNECT_SEL, 0x2},
602 { 0x0f, AC_VERB_SET_CONNECT_SEL, 0x2},
a64135a2 603 { 0x0f, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT}, /* Speaker */
9b35947f
MR		 604 /* unmute dac0 input in audio mixer */
605 { 0x17, AC_VERB_SET_AMP_GAIN_MUTE, 0x701f},
e035b841
MR		 606 /* unmute right and left channels for nodes 0x0a, 0xd, 0x0f */
607 { 0x0a, AC_VERB_SET_AMP_GAIN_MUTE, AMP_IN_UNMUTE(0)},
608 { 0x0d, AC_VERB_SET_AMP_GAIN_MUTE, AMP_IN_UNMUTE(0)},
609 { 0x0f, AC_VERB_SET_AMP_GAIN_MUTE, AMP_IN_UNMUTE(0)},
e035b841
MR		 610 {}
611};
612
8e21c34c
TD		 613static struct hda_verb stac925x_core_init[] = {
614 /* set dac0mux for dac converter */
615 { 0x06, AC_VERB_SET_CONNECT_SEL, 0x00},
616 {}
617};
618
c7d4b2fa 619static struct hda_verb stac922x_core_init[] = {
2f2f4251 620 /* set master volume and direct control */
c7d4b2fa 621 { 0x16, AC_VERB_SET_VOLUME_KNOB_CONTROL, 0xff},
2f2f4251
M		 622 {}
623};
624
93ed1503 625static struct hda_verb d965_core_init[] = {
19039bd0 626 /* set master volume and direct control */
93ed1503 627 { 0x24, AC_VERB_SET_VOLUME_KNOB_CONTROL, 0xff},
19039bd0
TI		 628 /* unmute node 0x1b */
629 { 0x1b, AC_VERB_SET_AMP_GAIN_MUTE, 0xb000},
630 /* select node 0x03 as DAC */
631 { 0x0b, AC_VERB_SET_CONNECT_SEL, 0x01},
632 {}
633};
634
3cc08dc6
MP		 635static struct hda_verb stac927x_core_init[] = {
636 /* set master volume and direct control */
637 { 0x24, AC_VERB_SET_VOLUME_KNOB_CONTROL, 0xff},
638 {}
639};
640
f3302a59
MP		 641static struct hda_verb stac9205_core_init[] = {
642 /* set master volume and direct control */
643 { 0x24, AC_VERB_SET_VOLUME_KNOB_CONTROL, 0xff},
644 {}
645};
646
b22b4821
MR		 647#define STAC_MONO_MUX \
648 { \
649 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
650 .name = "Mono Mux", \
651 .count = 1, \
652 .info = stac92xx_mono_mux_enum_info, \
653 .get = stac92xx_mono_mux_enum_get, \
654 .put = stac92xx_mono_mux_enum_put, \
655 }
656
9e05b7a3 657#define STAC_INPUT_SOURCE(cnt) \
ca7c5a8b
ML		 658 { \
659 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
660 .name = "Input Source", \
9e05b7a3 661 .count = cnt, \
ca7c5a8b
ML		 662 .info = stac92xx_mux_enum_info, \
663 .get = stac92xx_mux_enum_get, \
664 .put = stac92xx_mux_enum_put, \
665 }
666
e1f0d669 667#define STAC_ANALOG_LOOPBACK(verb_read, verb_write, cnt) \
5f10c4a9
ML		 668 { \
669 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
670 .name = "Analog Loopback", \
e1f0d669 671 .count = cnt, \
5f10c4a9
ML		 672 .info = stac92xx_aloopback_info, \
673 .get = stac92xx_aloopback_get, \
674 .put = stac92xx_aloopback_put, \
675 .private_value = verb_read | (verb_write << 16), \
676 }
677
c8b6bf9b 678static struct snd_kcontrol_new stac9200_mixer[] = {
2f2f4251
M		 679 HDA_CODEC_VOLUME("Master Playback Volume", 0xb, 0, HDA_OUTPUT),
680 HDA_CODEC_MUTE("Master Playback Switch", 0xb, 0, HDA_OUTPUT),
9e05b7a3 681 STAC_INPUT_SOURCE(1),
2f2f4251
M		 682 HDA_CODEC_VOLUME("Capture Volume", 0x0a, 0, HDA_OUTPUT),
683 HDA_CODEC_MUTE("Capture Switch", 0x0a, 0, HDA_OUTPUT),
c7d4b2fa 684 HDA_CODEC_VOLUME("Capture Mux Volume", 0x0c, 0, HDA_OUTPUT),
2f2f4251
M		 685 { } /* end */
686};
687
e1f0d669 688static struct snd_kcontrol_new stac92hd73xx_6ch_mixer[] = {
e1f0d669
MR		 689 STAC_ANALOG_LOOPBACK(0xFA0, 0x7A1, 3),
690
e1f0d669
MR		 691 HDA_CODEC_VOLUME_IDX("Capture Volume", 0x0, 0x20, 0x0, HDA_OUTPUT),
692 HDA_CODEC_MUTE_IDX("Capture Switch", 0x0, 0x20, 0x0, HDA_OUTPUT),
693
694 HDA_CODEC_VOLUME_IDX("Capture Volume", 0x1, 0x21, 0x0, HDA_OUTPUT),
695 HDA_CODEC_MUTE_IDX("Capture Switch", 0x1, 0x21, 0x0, HDA_OUTPUT),
696
697 HDA_CODEC_VOLUME("Front Mic Mixer Capture Volume", 0x1d, 0, HDA_INPUT),
698 HDA_CODEC_MUTE("Front Mic Mixer Capture Switch", 0x1d, 0, HDA_INPUT),
699
700 HDA_CODEC_VOLUME("Mic Mixer Capture Volume", 0x1d, 0x1, HDA_INPUT),
701 HDA_CODEC_MUTE("Mic Mixer Capture Switch", 0x1d, 0x1, HDA_INPUT),
702
703 HDA_CODEC_VOLUME("Line In Mixer Capture Volume", 0x1d, 0x2, HDA_INPUT),
704 HDA_CODEC_MUTE("Line In Mixer Capture Switch", 0x1d, 0x2, HDA_INPUT),
705
706 HDA_CODEC_VOLUME("DAC Mixer Capture Volume", 0x1d, 0x3, HDA_INPUT),
707 HDA_CODEC_MUTE("DAC Mixer Capture Switch", 0x1d, 0x3, HDA_INPUT),
708
709 HDA_CODEC_VOLUME("CD Mixer Capture Volume", 0x1d, 0x4, HDA_INPUT),
710 HDA_CODEC_MUTE("CD Mixer Capture Switch", 0x1d, 0x4, HDA_INPUT),
711 { } /* end */
712};
713
714static struct snd_kcontrol_new stac92hd73xx_8ch_mixer[] = {
e1f0d669
MR		 715 STAC_ANALOG_LOOPBACK(0xFA0, 0x7A1, 4),
716
e1f0d669
MR		 717 HDA_CODEC_VOLUME_IDX("Capture Volume", 0x0, 0x20, 0x0, HDA_OUTPUT),
718 HDA_CODEC_MUTE_IDX("Capture Switch", 0x0, 0x20, 0x0, HDA_OUTPUT),
719
720 HDA_CODEC_VOLUME_IDX("Capture Volume", 0x1, 0x21, 0x0, HDA_OUTPUT),
721 HDA_CODEC_MUTE_IDX("Capture Switch", 0x1, 0x21, 0x0, HDA_OUTPUT),
722
723 HDA_CODEC_VOLUME("Front Mic Mixer Capture Volume", 0x1d, 0, HDA_INPUT),
724 HDA_CODEC_MUTE("Front Mic Mixer Capture Switch", 0x1d, 0, HDA_INPUT),
725
726 HDA_CODEC_VOLUME("Mic Mixer Capture Volume", 0x1d, 0x1, HDA_INPUT),
727 HDA_CODEC_MUTE("Mic Mixer Capture Switch", 0x1d, 0x1, HDA_INPUT),
728
729 HDA_CODEC_VOLUME("Line In Mixer Capture Volume", 0x1d, 0x2, HDA_INPUT),
730 HDA_CODEC_MUTE("Line In Mixer Capture Switch", 0x1d, 0x2, HDA_INPUT),
731
732 HDA_CODEC_VOLUME("DAC Mixer Capture Volume", 0x1d, 0x3, HDA_INPUT),
733 HDA_CODEC_MUTE("DAC Mixer Capture Switch", 0x1d, 0x3, HDA_INPUT),
734
735 HDA_CODEC_VOLUME("CD Mixer Capture Volume", 0x1d, 0x4, HDA_INPUT),
736 HDA_CODEC_MUTE("CD Mixer Capture Switch", 0x1d, 0x4, HDA_INPUT),
737 { } /* end */
738};
739
740static struct snd_kcontrol_new stac92hd73xx_10ch_mixer[] = {
e1f0d669
MR		 741 STAC_ANALOG_LOOPBACK(0xFA0, 0x7A1, 5),
742
e1f0d669
MR		 743 HDA_CODEC_VOLUME_IDX("Capture Volume", 0x0, 0x20, 0x0, HDA_OUTPUT),
744 HDA_CODEC_MUTE_IDX("Capture Switch", 0x0, 0x20, 0x0, HDA_OUTPUT),
745
746 HDA_CODEC_VOLUME_IDX("Capture Volume", 0x1, 0x21, 0x0, HDA_OUTPUT),
747 HDA_CODEC_MUTE_IDX("Capture Switch", 0x1, 0x21, 0x0, HDA_OUTPUT),
748
749 HDA_CODEC_VOLUME("Front Mic Mixer Capture Volume", 0x1d, 0, HDA_INPUT),
750 HDA_CODEC_MUTE("Front Mic Mixer Capture Switch", 0x1d, 0, HDA_INPUT),
751
752 HDA_CODEC_VOLUME("Mic Mixer Capture Volume", 0x1d, 0x1, HDA_INPUT),
753 HDA_CODEC_MUTE("Mic Mixer Capture Switch", 0x1d, 0x1, HDA_INPUT),
754
755 HDA_CODEC_VOLUME("Line In Mixer Capture Volume", 0x1d, 0x2, HDA_INPUT),
756 HDA_CODEC_MUTE("Line In Mixer Capture Switch", 0x1d, 0x2, HDA_INPUT),
757
758 HDA_CODEC_VOLUME("DAC Mixer Capture Volume", 0x1d, 0x3, HDA_INPUT),
759 HDA_CODEC_MUTE("DAC Mixer Capture Switch", 0x1d, 0x3, HDA_INPUT),
760
761 HDA_CODEC_VOLUME("CD Mixer Capture Volume", 0x1d, 0x4, HDA_INPUT),
762 HDA_CODEC_MUTE("CD Mixer Capture Switch", 0x1d, 0x4, HDA_INPUT),
763 { } /* end */
764};
765
541eee87 766static struct snd_kcontrol_new stac92hd71bxx_analog_mixer[] = {
e035b841 767 STAC_INPUT_SOURCE(2),
e035b841 768
9b35947f
MR		 769 HDA_CODEC_VOLUME_IDX("Capture Volume", 0x0, 0x1c, 0x0, HDA_OUTPUT),
770 HDA_CODEC_MUTE_IDX("Capture Switch", 0x0, 0x1c, 0x0, HDA_OUTPUT),
771 HDA_CODEC_VOLUME_IDX("Capture Mux Volume", 0x0, 0x1a, 0x0, HDA_OUTPUT),
772
773 HDA_CODEC_VOLUME_IDX("Capture Volume", 0x1, 0x1d, 0x0, HDA_OUTPUT),
774 HDA_CODEC_MUTE_IDX("Capture Switch", 0x1, 0x1d, 0x0, HDA_OUTPUT),
775 HDA_CODEC_VOLUME_IDX("Capture Mux Volume", 0x1, 0x1b, 0x0, HDA_OUTPUT),
e035b841 776
9b35947f
MR		 777 HDA_CODEC_MUTE("Analog Loopback 1", 0x17, 0x3, HDA_INPUT),
778 HDA_CODEC_MUTE("Analog Loopback 2", 0x17, 0x4, HDA_INPUT),
e035b841
MR		 779 { } /* end */
780};
781
541eee87 782static struct snd_kcontrol_new stac92hd71bxx_mixer[] = {
541eee87
MR		 783 STAC_INPUT_SOURCE(2),
784 STAC_ANALOG_LOOPBACK(0xFA0, 0x7A0, 2),
785
541eee87
MR		 786 HDA_CODEC_VOLUME_IDX("Capture Volume", 0x0, 0x1c, 0x0, HDA_OUTPUT),
787 HDA_CODEC_MUTE_IDX("Capture Switch", 0x0, 0x1c, 0x0, HDA_OUTPUT),
788 HDA_CODEC_VOLUME_IDX("Capture Mux Volume", 0x0, 0x1a, 0x0, HDA_OUTPUT),
789
790 HDA_CODEC_VOLUME_IDX("Capture Volume", 0x1, 0x1d, 0x0, HDA_OUTPUT),
791 HDA_CODEC_MUTE_IDX("Capture Switch", 0x1, 0x1d, 0x0, HDA_OUTPUT),
792 HDA_CODEC_VOLUME_IDX("Capture Mux Volume", 0x1, 0x1b, 0x0, HDA_OUTPUT),
793 { } /* end */
794};
795
8e21c34c 796static struct snd_kcontrol_new stac925x_mixer[] = {
9e05b7a3 797 STAC_INPUT_SOURCE(1),
8e21c34c
TD		 798 HDA_CODEC_VOLUME("Capture Volume", 0x09, 0, HDA_OUTPUT),
799 HDA_CODEC_MUTE("Capture Switch", 0x09, 0, HDA_OUTPUT),
800 HDA_CODEC_VOLUME("Capture Mux Volume", 0x0f, 0, HDA_OUTPUT),
801 { } /* end */
802};
803
9e05b7a3 804static struct snd_kcontrol_new stac9205_mixer[] = {
9e05b7a3 805 STAC_INPUT_SOURCE(2),
e1f0d669 806 STAC_ANALOG_LOOPBACK(0xFE0, 0x7E0, 1),
9e05b7a3
ML		 807
808 HDA_CODEC_VOLUME_IDX("Capture Volume", 0x0, 0x1b, 0x0, HDA_INPUT),
809 HDA_CODEC_MUTE_IDX("Capture Switch", 0x0, 0x1d, 0x0, HDA_OUTPUT),
810 HDA_CODEC_VOLUME_IDX("Mux Capture Volume", 0x0, 0x19, 0x0, HDA_OUTPUT),
811
812 HDA_CODEC_VOLUME_IDX("Capture Volume", 0x1, 0x1c, 0x0, HDA_INPUT),
813 HDA_CODEC_MUTE_IDX("Capture Switch", 0x1, 0x1e, 0x0, HDA_OUTPUT),
814 HDA_CODEC_VOLUME_IDX("Mux Capture Volume", 0x1, 0x1A, 0x0, HDA_OUTPUT),
815
2f2f4251
M		 816 { } /* end */
817};
818
19039bd0 819/* This needs to be generated dynamically based on sequence */
9e05b7a3
ML		 820static struct snd_kcontrol_new stac922x_mixer[] = {
821 STAC_INPUT_SOURCE(2),
9e05b7a3
ML		 822 HDA_CODEC_VOLUME_IDX("Capture Volume", 0x0, 0x17, 0x0, HDA_INPUT),
823 HDA_CODEC_MUTE_IDX("Capture Switch", 0x0, 0x17, 0x0, HDA_INPUT),
824 HDA_CODEC_VOLUME_IDX("Mux Capture Volume", 0x0, 0x12, 0x0, HDA_OUTPUT),
825
826 HDA_CODEC_VOLUME_IDX("Capture Volume", 0x1, 0x18, 0x0, HDA_INPUT),
827 HDA_CODEC_MUTE_IDX("Capture Switch", 0x1, 0x18, 0x0, HDA_INPUT),
828 HDA_CODEC_VOLUME_IDX("Mux Capture Volume", 0x1, 0x13, 0x0, HDA_OUTPUT),
19039bd0
TI		 829 { } /* end */
830};
831
9e05b7a3 832
d1d985f0 833static struct snd_kcontrol_new stac927x_mixer[] = {
9e05b7a3 834 STAC_INPUT_SOURCE(3),
e1f0d669 835 STAC_ANALOG_LOOPBACK(0xFEB, 0x7EB, 1),
3cc08dc6 836
9e05b7a3
ML		 837 HDA_CODEC_VOLUME_IDX("Capture Volume", 0x0, 0x18, 0x0, HDA_INPUT),
838 HDA_CODEC_MUTE_IDX("Capture Switch", 0x0, 0x1b, 0x0, HDA_OUTPUT),
839 HDA_CODEC_VOLUME_IDX("Mux Capture Volume", 0x0, 0x15, 0x0, HDA_OUTPUT),
840
841 HDA_CODEC_VOLUME_IDX("Capture Volume", 0x1, 0x19, 0x0, HDA_INPUT),
842 HDA_CODEC_MUTE_IDX("Capture Switch", 0x1, 0x1c, 0x0, HDA_OUTPUT),
843 HDA_CODEC_VOLUME_IDX("Mux Capture Volume", 0x1, 0x16, 0x0, HDA_OUTPUT),
844
845 HDA_CODEC_VOLUME_IDX("Capture Volume", 0x2, 0x1A, 0x0, HDA_INPUT),
846 HDA_CODEC_MUTE_IDX("Capture Switch", 0x2, 0x1d, 0x0, HDA_OUTPUT),
847 HDA_CODEC_VOLUME_IDX("Mux Capture Volume", 0x2, 0x17, 0x0, HDA_OUTPUT),
f3302a59
MP		 848 { } /* end */
849};
850
1697055e
TI		 851static struct snd_kcontrol_new stac_dmux_mixer = {
852 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
853 .name = "Digital Input Source",
854 /* count set later */
855 .info = stac92xx_dmux_enum_info,
856 .get = stac92xx_dmux_enum_get,
857 .put = stac92xx_dmux_enum_put,
858};
859
2134ea4f
TI		 860static const char *slave_vols[] = {
861 "Front Playback Volume",
862 "Surround Playback Volume",
863 "Center Playback Volume",
864 "LFE Playback Volume",
865 "Side Playback Volume",
866 "Headphone Playback Volume",
867 "Headphone Playback Volume",
868 "Speaker Playback Volume",
869 "External Speaker Playback Volume",
870 "Speaker2 Playback Volume",
871 NULL
872};
873
874static const char *slave_sws[] = {
875 "Front Playback Switch",
876 "Surround Playback Switch",
877 "Center Playback Switch",
878 "LFE Playback Switch",
879 "Side Playback Switch",
880 "Headphone Playback Switch",
881 "Headphone Playback Switch",
882 "Speaker Playback Switch",
883 "External Speaker Playback Switch",
884 "Speaker2 Playback Switch",
edb54a55 885 "IEC958 Playback Switch",
2134ea4f
TI		 886 NULL
887};
888
2f2f4251
M		 889static int stac92xx_build_controls(struct hda_codec *codec)
890{
891 struct sigmatel_spec *spec = codec->spec;
892 int err;
c7d4b2fa 893 int i;
2f2f4251
M		 894
895 err = snd_hda_add_new_ctls(codec, spec->mixer);
896 if (err < 0)
897 return err;
c7d4b2fa
M		 898
899 for (i = 0; i < spec->num_mixers; i++) {
900 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
901 if (err < 0)
902 return err;
903 }
1697055e
TI		 904 if (spec->num_dmuxes > 0) {
905 stac_dmux_mixer.count = spec->num_dmuxes;
906 err = snd_ctl_add(codec->bus->card,
907 snd_ctl_new1(&stac_dmux_mixer, codec));
908 if (err < 0)
909 return err;
910 }
c7d4b2fa 911
dabbed6f
M		 912 if (spec->multiout.dig_out_nid) {
913 err = snd_hda_create_spdif_out_ctls(codec, spec->multiout.dig_out_nid);
914 if (err < 0)
915 return err;
9a08160b
TI		 916 err = snd_hda_create_spdif_share_sw(codec,
917 &spec->multiout);
918 if (err < 0)
919 return err;
920 spec->multiout.share_spdif = 1;
dabbed6f
M		 921 }
922 if (spec->dig_in_nid) {
923 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in_nid);
924 if (err < 0)
925 return err;
926 }
2134ea4f
TI		 927
928 /* if we have no master control, let's create it */
929 if (!snd_hda_find_mixer_ctl(codec, "Master Playback Volume")) {
1c82ed1b 930 unsigned int vmaster_tlv[4];
2134ea4f 931 snd_hda_set_vmaster_tlv(codec, spec->multiout.dac_nids[0],
1c82ed1b 932 HDA_OUTPUT, vmaster_tlv);
2134ea4f 933 err = snd_hda_add_vmaster(codec, "Master Playback Volume",
1c82ed1b 934 vmaster_tlv, slave_vols);
2134ea4f
TI		 935 if (err < 0)
936 return err;
937 }
938 if (!snd_hda_find_mixer_ctl(codec, "Master Playback Switch")) {
939 err = snd_hda_add_vmaster(codec, "Master Playback Switch",
940 NULL, slave_sws);
941 if (err < 0)
942 return err;
943 }
944
dabbed6f 945 return 0;
2f2f4251
M		 946}
947
403d1944 948static unsigned int ref9200_pin_configs[8] = {
dabbed6f 949 0x01c47010, 0x01447010, 0x0221401f, 0x01114010,
2f2f4251
M		 950 0x02a19020, 0x01a19021, 0x90100140, 0x01813122,
951};
952
dfe495d0
TI		 953/*
954 STAC 9200 pin configs for
955 102801A8
956 102801DE
957 102801E8
958*/
959static unsigned int dell9200_d21_pin_configs[8] = {
af6c016e
TI		 960 0x400001f0, 0x400001f1, 0x02214030, 0x01014010,
961 0x02a19020, 0x01a19021, 0x90100140, 0x01813122,
dfe495d0
TI		 962};
963
964/*
965 STAC 9200 pin configs for
966 102801C0
967 102801C1
968*/
969static unsigned int dell9200_d22_pin_configs[8] = {
af6c016e
TI		 970 0x400001f0, 0x400001f1, 0x0221401f, 0x01014010,
971 0x01813020, 0x02a19021, 0x90100140, 0x400001f2,
dfe495d0
TI		 972};
973
974/*
975 STAC 9200 pin configs for
976 102801C4 (Dell Dimension E310)
977 102801C5
978 102801C7
979 102801D9
980 102801DA
981 102801E3
982*/
983static unsigned int dell9200_d23_pin_configs[8] = {
af6c016e
TI		 984 0x400001f0, 0x400001f1, 0x0221401f, 0x01014010,
985 0x01813020, 0x01a19021, 0x90100140, 0x400001f2,
dfe495d0
TI		 986};
987
988
989/*
990 STAC 9200-32 pin configs for
991 102801B5 (Dell Inspiron 630m)
992 102801D8 (Dell Inspiron 640m)
993*/
994static unsigned int dell9200_m21_pin_configs[8] = {
af6c016e
TI		 995 0x40c003fa, 0x03441340, 0x0321121f, 0x90170310,
996 0x408003fb, 0x03a11020, 0x401003fc, 0x403003fd,
dfe495d0
TI		 997};
998
999/*
1000 STAC 9200-32 pin configs for
1001 102801C2 (Dell Latitude D620)
1002 102801C8
1003 102801CC (Dell Latitude D820)
1004 102801D4
1005 102801D6
1006*/
1007static unsigned int dell9200_m22_pin_configs[8] = {
af6c016e
TI		 1008 0x40c003fa, 0x0144131f, 0x0321121f, 0x90170310,
1009 0x90a70321, 0x03a11020, 0x401003fb, 0x40f000fc,
dfe495d0
TI		 1010};
1011
1012/*
1013 STAC 9200-32 pin configs for
1014 102801CE (Dell XPS M1710)
1015 102801CF (Dell Precision M90)
1016*/
1017static unsigned int dell9200_m23_pin_configs[8] = {
1018 0x40c003fa, 0x01441340, 0x0421421f, 0x90170310,
1019 0x408003fb, 0x04a1102e, 0x90170311, 0x403003fc,
1020};
1021
1022/*
1023 STAC 9200-32 pin configs for
1024 102801C9
1025 102801CA
1026 102801CB (Dell Latitude 120L)
1027 102801D3
1028*/
1029static unsigned int dell9200_m24_pin_configs[8] = {
af6c016e
TI		 1030 0x40c003fa, 0x404003fb, 0x0321121f, 0x90170310,
1031 0x408003fc, 0x03a11020, 0x401003fd, 0x403003fe,
dfe495d0
TI		 1032};
1033
1034/*
1035 STAC 9200-32 pin configs for
1036 102801BD (Dell Inspiron E1505n)
1037 102801EE
1038 102801EF
1039*/
1040static unsigned int dell9200_m25_pin_configs[8] = {
af6c016e
TI		 1041 0x40c003fa, 0x01441340, 0x0421121f, 0x90170310,
1042 0x408003fb, 0x04a11020, 0x401003fc, 0x403003fd,
dfe495d0
TI		 1043};
1044
1045/*
1046 STAC 9200-32 pin configs for
1047 102801F5 (Dell Inspiron 1501)
1048 102801F6
1049*/
1050static unsigned int dell9200_m26_pin_configs[8] = {
af6c016e
TI		 1051 0x40c003fa, 0x404003fb, 0x0421121f, 0x90170310,
1052 0x408003fc, 0x04a11020, 0x401003fd, 0x403003fe,
dfe495d0
TI		 1053};
1054
1055/*
1056 STAC 9200-32
1057 102801CD (Dell Inspiron E1705/9400)
1058*/
1059static unsigned int dell9200_m27_pin_configs[8] = {
af6c016e
TI		 1060 0x40c003fa, 0x01441340, 0x0421121f, 0x90170310,
1061 0x90170310, 0x04a11020, 0x90170310, 0x40f003fc,
dfe495d0
TI		 1062};
1063
bf277785
TD		 1064static unsigned int oqo9200_pin_configs[8] = {
1065 0x40c000f0, 0x404000f1, 0x0221121f, 0x02211210,
1066 0x90170111, 0x90a70120, 0x400000f2, 0x400000f3,
1067};
1068
dfe495d0 1069
f5fcc13c
TI		 1070static unsigned int *stac9200_brd_tbl[STAC_9200_MODELS] = {
1071 [STAC_REF] = ref9200_pin_configs,
bf277785 1072 [STAC_9200_OQO] = oqo9200_pin_configs,
dfe495d0
TI		 1073 [STAC_9200_DELL_D21] = dell9200_d21_pin_configs,
1074 [STAC_9200_DELL_D22] = dell9200_d22_pin_configs,
1075 [STAC_9200_DELL_D23] = dell9200_d23_pin_configs,
1076 [STAC_9200_DELL_M21] = dell9200_m21_pin_configs,
1077 [STAC_9200_DELL_M22] = dell9200_m22_pin_configs,
1078 [STAC_9200_DELL_M23] = dell9200_m23_pin_configs,
1079 [STAC_9200_DELL_M24] = dell9200_m24_pin_configs,
1080 [STAC_9200_DELL_M25] = dell9200_m25_pin_configs,
1081 [STAC_9200_DELL_M26] = dell9200_m26_pin_configs,
1082 [STAC_9200_DELL_M27] = dell9200_m27_pin_configs,
403d1944
MP		 1083};
1084
f5fcc13c
TI		 1085static const char *stac9200_models[STAC_9200_MODELS] = {
1086 [STAC_REF] = "ref",
bf277785 1087 [STAC_9200_OQO] = "oqo",
dfe495d0
TI		 1088 [STAC_9200_DELL_D21] = "dell-d21",
1089 [STAC_9200_DELL_D22] = "dell-d22",
1090 [STAC_9200_DELL_D23] = "dell-d23",
1091 [STAC_9200_DELL_M21] = "dell-m21",
1092 [STAC_9200_DELL_M22] = "dell-m22",
1093 [STAC_9200_DELL_M23] = "dell-m23",
1094 [STAC_9200_DELL_M24] = "dell-m24",
1095 [STAC_9200_DELL_M25] = "dell-m25",
1096 [STAC_9200_DELL_M26] = "dell-m26",
1097 [STAC_9200_DELL_M27] = "dell-m27",
1194b5b7 1098 [STAC_9200_GATEWAY] = "gateway",
f5fcc13c
TI		 1099};
1100
1101static struct snd_pci_quirk stac9200_cfg_tbl[] = {
1102 /* SigmaTel reference board */
1103 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2668,
1104 "DFI LanParty", STAC_REF),
e7377071 1105 /* Dell laptops have BIOS problem */
dfe495d0
TI		 1106 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01a8,
1107 "unknown Dell", STAC_9200_DELL_D21),
f5fcc13c 1108 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01b5,
dfe495d0
TI		 1109 "Dell Inspiron 630m", STAC_9200_DELL_M21),
1110 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01bd,
1111 "Dell Inspiron E1505n", STAC_9200_DELL_M25),
1112 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01c0,
1113 "unknown Dell", STAC_9200_DELL_D22),
1114 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01c1,
1115 "unknown Dell", STAC_9200_DELL_D22),
f5fcc13c 1116 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01c2,
dfe495d0
TI		 1117 "Dell Latitude D620", STAC_9200_DELL_M22),
1118 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01c5,
1119 "unknown Dell", STAC_9200_DELL_D23),
1120 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01c7,
1121 "unknown Dell", STAC_9200_DELL_D23),
1122 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01c8,
1123 "unknown Dell", STAC_9200_DELL_M22),
1124 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01c9,
1125 "unknown Dell", STAC_9200_DELL_M24),
1126 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01ca,
1127 "unknown Dell", STAC_9200_DELL_M24),
f5fcc13c 1128 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01cb,
dfe495d0 1129 "Dell Latitude 120L", STAC_9200_DELL_M24),
877b866d 1130 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01cc,
dfe495d0 1131 "Dell Latitude D820", STAC_9200_DELL_M22),
46f02ca3 1132 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01cd,
dfe495d0 1133 "Dell Inspiron E1705/9400", STAC_9200_DELL_M27),
46f02ca3 1134 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01ce,
dfe495d0 1135 "Dell XPS M1710", STAC_9200_DELL_M23),
f0f96745 1136 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01cf,
dfe495d0
TI		 1137 "Dell Precision M90", STAC_9200_DELL_M23),
1138 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01d3,
1139 "unknown Dell", STAC_9200_DELL_M22),
1140 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01d4,
1141 "unknown Dell", STAC_9200_DELL_M22),
8286c53e 1142 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01d6,
dfe495d0 1143 "unknown Dell", STAC_9200_DELL_M22),
49c605db 1144 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01d8,
dfe495d0
TI		 1145 "Dell Inspiron 640m", STAC_9200_DELL_M21),
1146 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01d9,
1147 "unknown Dell", STAC_9200_DELL_D23),
1148 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01da,
1149 "unknown Dell", STAC_9200_DELL_D23),
1150 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01de,
1151 "unknown Dell", STAC_9200_DELL_D21),
1152 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01e3,
1153 "unknown Dell", STAC_9200_DELL_D23),
1154 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01e8,
1155 "unknown Dell", STAC_9200_DELL_D21),
1156 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01ee,
1157 "unknown Dell", STAC_9200_DELL_M25),
1158 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01ef,
1159 "unknown Dell", STAC_9200_DELL_M25),
49c605db 1160 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f5,
dfe495d0
TI		 1161 "Dell Inspiron 1501", STAC_9200_DELL_M26),
1162 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f6,
1163 "unknown Dell", STAC_9200_DELL_M26),
49c605db
TD		 1164 /* Panasonic */
1165 SND_PCI_QUIRK(0x10f7, 0x8338, "Panasonic CF-74", STAC_REF),
1194b5b7
TI		 1166 /* Gateway machines needs EAPD to be set on resume */
1167 SND_PCI_QUIRK(0x107b, 0x0205, "Gateway S-7110M", STAC_9200_GATEWAY),
1168 SND_PCI_QUIRK(0x107b, 0x0317, "Gateway MT3423, MX341*",
1169 STAC_9200_GATEWAY),
1170 SND_PCI_QUIRK(0x107b, 0x0318, "Gateway ML3019, MT3707",
1171 STAC_9200_GATEWAY),
bf277785
TD		 1172 /* OQO Mobile */
1173 SND_PCI_QUIRK(0x1106, 0x3288, "OQO Model 2", STAC_9200_OQO),
403d1944
MP		 1174 {} /* terminator */
1175};
1176
8e21c34c
TD		 1177static unsigned int ref925x_pin_configs[8] = {
1178 0x40c003f0, 0x424503f2, 0x01813022, 0x02a19021,
09a99959 1179 0x90a70320, 0x02214210, 0x01019020, 0x9033032e,
8e21c34c
TD		 1180};
1181
1182static unsigned int stac925x_MA6_pin_configs[8] = {
1183 0x40c003f0, 0x424503f2, 0x01813022, 0x02a19021,
1184 0x90a70320, 0x90100211, 0x400003f1, 0x9033032e,
1185};
1186
2c11f955
TD		 1187static unsigned int stac925x_PA6_pin_configs[8] = {
1188 0x40c003f0, 0x424503f2, 0x01813022, 0x02a19021,
1189 0x50a103f0, 0x90100211, 0x400003f1, 0x9033032e,
1190};
1191
8e21c34c 1192static unsigned int stac925xM2_2_pin_configs[8] = {
7353e14d
SL		 1193 0x40c003f3, 0x424503f2, 0x04180011, 0x02a19020,
1194 0x50a103f0, 0x90100212, 0x400003f1, 0x9033032e,
8e21c34c
TD		 1195};
1196
1197static unsigned int *stac925x_brd_tbl[STAC_925x_MODELS] = {
1198 [STAC_REF] = ref925x_pin_configs,
1199 [STAC_M2_2] = stac925xM2_2_pin_configs,
1200 [STAC_MA6] = stac925x_MA6_pin_configs,
2c11f955 1201 [STAC_PA6] = stac925x_PA6_pin_configs,
8e21c34c
TD		 1202};
1203
1204static const char *stac925x_models[STAC_925x_MODELS] = {
1205 [STAC_REF] = "ref",
1206 [STAC_M2_2] = "m2-2",
1207 [STAC_MA6] = "m6",
2c11f955 1208 [STAC_PA6] = "pa6",
8e21c34c
TD		 1209};
1210
1211static struct snd_pci_quirk stac925x_cfg_tbl[] = {
1212 /* SigmaTel reference board */
1213 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2668, "DFI LanParty", STAC_REF),
2c11f955 1214 SND_PCI_QUIRK(0x8384, 0x7632, "Stac9202 Reference Board", STAC_REF),
8e21c34c
TD		 1215 SND_PCI_QUIRK(0x107b, 0x0316, "Gateway M255", STAC_REF),
1216 SND_PCI_QUIRK(0x107b, 0x0366, "Gateway MP6954", STAC_REF),
1217 SND_PCI_QUIRK(0x107b, 0x0461, "Gateway NX560XL", STAC_MA6),
2c11f955 1218 SND_PCI_QUIRK(0x107b, 0x0681, "Gateway NX860", STAC_PA6),
8e21c34c
TD		 1219 SND_PCI_QUIRK(0x1002, 0x437b, "Gateway MX6453", STAC_M2_2),
1220 {} /* terminator */
1221};
1222
e1f0d669
MR		 1223static unsigned int ref92hd73xx_pin_configs[12] = {
1224 0x02214030, 0x02a19040, 0x01a19020, 0x02214030,
1225 0x0181302e, 0x01014010, 0x01014020, 0x01014030,
1226 0x02319040, 0x90a000f0, 0x90a000f0, 0x01452050,
1227};
1228
1229static unsigned int *stac92hd73xx_brd_tbl[STAC_92HD73XX_MODELS] = {
1230 [STAC_92HD73XX_REF] = ref92hd73xx_pin_configs,
1231};
1232
1233static const char *stac92hd73xx_models[STAC_92HD73XX_MODELS] = {
1234 [STAC_92HD73XX_REF] = "ref",
1235};
1236
1237static struct snd_pci_quirk stac92hd73xx_cfg_tbl[] = {
1238 /* SigmaTel reference board */
1239 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2668,
1240 "DFI LanParty", STAC_92HD73XX_REF),
1241 {} /* terminator */
1242};
1243
e035b841
MR		 1244static unsigned int ref92hd71bxx_pin_configs[10] = {
1245 0x02214030, 0x02a19040, 0x01a19020, 0x01014010,
b22b4821 1246 0x0181302e, 0x01114010, 0x01019020, 0x90a000f0,
e035b841
MR		 1247 0x90a000f0, 0x01452050,
1248};
1249
1250static unsigned int *stac92hd71bxx_brd_tbl[STAC_92HD71BXX_MODELS] = {
1251 [STAC_92HD71BXX_REF] = ref92hd71bxx_pin_configs,
1252};
1253
1254static const char *stac92hd71bxx_models[STAC_92HD71BXX_MODELS] = {
1255 [STAC_92HD71BXX_REF] = "ref",
1256};
1257
1258static struct snd_pci_quirk stac92hd71bxx_cfg_tbl[] = {
1259 /* SigmaTel reference board */
1260 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2668,
1261 "DFI LanParty", STAC_92HD71BXX_REF),
1262 {} /* terminator */
1263};
1264
403d1944
MP		 1265static unsigned int ref922x_pin_configs[10] = {
1266 0x01014010, 0x01016011, 0x01012012, 0x0221401f,
1267 0x01813122, 0x01011014, 0x01441030, 0x01c41030,
2f2f4251
M		 1268 0x40000100, 0x40000100,
1269};
1270
dfe495d0
TI		 1271/*
1272 STAC 922X pin configs for
1273 102801A7
1274 102801AB
1275 102801A9
1276 102801D1
1277 102801D2
1278*/
1279static unsigned int dell_922x_d81_pin_configs[10] = {
1280 0x02214030, 0x01a19021, 0x01111012, 0x01114010,
1281 0x02a19020, 0x01117011, 0x400001f0, 0x400001f1,
1282 0x01813122, 0x400001f2,
1283};
1284
1285/*
1286 STAC 922X pin configs for
1287 102801AC
1288 102801D0
1289*/
1290static unsigned int dell_922x_d82_pin_configs[10] = {
1291 0x02214030, 0x01a19021, 0x01111012, 0x01114010,
1292 0x02a19020, 0x01117011, 0x01451140, 0x400001f0,
1293 0x01813122, 0x400001f1,
1294};
1295
1296/*
1297 STAC 922X pin configs for
1298 102801BF
1299*/
1300static unsigned int dell_922x_m81_pin_configs[10] = {
1301 0x0321101f, 0x01112024, 0x01111222, 0x91174220,
1302 0x03a11050, 0x01116221, 0x90a70330, 0x01452340,
1303 0x40C003f1, 0x405003f0,
1304};
1305
1306/*
1307 STAC 9221 A1 pin configs for
1308 102801D7 (Dell XPS M1210)
1309*/
1310static unsigned int dell_922x_m82_pin_configs[10] = {
7f9310c1
JZ		 1311 0x02211211, 0x408103ff, 0x02a1123e, 0x90100310,
1312 0x408003f1, 0x0221121f, 0x03451340, 0x40c003f2,
dfe495d0
TI		 1313 0x508003f3, 0x405003f4,
1314};
1315
403d1944 1316static unsigned int d945gtp3_pin_configs[10] = {
869264c4 1317 0x0221401f, 0x01a19022, 0x01813021, 0x01014010,
403d1944
MP		 1318 0x40000100, 0x40000100, 0x40000100, 0x40000100,
1319 0x02a19120, 0x40000100,
1320};
1321
1322static unsigned int d945gtp5_pin_configs[10] = {
869264c4
MP		 1323 0x0221401f, 0x01011012, 0x01813024, 0x01014010,
1324 0x01a19021, 0x01016011, 0x01452130, 0x40000100,
403d1944
MP		 1325 0x02a19320, 0x40000100,
1326};
1327
5d5d3bc3
IZ		 1328static unsigned int intel_mac_v1_pin_configs[10] = {
1329 0x0121e21f, 0x400000ff, 0x9017e110, 0x400000fd,
1330 0x400000fe, 0x0181e020, 0x1145e030, 0x11c5e240,
1331 0x400000fc, 0x400000fb,
1332};
1333
1334static unsigned int intel_mac_v2_pin_configs[10] = {
1335 0x0121e21f, 0x90a7012e, 0x9017e110, 0x400000fd,
1336 0x400000fe, 0x0181e020, 0x1145e230, 0x500000fa,
1337 0x400000fc, 0x400000fb,
6f0778d8
NB		 1338};
1339
5d5d3bc3
IZ		 1340static unsigned int intel_mac_v3_pin_configs[10] = {
1341 0x0121e21f, 0x90a7012e, 0x9017e110, 0x400000fd,
1342 0x400000fe, 0x0181e020, 0x1145e230, 0x11c5e240,
3fc24d85
TI		 1343 0x400000fc, 0x400000fb,
1344};
1345
5d5d3bc3
IZ		 1346static unsigned int intel_mac_v4_pin_configs[10] = {
1347 0x0321e21f, 0x03a1e02e, 0x9017e110, 0x9017e11f,
1348 0x400000fe, 0x0381e020, 0x1345e230, 0x13c5e240,
f16928fb
SF		 1349 0x400000fc, 0x400000fb,
1350};
1351
5d5d3bc3
IZ		 1352static unsigned int intel_mac_v5_pin_configs[10] = {
1353 0x0321e21f, 0x03a1e02e, 0x9017e110, 0x9017e11f,
1354 0x400000fe, 0x0381e020, 0x1345e230, 0x13c5e240,
1355 0x400000fc, 0x400000fb,
0dae0f83
TI		 1356};
1357
76c08828 1358
19039bd0 1359static unsigned int *stac922x_brd_tbl[STAC_922X_MODELS] = {
f5fcc13c 1360 [STAC_D945_REF] = ref922x_pin_configs,
19039bd0
TI		 1361 [STAC_D945GTP3] = d945gtp3_pin_configs,
1362 [STAC_D945GTP5] = d945gtp5_pin_configs,
5d5d3bc3
IZ		 1363 [STAC_INTEL_MAC_V1] = intel_mac_v1_pin_configs,
1364 [STAC_INTEL_MAC_V2] = intel_mac_v2_pin_configs,
1365 [STAC_INTEL_MAC_V3] = intel_mac_v3_pin_configs,
1366 [STAC_INTEL_MAC_V4] = intel_mac_v4_pin_configs,
1367 [STAC_INTEL_MAC_V5] = intel_mac_v5_pin_configs,
dfe495d0 1368 /* for backward compatibility */
5d5d3bc3
IZ		 1369 [STAC_MACMINI] = intel_mac_v3_pin_configs,
1370 [STAC_MACBOOK] = intel_mac_v5_pin_configs,
1371 [STAC_MACBOOK_PRO_V1] = intel_mac_v3_pin_configs,
1372 [STAC_MACBOOK_PRO_V2] = intel_mac_v3_pin_configs,
1373 [STAC_IMAC_INTEL] = intel_mac_v2_pin_configs,
1374 [STAC_IMAC_INTEL_20] = intel_mac_v3_pin_configs,
dfe495d0
TI		 1375 [STAC_922X_DELL_D81] = dell_922x_d81_pin_configs,
1376 [STAC_922X_DELL_D82] = dell_922x_d82_pin_configs,
1377 [STAC_922X_DELL_M81] = dell_922x_m81_pin_configs,
1378 [STAC_922X_DELL_M82] = dell_922x_m82_pin_configs,
403d1944
MP		 1379};
1380
f5fcc13c
TI		 1381static const char *stac922x_models[STAC_922X_MODELS] = {
1382 [STAC_D945_REF] = "ref",
1383 [STAC_D945GTP5] = "5stack",
1384 [STAC_D945GTP3] = "3stack",
5d5d3bc3
IZ		 1385 [STAC_INTEL_MAC_V1] = "intel-mac-v1",
1386 [STAC_INTEL_MAC_V2] = "intel-mac-v2",
1387 [STAC_INTEL_MAC_V3] = "intel-mac-v3",
1388 [STAC_INTEL_MAC_V4] = "intel-mac-v4",
1389 [STAC_INTEL_MAC_V5] = "intel-mac-v5",
dfe495d0 1390 /* for backward compatibility */
f5fcc13c 1391 [STAC_MACMINI] = "macmini",
3fc24d85 1392 [STAC_MACBOOK] = "macbook",
6f0778d8
NB		 1393 [STAC_MACBOOK_PRO_V1] = "macbook-pro-v1",
1394 [STAC_MACBOOK_PRO_V2] = "macbook-pro",
f16928fb 1395 [STAC_IMAC_INTEL] = "imac-intel",
0dae0f83 1396 [STAC_IMAC_INTEL_20] = "imac-intel-20",
dfe495d0
TI		 1397 [STAC_922X_DELL_D81] = "dell-d81",
1398 [STAC_922X_DELL_D82] = "dell-d82",
1399 [STAC_922X_DELL_M81] = "dell-m81",
1400 [STAC_922X_DELL_M82] = "dell-m82",
f5fcc13c
TI		 1401};
1402
1403static struct snd_pci_quirk stac922x_cfg_tbl[] = {
1404 /* SigmaTel reference board */
1405 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2668,
1406 "DFI LanParty", STAC_D945_REF),
1407 /* Intel 945G based systems */
1408 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0101,
1409 "Intel D945G", STAC_D945GTP3),
1410 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0202,
1411 "Intel D945G", STAC_D945GTP3),
1412 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0606,
1413 "Intel D945G", STAC_D945GTP3),
1414 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0601,
1415 "Intel D945G", STAC_D945GTP3),
1416 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0111,
1417 "Intel D945G", STAC_D945GTP3),
1418 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x1115,
1419 "Intel D945G", STAC_D945GTP3),
1420 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x1116,
1421 "Intel D945G", STAC_D945GTP3),
1422 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x1117,
1423 "Intel D945G", STAC_D945GTP3),
1424 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x1118,
1425 "Intel D945G", STAC_D945GTP3),
1426 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x1119,
1427 "Intel D945G", STAC_D945GTP3),
1428 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x8826,
1429 "Intel D945G", STAC_D945GTP3),
1430 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x5049,
1431 "Intel D945G", STAC_D945GTP3),
1432 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x5055,
1433 "Intel D945G", STAC_D945GTP3),
1434 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x5048,
1435 "Intel D945G", STAC_D945GTP3),
1436 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0110,
1437 "Intel D945G", STAC_D945GTP3),
1438 /* Intel D945G 5-stack systems */
1439 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0404,
1440 "Intel D945G", STAC_D945GTP5),
1441 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0303,
1442 "Intel D945G", STAC_D945GTP5),
1443 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0013,
1444 "Intel D945G", STAC_D945GTP5),
1445 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0417,
1446 "Intel D945G", STAC_D945GTP5),
1447 /* Intel 945P based systems */
1448 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0b0b,
1449 "Intel D945P", STAC_D945GTP3),
1450 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0112,
1451 "Intel D945P", STAC_D945GTP3),
1452 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0d0d,
1453 "Intel D945P", STAC_D945GTP3),
1454 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0909,
1455 "Intel D945P", STAC_D945GTP3),
1456 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0505,
1457 "Intel D945P", STAC_D945GTP3),
1458 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x0707,
1459 "Intel D945P", STAC_D945GTP5),
1460 /* other systems */
1461 /* Apple Mac Mini (early 2006) */
1462 SND_PCI_QUIRK(0x8384, 0x7680,
5d5d3bc3 1463 "Mac Mini", STAC_INTEL_MAC_V3),
dfe495d0
TI		 1464 /* Dell systems */
1465 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01a7,
1466 "unknown Dell", STAC_922X_DELL_D81),
1467 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01a9,
1468 "unknown Dell", STAC_922X_DELL_D81),
1469 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01ab,
1470 "unknown Dell", STAC_922X_DELL_D81),
1471 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01ac,
1472 "unknown Dell", STAC_922X_DELL_D82),
1473 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01bf,
1474 "unknown Dell", STAC_922X_DELL_M81),
1475 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01d0,
1476 "unknown Dell", STAC_922X_DELL_D82),
1477 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01d1,
1478 "unknown Dell", STAC_922X_DELL_D81),
1479 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01d2,
1480 "unknown Dell", STAC_922X_DELL_D81),
1481 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01d7,
1482 "Dell XPS M1210", STAC_922X_DELL_M82),
403d1944
MP		 1483 {} /* terminator */
1484};
1485
3cc08dc6 1486static unsigned int ref927x_pin_configs[14] = {
93ed1503
TD		 1487 0x02214020, 0x02a19080, 0x0181304e, 0x01014010,
1488 0x01a19040, 0x01011012, 0x01016011, 0x0101201f,
1489 0x183301f0, 0x18a001f0, 0x18a001f0, 0x01442070,
1490 0x01c42190, 0x40000100,
3cc08dc6
MP		 1491};
1492
93ed1503 1493static unsigned int d965_3st_pin_configs[14] = {
81d3dbde
TD		 1494 0x0221401f, 0x02a19120, 0x40000100, 0x01014011,
1495 0x01a19021, 0x01813024, 0x40000100, 0x40000100,
1496 0x40000100, 0x40000100, 0x40000100, 0x40000100,
1497 0x40000100, 0x40000100
1498};
1499
93ed1503
TD		 1500static unsigned int d965_5st_pin_configs[14] = {
1501 0x02214020, 0x02a19080, 0x0181304e, 0x01014010,
1502 0x01a19040, 0x01011012, 0x01016011, 0x40000100,
1503 0x40000100, 0x40000100, 0x40000100, 0x01442070,
1504 0x40000100, 0x40000100
1505};
1506
4ff076e5
TD		 1507static unsigned int dell_3st_pin_configs[14] = {
1508 0x02211230, 0x02a11220, 0x01a19040, 0x01114210,
1509 0x01111212, 0x01116211, 0x01813050, 0x01112214,
8e9068b1 1510 0x403003fa, 0x90a60040, 0x90a60040, 0x404003fb,
4ff076e5
TD		 1511 0x40c003fc, 0x40000100
1512};
1513
93ed1503 1514static unsigned int *stac927x_brd_tbl[STAC_927X_MODELS] = {
8e9068b1
MR		 1515 [STAC_D965_REF] = ref927x_pin_configs,
1516 [STAC_D965_3ST] = d965_3st_pin_configs,
1517 [STAC_D965_5ST] = d965_5st_pin_configs,
1518 [STAC_DELL_3ST] = dell_3st_pin_configs,
1519 [STAC_DELL_BIOS] = NULL,
3cc08dc6
MP		 1520};
1521
f5fcc13c 1522static const char *stac927x_models[STAC_927X_MODELS] = {
8e9068b1
MR		 1523 [STAC_D965_REF] = "ref",
1524 [STAC_D965_3ST] = "3stack",
1525 [STAC_D965_5ST] = "5stack",
1526 [STAC_DELL_3ST] = "dell-3stack",
1527 [STAC_DELL_BIOS] = "dell-bios",
f5fcc13c
TI		 1528};
1529
1530static struct snd_pci_quirk stac927x_cfg_tbl[] = {
1531 /* SigmaTel reference board */
1532 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2668,
1533 "DFI LanParty", STAC_D965_REF),
81d3dbde 1534 /* Intel 946 based systems */
f5fcc13c
TI		 1535 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x3d01, "Intel D946", STAC_D965_3ST),
1536 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0xa301, "Intel D946", STAC_D965_3ST),
93ed1503 1537 /* 965 based 3 stack systems */
f5fcc13c
TI		 1538 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2116, "Intel D965", STAC_D965_3ST),
1539 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2115, "Intel D965", STAC_D965_3ST),
1540 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2114, "Intel D965", STAC_D965_3ST),
1541 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2113, "Intel D965", STAC_D965_3ST),
1542 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2112, "Intel D965", STAC_D965_3ST),
1543 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2111, "Intel D965", STAC_D965_3ST),
1544 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2110, "Intel D965", STAC_D965_3ST),
1545 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2009, "Intel D965", STAC_D965_3ST),
1546 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2008, "Intel D965", STAC_D965_3ST),
1547 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2007, "Intel D965", STAC_D965_3ST),
1548 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2006, "Intel D965", STAC_D965_3ST),
1549 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2005, "Intel D965", STAC_D965_3ST),
1550 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2004, "Intel D965", STAC_D965_3ST),
1551 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2003, "Intel D965", STAC_D965_3ST),
1552 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2002, "Intel D965", STAC_D965_3ST),
1553 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2001, "Intel D965", STAC_D965_3ST),
4ff076e5 1554 /* Dell 3 stack systems */
8e9068b1 1555 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f7, "Dell XPS M1730", STAC_DELL_3ST),
dfe495d0 1556 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01dd, "Dell Dimension E520", STAC_DELL_3ST),
4ff076e5
TD		 1557 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01ed, "Dell ", STAC_DELL_3ST),
1558 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f4, "Dell ", STAC_DELL_3ST),
8e9068b1 1559 /* Dell 3 stack systems with verb table in BIOS */
2f32d909
MR		 1560 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f3, "Dell Inspiron 1420", STAC_DELL_BIOS),
1561 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0227, "Dell Vostro 1400 ", STAC_DELL_BIOS),
8e9068b1
MR		 1562 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x022f, "Dell ", STAC_DELL_BIOS),
1563 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x022e, "Dell ", STAC_DELL_BIOS),
1564 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0242, "Dell ", STAC_DELL_BIOS),
1565 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0243, "Dell ", STAC_DELL_BIOS),
1566 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x02ff, "Dell ", STAC_DELL_BIOS),
1567 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0209, "Dell XPS 1330", STAC_DELL_BIOS),
93ed1503 1568 /* 965 based 5 stack systems */
f5fcc13c
TI		 1569 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2301, "Intel D965", STAC_D965_5ST),
1570 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2302, "Intel D965", STAC_D965_5ST),
1571 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2303, "Intel D965", STAC_D965_5ST),
1572 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2304, "Intel D965", STAC_D965_5ST),
1573 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2305, "Intel D965", STAC_D965_5ST),
1574 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2501, "Intel D965", STAC_D965_5ST),
1575 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2502, "Intel D965", STAC_D965_5ST),
1576 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2503, "Intel D965", STAC_D965_5ST),
1577 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2504, "Intel D965", STAC_D965_5ST),
3cc08dc6
MP		 1578 {} /* terminator */
1579};
1580
f3302a59
MP		 1581static unsigned int ref9205_pin_configs[12] = {
1582 0x40000100, 0x40000100, 0x01016011, 0x01014010,
09a99959 1583 0x01813122, 0x01a19021, 0x01019020, 0x40000100,
8b65727b 1584 0x90a000f0, 0x90a000f0, 0x01441030, 0x01c41030
f3302a59
MP		 1585};
1586
dfe495d0
TI		 1587/*
1588 STAC 9205 pin configs for
1589 102801F1
1590 102801F2
1591 102801FC
1592 102801FD
1593 10280204
1594 1028021F
3fa2ef74 1595 10280228 (Dell Vostro 1500)
dfe495d0
TI		 1596*/
1597static unsigned int dell_9205_m42_pin_configs[12] = {
1598 0x0321101F, 0x03A11020, 0x400003FA, 0x90170310,
1599 0x400003FB, 0x400003FC, 0x400003FD, 0x40F000F9,
1600 0x90A60330, 0x400003FF, 0x0144131F, 0x40C003FE,
1601};
1602
1603/*
1604 STAC 9205 pin configs for
1605 102801F9
1606 102801FA
1607 102801FE
1608 102801FF (Dell Precision M4300)
1609 10280206
1610 10280200
1611 10280201
1612*/
1613static unsigned int dell_9205_m43_pin_configs[12] = {
ae0a8ed8
TD		 1614 0x0321101f, 0x03a11020, 0x90a70330, 0x90170310,
1615 0x400000fe, 0x400000ff, 0x400000fd, 0x40f000f9,
1616 0x400000fa, 0x400000fc, 0x0144131f, 0x40c003f8,
1617};
1618
dfe495d0 1619static unsigned int dell_9205_m44_pin_configs[12] = {
ae0a8ed8
TD		 1620 0x0421101f, 0x04a11020, 0x400003fa, 0x90170310,
1621 0x400003fb, 0x400003fc, 0x400003fd, 0x400003f9,
1622 0x90a60330, 0x400003ff, 0x01441340, 0x40c003fe,
1623};
1624
f5fcc13c 1625static unsigned int *stac9205_brd_tbl[STAC_9205_MODELS] = {
ae0a8ed8 1626 [STAC_9205_REF] = ref9205_pin_configs,
dfe495d0
TI		 1627 [STAC_9205_DELL_M42] = dell_9205_m42_pin_configs,
1628 [STAC_9205_DELL_M43] = dell_9205_m43_pin_configs,
1629 [STAC_9205_DELL_M44] = dell_9205_m44_pin_configs,
f3302a59
MP		 1630};
1631
f5fcc13c
TI		 1632static const char *stac9205_models[STAC_9205_MODELS] = {
1633 [STAC_9205_REF] = "ref",
dfe495d0 1634 [STAC_9205_DELL_M42] = "dell-m42",
ae0a8ed8
TD		 1635 [STAC_9205_DELL_M43] = "dell-m43",
1636 [STAC_9205_DELL_M44] = "dell-m44",
f5fcc13c
TI		 1637};
1638
1639static struct snd_pci_quirk stac9205_cfg_tbl[] = {
1640 /* SigmaTel reference board */
1641 SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x2668,
1642 "DFI LanParty", STAC_9205_REF),
dfe495d0
TI		 1643 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f1,
1644 "unknown Dell", STAC_9205_DELL_M42),
1645 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f2,
1646 "unknown Dell", STAC_9205_DELL_M42),
ae0a8ed8 1647 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f8,
b44ef2f1
MR		 1648 "Dell Precision", STAC_9205_DELL_M43),
1649 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x021c,
1650 "Dell Precision", STAC_9205_DELL_M43),
ae0a8ed8
TD		 1651 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f9,
1652 "Dell Precision", STAC_9205_DELL_M43),
e45e459e
MR		 1653 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x021b,
1654 "Dell Precision", STAC_9205_DELL_M43),
ae0a8ed8
TD		 1655 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01fa,
1656 "Dell Precision", STAC_9205_DELL_M43),
dfe495d0
TI		 1657 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01fc,
1658 "unknown Dell", STAC_9205_DELL_M42),
1659 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01fd,
1660 "unknown Dell", STAC_9205_DELL_M42),
ae0a8ed8
TD		 1661 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01fe,
1662 "Dell Precision", STAC_9205_DELL_M43),
1663 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01ff,
dfe495d0 1664 "Dell Precision M4300", STAC_9205_DELL_M43),
ae0a8ed8
TD		 1665 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0206,
1666 "Dell Precision", STAC_9205_DELL_M43),
1667 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f1,
1668 "Dell Inspiron", STAC_9205_DELL_M44),
1669 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01f2,
1670 "Dell Inspiron", STAC_9205_DELL_M44),
1671 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01fc,
1672 "Dell Inspiron", STAC_9205_DELL_M44),
1673 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x01fd,
1674 "Dell Inspiron", STAC_9205_DELL_M44),
dfe495d0
TI		 1675 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0204,
1676 "unknown Dell", STAC_9205_DELL_M42),
ae0a8ed8
TD		 1677 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x021f,
1678 "Dell Inspiron", STAC_9205_DELL_M44),
3fa2ef74
MR		 1679 SND_PCI_QUIRK(PCI_VENDOR_ID_DELL, 0x0228,
1680 "Dell Vostro 1500", STAC_9205_DELL_M42),
f3302a59
MP		 1681 {} /* terminator */
1682};
1683
11b44bbd
RF		 1684static int stac92xx_save_bios_config_regs(struct hda_codec *codec)
1685{
1686 int i;
1687 struct sigmatel_spec *spec = codec->spec;
1688
1689 if (! spec->bios_pin_configs) {
1690 spec->bios_pin_configs = kcalloc(spec->num_pins,
1691 sizeof(*spec->bios_pin_configs), GFP_KERNEL);
1692 if (! spec->bios_pin_configs)
1693 return -ENOMEM;
1694 }
1695
1696 for (i = 0; i < spec->num_pins; i++) {
1697 hda_nid_t nid = spec->pin_nids[i];
1698 unsigned int pin_cfg;
1699
1700 pin_cfg = snd_hda_codec_read(codec, nid, 0,
1701 AC_VERB_GET_CONFIG_DEFAULT, 0x00);
1702 snd_printdd(KERN_INFO "hda_codec: pin nid %2.2x bios pin config %8.8x\n",
1703 nid, pin_cfg);
1704 spec->bios_pin_configs[i] = pin_cfg;
1705 }
1706
1707 return 0;
1708}
1709
87d48363
MR		 1710static void stac92xx_set_config_reg(struct hda_codec *codec,
1711 hda_nid_t pin_nid, unsigned int pin_config)
1712{
1713 int i;
1714 snd_hda_codec_write(codec, pin_nid, 0,
1715 AC_VERB_SET_CONFIG_DEFAULT_BYTES_0,
1716 pin_config & 0x000000ff);
1717 snd_hda_codec_write(codec, pin_nid, 0,
1718 AC_VERB_SET_CONFIG_DEFAULT_BYTES_1,
1719 (pin_config & 0x0000ff00) >> 8);
1720 snd_hda_codec_write(codec, pin_nid, 0,
1721 AC_VERB_SET_CONFIG_DEFAULT_BYTES_2,
1722 (pin_config & 0x00ff0000) >> 16);
1723 snd_hda_codec_write(codec, pin_nid, 0,
1724 AC_VERB_SET_CONFIG_DEFAULT_BYTES_3,
1725 pin_config >> 24);
1726 i = snd_hda_codec_read(codec, pin_nid, 0,
1727 AC_VERB_GET_CONFIG_DEFAULT,
1728 0x00);
1729 snd_printdd(KERN_INFO "hda_codec: pin nid %2.2x pin config %8.8x\n",
1730 pin_nid, i);
1731}
1732
2f2f4251
M		 1733static void stac92xx_set_config_regs(struct hda_codec *codec)
1734{
1735 int i;
1736 struct sigmatel_spec *spec = codec->spec;
2f2f4251 1737
87d48363
MR		 1738 if (!spec->pin_configs)
1739 return;
11b44bbd 1740
87d48363
MR		 1741 for (i = 0; i < spec->num_pins; i++)
1742 stac92xx_set_config_reg(codec, spec->pin_nids[i],
1743 spec->pin_configs[i]);
2f2f4251 1744}
2f2f4251 1745
dabbed6f 1746/*
c7d4b2fa 1747 * Analog playback callbacks
dabbed6f 1748 */
c7d4b2fa
M		 1749static int stac92xx_playback_pcm_open(struct hda_pcm_stream *hinfo,
1750 struct hda_codec *codec,
c8b6bf9b 1751 struct snd_pcm_substream *substream)
2f2f4251 1752{
dabbed6f 1753 struct sigmatel_spec *spec = codec->spec;
9a08160b
TI		 1754 return snd_hda_multi_out_analog_open(codec, &spec->multiout, substream,
1755 hinfo);
2f2f4251
M		 1756}
1757
2f2f4251
M		 1758static int stac92xx_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1759 struct hda_codec *codec,
1760 unsigned int stream_tag,
1761 unsigned int format,
c8b6bf9b 1762 struct snd_pcm_substream *substream)
2f2f4251
M		 1763{
1764 struct sigmatel_spec *spec = codec->spec;
403d1944 1765 return snd_hda_multi_out_analog_prepare(codec, &spec->multiout, stream_tag, format, substream);
2f2f4251
M		 1766}
1767
1768static int stac92xx_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1769 struct hda_codec *codec,
c8b6bf9b 1770 struct snd_pcm_substream *substream)
2f2f4251
M		 1771{
1772 struct sigmatel_spec *spec = codec->spec;
1773 return snd_hda_multi_out_analog_cleanup(codec, &spec->multiout);
1774}
1775
dabbed6f
M		 1776/*
1777 * Digital playback callbacks
1778 */
1779static int stac92xx_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
1780 struct hda_codec *codec,
c8b6bf9b 1781 struct snd_pcm_substream *substream)
dabbed6f
M		 1782{
1783 struct sigmatel_spec *spec = codec->spec;
1784 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
1785}
1786
1787static int stac92xx_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
1788 struct hda_codec *codec,
c8b6bf9b 1789 struct snd_pcm_substream *substream)
dabbed6f
M		 1790{
1791 struct sigmatel_spec *spec = codec->spec;
1792 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
1793}
1794
6b97eb45
TI		 1795static int stac92xx_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1796 struct hda_codec *codec,
1797 unsigned int stream_tag,
1798 unsigned int format,
1799 struct snd_pcm_substream *substream)
1800{
1801 struct sigmatel_spec *spec = codec->spec;
1802 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
1803 stream_tag, format, substream);
1804}
1805
dabbed6f 1806
2f2f4251
M		 1807/*
1808 * Analog capture callbacks
1809 */
1810static int stac92xx_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
1811 struct hda_codec *codec,
1812 unsigned int stream_tag,
1813 unsigned int format,
c8b6bf9b 1814 struct snd_pcm_substream *substream)
2f2f4251
M		 1815{
1816 struct sigmatel_spec *spec = codec->spec;
1817
1818 snd_hda_codec_setup_stream(codec, spec->adc_nids[substream->number],
1819 stream_tag, 0, format);
1820 return 0;
1821}
1822
1823static int stac92xx_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
1824 struct hda_codec *codec,
c8b6bf9b 1825 struct snd_pcm_substream *substream)
2f2f4251
M		 1826{
1827 struct sigmatel_spec *spec = codec->spec;
1828
1829 snd_hda_codec_setup_stream(codec, spec->adc_nids[substream->number], 0, 0, 0);
1830 return 0;
1831}
1832
dabbed6f
M		 1833static struct hda_pcm_stream stac92xx_pcm_digital_playback = {
1834 .substreams = 1,
1835 .channels_min = 2,
1836 .channels_max = 2,
1837 /* NID is set in stac92xx_build_pcms */
1838 .ops = {
1839 .open = stac92xx_dig_playback_pcm_open,
6b97eb45
TI		 1840 .close = stac92xx_dig_playback_pcm_close,
1841 .prepare = stac92xx_dig_playback_pcm_prepare
dabbed6f
M		 1842 },
1843};
1844
1845static struct hda_pcm_stream stac92xx_pcm_digital_capture = {
1846 .substreams = 1,
1847 .channels_min = 2,
1848 .channels_max = 2,
1849 /* NID is set in stac92xx_build_pcms */
1850};
1851
2f2f4251
M		 1852static struct hda_pcm_stream stac92xx_pcm_analog_playback = {
1853 .substreams = 1,
1854 .channels_min = 2,
c7d4b2fa 1855 .channels_max = 8,
2f2f4251
M		 1856 .nid = 0x02, /* NID to query formats and rates */
1857 .ops = {
1858 .open = stac92xx_playback_pcm_open,
1859 .prepare = stac92xx_playback_pcm_prepare,
1860 .cleanup = stac92xx_playback_pcm_cleanup
1861 },
1862};
1863
3cc08dc6
MP		 1864static struct hda_pcm_stream stac92xx_pcm_analog_alt_playback = {
1865 .substreams = 1,
1866 .channels_min = 2,
1867 .channels_max = 2,
1868 .nid = 0x06, /* NID to query formats and rates */
1869 .ops = {
1870 .open = stac92xx_playback_pcm_open,
1871 .prepare = stac92xx_playback_pcm_prepare,
1872 .cleanup = stac92xx_playback_pcm_cleanup
1873 },
1874};
1875
2f2f4251 1876static struct hda_pcm_stream stac92xx_pcm_analog_capture = {
2f2f4251
M		 1877 .channels_min = 2,
1878 .channels_max = 2,
9e05b7a3 1879 /* NID + .substreams is set in stac92xx_build_pcms */
2f2f4251
M		 1880 .ops = {
1881 .prepare = stac92xx_capture_pcm_prepare,
1882 .cleanup = stac92xx_capture_pcm_cleanup
1883 },
1884};
1885
1886static int stac92xx_build_pcms(struct hda_codec *codec)
1887{
1888 struct sigmatel_spec *spec = codec->spec;
1889 struct hda_pcm *info = spec->pcm_rec;
1890
1891 codec->num_pcms = 1;
1892 codec->pcm_info = info;
1893
c7d4b2fa 1894 info->name = "STAC92xx Analog";
2f2f4251 1895 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = stac92xx_pcm_analog_playback;
2f2f4251 1896 info->stream[SNDRV_PCM_STREAM_CAPTURE] = stac92xx_pcm_analog_capture;
3cc08dc6 1897 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adc_nids[0];
9e05b7a3 1898 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = spec->num_adcs;
3cc08dc6
MP		 1899
1900 if (spec->alt_switch) {
1901 codec->num_pcms++;
1902 info++;
1903 info->name = "STAC92xx Analog Alt";
1904 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = stac92xx_pcm_analog_alt_playback;
1905 }
2f2f4251 1906
dabbed6f
M		 1907 if (spec->multiout.dig_out_nid || spec->dig_in_nid) {
1908 codec->num_pcms++;
1909 info++;
1910 info->name = "STAC92xx Digital";
7ba72ba1 1911 info->pcm_type = HDA_PCM_TYPE_SPDIF;
dabbed6f
M		 1912 if (spec->multiout.dig_out_nid) {
1913 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = stac92xx_pcm_digital_playback;
1914 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->multiout.dig_out_nid;
1915 }
1916 if (spec->dig_in_nid) {
1917 info->stream[SNDRV_PCM_STREAM_CAPTURE] = stac92xx_pcm_digital_capture;
1918 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in_nid;
1919 }
1920 }
1921
2f2f4251
M		 1922 return 0;
1923}
1924
c960a03b
TI		 1925static unsigned int stac92xx_get_vref(struct hda_codec *codec, hda_nid_t nid)
1926{
1927 unsigned int pincap = snd_hda_param_read(codec, nid,
1928 AC_PAR_PIN_CAP);
1929 pincap = (pincap & AC_PINCAP_VREF) >> AC_PINCAP_VREF_SHIFT;
1930 if (pincap & AC_PINCAP_VREF_100)
1931 return AC_PINCTL_VREF_100;
1932 if (pincap & AC_PINCAP_VREF_80)
1933 return AC_PINCTL_VREF_80;
1934 if (pincap & AC_PINCAP_VREF_50)
1935 return AC_PINCTL_VREF_50;
1936 if (pincap & AC_PINCAP_VREF_GRD)
1937 return AC_PINCTL_VREF_GRD;
1938 return 0;
1939}
1940
403d1944
MP		 1941static void stac92xx_auto_set_pinctl(struct hda_codec *codec, hda_nid_t nid, int pin_type)
1942
1943{
82beb8fd
TI		 1944 snd_hda_codec_write_cache(codec, nid, 0,
1945 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_type);
403d1944
MP		 1946}
1947
a5ce8890 1948#define stac92xx_io_switch_info snd_ctl_boolean_mono_info
403d1944
MP		 1949
1950static int stac92xx_io_switch_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1951{
1952 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
1953 struct sigmatel_spec *spec = codec->spec;
1954 int io_idx = kcontrol-> private_value & 0xff;
1955
1956 ucontrol->value.integer.value[0] = spec->io_switch[io_idx];
1957 return 0;
1958}
1959
1960static int stac92xx_io_switch_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1961{
1962 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
1963 struct sigmatel_spec *spec = codec->spec;
1964 hda_nid_t nid = kcontrol->private_value >> 8;
1965 int io_idx = kcontrol-> private_value & 0xff;
68ea7b2f 1966 unsigned short val = !!ucontrol->value.integer.value[0];
403d1944
MP		 1967
1968 spec->io_switch[io_idx] = val;
1969
1970 if (val)
1971 stac92xx_auto_set_pinctl(codec, nid, AC_PINCTL_OUT_EN);
c960a03b
TI		 1972 else {
1973 unsigned int pinctl = AC_PINCTL_IN_EN;
1974 if (io_idx) /* set VREF for mic */
1975 pinctl |= stac92xx_get_vref(codec, nid);
1976 stac92xx_auto_set_pinctl(codec, nid, pinctl);
1977 }
40c1d308
JZ		 1978
1979 /* check the auto-mute again: we need to mute/unmute the speaker
1980 * appropriately according to the pin direction
1981 */
1982 if (spec->hp_detect)
1983 codec->patch_ops.unsol_event(codec, STAC_HP_EVENT << 26);
1984
403d1944
MP		 1985 return 1;
1986}
1987
0fb87bb4
ML		 1988#define stac92xx_clfe_switch_info snd_ctl_boolean_mono_info
1989
1990static int stac92xx_clfe_switch_get(struct snd_kcontrol *kcontrol,
1991 struct snd_ctl_elem_value *ucontrol)
1992{
1993 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
1994 struct sigmatel_spec *spec = codec->spec;
1995
1996 ucontrol->value.integer.value[0] = spec->clfe_swap;
1997 return 0;
1998}
1999
2000static int stac92xx_clfe_switch_put(struct snd_kcontrol *kcontrol,
2001 struct snd_ctl_elem_value *ucontrol)
2002{
2003 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2004 struct sigmatel_spec *spec = codec->spec;
2005 hda_nid_t nid = kcontrol->private_value & 0xff;
68ea7b2f 2006 unsigned int val = !!ucontrol->value.integer.value[0];
0fb87bb4 2007
68ea7b2f 2008 if (spec->clfe_swap == val)
0fb87bb4
ML		 2009 return 0;
2010
68ea7b2f 2011 spec->clfe_swap = val;
0fb87bb4
ML		 2012
2013 snd_hda_codec_write_cache(codec, nid, 0, AC_VERB_SET_EAPD_BTLENABLE,
2014 spec->clfe_swap ? 0x4 : 0x0);
2015
2016 return 1;
2017}
2018
403d1944
MP		 2019#define STAC_CODEC_IO_SWITCH(xname, xpval) \
2020 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2021 .name = xname, \
2022 .index = 0, \
2023 .info = stac92xx_io_switch_info, \
2024 .get = stac92xx_io_switch_get, \
2025 .put = stac92xx_io_switch_put, \
2026 .private_value = xpval, \
2027 }
2028
0fb87bb4
ML		 2029#define STAC_CODEC_CLFE_SWITCH(xname, xpval) \
2030 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2031 .name = xname, \
2032 .index = 0, \
2033 .info = stac92xx_clfe_switch_info, \
2034 .get = stac92xx_clfe_switch_get, \
2035 .put = stac92xx_clfe_switch_put, \
2036 .private_value = xpval, \
2037 }
403d1944 2038
c7d4b2fa
M		 2039enum {
2040 STAC_CTL_WIDGET_VOL,
2041 STAC_CTL_WIDGET_MUTE,
09a99959 2042 STAC_CTL_WIDGET_MONO_MUX,
403d1944 2043 STAC_CTL_WIDGET_IO_SWITCH,
0fb87bb4 2044 STAC_CTL_WIDGET_CLFE_SWITCH
c7d4b2fa
M		 2045};
2046
c8b6bf9b 2047static struct snd_kcontrol_new stac92xx_control_templates[] = {
c7d4b2fa
M		 2048 HDA_CODEC_VOLUME(NULL, 0, 0, 0),
2049 HDA_CODEC_MUTE(NULL, 0, 0, 0),
09a99959 2050 STAC_MONO_MUX,
403d1944 2051 STAC_CODEC_IO_SWITCH(NULL, 0),
0fb87bb4 2052 STAC_CODEC_CLFE_SWITCH(NULL, 0),
c7d4b2fa
M		 2053};
2054
2055/* add dynamic controls */
2056static int stac92xx_add_control(struct sigmatel_spec *spec, int type, const char *name, unsigned long val)
2057{
c8b6bf9b 2058 struct snd_kcontrol_new *knew;
c7d4b2fa
M		 2059
2060 if (spec->num_kctl_used >= spec->num_kctl_alloc) {
2061 int num = spec->num_kctl_alloc + NUM_CONTROL_ALLOC;
2062
2063 knew = kcalloc(num + 1, sizeof(*knew), GFP_KERNEL); /* array + terminator */
2064 if (! knew)
2065 return -ENOMEM;
2066 if (spec->kctl_alloc) {
2067 memcpy(knew, spec->kctl_alloc, sizeof(*knew) * spec->num_kctl_alloc);
2068 kfree(spec->kctl_alloc);
2069 }
2070 spec->kctl_alloc = knew;
2071 spec->num_kctl_alloc = num;
2072 }
2073
2074 knew = &spec->kctl_alloc[spec->num_kctl_used];
2075 *knew = stac92xx_control_templates[type];
82fe0c58 2076 knew->name = kstrdup(name, GFP_KERNEL);
c7d4b2fa
M		 2077 if (! knew->name)
2078 return -ENOMEM;
2079 knew->private_value = val;
2080 spec->num_kctl_used++;
2081 return 0;
2082}
2083
403d1944
MP		 2084/* flag inputs as additional dynamic lineouts */
2085static int stac92xx_add_dyn_out_pins(struct hda_codec *codec, struct auto_pin_cfg *cfg)
2086{
2087 struct sigmatel_spec *spec = codec->spec;
7b043899
SL		 2088 unsigned int wcaps, wtype;
2089 int i, num_dacs = 0;
2090
2091 /* use the wcaps cache to count all DACs available for line-outs */
2092 for (i = 0; i < codec->num_nodes; i++) {
2093 wcaps = codec->wcaps[i];
2094 wtype = (wcaps & AC_WCAP_TYPE) >> AC_WCAP_TYPE_SHIFT;
8e9068b1 2095
7b043899
SL		 2096 if (wtype == AC_WID_AUD_OUT && !(wcaps & AC_WCAP_DIGITAL))
2097 num_dacs++;
2098 }
403d1944 2099
7b043899
SL		 2100 snd_printdd("%s: total dac count=%d\n", __func__, num_dacs);
2101
403d1944
MP		 2102 switch (cfg->line_outs) {
2103 case 3:
2104 /* add line-in as side */
7b043899 2105 if (cfg->input_pins[AUTO_PIN_LINE] && num_dacs > 3) {
c480f79b
TI		 2106 cfg->line_out_pins[cfg->line_outs] =
2107 cfg->input_pins[AUTO_PIN_LINE];
403d1944
MP		 2108 spec->line_switch = 1;
2109 cfg->line_outs++;
2110 }
2111 break;
2112 case 2:
2113 /* add line-in as clfe and mic as side */
7b043899 2114 if (cfg->input_pins[AUTO_PIN_LINE] && num_dacs > 2) {
c480f79b
TI		 2115 cfg->line_out_pins[cfg->line_outs] =
2116 cfg->input_pins[AUTO_PIN_LINE];
403d1944
MP		 2117 spec->line_switch = 1;
2118 cfg->line_outs++;
2119 }
7b043899 2120 if (cfg->input_pins[AUTO_PIN_MIC] && num_dacs > 3) {
c480f79b
TI		 2121 cfg->line_out_pins[cfg->line_outs] =
2122 cfg->input_pins[AUTO_PIN_MIC];
403d1944
MP		 2123 spec->mic_switch = 1;
2124 cfg->line_outs++;
2125 }
2126 break;
2127 case 1:
2128 /* add line-in as surr and mic as clfe */
7b043899 2129 if (cfg->input_pins[AUTO_PIN_LINE] && num_dacs > 1) {
c480f79b
TI		 2130 cfg->line_out_pins[cfg->line_outs] =
2131 cfg->input_pins[AUTO_PIN_LINE];
403d1944
MP		 2132 spec->line_switch = 1;
2133 cfg->line_outs++;
2134 }
7b043899 2135 if (cfg->input_pins[AUTO_PIN_MIC] && num_dacs > 2) {
c480f79b
TI		 2136 cfg->line_out_pins[cfg->line_outs] =
2137 cfg->input_pins[AUTO_PIN_MIC];
403d1944
MP		 2138 spec->mic_switch = 1;
2139 cfg->line_outs++;
2140 }
2141 break;
2142 }
2143
2144 return 0;
2145}
2146
7b043899
SL		 2147
2148static int is_in_dac_nids(struct sigmatel_spec *spec, hda_nid_t nid)
2149{
2150 int i;
2151
2152 for (i = 0; i < spec->multiout.num_dacs; i++) {
2153 if (spec->multiout.dac_nids[i] == nid)
2154 return 1;
2155 }
2156
2157 return 0;
2158}
2159
3cc08dc6 2160/*
7b043899
SL		 2161 * Fill in the dac_nids table from the parsed pin configuration
2162 * This function only works when every pin in line_out_pins[]
2163 * contains atleast one DAC in its connection list. Some 92xx
2164 * codecs are not connected directly to a DAC, such as the 9200
2165 * and 9202/925x. For those, dac_nids[] must be hard-coded.
3cc08dc6 2166 */
19039bd0 2167static int stac92xx_auto_fill_dac_nids(struct hda_codec *codec,
df802952 2168 struct auto_pin_cfg *cfg)
c7d4b2fa
M		 2169{
2170 struct sigmatel_spec *spec = codec->spec;
7b043899
SL		 2171 int i, j, conn_len = 0;
2172 hda_nid_t nid, conn[HDA_MAX_CONNECTIONS];
2173 unsigned int wcaps, wtype;
2174
c7d4b2fa
M		 2175 for (i = 0; i < cfg->line_outs; i++) {
2176 nid = cfg->line_out_pins[i];
7b043899
SL		 2177 conn_len = snd_hda_get_connections(codec, nid, conn,
2178 HDA_MAX_CONNECTIONS);
2179 for (j = 0; j < conn_len; j++) {
2180 wcaps = snd_hda_param_read(codec, conn[j],
2181 AC_PAR_AUDIO_WIDGET_CAP);
2182 wtype = (wcaps & AC_WCAP_TYPE) >> AC_WCAP_TYPE_SHIFT;
7b043899
SL		 2183 if (wtype != AC_WID_AUD_OUT ||
2184 (wcaps & AC_WCAP_DIGITAL))
2185 continue;
2186 /* conn[j] is a DAC routed to this line-out */
2187 if (!is_in_dac_nids(spec, conn[j]))
2188 break;
2189 }
2190
2191 if (j == conn_len) {
df802952
TI		 2192 if (spec->multiout.num_dacs > 0) {
2193 /* we have already working output pins,
2194 * so let's drop the broken ones again
2195 */
2196 cfg->line_outs = spec->multiout.num_dacs;
2197 break;
2198 }
7b043899
SL		 2199 /* error out, no available DAC found */
2200 snd_printk(KERN_ERR
2201 "%s: No available DAC for pin 0x%x\n",
2202 __func__, nid);
2203 return -ENODEV;
2204 }
2205
2206 spec->multiout.dac_nids[i] = conn[j];
2207 spec->multiout.num_dacs++;
2208 if (conn_len > 1) {
2209 /* select this DAC in the pin's input mux */
82beb8fd
TI		 2210 snd_hda_codec_write_cache(codec, nid, 0,
2211 AC_VERB_SET_CONNECT_SEL, j);
c7d4b2fa 2212
7b043899
SL		 2213 }
2214 }
c7d4b2fa 2215
7b043899
SL		 2216 snd_printd("dac_nids=%d (0x%x/0x%x/0x%x/0x%x/0x%x)\n",
2217 spec->multiout.num_dacs,
2218 spec->multiout.dac_nids[0],
2219 spec->multiout.dac_nids[1],
2220 spec->multiout.dac_nids[2],
2221 spec->multiout.dac_nids[3],
2222 spec->multiout.dac_nids[4]);
c7d4b2fa
M		 2223 return 0;
2224}
2225
eb06ed8f
TI		 2226/* create volume control/switch for the given prefx type */
2227static int create_controls(struct sigmatel_spec *spec, const char *pfx, hda_nid_t nid, int chs)
2228{
2229 char name[32];
2230 int err;
2231
2232 sprintf(name, "%s Playback Volume", pfx);
2233 err = stac92xx_add_control(spec, STAC_CTL_WIDGET_VOL, name,
2234 HDA_COMPOSE_AMP_VAL(nid, chs, 0, HDA_OUTPUT));
2235 if (err < 0)
2236 return err;
2237 sprintf(name, "%s Playback Switch", pfx);
2238 err = stac92xx_add_control(spec, STAC_CTL_WIDGET_MUTE, name,
2239 HDA_COMPOSE_AMP_VAL(nid, chs, 0, HDA_OUTPUT));
2240 if (err < 0)
2241 return err;
2242 return 0;
2243}
2244
c7d4b2fa 2245/* add playback controls from the parsed DAC table */
0fb87bb4 2246static int stac92xx_auto_create_multi_out_ctls(struct hda_codec *codec,
19039bd0 2247 const struct auto_pin_cfg *cfg)
c7d4b2fa 2248{
19039bd0
TI		 2249 static const char *chname[4] = {
2250 "Front", "Surround", NULL /*CLFE*/, "Side"
2251 };
c7d4b2fa
M		 2252 hda_nid_t nid;
2253 int i, err;
2254
0fb87bb4 2255 struct sigmatel_spec *spec = codec->spec;
b5895dc8 2256 unsigned int wid_caps, pincap;
0fb87bb4
ML		 2257
2258
c7d4b2fa 2259 for (i = 0; i < cfg->line_outs; i++) {
403d1944 2260 if (!spec->multiout.dac_nids[i])
c7d4b2fa
M		 2261 continue;
2262
2263 nid = spec->multiout.dac_nids[i];
2264
2265 if (i == 2) {
2266 /* Center/LFE */
eb06ed8f
TI		 2267 err = create_controls(spec, "Center", nid, 1);
2268 if (err < 0)
c7d4b2fa 2269 return err;
eb06ed8f
TI		 2270 err = create_controls(spec, "LFE", nid, 2);
2271 if (err < 0)
c7d4b2fa 2272 return err;
0fb87bb4
ML		 2273
2274 wid_caps = get_wcaps(codec, nid);
2275
2276 if (wid_caps & AC_WCAP_LR_SWAP) {
2277 err = stac92xx_add_control(spec,
2278 STAC_CTL_WIDGET_CLFE_SWITCH,
2279 "Swap Center/LFE Playback Switch", nid);
2280
2281 if (err < 0)
2282 return err;
2283 }
2284
c7d4b2fa 2285 } else {
eb06ed8f
TI		 2286 err = create_controls(spec, chname[i], nid, 3);
2287 if (err < 0)
c7d4b2fa
M		 2288 return err;
2289 }
2290 }
2291
b5895dc8
MR		 2292 if (spec->line_switch) {
2293 nid = cfg->input_pins[AUTO_PIN_LINE];
2294 pincap = snd_hda_param_read(codec, nid,
2295 AC_PAR_PIN_CAP);
2296 if (pincap & AC_PINCAP_OUT) {
2297 err = stac92xx_add_control(spec,
2298 STAC_CTL_WIDGET_IO_SWITCH,
2299 "Line In as Output Switch", nid << 8);
2300 if (err < 0)
2301 return err;
2302 }
2303 }
403d1944 2304
b5895dc8 2305 if (spec->mic_switch) {
cace16f1 2306 unsigned int def_conf;
b5895dc8 2307 nid = cfg->input_pins[AUTO_PIN_MIC];
cace16f1
MR		 2308 def_conf = snd_hda_codec_read(codec, nid, 0,
2309 AC_VERB_GET_CONFIG_DEFAULT, 0);
2310
2311 /* some laptops have an internal analog microphone
2312 * which can't be used as a output */
2313 if (get_defcfg_connect(def_conf) != AC_JACK_PORT_FIXED) {
2314 pincap = snd_hda_param_read(codec, nid,
2315 AC_PAR_PIN_CAP);
2316 if (pincap & AC_PINCAP_OUT) {
2317 err = stac92xx_add_control(spec,
2318 STAC_CTL_WIDGET_IO_SWITCH,
2319 "Mic as Output Switch", (nid << 8) | 1);
2320 if (err < 0)
2321 return err;
2322 }
b5895dc8
MR		 2323 }
2324 }
403d1944 2325
c7d4b2fa
M		 2326 return 0;
2327}
2328
eb06ed8f 2329static int check_in_dac_nids(struct sigmatel_spec *spec, hda_nid_t nid)
c7d4b2fa 2330{
7b043899
SL		 2331 if (is_in_dac_nids(spec, nid))
2332 return 1;
eb06ed8f
TI		 2333 if (spec->multiout.hp_nid == nid)
2334 return 1;
2335 return 0;
2336}
c7d4b2fa 2337
eb06ed8f
TI		 2338static int add_spec_dacs(struct sigmatel_spec *spec, hda_nid_t nid)
2339{
2340 if (!spec->multiout.hp_nid)
2341 spec->multiout.hp_nid = nid;
2342 else if (spec->multiout.num_dacs > 4) {
2343 printk(KERN_WARNING "stac92xx: No space for DAC 0x%x\n", nid);
2344 return 1;
2345 } else {
2346 spec->multiout.dac_nids[spec->multiout.num_dacs] = nid;
2347 spec->multiout.num_dacs++;
2348 }
2349 return 0;
2350}
4e55096e 2351
eb06ed8f
TI		 2352/* add playback controls for Speaker and HP outputs */
2353static int stac92xx_auto_create_hp_ctls(struct hda_codec *codec,
2354 struct auto_pin_cfg *cfg)
2355{
2356 struct sigmatel_spec *spec = codec->spec;
2357 hda_nid_t nid;
2358 int i, old_num_dacs, err;
2359
2360 old_num_dacs = spec->multiout.num_dacs;
2361 for (i = 0; i < cfg->hp_outs; i++) {
2362 unsigned int wid_caps = get_wcaps(codec, cfg->hp_pins[i]);
2363 if (wid_caps & AC_WCAP_UNSOL_CAP)
2364 spec->hp_detect = 1;
2365 nid = snd_hda_codec_read(codec, cfg->hp_pins[i], 0,
2366 AC_VERB_GET_CONNECT_LIST, 0) & 0xff;
2367 if (check_in_dac_nids(spec, nid))
2368 nid = 0;
2369 if (! nid)
c7d4b2fa 2370 continue;
eb06ed8f
TI		 2371 add_spec_dacs(spec, nid);
2372 }
2373 for (i = 0; i < cfg->speaker_outs; i++) {
7b043899 2374 nid = snd_hda_codec_read(codec, cfg->speaker_pins[i], 0,
eb06ed8f
TI		 2375 AC_VERB_GET_CONNECT_LIST, 0) & 0xff;
2376 if (check_in_dac_nids(spec, nid))
2377 nid = 0;
eb06ed8f
TI		 2378 if (! nid)
2379 continue;
2380 add_spec_dacs(spec, nid);
c7d4b2fa 2381 }
1b290a51
MR		 2382 for (i = 0; i < cfg->line_outs; i++) {
2383 nid = snd_hda_codec_read(codec, cfg->line_out_pins[i], 0,
2384 AC_VERB_GET_CONNECT_LIST, 0) & 0xff;
2385 if (check_in_dac_nids(spec, nid))
2386 nid = 0;
2387 if (! nid)
2388 continue;
2389 add_spec_dacs(spec, nid);
2390 }
eb06ed8f
TI		 2391 for (i = old_num_dacs; i < spec->multiout.num_dacs; i++) {
2392 static const char *pfxs[] = {
2393 "Speaker", "External Speaker", "Speaker2",
2394 };
2395 err = create_controls(spec, pfxs[i - old_num_dacs],
2396 spec->multiout.dac_nids[i], 3);
2397 if (err < 0)
2398 return err;
2399 }
2400 if (spec->multiout.hp_nid) {
2401 const char *pfx;
6020c008 2402 if (old_num_dacs == spec->multiout.num_dacs)
eb06ed8f
TI		 2403 pfx = "Master";
2404 else
2405 pfx = "Headphone";
2406 err = create_controls(spec, pfx, spec->multiout.hp_nid, 3);
2407 if (err < 0)
2408 return err;
2409 }
c7d4b2fa
M		 2410
2411 return 0;
2412}
2413
b22b4821
MR		 2414/* labels for mono mux outputs */
2415static const char *stac92xx_mono_labels[3] = {
2416 "DAC0", "DAC1", "Mixer"
2417};
2418
2419/* create mono mux for mono out on capable codecs */
2420static int stac92xx_auto_create_mono_output_ctls(struct hda_codec *codec)
2421{
2422 struct sigmatel_spec *spec = codec->spec;
2423 struct hda_input_mux *mono_mux = &spec->private_mono_mux;
2424 int i, num_cons;
2425 hda_nid_t con_lst[ARRAY_SIZE(stac92xx_mono_labels)];
2426
2427 num_cons = snd_hda_get_connections(codec,
2428 spec->mono_nid,
2429 con_lst,
2430 HDA_MAX_NUM_INPUTS);
2431 if (!num_cons || num_cons > ARRAY_SIZE(stac92xx_mono_labels))
2432 return -EINVAL;
2433
2434 for (i = 0; i < num_cons; i++) {
2435 mono_mux->items[mono_mux->num_items].label =
2436 stac92xx_mono_labels[i];
2437 mono_mux->items[mono_mux->num_items].index = i;
2438 mono_mux->num_items++;
2439 }
09a99959
MR		 2440
2441 return stac92xx_add_control(spec, STAC_CTL_WIDGET_MONO_MUX,
2442 "Mono Mux", spec->mono_nid);
b22b4821
MR		 2443}
2444
8b65727b 2445/* labels for dmic mux inputs */
ddc2cec4 2446static const char *stac92xx_dmic_labels[5] = {
8b65727b
MP		 2447 "Analog Inputs", "Digital Mic 1", "Digital Mic 2",
2448 "Digital Mic 3", "Digital Mic 4"
2449};
2450
2451/* create playback/capture controls for input pins on dmic capable codecs */
2452static int stac92xx_auto_create_dmic_input_ctls(struct hda_codec *codec,
2453 const struct auto_pin_cfg *cfg)
2454{
2455 struct sigmatel_spec *spec = codec->spec;
2456 struct hda_input_mux *dimux = &spec->private_dimux;
2457 hda_nid_t con_lst[HDA_MAX_NUM_INPUTS];
0678accd
MR		 2458 int err, i, j;
2459 char name[32];
8b65727b
MP		 2460
2461 dimux->items[dimux->num_items].label = stac92xx_dmic_labels[0];
2462 dimux->items[dimux->num_items].index = 0;
2463 dimux->num_items++;
2464
2465 for (i = 0; i < spec->num_dmics; i++) {
0678accd 2466 hda_nid_t nid;
8b65727b
MP		 2467 int index;
2468 int num_cons;
0678accd 2469 unsigned int wcaps;
8b65727b
MP		 2470 unsigned int def_conf;
2471
2472 def_conf = snd_hda_codec_read(codec,
2473 spec->dmic_nids[i],
2474 0,
2475 AC_VERB_GET_CONFIG_DEFAULT,
2476 0);
2477 if (get_defcfg_connect(def_conf) == AC_JACK_PORT_NONE)
2478 continue;
2479
0678accd 2480 nid = spec->dmic_nids[i];
8b65727b 2481 num_cons = snd_hda_get_connections(codec,
e1f0d669 2482 spec->dmux_nids[0],
8b65727b
MP		 2483 con_lst,
2484 HDA_MAX_NUM_INPUTS);
2485 for (j = 0; j < num_cons; j++)
0678accd 2486 if (con_lst[j] == nid) {
8b65727b
MP		 2487 index = j;
2488 goto found;
2489 }
2490 continue;
2491found:
0678accd
MR		 2492 wcaps = get_wcaps(codec, nid);
2493
2494 if (wcaps & AC_WCAP_OUT_AMP) {
2495 sprintf(name, "%s Capture Volume",
2496 stac92xx_dmic_labels[dimux->num_items]);
2497
2498 err = stac92xx_add_control(spec,
2499 STAC_CTL_WIDGET_VOL,
2500 name,
2501 HDA_COMPOSE_AMP_VAL(nid, 3, 0, HDA_OUTPUT));
2502 if (err < 0)
2503 return err;
2504 }
2505
8b65727b
MP		 2506 dimux->items[dimux->num_items].label =
2507 stac92xx_dmic_labels[dimux->num_items];
2508 dimux->items[dimux->num_items].index = index;
2509 dimux->num_items++;
2510 }
2511
2512 return 0;
2513}
2514
c7d4b2fa
M		 2515/* create playback/capture controls for input pins */
2516static int stac92xx_auto_create_analog_input_ctls(struct hda_codec *codec, const struct auto_pin_cfg *cfg)
2517{
2518 struct sigmatel_spec *spec = codec->spec;
c7d4b2fa
M		 2519 struct hda_input_mux *imux = &spec->private_imux;
2520 hda_nid_t con_lst[HDA_MAX_NUM_INPUTS];
2521 int i, j, k;
2522
2523 for (i = 0; i < AUTO_PIN_LAST; i++) {
314634bc
TI		 2524 int index;
2525
2526 if (!cfg->input_pins[i])
2527 continue;
2528 index = -1;
2529 for (j = 0; j < spec->num_muxes; j++) {
2530 int num_cons;
2531 num_cons = snd_hda_get_connections(codec,
2532 spec->mux_nids[j],
2533 con_lst,
2534 HDA_MAX_NUM_INPUTS);
2535 for (k = 0; k < num_cons; k++)
2536 if (con_lst[k] == cfg->input_pins[i]) {
2537 index = k;
2538 goto found;
2539 }
c7d4b2fa 2540 }
314634bc
TI		 2541 continue;
2542 found:
2543 imux->items[imux->num_items].label = auto_pin_cfg_labels[i];
2544 imux->items[imux->num_items].index = index;
2545 imux->num_items++;
c7d4b2fa
M		 2546 }
2547
7b043899 2548 if (imux->num_items) {
62fe78e9
SR		 2549 /*
2550 * Set the current input for the muxes.
2551 * The STAC9221 has two input muxes with identical source
2552 * NID lists. Hopefully this won't get confused.
2553 */
2554 for (i = 0; i < spec->num_muxes; i++) {
82beb8fd
TI		 2555 snd_hda_codec_write_cache(codec, spec->mux_nids[i], 0,
2556 AC_VERB_SET_CONNECT_SEL,
2557 imux->items[0].index);
62fe78e9
SR		 2558 }
2559 }
2560
c7d4b2fa
M		 2561 return 0;
2562}
2563
c7d4b2fa
M		 2564static void stac92xx_auto_init_multi_out(struct hda_codec *codec)
2565{
2566 struct sigmatel_spec *spec = codec->spec;
2567 int i;
2568
2569 for (i = 0; i < spec->autocfg.line_outs; i++) {
2570 hda_nid_t nid = spec->autocfg.line_out_pins[i];
2571 stac92xx_auto_set_pinctl(codec, nid, AC_PINCTL_OUT_EN);
2572 }
2573}
2574
2575static void stac92xx_auto_init_hp_out(struct hda_codec *codec)
2576{
2577 struct sigmatel_spec *spec = codec->spec;
eb06ed8f 2578 int i;
c7d4b2fa 2579
eb06ed8f
TI		 2580 for (i = 0; i < spec->autocfg.hp_outs; i++) {
2581 hda_nid_t pin;
2582 pin = spec->autocfg.hp_pins[i];
2583 if (pin) /* connect to front */
2584 stac92xx_auto_set_pinctl(codec, pin, AC_PINCTL_OUT_EN | AC_PINCTL_HP_EN);
2585 }
2586 for (i = 0; i < spec->autocfg.speaker_outs; i++) {
2587 hda_nid_t pin;
2588 pin = spec->autocfg.speaker_pins[i];
2589 if (pin) /* connect to front */
2590 stac92xx_auto_set_pinctl(codec, pin, AC_PINCTL_OUT_EN);
2591 }
c7d4b2fa
M		 2592}
2593
3cc08dc6 2594static int stac92xx_parse_auto_config(struct hda_codec *codec, hda_nid_t dig_out, hda_nid_t dig_in)
c7d4b2fa
M		 2595{
2596 struct sigmatel_spec *spec = codec->spec;
2597 int err;
bcecd9bd 2598 int hp_speaker_swap = 0;
c7d4b2fa 2599
8b65727b
MP		 2600 if ((err = snd_hda_parse_pin_def_config(codec,
2601 &spec->autocfg,
2602 spec->dmic_nids)) < 0)
c7d4b2fa 2603 return err;
82bc955f 2604 if (! spec->autocfg.line_outs)
869264c4 2605 return 0; /* can't find valid pin config */
19039bd0 2606
bcecd9bd
JZ		 2607 /* If we have no real line-out pin and multiple hp-outs, HPs should
2608 * be set up as multi-channel outputs.
2609 */
2610 if (spec->autocfg.line_out_type == AUTO_PIN_SPEAKER_OUT &&
2611 spec->autocfg.hp_outs > 1) {
2612 /* Copy hp_outs to line_outs, backup line_outs in
2613 * speaker_outs so that the following routines can handle
2614 * HP pins as primary outputs.
2615 */
2616 memcpy(spec->autocfg.speaker_pins, spec->autocfg.line_out_pins,
2617 sizeof(spec->autocfg.line_out_pins));
2618 spec->autocfg.speaker_outs = spec->autocfg.line_outs;
2619 memcpy(spec->autocfg.line_out_pins, spec->autocfg.hp_pins,
2620 sizeof(spec->autocfg.hp_pins));
2621 spec->autocfg.line_outs = spec->autocfg.hp_outs;
2622 hp_speaker_swap = 1;
2623 }
09a99959
MR		 2624 if (spec->autocfg.mono_out_pin) {
2625 int dir = (get_wcaps(codec, spec->autocfg.mono_out_pin)
2626 & AC_WCAP_OUT_AMP) ? HDA_OUTPUT : HDA_INPUT;
2627 u32 caps = query_amp_caps(codec,
2628 spec->autocfg.mono_out_pin, dir);
2629 hda_nid_t conn_list[1];
2630
2631 /* get the mixer node and then the mono mux if it exists */
2632 if (snd_hda_get_connections(codec,
2633 spec->autocfg.mono_out_pin, conn_list, 1) &&
2634 snd_hda_get_connections(codec, conn_list[0],
2635 conn_list, 1)) {
2636
2637 int wcaps = get_wcaps(codec, conn_list[0]);
2638 int wid_type = (wcaps & AC_WCAP_TYPE)
2639 >> AC_WCAP_TYPE_SHIFT;
2640 /* LR swap check, some stac925x have a mux that
2641 * changes the DACs output path instead of the
2642 * mono-mux path.
2643 */
2644 if (wid_type == AC_WID_AUD_SEL &&
2645 !(wcaps & AC_WCAP_LR_SWAP))
2646 spec->mono_nid = conn_list[0];
2647 }
2648 /* all mono outs have a least a mute/unmute switch */
2649 err = stac92xx_add_control(spec, STAC_CTL_WIDGET_MUTE,
2650 "Mono Playback Switch",
2651 HDA_COMPOSE_AMP_VAL(spec->autocfg.mono_out_pin,
2652 1, 0, dir));
2653 if (err < 0)
2654 return err;
2655 /* check to see if there is volume support for the amp */
2656 if ((caps & AC_AMPCAP_NUM_STEPS) >> AC_AMPCAP_NUM_STEPS_SHIFT) {
2657 err = stac92xx_add_control(spec, STAC_CTL_WIDGET_VOL,
2658 "Mono Playback Volume",
2659 HDA_COMPOSE_AMP_VAL(spec->autocfg.mono_out_pin,
2660 1, 0, dir));
2661 if (err < 0)
2662 return err;
2663 }
2664
2665 stac92xx_auto_set_pinctl(codec, spec->autocfg.mono_out_pin,
2666 AC_PINCTL_OUT_EN);
2667 }
bcecd9bd 2668
403d1944
MP		 2669 if ((err = stac92xx_add_dyn_out_pins(codec, &spec->autocfg)) < 0)
2670 return err;
19039bd0
TI		 2671 if (spec->multiout.num_dacs == 0)
2672 if ((err = stac92xx_auto_fill_dac_nids(codec, &spec->autocfg)) < 0)
2673 return err;
c7d4b2fa 2674
0fb87bb4
ML		 2675 err = stac92xx_auto_create_multi_out_ctls(codec, &spec->autocfg);
2676
2677 if (err < 0)
2678 return err;
2679
bcecd9bd
JZ		 2680 if (hp_speaker_swap == 1) {
2681 /* Restore the hp_outs and line_outs */
2682 memcpy(spec->autocfg.hp_pins, spec->autocfg.line_out_pins,
2683 sizeof(spec->autocfg.line_out_pins));
2684 spec->autocfg.hp_outs = spec->autocfg.line_outs;
2685 memcpy(spec->autocfg.line_out_pins, spec->autocfg.speaker_pins,
2686 sizeof(spec->autocfg.speaker_pins));
2687 spec->autocfg.line_outs = spec->autocfg.speaker_outs;
2688 memset(spec->autocfg.speaker_pins, 0,
2689 sizeof(spec->autocfg.speaker_pins));
2690 spec->autocfg.speaker_outs = 0;
2691 }
2692
0fb87bb4
ML		 2693 err = stac92xx_auto_create_hp_ctls(codec, &spec->autocfg);
2694
2695 if (err < 0)
2696 return err;
2697
2698 err = stac92xx_auto_create_analog_input_ctls(codec, &spec->autocfg);
2699
2700 if (err < 0)
c7d4b2fa
M		 2701 return err;
2702
b22b4821
MR		 2703 if (spec->mono_nid > 0) {
2704 err = stac92xx_auto_create_mono_output_ctls(codec);
2705 if (err < 0)
2706 return err;
2707 }
2708
8b65727b
MP		 2709 if (spec->num_dmics > 0)
2710 if ((err = stac92xx_auto_create_dmic_input_ctls(codec,
2711 &spec->autocfg)) < 0)
2712 return err;
2713
c7d4b2fa 2714 spec->multiout.max_channels = spec->multiout.num_dacs * 2;
403d1944 2715 if (spec->multiout.max_channels > 2)
c7d4b2fa 2716 spec->surr_switch = 1;
c7d4b2fa 2717
82bc955f 2718 if (spec->autocfg.dig_out_pin)
3cc08dc6 2719 spec->multiout.dig_out_nid = dig_out;
82bc955f 2720 if (spec->autocfg.dig_in_pin)
3cc08dc6 2721 spec->dig_in_nid = dig_in;
c7d4b2fa
M		 2722
2723 if (spec->kctl_alloc)
2724 spec->mixers[spec->num_mixers++] = spec->kctl_alloc;
2725
2726 spec->input_mux = &spec->private_imux;
e1f0d669
MR		 2727 if (!spec->dinput_mux)
2728 spec->dinput_mux = &spec->private_dimux;
b22b4821 2729 spec->mono_mux = &spec->private_mono_mux;
c7d4b2fa
M		 2730
2731 return 1;
2732}
2733
82bc955f
TI		 2734/* add playback controls for HP output */
2735static int stac9200_auto_create_hp_ctls(struct hda_codec *codec,
2736 struct auto_pin_cfg *cfg)
2737{
2738 struct sigmatel_spec *spec = codec->spec;
eb06ed8f 2739 hda_nid_t pin = cfg->hp_pins[0];
82bc955f
TI		 2740 unsigned int wid_caps;
2741
2742 if (! pin)
2743 return 0;
2744
2745 wid_caps = get_wcaps(codec, pin);
505cb341 2746 if (wid_caps & AC_WCAP_UNSOL_CAP)
82bc955f 2747 spec->hp_detect = 1;
82bc955f
TI		 2748
2749 return 0;
2750}
2751
160ea0dc
RF		 2752/* add playback controls for LFE output */
2753static int stac9200_auto_create_lfe_ctls(struct hda_codec *codec,
2754 struct auto_pin_cfg *cfg)
2755{
2756 struct sigmatel_spec *spec = codec->spec;
2757 int err;
2758 hda_nid_t lfe_pin = 0x0;
2759 int i;
2760
2761 /*
2762 * search speaker outs and line outs for a mono speaker pin
2763 * with an amp. If one is found, add LFE controls
2764 * for it.
2765 */
2766 for (i = 0; i < spec->autocfg.speaker_outs && lfe_pin == 0x0; i++) {
2767 hda_nid_t pin = spec->autocfg.speaker_pins[i];
2768 unsigned long wcaps = get_wcaps(codec, pin);
2769 wcaps &= (AC_WCAP_STEREO | AC_WCAP_OUT_AMP);
2770 if (wcaps == AC_WCAP_OUT_AMP)
2771 /* found a mono speaker with an amp, must be lfe */
2772 lfe_pin = pin;
2773 }
2774
2775 /* if speaker_outs is 0, then speakers may be in line_outs */
2776 if (lfe_pin == 0 && spec->autocfg.speaker_outs == 0) {
2777 for (i = 0; i < spec->autocfg.line_outs && lfe_pin == 0x0; i++) {
2778 hda_nid_t pin = spec->autocfg.line_out_pins[i];
2779 unsigned long cfg;
2780 cfg = snd_hda_codec_read(codec, pin, 0,
2781 AC_VERB_GET_CONFIG_DEFAULT,
2782 0x00);
2783 if (get_defcfg_device(cfg) == AC_JACK_SPEAKER) {
2784 unsigned long wcaps = get_wcaps(codec, pin);
2785 wcaps &= (AC_WCAP_STEREO | AC_WCAP_OUT_AMP);
2786 if (wcaps == AC_WCAP_OUT_AMP)
2787 /* found a mono speaker with an amp,
2788 must be lfe */
2789 lfe_pin = pin;
2790 }
2791 }
2792 }
2793
2794 if (lfe_pin) {
eb06ed8f 2795 err = create_controls(spec, "LFE", lfe_pin, 1);
160ea0dc
RF		 2796 if (err < 0)
2797 return err;
2798 }
2799
2800 return 0;
2801}
2802
c7d4b2fa
M		 2803static int stac9200_parse_auto_config(struct hda_codec *codec)
2804{
2805 struct sigmatel_spec *spec = codec->spec;
2806 int err;
2807
df694daa 2808 if ((err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL)) < 0)
c7d4b2fa
M		 2809 return err;
2810
2811 if ((err = stac92xx_auto_create_analog_input_ctls(codec, &spec->autocfg)) < 0)
2812 return err;
2813
82bc955f
TI		 2814 if ((err = stac9200_auto_create_hp_ctls(codec, &spec->autocfg)) < 0)
2815 return err;
2816
160ea0dc
RF		 2817 if ((err = stac9200_auto_create_lfe_ctls(codec, &spec->autocfg)) < 0)
2818 return err;
2819
82bc955f 2820 if (spec->autocfg.dig_out_pin)
c7d4b2fa 2821 spec->multiout.dig_out_nid = 0x05;
82bc955f 2822 if (spec->autocfg.dig_in_pin)
c7d4b2fa 2823 spec->dig_in_nid = 0x04;
c7d4b2fa
M		 2824
2825 if (spec->kctl_alloc)
2826 spec->mixers[spec->num_mixers++] = spec->kctl_alloc;
2827
2828 spec->input_mux = &spec->private_imux;
8b65727b 2829 spec->dinput_mux = &spec->private_dimux;
c7d4b2fa
M		 2830
2831 return 1;
2832}
2833
62fe78e9
SR		 2834/*
2835 * Early 2006 Intel Macintoshes with STAC9220X5 codecs seem to have a
2836 * funky external mute control using GPIO pins.
2837 */
2838
76e1ddfb 2839static void stac_gpio_set(struct hda_codec *codec, unsigned int mask,
4fe5195c 2840 unsigned int dir_mask, unsigned int data)
62fe78e9
SR		 2841{
2842 unsigned int gpiostate, gpiomask, gpiodir;
2843
2844 gpiostate = snd_hda_codec_read(codec, codec->afg, 0,
2845 AC_VERB_GET_GPIO_DATA, 0);
4fe5195c 2846 gpiostate = (gpiostate & ~dir_mask) | (data & dir_mask);
62fe78e9
SR		 2847
2848 gpiomask = snd_hda_codec_read(codec, codec->afg, 0,
2849 AC_VERB_GET_GPIO_MASK, 0);
76e1ddfb 2850 gpiomask |= mask;
62fe78e9
SR		 2851
2852 gpiodir = snd_hda_codec_read(codec, codec->afg, 0,
2853 AC_VERB_GET_GPIO_DIRECTION, 0);
4fe5195c 2854 gpiodir |= dir_mask;
62fe78e9 2855
76e1ddfb 2856 /* Configure GPIOx as CMOS */
62fe78e9
SR		 2857 snd_hda_codec_write(codec, codec->afg, 0, 0x7e7, 0);
2858
2859 snd_hda_codec_write(codec, codec->afg, 0,
2860 AC_VERB_SET_GPIO_MASK, gpiomask);
76e1ddfb
TI		 2861 snd_hda_codec_read(codec, codec->afg, 0,
2862 AC_VERB_SET_GPIO_DIRECTION, gpiodir); /* sync */
62fe78e9
SR		 2863
2864 msleep(1);
2865
76e1ddfb
TI		 2866 snd_hda_codec_read(codec, codec->afg, 0,
2867 AC_VERB_SET_GPIO_DATA, gpiostate); /* sync */
62fe78e9
SR		 2868}
2869
314634bc
TI		 2870static void enable_pin_detect(struct hda_codec *codec, hda_nid_t nid,
2871 unsigned int event)
2872{
2873 if (get_wcaps(codec, nid) & AC_WCAP_UNSOL_CAP)
dc81bed1
TI		 2874 snd_hda_codec_write_cache(codec, nid, 0,
2875 AC_VERB_SET_UNSOLICITED_ENABLE,
2876 (AC_USRSP_EN | event));
314634bc
TI		 2877}
2878
a64135a2
MR		 2879static int is_nid_hp_pin(struct auto_pin_cfg *cfg, hda_nid_t nid)
2880{
2881 int i;
2882 for (i = 0; i < cfg->hp_outs; i++)
2883 if (cfg->hp_pins[i] == nid)
2884 return 1; /* nid is a HP-Out */
2885
2886 return 0; /* nid is not a HP-Out */
2887};
2888
b76c850f
MR		 2889static void stac92xx_power_down(struct hda_codec *codec)
2890{
2891 struct sigmatel_spec *spec = codec->spec;
2892
2893 /* power down inactive DACs */
2894 hda_nid_t *dac;
2895 for (dac = spec->dac_list; *dac; dac++)
2896 if (!is_in_dac_nids(spec, *dac))
2897 snd_hda_codec_write_cache(codec, *dac, 0,
2898 AC_VERB_SET_POWER_STATE, AC_PWRST_D3);
2899}
2900
c7d4b2fa
M		 2901static int stac92xx_init(struct hda_codec *codec)
2902{
2903 struct sigmatel_spec *spec = codec->spec;
82bc955f
TI		 2904 struct auto_pin_cfg *cfg = &spec->autocfg;
2905 int i;
c7d4b2fa 2906
c7d4b2fa
M		 2907 snd_hda_sequence_write(codec, spec->init);
2908
82bc955f
TI		 2909 /* set up pins */
2910 if (spec->hp_detect) {
505cb341 2911 /* Enable unsolicited responses on the HP widget */
eb06ed8f 2912 for (i = 0; i < cfg->hp_outs; i++)
314634bc
TI		 2913 enable_pin_detect(codec, cfg->hp_pins[i],
2914 STAC_HP_EVENT);
0a07acaf
TI		 2915 /* force to enable the first line-out; the others are set up
2916 * in unsol_event
2917 */
2918 stac92xx_auto_set_pinctl(codec, spec->autocfg.line_out_pins[0],
2919 AC_PINCTL_OUT_EN);
eb995a8c 2920 stac92xx_auto_init_hp_out(codec);
82bc955f
TI		 2921 /* fake event to set up pins */
2922 codec->patch_ops.unsol_event(codec, STAC_HP_EVENT << 26);
2923 } else {
2924 stac92xx_auto_init_multi_out(codec);
2925 stac92xx_auto_init_hp_out(codec);
2926 }
2927 for (i = 0; i < AUTO_PIN_LAST; i++) {
c960a03b
TI		 2928 hda_nid_t nid = cfg->input_pins[i];
2929 if (nid) {
2930 unsigned int pinctl = AC_PINCTL_IN_EN;
2931 if (i == AUTO_PIN_MIC || i == AUTO_PIN_FRONT_MIC)
2932 pinctl |= stac92xx_get_vref(codec, nid);
2933 stac92xx_auto_set_pinctl(codec, nid, pinctl);
2934 }
82bc955f 2935 }
a64135a2
MR		 2936 for (i = 0; i < spec->num_dmics; i++)
2937 stac92xx_auto_set_pinctl(codec, spec->dmic_nids[i],
2938 AC_PINCTL_IN_EN);
2939 for (i = 0; i < spec->num_pwrs; i++) {
2940 int event = is_nid_hp_pin(cfg, spec->pwr_nids[i])
2941 ? STAC_HP_EVENT : STAC_PWR_EVENT;
2942 int pinctl = snd_hda_codec_read(codec, spec->pwr_nids[i],
2943 0, AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2944 /* outputs are only ports capable of power management
2945 * any attempts on powering down a input port cause the
2946 * referenced VREF to act quirky.
2947 */
2948 if (pinctl & AC_PINCTL_IN_EN)
2949 continue;
2950 enable_pin_detect(codec, spec->pwr_nids[i], event | i);
2951 codec->patch_ops.unsol_event(codec, (event | i) << 26);
2952 }
b76c850f
MR		 2953 if (spec->dac_list)
2954 stac92xx_power_down(codec);
82bc955f
TI		 2955 if (cfg->dig_out_pin)
2956 stac92xx_auto_set_pinctl(codec, cfg->dig_out_pin,
2957 AC_PINCTL_OUT_EN);
2958 if (cfg->dig_in_pin)
2959 stac92xx_auto_set_pinctl(codec, cfg->dig_in_pin,
2960 AC_PINCTL_IN_EN);
2961
4fe5195c
MR		 2962 stac_gpio_set(codec, spec->gpio_mask,
2963 spec->gpio_dir, spec->gpio_data);
62fe78e9 2964
c7d4b2fa
M		 2965 return 0;
2966}
2967
2f2f4251
M		 2968static void stac92xx_free(struct hda_codec *codec)
2969{
c7d4b2fa
M		 2970 struct sigmatel_spec *spec = codec->spec;
2971 int i;
2972
2973 if (! spec)
2974 return;
2975
2976 if (spec->kctl_alloc) {
2977 for (i = 0; i < spec->num_kctl_used; i++)
2978 kfree(spec->kctl_alloc[i].name);
2979 kfree(spec->kctl_alloc);
2980 }
2981
11b44bbd
RF		 2982 if (spec->bios_pin_configs)
2983 kfree(spec->bios_pin_configs);
2984
c7d4b2fa 2985 kfree(spec);
2f2f4251
M		 2986}
2987
4e55096e
M		 2988static void stac92xx_set_pinctl(struct hda_codec *codec, hda_nid_t nid,
2989 unsigned int flag)
2990{
2991 unsigned int pin_ctl = snd_hda_codec_read(codec, nid,
2992 0, AC_VERB_GET_PIN_WIDGET_CONTROL, 0x00);
7b043899 2993
f9acba43
TI		 2994 if (pin_ctl & AC_PINCTL_IN_EN) {
2995 /*
2996 * we need to check the current set-up direction of
2997 * shared input pins since they can be switched via
2998 * "xxx as Output" mixer switch
2999 */
3000 struct sigmatel_spec *spec = codec->spec;
3001 struct auto_pin_cfg *cfg = &spec->autocfg;
3002 if ((nid == cfg->input_pins[AUTO_PIN_LINE] &&
3003 spec->line_switch) ||
3004 (nid == cfg->input_pins[AUTO_PIN_MIC] &&
3005 spec->mic_switch))
3006 return;
3007 }
3008
7b043899
SL		 3009 /* if setting pin direction bits, clear the current
3010 direction bits first */
3011 if (flag & (AC_PINCTL_IN_EN | AC_PINCTL_OUT_EN))
3012 pin_ctl &= ~(AC_PINCTL_IN_EN | AC_PINCTL_OUT_EN);
3013
82beb8fd 3014 snd_hda_codec_write_cache(codec, nid, 0,
4e55096e
M		 3015 AC_VERB_SET_PIN_WIDGET_CONTROL,
3016 pin_ctl | flag);
3017}
3018
3019static void stac92xx_reset_pinctl(struct hda_codec *codec, hda_nid_t nid,
3020 unsigned int flag)
3021{
3022 unsigned int pin_ctl = snd_hda_codec_read(codec, nid,
3023 0, AC_VERB_GET_PIN_WIDGET_CONTROL, 0x00);
82beb8fd 3024 snd_hda_codec_write_cache(codec, nid, 0,
4e55096e
M		 3025 AC_VERB_SET_PIN_WIDGET_CONTROL,
3026 pin_ctl & ~flag);
3027}
3028
40c1d308 3029static int get_hp_pin_presence(struct hda_codec *codec, hda_nid_t nid)
314634bc
TI		 3030{
3031 if (!nid)
3032 return 0;
3033 if (snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_PIN_SENSE, 0x00)
40c1d308
JZ		 3034 & (1 << 31)) {
3035 unsigned int pinctl;
3036 pinctl = snd_hda_codec_read(codec, nid, 0,
3037 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3038 if (pinctl & AC_PINCTL_IN_EN)
3039 return 0; /* mic- or line-input */
3040 else
3041 return 1; /* HP-output */
3042 }
314634bc
TI		 3043 return 0;
3044}
3045
3046static void stac92xx_hp_detect(struct hda_codec *codec, unsigned int res)
4e55096e
M		 3047{
3048 struct sigmatel_spec *spec = codec->spec;
3049 struct auto_pin_cfg *cfg = &spec->autocfg;
3050 int i, presence;
3051
eb06ed8f 3052 presence = 0;
4fe5195c
MR		 3053 if (spec->gpio_mute)
3054 presence = !(snd_hda_codec_read(codec, codec->afg, 0,
3055 AC_VERB_GET_GPIO_DATA, 0) & spec->gpio_mute);
3056
eb06ed8f 3057 for (i = 0; i < cfg->hp_outs; i++) {
314634bc
TI		 3058 if (presence)
3059 break;
4fe5195c 3060 presence = get_hp_pin_presence(codec, cfg->hp_pins[i]);
eb06ed8f 3061 }
4e55096e
M		 3062
3063 if (presence) {
3064 /* disable lineouts, enable hp */
3065 for (i = 0; i < cfg->line_outs; i++)
3066 stac92xx_reset_pinctl(codec, cfg->line_out_pins[i],
3067 AC_PINCTL_OUT_EN);
eb06ed8f
TI		 3068 for (i = 0; i < cfg->speaker_outs; i++)
3069 stac92xx_reset_pinctl(codec, cfg->speaker_pins[i],
3070 AC_PINCTL_OUT_EN);
4e55096e
M		 3071 } else {
3072 /* enable lineouts, disable hp */
3073 for (i = 0; i < cfg->line_outs; i++)
3074 stac92xx_set_pinctl(codec, cfg->line_out_pins[i],
3075 AC_PINCTL_OUT_EN);
eb06ed8f
TI		 3076 for (i = 0; i < cfg->speaker_outs; i++)
3077 stac92xx_set_pinctl(codec, cfg->speaker_pins[i],
3078 AC_PINCTL_OUT_EN);
4e55096e
M		 3079 }
3080}
3081
a64135a2
MR		 3082static void stac92xx_pin_sense(struct hda_codec *codec, int idx)
3083{
3084 struct sigmatel_spec *spec = codec->spec;
3085 hda_nid_t nid = spec->pwr_nids[idx];
3086 int presence, val;
3087 val = snd_hda_codec_read(codec, codec->afg, 0, 0x0fec, 0x0)
3088 & 0x000000ff;
3089 presence = get_hp_pin_presence(codec, nid);
3090 idx = 1 << idx;
3091
3092 if (presence)
3093 val &= ~idx;
3094 else
3095 val |= idx;
3096
3097 /* power down unused output ports */
3098 snd_hda_codec_write(codec, codec->afg, 0, 0x7ec, val);
3099};
3100
314634bc
TI		 3101static void stac92xx_unsol_event(struct hda_codec *codec, unsigned int res)
3102{
a64135a2
MR		 3103 struct sigmatel_spec *spec = codec->spec;
3104 int idx = res >> 26 & 0x0f;
3105
3106 switch ((res >> 26) & 0x30) {
314634bc
TI		 3107 case STAC_HP_EVENT:
3108 stac92xx_hp_detect(codec, res);
a64135a2
MR		 3109 /* fallthru */
3110 case STAC_PWR_EVENT:
3111 if (spec->num_pwrs > 0)
3112 stac92xx_pin_sense(codec, idx);
314634bc
TI		 3113 }
3114}
3115
cb53c626 3116#ifdef SND_HDA_NEEDS_RESUME
ff6fdc37
M		 3117static int stac92xx_resume(struct hda_codec *codec)
3118{
dc81bed1
TI		 3119 struct sigmatel_spec *spec = codec->spec;
3120
11b44bbd 3121 stac92xx_set_config_regs(codec);
dc81bed1 3122 snd_hda_sequence_write(codec, spec->init);
4fe5195c
MR		 3123 stac_gpio_set(codec, spec->gpio_mask,
3124 spec->gpio_dir, spec->gpio_data);
82beb8fd
TI		 3125 snd_hda_codec_resume_amp(codec);
3126 snd_hda_codec_resume_cache(codec);
b76c850f
MR		 3127 /* power down inactive DACs */
3128 if (spec->dac_list)
3129 stac92xx_power_down(codec);
dc81bed1
TI		 3130 /* invoke unsolicited event to reset the HP state */
3131 if (spec->hp_detect)
3132 codec->patch_ops.unsol_event(codec, STAC_HP_EVENT << 26);
ff6fdc37
M		 3133 return 0;
3134}
3135#endif
3136
2f2f4251
M		 3137static struct hda_codec_ops stac92xx_patch_ops = {
3138 .build_controls = stac92xx_build_controls,
3139 .build_pcms = stac92xx_build_pcms,
3140 .init = stac92xx_init,
3141 .free = stac92xx_free,
4e55096e 3142 .unsol_event = stac92xx_unsol_event,
cb53c626 3143#ifdef SND_HDA_NEEDS_RESUME
ff6fdc37
M		 3144 .resume = stac92xx_resume,
3145#endif
2f2f4251
M		 3146};
3147
3148static int patch_stac9200(struct hda_codec *codec)
3149{
3150 struct sigmatel_spec *spec;
c7d4b2fa 3151 int err;
2f2f4251 3152
e560d8d8 3153 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2f2f4251
M		 3154 if (spec == NULL)
3155 return -ENOMEM;
3156
3157 codec->spec = spec;
a4eed138 3158 spec->num_pins = ARRAY_SIZE(stac9200_pin_nids);
11b44bbd 3159 spec->pin_nids = stac9200_pin_nids;
f5fcc13c
TI		 3160 spec->board_config = snd_hda_check_board_config(codec, STAC_9200_MODELS,
3161 stac9200_models,
3162 stac9200_cfg_tbl);
11b44bbd
RF		 3163 if (spec->board_config < 0) {
3164 snd_printdd(KERN_INFO "hda_codec: Unknown model for STAC9200, using BIOS defaults\n");
3165 err = stac92xx_save_bios_config_regs(codec);
3166 if (err < 0) {
3167 stac92xx_free(codec);
3168 return err;
3169 }
3170 spec->pin_configs = spec->bios_pin_configs;
3171 } else {
403d1944
MP		 3172 spec->pin_configs = stac9200_brd_tbl[spec->board_config];
3173 stac92xx_set_config_regs(codec);
3174 }
2f2f4251
M		 3175
3176 spec->multiout.max_channels = 2;
3177 spec->multiout.num_dacs = 1;
3178 spec->multiout.dac_nids = stac9200_dac_nids;
3179 spec->adc_nids = stac9200_adc_nids;
3180 spec->mux_nids = stac9200_mux_nids;
dabbed6f 3181 spec->num_muxes = 1;
8b65727b 3182 spec->num_dmics = 0;
9e05b7a3 3183 spec->num_adcs = 1;
a64135a2 3184 spec->num_pwrs = 0;
c7d4b2fa 3185
bf277785
TD		 3186 if (spec->board_config == STAC_9200_GATEWAY ||
3187 spec->board_config == STAC_9200_OQO)
1194b5b7
TI		 3188 spec->init = stac9200_eapd_init;
3189 else
3190 spec->init = stac9200_core_init;
2f2f4251 3191 spec->mixer = stac9200_mixer;
c7d4b2fa
M		 3192
3193 err = stac9200_parse_auto_config(codec);
3194 if (err < 0) {
3195 stac92xx_free(codec);
3196 return err;
3197 }
2f2f4251
M		 3198
3199 codec->patch_ops = stac92xx_patch_ops;
3200
3201 return 0;
3202}
3203
8e21c34c
TD		 3204static int patch_stac925x(struct hda_codec *codec)
3205{
3206 struct sigmatel_spec *spec;
3207 int err;
3208
3209 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
3210 if (spec == NULL)
3211 return -ENOMEM;
3212
3213 codec->spec = spec;
a4eed138 3214 spec->num_pins = ARRAY_SIZE(stac925x_pin_nids);
8e21c34c
TD		 3215 spec->pin_nids = stac925x_pin_nids;
3216 spec->board_config = snd_hda_check_board_config(codec, STAC_925x_MODELS,
3217 stac925x_models,
3218 stac925x_cfg_tbl);
9e507abd 3219 again:
8e21c34c 3220 if (spec->board_config < 0) {
2c11f955
TD		 3221 snd_printdd(KERN_INFO "hda_codec: Unknown model for STAC925x,"
3222 "using BIOS defaults\n");
8e21c34c
TD		 3223 err = stac92xx_save_bios_config_regs(codec);
3224 if (err < 0) {
3225 stac92xx_free(codec);
3226 return err;
3227 }
3228 spec->pin_configs = spec->bios_pin_configs;
3229 } else if (stac925x_brd_tbl[spec->board_config] != NULL){
3230 spec->pin_configs = stac925x_brd_tbl[spec->board_config];
3231 stac92xx_set_config_regs(codec);
3232 }
3233
3234 spec->multiout.max_channels = 2;
3235 spec->multiout.num_dacs = 1;
3236 spec->multiout.dac_nids = stac925x_dac_nids;
3237 spec->adc_nids = stac925x_adc_nids;
3238 spec->mux_nids = stac925x_mux_nids;
3239 spec->num_muxes = 1;
9e05b7a3 3240 spec->num_adcs = 1;
a64135a2 3241 spec->num_pwrs = 0;
2c11f955
TD		 3242 switch (codec->vendor_id) {
3243 case 0x83847632: /* STAC9202 */
3244 case 0x83847633: /* STAC9202D */
3245 case 0x83847636: /* STAC9251 */
3246 case 0x83847637: /* STAC9251D */
f6e9852a 3247 spec->num_dmics = STAC925X_NUM_DMICS;
2c11f955 3248 spec->dmic_nids = stac925x_dmic_nids;
1697055e
TI		 3249 spec->num_dmuxes = ARRAY_SIZE(stac925x_dmux_nids);
3250 spec->dmux_nids = stac925x_dmux_nids;
2c11f955
TD		 3251 break;
3252 default:
3253 spec->num_dmics = 0;
3254 break;
3255 }
8e21c34c
TD		 3256
3257 spec->init = stac925x_core_init;
3258 spec->mixer = stac925x_mixer;
3259
3260 err = stac92xx_parse_auto_config(codec, 0x8, 0x7);
9e507abd
TI		 3261 if (!err) {
3262 if (spec->board_config < 0) {
3263 printk(KERN_WARNING "hda_codec: No auto-config is "
3264 "available, default to model=ref\n");
3265 spec->board_config = STAC_925x_REF;
3266 goto again;
3267 }
3268 err = -EINVAL;
3269 }
8e21c34c
TD		 3270 if (err < 0) {
3271 stac92xx_free(codec);
3272 return err;
3273 }
3274
3275 codec->patch_ops = stac92xx_patch_ops;
3276
3277 return 0;
3278}
3279
e1f0d669
MR		 3280static struct hda_input_mux stac92hd73xx_dmux = {
3281 .num_items = 4,
3282 .items = {
3283 { "Analog Inputs", 0x0b },
3284 { "CD", 0x08 },
3285 { "Digital Mic 1", 0x09 },
3286 { "Digital Mic 2", 0x0a },
3287 }
3288};
3289
3290static int patch_stac92hd73xx(struct hda_codec *codec)
3291{
3292 struct sigmatel_spec *spec;
3293 hda_nid_t conn[STAC92HD73_DAC_COUNT + 2];
3294 int err = 0;
3295
3296 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
3297 if (spec == NULL)
3298 return -ENOMEM;
3299
3300 codec->spec = spec;
3301 spec->num_pins = ARRAY_SIZE(stac92hd73xx_pin_nids);
3302 spec->pin_nids = stac92hd73xx_pin_nids;
3303 spec->board_config = snd_hda_check_board_config(codec,
3304 STAC_92HD73XX_MODELS,
3305 stac92hd73xx_models,
3306 stac92hd73xx_cfg_tbl);
3307again:
3308 if (spec->board_config < 0) {
3309 snd_printdd(KERN_INFO "hda_codec: Unknown model for"
3310 " STAC92HD73XX, using BIOS defaults\n");
3311 err = stac92xx_save_bios_config_regs(codec);
3312 if (err < 0) {
3313 stac92xx_free(codec);
3314 return err;
3315 }
3316 spec->pin_configs = spec->bios_pin_configs;
3317 } else {
3318 spec->pin_configs = stac92hd73xx_brd_tbl[spec->board_config];
3319 stac92xx_set_config_regs(codec);
3320 }
3321
3322 spec->multiout.num_dacs = snd_hda_get_connections(codec, 0x0a,
3323 conn, STAC92HD73_DAC_COUNT + 2) - 1;
3324
3325 if (spec->multiout.num_dacs < 0) {
3326 printk(KERN_WARNING "hda_codec: Could not determine "
3327 "number of channels defaulting to DAC count\n");
3328 spec->multiout.num_dacs = STAC92HD73_DAC_COUNT;
3329 }
3330
3331 switch (spec->multiout.num_dacs) {
3332 case 0x3: /* 6 Channel */
3333 spec->mixer = stac92hd73xx_6ch_mixer;
3334 spec->init = stac92hd73xx_6ch_core_init;
3335 break;
3336 case 0x4: /* 8 Channel */
3337 spec->multiout.hp_nid = 0x18;
3338 spec->mixer = stac92hd73xx_8ch_mixer;
3339 spec->init = stac92hd73xx_8ch_core_init;
3340 break;
3341 case 0x5: /* 10 Channel */
3342 spec->multiout.hp_nid = 0x19;
3343 spec->mixer = stac92hd73xx_10ch_mixer;
3344 spec->init = stac92hd73xx_10ch_core_init;
3345 };
3346
3347 spec->multiout.dac_nids = stac92hd73xx_dac_nids;
3348 spec->aloopback_mask = 0x01;
3349 spec->aloopback_shift = 8;
3350
3351 spec->mux_nids = stac92hd73xx_mux_nids;
3352 spec->adc_nids = stac92hd73xx_adc_nids;
3353 spec->dmic_nids = stac92hd73xx_dmic_nids;
3354 spec->dmux_nids = stac92hd73xx_dmux_nids;
3355
3356 spec->num_muxes = ARRAY_SIZE(stac92hd73xx_mux_nids);
3357 spec->num_adcs = ARRAY_SIZE(stac92hd73xx_adc_nids);
3358 spec->num_dmics = STAC92HD73XX_NUM_DMICS;
1697055e 3359 spec->num_dmuxes = ARRAY_SIZE(stac92hd73xx_dmux_nids);
e1f0d669
MR		 3360 spec->dinput_mux = &stac92hd73xx_dmux;
3361 /* GPIO0 High = Enable EAPD */
4fe5195c
MR		 3362 spec->gpio_mask = spec->gpio_dir = 0x1;
3363 spec->gpio_data = 0x01;
e1f0d669 3364
a64135a2
MR		 3365 spec->num_pwrs = ARRAY_SIZE(stac92hd73xx_pwr_nids);
3366 spec->pwr_nids = stac92hd73xx_pwr_nids;
3367
e1f0d669
MR		 3368 err = stac92xx_parse_auto_config(codec, 0x22, 0x24);
3369
3370 if (!err) {
3371 if (spec->board_config < 0) {
3372 printk(KERN_WARNING "hda_codec: No auto-config is "
3373 "available, default to model=ref\n");
3374 spec->board_config = STAC_92HD73XX_REF;
3375 goto again;
3376 }
3377 err = -EINVAL;
3378 }
3379
3380 if (err < 0) {
3381 stac92xx_free(codec);
3382 return err;
3383 }
3384
3385 codec->patch_ops = stac92xx_patch_ops;
3386
3387 return 0;
3388}
3389
e035b841
MR		 3390static int patch_stac92hd71bxx(struct hda_codec *codec)
3391{
3392 struct sigmatel_spec *spec;
3393 int err = 0;
3394
3395 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
3396 if (spec == NULL)
3397 return -ENOMEM;
3398
3399 codec->spec = spec;
3400 spec->num_pins = ARRAY_SIZE(stac92hd71bxx_pin_nids);
3401 spec->pin_nids = stac92hd71bxx_pin_nids;
3402 spec->board_config = snd_hda_check_board_config(codec,
3403 STAC_92HD71BXX_MODELS,
3404 stac92hd71bxx_models,
3405 stac92hd71bxx_cfg_tbl);
3406again:
3407 if (spec->board_config < 0) {
3408 snd_printdd(KERN_INFO "hda_codec: Unknown model for"
3409 " STAC92HD71BXX, using BIOS defaults\n");
3410 err = stac92xx_save_bios_config_regs(codec);
3411 if (err < 0) {
3412 stac92xx_free(codec);
3413 return err;
3414 }
3415 spec->pin_configs = spec->bios_pin_configs;
3416 } else {
3417 spec->pin_configs = stac92hd71bxx_brd_tbl[spec->board_config];
3418 stac92xx_set_config_regs(codec);
3419 }
3420
541eee87
MR		 3421 switch (codec->vendor_id) {
3422 case 0x111d76b6: /* 4 Port without Analog Mixer */
3423 case 0x111d76b7:
3424 case 0x111d76b4: /* 6 Port without Analog Mixer */
3425 case 0x111d76b5:
3426 spec->mixer = stac92hd71bxx_mixer;
3427 spec->init = stac92hd71bxx_core_init;
3428 break;
3429 default:
3430 spec->mixer = stac92hd71bxx_analog_mixer;
3431 spec->init = stac92hd71bxx_analog_core_init;
3432 }
3433
3434 spec->aloopback_mask = 0x20;
3435 spec->aloopback_shift = 0;
3436
4fe5195c
MR		 3437 /* GPIO0 High = EAPD */
3438 spec->gpio_mask = spec->gpio_dir = spec->gpio_data = 0x1;
e035b841 3439
e035b841
MR		 3440 spec->mux_nids = stac92hd71bxx_mux_nids;
3441 spec->adc_nids = stac92hd71bxx_adc_nids;
3442 spec->dmic_nids = stac92hd71bxx_dmic_nids;
e1f0d669 3443 spec->dmux_nids = stac92hd71bxx_dmux_nids;
e035b841
MR		 3444
3445 spec->num_muxes = ARRAY_SIZE(stac92hd71bxx_mux_nids);
3446 spec->num_adcs = ARRAY_SIZE(stac92hd71bxx_adc_nids);
3447 spec->num_dmics = STAC92HD71BXX_NUM_DMICS;
1697055e 3448 spec->num_dmuxes = ARRAY_SIZE(stac92hd71bxx_dmux_nids);
e035b841 3449
a64135a2
MR		 3450 spec->num_pwrs = ARRAY_SIZE(stac92hd71bxx_pwr_nids);
3451 spec->pwr_nids = stac92hd71bxx_pwr_nids;
3452
e035b841
MR		 3453 spec->multiout.num_dacs = 2;
3454 spec->multiout.hp_nid = 0x11;
3455 spec->multiout.dac_nids = stac92hd71bxx_dac_nids;
3456
3457 err = stac92xx_parse_auto_config(codec, 0x21, 0x23);
3458 if (!err) {
3459 if (spec->board_config < 0) {
3460 printk(KERN_WARNING "hda_codec: No auto-config is "
3461 "available, default to model=ref\n");
3462 spec->board_config = STAC_92HD71BXX_REF;
3463 goto again;
3464 }
3465 err = -EINVAL;
3466 }
3467
3468 if (err < 0) {
3469 stac92xx_free(codec);
3470 return err;
3471 }
3472
3473 codec->patch_ops = stac92xx_patch_ops;
3474
3475 return 0;
3476};
3477
2f2f4251
M		 3478static int patch_stac922x(struct hda_codec *codec)
3479{
3480 struct sigmatel_spec *spec;
c7d4b2fa 3481 int err;
2f2f4251 3482
e560d8d8 3483 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2f2f4251
M		 3484 if (spec == NULL)
3485 return -ENOMEM;
3486
3487 codec->spec = spec;
a4eed138 3488 spec->num_pins = ARRAY_SIZE(stac922x_pin_nids);
11b44bbd 3489 spec->pin_nids = stac922x_pin_nids;
f5fcc13c
TI		 3490 spec->board_config = snd_hda_check_board_config(codec, STAC_922X_MODELS,
3491 stac922x_models,
3492 stac922x_cfg_tbl);
5d5d3bc3 3493 if (spec->board_config == STAC_INTEL_MAC_V3) {
4fe5195c
MR		 3494 spec->gpio_mask = spec->gpio_dir = 0x03;
3495 spec->gpio_data = 0x03;
3fc24d85
TI		 3496 /* Intel Macs have all same PCI SSID, so we need to check
3497 * codec SSID to distinguish the exact models
3498 */
6f0778d8 3499 printk(KERN_INFO "hda_codec: STAC922x, Apple subsys_id=%x\n", codec->subsystem_id);
3fc24d85 3500 switch (codec->subsystem_id) {
5d5d3bc3
IZ		 3501
3502 case 0x106b0800:
3503 spec->board_config = STAC_INTEL_MAC_V1;
c45e20eb 3504 break;
5d5d3bc3
IZ		 3505 case 0x106b0600:
3506 case 0x106b0700:
3507 spec->board_config = STAC_INTEL_MAC_V2;
6f0778d8 3508 break;
5d5d3bc3
IZ		 3509 case 0x106b0e00:
3510 case 0x106b0f00:
3511 case 0x106b1600:
3512 case 0x106b1700:
3513 case 0x106b0200:
3514 case 0x106b1e00:
3515 spec->board_config = STAC_INTEL_MAC_V3;
3fc24d85 3516 break;
5d5d3bc3
IZ		 3517 case 0x106b1a00:
3518 case 0x00000100:
3519 spec->board_config = STAC_INTEL_MAC_V4;
f16928fb 3520 break;
5d5d3bc3
IZ		 3521 case 0x106b0a00:
3522 case 0x106b2200:
3523 spec->board_config = STAC_INTEL_MAC_V5;
0dae0f83 3524 break;
3fc24d85
TI		 3525 }
3526 }
3527
9e507abd 3528 again:
11b44bbd
RF		 3529 if (spec->board_config < 0) {
3530 snd_printdd(KERN_INFO "hda_codec: Unknown model for STAC922x, "
3531 "using BIOS defaults\n");
3532 err = stac92xx_save_bios_config_regs(codec);
3533 if (err < 0) {
3534 stac92xx_free(codec);
3535 return err;
3536 }
3537 spec->pin_configs = spec->bios_pin_configs;
3538 } else if (stac922x_brd_tbl[spec->board_config] != NULL) {
403d1944
MP		 3539 spec->pin_configs = stac922x_brd_tbl[spec->board_config];
3540 stac92xx_set_config_regs(codec);
3541 }
2f2f4251 3542
c7d4b2fa
M		 3543 spec->adc_nids = stac922x_adc_nids;
3544 spec->mux_nids = stac922x_mux_nids;
2549413e 3545 spec->num_muxes = ARRAY_SIZE(stac922x_mux_nids);
9e05b7a3 3546 spec->num_adcs = ARRAY_SIZE(stac922x_adc_nids);
8b65727b 3547 spec->num_dmics = 0;
a64135a2 3548 spec->num_pwrs = 0;
c7d4b2fa
M		 3549
3550 spec->init = stac922x_core_init;
2f2f4251 3551 spec->mixer = stac922x_mixer;
c7d4b2fa
M		 3552
3553 spec->multiout.dac_nids = spec->dac_nids;
19039bd0 3554
3cc08dc6 3555 err = stac92xx_parse_auto_config(codec, 0x08, 0x09);
9e507abd
TI		 3556 if (!err) {
3557 if (spec->board_config < 0) {
3558 printk(KERN_WARNING "hda_codec: No auto-config is "
3559 "available, default to model=ref\n");
3560 spec->board_config = STAC_D945_REF;
3561 goto again;
3562 }
3563 err = -EINVAL;
3564 }
3cc08dc6
MP		 3565 if (err < 0) {
3566 stac92xx_free(codec);
3567 return err;
3568 }
3569
3570 codec->patch_ops = stac92xx_patch_ops;
3571
807a4636
TI		 3572 /* Fix Mux capture level; max to 2 */
3573 snd_hda_override_amp_caps(codec, 0x12, HDA_OUTPUT,
3574 (0 << AC_AMPCAP_OFFSET_SHIFT) |
3575 (2 << AC_AMPCAP_NUM_STEPS_SHIFT) |
3576 (0x27 << AC_AMPCAP_STEP_SIZE_SHIFT) |
3577 (0 << AC_AMPCAP_MUTE_SHIFT));
3578
3cc08dc6
MP		 3579 return 0;
3580}
3581
3582static int patch_stac927x(struct hda_codec *codec)
3583{
3584 struct sigmatel_spec *spec;
3585 int err;
3586
3587 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
3588 if (spec == NULL)
3589 return -ENOMEM;
3590
3591 codec->spec = spec;
a4eed138 3592 spec->num_pins = ARRAY_SIZE(stac927x_pin_nids);
11b44bbd 3593 spec->pin_nids = stac927x_pin_nids;
f5fcc13c
TI		 3594 spec->board_config = snd_hda_check_board_config(codec, STAC_927X_MODELS,
3595 stac927x_models,
3596 stac927x_cfg_tbl);
9e507abd 3597 again:
8e9068b1
MR		 3598 if (spec->board_config < 0 || !stac927x_brd_tbl[spec->board_config]) {
3599 if (spec->board_config < 0)
3600 snd_printdd(KERN_INFO "hda_codec: Unknown model for"
3601 "STAC927x, using BIOS defaults\n");
11b44bbd
RF		 3602 err = stac92xx_save_bios_config_regs(codec);
3603 if (err < 0) {
3604 stac92xx_free(codec);
3605 return err;
3606 }
3607 spec->pin_configs = spec->bios_pin_configs;
8e9068b1 3608 } else {
3cc08dc6
MP		 3609 spec->pin_configs = stac927x_brd_tbl[spec->board_config];
3610 stac92xx_set_config_regs(codec);
3611 }
3612
8e9068b1
MR		 3613 spec->adc_nids = stac927x_adc_nids;
3614 spec->num_adcs = ARRAY_SIZE(stac927x_adc_nids);
3615 spec->mux_nids = stac927x_mux_nids;
3616 spec->num_muxes = ARRAY_SIZE(stac927x_mux_nids);
b76c850f 3617 spec->dac_list = stac927x_dac_nids;
8e9068b1
MR		 3618 spec->multiout.dac_nids = spec->dac_nids;
3619
81d3dbde 3620 switch (spec->board_config) {
93ed1503 3621 case STAC_D965_3ST:
93ed1503 3622 case STAC_D965_5ST:
8e9068b1 3623 /* GPIO0 High = Enable EAPD */
4fe5195c
MR		 3624 spec->gpio_mask = spec->gpio_dir = 0x01;
3625 spec->gpio_data = 0x01;
8e9068b1
MR		 3626 spec->num_dmics = 0;
3627
93ed1503 3628 spec->init = d965_core_init;
9e05b7a3 3629 spec->mixer = stac927x_mixer;
81d3dbde 3630 break;
8e9068b1 3631 case STAC_DELL_BIOS:
2f32d909
MR		 3632 /* correct the front output jack as a hp out */
3633 stac92xx_set_config_reg(codec, 0x0f, 0x02270110);
c481fca3
MR		 3634 /* correct the front input jack as a mic */
3635 stac92xx_set_config_reg(codec, 0x0e, 0x02a79130);
3636 /* fallthru */
8e9068b1
MR		 3637 case STAC_DELL_3ST:
3638 /* GPIO2 High = Enable EAPD */
4fe5195c
MR		 3639 spec->gpio_mask = spec->gpio_dir = 0x04;
3640 spec->gpio_data = 0x04;
7f16859a
MR		 3641 spec->dmic_nids = stac927x_dmic_nids;
3642 spec->num_dmics = STAC927X_NUM_DMICS;
f1f208d0 3643
8e9068b1
MR		 3644 spec->init = d965_core_init;
3645 spec->mixer = stac927x_mixer;
3646 spec->dmux_nids = stac927x_dmux_nids;
1697055e 3647 spec->num_dmuxes = ARRAY_SIZE(stac927x_dmux_nids);
7f16859a
MR		 3648 break;
3649 default:
f1f208d0 3650 /* GPIO0 High = Enable EAPD */
4fe5195c
MR		 3651 spec->gpio_mask = spec->gpio_dir = 0x1;
3652 spec->gpio_data = 0x01;
8e9068b1
MR		 3653 spec->num_dmics = 0;
3654
3655 spec->init = stac927x_core_init;
3656 spec->mixer = stac927x_mixer;
7f16859a
MR		 3657 }
3658
a64135a2 3659 spec->num_pwrs = 0;
e1f0d669
MR		 3660 spec->aloopback_mask = 0x40;
3661 spec->aloopback_shift = 0;
8e9068b1 3662
3cc08dc6 3663 err = stac92xx_parse_auto_config(codec, 0x1e, 0x20);
9e507abd
TI		 3664 if (!err) {
3665 if (spec->board_config < 0) {
3666 printk(KERN_WARNING "hda_codec: No auto-config is "
3667 "available, default to model=ref\n");
3668 spec->board_config = STAC_D965_REF;
3669 goto again;
3670 }
3671 err = -EINVAL;
3672 }
c7d4b2fa
M		 3673 if (err < 0) {
3674 stac92xx_free(codec);
3675 return err;
3676 }
2f2f4251
M		 3677
3678 codec->patch_ops = stac92xx_patch_ops;
3679
52987656
TI		 3680 /*
3681 * !!FIXME!!
3682 * The STAC927x seem to require fairly long delays for certain
3683 * command sequences. With too short delays (even if the answer
3684 * is set to RIRB properly), it results in the silence output
3685 * on some hardwares like Dell.
3686 *
3687 * The below flag enables the longer delay (see get_response
3688 * in hda_intel.c).
3689 */
3690 codec->bus->needs_damn_long_delay = 1;
3691
2f2f4251
M		 3692 return 0;
3693}
3694
f3302a59
MP		 3695static int patch_stac9205(struct hda_codec *codec)
3696{
3697 struct sigmatel_spec *spec;
8259980e 3698 int err;
f3302a59
MP		 3699
3700 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
3701 if (spec == NULL)
3702 return -ENOMEM;
3703
3704 codec->spec = spec;
a4eed138 3705 spec->num_pins = ARRAY_SIZE(stac9205_pin_nids);
11b44bbd 3706 spec->pin_nids = stac9205_pin_nids;
f5fcc13c
TI		 3707 spec->board_config = snd_hda_check_board_config(codec, STAC_9205_MODELS,
3708 stac9205_models,
3709 stac9205_cfg_tbl);
9e507abd 3710 again:
11b44bbd
RF		 3711 if (spec->board_config < 0) {
3712 snd_printdd(KERN_INFO "hda_codec: Unknown model for STAC9205, using BIOS defaults\n");
3713 err = stac92xx_save_bios_config_regs(codec);
3714 if (err < 0) {
3715 stac92xx_free(codec);
3716 return err;
3717 }
3718 spec->pin_configs = spec->bios_pin_configs;
3719 } else {
f3302a59
MP		 3720 spec->pin_configs = stac9205_brd_tbl[spec->board_config];
3721 stac92xx_set_config_regs(codec);
3722 }
3723
3724 spec->adc_nids = stac9205_adc_nids;
9e05b7a3 3725 spec->num_adcs = ARRAY_SIZE(stac9205_adc_nids);
f3302a59 3726 spec->mux_nids = stac9205_mux_nids;
2549413e 3727 spec->num_muxes = ARRAY_SIZE(stac9205_mux_nids);
8b65727b 3728 spec->dmic_nids = stac9205_dmic_nids;
f6e9852a 3729 spec->num_dmics = STAC9205_NUM_DMICS;
e1f0d669 3730 spec->dmux_nids = stac9205_dmux_nids;
1697055e 3731 spec->num_dmuxes = ARRAY_SIZE(stac9205_dmux_nids);
a64135a2 3732 spec->num_pwrs = 0;
f3302a59
MP		 3733
3734 spec->init = stac9205_core_init;
3735 spec->mixer = stac9205_mixer;
3736
e1f0d669
MR		 3737 spec->aloopback_mask = 0x40;
3738 spec->aloopback_shift = 0;
f3302a59 3739 spec->multiout.dac_nids = spec->dac_nids;
87d48363 3740
ae0a8ed8 3741 switch (spec->board_config){
ae0a8ed8 3742 case STAC_9205_DELL_M43:
87d48363
MR		 3743 /* Enable SPDIF in/out */
3744 stac92xx_set_config_reg(codec, 0x1f, 0x01441030);
3745 stac92xx_set_config_reg(codec, 0x20, 0x1c410030);
3746
4fe5195c
MR		 3747 /* Enable unsol response for GPIO4/Dock HP connection */
3748 snd_hda_codec_write(codec, codec->afg, 0,
3749 AC_VERB_SET_GPIO_UNSOLICITED_RSP_MASK, 0x10);
3750 snd_hda_codec_write_cache(codec, codec->afg, 0,
3751 AC_VERB_SET_UNSOLICITED_ENABLE,
3752 (AC_USRSP_EN | STAC_HP_EVENT));
3753
3754 spec->gpio_dir = 0x0b;
3755 spec->gpio_mask = 0x1b;
3756 spec->gpio_mute = 0x10;
e2e7d624 3757 /* GPIO0 High = EAPD, GPIO1 Low = Headphone Mute,
4fe5195c 3758 * GPIO3 Low = DRM
87d48363 3759 */
4fe5195c 3760 spec->gpio_data = 0x01;
ae0a8ed8
TD		 3761 break;
3762 default:
3763 /* GPIO0 High = EAPD */
4fe5195c
MR		 3764 spec->gpio_mask = spec->gpio_dir = 0x1;
3765 spec->gpio_data = 0x01;
ae0a8ed8
TD		 3766 break;
3767 }
33382403 3768
f3302a59 3769 err = stac92xx_parse_auto_config(codec, 0x1f, 0x20);
9e507abd
TI		 3770 if (!err) {
3771 if (spec->board_config < 0) {
3772 printk(KERN_WARNING "hda_codec: No auto-config is "
3773 "available, default to model=ref\n");
3774 spec->board_config = STAC_9205_REF;
3775 goto again;
3776 }
3777 err = -EINVAL;
3778 }
f3302a59
MP		 3779 if (err < 0) {
3780 stac92xx_free(codec);
3781 return err;
3782 }
3783
3784 codec->patch_ops = stac92xx_patch_ops;
3785
3786 return 0;
3787}
3788
db064e50 3789/*
6d859065 3790 * STAC9872 hack
db064e50
TI		 3791 */
3792
99ccc560 3793/* static config for Sony VAIO FE550G and Sony VAIO AR */
db064e50
TI		 3794static hda_nid_t vaio_dacs[] = { 0x2 };
3795#define VAIO_HP_DAC 0x5
3796static hda_nid_t vaio_adcs[] = { 0x8 /*,0x6*/ };
3797static hda_nid_t vaio_mux_nids[] = { 0x15 };
3798
3799static struct hda_input_mux vaio_mux = {
a3a2f429 3800 .num_items = 3,
db064e50 3801 .items = {
d773781c 3802 /* { "HP", 0x0 }, */
1624cb9a
TI		 3803 { "Mic Jack", 0x1 },
3804 { "Internal Mic", 0x2 },
db064e50
TI		 3805 { "PCM", 0x3 },
3806 }
3807};
3808
3809static struct hda_verb vaio_init[] = {
3810 {0x0a, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_HP }, /* HP <- 0x2 */
72e7b0dd 3811 {0x0a, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | STAC_HP_EVENT},
db064e50
TI		 3812 {0x0f, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT }, /* Speaker <- 0x5 */
3813 {0x0d, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_VREF80 }, /* Mic? (<- 0x2) */
3814 {0x0e, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_IN }, /* CD */
3815 {0x14, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_VREF80 }, /* Mic? */
1624cb9a 3816 {0x15, AC_VERB_SET_CONNECT_SEL, 0x1}, /* mic-sel: 0a,0d,14,02 */
db064e50
TI		 3817 {0x02, AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_MUTE}, /* HP */
3818 {0x05, AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_MUTE}, /* Speaker */
3819 {0x09, AC_VERB_SET_AMP_GAIN_MUTE, AMP_IN_MUTE(0)}, /* capture sw/vol -> 0x8 */
3820 {0x07, AC_VERB_SET_AMP_GAIN_MUTE, AMP_IN_UNMUTE(0)}, /* CD-in -> 0x6 */
3821 {0x15, AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE}, /* Mic-in -> 0x9 */
3822 {}
3823};
3824
6d859065
GM		 3825static struct hda_verb vaio_ar_init[] = {
3826 {0x0a, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_HP }, /* HP <- 0x2 */
3827 {0x0f, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT }, /* Speaker <- 0x5 */
3828 {0x0d, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_VREF80 }, /* Mic? (<- 0x2) */
3829 {0x0e, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_IN }, /* CD */
3830/* {0x11, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT },*/ /* Optical Out */
3831 {0x14, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_VREF80 }, /* Mic? */
1624cb9a 3832 {0x15, AC_VERB_SET_CONNECT_SEL, 0x1}, /* mic-sel: 0a,0d,14,02 */
6d859065
GM		 3833 {0x02, AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_MUTE}, /* HP */
3834 {0x05, AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_MUTE}, /* Speaker */
3835/* {0x10, AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_MUTE},*/ /* Optical Out */
3836 {0x09, AC_VERB_SET_AMP_GAIN_MUTE, AMP_IN_MUTE(0)}, /* capture sw/vol -> 0x8 */
3837 {0x07, AC_VERB_SET_AMP_GAIN_MUTE, AMP_IN_UNMUTE(0)}, /* CD-in -> 0x6 */
3838 {0x15, AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE}, /* Mic-in -> 0x9 */
3839 {}
3840};
3841
db064e50 3842/* bind volumes of both NID 0x02 and 0x05 */
cca3b371
TI		 3843static struct hda_bind_ctls vaio_bind_master_vol = {
3844 .ops = &snd_hda_bind_vol,
3845 .values = {
3846 HDA_COMPOSE_AMP_VAL(0x02, 3, 0, HDA_OUTPUT),
3847 HDA_COMPOSE_AMP_VAL(0x05, 3, 0, HDA_OUTPUT),
3848 0
3849 },
3850};
db064e50
TI		 3851
3852/* bind volumes of both NID 0x02 and 0x05 */
cca3b371
TI		 3853static struct hda_bind_ctls vaio_bind_master_sw = {
3854 .ops = &snd_hda_bind_sw,
3855 .values = {
3856 HDA_COMPOSE_AMP_VAL(0x02, 3, 0, HDA_OUTPUT),
3857 HDA_COMPOSE_AMP_VAL(0x05, 3, 0, HDA_OUTPUT),
3858 0,
3859 },
3860};
db064e50
TI		 3861
3862static struct snd_kcontrol_new vaio_mixer[] = {
cca3b371
TI		 3863 HDA_BIND_VOL("Master Playback Volume", &vaio_bind_master_vol),
3864 HDA_BIND_SW("Master Playback Switch", &vaio_bind_master_sw),
db064e50
TI		 3865 /* HDA_CODEC_VOLUME("CD Capture Volume", 0x07, 0, HDA_INPUT), */
3866 HDA_CODEC_VOLUME("Capture Volume", 0x09, 0, HDA_INPUT),
3867 HDA_CODEC_MUTE("Capture Switch", 0x09, 0, HDA_INPUT),
3868 {
3869 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3870 .name = "Capture Source",
3871 .count = 1,
3872 .info = stac92xx_mux_enum_info,
3873 .get = stac92xx_mux_enum_get,
3874 .put = stac92xx_mux_enum_put,
3875 },
3876 {}
3877};
3878
6d859065 3879static struct snd_kcontrol_new vaio_ar_mixer[] = {
cca3b371
TI		 3880 HDA_BIND_VOL("Master Playback Volume", &vaio_bind_master_vol),
3881 HDA_BIND_SW("Master Playback Switch", &vaio_bind_master_sw),
6d859065
GM		 3882 /* HDA_CODEC_VOLUME("CD Capture Volume", 0x07, 0, HDA_INPUT), */
3883 HDA_CODEC_VOLUME("Capture Volume", 0x09, 0, HDA_INPUT),
3884 HDA_CODEC_MUTE("Capture Switch", 0x09, 0, HDA_INPUT),
3885 /*HDA_CODEC_MUTE("Optical Out Switch", 0x10, 0, HDA_OUTPUT),
3886 HDA_CODEC_VOLUME("Optical Out Volume", 0x10, 0, HDA_OUTPUT),*/
3887 {
3888 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3889 .name = "Capture Source",
3890 .count = 1,
3891 .info = stac92xx_mux_enum_info,
3892 .get = stac92xx_mux_enum_get,
3893 .put = stac92xx_mux_enum_put,
3894 },
3895 {}
3896};
3897
3898static struct hda_codec_ops stac9872_patch_ops = {
db064e50
TI		 3899 .build_controls = stac92xx_build_controls,
3900 .build_pcms = stac92xx_build_pcms,
3901 .init = stac92xx_init,
3902 .free = stac92xx_free,
cb53c626 3903#ifdef SND_HDA_NEEDS_RESUME
db064e50
TI		 3904 .resume = stac92xx_resume,
3905#endif
3906};
3907
72e7b0dd
TI		 3908static int stac9872_vaio_init(struct hda_codec *codec)
3909{
3910 int err;
3911
3912 err = stac92xx_init(codec);
3913 if (err < 0)
3914 return err;
3915 if (codec->patch_ops.unsol_event)
3916 codec->patch_ops.unsol_event(codec, STAC_HP_EVENT << 26);
3917 return 0;
3918}
3919
3920static void stac9872_vaio_hp_detect(struct hda_codec *codec, unsigned int res)
3921{
40c1d308 3922 if (get_hp_pin_presence(codec, 0x0a)) {
72e7b0dd
TI		 3923 stac92xx_reset_pinctl(codec, 0x0f, AC_PINCTL_OUT_EN);
3924 stac92xx_set_pinctl(codec, 0x0a, AC_PINCTL_OUT_EN);
3925 } else {
3926 stac92xx_reset_pinctl(codec, 0x0a, AC_PINCTL_OUT_EN);
3927 stac92xx_set_pinctl(codec, 0x0f, AC_PINCTL_OUT_EN);
3928 }
3929}
3930
3931static void stac9872_vaio_unsol_event(struct hda_codec *codec, unsigned int res)
3932{
3933 switch (res >> 26) {
3934 case STAC_HP_EVENT:
3935 stac9872_vaio_hp_detect(codec, res);
3936 break;
3937 }
3938}
3939
3940static struct hda_codec_ops stac9872_vaio_patch_ops = {
3941 .build_controls = stac92xx_build_controls,
3942 .build_pcms = stac92xx_build_pcms,
3943 .init = stac9872_vaio_init,
3944 .free = stac92xx_free,
3945 .unsol_event = stac9872_vaio_unsol_event,
3946#ifdef CONFIG_PM
3947 .resume = stac92xx_resume,
3948#endif
3949};
3950
6d859065
GM		 3951enum { /* FE and SZ series. id=0x83847661 and subsys=0x104D0700 or 104D1000. */
3952 CXD9872RD_VAIO,
3953 /* Unknown. id=0x83847662 and subsys=0x104D1200 or 104D1000. */
3954 STAC9872AK_VAIO,
3955 /* Unknown. id=0x83847661 and subsys=0x104D1200. */
3956 STAC9872K_VAIO,
3957 /* AR Series. id=0x83847664 and subsys=104D1300 */
f5fcc13c
TI		 3958 CXD9872AKD_VAIO,
3959 STAC_9872_MODELS,
3960};
3961
3962static const char *stac9872_models[STAC_9872_MODELS] = {
3963 [CXD9872RD_VAIO] = "vaio",
3964 [CXD9872AKD_VAIO] = "vaio-ar",
3965};
3966
3967static struct snd_pci_quirk stac9872_cfg_tbl[] = {
3968 SND_PCI_QUIRK(0x104d, 0x81e6, "Sony VAIO F/S", CXD9872RD_VAIO),
3969 SND_PCI_QUIRK(0x104d, 0x81ef, "Sony VAIO F/S", CXD9872RD_VAIO),
3970 SND_PCI_QUIRK(0x104d, 0x81fd, "Sony VAIO AR", CXD9872AKD_VAIO),
68e22543 3971 SND_PCI_QUIRK(0x104d, 0x8205, "Sony VAIO AR", CXD9872AKD_VAIO),
db064e50
TI		 3972 {}
3973};
3974
6d859065 3975static int patch_stac9872(struct hda_codec *codec)
db064e50
TI		 3976{
3977 struct sigmatel_spec *spec;
3978 int board_config;
3979
f5fcc13c
TI		 3980 board_config = snd_hda_check_board_config(codec, STAC_9872_MODELS,
3981 stac9872_models,
3982 stac9872_cfg_tbl);
db064e50
TI		 3983 if (board_config < 0)
3984 /* unknown config, let generic-parser do its job... */
3985 return snd_hda_parse_generic_codec(codec);
3986
3987 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
3988 if (spec == NULL)
3989 return -ENOMEM;
3990
3991 codec->spec = spec;
3992 switch (board_config) {
6d859065
GM		 3993 case CXD9872RD_VAIO:
3994 case STAC9872AK_VAIO:
3995 case STAC9872K_VAIO:
db064e50
TI		 3996 spec->mixer = vaio_mixer;
3997 spec->init = vaio_init;
3998 spec->multiout.max_channels = 2;
3999 spec->multiout.num_dacs = ARRAY_SIZE(vaio_dacs);
4000 spec->multiout.dac_nids = vaio_dacs;
4001 spec->multiout.hp_nid = VAIO_HP_DAC;
4002 spec->num_adcs = ARRAY_SIZE(vaio_adcs);
4003 spec->adc_nids = vaio_adcs;
a64135a2 4004 spec->num_pwrs = 0;
db064e50
TI		 4005 spec->input_mux = &vaio_mux;
4006 spec->mux_nids = vaio_mux_nids;
72e7b0dd 4007 codec->patch_ops = stac9872_vaio_patch_ops;
db064e50 4008 break;
6d859065
GM		 4009
4010 case CXD9872AKD_VAIO:
4011 spec->mixer = vaio_ar_mixer;
4012 spec->init = vaio_ar_init;
4013 spec->multiout.max_channels = 2;
4014 spec->multiout.num_dacs = ARRAY_SIZE(vaio_dacs);
4015 spec->multiout.dac_nids = vaio_dacs;
4016 spec->multiout.hp_nid = VAIO_HP_DAC;
4017 spec->num_adcs = ARRAY_SIZE(vaio_adcs);
a64135a2 4018 spec->num_pwrs = 0;
6d859065
GM		 4019 spec->adc_nids = vaio_adcs;
4020 spec->input_mux = &vaio_mux;
4021 spec->mux_nids = vaio_mux_nids;
72e7b0dd 4022 codec->patch_ops = stac9872_patch_ops;
6d859065 4023 break;
db064e50
TI		 4024 }
4025
db064e50
TI		 4026 return 0;
4027}
4028
4029
2f2f4251
M		 4030/*
4031 * patch entries
4032 */
4033struct hda_codec_preset snd_hda_preset_sigmatel[] = {
4034 { .id = 0x83847690, .name = "STAC9200", .patch = patch_stac9200 },
4035 { .id = 0x83847882, .name = "STAC9220 A1", .patch = patch_stac922x },
4036 { .id = 0x83847680, .name = "STAC9221 A1", .patch = patch_stac922x },
4037 { .id = 0x83847880, .name = "STAC9220 A2", .patch = patch_stac922x },
4038 { .id = 0x83847681, .name = "STAC9220D/9223D A2", .patch = patch_stac922x },
4039 { .id = 0x83847682, .name = "STAC9221 A2", .patch = patch_stac922x },
4040 { .id = 0x83847683, .name = "STAC9221D A2", .patch = patch_stac922x },
22a27c7f
MP		 4041 { .id = 0x83847618, .name = "STAC9227", .patch = patch_stac927x },
4042 { .id = 0x83847619, .name = "STAC9227", .patch = patch_stac927x },
4043 { .id = 0x83847616, .name = "STAC9228", .patch = patch_stac927x },
4044 { .id = 0x83847617, .name = "STAC9228", .patch = patch_stac927x },
4045 { .id = 0x83847614, .name = "STAC9229", .patch = patch_stac927x },
4046 { .id = 0x83847615, .name = "STAC9229", .patch = patch_stac927x },
3cc08dc6
MP		 4047 { .id = 0x83847620, .name = "STAC9274", .patch = patch_stac927x },
4048 { .id = 0x83847621, .name = "STAC9274D", .patch = patch_stac927x },
4049 { .id = 0x83847622, .name = "STAC9273X", .patch = patch_stac927x },
4050 { .id = 0x83847623, .name = "STAC9273D", .patch = patch_stac927x },
4051 { .id = 0x83847624, .name = "STAC9272X", .patch = patch_stac927x },
4052 { .id = 0x83847625, .name = "STAC9272D", .patch = patch_stac927x },
4053 { .id = 0x83847626, .name = "STAC9271X", .patch = patch_stac927x },
4054 { .id = 0x83847627, .name = "STAC9271D", .patch = patch_stac927x },
4055 { .id = 0x83847628, .name = "STAC9274X5NH", .patch = patch_stac927x },
4056 { .id = 0x83847629, .name = "STAC9274D5NH", .patch = patch_stac927x },
8e21c34c
TD		 4057 { .id = 0x83847632, .name = "STAC9202", .patch = patch_stac925x },
4058 { .id = 0x83847633, .name = "STAC9202D", .patch = patch_stac925x },
4059 { .id = 0x83847634, .name = "STAC9250", .patch = patch_stac925x },
4060 { .id = 0x83847635, .name = "STAC9250D", .patch = patch_stac925x },
4061 { .id = 0x83847636, .name = "STAC9251", .patch = patch_stac925x },
4062 { .id = 0x83847637, .name = "STAC9250D", .patch = patch_stac925x },
6d859065
GM		 4063 /* The following does not take into account .id=0x83847661 when subsys =
4064 * 104D0C00 which is STAC9225s. Because of this, some SZ Notebooks are
4065 * currently not fully supported.
4066 */
4067 { .id = 0x83847661, .name = "CXD9872RD/K", .patch = patch_stac9872 },
4068 { .id = 0x83847662, .name = "STAC9872AK", .patch = patch_stac9872 },
4069 { .id = 0x83847664, .name = "CXD9872AKD", .patch = patch_stac9872 },
f3302a59
MP		 4070 { .id = 0x838476a0, .name = "STAC9205", .patch = patch_stac9205 },
4071 { .id = 0x838476a1, .name = "STAC9205D", .patch = patch_stac9205 },
4072 { .id = 0x838476a2, .name = "STAC9204", .patch = patch_stac9205 },
4073 { .id = 0x838476a3, .name = "STAC9204D", .patch = patch_stac9205 },
4074 { .id = 0x838476a4, .name = "STAC9255", .patch = patch_stac9205 },
4075 { .id = 0x838476a5, .name = "STAC9255D", .patch = patch_stac9205 },
4076 { .id = 0x838476a6, .name = "STAC9254", .patch = patch_stac9205 },
4077 { .id = 0x838476a7, .name = "STAC9254D", .patch = patch_stac9205 },
541eee87
MR		 4078 { .id = 0x111d7674, .name = "92HD73D1X5", .patch = patch_stac92hd73xx },
4079 { .id = 0x111d7675, .name = "92HD73C1X5", .patch = patch_stac92hd73xx },
e1f0d669 4080 { .id = 0x111d7676, .name = "92HD73E1X5", .patch = patch_stac92hd73xx },
541eee87
MR		 4081 { .id = 0x111d7608, .name = "92HD71BXX", .patch = patch_stac92hd71bxx },
4082 { .id = 0x111d76b0, .name = "92HD71B8X", .patch = patch_stac92hd71bxx },
4083 { .id = 0x111d76b1, .name = "92HD71B8X", .patch = patch_stac92hd71bxx },
4084 { .id = 0x111d76b2, .name = "92HD71B7X", .patch = patch_stac92hd71bxx },
4085 { .id = 0x111d76b3, .name = "92HD71B7X", .patch = patch_stac92hd71bxx },
4086 { .id = 0x111d76b4, .name = "92HD71B6X", .patch = patch_stac92hd71bxx },
4087 { .id = 0x111d76b5, .name = "92HD71B6X", .patch = patch_stac92hd71bxx },
4088 { .id = 0x111d76b6, .name = "92HD71B5X", .patch = patch_stac92hd71bxx },
4089 { .id = 0x111d76b7, .name = "92HD71B5X", .patch = patch_stac92hd71bxx },
2f2f4251
M		 4090 {} /* terminator */
4091};
Linux kernel - Deliverables
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