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ALSA: 6fire: Convert byte_rev_table uses to bitrev8
[deliverable/linux.git] / sound / pci / ice1712 / ice1712.c
CommitLineData
1da177e4
LT		 1/*
2 * ALSA driver for ICEnsemble ICE1712 (Envy24)
3 *
c1017a4c 4 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
1da177e4
LT		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
3d8cb466 20 */
1da177e4
LT		 21
22/*
23 NOTES:
24 - spdif nonaudio consumer mode does not work (at least with my
25 Sony STR-DB830)
26*/
27
28/*
29 * Changes:
30 *
31 * 2002.09.09 Takashi Iwai <tiwai@suse.de>
32 * split the code to several files. each low-level routine
33 * is stored in the local file and called from registration
34 * function from card_info struct.
35 *
36 * 2002.11.26 James Stafford <jstafford@ampltd.com>
37 * Added support for VT1724 (Envy24HT)
3d8cb466 38 * I have left out support for 176.4 and 192 KHz for the moment.
1da177e4
LT		 39 * I also haven't done anything with the internal S/PDIF transmitter or the MPU-401
40 *
41 * 2003.02.20 Taksahi Iwai <tiwai@suse.de>
42 * Split vt1724 part to an independent driver.
43 * The GPIO is accessed through the callback functions now.
44 *
45 * 2004.03.31 Doug McLain <nostar@comcast.net>
46 * Added support for Event Electronics EZ8 card to hoontech.c.
47 */
48
49
1da177e4
LT		 50#include <linux/delay.h>
51#include <linux/interrupt.h>
52#include <linux/init.h>
53#include <linux/pci.h>
9d2f928d 54#include <linux/dma-mapping.h>
1da177e4 55#include <linux/slab.h>
65a77217 56#include <linux/module.h>
62932df8 57#include <linux/mutex.h>
910638ae 58
1da177e4
LT		 59#include <sound/core.h>
60#include <sound/cs8427.h>
61#include <sound/info.h>
1da177e4 62#include <sound/initval.h>
680ef792 63#include <sound/tlv.h>
1da177e4
LT		 64
65#include <sound/asoundef.h>
66
67#include "ice1712.h"
68
69/* lowlevel routines */
70#include "delta.h"
71#include "ews.h"
72#include "hoontech.h"
73
c1017a4c 74MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
1da177e4
LT		 75MODULE_DESCRIPTION("ICEnsemble ICE1712 (Envy24)");
76MODULE_LICENSE("GPL");
77MODULE_SUPPORTED_DEVICE("{"
78 HOONTECH_DEVICE_DESC
79 DELTA_DEVICE_DESC
80 EWS_DEVICE_DESC
81 "{ICEnsemble,Generic ICE1712},"
82 "{ICEnsemble,Generic Envy24}}");
83
84static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
85static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
a67ff6a5 86static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
1da177e4 87static char *model[SNDRV_CARDS];
a67ff6a5 88static bool omni[SNDRV_CARDS]; /* Delta44 & 66 Omni I/O support */
7c9d440e 89static int cs8427_timeout[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 500}; /* CS8427 S/PDIF transceiver reset timeout value in msec */
01a00e5e 90static int dxr_enable[SNDRV_CARDS]; /* DXR enable for DMX6FIRE */
1da177e4
LT		 91
92module_param_array(index, int, NULL, 0444);
93MODULE_PARM_DESC(index, "Index value for ICE1712 soundcard.");
94module_param_array(id, charp, NULL, 0444);
95MODULE_PARM_DESC(id, "ID string for ICE1712 soundcard.");
96module_param_array(enable, bool, NULL, 0444);
97MODULE_PARM_DESC(enable, "Enable ICE1712 soundcard.");
98module_param_array(omni, bool, NULL, 0444);
99MODULE_PARM_DESC(omni, "Enable Midiman M-Audio Delta Omni I/O support.");
100module_param_array(cs8427_timeout, int, NULL, 0444);
101MODULE_PARM_DESC(cs8427_timeout, "Define reset timeout for cs8427 chip in msec resolution.");
102module_param_array(model, charp, NULL, 0444);
103MODULE_PARM_DESC(model, "Use the given board model.");
531af462 104module_param_array(dxr_enable, int, NULL, 0444);
01a00e5e 105MODULE_PARM_DESC(dxr_enable, "Enable DXR support for Terratec DMX6FIRE.");
1da177e4 106
1da177e4 107
9baa3c34 108static const struct pci_device_id snd_ice1712_ids[] = {
28d27aae 109 { PCI_VDEVICE(ICE, PCI_DEVICE_ID_ICE_1712), 0 }, /* ICE1712 */
1da177e4
LT		 110 { 0, }
111};
112
113MODULE_DEVICE_TABLE(pci, snd_ice1712_ids);
114
6ca308d4
TI		 115static int snd_ice1712_build_pro_mixer(struct snd_ice1712 *ice);
116static int snd_ice1712_build_controls(struct snd_ice1712 *ice);
1da177e4
LT		 117
118static int PRO_RATE_LOCKED;
119static int PRO_RATE_RESET = 1;
120static unsigned int PRO_RATE_DEFAULT = 44100;
121
122/*
123 * Basic I/O
124 */
3d8cb466 125
1da177e4 126/* check whether the clock mode is spdif-in */
6ca308d4 127static inline int is_spdif_master(struct snd_ice1712 *ice)
1da177e4
LT		 128{
129 return (inb(ICEMT(ice, RATE)) & ICE1712_SPDIF_MASTER) ? 1 : 0;
130}
131
6ca308d4 132static inline int is_pro_rate_locked(struct snd_ice1712 *ice)
1da177e4
LT		 133{
134 return is_spdif_master(ice) || PRO_RATE_LOCKED;
135}
136
3d8cb466 137static inline void snd_ice1712_ds_write(struct snd_ice1712 *ice, u8 channel, u8 addr, u32 data)
1da177e4
LT		 138{
139 outb((channel << 4) | addr, ICEDS(ice, INDEX));
140 outl(data, ICEDS(ice, DATA));
141}
142
3d8cb466 143static inline u32 snd_ice1712_ds_read(struct snd_ice1712 *ice, u8 channel, u8 addr)
1da177e4
LT		 144{
145 outb((channel << 4) | addr, ICEDS(ice, INDEX));
146 return inl(ICEDS(ice, DATA));
147}
148
6ca308d4 149static void snd_ice1712_ac97_write(struct snd_ac97 *ac97,
1da177e4
LT		 150 unsigned short reg,
151 unsigned short val)
152{
6ca308d4 153 struct snd_ice1712 *ice = ac97->private_data;
1da177e4
LT		 154 int tm;
155 unsigned char old_cmd = 0;
156
157 for (tm = 0; tm < 0x10000; tm++) {
158 old_cmd = inb(ICEREG(ice, AC97_CMD));
159 if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
160 continue;
161 if (!(old_cmd & ICE1712_AC97_READY))
162 continue;
163 break;
164 }
165 outb(reg, ICEREG(ice, AC97_INDEX));
166 outw(val, ICEREG(ice, AC97_DATA));
167 old_cmd &= ~(ICE1712_AC97_PBK_VSR | ICE1712_AC97_CAP_VSR);
168 outb(old_cmd | ICE1712_AC97_WRITE, ICEREG(ice, AC97_CMD));
169 for (tm = 0; tm < 0x10000; tm++)
170 if ((inb(ICEREG(ice, AC97_CMD)) & ICE1712_AC97_WRITE) == 0)
171 break;
172}
173
6ca308d4 174static unsigned short snd_ice1712_ac97_read(struct snd_ac97 *ac97,
1da177e4
LT		 175 unsigned short reg)
176{
6ca308d4 177 struct snd_ice1712 *ice = ac97->private_data;
1da177e4
LT		 178 int tm;
179 unsigned char old_cmd = 0;
180
181 for (tm = 0; tm < 0x10000; tm++) {
182 old_cmd = inb(ICEREG(ice, AC97_CMD));
183 if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
184 continue;
185 if (!(old_cmd & ICE1712_AC97_READY))
186 continue;
187 break;
188 }
189 outb(reg, ICEREG(ice, AC97_INDEX));
190 outb(old_cmd | ICE1712_AC97_READ, ICEREG(ice, AC97_CMD));
191 for (tm = 0; tm < 0x10000; tm++)
192 if ((inb(ICEREG(ice, AC97_CMD)) & ICE1712_AC97_READ) == 0)
193 break;
194 if (tm >= 0x10000) /* timeout */
195 return ~0;
196 return inw(ICEREG(ice, AC97_DATA));
197}
198
199/*
200 * pro ac97 section
201 */
202
6ca308d4 203static void snd_ice1712_pro_ac97_write(struct snd_ac97 *ac97,
1da177e4
LT		 204 unsigned short reg,
205 unsigned short val)
206{
6ca308d4 207 struct snd_ice1712 *ice = ac97->private_data;
1da177e4
LT		 208 int tm;
209 unsigned char old_cmd = 0;
210
211 for (tm = 0; tm < 0x10000; tm++) {
212 old_cmd = inb(ICEMT(ice, AC97_CMD));
213 if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
214 continue;
215 if (!(old_cmd & ICE1712_AC97_READY))
216 continue;
217 break;
218 }
219 outb(reg, ICEMT(ice, AC97_INDEX));
220 outw(val, ICEMT(ice, AC97_DATA));
221 old_cmd &= ~(ICE1712_AC97_PBK_VSR | ICE1712_AC97_CAP_VSR);
222 outb(old_cmd | ICE1712_AC97_WRITE, ICEMT(ice, AC97_CMD));
223 for (tm = 0; tm < 0x10000; tm++)
224 if ((inb(ICEMT(ice, AC97_CMD)) & ICE1712_AC97_WRITE) == 0)
225 break;
226}
227
228
6ca308d4 229static unsigned short snd_ice1712_pro_ac97_read(struct snd_ac97 *ac97,
1da177e4
LT		 230 unsigned short reg)
231{
6ca308d4 232 struct snd_ice1712 *ice = ac97->private_data;
1da177e4
LT		 233 int tm;
234 unsigned char old_cmd = 0;
235
236 for (tm = 0; tm < 0x10000; tm++) {
237 old_cmd = inb(ICEMT(ice, AC97_CMD));
238 if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
239 continue;
240 if (!(old_cmd & ICE1712_AC97_READY))
241 continue;
242 break;
243 }
244 outb(reg, ICEMT(ice, AC97_INDEX));
245 outb(old_cmd | ICE1712_AC97_READ, ICEMT(ice, AC97_CMD));
246 for (tm = 0; tm < 0x10000; tm++)
247 if ((inb(ICEMT(ice, AC97_CMD)) & ICE1712_AC97_READ) == 0)
248 break;
249 if (tm >= 0x10000) /* timeout */
250 return ~0;
251 return inw(ICEMT(ice, AC97_DATA));
252}
253
254/*
255 * consumer ac97 digital mix
256 */
a5ce8890 257#define snd_ice1712_digmix_route_ac97_info snd_ctl_boolean_mono_info
1da177e4 258
6ca308d4 259static int snd_ice1712_digmix_route_ac97_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 260{
6ca308d4 261 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
3d8cb466 262
1da177e4
LT		 263 ucontrol->value.integer.value[0] = inb(ICEMT(ice, MONITOR_ROUTECTRL)) & ICE1712_ROUTE_AC97 ? 1 : 0;
264 return 0;
265}
266
6ca308d4 267static int snd_ice1712_digmix_route_ac97_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 268{
6ca308d4 269 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4 270 unsigned char val, nval;
3d8cb466 271
1da177e4
LT		 272 spin_lock_irq(&ice->reg_lock);
273 val = inb(ICEMT(ice, MONITOR_ROUTECTRL));
274 nval = val & ~ICE1712_ROUTE_AC97;
3d8cb466
AB		 275 if (ucontrol->value.integer.value[0])
276 nval |= ICE1712_ROUTE_AC97;
1da177e4
LT		 277 outb(nval, ICEMT(ice, MONITOR_ROUTECTRL));
278 spin_unlock_irq(&ice->reg_lock);
279 return val != nval;
280}
281
e23e7a14 282static struct snd_kcontrol_new snd_ice1712_mixer_digmix_route_ac97 = {
1da177e4
LT		 283 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
284 .name = "Digital Mixer To AC97",
285 .info = snd_ice1712_digmix_route_ac97_info,
286 .get = snd_ice1712_digmix_route_ac97_get,
287 .put = snd_ice1712_digmix_route_ac97_put,
288};
289
290
291/*
292 * gpio operations
293 */
6ca308d4 294static void snd_ice1712_set_gpio_dir(struct snd_ice1712 *ice, unsigned int data)
1da177e4
LT		 295{
296 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION, data);
297 inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
298}
299
49470306
PH		 300static unsigned int snd_ice1712_get_gpio_dir(struct snd_ice1712 *ice)
301{
302 return snd_ice1712_read(ice, ICE1712_IREG_GPIO_DIRECTION);
303}
304
305static unsigned int snd_ice1712_get_gpio_mask(struct snd_ice1712 *ice)
306{
307 return snd_ice1712_read(ice, ICE1712_IREG_GPIO_WRITE_MASK);
308}
309
6ca308d4 310static void snd_ice1712_set_gpio_mask(struct snd_ice1712 *ice, unsigned int data)
1da177e4
LT		 311{
312 snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, data);
313 inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
314}
315
6ca308d4 316static unsigned int snd_ice1712_get_gpio_data(struct snd_ice1712 *ice)
1da177e4
LT		 317{
318 return snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA);
319}
320
6ca308d4 321static void snd_ice1712_set_gpio_data(struct snd_ice1712 *ice, unsigned int val)
1da177e4
LT		 322{
323 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, val);
324 inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
325}
326
1da177e4
LT		 327/*
328 *
329 * CS8427 interface
330 *
331 */
332
333/*
334 * change the input clock selection
335 * spdif_clock = 1 - IEC958 input, 0 - Envy24
336 */
6ca308d4 337static int snd_ice1712_cs8427_set_input_clock(struct snd_ice1712 *ice, int spdif_clock)
1da177e4
LT		 338{
339 unsigned char reg[2] = { 0x80 | 4, 0 }; /* CS8427 auto increment | register number 4 + data */
340 unsigned char val, nval;
341 int res = 0;
3d8cb466 342
1da177e4
LT		 343 snd_i2c_lock(ice->i2c);
344 if (snd_i2c_sendbytes(ice->cs8427, reg, 1) != 1) {
345 snd_i2c_unlock(ice->i2c);
346 return -EIO;
347 }
348 if (snd_i2c_readbytes(ice->cs8427, &val, 1) != 1) {
349 snd_i2c_unlock(ice->i2c);
350 return -EIO;
351 }
352 nval = val & 0xf0;
353 if (spdif_clock)
354 nval |= 0x01;
355 else
356 nval |= 0x04;
357 if (val != nval) {
358 reg[1] = nval;
359 if (snd_i2c_sendbytes(ice->cs8427, reg, 2) != 2) {
360 res = -EIO;
361 } else {
362 res++;
363 }
364 }
365 snd_i2c_unlock(ice->i2c);
366 return res;
367}
368
369/*
370 * spdif callbacks
371 */
6ca308d4 372static void open_cs8427(struct snd_ice1712 *ice, struct snd_pcm_substream *substream)
1da177e4
LT		 373{
374 snd_cs8427_iec958_active(ice->cs8427, 1);
375}
376
6ca308d4 377static void close_cs8427(struct snd_ice1712 *ice, struct snd_pcm_substream *substream)
1da177e4
LT		 378{
379 snd_cs8427_iec958_active(ice->cs8427, 0);
380}
381
6ca308d4 382static void setup_cs8427(struct snd_ice1712 *ice, int rate)
1da177e4
LT		 383{
384 snd_cs8427_iec958_pcm(ice->cs8427, rate);
385}
386
387/*
388 * create and initialize callbacks for cs8427 interface
389 */
e23e7a14 390int snd_ice1712_init_cs8427(struct snd_ice1712 *ice, int addr)
1da177e4
LT		 391{
392 int err;
393
3d8cb466
AB		 394 err = snd_cs8427_create(ice->i2c, addr,
395 (ice->cs8427_timeout * HZ) / 1000, &ice->cs8427);
396 if (err < 0) {
6dfb5aff 397 dev_err(ice->card->dev, "CS8427 initialization failed\n");
1da177e4
LT		 398 return err;
399 }
400 ice->spdif.ops.open = open_cs8427;
401 ice->spdif.ops.close = close_cs8427;
402 ice->spdif.ops.setup_rate = setup_cs8427;
403 return 0;
404}
405
e957ebf1
JK		 406static void snd_ice1712_set_input_clock_source(struct snd_ice1712 *ice, int spdif_is_master)
407{
3d8cb466
AB		 408 /* change CS8427 clock source too */
409 if (ice->cs8427)
410 snd_ice1712_cs8427_set_input_clock(ice, spdif_is_master);
e957ebf1
JK		 411 /* notify ak4524 chip as well */
412 if (spdif_is_master) {
413 unsigned int i;
414 for (i = 0; i < ice->akm_codecs; i++) {
415 if (ice->akm[i].ops.set_rate_val)
416 ice->akm[i].ops.set_rate_val(&ice->akm[i], 0);
417 }
418 }
419}
1da177e4
LT		 420
421/*
422 * Interrupt handler
423 */
424
7d12e780 425static irqreturn_t snd_ice1712_interrupt(int irq, void *dev_id)
1da177e4 426{
6ca308d4 427 struct snd_ice1712 *ice = dev_id;
1da177e4
LT		 428 unsigned char status;
429 int handled = 0;
430
431 while (1) {
432 status = inb(ICEREG(ice, IRQSTAT));
433 if (status == 0)
434 break;
435 handled = 1;
436 if (status & ICE1712_IRQ_MPU1) {
437 if (ice->rmidi[0])
7d12e780 438 snd_mpu401_uart_interrupt(irq, ice->rmidi[0]->private_data);
1da177e4
LT		 439 outb(ICE1712_IRQ_MPU1, ICEREG(ice, IRQSTAT));
440 status &= ~ICE1712_IRQ_MPU1;
441 }
442 if (status & ICE1712_IRQ_TIMER)
443 outb(ICE1712_IRQ_TIMER, ICEREG(ice, IRQSTAT));
444 if (status & ICE1712_IRQ_MPU2) {
445 if (ice->rmidi[1])
7d12e780 446 snd_mpu401_uart_interrupt(irq, ice->rmidi[1]->private_data);
1da177e4
LT		 447 outb(ICE1712_IRQ_MPU2, ICEREG(ice, IRQSTAT));
448 status &= ~ICE1712_IRQ_MPU2;
449 }
450 if (status & ICE1712_IRQ_PROPCM) {
451 unsigned char mtstat = inb(ICEMT(ice, IRQ));
452 if (mtstat & ICE1712_MULTI_PBKSTATUS) {
453 if (ice->playback_pro_substream)
454 snd_pcm_period_elapsed(ice->playback_pro_substream);
455 outb(ICE1712_MULTI_PBKSTATUS, ICEMT(ice, IRQ));
456 }
457 if (mtstat & ICE1712_MULTI_CAPSTATUS) {
458 if (ice->capture_pro_substream)
459 snd_pcm_period_elapsed(ice->capture_pro_substream);
460 outb(ICE1712_MULTI_CAPSTATUS, ICEMT(ice, IRQ));
461 }
462 }
463 if (status & ICE1712_IRQ_FM)
464 outb(ICE1712_IRQ_FM, ICEREG(ice, IRQSTAT));
465 if (status & ICE1712_IRQ_PBKDS) {
466 u32 idx;
467 u16 pbkstatus;
6ca308d4 468 struct snd_pcm_substream *substream;
1da177e4 469 pbkstatus = inw(ICEDS(ice, INTSTAT));
6dfb5aff 470 /* dev_dbg(ice->card->dev, "pbkstatus = 0x%x\n", pbkstatus); */
1da177e4
LT		 471 for (idx = 0; idx < 6; idx++) {
472 if ((pbkstatus & (3 << (idx * 2))) == 0)
473 continue;
3d8cb466
AB		 474 substream = ice->playback_con_substream_ds[idx];
475 if (substream != NULL)
1da177e4
LT		 476 snd_pcm_period_elapsed(substream);
477 outw(3 << (idx * 2), ICEDS(ice, INTSTAT));
478 }
479 outb(ICE1712_IRQ_PBKDS, ICEREG(ice, IRQSTAT));
480 }
481 if (status & ICE1712_IRQ_CONCAP) {
482 if (ice->capture_con_substream)
483 snd_pcm_period_elapsed(ice->capture_con_substream);
484 outb(ICE1712_IRQ_CONCAP, ICEREG(ice, IRQSTAT));
485 }
486 if (status & ICE1712_IRQ_CONPBK) {
487 if (ice->playback_con_substream)
488 snd_pcm_period_elapsed(ice->playback_con_substream);
489 outb(ICE1712_IRQ_CONPBK, ICEREG(ice, IRQSTAT));
490 }
491 }
492 return IRQ_RETVAL(handled);
493}
494
495
496/*
497 * PCM part - misc
498 */
499
6ca308d4
TI		 500static int snd_ice1712_hw_params(struct snd_pcm_substream *substream,
501 struct snd_pcm_hw_params *hw_params)
1da177e4
LT		 502{
503 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
504}
505
6ca308d4 506static int snd_ice1712_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 507{
508 return snd_pcm_lib_free_pages(substream);
509}
510
511/*
512 * PCM part - consumer I/O
513 */
514
6ca308d4 515static int snd_ice1712_playback_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 516 int cmd)
517{
6ca308d4 518 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 519 int result = 0;
520 u32 tmp;
3d8cb466 521
1da177e4
LT		 522 spin_lock(&ice->reg_lock);
523 tmp = snd_ice1712_read(ice, ICE1712_IREG_PBK_CTRL);
524 if (cmd == SNDRV_PCM_TRIGGER_START) {
525 tmp |= 1;
526 } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
527 tmp &= ~1;
528 } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) {
529 tmp |= 2;
530 } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE) {
531 tmp &= ~2;
532 } else {
533 result = -EINVAL;
534 }
535 snd_ice1712_write(ice, ICE1712_IREG_PBK_CTRL, tmp);
536 spin_unlock(&ice->reg_lock);
537 return result;
538}
539
6ca308d4 540static int snd_ice1712_playback_ds_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 541 int cmd)
542{
6ca308d4 543 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 544 int result = 0;
545 u32 tmp;
3d8cb466 546
1da177e4
LT		 547 spin_lock(&ice->reg_lock);
548 tmp = snd_ice1712_ds_read(ice, substream->number * 2, ICE1712_DSC_CONTROL);
549 if (cmd == SNDRV_PCM_TRIGGER_START) {
550 tmp |= 1;
551 } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
552 tmp &= ~1;
553 } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) {
554 tmp |= 2;
555 } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE) {
556 tmp &= ~2;
557 } else {
558 result = -EINVAL;
559 }
560 snd_ice1712_ds_write(ice, substream->number * 2, ICE1712_DSC_CONTROL, tmp);
561 spin_unlock(&ice->reg_lock);
562 return result;
563}
564
6ca308d4 565static int snd_ice1712_capture_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 566 int cmd)
567{
6ca308d4 568 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 569 int result = 0;
570 u8 tmp;
3d8cb466 571
1da177e4
LT		 572 spin_lock(&ice->reg_lock);
573 tmp = snd_ice1712_read(ice, ICE1712_IREG_CAP_CTRL);
574 if (cmd == SNDRV_PCM_TRIGGER_START) {
575 tmp |= 1;
576 } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
577 tmp &= ~1;
578 } else {
579 result = -EINVAL;
580 }
581 snd_ice1712_write(ice, ICE1712_IREG_CAP_CTRL, tmp);
582 spin_unlock(&ice->reg_lock);
583 return result;
584}
585
6ca308d4 586static int snd_ice1712_playback_prepare(struct snd_pcm_substream *substream)
1da177e4 587{
6ca308d4
TI		 588 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
589 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 590 u32 period_size, buf_size, rate, tmp;
591
592 period_size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
593 buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
594 tmp = 0x0000;
595 if (snd_pcm_format_width(runtime->format) == 16)
596 tmp |= 0x10;
597 if (runtime->channels == 2)
598 tmp |= 0x08;
599 rate = (runtime->rate * 8192) / 375;
600 if (rate > 0x000fffff)
601 rate = 0x000fffff;
602 spin_lock_irq(&ice->reg_lock);
603 outb(0, ice->ddma_port + 15);
604 outb(ICE1712_DMA_MODE_WRITE | ICE1712_DMA_AUTOINIT, ice->ddma_port + 0x0b);
605 outl(runtime->dma_addr, ice->ddma_port + 0);
606 outw(buf_size, ice->ddma_port + 4);
607 snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_LO, rate & 0xff);
608 snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_MID, (rate >> 8) & 0xff);
609 snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_HI, (rate >> 16) & 0xff);
610 snd_ice1712_write(ice, ICE1712_IREG_PBK_CTRL, tmp);
611 snd_ice1712_write(ice, ICE1712_IREG_PBK_COUNT_LO, period_size & 0xff);
612 snd_ice1712_write(ice, ICE1712_IREG_PBK_COUNT_HI, period_size >> 8);
613 snd_ice1712_write(ice, ICE1712_IREG_PBK_LEFT, 0);
614 snd_ice1712_write(ice, ICE1712_IREG_PBK_RIGHT, 0);
615 spin_unlock_irq(&ice->reg_lock);
616 return 0;
617}
618
6ca308d4 619static int snd_ice1712_playback_ds_prepare(struct snd_pcm_substream *substream)
1da177e4 620{
6ca308d4
TI		 621 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
622 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 623 u32 period_size, buf_size, rate, tmp, chn;
624
625 period_size = snd_pcm_lib_period_bytes(substream) - 1;
626 buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
627 tmp = 0x0064;
628 if (snd_pcm_format_width(runtime->format) == 16)
629 tmp &= ~0x04;
630 if (runtime->channels == 2)
631 tmp |= 0x08;
632 rate = (runtime->rate * 8192) / 375;
633 if (rate > 0x000fffff)
634 rate = 0x000fffff;
635 ice->playback_con_active_buf[substream->number] = 0;
636 ice->playback_con_virt_addr[substream->number] = runtime->dma_addr;
637 chn = substream->number * 2;
638 spin_lock_irq(&ice->reg_lock);
639 snd_ice1712_ds_write(ice, chn, ICE1712_DSC_ADDR0, runtime->dma_addr);
640 snd_ice1712_ds_write(ice, chn, ICE1712_DSC_COUNT0, period_size);
641 snd_ice1712_ds_write(ice, chn, ICE1712_DSC_ADDR1, runtime->dma_addr + (runtime->periods > 1 ? period_size + 1 : 0));
642 snd_ice1712_ds_write(ice, chn, ICE1712_DSC_COUNT1, period_size);
643 snd_ice1712_ds_write(ice, chn, ICE1712_DSC_RATE, rate);
644 snd_ice1712_ds_write(ice, chn, ICE1712_DSC_VOLUME, 0);
645 snd_ice1712_ds_write(ice, chn, ICE1712_DSC_CONTROL, tmp);
646 if (runtime->channels == 2) {
647 snd_ice1712_ds_write(ice, chn + 1, ICE1712_DSC_RATE, rate);
648 snd_ice1712_ds_write(ice, chn + 1, ICE1712_DSC_VOLUME, 0);
649 }
650 spin_unlock_irq(&ice->reg_lock);
651 return 0;
652}
653
6ca308d4 654static int snd_ice1712_capture_prepare(struct snd_pcm_substream *substream)
1da177e4 655{
6ca308d4
TI		 656 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
657 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 658 u32 period_size, buf_size;
659 u8 tmp;
660
661 period_size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
662 buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
663 tmp = 0x06;
664 if (snd_pcm_format_width(runtime->format) == 16)
665 tmp &= ~0x04;
666 if (runtime->channels == 2)
667 tmp &= ~0x02;
668 spin_lock_irq(&ice->reg_lock);
669 outl(ice->capture_con_virt_addr = runtime->dma_addr, ICEREG(ice, CONCAP_ADDR));
670 outw(buf_size, ICEREG(ice, CONCAP_COUNT));
671 snd_ice1712_write(ice, ICE1712_IREG_CAP_COUNT_HI, period_size >> 8);
672 snd_ice1712_write(ice, ICE1712_IREG_CAP_COUNT_LO, period_size & 0xff);
673 snd_ice1712_write(ice, ICE1712_IREG_CAP_CTRL, tmp);
674 spin_unlock_irq(&ice->reg_lock);
675 snd_ac97_set_rate(ice->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
676 return 0;
677}
678
6ca308d4 679static snd_pcm_uframes_t snd_ice1712_playback_pointer(struct snd_pcm_substream *substream)
1da177e4 680{
6ca308d4
TI		 681 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
682 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 683 size_t ptr;
684
685 if (!(snd_ice1712_read(ice, ICE1712_IREG_PBK_CTRL) & 1))
686 return 0;
687 ptr = runtime->buffer_size - inw(ice->ddma_port + 4);
4f8e9400 688 ptr = bytes_to_frames(substream->runtime, ptr);
1da177e4
LT		 689 if (ptr == runtime->buffer_size)
690 ptr = 0;
4f8e9400 691 return ptr;
1da177e4
LT		 692}
693
6ca308d4 694static snd_pcm_uframes_t snd_ice1712_playback_ds_pointer(struct snd_pcm_substream *substream)
1da177e4 695{
6ca308d4 696 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 697 u8 addr;
698 size_t ptr;
699
700 if (!(snd_ice1712_ds_read(ice, substream->number * 2, ICE1712_DSC_CONTROL) & 1))
701 return 0;
702 if (ice->playback_con_active_buf[substream->number])
703 addr = ICE1712_DSC_ADDR1;
704 else
705 addr = ICE1712_DSC_ADDR0;
706 ptr = snd_ice1712_ds_read(ice, substream->number * 2, addr) -
707 ice->playback_con_virt_addr[substream->number];
4f8e9400 708 ptr = bytes_to_frames(substream->runtime, ptr);
1da177e4
LT		 709 if (ptr == substream->runtime->buffer_size)
710 ptr = 0;
4f8e9400 711 return ptr;
1da177e4
LT		 712}
713
6ca308d4 714static snd_pcm_uframes_t snd_ice1712_capture_pointer(struct snd_pcm_substream *substream)
1da177e4 715{
6ca308d4 716 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 717 size_t ptr;
718
719 if (!(snd_ice1712_read(ice, ICE1712_IREG_CAP_CTRL) & 1))
720 return 0;
721 ptr = inl(ICEREG(ice, CONCAP_ADDR)) - ice->capture_con_virt_addr;
4f8e9400 722 ptr = bytes_to_frames(substream->runtime, ptr);
1da177e4
LT		 723 if (ptr == substream->runtime->buffer_size)
724 ptr = 0;
4f8e9400 725 return ptr;
1da177e4
LT		 726}
727
3d8cb466 728static const struct snd_pcm_hardware snd_ice1712_playback = {
1da177e4
LT		 729 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
730 SNDRV_PCM_INFO_BLOCK_TRANSFER |
731 SNDRV_PCM_INFO_MMAP_VALID |
732 SNDRV_PCM_INFO_PAUSE),
733 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
734 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
735 .rate_min = 4000,
736 .rate_max = 48000,
737 .channels_min = 1,
738 .channels_max = 2,
739 .buffer_bytes_max = (64*1024),
740 .period_bytes_min = 64,
741 .period_bytes_max = (64*1024),
742 .periods_min = 1,
743 .periods_max = 1024,
744 .fifo_size = 0,
745};
746
3d8cb466 747static const struct snd_pcm_hardware snd_ice1712_playback_ds = {
1da177e4
LT		 748 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
749 SNDRV_PCM_INFO_BLOCK_TRANSFER |
750 SNDRV_PCM_INFO_MMAP_VALID |
751 SNDRV_PCM_INFO_PAUSE),
752 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
753 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
754 .rate_min = 4000,
755 .rate_max = 48000,
756 .channels_min = 1,
757 .channels_max = 2,
758 .buffer_bytes_max = (128*1024),
759 .period_bytes_min = 64,
760 .period_bytes_max = (128*1024),
761 .periods_min = 2,
762 .periods_max = 2,
763 .fifo_size = 0,
764};
765
3d8cb466 766static const struct snd_pcm_hardware snd_ice1712_capture = {
1da177e4
LT		 767 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
768 SNDRV_PCM_INFO_BLOCK_TRANSFER |
769 SNDRV_PCM_INFO_MMAP_VALID),
770 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
771 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
772 .rate_min = 4000,
773 .rate_max = 48000,
774 .channels_min = 1,
775 .channels_max = 2,
776 .buffer_bytes_max = (64*1024),
777 .period_bytes_min = 64,
778 .period_bytes_max = (64*1024),
779 .periods_min = 1,
780 .periods_max = 1024,
781 .fifo_size = 0,
782};
783
6ca308d4 784static int snd_ice1712_playback_open(struct snd_pcm_substream *substream)
1da177e4 785{
6ca308d4
TI		 786 struct snd_pcm_runtime *runtime = substream->runtime;
787 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 788
789 ice->playback_con_substream = substream;
790 runtime->hw = snd_ice1712_playback;
791 return 0;
792}
793
6ca308d4 794static int snd_ice1712_playback_ds_open(struct snd_pcm_substream *substream)
1da177e4 795{
6ca308d4
TI		 796 struct snd_pcm_runtime *runtime = substream->runtime;
797 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 798 u32 tmp;
799
800 ice->playback_con_substream_ds[substream->number] = substream;
801 runtime->hw = snd_ice1712_playback_ds;
3d8cb466 802 spin_lock_irq(&ice->reg_lock);
1da177e4
LT		 803 tmp = inw(ICEDS(ice, INTMASK)) & ~(1 << (substream->number * 2));
804 outw(tmp, ICEDS(ice, INTMASK));
805 spin_unlock_irq(&ice->reg_lock);
806 return 0;
807}
808
6ca308d4 809static int snd_ice1712_capture_open(struct snd_pcm_substream *substream)
1da177e4 810{
6ca308d4
TI		 811 struct snd_pcm_runtime *runtime = substream->runtime;
812 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 813
814 ice->capture_con_substream = substream;
815 runtime->hw = snd_ice1712_capture;
816 runtime->hw.rates = ice->ac97->rates[AC97_RATES_ADC];
817 if (!(runtime->hw.rates & SNDRV_PCM_RATE_8000))
818 runtime->hw.rate_min = 48000;
819 return 0;
820}
821
6ca308d4 822static int snd_ice1712_playback_close(struct snd_pcm_substream *substream)
1da177e4 823{
6ca308d4 824 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 825
826 ice->playback_con_substream = NULL;
827 return 0;
828}
829
6ca308d4 830static int snd_ice1712_playback_ds_close(struct snd_pcm_substream *substream)
1da177e4 831{
6ca308d4 832 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 833 u32 tmp;
834
3d8cb466 835 spin_lock_irq(&ice->reg_lock);
1da177e4
LT		 836 tmp = inw(ICEDS(ice, INTMASK)) | (3 << (substream->number * 2));
837 outw(tmp, ICEDS(ice, INTMASK));
838 spin_unlock_irq(&ice->reg_lock);
839 ice->playback_con_substream_ds[substream->number] = NULL;
840 return 0;
841}
842
6ca308d4 843static int snd_ice1712_capture_close(struct snd_pcm_substream *substream)
1da177e4 844{
6ca308d4 845 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 846
847 ice->capture_con_substream = NULL;
848 return 0;
849}
850
6ca308d4 851static struct snd_pcm_ops snd_ice1712_playback_ops = {
1da177e4
LT		 852 .open = snd_ice1712_playback_open,
853 .close = snd_ice1712_playback_close,
854 .ioctl = snd_pcm_lib_ioctl,
855 .hw_params = snd_ice1712_hw_params,
856 .hw_free = snd_ice1712_hw_free,
857 .prepare = snd_ice1712_playback_prepare,
858 .trigger = snd_ice1712_playback_trigger,
859 .pointer = snd_ice1712_playback_pointer,
860};
861
6ca308d4 862static struct snd_pcm_ops snd_ice1712_playback_ds_ops = {
1da177e4
LT		 863 .open = snd_ice1712_playback_ds_open,
864 .close = snd_ice1712_playback_ds_close,
865 .ioctl = snd_pcm_lib_ioctl,
866 .hw_params = snd_ice1712_hw_params,
867 .hw_free = snd_ice1712_hw_free,
868 .prepare = snd_ice1712_playback_ds_prepare,
869 .trigger = snd_ice1712_playback_ds_trigger,
870 .pointer = snd_ice1712_playback_ds_pointer,
871};
872
6ca308d4 873static struct snd_pcm_ops snd_ice1712_capture_ops = {
1da177e4
LT		 874 .open = snd_ice1712_capture_open,
875 .close = snd_ice1712_capture_close,
876 .ioctl = snd_pcm_lib_ioctl,
877 .hw_params = snd_ice1712_hw_params,
878 .hw_free = snd_ice1712_hw_free,
879 .prepare = snd_ice1712_capture_prepare,
880 .trigger = snd_ice1712_capture_trigger,
881 .pointer = snd_ice1712_capture_pointer,
882};
883
e23e7a14 884static int snd_ice1712_pcm(struct snd_ice1712 *ice, int device, struct snd_pcm **rpcm)
1da177e4 885{
6ca308d4 886 struct snd_pcm *pcm;
1da177e4
LT		 887 int err;
888
889 if (rpcm)
890 *rpcm = NULL;
891 err = snd_pcm_new(ice->card, "ICE1712 consumer", device, 1, 1, &pcm);
892 if (err < 0)
893 return err;
894
895 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_ops);
896 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ice1712_capture_ops);
897
898 pcm->private_data = ice;
1da177e4
LT		 899 pcm->info_flags = 0;
900 strcpy(pcm->name, "ICE1712 consumer");
901 ice->pcm = pcm;
902
903 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
904 snd_dma_pci_data(ice->pci), 64*1024, 64*1024);
905
906 if (rpcm)
907 *rpcm = pcm;
908
6dfb5aff
TI		 909 dev_warn(ice->card->dev,
910 "Consumer PCM code does not work well at the moment --jk\n");
1da177e4
LT		 911
912 return 0;
913}
914
e23e7a14 915static int snd_ice1712_pcm_ds(struct snd_ice1712 *ice, int device, struct snd_pcm **rpcm)
1da177e4 916{
6ca308d4 917 struct snd_pcm *pcm;
1da177e4
LT		 918 int err;
919
920 if (rpcm)
921 *rpcm = NULL;
922 err = snd_pcm_new(ice->card, "ICE1712 consumer (DS)", device, 6, 0, &pcm);
923 if (err < 0)
924 return err;
925
926 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_ds_ops);
927
928 pcm->private_data = ice;
1da177e4
LT		 929 pcm->info_flags = 0;
930 strcpy(pcm->name, "ICE1712 consumer (DS)");
931 ice->pcm_ds = pcm;
932
933 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
934 snd_dma_pci_data(ice->pci), 64*1024, 128*1024);
935
936 if (rpcm)
937 *rpcm = pcm;
938
939 return 0;
940}
941
942/*
943 * PCM code - professional part (multitrack)
944 */
945
946static unsigned int rates[] = { 8000, 9600, 11025, 12000, 16000, 22050, 24000,
947 32000, 44100, 48000, 64000, 88200, 96000 };
948
6ca308d4 949static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
1da177e4
LT		 950 .count = ARRAY_SIZE(rates),
951 .list = rates,
952 .mask = 0,
953};
954
6ca308d4 955static int snd_ice1712_pro_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 956 int cmd)
957{
6ca308d4 958 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 959 switch (cmd) {
960 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
961 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
962 {
963 unsigned int what;
964 unsigned int old;
965 if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
966 return -EINVAL;
967 what = ICE1712_PLAYBACK_PAUSE;
968 snd_pcm_trigger_done(substream, substream);
969 spin_lock(&ice->reg_lock);
970 old = inl(ICEMT(ice, PLAYBACK_CONTROL));
971 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
972 old |= what;
973 else
974 old &= ~what;
975 outl(old, ICEMT(ice, PLAYBACK_CONTROL));
976 spin_unlock(&ice->reg_lock);
977 break;
978 }
979 case SNDRV_PCM_TRIGGER_START:
980 case SNDRV_PCM_TRIGGER_STOP:
981 {
982 unsigned int what = 0;
983 unsigned int old;
6ca308d4 984 struct snd_pcm_substream *s;
1da177e4 985
ef991b95 986 snd_pcm_group_for_each_entry(s, substream) {
1da177e4
LT		 987 if (s == ice->playback_pro_substream) {
988 what |= ICE1712_PLAYBACK_START;
989 snd_pcm_trigger_done(s, substream);
990 } else if (s == ice->capture_pro_substream) {
991 what |= ICE1712_CAPTURE_START_SHADOW;
992 snd_pcm_trigger_done(s, substream);
993 }
994 }
995 spin_lock(&ice->reg_lock);
996 old = inl(ICEMT(ice, PLAYBACK_CONTROL));
997 if (cmd == SNDRV_PCM_TRIGGER_START)
998 old |= what;
999 else
1000 old &= ~what;
1001 outl(old, ICEMT(ice, PLAYBACK_CONTROL));
1002 spin_unlock(&ice->reg_lock);
1003 break;
1004 }
1005 default:
1006 return -EINVAL;
1007 }
1008 return 0;
1009}
1010
1011/*
1012 */
6ca308d4 1013static void snd_ice1712_set_pro_rate(struct snd_ice1712 *ice, unsigned int rate, int force)
1da177e4
LT		 1014{
1015 unsigned long flags;
1016 unsigned char val, old;
1017 unsigned int i;
1018
1019 switch (rate) {
1020 case 8000: val = 6; break;
1021 case 9600: val = 3; break;
1022 case 11025: val = 10; break;
1023 case 12000: val = 2; break;
1024 case 16000: val = 5; break;
1025 case 22050: val = 9; break;
1026 case 24000: val = 1; break;
1027 case 32000: val = 4; break;
1028 case 44100: val = 8; break;
1029 case 48000: val = 0; break;
1030 case 64000: val = 15; break;
1031 case 88200: val = 11; break;
1032 case 96000: val = 7; break;
1033 default:
1034 snd_BUG();
1035 val = 0;
1036 rate = 48000;
1037 break;
1038 }
1039
1040 spin_lock_irqsave(&ice->reg_lock, flags);
1041 if (inb(ICEMT(ice, PLAYBACK_CONTROL)) & (ICE1712_CAPTURE_START_SHADOW|
1042 ICE1712_PLAYBACK_PAUSE|
1043 ICE1712_PLAYBACK_START)) {
3d8cb466 1044__out:
1da177e4
LT		 1045 spin_unlock_irqrestore(&ice->reg_lock, flags);
1046 return;
1047 }
1048 if (!force && is_pro_rate_locked(ice))
1049 goto __out;
1050
3d8cb466 1051 old = inb(ICEMT(ice, RATE));
1da177e4
LT		 1052 if (!force && old == val)
1053 goto __out;
6ea0cae7
OZ		 1054
1055 ice->cur_rate = rate;
1da177e4
LT		 1056 outb(val, ICEMT(ice, RATE));
1057 spin_unlock_irqrestore(&ice->reg_lock, flags);
1058
1059 if (ice->gpio.set_pro_rate)
1060 ice->gpio.set_pro_rate(ice, rate);
1061 for (i = 0; i < ice->akm_codecs; i++) {
1062 if (ice->akm[i].ops.set_rate_val)
1063 ice->akm[i].ops.set_rate_val(&ice->akm[i], rate);
1064 }
1065 if (ice->spdif.ops.setup_rate)
1066 ice->spdif.ops.setup_rate(ice, rate);
1067}
1068
6ca308d4 1069static int snd_ice1712_playback_pro_prepare(struct snd_pcm_substream *substream)
1da177e4 1070{
6ca308d4 1071 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 1072
1073 ice->playback_pro_size = snd_pcm_lib_buffer_bytes(substream);
1074 spin_lock_irq(&ice->reg_lock);
1075 outl(substream->runtime->dma_addr, ICEMT(ice, PLAYBACK_ADDR));
1076 outw((ice->playback_pro_size >> 2) - 1, ICEMT(ice, PLAYBACK_SIZE));
1077 outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1, ICEMT(ice, PLAYBACK_COUNT));
1078 spin_unlock_irq(&ice->reg_lock);
1079
1080 return 0;
1081}
1082
6ca308d4
TI		 1083static int snd_ice1712_playback_pro_hw_params(struct snd_pcm_substream *substream,
1084 struct snd_pcm_hw_params *hw_params)
1da177e4 1085{
6ca308d4 1086 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 1087
1088 snd_ice1712_set_pro_rate(ice, params_rate(hw_params), 0);
1089 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
1090}
1091
6ca308d4 1092static int snd_ice1712_capture_pro_prepare(struct snd_pcm_substream *substream)
1da177e4 1093{
6ca308d4 1094 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 1095
1096 ice->capture_pro_size = snd_pcm_lib_buffer_bytes(substream);
1097 spin_lock_irq(&ice->reg_lock);
1098 outl(substream->runtime->dma_addr, ICEMT(ice, CAPTURE_ADDR));
1099 outw((ice->capture_pro_size >> 2) - 1, ICEMT(ice, CAPTURE_SIZE));
1100 outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1, ICEMT(ice, CAPTURE_COUNT));
1101 spin_unlock_irq(&ice->reg_lock);
1102 return 0;
1103}
1104
6ca308d4
TI		 1105static int snd_ice1712_capture_pro_hw_params(struct snd_pcm_substream *substream,
1106 struct snd_pcm_hw_params *hw_params)
1da177e4 1107{
6ca308d4 1108 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 1109
1110 snd_ice1712_set_pro_rate(ice, params_rate(hw_params), 0);
1111 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
1112}
1113
6ca308d4 1114static snd_pcm_uframes_t snd_ice1712_playback_pro_pointer(struct snd_pcm_substream *substream)
1da177e4 1115{
6ca308d4 1116 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 1117 size_t ptr;
1118
1119 if (!(inl(ICEMT(ice, PLAYBACK_CONTROL)) & ICE1712_PLAYBACK_START))
1120 return 0;
1121 ptr = ice->playback_pro_size - (inw(ICEMT(ice, PLAYBACK_SIZE)) << 2);
4f8e9400 1122 ptr = bytes_to_frames(substream->runtime, ptr);
1da177e4
LT		 1123 if (ptr == substream->runtime->buffer_size)
1124 ptr = 0;
4f8e9400 1125 return ptr;
1da177e4
LT		 1126}
1127
6ca308d4 1128static snd_pcm_uframes_t snd_ice1712_capture_pro_pointer(struct snd_pcm_substream *substream)
1da177e4 1129{
6ca308d4 1130 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 1131 size_t ptr;
1132
1133 if (!(inl(ICEMT(ice, PLAYBACK_CONTROL)) & ICE1712_CAPTURE_START_SHADOW))
1134 return 0;
1135 ptr = ice->capture_pro_size - (inw(ICEMT(ice, CAPTURE_SIZE)) << 2);
4f8e9400 1136 ptr = bytes_to_frames(substream->runtime, ptr);
1da177e4
LT		 1137 if (ptr == substream->runtime->buffer_size)
1138 ptr = 0;
4f8e9400 1139 return ptr;
1da177e4
LT		 1140}
1141
3d8cb466 1142static const struct snd_pcm_hardware snd_ice1712_playback_pro = {
1da177e4
LT		 1143 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1144 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1145 SNDRV_PCM_INFO_MMAP_VALID |
1146 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
1147 .formats = SNDRV_PCM_FMTBIT_S32_LE,
1148 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_96000,
1149 .rate_min = 4000,
1150 .rate_max = 96000,
1151 .channels_min = 10,
1152 .channels_max = 10,
1153 .buffer_bytes_max = (256*1024),
1154 .period_bytes_min = 10 * 4 * 2,
1155 .period_bytes_max = 131040,
1156 .periods_min = 1,
1157 .periods_max = 1024,
1158 .fifo_size = 0,
1159};
1160
3d8cb466 1161static const struct snd_pcm_hardware snd_ice1712_capture_pro = {
1da177e4
LT		 1162 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1163 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1164 SNDRV_PCM_INFO_MMAP_VALID |
1165 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
1166 .formats = SNDRV_PCM_FMTBIT_S32_LE,
1167 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_96000,
1168 .rate_min = 4000,
1169 .rate_max = 96000,
1170 .channels_min = 12,
1171 .channels_max = 12,
1172 .buffer_bytes_max = (256*1024),
1173 .period_bytes_min = 12 * 4 * 2,
1174 .period_bytes_max = 131040,
1175 .periods_min = 1,
1176 .periods_max = 1024,
1177 .fifo_size = 0,
1178};
1179
6ca308d4 1180static int snd_ice1712_playback_pro_open(struct snd_pcm_substream *substream)
1da177e4 1181{
6ca308d4
TI		 1182 struct snd_pcm_runtime *runtime = substream->runtime;
1183 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 1184
1185 ice->playback_pro_substream = substream;
1186 runtime->hw = snd_ice1712_playback_pro;
1187 snd_pcm_set_sync(substream);
1188 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1189 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
350a5147
SA		 1190 if (is_pro_rate_locked(ice)) {
1191 runtime->hw.rate_min = PRO_RATE_DEFAULT;
1192 runtime->hw.rate_max = PRO_RATE_DEFAULT;
1193 }
1da177e4
LT		 1194
1195 if (ice->spdif.ops.open)
1196 ice->spdif.ops.open(ice, substream);
1197
1198 return 0;
1199}
1200
6ca308d4 1201static int snd_ice1712_capture_pro_open(struct snd_pcm_substream *substream)
1da177e4 1202{
6ca308d4
TI		 1203 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1204 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1205
1206 ice->capture_pro_substream = substream;
1207 runtime->hw = snd_ice1712_capture_pro;
1208 snd_pcm_set_sync(substream);
1209 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1210 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
350a5147
SA		 1211 if (is_pro_rate_locked(ice)) {
1212 runtime->hw.rate_min = PRO_RATE_DEFAULT;
1213 runtime->hw.rate_max = PRO_RATE_DEFAULT;
1214 }
1215
1da177e4
LT		 1216 return 0;
1217}
1218
6ca308d4 1219static int snd_ice1712_playback_pro_close(struct snd_pcm_substream *substream)
1da177e4 1220{
6ca308d4 1221 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 1222
1223 if (PRO_RATE_RESET)
1224 snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 0);
1225 ice->playback_pro_substream = NULL;
1226 if (ice->spdif.ops.close)
1227 ice->spdif.ops.close(ice, substream);
1228
1229 return 0;
1230}
1231
6ca308d4 1232static int snd_ice1712_capture_pro_close(struct snd_pcm_substream *substream)
1da177e4 1233{
6ca308d4 1234 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 1235
1236 if (PRO_RATE_RESET)
1237 snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 0);
1238 ice->capture_pro_substream = NULL;
1239 return 0;
1240}
1241
6ca308d4 1242static struct snd_pcm_ops snd_ice1712_playback_pro_ops = {
1da177e4
LT		 1243 .open = snd_ice1712_playback_pro_open,
1244 .close = snd_ice1712_playback_pro_close,
1245 .ioctl = snd_pcm_lib_ioctl,
1246 .hw_params = snd_ice1712_playback_pro_hw_params,
1247 .hw_free = snd_ice1712_hw_free,
1248 .prepare = snd_ice1712_playback_pro_prepare,
1249 .trigger = snd_ice1712_pro_trigger,
1250 .pointer = snd_ice1712_playback_pro_pointer,
1251};
1252
6ca308d4 1253static struct snd_pcm_ops snd_ice1712_capture_pro_ops = {
1da177e4
LT		 1254 .open = snd_ice1712_capture_pro_open,
1255 .close = snd_ice1712_capture_pro_close,
1256 .ioctl = snd_pcm_lib_ioctl,
1257 .hw_params = snd_ice1712_capture_pro_hw_params,
1258 .hw_free = snd_ice1712_hw_free,
1259 .prepare = snd_ice1712_capture_pro_prepare,
1260 .trigger = snd_ice1712_pro_trigger,
1261 .pointer = snd_ice1712_capture_pro_pointer,
1262};
1263
e23e7a14 1264static int snd_ice1712_pcm_profi(struct snd_ice1712 *ice, int device, struct snd_pcm **rpcm)
1da177e4 1265{
6ca308d4 1266 struct snd_pcm *pcm;
1da177e4
LT		 1267 int err;
1268
1269 if (rpcm)
1270 *rpcm = NULL;
1271 err = snd_pcm_new(ice->card, "ICE1712 multi", device, 1, 1, &pcm);
1272 if (err < 0)
1273 return err;
1274
1275 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_pro_ops);
1276 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ice1712_capture_pro_ops);
1277
1278 pcm->private_data = ice;
1da177e4
LT		 1279 pcm->info_flags = 0;
1280 strcpy(pcm->name, "ICE1712 multi");
1281
1282 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1283 snd_dma_pci_data(ice->pci), 256*1024, 256*1024);
1284
1285 ice->pcm_pro = pcm;
1286 if (rpcm)
1287 *rpcm = pcm;
3d8cb466 1288
1da177e4
LT		 1289 if (ice->cs8427) {
1290 /* assign channels to iec958 */
1291 err = snd_cs8427_iec958_build(ice->cs8427,
1292 pcm->streams[0].substream,
1293 pcm->streams[1].substream);
1294 if (err < 0)
1295 return err;
1296 }
1297
3d8cb466
AB		 1298 err = snd_ice1712_build_pro_mixer(ice);
1299 if (err < 0)
1da177e4
LT		 1300 return err;
1301 return 0;
1302}
1303
1304/*
1305 * Mixer section
1306 */
1307
6ca308d4 1308static void snd_ice1712_update_volume(struct snd_ice1712 *ice, int index)
1da177e4
LT		 1309{
1310 unsigned int vol = ice->pro_volumes[index];
1311 unsigned short val = 0;
1312
1313 val |= (vol & 0x8000) == 0 ? (96 - (vol & 0x7f)) : 0x7f;
1314 val |= ((vol & 0x80000000) == 0 ? (96 - ((vol >> 16) & 0x7f)) : 0x7f) << 8;
1315 outb(index, ICEMT(ice, MONITOR_INDEX));
1316 outw(val, ICEMT(ice, MONITOR_VOLUME));
1317}
1318
a5ce8890 1319#define snd_ice1712_pro_mixer_switch_info snd_ctl_boolean_stereo_info
1da177e4 1320
6ca308d4 1321static int snd_ice1712_pro_mixer_switch_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1322{
6ca308d4 1323 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
c3daa92d
HH		 1324 int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
1325 kcontrol->private_value;
3d8cb466 1326
1da177e4 1327 spin_lock_irq(&ice->reg_lock);
c3daa92d
HH		 1328 ucontrol->value.integer.value[0] =
1329 !((ice->pro_volumes[priv_idx] >> 15) & 1);
1330 ucontrol->value.integer.value[1] =
1331 !((ice->pro_volumes[priv_idx] >> 31) & 1);
1da177e4
LT		 1332 spin_unlock_irq(&ice->reg_lock);
1333 return 0;
1334}
1335
6ca308d4 1336static int snd_ice1712_pro_mixer_switch_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1337{
6ca308d4 1338 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
c3daa92d
HH		 1339 int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
1340 kcontrol->private_value;
1da177e4
LT		 1341 unsigned int nval, change;
1342
1343 nval = (ucontrol->value.integer.value[0] ? 0 : 0x00008000) |
1344 (ucontrol->value.integer.value[1] ? 0 : 0x80000000);
1345 spin_lock_irq(&ice->reg_lock);
c3daa92d
HH		 1346 nval |= ice->pro_volumes[priv_idx] & ~0x80008000;
1347 change = nval != ice->pro_volumes[priv_idx];
1348 ice->pro_volumes[priv_idx] = nval;
1349 snd_ice1712_update_volume(ice, priv_idx);
1da177e4
LT		 1350 spin_unlock_irq(&ice->reg_lock);
1351 return change;
1352}
1353
6ca308d4 1354static int snd_ice1712_pro_mixer_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1355{
1356 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1357 uinfo->count = 2;
1358 uinfo->value.integer.min = 0;
1359 uinfo->value.integer.max = 96;
1360 return 0;
1361}
1362
6ca308d4 1363static int snd_ice1712_pro_mixer_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1364{
6ca308d4 1365 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
c3daa92d
HH		 1366 int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
1367 kcontrol->private_value;
3d8cb466 1368
1da177e4 1369 spin_lock_irq(&ice->reg_lock);
c3daa92d
HH		 1370 ucontrol->value.integer.value[0] =
1371 (ice->pro_volumes[priv_idx] >> 0) & 127;
1372 ucontrol->value.integer.value[1] =
1373 (ice->pro_volumes[priv_idx] >> 16) & 127;
1da177e4
LT		 1374 spin_unlock_irq(&ice->reg_lock);
1375 return 0;
1376}
1377
6ca308d4 1378static int snd_ice1712_pro_mixer_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1379{
6ca308d4 1380 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
c3daa92d
HH		 1381 int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
1382 kcontrol->private_value;
1da177e4
LT		 1383 unsigned int nval, change;
1384
1385 nval = (ucontrol->value.integer.value[0] & 127) |
1386 ((ucontrol->value.integer.value[1] & 127) << 16);
1387 spin_lock_irq(&ice->reg_lock);
c3daa92d
HH		 1388 nval |= ice->pro_volumes[priv_idx] & ~0x007f007f;
1389 change = nval != ice->pro_volumes[priv_idx];
1390 ice->pro_volumes[priv_idx] = nval;
1391 snd_ice1712_update_volume(ice, priv_idx);
1da177e4
LT		 1392 spin_unlock_irq(&ice->reg_lock);
1393 return change;
1394}
1395
0cb29ea0 1396static const DECLARE_TLV_DB_SCALE(db_scale_playback, -14400, 150, 0);
1da177e4 1397
e23e7a14 1398static struct snd_kcontrol_new snd_ice1712_multi_playback_ctrls[] = {
1da177e4
LT		 1399 {
1400 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1401 .name = "Multi Playback Switch",
1402 .info = snd_ice1712_pro_mixer_switch_info,
1403 .get = snd_ice1712_pro_mixer_switch_get,
1404 .put = snd_ice1712_pro_mixer_switch_put,
1405 .private_value = 0,
1406 .count = 10,
1407 },
1408 {
1409 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
680ef792
TI		 1410 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
1411 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
1da177e4
LT		 1412 .name = "Multi Playback Volume",
1413 .info = snd_ice1712_pro_mixer_volume_info,
1414 .get = snd_ice1712_pro_mixer_volume_get,
1415 .put = snd_ice1712_pro_mixer_volume_put,
1416 .private_value = 0,
1417 .count = 10,
680ef792 1418 .tlv = { .p = db_scale_playback }
1da177e4
LT		 1419 },
1420};
1421
e23e7a14 1422static struct snd_kcontrol_new snd_ice1712_multi_capture_analog_switch = {
1da177e4
LT		 1423 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1424 .name = "H/W Multi Capture Switch",
1425 .info = snd_ice1712_pro_mixer_switch_info,
1426 .get = snd_ice1712_pro_mixer_switch_get,
1427 .put = snd_ice1712_pro_mixer_switch_put,
1428 .private_value = 10,
1429};
1430
e23e7a14 1431static struct snd_kcontrol_new snd_ice1712_multi_capture_spdif_switch = {
1da177e4 1432 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3d8cb466 1433 .name = SNDRV_CTL_NAME_IEC958("Multi ", CAPTURE, SWITCH),
1da177e4
LT		 1434 .info = snd_ice1712_pro_mixer_switch_info,
1435 .get = snd_ice1712_pro_mixer_switch_get,
1436 .put = snd_ice1712_pro_mixer_switch_put,
1437 .private_value = 18,
1438 .count = 2,
1439};
1440
e23e7a14 1441static struct snd_kcontrol_new snd_ice1712_multi_capture_analog_volume = {
1da177e4 1442 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
680ef792
TI		 1443 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
1444 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
1da177e4
LT		 1445 .name = "H/W Multi Capture Volume",
1446 .info = snd_ice1712_pro_mixer_volume_info,
1447 .get = snd_ice1712_pro_mixer_volume_get,
1448 .put = snd_ice1712_pro_mixer_volume_put,
1449 .private_value = 10,
680ef792 1450 .tlv = { .p = db_scale_playback }
1da177e4
LT		 1451};
1452
e23e7a14 1453static struct snd_kcontrol_new snd_ice1712_multi_capture_spdif_volume = {
1da177e4 1454 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3d8cb466 1455 .name = SNDRV_CTL_NAME_IEC958("Multi ", CAPTURE, VOLUME),
1da177e4
LT		 1456 .info = snd_ice1712_pro_mixer_volume_info,
1457 .get = snd_ice1712_pro_mixer_volume_get,
1458 .put = snd_ice1712_pro_mixer_volume_put,
1459 .private_value = 18,
1460 .count = 2,
1461};
1462
e23e7a14 1463static int snd_ice1712_build_pro_mixer(struct snd_ice1712 *ice)
1da177e4 1464{
6ca308d4 1465 struct snd_card *card = ice->card;
1da177e4
LT		 1466 unsigned int idx;
1467 int err;
1468
1469 /* multi-channel mixer */
1470 for (idx = 0; idx < ARRAY_SIZE(snd_ice1712_multi_playback_ctrls); idx++) {
1471 err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_playback_ctrls[idx], ice));
1472 if (err < 0)
1473 return err;
1474 }
3d8cb466 1475
1da177e4 1476 if (ice->num_total_adcs > 0) {
6ca308d4 1477 struct snd_kcontrol_new tmp = snd_ice1712_multi_capture_analog_switch;
1da177e4
LT		 1478 tmp.count = ice->num_total_adcs;
1479 err = snd_ctl_add(card, snd_ctl_new1(&tmp, ice));
1480 if (err < 0)
1481 return err;
1482 }
1483
1484 err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_capture_spdif_switch, ice));
1485 if (err < 0)
1486 return err;
1487
1488 if (ice->num_total_adcs > 0) {
6ca308d4 1489 struct snd_kcontrol_new tmp = snd_ice1712_multi_capture_analog_volume;
1da177e4
LT		 1490 tmp.count = ice->num_total_adcs;
1491 err = snd_ctl_add(card, snd_ctl_new1(&tmp, ice));
1492 if (err < 0)
1493 return err;
1494 }
1495
1496 err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_capture_spdif_volume, ice));
1497 if (err < 0)
1498 return err;
1499
1500 /* initialize volumes */
1501 for (idx = 0; idx < 10; idx++) {
1502 ice->pro_volumes[idx] = 0x80008000; /* mute */
1503 snd_ice1712_update_volume(ice, idx);
1504 }
1505 for (idx = 10; idx < 10 + ice->num_total_adcs; idx++) {
1506 ice->pro_volumes[idx] = 0x80008000; /* mute */
1507 snd_ice1712_update_volume(ice, idx);
1508 }
1509 for (idx = 18; idx < 20; idx++) {
1510 ice->pro_volumes[idx] = 0x80008000; /* mute */
1511 snd_ice1712_update_volume(ice, idx);
1512 }
1513 return 0;
1514}
1515
6ca308d4 1516static void snd_ice1712_mixer_free_ac97(struct snd_ac97 *ac97)
1da177e4 1517{
6ca308d4 1518 struct snd_ice1712 *ice = ac97->private_data;
1da177e4
LT		 1519 ice->ac97 = NULL;
1520}
1521
e23e7a14 1522static int snd_ice1712_ac97_mixer(struct snd_ice1712 *ice)
1da177e4
LT		 1523{
1524 int err, bus_num = 0;
6ca308d4
TI		 1525 struct snd_ac97_template ac97;
1526 struct snd_ac97_bus *pbus;
1527 static struct snd_ac97_bus_ops con_ops = {
1da177e4
LT		 1528 .write = snd_ice1712_ac97_write,
1529 .read = snd_ice1712_ac97_read,
1530 };
6ca308d4 1531 static struct snd_ac97_bus_ops pro_ops = {
1da177e4
LT		 1532 .write = snd_ice1712_pro_ac97_write,
1533 .read = snd_ice1712_pro_ac97_read,
1534 };
1535
1536 if (ice_has_con_ac97(ice)) {
3d8cb466
AB		 1537 err = snd_ac97_bus(ice->card, bus_num++, &con_ops, NULL, &pbus);
1538 if (err < 0)
1da177e4
LT		 1539 return err;
1540 memset(&ac97, 0, sizeof(ac97));
1541 ac97.private_data = ice;
1542 ac97.private_free = snd_ice1712_mixer_free_ac97;
3d8cb466
AB		 1543 err = snd_ac97_mixer(pbus, &ac97, &ice->ac97);
1544 if (err < 0)
6dfb5aff
TI		 1545 dev_warn(ice->card->dev,
1546 "cannot initialize ac97 for consumer, skipped\n");
1da177e4 1547 else {
3d8cb466
AB		 1548 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_digmix_route_ac97, ice));
1549 if (err < 0)
1da177e4
LT		 1550 return err;
1551 return 0;
1552 }
1553 }
1554
3d8cb466
AB		 1555 if (!(ice->eeprom.data[ICE_EEP1_ACLINK] & ICE1712_CFG_PRO_I2S)) {
1556 err = snd_ac97_bus(ice->card, bus_num, &pro_ops, NULL, &pbus);
1557 if (err < 0)
1da177e4
LT		 1558 return err;
1559 memset(&ac97, 0, sizeof(ac97));
1560 ac97.private_data = ice;
1561 ac97.private_free = snd_ice1712_mixer_free_ac97;
3d8cb466
AB		 1562 err = snd_ac97_mixer(pbus, &ac97, &ice->ac97);
1563 if (err < 0)
6dfb5aff
TI		 1564 dev_warn(ice->card->dev,
1565 "cannot initialize pro ac97, skipped\n");
1da177e4
LT		 1566 else
1567 return 0;
1568 }
1569 /* I2S mixer only */
1570 strcat(ice->card->mixername, "ICE1712 - multitrack");
1571 return 0;
1572}
1573
1574/*
1575 *
1576 */
1577
6ca308d4 1578static inline unsigned int eeprom_double(struct snd_ice1712 *ice, int idx)
1da177e4
LT		 1579{
1580 return (unsigned int)ice->eeprom.data[idx] | ((unsigned int)ice->eeprom.data[idx + 1] << 8);
1581}
1582
3d8cb466 1583static void snd_ice1712_proc_read(struct snd_info_entry *entry,
6ca308d4 1584 struct snd_info_buffer *buffer)
1da177e4 1585{
6ca308d4 1586 struct snd_ice1712 *ice = entry->private_data;
1da177e4
LT		 1587 unsigned int idx;
1588
1589 snd_iprintf(buffer, "%s\n\n", ice->card->longname);
1590 snd_iprintf(buffer, "EEPROM:\n");
1591
1592 snd_iprintf(buffer, " Subvendor : 0x%x\n", ice->eeprom.subvendor);
1593 snd_iprintf(buffer, " Size : %i bytes\n", ice->eeprom.size);
1594 snd_iprintf(buffer, " Version : %i\n", ice->eeprom.version);
1595 snd_iprintf(buffer, " Codec : 0x%x\n", ice->eeprom.data[ICE_EEP1_CODEC]);
1596 snd_iprintf(buffer, " ACLink : 0x%x\n", ice->eeprom.data[ICE_EEP1_ACLINK]);
1597 snd_iprintf(buffer, " I2S ID : 0x%x\n", ice->eeprom.data[ICE_EEP1_I2SID]);
1598 snd_iprintf(buffer, " S/PDIF : 0x%x\n", ice->eeprom.data[ICE_EEP1_SPDIF]);
1599 snd_iprintf(buffer, " GPIO mask : 0x%x\n", ice->eeprom.gpiomask);
1600 snd_iprintf(buffer, " GPIO state : 0x%x\n", ice->eeprom.gpiostate);
1601 snd_iprintf(buffer, " GPIO direction : 0x%x\n", ice->eeprom.gpiodir);
1602 snd_iprintf(buffer, " AC'97 main : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_MAIN_LO));
1603 snd_iprintf(buffer, " AC'97 pcm : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_PCM_LO));
1604 snd_iprintf(buffer, " AC'97 record : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_REC_LO));
1605 snd_iprintf(buffer, " AC'97 record src : 0x%x\n", ice->eeprom.data[ICE_EEP1_AC97_RECSRC]);
1606 for (idx = 0; idx < 4; idx++)
1607 snd_iprintf(buffer, " DAC ID #%i : 0x%x\n", idx, ice->eeprom.data[ICE_EEP1_DAC_ID + idx]);
1608 for (idx = 0; idx < 4; idx++)
1609 snd_iprintf(buffer, " ADC ID #%i : 0x%x\n", idx, ice->eeprom.data[ICE_EEP1_ADC_ID + idx]);
1610 for (idx = 0x1c; idx < ice->eeprom.size; idx++)
1611 snd_iprintf(buffer, " Extra #%02i : 0x%x\n", idx, ice->eeprom.data[idx]);
1612
1613 snd_iprintf(buffer, "\nRegisters:\n");
1614 snd_iprintf(buffer, " PSDOUT03 : 0x%04x\n", (unsigned)inw(ICEMT(ice, ROUTE_PSDOUT03)));
1615 snd_iprintf(buffer, " CAPTURE : 0x%08x\n", inl(ICEMT(ice, ROUTE_CAPTURE)));
1616 snd_iprintf(buffer, " SPDOUT : 0x%04x\n", (unsigned)inw(ICEMT(ice, ROUTE_SPDOUT)));
1617 snd_iprintf(buffer, " RATE : 0x%02x\n", (unsigned)inb(ICEMT(ice, RATE)));
f7004f39 1618 snd_iprintf(buffer, " GPIO_DATA : 0x%02x\n", (unsigned)snd_ice1712_get_gpio_data(ice));
3d8cb466 1619 snd_iprintf(buffer, " GPIO_WRITE_MASK : 0x%02x\n", (unsigned)snd_ice1712_read(ice, ICE1712_IREG_GPIO_WRITE_MASK));
f7004f39 1620 snd_iprintf(buffer, " GPIO_DIRECTION : 0x%02x\n", (unsigned)snd_ice1712_read(ice, ICE1712_IREG_GPIO_DIRECTION));
1da177e4
LT		 1621}
1622
e23e7a14 1623static void snd_ice1712_proc_init(struct snd_ice1712 *ice)
1da177e4 1624{
6ca308d4 1625 struct snd_info_entry *entry;
1da177e4 1626
3d8cb466 1627 if (!snd_card_proc_new(ice->card, "ice1712", &entry))
bf850204 1628 snd_info_set_text_ops(entry, ice, snd_ice1712_proc_read);
1da177e4
LT		 1629}
1630
1631/*
1632 *
1633 */
1634
6ca308d4
TI		 1635static int snd_ice1712_eeprom_info(struct snd_kcontrol *kcontrol,
1636 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1637{
1638 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
6ca308d4 1639 uinfo->count = sizeof(struct snd_ice1712_eeprom);
1da177e4
LT		 1640 return 0;
1641}
1642
6ca308d4
TI		 1643static int snd_ice1712_eeprom_get(struct snd_kcontrol *kcontrol,
1644 struct snd_ctl_elem_value *ucontrol)
1da177e4 1645{
6ca308d4 1646 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
3d8cb466 1647
1da177e4
LT		 1648 memcpy(ucontrol->value.bytes.data, &ice->eeprom, sizeof(ice->eeprom));
1649 return 0;
1650}
1651
e23e7a14 1652static struct snd_kcontrol_new snd_ice1712_eeprom = {
1da177e4
LT		 1653 .iface = SNDRV_CTL_ELEM_IFACE_CARD,
1654 .name = "ICE1712 EEPROM",
1655 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1656 .info = snd_ice1712_eeprom_info,
1657 .get = snd_ice1712_eeprom_get
1658};
1659
1660/*
1661 */
6ca308d4
TI		 1662static int snd_ice1712_spdif_info(struct snd_kcontrol *kcontrol,
1663 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1664{
1665 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1666 uinfo->count = 1;
1667 return 0;
1668}
1669
6ca308d4
TI		 1670static int snd_ice1712_spdif_default_get(struct snd_kcontrol *kcontrol,
1671 struct snd_ctl_elem_value *ucontrol)
1da177e4 1672{
6ca308d4 1673 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4 1674 if (ice->spdif.ops.default_get)
3d8cb466 1675 ice->spdif.ops.default_get(ice, ucontrol);
1da177e4
LT		 1676 return 0;
1677}
1678
6ca308d4
TI		 1679static int snd_ice1712_spdif_default_put(struct snd_kcontrol *kcontrol,
1680 struct snd_ctl_elem_value *ucontrol)
1da177e4 1681{
6ca308d4 1682 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1683 if (ice->spdif.ops.default_put)
1684 return ice->spdif.ops.default_put(ice, ucontrol);
1685 return 0;
1686}
1687
e23e7a14 1688static struct snd_kcontrol_new snd_ice1712_spdif_default =
1da177e4
LT		 1689{
1690 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3d8cb466 1691 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1da177e4
LT		 1692 .info = snd_ice1712_spdif_info,
1693 .get = snd_ice1712_spdif_default_get,
1694 .put = snd_ice1712_spdif_default_put
1695};
1696
6ca308d4
TI		 1697static int snd_ice1712_spdif_maskc_get(struct snd_kcontrol *kcontrol,
1698 struct snd_ctl_elem_value *ucontrol)
1da177e4 1699{
6ca308d4 1700 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1701 if (ice->spdif.ops.default_get) {
1702 ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
1703 IEC958_AES0_PROFESSIONAL |
1704 IEC958_AES0_CON_NOT_COPYRIGHT |
1705 IEC958_AES0_CON_EMPHASIS;
1706 ucontrol->value.iec958.status[1] = IEC958_AES1_CON_ORIGINAL |
1707 IEC958_AES1_CON_CATEGORY;
1708 ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS;
1709 } else {
1710 ucontrol->value.iec958.status[0] = 0xff;
1711 ucontrol->value.iec958.status[1] = 0xff;
1712 ucontrol->value.iec958.status[2] = 0xff;
1713 ucontrol->value.iec958.status[3] = 0xff;
1714 ucontrol->value.iec958.status[4] = 0xff;
1715 }
1716 return 0;
1717}
1718
6ca308d4
TI		 1719static int snd_ice1712_spdif_maskp_get(struct snd_kcontrol *kcontrol,
1720 struct snd_ctl_elem_value *ucontrol)
1da177e4 1721{
6ca308d4 1722 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1723 if (ice->spdif.ops.default_get) {
1724 ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
1725 IEC958_AES0_PROFESSIONAL |
1726 IEC958_AES0_PRO_FS |
1727 IEC958_AES0_PRO_EMPHASIS;
1728 ucontrol->value.iec958.status[1] = IEC958_AES1_PRO_MODE;
1729 } else {
1730 ucontrol->value.iec958.status[0] = 0xff;
1731 ucontrol->value.iec958.status[1] = 0xff;
1732 ucontrol->value.iec958.status[2] = 0xff;
1733 ucontrol->value.iec958.status[3] = 0xff;
1734 ucontrol->value.iec958.status[4] = 0xff;
1735 }
1736 return 0;
1737}
1738
e23e7a14 1739static struct snd_kcontrol_new snd_ice1712_spdif_maskc =
1da177e4
LT		 1740{
1741 .access = SNDRV_CTL_ELEM_ACCESS_READ,
67ed4161 1742 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3d8cb466 1743 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
1da177e4
LT		 1744 .info = snd_ice1712_spdif_info,
1745 .get = snd_ice1712_spdif_maskc_get,
1746};
1747
e23e7a14 1748static struct snd_kcontrol_new snd_ice1712_spdif_maskp =
1da177e4
LT		 1749{
1750 .access = SNDRV_CTL_ELEM_ACCESS_READ,
67ed4161 1751 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3d8cb466 1752 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
1da177e4
LT		 1753 .info = snd_ice1712_spdif_info,
1754 .get = snd_ice1712_spdif_maskp_get,
1755};
1756
6ca308d4
TI		 1757static int snd_ice1712_spdif_stream_get(struct snd_kcontrol *kcontrol,
1758 struct snd_ctl_elem_value *ucontrol)
1da177e4 1759{
6ca308d4 1760 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1761 if (ice->spdif.ops.stream_get)
1762 ice->spdif.ops.stream_get(ice, ucontrol);
1763 return 0;
1764}
1765
6ca308d4
TI		 1766static int snd_ice1712_spdif_stream_put(struct snd_kcontrol *kcontrol,
1767 struct snd_ctl_elem_value *ucontrol)
1da177e4 1768{
6ca308d4 1769 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1770 if (ice->spdif.ops.stream_put)
1771 return ice->spdif.ops.stream_put(ice, ucontrol);
1772 return 0;
1773}
1774
e23e7a14 1775static struct snd_kcontrol_new snd_ice1712_spdif_stream =
1da177e4 1776{
6ca308d4
TI		 1777 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
1778 SNDRV_CTL_ELEM_ACCESS_INACTIVE),
1da177e4 1779 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3d8cb466 1780 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM),
1da177e4
LT		 1781 .info = snd_ice1712_spdif_info,
1782 .get = snd_ice1712_spdif_stream_get,
1783 .put = snd_ice1712_spdif_stream_put
1784};
1785
6ca308d4
TI		 1786int snd_ice1712_gpio_get(struct snd_kcontrol *kcontrol,
1787 struct snd_ctl_elem_value *ucontrol)
1da177e4 1788{
6ca308d4 1789 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1790 unsigned char mask = kcontrol->private_value & 0xff;
1791 int invert = (kcontrol->private_value & (1<<24)) ? 1 : 0;
3d8cb466 1792
1da177e4 1793 snd_ice1712_save_gpio_status(ice);
6ca308d4
TI		 1794 ucontrol->value.integer.value[0] =
1795 (snd_ice1712_gpio_read(ice) & mask ? 1 : 0) ^ invert;
1da177e4
LT		 1796 snd_ice1712_restore_gpio_status(ice);
1797 return 0;
1798}
1799
6ca308d4
TI		 1800int snd_ice1712_gpio_put(struct snd_kcontrol *kcontrol,
1801 struct snd_ctl_elem_value *ucontrol)
1da177e4 1802{
6ca308d4 1803 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1804 unsigned char mask = kcontrol->private_value & 0xff;
1805 int invert = (kcontrol->private_value & (1<<24)) ? mask : 0;
1806 unsigned int val, nval;
1807
1808 if (kcontrol->private_value & (1 << 31))
1809 return -EPERM;
1810 nval = (ucontrol->value.integer.value[0] ? mask : 0) ^ invert;
1811 snd_ice1712_save_gpio_status(ice);
1812 val = snd_ice1712_gpio_read(ice);
1813 nval |= val & ~mask;
1814 if (val != nval)
1815 snd_ice1712_gpio_write(ice, nval);
1816 snd_ice1712_restore_gpio_status(ice);
1817 return val != nval;
1818}
1819
1820/*
1821 * rate
1822 */
6ca308d4
TI		 1823static int snd_ice1712_pro_internal_clock_info(struct snd_kcontrol *kcontrol,
1824 struct snd_ctl_elem_info *uinfo)
1da177e4 1825{
32b47da0 1826 static const char * const texts[] = {
1da177e4
LT		 1827 "8000", /* 0: 6 */
1828 "9600", /* 1: 3 */
1829 "11025", /* 2: 10 */
1830 "12000", /* 3: 2 */
1831 "16000", /* 4: 5 */
1832 "22050", /* 5: 9 */
1833 "24000", /* 6: 1 */
1834 "32000", /* 7: 4 */
1835 "44100", /* 8: 8 */
1836 "48000", /* 9: 0 */
1837 "64000", /* 10: 15 */
1838 "88200", /* 11: 11 */
1839 "96000", /* 12: 7 */
1840 "IEC958 Input", /* 13: -- */
1841 };
c4fa251f 1842 return snd_ctl_enum_info(uinfo, 1, 14, texts);
1da177e4
LT		 1843}
1844
6ca308d4
TI		 1845static int snd_ice1712_pro_internal_clock_get(struct snd_kcontrol *kcontrol,
1846 struct snd_ctl_elem_value *ucontrol)
1da177e4 1847{
6ca308d4 1848 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
32b47da0 1849 static const unsigned char xlate[16] = {
1da177e4
LT		 1850 9, 6, 3, 1, 7, 4, 0, 12, 8, 5, 2, 11, 255, 255, 255, 10
1851 };
1852 unsigned char val;
3d8cb466 1853
1da177e4
LT		 1854 spin_lock_irq(&ice->reg_lock);
1855 if (is_spdif_master(ice)) {
1856 ucontrol->value.enumerated.item[0] = 13;
1857 } else {
1858 val = xlate[inb(ICEMT(ice, RATE)) & 15];
1859 if (val == 255) {
1860 snd_BUG();
1861 val = 0;
1862 }
1863 ucontrol->value.enumerated.item[0] = val;
1864 }
1865 spin_unlock_irq(&ice->reg_lock);
1866 return 0;
1867}
1868
6ca308d4
TI		 1869static int snd_ice1712_pro_internal_clock_put(struct snd_kcontrol *kcontrol,
1870 struct snd_ctl_elem_value *ucontrol)
1da177e4 1871{
6ca308d4 1872 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
32b47da0 1873 static const unsigned int xrate[13] = {
fe25befd 1874 8000, 9600, 11025, 12000, 16000, 22050, 24000,
1da177e4
LT		 1875 32000, 44100, 48000, 64000, 88200, 96000
1876 };
1877 unsigned char oval;
1878 int change = 0;
1879
1880 spin_lock_irq(&ice->reg_lock);
1881 oval = inb(ICEMT(ice, RATE));
1882 if (ucontrol->value.enumerated.item[0] == 13) {
1883 outb(oval | ICE1712_SPDIF_MASTER, ICEMT(ice, RATE));
1884 } else {
1885 PRO_RATE_DEFAULT = xrate[ucontrol->value.integer.value[0] % 13];
1886 spin_unlock_irq(&ice->reg_lock);
1887 snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 1);
1888 spin_lock_irq(&ice->reg_lock);
1889 }
1890 change = inb(ICEMT(ice, RATE)) != oval;
1891 spin_unlock_irq(&ice->reg_lock);
1892
6ca308d4 1893 if ((oval & ICE1712_SPDIF_MASTER) !=
e957ebf1 1894 (inb(ICEMT(ice, RATE)) & ICE1712_SPDIF_MASTER))
3d8cb466 1895 snd_ice1712_set_input_clock_source(ice, is_spdif_master(ice));
1da177e4
LT		 1896
1897 return change;
1898}
1899
e23e7a14 1900static struct snd_kcontrol_new snd_ice1712_pro_internal_clock = {
1da177e4
LT		 1901 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1902 .name = "Multi Track Internal Clock",
1903 .info = snd_ice1712_pro_internal_clock_info,
1904 .get = snd_ice1712_pro_internal_clock_get,
1905 .put = snd_ice1712_pro_internal_clock_put
1906};
1907
6ca308d4
TI		 1908static int snd_ice1712_pro_internal_clock_default_info(struct snd_kcontrol *kcontrol,
1909 struct snd_ctl_elem_info *uinfo)
1da177e4 1910{
32b47da0 1911 static const char * const texts[] = {
1da177e4
LT		 1912 "8000", /* 0: 6 */
1913 "9600", /* 1: 3 */
1914 "11025", /* 2: 10 */
1915 "12000", /* 3: 2 */
1916 "16000", /* 4: 5 */
1917 "22050", /* 5: 9 */
1918 "24000", /* 6: 1 */
1919 "32000", /* 7: 4 */
1920 "44100", /* 8: 8 */
1921 "48000", /* 9: 0 */
1922 "64000", /* 10: 15 */
1923 "88200", /* 11: 11 */
1924 "96000", /* 12: 7 */
3d8cb466 1925 /* "IEC958 Input", 13: -- */
1da177e4 1926 };
c4fa251f 1927 return snd_ctl_enum_info(uinfo, 1, 13, texts);
1da177e4
LT		 1928}
1929
6ca308d4
TI		 1930static int snd_ice1712_pro_internal_clock_default_get(struct snd_kcontrol *kcontrol,
1931 struct snd_ctl_elem_value *ucontrol)
1da177e4
LT		 1932{
1933 int val;
32b47da0 1934 static const unsigned int xrate[13] = {
fe25befd 1935 8000, 9600, 11025, 12000, 16000, 22050, 24000,
1da177e4
LT		 1936 32000, 44100, 48000, 64000, 88200, 96000
1937 };
1938
1939 for (val = 0; val < 13; val++) {
1940 if (xrate[val] == PRO_RATE_DEFAULT)
1941 break;
1942 }
1943
1944 ucontrol->value.enumerated.item[0] = val;
1945 return 0;
1946}
1947
6ca308d4
TI		 1948static int snd_ice1712_pro_internal_clock_default_put(struct snd_kcontrol *kcontrol,
1949 struct snd_ctl_elem_value *ucontrol)
1da177e4 1950{
32b47da0 1951 static const unsigned int xrate[13] = {
fe25befd 1952 8000, 9600, 11025, 12000, 16000, 22050, 24000,
1da177e4
LT		 1953 32000, 44100, 48000, 64000, 88200, 96000
1954 };
1955 unsigned char oval;
1956 int change = 0;
1957
1958 oval = PRO_RATE_DEFAULT;
1959 PRO_RATE_DEFAULT = xrate[ucontrol->value.integer.value[0] % 13];
1960 change = PRO_RATE_DEFAULT != oval;
1961
1962 return change;
1963}
1964
e23e7a14 1965static struct snd_kcontrol_new snd_ice1712_pro_internal_clock_default = {
1da177e4
LT		 1966 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1967 .name = "Multi Track Internal Clock Default",
1968 .info = snd_ice1712_pro_internal_clock_default_info,
1969 .get = snd_ice1712_pro_internal_clock_default_get,
1970 .put = snd_ice1712_pro_internal_clock_default_put
1971};
1972
a5ce8890 1973#define snd_ice1712_pro_rate_locking_info snd_ctl_boolean_mono_info
1da177e4 1974
6ca308d4
TI		 1975static int snd_ice1712_pro_rate_locking_get(struct snd_kcontrol *kcontrol,
1976 struct snd_ctl_elem_value *ucontrol)
1da177e4
LT		 1977{
1978 ucontrol->value.integer.value[0] = PRO_RATE_LOCKED;
1979 return 0;
1980}
1981
6ca308d4
TI		 1982static int snd_ice1712_pro_rate_locking_put(struct snd_kcontrol *kcontrol,
1983 struct snd_ctl_elem_value *ucontrol)
1da177e4 1984{
6ca308d4 1985 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1986 int change = 0, nval;
1987
1988 nval = ucontrol->value.integer.value[0] ? 1 : 0;
1989 spin_lock_irq(&ice->reg_lock);
1990 change = PRO_RATE_LOCKED != nval;
1991 PRO_RATE_LOCKED = nval;
1992 spin_unlock_irq(&ice->reg_lock);
1993 return change;
1994}
1995
e23e7a14 1996static struct snd_kcontrol_new snd_ice1712_pro_rate_locking = {
1da177e4
LT		 1997 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1998 .name = "Multi Track Rate Locking",
1999 .info = snd_ice1712_pro_rate_locking_info,
2000 .get = snd_ice1712_pro_rate_locking_get,
2001 .put = snd_ice1712_pro_rate_locking_put
2002};
2003
a5ce8890 2004#define snd_ice1712_pro_rate_reset_info snd_ctl_boolean_mono_info
1da177e4 2005
6ca308d4
TI		 2006static int snd_ice1712_pro_rate_reset_get(struct snd_kcontrol *kcontrol,
2007 struct snd_ctl_elem_value *ucontrol)
1da177e4
LT		 2008{
2009 ucontrol->value.integer.value[0] = PRO_RATE_RESET;
2010 return 0;
2011}
2012
6ca308d4
TI		 2013static int snd_ice1712_pro_rate_reset_put(struct snd_kcontrol *kcontrol,
2014 struct snd_ctl_elem_value *ucontrol)
1da177e4 2015{
6ca308d4 2016 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2017 int change = 0, nval;
2018
2019 nval = ucontrol->value.integer.value[0] ? 1 : 0;
2020 spin_lock_irq(&ice->reg_lock);
2021 change = PRO_RATE_RESET != nval;
2022 PRO_RATE_RESET = nval;
2023 spin_unlock_irq(&ice->reg_lock);
2024 return change;
2025}
2026
e23e7a14 2027static struct snd_kcontrol_new snd_ice1712_pro_rate_reset = {
1da177e4
LT		 2028 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2029 .name = "Multi Track Rate Reset",
2030 .info = snd_ice1712_pro_rate_reset_info,
2031 .get = snd_ice1712_pro_rate_reset_get,
2032 .put = snd_ice1712_pro_rate_reset_put
2033};
2034
2035/*
2036 * routing
2037 */
6ca308d4
TI		 2038static int snd_ice1712_pro_route_info(struct snd_kcontrol *kcontrol,
2039 struct snd_ctl_elem_info *uinfo)
1da177e4 2040{
32b47da0 2041 static const char * const texts[] = {
1da177e4
LT		 2042 "PCM Out", /* 0 */
2043 "H/W In 0", "H/W In 1", "H/W In 2", "H/W In 3", /* 1-4 */
2044 "H/W In 4", "H/W In 5", "H/W In 6", "H/W In 7", /* 5-8 */
2045 "IEC958 In L", "IEC958 In R", /* 9-10 */
2046 "Digital Mixer", /* 11 - optional */
2047 };
c4fa251f
TI		 2048 int num_items = snd_ctl_get_ioffidx(kcontrol, &uinfo->id) < 2 ? 12 : 11;
2049 return snd_ctl_enum_info(uinfo, 1, num_items, texts);
1da177e4
LT		 2050}
2051
6ca308d4
TI		 2052static int snd_ice1712_pro_route_analog_get(struct snd_kcontrol *kcontrol,
2053 struct snd_ctl_elem_value *ucontrol)
1da177e4 2054{
6ca308d4 2055 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2056 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2057 unsigned int val, cval;
2058
2059 spin_lock_irq(&ice->reg_lock);
2060 val = inw(ICEMT(ice, ROUTE_PSDOUT03));
2061 cval = inl(ICEMT(ice, ROUTE_CAPTURE));
2062 spin_unlock_irq(&ice->reg_lock);
2063
2064 val >>= ((idx % 2) * 8) + ((idx / 2) * 2);
2065 val &= 3;
2066 cval >>= ((idx / 2) * 8) + ((idx % 2) * 4);
2067 if (val == 1 && idx < 2)
2068 ucontrol->value.enumerated.item[0] = 11;
2069 else if (val == 2)
2070 ucontrol->value.enumerated.item[0] = (cval & 7) + 1;
2071 else if (val == 3)
2072 ucontrol->value.enumerated.item[0] = ((cval >> 3) & 1) + 9;
2073 else
2074 ucontrol->value.enumerated.item[0] = 0;
2075 return 0;
2076}
2077
6ca308d4
TI		 2078static int snd_ice1712_pro_route_analog_put(struct snd_kcontrol *kcontrol,
2079 struct snd_ctl_elem_value *ucontrol)
1da177e4 2080{
6ca308d4 2081 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2082 int change, shift;
2083 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2084 unsigned int val, old_val, nval;
3d8cb466 2085
1da177e4
LT		 2086 /* update PSDOUT */
2087 if (ucontrol->value.enumerated.item[0] >= 11)
2088 nval = idx < 2 ? 1 : 0; /* dig mixer (or pcm) */
2089 else if (ucontrol->value.enumerated.item[0] >= 9)
2090 nval = 3; /* spdif in */
2091 else if (ucontrol->value.enumerated.item[0] >= 1)
2092 nval = 2; /* analog in */
2093 else
2094 nval = 0; /* pcm */
2095 shift = ((idx % 2) * 8) + ((idx / 2) * 2);
2096 spin_lock_irq(&ice->reg_lock);
2097 val = old_val = inw(ICEMT(ice, ROUTE_PSDOUT03));
2098 val &= ~(0x03 << shift);
2099 val |= nval << shift;
2100 change = val != old_val;
2101 if (change)
2102 outw(val, ICEMT(ice, ROUTE_PSDOUT03));
2103 spin_unlock_irq(&ice->reg_lock);
2104 if (nval < 2) /* dig mixer of pcm */
2105 return change;
2106
2107 /* update CAPTURE */
2108 spin_lock_irq(&ice->reg_lock);
2109 val = old_val = inl(ICEMT(ice, ROUTE_CAPTURE));
2110 shift = ((idx / 2) * 8) + ((idx % 2) * 4);
2111 if (nval == 2) { /* analog in */
2112 nval = ucontrol->value.enumerated.item[0] - 1;
2113 val &= ~(0x07 << shift);
2114 val |= nval << shift;
2115 } else { /* spdif in */
2116 nval = (ucontrol->value.enumerated.item[0] - 9) << 3;
2117 val &= ~(0x08 << shift);
2118 val |= nval << shift;
2119 }
2120 if (val != old_val) {
2121 change = 1;
2122 outl(val, ICEMT(ice, ROUTE_CAPTURE));
2123 }
2124 spin_unlock_irq(&ice->reg_lock);
2125 return change;
2126}
2127
6ca308d4
TI		 2128static int snd_ice1712_pro_route_spdif_get(struct snd_kcontrol *kcontrol,
2129 struct snd_ctl_elem_value *ucontrol)
1da177e4 2130{
6ca308d4 2131 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2132 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2133 unsigned int val, cval;
2134 val = inw(ICEMT(ice, ROUTE_SPDOUT));
2135 cval = (val >> (idx * 4 + 8)) & 0x0f;
2136 val = (val >> (idx * 2)) & 0x03;
2137 if (val == 1)
2138 ucontrol->value.enumerated.item[0] = 11;
2139 else if (val == 2)
2140 ucontrol->value.enumerated.item[0] = (cval & 7) + 1;
2141 else if (val == 3)
2142 ucontrol->value.enumerated.item[0] = ((cval >> 3) & 1) + 9;
2143 else
2144 ucontrol->value.enumerated.item[0] = 0;
2145 return 0;
2146}
2147
6ca308d4
TI		 2148static int snd_ice1712_pro_route_spdif_put(struct snd_kcontrol *kcontrol,
2149 struct snd_ctl_elem_value *ucontrol)
1da177e4 2150{
6ca308d4 2151 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2152 int change, shift;
2153 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2154 unsigned int val, old_val, nval;
3d8cb466 2155
1da177e4
LT		 2156 /* update SPDOUT */
2157 spin_lock_irq(&ice->reg_lock);
2158 val = old_val = inw(ICEMT(ice, ROUTE_SPDOUT));
2159 if (ucontrol->value.enumerated.item[0] >= 11)
2160 nval = 1;
2161 else if (ucontrol->value.enumerated.item[0] >= 9)
2162 nval = 3;
2163 else if (ucontrol->value.enumerated.item[0] >= 1)
2164 nval = 2;
2165 else
2166 nval = 0;
2167 shift = idx * 2;
2168 val &= ~(0x03 << shift);
2169 val |= nval << shift;
2170 shift = idx * 4 + 8;
2171 if (nval == 2) {
2172 nval = ucontrol->value.enumerated.item[0] - 1;
2173 val &= ~(0x07 << shift);
2174 val |= nval << shift;
2175 } else if (nval == 3) {
2176 nval = (ucontrol->value.enumerated.item[0] - 9) << 3;
2177 val &= ~(0x08 << shift);
2178 val |= nval << shift;
2179 }
2180 change = val != old_val;
2181 if (change)
2182 outw(val, ICEMT(ice, ROUTE_SPDOUT));
2183 spin_unlock_irq(&ice->reg_lock);
2184 return change;
2185}
2186
e23e7a14 2187static struct snd_kcontrol_new snd_ice1712_mixer_pro_analog_route = {
1da177e4
LT		 2188 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2189 .name = "H/W Playback Route",
2190 .info = snd_ice1712_pro_route_info,
2191 .get = snd_ice1712_pro_route_analog_get,
2192 .put = snd_ice1712_pro_route_analog_put,
2193};
2194
e23e7a14 2195static struct snd_kcontrol_new snd_ice1712_mixer_pro_spdif_route = {
1da177e4 2196 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3d8cb466 2197 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, NONE) "Route",
1da177e4
LT		 2198 .info = snd_ice1712_pro_route_info,
2199 .get = snd_ice1712_pro_route_spdif_get,
2200 .put = snd_ice1712_pro_route_spdif_put,
2201 .count = 2,
2202};
2203
2204
6ca308d4
TI		 2205static int snd_ice1712_pro_volume_rate_info(struct snd_kcontrol *kcontrol,
2206 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 2207{
2208 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2209 uinfo->count = 1;
2210 uinfo->value.integer.min = 0;
2211 uinfo->value.integer.max = 255;
2212 return 0;
2213}
2214
6ca308d4
TI		 2215static int snd_ice1712_pro_volume_rate_get(struct snd_kcontrol *kcontrol,
2216 struct snd_ctl_elem_value *ucontrol)
1da177e4 2217{
6ca308d4 2218 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
3d8cb466 2219
1da177e4
LT		 2220 ucontrol->value.integer.value[0] = inb(ICEMT(ice, MONITOR_RATE));
2221 return 0;
2222}
2223
6ca308d4
TI		 2224static int snd_ice1712_pro_volume_rate_put(struct snd_kcontrol *kcontrol,
2225 struct snd_ctl_elem_value *ucontrol)
1da177e4 2226{
6ca308d4 2227 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2228 int change;
2229
2230 spin_lock_irq(&ice->reg_lock);
2231 change = inb(ICEMT(ice, MONITOR_RATE)) != ucontrol->value.integer.value[0];
2232 outb(ucontrol->value.integer.value[0], ICEMT(ice, MONITOR_RATE));
2233 spin_unlock_irq(&ice->reg_lock);
2234 return change;
2235}
2236
e23e7a14 2237static struct snd_kcontrol_new snd_ice1712_mixer_pro_volume_rate = {
1da177e4
LT		 2238 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2239 .name = "Multi Track Volume Rate",
2240 .info = snd_ice1712_pro_volume_rate_info,
2241 .get = snd_ice1712_pro_volume_rate_get,
2242 .put = snd_ice1712_pro_volume_rate_put
2243};
2244
6ca308d4
TI		 2245static int snd_ice1712_pro_peak_info(struct snd_kcontrol *kcontrol,
2246 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 2247{
2248 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2249 uinfo->count = 22;
2250 uinfo->value.integer.min = 0;
2251 uinfo->value.integer.max = 255;
2252 return 0;
2253}
2254
6ca308d4
TI		 2255static int snd_ice1712_pro_peak_get(struct snd_kcontrol *kcontrol,
2256 struct snd_ctl_elem_value *ucontrol)
1da177e4 2257{
6ca308d4 2258 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4 2259 int idx;
3d8cb466 2260
1da177e4
LT		 2261 spin_lock_irq(&ice->reg_lock);
2262 for (idx = 0; idx < 22; idx++) {
2263 outb(idx, ICEMT(ice, MONITOR_PEAKINDEX));
2264 ucontrol->value.integer.value[idx] = inb(ICEMT(ice, MONITOR_PEAKDATA));
2265 }
2266 spin_unlock_irq(&ice->reg_lock);
2267 return 0;
2268}
2269
e23e7a14 2270static struct snd_kcontrol_new snd_ice1712_mixer_pro_peak = {
2bdf6633 2271 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT		 2272 .name = "Multi Track Peak",
2273 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
2274 .info = snd_ice1712_pro_peak_info,
2275 .get = snd_ice1712_pro_peak_get
2276};
2277
2278/*
2279 *
2280 */
2281
2282/*
2283 * list of available boards
2284 */
e23e7a14 2285static struct snd_ice1712_card_info *card_tables[] = {
1da177e4
LT		 2286 snd_ice1712_hoontech_cards,
2287 snd_ice1712_delta_cards,
2288 snd_ice1712_ews_cards,
2289 NULL,
2290};
2291
e23e7a14
BP		 2292static unsigned char snd_ice1712_read_i2c(struct snd_ice1712 *ice,
2293 unsigned char dev,
2294 unsigned char addr)
1da177e4
LT		 2295{
2296 long t = 0x10000;
2297
2298 outb(addr, ICEREG(ice, I2C_BYTE_ADDR));
2299 outb(dev & ~ICE1712_I2C_WRITE, ICEREG(ice, I2C_DEV_ADDR));
2300 while (t-- > 0 && (inb(ICEREG(ice, I2C_CTRL)) & ICE1712_I2C_BUSY)) ;
2301 return inb(ICEREG(ice, I2C_DATA));
2302}
2303
e23e7a14
BP		 2304static int snd_ice1712_read_eeprom(struct snd_ice1712 *ice,
2305 const char *modelname)
1da177e4
LT		 2306{
2307 int dev = 0xa0; /* EEPROM device address */
2308 unsigned int i, size;
bf748ed7 2309 struct snd_ice1712_card_info * const *tbl, *c;
1da177e4 2310
3d8cb466 2311 if (!modelname || !*modelname) {
1da177e4
LT		 2312 ice->eeprom.subvendor = 0;
2313 if ((inb(ICEREG(ice, I2C_CTRL)) & ICE1712_I2C_EEPROM) != 0)
2314 ice->eeprom.subvendor = (snd_ice1712_read_i2c(ice, dev, 0x00) << 0) |
3d8cb466
AB		 2315 (snd_ice1712_read_i2c(ice, dev, 0x01) << 8) |
2316 (snd_ice1712_read_i2c(ice, dev, 0x02) << 16) |
1da177e4 2317 (snd_ice1712_read_i2c(ice, dev, 0x03) << 24);
6ca308d4
TI		 2318 if (ice->eeprom.subvendor == 0 ||
2319 ice->eeprom.subvendor == (unsigned int)-1) {
1da177e4
LT		 2320 /* invalid subvendor from EEPROM, try the PCI subststem ID instead */
2321 u16 vendor, device;
2322 pci_read_config_word(ice->pci, PCI_SUBSYSTEM_VENDOR_ID, &vendor);
2323 pci_read_config_word(ice->pci, PCI_SUBSYSTEM_ID, &device);
2324 ice->eeprom.subvendor = ((unsigned int)swab16(vendor) << 16) | swab16(device);
2325 if (ice->eeprom.subvendor == 0 || ice->eeprom.subvendor == (unsigned int)-1) {
6dfb5aff
TI		 2326 dev_err(ice->card->dev,
2327 "No valid ID is found\n");
1da177e4
LT		 2328 return -ENXIO;
2329 }
2330 }
2331 }
2332 for (tbl = card_tables; *tbl; tbl++) {
2333 for (c = *tbl; c->subvendor; c++) {
3d8cb466 2334 if (modelname && c->model && !strcmp(modelname, c->model)) {
6dfb5aff
TI		 2335 dev_info(ice->card->dev,
2336 "Using board model %s\n", c->name);
1da177e4
LT		 2337 ice->eeprom.subvendor = c->subvendor;
2338 } else if (c->subvendor != ice->eeprom.subvendor)
2339 continue;
3d8cb466 2340 if (!c->eeprom_size || !c->eeprom_data)
1da177e4
LT		 2341 goto found;
2342 /* if the EEPROM is given by the driver, use it */
6dfb5aff 2343 dev_dbg(ice->card->dev, "using the defined eeprom..\n");
1da177e4
LT		 2344 ice->eeprom.version = 1;
2345 ice->eeprom.size = c->eeprom_size + 6;
2346 memcpy(ice->eeprom.data, c->eeprom_data, c->eeprom_size);
2347 goto read_skipped;
2348 }
2349 }
6dfb5aff 2350 dev_warn(ice->card->dev, "No matching model found for ID 0x%x\n",
6ca308d4 2351 ice->eeprom.subvendor);
1da177e4
LT		 2352
2353 found:
2354 ice->eeprom.size = snd_ice1712_read_i2c(ice, dev, 0x04);
2355 if (ice->eeprom.size < 6)
2356 ice->eeprom.size = 32; /* FIXME: any cards without the correct size? */
2357 else if (ice->eeprom.size > 32) {
6dfb5aff
TI		 2358 dev_err(ice->card->dev,
2359 "invalid EEPROM (size = %i)\n", ice->eeprom.size);
1da177e4
LT		 2360 return -EIO;
2361 }
2362 ice->eeprom.version = snd_ice1712_read_i2c(ice, dev, 0x05);
2363 if (ice->eeprom.version != 1) {
6dfb5aff 2364 dev_err(ice->card->dev, "invalid EEPROM version %i\n",
6ca308d4 2365 ice->eeprom.version);
1da177e4
LT		 2366 /* return -EIO; */
2367 }
2368 size = ice->eeprom.size - 6;
2369 for (i = 0; i < size; i++)
2370 ice->eeprom.data[i] = snd_ice1712_read_i2c(ice, dev, i + 6);
2371
2372 read_skipped:
2373 ice->eeprom.gpiomask = ice->eeprom.data[ICE_EEP1_GPIO_MASK];
2374 ice->eeprom.gpiostate = ice->eeprom.data[ICE_EEP1_GPIO_STATE];
2375 ice->eeprom.gpiodir = ice->eeprom.data[ICE_EEP1_GPIO_DIR];
2376
2377 return 0;
2378}
2379
2380
2381
e23e7a14 2382static int snd_ice1712_chip_init(struct snd_ice1712 *ice)
1da177e4
LT		 2383{
2384 outb(ICE1712_RESET | ICE1712_NATIVE, ICEREG(ice, CONTROL));
2385 udelay(200);
2386 outb(ICE1712_NATIVE, ICEREG(ice, CONTROL));
2387 udelay(200);
721b8a29
AH		 2388 if (ice->eeprom.subvendor == ICE1712_SUBDEVICE_DMX6FIRE &&
2389 !ice->dxr_enable)
2390 /* Set eeprom value to limit active ADCs and DACs to 6;
2391 * Also disable AC97 as no hardware in standard 6fire card/box
2392 * Note: DXR extensions are not currently supported
2393 */
2394 ice->eeprom.data[ICE_EEP1_CODEC] = 0x3a;
2395 pci_write_config_byte(ice->pci, 0x60, ice->eeprom.data[ICE_EEP1_CODEC]);
1da177e4
LT		 2396 pci_write_config_byte(ice->pci, 0x61, ice->eeprom.data[ICE_EEP1_ACLINK]);
2397 pci_write_config_byte(ice->pci, 0x62, ice->eeprom.data[ICE_EEP1_I2SID]);
2398 pci_write_config_byte(ice->pci, 0x63, ice->eeprom.data[ICE_EEP1_SPDIF]);
2399 if (ice->eeprom.subvendor != ICE1712_SUBDEVICE_STDSP24) {
2400 ice->gpio.write_mask = ice->eeprom.gpiomask;
2401 ice->gpio.direction = ice->eeprom.gpiodir;
6ca308d4
TI		 2402 snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK,
2403 ice->eeprom.gpiomask);
2404 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION,
2405 ice->eeprom.gpiodir);
2406 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA,
2407 ice->eeprom.gpiostate);
1da177e4
LT		 2408 } else {
2409 ice->gpio.write_mask = 0xc0;
2410 ice->gpio.direction = 0xff;
2411 snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, 0xc0);
2412 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION, 0xff);
6ca308d4
TI		 2413 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA,
2414 ICE1712_STDSP24_CLOCK_BIT);
1da177e4
LT		 2415 }
2416 snd_ice1712_write(ice, ICE1712_IREG_PRO_POWERDOWN, 0);
2417 if (!(ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97)) {
2418 outb(ICE1712_AC97_WARM, ICEREG(ice, AC97_CMD));
2419 udelay(100);
2420 outb(0, ICEREG(ice, AC97_CMD));
2421 udelay(200);
2422 snd_ice1712_write(ice, ICE1712_IREG_CONSUMER_POWERDOWN, 0);
2423 }
2424 snd_ice1712_set_pro_rate(ice, 48000, 1);
ca051e8a
OZ		 2425 /* unmask used interrupts */
2426 outb(((ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_2xMPU401) == 0 ?
2427 ICE1712_IRQ_MPU2 : 0) |
2428 ((ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97) ?
2429 ICE1712_IRQ_PBKDS | ICE1712_IRQ_CONCAP | ICE1712_IRQ_CONPBK : 0),
2430 ICEREG(ice, IRQMASK));
2431 outb(0x00, ICEMT(ice, IRQ));
1da177e4
LT		 2432
2433 return 0;
2434}
2435
e23e7a14 2436int snd_ice1712_spdif_build_controls(struct snd_ice1712 *ice)
1da177e4
LT		 2437{
2438 int err;
6ca308d4 2439 struct snd_kcontrol *kctl;
1da177e4 2440
da3cec35
TI		 2441 if (snd_BUG_ON(!ice->pcm_pro))
2442 return -EIO;
1da177e4
LT		 2443 err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_default, ice));
2444 if (err < 0)
2445 return err;
2446 kctl->id.device = ice->pcm_pro->device;
2447 err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_maskc, ice));
2448 if (err < 0)
2449 return err;
2450 kctl->id.device = ice->pcm_pro->device;
2451 err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_maskp, ice));
2452 if (err < 0)
2453 return err;
2454 kctl->id.device = ice->pcm_pro->device;
2455 err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_stream, ice));
2456 if (err < 0)
2457 return err;
2458 kctl->id.device = ice->pcm_pro->device;
2459 ice->spdif.stream_ctl = kctl;
2460 return 0;
2461}
2462
2463
e23e7a14 2464static int snd_ice1712_build_controls(struct snd_ice1712 *ice)
1da177e4
LT		 2465{
2466 int err;
2467
2468 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_eeprom, ice));
2469 if (err < 0)
2470 return err;
2471 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_internal_clock, ice));
2472 if (err < 0)
2473 return err;
2474 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_internal_clock_default, ice));
2475 if (err < 0)
2476 return err;
2477
2478 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_rate_locking, ice));
2479 if (err < 0)
2480 return err;
2481 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_rate_reset, ice));
2482 if (err < 0)
2483 return err;
2484
2485 if (ice->num_total_dacs > 0) {
6ca308d4 2486 struct snd_kcontrol_new tmp = snd_ice1712_mixer_pro_analog_route;
1da177e4
LT		 2487 tmp.count = ice->num_total_dacs;
2488 err = snd_ctl_add(ice->card, snd_ctl_new1(&tmp, ice));
2489 if (err < 0)
2490 return err;
2491 }
2492
2493 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_spdif_route, ice));
2494 if (err < 0)
2495 return err;
2496
2497 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_volume_rate, ice));
2498 if (err < 0)
2499 return err;
2500 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_peak, ice));
2501 if (err < 0)
2502 return err;
2503
2504 return 0;
2505}
2506
6ca308d4 2507static int snd_ice1712_free(struct snd_ice1712 *ice)
1da177e4 2508{
3d8cb466 2509 if (!ice->port)
1da177e4
LT		 2510 goto __hw_end;
2511 /* mask all interrupts */
890b13a3 2512 outb(ICE1712_MULTI_CAPTURE | ICE1712_MULTI_PLAYBACK, ICEMT(ice, IRQ));
1da177e4
LT		 2513 outb(0xff, ICEREG(ice, IRQMASK));
2514 /* --- */
3d8cb466 2515__hw_end:
f000fd80 2516 if (ice->irq >= 0)
6ca308d4 2517 free_irq(ice->irq, ice);
f000fd80 2518
1da177e4
LT		 2519 if (ice->port)
2520 pci_release_regions(ice->pci);
2521 snd_ice1712_akm4xxx_free(ice);
2522 pci_disable_device(ice->pci);
7cda8ba9 2523 kfree(ice->spec);
1da177e4
LT		 2524 kfree(ice);
2525 return 0;
2526}
2527
6ca308d4 2528static int snd_ice1712_dev_free(struct snd_device *device)
1da177e4 2529{
6ca308d4 2530 struct snd_ice1712 *ice = device->device_data;
1da177e4
LT		 2531 return snd_ice1712_free(ice);
2532}
2533
e23e7a14
BP		 2534static int snd_ice1712_create(struct snd_card *card,
2535 struct pci_dev *pci,
2536 const char *modelname,
2537 int omni,
2538 int cs8427_timeout,
2539 int dxr_enable,
2540 struct snd_ice1712 **r_ice1712)
1da177e4 2541{
6ca308d4 2542 struct snd_ice1712 *ice;
1da177e4 2543 int err;
6ca308d4 2544 static struct snd_device_ops ops = {
1da177e4
LT		 2545 .dev_free = snd_ice1712_dev_free,
2546 };
2547
2548 *r_ice1712 = NULL;
2549
3d8cb466
AB		 2550 /* enable PCI device */
2551 err = pci_enable_device(pci);
2552 if (err < 0)
1da177e4
LT		 2553 return err;
2554 /* check, if we can restrict PCI DMA transfers to 28 bits */
ce0b6201
YH		 2555 if (pci_set_dma_mask(pci, DMA_BIT_MASK(28)) < 0 ||
2556 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(28)) < 0) {
6dfb5aff
TI		 2557 dev_err(card->dev,
2558 "architecture does not support 28bit PCI busmaster DMA\n");
1da177e4
LT		 2559 pci_disable_device(pci);
2560 return -ENXIO;
2561 }
2562
e560d8d8 2563 ice = kzalloc(sizeof(*ice), GFP_KERNEL);
1da177e4
LT		 2564 if (ice == NULL) {
2565 pci_disable_device(pci);
2566 return -ENOMEM;
2567 }
2568 ice->omni = omni ? 1 : 0;
2569 if (cs8427_timeout < 1)
2570 cs8427_timeout = 1;
2571 else if (cs8427_timeout > 1000)
2572 cs8427_timeout = 1000;
2573 ice->cs8427_timeout = cs8427_timeout;
531af462 2574 ice->dxr_enable = dxr_enable;
1da177e4 2575 spin_lock_init(&ice->reg_lock);
62932df8
IM		 2576 mutex_init(&ice->gpio_mutex);
2577 mutex_init(&ice->i2c_mutex);
2578 mutex_init(&ice->open_mutex);
1da177e4 2579 ice->gpio.set_mask = snd_ice1712_set_gpio_mask;
49470306 2580 ice->gpio.get_mask = snd_ice1712_get_gpio_mask;
1da177e4 2581 ice->gpio.set_dir = snd_ice1712_set_gpio_dir;
49470306 2582 ice->gpio.get_dir = snd_ice1712_get_gpio_dir;
1da177e4
LT		 2583 ice->gpio.set_data = snd_ice1712_set_gpio_data;
2584 ice->gpio.get_data = snd_ice1712_get_gpio_data;
2585
2586 ice->spdif.cs8403_bits =
2587 ice->spdif.cs8403_stream_bits = (0x01 | /* consumer format */
2588 0x10 | /* no emphasis */
2589 0x20); /* PCM encoder/decoder */
2590 ice->card = card;
2591 ice->pci = pci;
2592 ice->irq = -1;
2593 pci_set_master(pci);
ca051e8a 2594 /* disable legacy emulation */
1da177e4
LT		 2595 pci_write_config_word(ice->pci, 0x40, 0x807f);
2596 pci_write_config_word(ice->pci, 0x42, 0x0006);
2597 snd_ice1712_proc_init(ice);
2598 synchronize_irq(pci->irq);
2599
69a4cfdd
SC		 2600 card->private_data = ice;
2601
3d8cb466
AB		 2602 err = pci_request_regions(pci, "ICE1712");
2603 if (err < 0) {
1da177e4
LT		 2604 kfree(ice);
2605 pci_disable_device(pci);
2606 return err;
2607 }
2608 ice->port = pci_resource_start(pci, 0);
2609 ice->ddma_port = pci_resource_start(pci, 1);
2610 ice->dmapath_port = pci_resource_start(pci, 2);
2611 ice->profi_port = pci_resource_start(pci, 3);
2612
437a5a46 2613 if (request_irq(pci->irq, snd_ice1712_interrupt, IRQF_SHARED,
934c2b6d 2614 KBUILD_MODNAME, ice)) {
6dfb5aff 2615 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
1da177e4
LT		 2616 snd_ice1712_free(ice);
2617 return -EIO;
2618 }
3d8cb466 2619
1da177e4
LT		 2620 ice->irq = pci->irq;
2621
2622 if (snd_ice1712_read_eeprom(ice, modelname) < 0) {
2623 snd_ice1712_free(ice);
2624 return -EIO;
2625 }
2626 if (snd_ice1712_chip_init(ice) < 0) {
2627 snd_ice1712_free(ice);
2628 return -EIO;
2629 }
2630
3d8cb466
AB		 2631 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ice, &ops);
2632 if (err < 0) {
1da177e4 2633 snd_ice1712_free(ice);
3d8cb466 2634 return err;
1da177e4
LT		 2635 }
2636
1da177e4
LT		 2637 *r_ice1712 = ice;
2638 return 0;
2639}
2640
2641
2642/*
2643 *
2644 * Registration
2645 *
2646 */
2647
e23e7a14 2648static struct snd_ice1712_card_info no_matched;
1da177e4 2649
e23e7a14
BP		 2650static int snd_ice1712_probe(struct pci_dev *pci,
2651 const struct pci_device_id *pci_id)
1da177e4
LT		 2652{
2653 static int dev;
6ca308d4
TI		 2654 struct snd_card *card;
2655 struct snd_ice1712 *ice;
1da177e4 2656 int pcm_dev = 0, err;
bf748ed7 2657 struct snd_ice1712_card_info * const *tbl, *c;
1da177e4
LT		 2658
2659 if (dev >= SNDRV_CARDS)
2660 return -ENODEV;
2661 if (!enable[dev]) {
2662 dev++;
2663 return -ENOENT;
2664 }
2665
60c5772b
TI		 2666 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2667 0, &card);
e58de7ba
TI		 2668 if (err < 0)
2669 return err;
1da177e4
LT		 2670
2671 strcpy(card->driver, "ICE1712");
2672 strcpy(card->shortname, "ICEnsemble ICE1712");
3d8cb466
AB		 2673
2674 err = snd_ice1712_create(card, pci, model[dev], omni[dev],
2675 cs8427_timeout[dev], dxr_enable[dev], &ice);
2676 if (err < 0) {
1da177e4
LT		 2677 snd_card_free(card);
2678 return err;
2679 }
2680
2681 for (tbl = card_tables; *tbl; tbl++) {
2682 for (c = *tbl; c->subvendor; c++) {
2683 if (c->subvendor == ice->eeprom.subvendor) {
267bccaf 2684 ice->card_info = c;
1da177e4
LT		 2685 strcpy(card->shortname, c->name);
2686 if (c->driver) /* specific driver? */
2687 strcpy(card->driver, c->driver);
2688 if (c->chip_init) {
3d8cb466
AB		 2689 err = c->chip_init(ice);
2690 if (err < 0) {
1da177e4
LT		 2691 snd_card_free(card);
2692 return err;
2693 }
2694 }
2695 goto __found;
2696 }
2697 }
2698 }
2699 c = &no_matched;
2700 __found:
2701
3d8cb466
AB		 2702 err = snd_ice1712_pcm_profi(ice, pcm_dev++, NULL);
2703 if (err < 0) {
1da177e4
LT		 2704 snd_card_free(card);
2705 return err;
2706 }
3d8cb466 2707
8cd2b264 2708 if (ice_has_con_ac97(ice)) {
3d8cb466
AB		 2709 err = snd_ice1712_pcm(ice, pcm_dev++, NULL);
2710 if (err < 0) {
1da177e4
LT		 2711 snd_card_free(card);
2712 return err;
2713 }
8cd2b264 2714 }
1da177e4 2715
3d8cb466
AB		 2716 err = snd_ice1712_ac97_mixer(ice);
2717 if (err < 0) {
1da177e4
LT		 2718 snd_card_free(card);
2719 return err;
2720 }
2721
3d8cb466
AB		 2722 err = snd_ice1712_build_controls(ice);
2723 if (err < 0) {
1da177e4
LT		 2724 snd_card_free(card);
2725 return err;
2726 }
2727
2728 if (c->build_controls) {
3d8cb466
AB		 2729 err = c->build_controls(ice);
2730 if (err < 0) {
1da177e4
LT		 2731 snd_card_free(card);
2732 return err;
2733 }
2734 }
2735
8cd2b264 2736 if (ice_has_con_ac97(ice)) {
3d8cb466
AB		 2737 err = snd_ice1712_pcm_ds(ice, pcm_dev++, NULL);
2738 if (err < 0) {
1da177e4
LT		 2739 snd_card_free(card);
2740 return err;
2741 }
8cd2b264 2742 }
1da177e4 2743
3d8cb466
AB		 2744 if (!c->no_mpu401) {
2745 err = snd_mpu401_uart_new(card, 0, MPU401_HW_ICE1712,
2746 ICEREG(ice, MPU1_CTRL),
dba8b469
CL		 2747 c->mpu401_1_info_flags |
2748 MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
2749 -1, &ice->rmidi[0]);
3d8cb466 2750 if (err < 0) {
1da177e4
LT		 2751 snd_card_free(card);
2752 return err;
2753 }
3bef229e 2754 if (c->mpu401_1_name)
25985edc 2755 /* Preferred name available in card_info */
3bef229e
AH		 2756 snprintf(ice->rmidi[0]->name,
2757 sizeof(ice->rmidi[0]->name),
2758 "%s %d", c->mpu401_1_name, card->number);
2759
2760 if (ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_2xMPU401) {
2761 /* 2nd port used */
3d8cb466
AB		 2762 err = snd_mpu401_uart_new(card, 1, MPU401_HW_ICE1712,
2763 ICEREG(ice, MPU2_CTRL),
dba8b469
CL		 2764 c->mpu401_2_info_flags |
2765 MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
2766 -1, &ice->rmidi[1]);
3d8cb466
AB		 2767
2768 if (err < 0) {
1da177e4
LT		 2769 snd_card_free(card);
2770 return err;
2771 }
3bef229e 2772 if (c->mpu401_2_name)
25985edc 2773 /* Preferred name available in card_info */
3bef229e
AH		 2774 snprintf(ice->rmidi[1]->name,
2775 sizeof(ice->rmidi[1]->name),
2776 "%s %d", c->mpu401_2_name,
2777 card->number);
2778 }
1da177e4
LT		 2779 }
2780
e957ebf1
JK		 2781 snd_ice1712_set_input_clock_source(ice, 0);
2782
1da177e4
LT		 2783 sprintf(card->longname, "%s at 0x%lx, irq %i",
2784 card->shortname, ice->port, ice->irq);
2785
3d8cb466
AB		 2786 err = snd_card_register(card);
2787 if (err < 0) {
1da177e4
LT		 2788 snd_card_free(card);
2789 return err;
2790 }
2791 pci_set_drvdata(pci, card);
2792 dev++;
2793 return 0;
2794}
2795
e23e7a14 2796static void snd_ice1712_remove(struct pci_dev *pci)
1da177e4 2797{
267bccaf
OZ		 2798 struct snd_card *card = pci_get_drvdata(pci);
2799 struct snd_ice1712 *ice = card->private_data;
2800
2801 if (ice->card_info && ice->card_info->chip_exit)
2802 ice->card_info->chip_exit(ice);
2803 snd_card_free(card);
1da177e4
LT		 2804}
2805
ca051e8a
OZ		 2806#ifdef CONFIG_PM_SLEEP
2807static int snd_ice1712_suspend(struct device *dev)
2808{
2809 struct pci_dev *pci = to_pci_dev(dev);
2810 struct snd_card *card = dev_get_drvdata(dev);
2811 struct snd_ice1712 *ice = card->private_data;
2812
2813 if (!ice->pm_suspend_enabled)
2814 return 0;
2815
2816 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2817
2818 snd_pcm_suspend_all(ice->pcm);
2819 snd_pcm_suspend_all(ice->pcm_pro);
2820 snd_pcm_suspend_all(ice->pcm_ds);
2821 snd_ac97_suspend(ice->ac97);
2822
6ea0cae7
OZ		 2823 spin_lock_irq(&ice->reg_lock);
2824 ice->pm_saved_is_spdif_master = is_spdif_master(ice);
2825 ice->pm_saved_spdif_ctrl = inw(ICEMT(ice, ROUTE_SPDOUT));
2826 ice->pm_saved_route = inw(ICEMT(ice, ROUTE_PSDOUT03));
2827 spin_unlock_irq(&ice->reg_lock);
2828
ca051e8a
OZ		 2829 if (ice->pm_suspend)
2830 ice->pm_suspend(ice);
2831
2832 pci_disable_device(pci);
2833 pci_save_state(pci);
2834 pci_set_power_state(pci, PCI_D3hot);
2835 return 0;
2836}
2837
2838static int snd_ice1712_resume(struct device *dev)
2839{
2840 struct pci_dev *pci = to_pci_dev(dev);
2841 struct snd_card *card = dev_get_drvdata(dev);
2842 struct snd_ice1712 *ice = card->private_data;
6ea0cae7 2843 int rate;
ca051e8a
OZ		 2844
2845 if (!ice->pm_suspend_enabled)
2846 return 0;
2847
2848 pci_set_power_state(pci, PCI_D0);
2849 pci_restore_state(pci);
2850
2851 if (pci_enable_device(pci) < 0) {
2852 snd_card_disconnect(card);
2853 return -EIO;
2854 }
2855
2856 pci_set_master(pci);
2857
6ea0cae7
OZ		 2858 if (ice->cur_rate)
2859 rate = ice->cur_rate;
2860 else
2861 rate = PRO_RATE_DEFAULT;
2862
ca051e8a
OZ		 2863 if (snd_ice1712_chip_init(ice) < 0) {
2864 snd_card_disconnect(card);
2865 return -EIO;
2866 }
2867
6ea0cae7
OZ		 2868 ice->cur_rate = rate;
2869
ca051e8a
OZ		 2870 if (ice->pm_resume)
2871 ice->pm_resume(ice);
2872
6ea0cae7
OZ		 2873 if (ice->pm_saved_is_spdif_master) {
2874 /* switching to external clock via SPDIF */
2875 spin_lock_irq(&ice->reg_lock);
2876 outb(inb(ICEMT(ice, RATE)) | ICE1712_SPDIF_MASTER,
2877 ICEMT(ice, RATE));
2878 spin_unlock_irq(&ice->reg_lock);
2879 snd_ice1712_set_input_clock_source(ice, 1);
2880 } else {
2881 /* internal on-card clock */
2882 snd_ice1712_set_pro_rate(ice, rate, 1);
2883 snd_ice1712_set_input_clock_source(ice, 0);
2884 }
2885
2886 outw(ice->pm_saved_spdif_ctrl, ICEMT(ice, ROUTE_SPDOUT));
2887 outw(ice->pm_saved_route, ICEMT(ice, ROUTE_PSDOUT03));
2888
ca051e8a
OZ		 2889 if (ice->ac97)
2890 snd_ac97_resume(ice->ac97);
2891
2892 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2893 return 0;
2894}
2895
2896static SIMPLE_DEV_PM_OPS(snd_ice1712_pm, snd_ice1712_suspend, snd_ice1712_resume);
2897#define SND_VT1712_PM_OPS &snd_ice1712_pm
2898#else
2899#define SND_VT1712_PM_OPS NULL
2900#endif /* CONFIG_PM_SLEEP */
2901
e9f66d9b 2902static struct pci_driver ice1712_driver = {
3733e424 2903 .name = KBUILD_MODNAME,
1da177e4
LT		 2904 .id_table = snd_ice1712_ids,
2905 .probe = snd_ice1712_probe,
e23e7a14 2906 .remove = snd_ice1712_remove,
ca051e8a
OZ		 2907 .driver = {
2908 .pm = SND_VT1712_PM_OPS,
2909 },
1da177e4
LT		 2910};
2911
e9f66d9b 2912module_pci_driver(ice1712_driver);
Linux kernel - Deliverables
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