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Merge branch 'timers/clockevents' of git://git.linaro.org/people/dlezcano/clockevents...
[deliverable/linux.git] / sound / pci / ice1712 / ice1712.h
CommitLineData
1da177e4
LT		 1#ifndef __SOUND_ICE1712_H
2#define __SOUND_ICE1712_H
3
4/*
5 * ALSA driver for ICEnsemble ICE1712 (Envy24)
6 *
c1017a4c 7 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
3d8cb466 23 */
1da177e4 24
de3ab850 25#include <linux/io.h>
1da177e4
LT		 26#include <sound/control.h>
27#include <sound/ac97_codec.h>
28#include <sound/rawmidi.h>
29#include <sound/i2c.h>
30#include <sound/ak4xxx-adda.h>
31#include <sound/ak4114.h>
feaa6a74 32#include <sound/pt2258.h>
1da177e4 33#include <sound/pcm.h>
cf78ee2c 34#include <sound/mpu401.h>
1da177e4
LT		 35
36
37/*
38 * Direct registers
39 */
40
41#define ICEREG(ice, x) ((ice)->port + ICE1712_REG_##x)
42
43#define ICE1712_REG_CONTROL 0x00 /* byte */
44#define ICE1712_RESET 0x80 /* reset whole chip */
45#define ICE1712_SERR_LEVEL 0x04 /* SERR# level otherwise edge */
46#define ICE1712_NATIVE 0x01 /* native mode otherwise SB */
47#define ICE1712_REG_IRQMASK 0x01 /* byte */
48#define ICE1712_IRQ_MPU1 0x80
49#define ICE1712_IRQ_TIMER 0x40
50#define ICE1712_IRQ_MPU2 0x20
51#define ICE1712_IRQ_PROPCM 0x10
52#define ICE1712_IRQ_FM 0x08 /* FM/MIDI - legacy */
53#define ICE1712_IRQ_PBKDS 0x04 /* playback DS channels */
54#define ICE1712_IRQ_CONCAP 0x02 /* consumer capture */
55#define ICE1712_IRQ_CONPBK 0x01 /* consumer playback */
56#define ICE1712_REG_IRQSTAT 0x02 /* byte */
57/* look to ICE1712_IRQ_* */
58#define ICE1712_REG_INDEX 0x03 /* byte - indirect CCIxx regs */
59#define ICE1712_REG_DATA 0x04 /* byte - indirect CCIxx regs */
60#define ICE1712_REG_NMI_STAT1 0x05 /* byte */
61#define ICE1712_REG_NMI_DATA 0x06 /* byte */
62#define ICE1712_REG_NMI_INDEX 0x07 /* byte */
63#define ICE1712_REG_AC97_INDEX 0x08 /* byte */
64#define ICE1712_REG_AC97_CMD 0x09 /* byte */
65#define ICE1712_AC97_COLD 0x80 /* cold reset */
66#define ICE1712_AC97_WARM 0x40 /* warm reset */
67#define ICE1712_AC97_WRITE 0x20 /* W: write, R: write in progress */
68#define ICE1712_AC97_READ 0x10 /* W: read, R: read in progress */
69#define ICE1712_AC97_READY 0x08 /* codec ready status bit */
70#define ICE1712_AC97_PBK_VSR 0x02 /* playback VSR */
71#define ICE1712_AC97_CAP_VSR 0x01 /* capture VSR */
72#define ICE1712_REG_AC97_DATA 0x0a /* word (little endian) */
73#define ICE1712_REG_MPU1_CTRL 0x0c /* byte */
74#define ICE1712_REG_MPU1_DATA 0x0d /* byte */
75#define ICE1712_REG_I2C_DEV_ADDR 0x10 /* byte */
76#define ICE1712_I2C_WRITE 0x01 /* write direction */
77#define ICE1712_REG_I2C_BYTE_ADDR 0x11 /* byte */
78#define ICE1712_REG_I2C_DATA 0x12 /* byte */
79#define ICE1712_REG_I2C_CTRL 0x13 /* byte */
80#define ICE1712_I2C_EEPROM 0x80 /* EEPROM exists */
81#define ICE1712_I2C_BUSY 0x01 /* busy bit */
82#define ICE1712_REG_CONCAP_ADDR 0x14 /* dword - consumer capture */
83#define ICE1712_REG_CONCAP_COUNT 0x18 /* word - current/base count */
84#define ICE1712_REG_SERR_SHADOW 0x1b /* byte */
85#define ICE1712_REG_MPU2_CTRL 0x1c /* byte */
86#define ICE1712_REG_MPU2_DATA 0x1d /* byte */
87#define ICE1712_REG_TIMER 0x1e /* word */
88
89/*
90 * Indirect registers
91 */
92
93#define ICE1712_IREG_PBK_COUNT_LO 0x00
94#define ICE1712_IREG_PBK_COUNT_HI 0x01
95#define ICE1712_IREG_PBK_CTRL 0x02
96#define ICE1712_IREG_PBK_LEFT 0x03 /* left volume */
97#define ICE1712_IREG_PBK_RIGHT 0x04 /* right volume */
98#define ICE1712_IREG_PBK_SOFT 0x05 /* soft volume */
99#define ICE1712_IREG_PBK_RATE_LO 0x06
100#define ICE1712_IREG_PBK_RATE_MID 0x07
101#define ICE1712_IREG_PBK_RATE_HI 0x08
102#define ICE1712_IREG_CAP_COUNT_LO 0x10
103#define ICE1712_IREG_CAP_COUNT_HI 0x11
104#define ICE1712_IREG_CAP_CTRL 0x12
105#define ICE1712_IREG_GPIO_DATA 0x20
106#define ICE1712_IREG_GPIO_WRITE_MASK 0x21
107#define ICE1712_IREG_GPIO_DIRECTION 0x22
108#define ICE1712_IREG_CONSUMER_POWERDOWN 0x30
109#define ICE1712_IREG_PRO_POWERDOWN 0x31
110
111/*
112 * Consumer section direct DMA registers
113 */
114
115#define ICEDS(ice, x) ((ice)->dmapath_port + ICE1712_DS_##x)
3d8cb466 116
1da177e4
LT		 117#define ICE1712_DS_INTMASK 0x00 /* word - interrupt mask */
118#define ICE1712_DS_INTSTAT 0x02 /* word - interrupt status */
119#define ICE1712_DS_DATA 0x04 /* dword - channel data */
120#define ICE1712_DS_INDEX 0x08 /* dword - channel index */
121
122/*
123 * Consumer section channel registers
124 */
3d8cb466 125
1da177e4
LT		 126#define ICE1712_DSC_ADDR0 0x00 /* dword - base address 0 */
127#define ICE1712_DSC_COUNT0 0x01 /* word - count 0 */
128#define ICE1712_DSC_ADDR1 0x02 /* dword - base address 1 */
129#define ICE1712_DSC_COUNT1 0x03 /* word - count 1 */
130#define ICE1712_DSC_CONTROL 0x04 /* byte - control & status */
131#define ICE1712_BUFFER1 0x80 /* buffer1 is active */
132#define ICE1712_BUFFER1_AUTO 0x40 /* buffer1 auto init */
133#define ICE1712_BUFFER0_AUTO 0x20 /* buffer0 auto init */
134#define ICE1712_FLUSH 0x10 /* flush FIFO */
135#define ICE1712_STEREO 0x08 /* stereo */
136#define ICE1712_16BIT 0x04 /* 16-bit data */
137#define ICE1712_PAUSE 0x02 /* pause */
138#define ICE1712_START 0x01 /* start */
139#define ICE1712_DSC_RATE 0x05 /* dword - rate */
140#define ICE1712_DSC_VOLUME 0x06 /* word - volume control */
141
3d8cb466 142/*
1da177e4
LT		 143 * Professional multi-track direct control registers
144 */
145
146#define ICEMT(ice, x) ((ice)->profi_port + ICE1712_MT_##x)
147
148#define ICE1712_MT_IRQ 0x00 /* byte - interrupt mask */
149#define ICE1712_MULTI_CAPTURE 0x80 /* capture IRQ */
150#define ICE1712_MULTI_PLAYBACK 0x40 /* playback IRQ */
151#define ICE1712_MULTI_CAPSTATUS 0x02 /* capture IRQ status */
152#define ICE1712_MULTI_PBKSTATUS 0x01 /* playback IRQ status */
153#define ICE1712_MT_RATE 0x01 /* byte - sampling rate select */
154#define ICE1712_SPDIF_MASTER 0x10 /* S/PDIF input is master clock */
155#define ICE1712_MT_I2S_FORMAT 0x02 /* byte - I2S data format */
156#define ICE1712_MT_AC97_INDEX 0x04 /* byte - AC'97 index */
157#define ICE1712_MT_AC97_CMD 0x05 /* byte - AC'97 command & status */
158/* look to ICE1712_AC97_* */
159#define ICE1712_MT_AC97_DATA 0x06 /* word - AC'97 data */
160#define ICE1712_MT_PLAYBACK_ADDR 0x10 /* dword - playback address */
161#define ICE1712_MT_PLAYBACK_SIZE 0x14 /* word - playback size */
162#define ICE1712_MT_PLAYBACK_COUNT 0x16 /* word - playback count */
163#define ICE1712_MT_PLAYBACK_CONTROL 0x18 /* byte - control */
164#define ICE1712_CAPTURE_START_SHADOW 0x04 /* capture start */
165#define ICE1712_PLAYBACK_PAUSE 0x02 /* playback pause */
166#define ICE1712_PLAYBACK_START 0x01 /* playback start */
167#define ICE1712_MT_CAPTURE_ADDR 0x20 /* dword - capture address */
168#define ICE1712_MT_CAPTURE_SIZE 0x24 /* word - capture size */
169#define ICE1712_MT_CAPTURE_COUNT 0x26 /* word - capture count */
170#define ICE1712_MT_CAPTURE_CONTROL 0x28 /* byte - control */
171#define ICE1712_CAPTURE_START 0x01 /* capture start */
172#define ICE1712_MT_ROUTE_PSDOUT03 0x30 /* word */
173#define ICE1712_MT_ROUTE_SPDOUT 0x32 /* word */
174#define ICE1712_MT_ROUTE_CAPTURE 0x34 /* dword */
175#define ICE1712_MT_MONITOR_VOLUME 0x38 /* word */
176#define ICE1712_MT_MONITOR_INDEX 0x3a /* byte */
177#define ICE1712_MT_MONITOR_RATE 0x3b /* byte */
178#define ICE1712_MT_MONITOR_ROUTECTRL 0x3c /* byte */
179#define ICE1712_ROUTE_AC97 0x01 /* route digital mixer output to AC'97 */
180#define ICE1712_MT_MONITOR_PEAKINDEX 0x3e /* byte */
181#define ICE1712_MT_MONITOR_PEAKDATA 0x3f /* byte */
182
183/*
184 * Codec configuration bits
185 */
186
187/* PCI[60] System Configuration */
188#define ICE1712_CFG_CLOCK 0xc0
189#define ICE1712_CFG_CLOCK512 0x00 /* 22.5692Mhz, 44.1kHz*512 */
190#define ICE1712_CFG_CLOCK384 0x40 /* 16.9344Mhz, 44.1kHz*384 */
191#define ICE1712_CFG_EXT 0x80 /* external clock */
192#define ICE1712_CFG_2xMPU401 0x20 /* two MPU401 UARTs */
193#define ICE1712_CFG_NO_CON_AC97 0x10 /* consumer AC'97 codec is not present */
194#define ICE1712_CFG_ADC_MASK 0x0c /* one, two, three, four stereo ADCs */
195#define ICE1712_CFG_DAC_MASK 0x03 /* one, two, three, four stereo DACs */
196/* PCI[61] AC-Link Configuration */
197#define ICE1712_CFG_PRO_I2S 0x80 /* multitrack converter: I2S or AC'97 */
198#define ICE1712_CFG_AC97_PACKED 0x01 /* split or packed mode - AC'97 */
199/* PCI[62] I2S Features */
200#define ICE1712_CFG_I2S_VOLUME 0x80 /* volume/mute capability */
201#define ICE1712_CFG_I2S_96KHZ 0x40 /* supports 96kHz sampling */
202#define ICE1712_CFG_I2S_RESMASK 0x30 /* resolution mask, 16,18,20,24-bit */
203#define ICE1712_CFG_I2S_OTHER 0x0f /* other I2S IDs */
204/* PCI[63] S/PDIF Configuration */
205#define ICE1712_CFG_I2S_CHIPID 0xfc /* I2S chip ID */
206#define ICE1712_CFG_SPDIF_IN 0x02 /* S/PDIF input is present */
207#define ICE1712_CFG_SPDIF_OUT 0x01 /* S/PDIF output is present */
208
209/*
210 * DMA mode values
211 * identical with DMA_XXX on i386 architecture.
212 */
213#define ICE1712_DMA_MODE_WRITE 0x48
214#define ICE1712_DMA_AUTOINIT 0x10
215
216
217/*
3d8cb466 218 *
1da177e4
LT		 219 */
220
6ca308d4 221struct snd_ice1712;
1da177e4 222
6ca308d4 223struct snd_ice1712_eeprom {
1da177e4
LT		 224 unsigned int subvendor; /* PCI[2c-2f] */
225 unsigned char size; /* size of EEPROM image in bytes */
226 unsigned char version; /* must be 1 (or 2 for vt1724) */
227 unsigned char data[32];
228 unsigned int gpiomask;
229 unsigned int gpiostate;
230 unsigned int gpiodir;
6ca308d4 231};
1da177e4
LT		 232
233enum {
234 ICE_EEP1_CODEC = 0, /* 06 */
235 ICE_EEP1_ACLINK, /* 07 */
236 ICE_EEP1_I2SID, /* 08 */
237 ICE_EEP1_SPDIF, /* 09 */
238 ICE_EEP1_GPIO_MASK, /* 0a */
239 ICE_EEP1_GPIO_STATE, /* 0b */
240 ICE_EEP1_GPIO_DIR, /* 0c */
241 ICE_EEP1_AC97_MAIN_LO, /* 0d */
242 ICE_EEP1_AC97_MAIN_HI, /* 0e */
243 ICE_EEP1_AC97_PCM_LO, /* 0f */
244 ICE_EEP1_AC97_PCM_HI, /* 10 */
245 ICE_EEP1_AC97_REC_LO, /* 11 */
246 ICE_EEP1_AC97_REC_HI, /* 12 */
247 ICE_EEP1_AC97_RECSRC, /* 13 */
248 ICE_EEP1_DAC_ID, /* 14 */
249 ICE_EEP1_DAC_ID1,
250 ICE_EEP1_DAC_ID2,
251 ICE_EEP1_DAC_ID3,
252 ICE_EEP1_ADC_ID, /* 18 */
253 ICE_EEP1_ADC_ID1,
254 ICE_EEP1_ADC_ID2,
255 ICE_EEP1_ADC_ID3
256};
3d8cb466 257
1da177e4
LT		 258#define ice_has_con_ac97(ice) (!((ice)->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97))
259
260
261struct snd_ak4xxx_private {
3d8cb466 262 unsigned int cif:1; /* CIF mode */
1da177e4
LT		 263 unsigned char caddr; /* C0 and C1 bits */
264 unsigned int data_mask; /* DATA gpio bit */
265 unsigned int clk_mask; /* CLK gpio bit */
266 unsigned int cs_mask; /* bit mask for select/deselect address */
267 unsigned int cs_addr; /* bits to select address */
268 unsigned int cs_none; /* bits to deselect address */
269 unsigned int add_flags; /* additional bits at init */
270 unsigned int mask_flags; /* total mask bits */
271 struct snd_akm4xxx_ops {
6ca308d4 272 void (*set_rate_val)(struct snd_akm4xxx *ak, unsigned int rate);
1da177e4
LT		 273 } ops;
274};
275
276struct snd_ice1712_spdif {
277 unsigned char cs8403_bits;
278 unsigned char cs8403_stream_bits;
6ca308d4 279 struct snd_kcontrol *stream_ctl;
1da177e4
LT		 280
281 struct snd_ice1712_spdif_ops {
6ca308d4
TI		 282 void (*open)(struct snd_ice1712 *, struct snd_pcm_substream *);
283 void (*setup_rate)(struct snd_ice1712 *, int rate);
284 void (*close)(struct snd_ice1712 *, struct snd_pcm_substream *);
285 void (*default_get)(struct snd_ice1712 *, struct snd_ctl_elem_value *ucontrol);
286 int (*default_put)(struct snd_ice1712 *, struct snd_ctl_elem_value *ucontrol);
287 void (*stream_get)(struct snd_ice1712 *, struct snd_ctl_elem_value *ucontrol);
288 int (*stream_put)(struct snd_ice1712 *, struct snd_ctl_elem_value *ucontrol);
1da177e4
LT		 289 } ops;
290};
291
267bccaf 292struct snd_ice1712_card_info;
1da177e4 293
6ca308d4 294struct snd_ice1712 {
1da177e4
LT		 295 unsigned long conp_dma_size;
296 unsigned long conc_dma_size;
297 unsigned long prop_dma_size;
298 unsigned long proc_dma_size;
299 int irq;
300
301 unsigned long port;
302 unsigned long ddma_port;
303 unsigned long dmapath_port;
304 unsigned long profi_port;
305
306 struct pci_dev *pci;
6ca308d4
TI		 307 struct snd_card *card;
308 struct snd_pcm *pcm;
309 struct snd_pcm *pcm_ds;
310 struct snd_pcm *pcm_pro;
3d8cb466
AB		 311 struct snd_pcm_substream *playback_con_substream;
312 struct snd_pcm_substream *playback_con_substream_ds[6];
313 struct snd_pcm_substream *capture_con_substream;
314 struct snd_pcm_substream *playback_pro_substream;
315 struct snd_pcm_substream *capture_pro_substream;
1da177e4
LT		 316 unsigned int playback_pro_size;
317 unsigned int capture_pro_size;
318 unsigned int playback_con_virt_addr[6];
319 unsigned int playback_con_active_buf[6];
320 unsigned int capture_con_virt_addr;
321 unsigned int ac97_ext_id;
6ca308d4
TI		 322 struct snd_ac97 *ac97;
323 struct snd_rawmidi *rmidi[2];
1da177e4
LT		 324
325 spinlock_t reg_lock;
6ca308d4 326 struct snd_info_entry *proc_entry;
1da177e4 327
6ca308d4 328 struct snd_ice1712_eeprom eeprom;
267bccaf 329 struct snd_ice1712_card_info *card_info;
1da177e4
LT		 330
331 unsigned int pro_volumes[20];
3d8cb466
AB		 332 unsigned int omni:1; /* Delta Omni I/O */
333 unsigned int dxr_enable:1; /* Terratec DXR enable for DMX6FIRE */
334 unsigned int vt1724:1;
335 unsigned int vt1720:1;
336 unsigned int has_spdif:1; /* VT1720/4 - has SPDIF I/O */
337 unsigned int force_pdma4:1; /* VT1720/4 - PDMA4 as non-spdif */
338 unsigned int force_rdma1:1; /* VT1720/4 - RDMA1 as non-spdif */
339 unsigned int midi_output:1; /* VT1720/4: MIDI output triggered */
340 unsigned int midi_input:1; /* VT1720/4: MIDI input triggered */
2bf864ac 341 unsigned int own_routing:1; /* VT1720/4: use own routing ctls */
1da177e4
LT		 342 unsigned int num_total_dacs; /* total DACs */
343 unsigned int num_total_adcs; /* total ADCs */
344 unsigned int cur_rate; /* current rate */
345
62932df8 346 struct mutex open_mutex;
6ca308d4
TI		 347 struct snd_pcm_substream *pcm_reserved[4];
348 struct snd_pcm_hw_constraint_list *hw_rates; /* card-specific rate constraints */
1da177e4
LT		 349
350 unsigned int akm_codecs;
6ca308d4 351 struct snd_akm4xxx *akm;
1da177e4
LT		 352 struct snd_ice1712_spdif spdif;
353
62932df8 354 struct mutex i2c_mutex; /* I2C mutex for ICE1724 registers */
6ca308d4
TI		 355 struct snd_i2c_bus *i2c; /* I2C bus */
356 struct snd_i2c_device *cs8427; /* CS8427 I2C device */
1da177e4 357 unsigned int cs8427_timeout; /* CS8427 reset timeout in HZ/100 */
3d8cb466 358
1da177e4
LT		 359 struct ice1712_gpio {
360 unsigned int direction; /* current direction bits */
361 unsigned int write_mask; /* current mask bits */
362 unsigned int saved[2]; /* for ewx_i2c */
363 /* operators */
6ca308d4 364 void (*set_mask)(struct snd_ice1712 *ice, unsigned int data);
49470306 365 unsigned int (*get_mask)(struct snd_ice1712 *ice);
6ca308d4 366 void (*set_dir)(struct snd_ice1712 *ice, unsigned int data);
49470306 367 unsigned int (*get_dir)(struct snd_ice1712 *ice);
6ca308d4
TI		 368 void (*set_data)(struct snd_ice1712 *ice, unsigned int data);
369 unsigned int (*get_data)(struct snd_ice1712 *ice);
1da177e4 370 /* misc operators - move to another place? */
6ca308d4
TI		 371 void (*set_pro_rate)(struct snd_ice1712 *ice, unsigned int rate);
372 void (*i2s_mclk_changed)(struct snd_ice1712 *ice);
1da177e4 373 } gpio;
62932df8 374 struct mutex gpio_mutex;
1da177e4
LT		 375
376 /* other board-specific data */
7cda8ba9 377 void *spec;
d16be8ed
PH		 378
379 /* VT172x specific */
380 int pro_rate_default;
381 int (*is_spdif_master)(struct snd_ice1712 *ice);
382 unsigned int (*get_rate)(struct snd_ice1712 *ice);
383 void (*set_rate)(struct snd_ice1712 *ice, unsigned int rate);
384 unsigned char (*set_mclk)(struct snd_ice1712 *ice, unsigned int rate);
1ff97cb9
PH		 385 int (*set_spdif_clock)(struct snd_ice1712 *ice, int type);
386 int (*get_spdif_master_type)(struct snd_ice1712 *ice);
a2af050f 387 const char * const *ext_clock_names;
1ff97cb9
PH		 388 int ext_clock_count;
389 void (*pro_open)(struct snd_ice1712 *, struct snd_pcm_substream *);
c7561cd8 390#ifdef CONFIG_PM_SLEEP
b40e9538
IC		 391 int (*pm_suspend)(struct snd_ice1712 *);
392 int (*pm_resume)(struct snd_ice1712 *);
bf974020
DC		 393 unsigned int pm_suspend_enabled:1;
394 unsigned int pm_saved_is_spdif_master:1;
b40e9538
IC		 395 unsigned int pm_saved_spdif_ctrl;
396 unsigned char pm_saved_spdif_cfg;
397 unsigned int pm_saved_route;
398#endif
1da177e4
LT		 399};
400
401
402/*
403 * gpio access functions
404 */
6ca308d4 405static inline void snd_ice1712_gpio_set_dir(struct snd_ice1712 *ice, unsigned int bits)
1da177e4
LT		 406{
407 ice->gpio.set_dir(ice, bits);
408}
409
49470306
PH		 410static inline unsigned int snd_ice1712_gpio_get_dir(struct snd_ice1712 *ice)
411{
412 return ice->gpio.get_dir(ice);
413}
414
6ca308d4 415static inline void snd_ice1712_gpio_set_mask(struct snd_ice1712 *ice, unsigned int bits)
1da177e4
LT		 416{
417 ice->gpio.set_mask(ice, bits);
418}
419
6ca308d4 420static inline void snd_ice1712_gpio_write(struct snd_ice1712 *ice, unsigned int val)
1da177e4
LT		 421{
422 ice->gpio.set_data(ice, val);
423}
424
6ca308d4 425static inline unsigned int snd_ice1712_gpio_read(struct snd_ice1712 *ice)
1da177e4
LT		 426{
427 return ice->gpio.get_data(ice);
428}
429
430/*
431 * save and restore gpio status
432 * The access to gpio will be protected by mutex, so don't forget to
433 * restore!
434 */
6ca308d4 435static inline void snd_ice1712_save_gpio_status(struct snd_ice1712 *ice)
1da177e4 436{
62932df8 437 mutex_lock(&ice->gpio_mutex);
1da177e4
LT		 438 ice->gpio.saved[0] = ice->gpio.direction;
439 ice->gpio.saved[1] = ice->gpio.write_mask;
440}
441
6ca308d4 442static inline void snd_ice1712_restore_gpio_status(struct snd_ice1712 *ice)
1da177e4
LT		 443{
444 ice->gpio.set_dir(ice, ice->gpio.saved[0]);
445 ice->gpio.set_mask(ice, ice->gpio.saved[1]);
446 ice->gpio.direction = ice->gpio.saved[0];
447 ice->gpio.write_mask = ice->gpio.saved[1];
62932df8 448 mutex_unlock(&ice->gpio_mutex);
1da177e4
LT		 449}
450
451/* for bit controls */
452#define ICE1712_GPIO(xiface, xname, xindex, mask, invert, xaccess) \
00283886 453{ .iface = xiface, .name = xname, .access = xaccess, .info = snd_ctl_boolean_mono_info, \
1da177e4
LT		 454 .get = snd_ice1712_gpio_get, .put = snd_ice1712_gpio_put, \
455 .private_value = mask | (invert << 24) }
456
6ca308d4
TI		 457int snd_ice1712_gpio_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
458int snd_ice1712_gpio_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
1da177e4
LT		 459
460/*
461 * set gpio direction, write mask and data
462 */
6ca308d4
TI		 463static inline void snd_ice1712_gpio_write_bits(struct snd_ice1712 *ice,
464 unsigned int mask, unsigned int bits)
1da177e4 465{
775c199e
KW		 466 unsigned val;
467
1da177e4
LT		 468 ice->gpio.direction |= mask;
469 snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
775c199e
KW		 470 val = snd_ice1712_gpio_read(ice);
471 val &= ~mask;
472 val |= mask & bits;
473 snd_ice1712_gpio_write(ice, val);
1da177e4
LT		 474}
475
feaa6a74
JV		 476static inline int snd_ice1712_gpio_read_bits(struct snd_ice1712 *ice,
477 unsigned int mask)
478{
479 ice->gpio.direction &= ~mask;
480 snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
3d8cb466 481 return snd_ice1712_gpio_read(ice) & mask;
feaa6a74
JV		 482}
483
2bf864ac
TI		 484/* route access functions */
485int snd_ice1724_get_route_val(struct snd_ice1712 *ice, int shift);
486int snd_ice1724_put_route_val(struct snd_ice1712 *ice, unsigned int val,
487 int shift);
488
6ca308d4 489int snd_ice1712_spdif_build_controls(struct snd_ice1712 *ice);
1da177e4 490
2bf864ac
TI		 491int snd_ice1712_akm4xxx_init(struct snd_akm4xxx *ak,
492 const struct snd_akm4xxx *template,
493 const struct snd_ak4xxx_private *priv,
494 struct snd_ice1712 *ice);
6ca308d4
TI		 495void snd_ice1712_akm4xxx_free(struct snd_ice1712 *ice);
496int snd_ice1712_akm4xxx_build_controls(struct snd_ice1712 *ice);
1da177e4 497
6ca308d4 498int snd_ice1712_init_cs8427(struct snd_ice1712 *ice, int addr);
1da177e4 499
3d8cb466 500static inline void snd_ice1712_write(struct snd_ice1712 *ice, u8 addr, u8 data)
1da177e4
LT		 501{
502 outb(addr, ICEREG(ice, INDEX));
503 outb(data, ICEREG(ice, DATA));
504}
505
3d8cb466 506static inline u8 snd_ice1712_read(struct snd_ice1712 *ice, u8 addr)
1da177e4
LT		 507{
508 outb(addr, ICEREG(ice, INDEX));
509 return inb(ICEREG(ice, DATA));
510}
511
512
513/*
514 * entry pointer
515 */
516
517struct snd_ice1712_card_info {
518 unsigned int subvendor;
a2af050f
TI		 519 const char *name;
520 const char *model;
521 const char *driver;
6ca308d4 522 int (*chip_init)(struct snd_ice1712 *);
267bccaf 523 void (*chip_exit)(struct snd_ice1712 *);
6ca308d4 524 int (*build_controls)(struct snd_ice1712 *);
3d8cb466 525 unsigned int no_mpu401:1;
cf78ee2c
AH		 526 unsigned int mpu401_1_info_flags;
527 unsigned int mpu401_2_info_flags;
3bef229e
AH		 528 const char *mpu401_1_name;
529 const char *mpu401_2_name;
32b47da0
TI		 530 const unsigned int eeprom_size;
531 const unsigned char *eeprom_data;
1da177e4
LT		 532};
533
534
535#endif /* __SOUND_ICE1712_H */
Linux kernel - Deliverables
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