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1da177e4 LT |
1 | #ifndef __SOUND_ICE1712_H |
2 | #define __SOUND_ICE1712_H | |
3 | ||
4 | /* | |
5 | * ALSA driver for ICEnsemble ICE1712 (Envy24) | |
6 | * | |
c1017a4c | 7 | * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz> |
1da177e4 LT |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | */ | |
24 | ||
25 | #include <sound/control.h> | |
26 | #include <sound/ac97_codec.h> | |
27 | #include <sound/rawmidi.h> | |
28 | #include <sound/i2c.h> | |
29 | #include <sound/ak4xxx-adda.h> | |
30 | #include <sound/ak4114.h> | |
feaa6a74 | 31 | #include <sound/pt2258.h> |
1da177e4 | 32 | #include <sound/pcm.h> |
cf78ee2c | 33 | #include <sound/mpu401.h> |
1da177e4 LT |
34 | |
35 | ||
36 | /* | |
37 | * Direct registers | |
38 | */ | |
39 | ||
40 | #define ICEREG(ice, x) ((ice)->port + ICE1712_REG_##x) | |
41 | ||
42 | #define ICE1712_REG_CONTROL 0x00 /* byte */ | |
43 | #define ICE1712_RESET 0x80 /* reset whole chip */ | |
44 | #define ICE1712_SERR_LEVEL 0x04 /* SERR# level otherwise edge */ | |
45 | #define ICE1712_NATIVE 0x01 /* native mode otherwise SB */ | |
46 | #define ICE1712_REG_IRQMASK 0x01 /* byte */ | |
47 | #define ICE1712_IRQ_MPU1 0x80 | |
48 | #define ICE1712_IRQ_TIMER 0x40 | |
49 | #define ICE1712_IRQ_MPU2 0x20 | |
50 | #define ICE1712_IRQ_PROPCM 0x10 | |
51 | #define ICE1712_IRQ_FM 0x08 /* FM/MIDI - legacy */ | |
52 | #define ICE1712_IRQ_PBKDS 0x04 /* playback DS channels */ | |
53 | #define ICE1712_IRQ_CONCAP 0x02 /* consumer capture */ | |
54 | #define ICE1712_IRQ_CONPBK 0x01 /* consumer playback */ | |
55 | #define ICE1712_REG_IRQSTAT 0x02 /* byte */ | |
56 | /* look to ICE1712_IRQ_* */ | |
57 | #define ICE1712_REG_INDEX 0x03 /* byte - indirect CCIxx regs */ | |
58 | #define ICE1712_REG_DATA 0x04 /* byte - indirect CCIxx regs */ | |
59 | #define ICE1712_REG_NMI_STAT1 0x05 /* byte */ | |
60 | #define ICE1712_REG_NMI_DATA 0x06 /* byte */ | |
61 | #define ICE1712_REG_NMI_INDEX 0x07 /* byte */ | |
62 | #define ICE1712_REG_AC97_INDEX 0x08 /* byte */ | |
63 | #define ICE1712_REG_AC97_CMD 0x09 /* byte */ | |
64 | #define ICE1712_AC97_COLD 0x80 /* cold reset */ | |
65 | #define ICE1712_AC97_WARM 0x40 /* warm reset */ | |
66 | #define ICE1712_AC97_WRITE 0x20 /* W: write, R: write in progress */ | |
67 | #define ICE1712_AC97_READ 0x10 /* W: read, R: read in progress */ | |
68 | #define ICE1712_AC97_READY 0x08 /* codec ready status bit */ | |
69 | #define ICE1712_AC97_PBK_VSR 0x02 /* playback VSR */ | |
70 | #define ICE1712_AC97_CAP_VSR 0x01 /* capture VSR */ | |
71 | #define ICE1712_REG_AC97_DATA 0x0a /* word (little endian) */ | |
72 | #define ICE1712_REG_MPU1_CTRL 0x0c /* byte */ | |
73 | #define ICE1712_REG_MPU1_DATA 0x0d /* byte */ | |
74 | #define ICE1712_REG_I2C_DEV_ADDR 0x10 /* byte */ | |
75 | #define ICE1712_I2C_WRITE 0x01 /* write direction */ | |
76 | #define ICE1712_REG_I2C_BYTE_ADDR 0x11 /* byte */ | |
77 | #define ICE1712_REG_I2C_DATA 0x12 /* byte */ | |
78 | #define ICE1712_REG_I2C_CTRL 0x13 /* byte */ | |
79 | #define ICE1712_I2C_EEPROM 0x80 /* EEPROM exists */ | |
80 | #define ICE1712_I2C_BUSY 0x01 /* busy bit */ | |
81 | #define ICE1712_REG_CONCAP_ADDR 0x14 /* dword - consumer capture */ | |
82 | #define ICE1712_REG_CONCAP_COUNT 0x18 /* word - current/base count */ | |
83 | #define ICE1712_REG_SERR_SHADOW 0x1b /* byte */ | |
84 | #define ICE1712_REG_MPU2_CTRL 0x1c /* byte */ | |
85 | #define ICE1712_REG_MPU2_DATA 0x1d /* byte */ | |
86 | #define ICE1712_REG_TIMER 0x1e /* word */ | |
87 | ||
88 | /* | |
89 | * Indirect registers | |
90 | */ | |
91 | ||
92 | #define ICE1712_IREG_PBK_COUNT_LO 0x00 | |
93 | #define ICE1712_IREG_PBK_COUNT_HI 0x01 | |
94 | #define ICE1712_IREG_PBK_CTRL 0x02 | |
95 | #define ICE1712_IREG_PBK_LEFT 0x03 /* left volume */ | |
96 | #define ICE1712_IREG_PBK_RIGHT 0x04 /* right volume */ | |
97 | #define ICE1712_IREG_PBK_SOFT 0x05 /* soft volume */ | |
98 | #define ICE1712_IREG_PBK_RATE_LO 0x06 | |
99 | #define ICE1712_IREG_PBK_RATE_MID 0x07 | |
100 | #define ICE1712_IREG_PBK_RATE_HI 0x08 | |
101 | #define ICE1712_IREG_CAP_COUNT_LO 0x10 | |
102 | #define ICE1712_IREG_CAP_COUNT_HI 0x11 | |
103 | #define ICE1712_IREG_CAP_CTRL 0x12 | |
104 | #define ICE1712_IREG_GPIO_DATA 0x20 | |
105 | #define ICE1712_IREG_GPIO_WRITE_MASK 0x21 | |
106 | #define ICE1712_IREG_GPIO_DIRECTION 0x22 | |
107 | #define ICE1712_IREG_CONSUMER_POWERDOWN 0x30 | |
108 | #define ICE1712_IREG_PRO_POWERDOWN 0x31 | |
109 | ||
110 | /* | |
111 | * Consumer section direct DMA registers | |
112 | */ | |
113 | ||
114 | #define ICEDS(ice, x) ((ice)->dmapath_port + ICE1712_DS_##x) | |
115 | ||
116 | #define ICE1712_DS_INTMASK 0x00 /* word - interrupt mask */ | |
117 | #define ICE1712_DS_INTSTAT 0x02 /* word - interrupt status */ | |
118 | #define ICE1712_DS_DATA 0x04 /* dword - channel data */ | |
119 | #define ICE1712_DS_INDEX 0x08 /* dword - channel index */ | |
120 | ||
121 | /* | |
122 | * Consumer section channel registers | |
123 | */ | |
124 | ||
125 | #define ICE1712_DSC_ADDR0 0x00 /* dword - base address 0 */ | |
126 | #define ICE1712_DSC_COUNT0 0x01 /* word - count 0 */ | |
127 | #define ICE1712_DSC_ADDR1 0x02 /* dword - base address 1 */ | |
128 | #define ICE1712_DSC_COUNT1 0x03 /* word - count 1 */ | |
129 | #define ICE1712_DSC_CONTROL 0x04 /* byte - control & status */ | |
130 | #define ICE1712_BUFFER1 0x80 /* buffer1 is active */ | |
131 | #define ICE1712_BUFFER1_AUTO 0x40 /* buffer1 auto init */ | |
132 | #define ICE1712_BUFFER0_AUTO 0x20 /* buffer0 auto init */ | |
133 | #define ICE1712_FLUSH 0x10 /* flush FIFO */ | |
134 | #define ICE1712_STEREO 0x08 /* stereo */ | |
135 | #define ICE1712_16BIT 0x04 /* 16-bit data */ | |
136 | #define ICE1712_PAUSE 0x02 /* pause */ | |
137 | #define ICE1712_START 0x01 /* start */ | |
138 | #define ICE1712_DSC_RATE 0x05 /* dword - rate */ | |
139 | #define ICE1712_DSC_VOLUME 0x06 /* word - volume control */ | |
140 | ||
141 | /* | |
142 | * Professional multi-track direct control registers | |
143 | */ | |
144 | ||
145 | #define ICEMT(ice, x) ((ice)->profi_port + ICE1712_MT_##x) | |
146 | ||
147 | #define ICE1712_MT_IRQ 0x00 /* byte - interrupt mask */ | |
148 | #define ICE1712_MULTI_CAPTURE 0x80 /* capture IRQ */ | |
149 | #define ICE1712_MULTI_PLAYBACK 0x40 /* playback IRQ */ | |
150 | #define ICE1712_MULTI_CAPSTATUS 0x02 /* capture IRQ status */ | |
151 | #define ICE1712_MULTI_PBKSTATUS 0x01 /* playback IRQ status */ | |
152 | #define ICE1712_MT_RATE 0x01 /* byte - sampling rate select */ | |
153 | #define ICE1712_SPDIF_MASTER 0x10 /* S/PDIF input is master clock */ | |
154 | #define ICE1712_MT_I2S_FORMAT 0x02 /* byte - I2S data format */ | |
155 | #define ICE1712_MT_AC97_INDEX 0x04 /* byte - AC'97 index */ | |
156 | #define ICE1712_MT_AC97_CMD 0x05 /* byte - AC'97 command & status */ | |
157 | /* look to ICE1712_AC97_* */ | |
158 | #define ICE1712_MT_AC97_DATA 0x06 /* word - AC'97 data */ | |
159 | #define ICE1712_MT_PLAYBACK_ADDR 0x10 /* dword - playback address */ | |
160 | #define ICE1712_MT_PLAYBACK_SIZE 0x14 /* word - playback size */ | |
161 | #define ICE1712_MT_PLAYBACK_COUNT 0x16 /* word - playback count */ | |
162 | #define ICE1712_MT_PLAYBACK_CONTROL 0x18 /* byte - control */ | |
163 | #define ICE1712_CAPTURE_START_SHADOW 0x04 /* capture start */ | |
164 | #define ICE1712_PLAYBACK_PAUSE 0x02 /* playback pause */ | |
165 | #define ICE1712_PLAYBACK_START 0x01 /* playback start */ | |
166 | #define ICE1712_MT_CAPTURE_ADDR 0x20 /* dword - capture address */ | |
167 | #define ICE1712_MT_CAPTURE_SIZE 0x24 /* word - capture size */ | |
168 | #define ICE1712_MT_CAPTURE_COUNT 0x26 /* word - capture count */ | |
169 | #define ICE1712_MT_CAPTURE_CONTROL 0x28 /* byte - control */ | |
170 | #define ICE1712_CAPTURE_START 0x01 /* capture start */ | |
171 | #define ICE1712_MT_ROUTE_PSDOUT03 0x30 /* word */ | |
172 | #define ICE1712_MT_ROUTE_SPDOUT 0x32 /* word */ | |
173 | #define ICE1712_MT_ROUTE_CAPTURE 0x34 /* dword */ | |
174 | #define ICE1712_MT_MONITOR_VOLUME 0x38 /* word */ | |
175 | #define ICE1712_MT_MONITOR_INDEX 0x3a /* byte */ | |
176 | #define ICE1712_MT_MONITOR_RATE 0x3b /* byte */ | |
177 | #define ICE1712_MT_MONITOR_ROUTECTRL 0x3c /* byte */ | |
178 | #define ICE1712_ROUTE_AC97 0x01 /* route digital mixer output to AC'97 */ | |
179 | #define ICE1712_MT_MONITOR_PEAKINDEX 0x3e /* byte */ | |
180 | #define ICE1712_MT_MONITOR_PEAKDATA 0x3f /* byte */ | |
181 | ||
182 | /* | |
183 | * Codec configuration bits | |
184 | */ | |
185 | ||
186 | /* PCI[60] System Configuration */ | |
187 | #define ICE1712_CFG_CLOCK 0xc0 | |
188 | #define ICE1712_CFG_CLOCK512 0x00 /* 22.5692Mhz, 44.1kHz*512 */ | |
189 | #define ICE1712_CFG_CLOCK384 0x40 /* 16.9344Mhz, 44.1kHz*384 */ | |
190 | #define ICE1712_CFG_EXT 0x80 /* external clock */ | |
191 | #define ICE1712_CFG_2xMPU401 0x20 /* two MPU401 UARTs */ | |
192 | #define ICE1712_CFG_NO_CON_AC97 0x10 /* consumer AC'97 codec is not present */ | |
193 | #define ICE1712_CFG_ADC_MASK 0x0c /* one, two, three, four stereo ADCs */ | |
194 | #define ICE1712_CFG_DAC_MASK 0x03 /* one, two, three, four stereo DACs */ | |
195 | /* PCI[61] AC-Link Configuration */ | |
196 | #define ICE1712_CFG_PRO_I2S 0x80 /* multitrack converter: I2S or AC'97 */ | |
197 | #define ICE1712_CFG_AC97_PACKED 0x01 /* split or packed mode - AC'97 */ | |
198 | /* PCI[62] I2S Features */ | |
199 | #define ICE1712_CFG_I2S_VOLUME 0x80 /* volume/mute capability */ | |
200 | #define ICE1712_CFG_I2S_96KHZ 0x40 /* supports 96kHz sampling */ | |
201 | #define ICE1712_CFG_I2S_RESMASK 0x30 /* resolution mask, 16,18,20,24-bit */ | |
202 | #define ICE1712_CFG_I2S_OTHER 0x0f /* other I2S IDs */ | |
203 | /* PCI[63] S/PDIF Configuration */ | |
204 | #define ICE1712_CFG_I2S_CHIPID 0xfc /* I2S chip ID */ | |
205 | #define ICE1712_CFG_SPDIF_IN 0x02 /* S/PDIF input is present */ | |
206 | #define ICE1712_CFG_SPDIF_OUT 0x01 /* S/PDIF output is present */ | |
207 | ||
208 | /* | |
209 | * DMA mode values | |
210 | * identical with DMA_XXX on i386 architecture. | |
211 | */ | |
212 | #define ICE1712_DMA_MODE_WRITE 0x48 | |
213 | #define ICE1712_DMA_AUTOINIT 0x10 | |
214 | ||
215 | ||
216 | /* | |
217 | * | |
218 | */ | |
219 | ||
6ca308d4 | 220 | struct snd_ice1712; |
1da177e4 | 221 | |
6ca308d4 | 222 | struct snd_ice1712_eeprom { |
1da177e4 LT |
223 | unsigned int subvendor; /* PCI[2c-2f] */ |
224 | unsigned char size; /* size of EEPROM image in bytes */ | |
225 | unsigned char version; /* must be 1 (or 2 for vt1724) */ | |
226 | unsigned char data[32]; | |
227 | unsigned int gpiomask; | |
228 | unsigned int gpiostate; | |
229 | unsigned int gpiodir; | |
6ca308d4 | 230 | }; |
1da177e4 LT |
231 | |
232 | enum { | |
233 | ICE_EEP1_CODEC = 0, /* 06 */ | |
234 | ICE_EEP1_ACLINK, /* 07 */ | |
235 | ICE_EEP1_I2SID, /* 08 */ | |
236 | ICE_EEP1_SPDIF, /* 09 */ | |
237 | ICE_EEP1_GPIO_MASK, /* 0a */ | |
238 | ICE_EEP1_GPIO_STATE, /* 0b */ | |
239 | ICE_EEP1_GPIO_DIR, /* 0c */ | |
240 | ICE_EEP1_AC97_MAIN_LO, /* 0d */ | |
241 | ICE_EEP1_AC97_MAIN_HI, /* 0e */ | |
242 | ICE_EEP1_AC97_PCM_LO, /* 0f */ | |
243 | ICE_EEP1_AC97_PCM_HI, /* 10 */ | |
244 | ICE_EEP1_AC97_REC_LO, /* 11 */ | |
245 | ICE_EEP1_AC97_REC_HI, /* 12 */ | |
246 | ICE_EEP1_AC97_RECSRC, /* 13 */ | |
247 | ICE_EEP1_DAC_ID, /* 14 */ | |
248 | ICE_EEP1_DAC_ID1, | |
249 | ICE_EEP1_DAC_ID2, | |
250 | ICE_EEP1_DAC_ID3, | |
251 | ICE_EEP1_ADC_ID, /* 18 */ | |
252 | ICE_EEP1_ADC_ID1, | |
253 | ICE_EEP1_ADC_ID2, | |
254 | ICE_EEP1_ADC_ID3 | |
255 | }; | |
256 | ||
257 | #define ice_has_con_ac97(ice) (!((ice)->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97)) | |
258 | ||
259 | ||
260 | struct snd_ak4xxx_private { | |
261 | unsigned int cif: 1; /* CIF mode */ | |
262 | unsigned char caddr; /* C0 and C1 bits */ | |
263 | unsigned int data_mask; /* DATA gpio bit */ | |
264 | unsigned int clk_mask; /* CLK gpio bit */ | |
265 | unsigned int cs_mask; /* bit mask for select/deselect address */ | |
266 | unsigned int cs_addr; /* bits to select address */ | |
267 | unsigned int cs_none; /* bits to deselect address */ | |
268 | unsigned int add_flags; /* additional bits at init */ | |
269 | unsigned int mask_flags; /* total mask bits */ | |
270 | struct snd_akm4xxx_ops { | |
6ca308d4 | 271 | void (*set_rate_val)(struct snd_akm4xxx *ak, unsigned int rate); |
1da177e4 LT |
272 | } ops; |
273 | }; | |
274 | ||
275 | struct snd_ice1712_spdif { | |
276 | unsigned char cs8403_bits; | |
277 | unsigned char cs8403_stream_bits; | |
6ca308d4 | 278 | struct snd_kcontrol *stream_ctl; |
1da177e4 LT |
279 | |
280 | struct snd_ice1712_spdif_ops { | |
6ca308d4 TI |
281 | void (*open)(struct snd_ice1712 *, struct snd_pcm_substream *); |
282 | void (*setup_rate)(struct snd_ice1712 *, int rate); | |
283 | void (*close)(struct snd_ice1712 *, struct snd_pcm_substream *); | |
284 | void (*default_get)(struct snd_ice1712 *, struct snd_ctl_elem_value *ucontrol); | |
285 | int (*default_put)(struct snd_ice1712 *, struct snd_ctl_elem_value *ucontrol); | |
286 | void (*stream_get)(struct snd_ice1712 *, struct snd_ctl_elem_value *ucontrol); | |
287 | int (*stream_put)(struct snd_ice1712 *, struct snd_ctl_elem_value *ucontrol); | |
1da177e4 LT |
288 | } ops; |
289 | }; | |
290 | ||
291 | ||
6ca308d4 | 292 | struct snd_ice1712 { |
1da177e4 LT |
293 | unsigned long conp_dma_size; |
294 | unsigned long conc_dma_size; | |
295 | unsigned long prop_dma_size; | |
296 | unsigned long proc_dma_size; | |
297 | int irq; | |
298 | ||
299 | unsigned long port; | |
300 | unsigned long ddma_port; | |
301 | unsigned long dmapath_port; | |
302 | unsigned long profi_port; | |
303 | ||
304 | struct pci_dev *pci; | |
6ca308d4 TI |
305 | struct snd_card *card; |
306 | struct snd_pcm *pcm; | |
307 | struct snd_pcm *pcm_ds; | |
308 | struct snd_pcm *pcm_pro; | |
309 | struct snd_pcm_substream *playback_con_substream; | |
310 | struct snd_pcm_substream *playback_con_substream_ds[6]; | |
311 | struct snd_pcm_substream *capture_con_substream; | |
312 | struct snd_pcm_substream *playback_pro_substream; | |
313 | struct snd_pcm_substream *capture_pro_substream; | |
1da177e4 LT |
314 | unsigned int playback_pro_size; |
315 | unsigned int capture_pro_size; | |
316 | unsigned int playback_con_virt_addr[6]; | |
317 | unsigned int playback_con_active_buf[6]; | |
318 | unsigned int capture_con_virt_addr; | |
319 | unsigned int ac97_ext_id; | |
6ca308d4 TI |
320 | struct snd_ac97 *ac97; |
321 | struct snd_rawmidi *rmidi[2]; | |
1da177e4 LT |
322 | |
323 | spinlock_t reg_lock; | |
6ca308d4 | 324 | struct snd_info_entry *proc_entry; |
1da177e4 | 325 | |
6ca308d4 | 326 | struct snd_ice1712_eeprom eeprom; |
1da177e4 LT |
327 | |
328 | unsigned int pro_volumes[20]; | |
329 | unsigned int omni: 1; /* Delta Omni I/O */ | |
531af462 | 330 | unsigned int dxr_enable: 1; /* Terratec DXR enable for DMX6FIRE */ |
1da177e4 LT |
331 | unsigned int vt1724: 1; |
332 | unsigned int vt1720: 1; | |
333 | unsigned int has_spdif: 1; /* VT1720/4 - has SPDIF I/O */ | |
334 | unsigned int force_pdma4: 1; /* VT1720/4 - PDMA4 as non-spdif */ | |
335 | unsigned int force_rdma1: 1; /* VT1720/4 - RDMA1 as non-spdif */ | |
336 | unsigned int num_total_dacs; /* total DACs */ | |
337 | unsigned int num_total_adcs; /* total ADCs */ | |
338 | unsigned int cur_rate; /* current rate */ | |
339 | ||
62932df8 | 340 | struct mutex open_mutex; |
6ca308d4 TI |
341 | struct snd_pcm_substream *pcm_reserved[4]; |
342 | struct snd_pcm_hw_constraint_list *hw_rates; /* card-specific rate constraints */ | |
1da177e4 LT |
343 | |
344 | unsigned int akm_codecs; | |
6ca308d4 | 345 | struct snd_akm4xxx *akm; |
1da177e4 LT |
346 | struct snd_ice1712_spdif spdif; |
347 | ||
62932df8 | 348 | struct mutex i2c_mutex; /* I2C mutex for ICE1724 registers */ |
6ca308d4 TI |
349 | struct snd_i2c_bus *i2c; /* I2C bus */ |
350 | struct snd_i2c_device *cs8427; /* CS8427 I2C device */ | |
1da177e4 LT |
351 | unsigned int cs8427_timeout; /* CS8427 reset timeout in HZ/100 */ |
352 | ||
353 | struct ice1712_gpio { | |
354 | unsigned int direction; /* current direction bits */ | |
355 | unsigned int write_mask; /* current mask bits */ | |
356 | unsigned int saved[2]; /* for ewx_i2c */ | |
357 | /* operators */ | |
6ca308d4 TI |
358 | void (*set_mask)(struct snd_ice1712 *ice, unsigned int data); |
359 | void (*set_dir)(struct snd_ice1712 *ice, unsigned int data); | |
360 | void (*set_data)(struct snd_ice1712 *ice, unsigned int data); | |
361 | unsigned int (*get_data)(struct snd_ice1712 *ice); | |
1da177e4 | 362 | /* misc operators - move to another place? */ |
6ca308d4 TI |
363 | void (*set_pro_rate)(struct snd_ice1712 *ice, unsigned int rate); |
364 | void (*i2s_mclk_changed)(struct snd_ice1712 *ice); | |
1da177e4 | 365 | } gpio; |
62932df8 | 366 | struct mutex gpio_mutex; |
1da177e4 LT |
367 | |
368 | /* other board-specific data */ | |
7cda8ba9 | 369 | void *spec; |
d16be8ed PH |
370 | |
371 | /* VT172x specific */ | |
372 | int pro_rate_default; | |
373 | int (*is_spdif_master)(struct snd_ice1712 *ice); | |
374 | unsigned int (*get_rate)(struct snd_ice1712 *ice); | |
375 | void (*set_rate)(struct snd_ice1712 *ice, unsigned int rate); | |
376 | unsigned char (*set_mclk)(struct snd_ice1712 *ice, unsigned int rate); | |
377 | void (*set_spdif_clock)(struct snd_ice1712 *ice); | |
378 | ||
1da177e4 LT |
379 | }; |
380 | ||
381 | ||
382 | /* | |
383 | * gpio access functions | |
384 | */ | |
6ca308d4 | 385 | static inline void snd_ice1712_gpio_set_dir(struct snd_ice1712 *ice, unsigned int bits) |
1da177e4 LT |
386 | { |
387 | ice->gpio.set_dir(ice, bits); | |
388 | } | |
389 | ||
6ca308d4 | 390 | static inline void snd_ice1712_gpio_set_mask(struct snd_ice1712 *ice, unsigned int bits) |
1da177e4 LT |
391 | { |
392 | ice->gpio.set_mask(ice, bits); | |
393 | } | |
394 | ||
6ca308d4 | 395 | static inline void snd_ice1712_gpio_write(struct snd_ice1712 *ice, unsigned int val) |
1da177e4 LT |
396 | { |
397 | ice->gpio.set_data(ice, val); | |
398 | } | |
399 | ||
6ca308d4 | 400 | static inline unsigned int snd_ice1712_gpio_read(struct snd_ice1712 *ice) |
1da177e4 LT |
401 | { |
402 | return ice->gpio.get_data(ice); | |
403 | } | |
404 | ||
405 | /* | |
406 | * save and restore gpio status | |
407 | * The access to gpio will be protected by mutex, so don't forget to | |
408 | * restore! | |
409 | */ | |
6ca308d4 | 410 | static inline void snd_ice1712_save_gpio_status(struct snd_ice1712 *ice) |
1da177e4 | 411 | { |
62932df8 | 412 | mutex_lock(&ice->gpio_mutex); |
1da177e4 LT |
413 | ice->gpio.saved[0] = ice->gpio.direction; |
414 | ice->gpio.saved[1] = ice->gpio.write_mask; | |
415 | } | |
416 | ||
6ca308d4 | 417 | static inline void snd_ice1712_restore_gpio_status(struct snd_ice1712 *ice) |
1da177e4 LT |
418 | { |
419 | ice->gpio.set_dir(ice, ice->gpio.saved[0]); | |
420 | ice->gpio.set_mask(ice, ice->gpio.saved[1]); | |
421 | ice->gpio.direction = ice->gpio.saved[0]; | |
422 | ice->gpio.write_mask = ice->gpio.saved[1]; | |
62932df8 | 423 | mutex_unlock(&ice->gpio_mutex); |
1da177e4 LT |
424 | } |
425 | ||
426 | /* for bit controls */ | |
427 | #define ICE1712_GPIO(xiface, xname, xindex, mask, invert, xaccess) \ | |
00283886 | 428 | { .iface = xiface, .name = xname, .access = xaccess, .info = snd_ctl_boolean_mono_info, \ |
1da177e4 LT |
429 | .get = snd_ice1712_gpio_get, .put = snd_ice1712_gpio_put, \ |
430 | .private_value = mask | (invert << 24) } | |
431 | ||
6ca308d4 TI |
432 | int snd_ice1712_gpio_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); |
433 | int snd_ice1712_gpio_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); | |
1da177e4 LT |
434 | |
435 | /* | |
436 | * set gpio direction, write mask and data | |
437 | */ | |
6ca308d4 TI |
438 | static inline void snd_ice1712_gpio_write_bits(struct snd_ice1712 *ice, |
439 | unsigned int mask, unsigned int bits) | |
1da177e4 LT |
440 | { |
441 | ice->gpio.direction |= mask; | |
442 | snd_ice1712_gpio_set_dir(ice, ice->gpio.direction); | |
443 | snd_ice1712_gpio_set_mask(ice, ~mask); | |
444 | snd_ice1712_gpio_write(ice, mask & bits); | |
445 | } | |
446 | ||
feaa6a74 JV |
447 | static inline int snd_ice1712_gpio_read_bits(struct snd_ice1712 *ice, |
448 | unsigned int mask) | |
449 | { | |
450 | ice->gpio.direction &= ~mask; | |
451 | snd_ice1712_gpio_set_dir(ice, ice->gpio.direction); | |
452 | return (snd_ice1712_gpio_read(ice) & mask); | |
453 | } | |
454 | ||
6ca308d4 | 455 | int snd_ice1712_spdif_build_controls(struct snd_ice1712 *ice); |
1da177e4 | 456 | |
6ca308d4 TI |
457 | int snd_ice1712_akm4xxx_init(struct snd_akm4xxx *ak, const struct snd_akm4xxx *template, |
458 | const struct snd_ak4xxx_private *priv, struct snd_ice1712 *ice); | |
459 | void snd_ice1712_akm4xxx_free(struct snd_ice1712 *ice); | |
460 | int snd_ice1712_akm4xxx_build_controls(struct snd_ice1712 *ice); | |
1da177e4 | 461 | |
6ca308d4 | 462 | int snd_ice1712_init_cs8427(struct snd_ice1712 *ice, int addr); |
1da177e4 | 463 | |
6ca308d4 | 464 | static inline void snd_ice1712_write(struct snd_ice1712 * ice, u8 addr, u8 data) |
1da177e4 LT |
465 | { |
466 | outb(addr, ICEREG(ice, INDEX)); | |
467 | outb(data, ICEREG(ice, DATA)); | |
468 | } | |
469 | ||
6ca308d4 | 470 | static inline u8 snd_ice1712_read(struct snd_ice1712 * ice, u8 addr) |
1da177e4 LT |
471 | { |
472 | outb(addr, ICEREG(ice, INDEX)); | |
473 | return inb(ICEREG(ice, DATA)); | |
474 | } | |
475 | ||
476 | ||
477 | /* | |
478 | * entry pointer | |
479 | */ | |
480 | ||
481 | struct snd_ice1712_card_info { | |
482 | unsigned int subvendor; | |
483 | char *name; | |
484 | char *model; | |
485 | char *driver; | |
6ca308d4 TI |
486 | int (*chip_init)(struct snd_ice1712 *); |
487 | int (*build_controls)(struct snd_ice1712 *); | |
1da177e4 | 488 | unsigned int no_mpu401: 1; |
cf78ee2c AH |
489 | unsigned int mpu401_1_info_flags; |
490 | unsigned int mpu401_2_info_flags; | |
3bef229e AH |
491 | const char *mpu401_1_name; |
492 | const char *mpu401_2_name; | |
32b47da0 TI |
493 | const unsigned int eeprom_size; |
494 | const unsigned char *eeprom_data; | |
1da177e4 LT |
495 | }; |
496 | ||
497 | ||
498 | #endif /* __SOUND_ICE1712_H */ |