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ALSA: ice1724 - Support for multiple external clock types
[deliverable/linux.git] / sound / pci / ice1712 / ice1724.c
CommitLineData
1da177e4
LT		 1/*
2 * ALSA driver for VT1724 ICEnsemble ICE1724 / VIA VT1724 (Envy24HT)
3 * VIA VT1720 (Envy24PT)
4 *
c1017a4c 5 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
1da177e4
LT		 6 * 2002 James Stafford <jstafford@ampltd.com>
7 * 2003 Takashi Iwai <tiwai@suse.de>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
1de9fdc2 23 */
1da177e4 24
1de9fdc2 25#include <linux/io.h>
1da177e4
LT		 26#include <linux/delay.h>
27#include <linux/interrupt.h>
28#include <linux/init.h>
29#include <linux/pci.h>
30#include <linux/slab.h>
31#include <linux/moduleparam.h>
62932df8 32#include <linux/mutex.h>
1da177e4
LT		 33#include <sound/core.h>
34#include <sound/info.h>
aea3bfbc 35#include <sound/rawmidi.h>
1da177e4
LT		 36#include <sound/initval.h>
37
38#include <sound/asoundef.h>
39
40#include "ice1712.h"
41#include "envy24ht.h"
42
43/* lowlevel routines */
44#include "amp.h"
45#include "revo.h"
46#include "aureon.h"
47#include "vt1720_mobo.h"
48#include "pontis.h"
49#include "prodigy192.h"
6b8d6e55 50#include "prodigy_hifi.h"
1da177e4 51#include "juli.h"
72cbfd45 52#include "maya44.h"
1da177e4 53#include "phase.h"
f6cdab5f 54#include "wtm.h"
f31639b8 55#include "se.h"
1da177e4 56
c1017a4c 57MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
1da177e4
LT		 58MODULE_DESCRIPTION("VIA ICEnsemble ICE1724/1720 (Envy24HT/PT)");
59MODULE_LICENSE("GPL");
60MODULE_SUPPORTED_DEVICE("{"
61 REVO_DEVICE_DESC
62 AMP_AUDIO2000_DEVICE_DESC
63 AUREON_DEVICE_DESC
64 VT1720_MOBO_DEVICE_DESC
65 PONTIS_DEVICE_DESC
66 PRODIGY192_DEVICE_DESC
6b8d6e55 67 PRODIGY_HIFI_DEVICE_DESC
1da177e4 68 JULI_DEVICE_DESC
72cbfd45 69 MAYA44_DEVICE_DESC
1da177e4 70 PHASE_DEVICE_DESC
f6cdab5f 71 WTM_DEVICE_DESC
f31639b8 72 SE_DEVICE_DESC
1da177e4
LT		 73 "{VIA,VT1720},"
74 "{VIA,VT1724},"
75 "{ICEnsemble,Generic ICE1724},"
76 "{ICEnsemble,Generic Envy24HT}"
77 "{ICEnsemble,Generic Envy24PT}}");
78
79static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
80static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
81static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
82static char *model[SNDRV_CARDS];
83
84module_param_array(index, int, NULL, 0444);
85MODULE_PARM_DESC(index, "Index value for ICE1724 soundcard.");
86module_param_array(id, charp, NULL, 0444);
87MODULE_PARM_DESC(id, "ID string for ICE1724 soundcard.");
88module_param_array(enable, bool, NULL, 0444);
89MODULE_PARM_DESC(enable, "Enable ICE1724 soundcard.");
90module_param_array(model, charp, NULL, 0444);
91MODULE_PARM_DESC(model, "Use the given board model.");
92
1da177e4
LT		 93
94/* Both VT1720 and VT1724 have the same PCI IDs */
32b47da0 95static const struct pci_device_id snd_vt1724_ids[] = {
28d27aae 96 { PCI_VDEVICE(ICE, PCI_DEVICE_ID_VT1724), 0 },
1da177e4
LT		 97 { 0, }
98};
99
100MODULE_DEVICE_TABLE(pci, snd_vt1724_ids);
101
102
103static int PRO_RATE_LOCKED;
104static int PRO_RATE_RESET = 1;
105static unsigned int PRO_RATE_DEFAULT = 44100;
106
1ff97cb9
PH		 107static char *ext_clock_names[1] = { "IEC958 In" };
108
1da177e4
LT		 109/*
110 * Basic I/O
111 */
1de9fdc2 112
d16be8ed
PH		 113/*
114 * default rates, default clock routines
115 */
116
1da177e4 117/* check whether the clock mode is spdif-in */
d16be8ed 118static inline int stdclock_is_spdif_master(struct snd_ice1712 *ice)
1da177e4
LT		 119{
120 return (inb(ICEMT1724(ice, RATE)) & VT1724_SPDIF_MASTER) ? 1 : 0;
121}
122
6796d5a0
PH		 123/*
124 * locking rate makes sense only for internal clock mode
125 */
ab0c7d72 126static inline int is_pro_rate_locked(struct snd_ice1712 *ice)
1da177e4 127{
6796d5a0 128 return (!ice->is_spdif_master(ice)) && PRO_RATE_LOCKED;
1da177e4
LT		 129}
130
131/*
132 * ac97 section
133 */
134
ab0c7d72 135static unsigned char snd_vt1724_ac97_ready(struct snd_ice1712 *ice)
1da177e4
LT		 136{
137 unsigned char old_cmd;
138 int tm;
139 for (tm = 0; tm < 0x10000; tm++) {
140 old_cmd = inb(ICEMT1724(ice, AC97_CMD));
141 if (old_cmd & (VT1724_AC97_WRITE | VT1724_AC97_READ))
142 continue;
143 if (!(old_cmd & VT1724_AC97_READY))
144 continue;
145 return old_cmd;
146 }
147 snd_printd(KERN_ERR "snd_vt1724_ac97_ready: timeout\n");
148 return old_cmd;
149}
150
ab0c7d72 151static int snd_vt1724_ac97_wait_bit(struct snd_ice1712 *ice, unsigned char bit)
1da177e4
LT		 152{
153 int tm;
154 for (tm = 0; tm < 0x10000; tm++)
155 if ((inb(ICEMT1724(ice, AC97_CMD)) & bit) == 0)
156 return 0;
157 snd_printd(KERN_ERR "snd_vt1724_ac97_wait_bit: timeout\n");
158 return -EIO;
159}
160
ab0c7d72 161static void snd_vt1724_ac97_write(struct snd_ac97 *ac97,
1da177e4
LT		 162 unsigned short reg,
163 unsigned short val)
164{
ab0c7d72 165 struct snd_ice1712 *ice = ac97->private_data;
1da177e4
LT		 166 unsigned char old_cmd;
167
168 old_cmd = snd_vt1724_ac97_ready(ice);
169 old_cmd &= ~VT1724_AC97_ID_MASK;
170 old_cmd |= ac97->num;
171 outb(reg, ICEMT1724(ice, AC97_INDEX));
172 outw(val, ICEMT1724(ice, AC97_DATA));
173 outb(old_cmd | VT1724_AC97_WRITE, ICEMT1724(ice, AC97_CMD));
174 snd_vt1724_ac97_wait_bit(ice, VT1724_AC97_WRITE);
175}
176
ab0c7d72 177static unsigned short snd_vt1724_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
1da177e4 178{
ab0c7d72 179 struct snd_ice1712 *ice = ac97->private_data;
1da177e4
LT		 180 unsigned char old_cmd;
181
182 old_cmd = snd_vt1724_ac97_ready(ice);
183 old_cmd &= ~VT1724_AC97_ID_MASK;
184 old_cmd |= ac97->num;
185 outb(reg, ICEMT1724(ice, AC97_INDEX));
186 outb(old_cmd | VT1724_AC97_READ, ICEMT1724(ice, AC97_CMD));
187 if (snd_vt1724_ac97_wait_bit(ice, VT1724_AC97_READ) < 0)
188 return ~0;
189 return inw(ICEMT1724(ice, AC97_DATA));
190}
191
192
193/*
194 * GPIO operations
195 */
196
197/* set gpio direction 0 = read, 1 = write */
ab0c7d72 198static void snd_vt1724_set_gpio_dir(struct snd_ice1712 *ice, unsigned int data)
1da177e4
LT		 199{
200 outl(data, ICEREG1724(ice, GPIO_DIRECTION));
201 inw(ICEREG1724(ice, GPIO_DIRECTION)); /* dummy read for pci-posting */
202}
203
49470306
PH		 204/* get gpio direction 0 = read, 1 = write */
205static unsigned int snd_vt1724_get_gpio_dir(struct snd_ice1712 *ice)
206{
207 return inl(ICEREG1724(ice, GPIO_DIRECTION));
208}
209
1da177e4 210/* set the gpio mask (0 = writable) */
ab0c7d72 211static void snd_vt1724_set_gpio_mask(struct snd_ice1712 *ice, unsigned int data)
1da177e4
LT		 212{
213 outw(data, ICEREG1724(ice, GPIO_WRITE_MASK));
1de9fdc2 214 if (!ice->vt1720) /* VT1720 supports only 16 GPIO bits */
1da177e4
LT		 215 outb((data >> 16) & 0xff, ICEREG1724(ice, GPIO_WRITE_MASK_22));
216 inw(ICEREG1724(ice, GPIO_WRITE_MASK)); /* dummy read for pci-posting */
217}
218
49470306
PH		 219static unsigned int snd_vt1724_get_gpio_mask(struct snd_ice1712 *ice)
220{
221 unsigned int mask;
222 if (!ice->vt1720)
223 mask = (unsigned int)inb(ICEREG1724(ice, GPIO_WRITE_MASK_22));
224 else
225 mask = 0;
226 mask = (mask << 16) | inw(ICEREG1724(ice, GPIO_WRITE_MASK));
227 return mask;
228}
229
ab0c7d72 230static void snd_vt1724_set_gpio_data(struct snd_ice1712 *ice, unsigned int data)
1da177e4
LT		 231{
232 outw(data, ICEREG1724(ice, GPIO_DATA));
1de9fdc2 233 if (!ice->vt1720)
1da177e4
LT		 234 outb(data >> 16, ICEREG1724(ice, GPIO_DATA_22));
235 inw(ICEREG1724(ice, GPIO_DATA)); /* dummy read for pci-posting */
236}
237
ab0c7d72 238static unsigned int snd_vt1724_get_gpio_data(struct snd_ice1712 *ice)
1da177e4
LT		 239{
240 unsigned int data;
1de9fdc2 241 if (!ice->vt1720)
1da177e4
LT		 242 data = (unsigned int)inb(ICEREG1724(ice, GPIO_DATA_22));
243 else
244 data = 0;
245 data = (data << 16) | inw(ICEREG1724(ice, GPIO_DATA));
246 return data;
247}
248
3a841d51 249/*
aea3bfbc 250 * MIDI
3a841d51 251 */
aea3bfbc
CL		 252
253static void vt1724_midi_clear_rx(struct snd_ice1712 *ice)
254{
255 unsigned int count;
256
257 for (count = inb(ICEREG1724(ice, MPU_RXFIFO)); count > 0; --count)
258 inb(ICEREG1724(ice, MPU_DATA));
259}
260
261static inline struct snd_rawmidi_substream *
262get_rawmidi_substream(struct snd_ice1712 *ice, unsigned int stream)
3a841d51 263{
aea3bfbc
CL		 264 return list_first_entry(&ice->rmidi[0]->streams[stream].substreams,
265 struct snd_rawmidi_substream, list);
266}
267
e683ec46
TI		 268static void enable_midi_irq(struct snd_ice1712 *ice, u8 flag, int enable);
269
aea3bfbc
CL		 270static void vt1724_midi_write(struct snd_ice1712 *ice)
271{
272 struct snd_rawmidi_substream *s;
273 int count, i;
274 u8 buffer[32];
275
276 s = get_rawmidi_substream(ice, SNDRV_RAWMIDI_STREAM_OUTPUT);
277 count = 31 - inb(ICEREG1724(ice, MPU_TXFIFO));
278 if (count > 0) {
279 count = snd_rawmidi_transmit(s, buffer, count);
280 for (i = 0; i < count; ++i)
281 outb(buffer[i], ICEREG1724(ice, MPU_DATA));
282 }
e683ec46
TI		 283 /* mask irq when all bytes have been transmitted.
284 * enabled again in output_trigger when the new data comes in.
285 */
286 enable_midi_irq(ice, VT1724_IRQ_MPU_TX,
287 !snd_rawmidi_transmit_empty(s));
aea3bfbc
CL		 288}
289
290static void vt1724_midi_read(struct snd_ice1712 *ice)
291{
292 struct snd_rawmidi_substream *s;
293 int count, i;
294 u8 buffer[32];
295
296 s = get_rawmidi_substream(ice, SNDRV_RAWMIDI_STREAM_INPUT);
297 count = inb(ICEREG1724(ice, MPU_RXFIFO));
298 if (count > 0) {
299 count = min(count, 32);
300 for (i = 0; i < count; ++i)
301 buffer[i] = inb(ICEREG1724(ice, MPU_DATA));
302 snd_rawmidi_receive(s, buffer, count);
303 }
304}
305
e683ec46
TI		 306/* call with ice->reg_lock */
307static void enable_midi_irq(struct snd_ice1712 *ice, u8 flag, int enable)
aea3bfbc 308{
e683ec46 309 u8 mask = inb(ICEREG1724(ice, IRQMASK));
aea3bfbc
CL		 310 if (enable)
311 mask &= ~flag;
3a841d51 312 else
aea3bfbc
CL		 313 mask |= flag;
314 outb(mask, ICEREG1724(ice, IRQMASK));
e683ec46
TI		 315}
316
317static void vt1724_enable_midi_irq(struct snd_rawmidi_substream *substream,
318 u8 flag, int enable)
319{
320 struct snd_ice1712 *ice = substream->rmidi->private_data;
321
322 spin_lock_irq(&ice->reg_lock);
323 enable_midi_irq(ice, flag, enable);
aea3bfbc 324 spin_unlock_irq(&ice->reg_lock);
3a841d51
TI		 325}
326
aea3bfbc 327static int vt1724_midi_output_open(struct snd_rawmidi_substream *s)
3a841d51 328{
aea3bfbc
CL		 329 return 0;
330}
331
332static int vt1724_midi_output_close(struct snd_rawmidi_substream *s)
333{
aea3bfbc 334 return 0;
3a841d51
TI		 335}
336
aea3bfbc
CL		 337static void vt1724_midi_output_trigger(struct snd_rawmidi_substream *s, int up)
338{
339 struct snd_ice1712 *ice = s->rmidi->private_data;
340 unsigned long flags;
341
342 spin_lock_irqsave(&ice->reg_lock, flags);
343 if (up) {
344 ice->midi_output = 1;
345 vt1724_midi_write(ice);
346 } else {
347 ice->midi_output = 0;
e683ec46 348 enable_midi_irq(ice, VT1724_IRQ_MPU_TX, 0);
aea3bfbc
CL		 349 }
350 spin_unlock_irqrestore(&ice->reg_lock, flags);
351}
352
353static void vt1724_midi_output_drain(struct snd_rawmidi_substream *s)
354{
355 struct snd_ice1712 *ice = s->rmidi->private_data;
356 unsigned long timeout;
357
e683ec46 358 vt1724_enable_midi_irq(s, VT1724_IRQ_MPU_TX, 0);
aea3bfbc
CL		 359 /* 32 bytes should be transmitted in less than about 12 ms */
360 timeout = jiffies + msecs_to_jiffies(15);
361 do {
362 if (inb(ICEREG1724(ice, MPU_CTRL)) & VT1724_MPU_TX_EMPTY)
363 break;
364 schedule_timeout_uninterruptible(1);
365 } while (time_after(timeout, jiffies));
366}
367
368static struct snd_rawmidi_ops vt1724_midi_output_ops = {
369 .open = vt1724_midi_output_open,
370 .close = vt1724_midi_output_close,
371 .trigger = vt1724_midi_output_trigger,
372 .drain = vt1724_midi_output_drain,
373};
374
375static int vt1724_midi_input_open(struct snd_rawmidi_substream *s)
376{
377 vt1724_midi_clear_rx(s->rmidi->private_data);
378 vt1724_enable_midi_irq(s, VT1724_IRQ_MPU_RX, 1);
379 return 0;
380}
381
382static int vt1724_midi_input_close(struct snd_rawmidi_substream *s)
383{
384 vt1724_enable_midi_irq(s, VT1724_IRQ_MPU_RX, 0);
385 return 0;
386}
387
388static void vt1724_midi_input_trigger(struct snd_rawmidi_substream *s, int up)
389{
390 struct snd_ice1712 *ice = s->rmidi->private_data;
391 unsigned long flags;
392
393 spin_lock_irqsave(&ice->reg_lock, flags);
394 if (up) {
395 ice->midi_input = 1;
396 vt1724_midi_read(ice);
397 } else {
398 ice->midi_input = 0;
399 }
400 spin_unlock_irqrestore(&ice->reg_lock, flags);
401}
402
403static struct snd_rawmidi_ops vt1724_midi_input_ops = {
404 .open = vt1724_midi_input_open,
405 .close = vt1724_midi_input_close,
406 .trigger = vt1724_midi_input_trigger,
407};
408
3a841d51 409
1da177e4
LT		 410/*
411 * Interrupt handler
412 */
413
7d12e780 414static irqreturn_t snd_vt1724_interrupt(int irq, void *dev_id)
1da177e4 415{
ab0c7d72 416 struct snd_ice1712 *ice = dev_id;
1da177e4 417 unsigned char status;
3a841d51
TI		 418 unsigned char status_mask =
419 VT1724_IRQ_MPU_RX | VT1724_IRQ_MPU_TX | VT1724_IRQ_MTPCM;
1da177e4 420 int handled = 0;
3a841d51 421 int timeout = 0;
1da177e4
LT		 422
423 while (1) {
424 status = inb(ICEREG1724(ice, IRQSTAT));
3a841d51 425 status &= status_mask;
1da177e4
LT		 426 if (status == 0)
427 break;
e683ec46 428 spin_lock(&ice->reg_lock);
3a841d51 429 if (++timeout > 10) {
1083206f
TI		 430 status = inb(ICEREG1724(ice, IRQSTAT));
431 printk(KERN_ERR "ice1724: Too long irq loop, "
432 "status = 0x%x\n", status);
433 if (status & VT1724_IRQ_MPU_TX) {
434 printk(KERN_ERR "ice1724: Disabling MPU_TX\n");
e683ec46 435 enable_midi_irq(ice, VT1724_IRQ_MPU_TX, 0);
1083206f 436 }
e683ec46 437 spin_unlock(&ice->reg_lock);
3a841d51
TI		 438 break;
439 }
1de9fdc2 440 handled = 1;
3a841d51 441 if (status & VT1724_IRQ_MPU_TX) {
aea3bfbc
CL		 442 if (ice->midi_output)
443 vt1724_midi_write(ice);
e683ec46
TI		 444 else
445 enable_midi_irq(ice, VT1724_IRQ_MPU_TX, 0);
3a841d51
TI		 446 /* Due to mysterical reasons, MPU_TX is always
447 * generated (and can't be cleared) when a PCM
448 * playback is going. So let's ignore at the
449 * next loop.
450 */
451 status_mask &= ~VT1724_IRQ_MPU_TX;
452 }
453 if (status & VT1724_IRQ_MPU_RX) {
aea3bfbc
CL		 454 if (ice->midi_input)
455 vt1724_midi_read(ice);
456 else
457 vt1724_midi_clear_rx(ice);
1da177e4 458 }
3a841d51
TI		 459 /* ack MPU irq */
460 outb(status, ICEREG1724(ice, IRQSTAT));
e683ec46 461 spin_unlock(&ice->reg_lock);
1da177e4
LT		 462 if (status & VT1724_IRQ_MTPCM) {
463 /*
464 * Multi-track PCM
465 * PCM assignment are:
466 * Playback DMA0 (M/C) = playback_pro_substream
467 * Playback DMA1 = playback_con_substream_ds[0]
468 * Playback DMA2 = playback_con_substream_ds[1]
469 * Playback DMA3 = playback_con_substream_ds[2]
470 * Playback DMA4 (SPDIF) = playback_con_substream
471 * Record DMA0 = capture_pro_substream
472 * Record DMA1 = capture_con_substream
473 */
474 unsigned char mtstat = inb(ICEMT1724(ice, IRQ));
475 if (mtstat & VT1724_MULTI_PDMA0) {
476 if (ice->playback_pro_substream)
477 snd_pcm_period_elapsed(ice->playback_pro_substream);
478 }
479 if (mtstat & VT1724_MULTI_RDMA0) {
480 if (ice->capture_pro_substream)
481 snd_pcm_period_elapsed(ice->capture_pro_substream);
482 }
483 if (mtstat & VT1724_MULTI_PDMA1) {
484 if (ice->playback_con_substream_ds[0])
485 snd_pcm_period_elapsed(ice->playback_con_substream_ds[0]);
486 }
487 if (mtstat & VT1724_MULTI_PDMA2) {
488 if (ice->playback_con_substream_ds[1])
489 snd_pcm_period_elapsed(ice->playback_con_substream_ds[1]);
490 }
491 if (mtstat & VT1724_MULTI_PDMA3) {
492 if (ice->playback_con_substream_ds[2])
493 snd_pcm_period_elapsed(ice->playback_con_substream_ds[2]);
494 }
495 if (mtstat & VT1724_MULTI_PDMA4) {
496 if (ice->playback_con_substream)
497 snd_pcm_period_elapsed(ice->playback_con_substream);
498 }
499 if (mtstat & VT1724_MULTI_RDMA1) {
500 if (ice->capture_con_substream)
501 snd_pcm_period_elapsed(ice->capture_con_substream);
502 }
503 /* ack anyway to avoid freeze */
504 outb(mtstat, ICEMT1724(ice, IRQ));
505 /* ought to really handle this properly */
506 if (mtstat & VT1724_MULTI_FIFO_ERR) {
507 unsigned char fstat = inb(ICEMT1724(ice, DMA_FIFO_ERR));
1de9fdc2
AB		 508 outb(fstat, ICEMT1724(ice, DMA_FIFO_ERR));
509 outb(VT1724_MULTI_FIFO_ERR | inb(ICEMT1724(ice, DMA_INT_MASK)), ICEMT1724(ice, DMA_INT_MASK));
1da177e4
LT		 510 /* If I don't do this, I get machine lockup due to continual interrupts */
511 }
512
513 }
514 }
515 return IRQ_RETVAL(handled);
516}
517
518/*
519 * PCM code - professional part (multitrack)
520 */
521
522static unsigned int rates[] = {
523 8000, 9600, 11025, 12000, 16000, 22050, 24000,
524 32000, 44100, 48000, 64000, 88200, 96000,
525 176400, 192000,
526};
527
ab0c7d72 528static struct snd_pcm_hw_constraint_list hw_constraints_rates_96 = {
1da177e4
LT		 529 .count = ARRAY_SIZE(rates) - 2, /* up to 96000 */
530 .list = rates,
531 .mask = 0,
532};
533
ab0c7d72 534static struct snd_pcm_hw_constraint_list hw_constraints_rates_48 = {
1da177e4
LT		 535 .count = ARRAY_SIZE(rates) - 5, /* up to 48000 */
536 .list = rates,
537 .mask = 0,
538};
539
ab0c7d72 540static struct snd_pcm_hw_constraint_list hw_constraints_rates_192 = {
1da177e4
LT		 541 .count = ARRAY_SIZE(rates),
542 .list = rates,
543 .mask = 0,
544};
545
546struct vt1724_pcm_reg {
547 unsigned int addr; /* ADDR register offset */
548 unsigned int size; /* SIZE register offset */
549 unsigned int count; /* COUNT register offset */
550 unsigned int start; /* start & pause bit */
551};
552
ab0c7d72 553static int snd_vt1724_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4 554{
ab0c7d72 555 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 556 unsigned char what;
557 unsigned char old;
ab0c7d72 558 struct snd_pcm_substream *s;
1da177e4
LT		 559
560 what = 0;
ef991b95 561 snd_pcm_group_for_each_entry(s, substream) {
29998d24
CL		 562 if (snd_pcm_substream_chip(s) == ice) {
563 const struct vt1724_pcm_reg *reg;
564 reg = s->runtime->private_data;
565 what |= reg->start;
566 snd_pcm_trigger_done(s, substream);
567 }
1da177e4
LT		 568 }
569
570 switch (cmd) {
571 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
572 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
573 spin_lock(&ice->reg_lock);
574 old = inb(ICEMT1724(ice, DMA_PAUSE));
575 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
576 old |= what;
577 else
578 old &= ~what;
579 outb(old, ICEMT1724(ice, DMA_PAUSE));
580 spin_unlock(&ice->reg_lock);
581 break;
582
583 case SNDRV_PCM_TRIGGER_START:
584 case SNDRV_PCM_TRIGGER_STOP:
b40e9538 585 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4
LT		 586 spin_lock(&ice->reg_lock);
587 old = inb(ICEMT1724(ice, DMA_CONTROL));
588 if (cmd == SNDRV_PCM_TRIGGER_START)
589 old |= what;
590 else
591 old &= ~what;
592 outb(old, ICEMT1724(ice, DMA_CONTROL));
593 spin_unlock(&ice->reg_lock);
594 break;
595
b40e9538
IC		 596 case SNDRV_PCM_TRIGGER_RESUME:
597 /* apps will have to restart stream */
598 break;
599
1da177e4
LT		 600 default:
601 return -EINVAL;
602 }
603 return 0;
604}
605
606/*
607 */
608
609#define DMA_STARTS (VT1724_RDMA0_START|VT1724_PDMA0_START|VT1724_RDMA1_START|\
610 VT1724_PDMA1_START|VT1724_PDMA2_START|VT1724_PDMA3_START|VT1724_PDMA4_START)
611#define DMA_PAUSES (VT1724_RDMA0_PAUSE|VT1724_PDMA0_PAUSE|VT1724_RDMA1_PAUSE|\
612 VT1724_PDMA1_PAUSE|VT1724_PDMA2_PAUSE|VT1724_PDMA3_PAUSE|VT1724_PDMA4_PAUSE)
613
d16be8ed
PH		 614static const unsigned int stdclock_rate_list[16] = {
615 48000, 24000, 12000, 9600, 32000, 16000, 8000, 96000, 44100,
616 22050, 11025, 88200, 176400, 0, 192000, 64000
617};
618
619static unsigned int stdclock_get_rate(struct snd_ice1712 *ice)
1da177e4 620{
d16be8ed
PH		 621 unsigned int rate;
622 rate = stdclock_rate_list[inb(ICEMT1724(ice, RATE)) & 15];
623 return rate;
624}
625
626static void stdclock_set_rate(struct snd_ice1712 *ice, unsigned int rate)
627{
628 int i;
629 for (i = 0; i < ARRAY_SIZE(stdclock_rate_list); i++) {
630 if (stdclock_rate_list[i] == rate) {
631 outb(i, ICEMT1724(ice, RATE));
632 return;
633 }
634 }
635}
636
637static unsigned char stdclock_set_mclk(struct snd_ice1712 *ice,
638 unsigned int rate)
639{
640 unsigned char val, old;
641 /* check MT02 */
1da177e4 642 if (ice->eeprom.data[ICE_EEP2_ACLINK] & VT1724_CFG_PRO_I2S) {
d16be8ed
PH		 643 val = old = inb(ICEMT1724(ice, I2S_FORMAT));
644 if (rate > 96000)
645 val |= VT1724_MT_I2S_MCLK_128X; /* 128x MCLK */
1da177e4 646 else
d16be8ed
PH		 647 val &= ~VT1724_MT_I2S_MCLK_128X; /* 256x MCLK */
648 if (val != old) {
649 outb(val, ICEMT1724(ice, I2S_FORMAT));
650 /* master clock changed */
651 return 1;
652 }
653 }
654 /* no change in master clock */
655 return 0;
1da177e4
LT		 656}
657
92d71005 658static int snd_vt1724_set_pro_rate(struct snd_ice1712 *ice, unsigned int rate,
ab0c7d72 659 int force)
1da177e4
LT		 660{
661 unsigned long flags;
d16be8ed
PH		 662 unsigned char mclk_change;
663 unsigned int i, old_rate;
1da177e4 664
d16be8ed 665 if (rate > ice->hw_rates->list[ice->hw_rates->count - 1])
92d71005
TI		 666 return -EINVAL;
667
1da177e4 668 spin_lock_irqsave(&ice->reg_lock, flags);
d16be8ed 669 if ((inb(ICEMT1724(ice, DMA_CONTROL)) & DMA_STARTS) ||
1da177e4
LT		 670 (inb(ICEMT1724(ice, DMA_PAUSE)) & DMA_PAUSES)) {
671 /* running? we cannot change the rate now... */
672 spin_unlock_irqrestore(&ice->reg_lock, flags);
92d71005 673 return -EBUSY;
1da177e4
LT		 674 }
675 if (!force && is_pro_rate_locked(ice)) {
6796d5a0
PH		 676 /* comparing required and current rate - makes sense for
677 * internal clock only */
1da177e4 678 spin_unlock_irqrestore(&ice->reg_lock, flags);
92d71005 679 return (rate == ice->cur_rate) ? 0 : -EBUSY;
1da177e4
LT		 680 }
681
6796d5a0
PH		 682 if (force || !ice->is_spdif_master(ice)) {
683 /* force means the rate was switched by ucontrol, otherwise
684 * setting clock rate for internal clock mode */
685 old_rate = ice->get_rate(ice);
686 if (force || (old_rate != rate))
687 ice->set_rate(ice, rate);
688 else if (rate == ice->cur_rate) {
689 spin_unlock_irqrestore(&ice->reg_lock, flags);
690 return 0;
691 }
1da177e4
LT		 692 }
693
694 ice->cur_rate = rate;
695
d16be8ed
PH		 696 /* setting master clock */
697 mclk_change = ice->set_mclk(ice, rate);
698
1da177e4
LT		 699 spin_unlock_irqrestore(&ice->reg_lock, flags);
700
701 if (mclk_change && ice->gpio.i2s_mclk_changed)
702 ice->gpio.i2s_mclk_changed(ice);
703 if (ice->gpio.set_pro_rate)
704 ice->gpio.set_pro_rate(ice, rate);
705
706 /* set up codecs */
707 for (i = 0; i < ice->akm_codecs; i++) {
708 if (ice->akm[i].ops.set_rate_val)
709 ice->akm[i].ops.set_rate_val(&ice->akm[i], rate);
710 }
711 if (ice->spdif.ops.setup_rate)
712 ice->spdif.ops.setup_rate(ice, rate);
92d71005
TI		 713
714 return 0;
1da177e4
LT		 715}
716
ab0c7d72
TI		 717static int snd_vt1724_pcm_hw_params(struct snd_pcm_substream *substream,
718 struct snd_pcm_hw_params *hw_params)
1da177e4 719{
ab0c7d72 720 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
92d71005 721 int i, chs, err;
1da177e4
LT		 722
723 chs = params_channels(hw_params);
62932df8 724 mutex_lock(&ice->open_mutex);
1da177e4
LT		 725 /* mark surround channels */
726 if (substream == ice->playback_pro_substream) {
727 /* PDMA0 can be multi-channel up to 8 */
728 chs = chs / 2 - 1;
729 for (i = 0; i < chs; i++) {
ab0c7d72
TI		 730 if (ice->pcm_reserved[i] &&
731 ice->pcm_reserved[i] != substream) {
62932df8 732 mutex_unlock(&ice->open_mutex);
1da177e4
LT		 733 return -EBUSY;
734 }
735 ice->pcm_reserved[i] = substream;
736 }
737 for (; i < 3; i++) {
738 if (ice->pcm_reserved[i] == substream)
739 ice->pcm_reserved[i] = NULL;
740 }
741 } else {
742 for (i = 0; i < 3; i++) {
743 /* check individual playback stream */
744 if (ice->playback_con_substream_ds[i] == substream) {
ab0c7d72
TI		 745 if (ice->pcm_reserved[i] &&
746 ice->pcm_reserved[i] != substream) {
62932df8 747 mutex_unlock(&ice->open_mutex);
1da177e4
LT		 748 return -EBUSY;
749 }
750 ice->pcm_reserved[i] = substream;
751 break;
752 }
753 }
754 }
62932df8 755 mutex_unlock(&ice->open_mutex);
92d71005
TI		 756
757 err = snd_vt1724_set_pro_rate(ice, params_rate(hw_params), 0);
758 if (err < 0)
759 return err;
760
1da177e4
LT		 761 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
762}
763
ab0c7d72 764static int snd_vt1724_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4 765{
ab0c7d72 766 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 767 int i;
768
62932df8 769 mutex_lock(&ice->open_mutex);
1da177e4
LT		 770 /* unmark surround channels */
771 for (i = 0; i < 3; i++)
772 if (ice->pcm_reserved[i] == substream)
773 ice->pcm_reserved[i] = NULL;
62932df8 774 mutex_unlock(&ice->open_mutex);
1da177e4
LT		 775 return snd_pcm_lib_free_pages(substream);
776}
777
ab0c7d72 778static int snd_vt1724_playback_pro_prepare(struct snd_pcm_substream *substream)
1da177e4 779{
ab0c7d72 780 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 781 unsigned char val;
782 unsigned int size;
783
784 spin_lock_irq(&ice->reg_lock);
785 val = (8 - substream->runtime->channels) >> 1;
786 outb(val, ICEMT1724(ice, BURST));
787
788 outl(substream->runtime->dma_addr, ICEMT1724(ice, PLAYBACK_ADDR));
789
790 size = (snd_pcm_lib_buffer_bytes(substream) >> 2) - 1;
1de9fdc2 791 /* outl(size, ICEMT1724(ice, PLAYBACK_SIZE)); */
1da177e4
LT		 792 outw(size, ICEMT1724(ice, PLAYBACK_SIZE));
793 outb(size >> 16, ICEMT1724(ice, PLAYBACK_SIZE) + 2);
794 size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
1de9fdc2 795 /* outl(size, ICEMT1724(ice, PLAYBACK_COUNT)); */
1da177e4
LT		 796 outw(size, ICEMT1724(ice, PLAYBACK_COUNT));
797 outb(size >> 16, ICEMT1724(ice, PLAYBACK_COUNT) + 2);
798
799 spin_unlock_irq(&ice->reg_lock);
800
e2ea7cfc
TI		 801 /*
802 printk(KERN_DEBUG "pro prepare: ch = %d, addr = 0x%x, "
803 "buffer = 0x%x, period = 0x%x\n",
804 substream->runtime->channels,
805 (unsigned int)substream->runtime->dma_addr,
806 snd_pcm_lib_buffer_bytes(substream),
807 snd_pcm_lib_period_bytes(substream));
808 */
1da177e4
LT		 809 return 0;
810}
811
ab0c7d72 812static snd_pcm_uframes_t snd_vt1724_playback_pro_pointer(struct snd_pcm_substream *substream)
1da177e4 813{
ab0c7d72 814 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 815 size_t ptr;
816
817 if (!(inl(ICEMT1724(ice, DMA_CONTROL)) & VT1724_PDMA0_START))
818 return 0;
819#if 0 /* read PLAYBACK_ADDR */
820 ptr = inl(ICEMT1724(ice, PLAYBACK_ADDR));
821 if (ptr < substream->runtime->dma_addr) {
822 snd_printd("ice1724: invalid negative ptr\n");
823 return 0;
824 }
825 ptr -= substream->runtime->dma_addr;
826 ptr = bytes_to_frames(substream->runtime, ptr);
827 if (ptr >= substream->runtime->buffer_size) {
ab0c7d72
TI		 828 snd_printd("ice1724: invalid ptr %d (size=%d)\n",
829 (int)ptr, (int)substream->runtime->period_size);
1da177e4
LT		 830 return 0;
831 }
832#else /* read PLAYBACK_SIZE */
833 ptr = inl(ICEMT1724(ice, PLAYBACK_SIZE)) & 0xffffff;
834 ptr = (ptr + 1) << 2;
835 ptr = bytes_to_frames(substream->runtime, ptr);
1de9fdc2 836 if (!ptr)
1da177e4
LT		 837 ;
838 else if (ptr <= substream->runtime->buffer_size)
839 ptr = substream->runtime->buffer_size - ptr;
840 else {
ab0c7d72
TI		 841 snd_printd("ice1724: invalid ptr %d (size=%d)\n",
842 (int)ptr, (int)substream->runtime->buffer_size);
1da177e4
LT		 843 ptr = 0;
844 }
845#endif
846 return ptr;
847}
848
ab0c7d72 849static int snd_vt1724_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4 850{
ab0c7d72 851 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
32b47da0 852 const struct vt1724_pcm_reg *reg = substream->runtime->private_data;
1da177e4
LT		 853
854 spin_lock_irq(&ice->reg_lock);
855 outl(substream->runtime->dma_addr, ice->profi_port + reg->addr);
ab0c7d72
TI		 856 outw((snd_pcm_lib_buffer_bytes(substream) >> 2) - 1,
857 ice->profi_port + reg->size);
858 outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1,
859 ice->profi_port + reg->count);
1da177e4
LT		 860 spin_unlock_irq(&ice->reg_lock);
861 return 0;
862}
863
ab0c7d72 864static snd_pcm_uframes_t snd_vt1724_pcm_pointer(struct snd_pcm_substream *substream)
1da177e4 865{
ab0c7d72 866 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
32b47da0 867 const struct vt1724_pcm_reg *reg = substream->runtime->private_data;
1da177e4
LT		 868 size_t ptr;
869
870 if (!(inl(ICEMT1724(ice, DMA_CONTROL)) & reg->start))
871 return 0;
872#if 0 /* use ADDR register */
873 ptr = inl(ice->profi_port + reg->addr);
874 ptr -= substream->runtime->dma_addr;
875 return bytes_to_frames(substream->runtime, ptr);
876#else /* use SIZE register */
877 ptr = inw(ice->profi_port + reg->size);
878 ptr = (ptr + 1) << 2;
879 ptr = bytes_to_frames(substream->runtime, ptr);
1de9fdc2 880 if (!ptr)
1da177e4
LT		 881 ;
882 else if (ptr <= substream->runtime->buffer_size)
883 ptr = substream->runtime->buffer_size - ptr;
884 else {
ab0c7d72
TI		 885 snd_printd("ice1724: invalid ptr %d (size=%d)\n",
886 (int)ptr, (int)substream->runtime->buffer_size);
1da177e4
LT		 887 ptr = 0;
888 }
889 return ptr;
890#endif
891}
892
a5b7b5c1 893static const struct vt1724_pcm_reg vt1724_pdma0_reg = {
1da177e4
LT		 894 .addr = VT1724_MT_PLAYBACK_ADDR,
895 .size = VT1724_MT_PLAYBACK_SIZE,
896 .count = VT1724_MT_PLAYBACK_COUNT,
897 .start = VT1724_PDMA0_START,
898};
899
a5b7b5c1
TI		 900static const struct vt1724_pcm_reg vt1724_pdma4_reg = {
901 .addr = VT1724_MT_PDMA4_ADDR,
902 .size = VT1724_MT_PDMA4_SIZE,
903 .count = VT1724_MT_PDMA4_COUNT,
904 .start = VT1724_PDMA4_START,
905};
906
907static const struct vt1724_pcm_reg vt1724_rdma0_reg = {
1da177e4
LT		 908 .addr = VT1724_MT_CAPTURE_ADDR,
909 .size = VT1724_MT_CAPTURE_SIZE,
910 .count = VT1724_MT_CAPTURE_COUNT,
911 .start = VT1724_RDMA0_START,
912};
913
a5b7b5c1
TI		 914static const struct vt1724_pcm_reg vt1724_rdma1_reg = {
915 .addr = VT1724_MT_RDMA1_ADDR,
916 .size = VT1724_MT_RDMA1_SIZE,
917 .count = VT1724_MT_RDMA1_COUNT,
918 .start = VT1724_RDMA1_START,
919};
920
921#define vt1724_playback_pro_reg vt1724_pdma0_reg
922#define vt1724_playback_spdif_reg vt1724_pdma4_reg
923#define vt1724_capture_pro_reg vt1724_rdma0_reg
924#define vt1724_capture_spdif_reg vt1724_rdma1_reg
925
1de9fdc2 926static const struct snd_pcm_hardware snd_vt1724_playback_pro = {
1da177e4
LT		 927 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
928 SNDRV_PCM_INFO_BLOCK_TRANSFER |
929 SNDRV_PCM_INFO_MMAP_VALID |
930 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
931 .formats = SNDRV_PCM_FMTBIT_S32_LE,
932 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_192000,
933 .rate_min = 8000,
934 .rate_max = 192000,
935 .channels_min = 2,
936 .channels_max = 8,
937 .buffer_bytes_max = (1UL << 21), /* 19bits dword */
938 .period_bytes_min = 8 * 4 * 2, /* FIXME: constraints needed */
939 .period_bytes_max = (1UL << 21),
940 .periods_min = 2,
941 .periods_max = 1024,
942};
943
1de9fdc2 944static const struct snd_pcm_hardware snd_vt1724_spdif = {
1da177e4
LT		 945 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
946 SNDRV_PCM_INFO_BLOCK_TRANSFER |
947 SNDRV_PCM_INFO_MMAP_VALID |
948 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
949 .formats = SNDRV_PCM_FMTBIT_S32_LE,
2dfbeca9
TI		 950 .rates = (SNDRV_PCM_RATE_32000|SNDRV_PCM_RATE_44100|
951 SNDRV_PCM_RATE_48000|SNDRV_PCM_RATE_88200|
952 SNDRV_PCM_RATE_96000|SNDRV_PCM_RATE_176400|
953 SNDRV_PCM_RATE_192000),
1da177e4 954 .rate_min = 32000,
2dfbeca9 955 .rate_max = 192000,
1da177e4
LT		 956 .channels_min = 2,
957 .channels_max = 2,
958 .buffer_bytes_max = (1UL << 18), /* 16bits dword */
959 .period_bytes_min = 2 * 4 * 2,
960 .period_bytes_max = (1UL << 18),
961 .periods_min = 2,
962 .periods_max = 1024,
963};
964
1de9fdc2 965static const struct snd_pcm_hardware snd_vt1724_2ch_stereo = {
1da177e4
LT		 966 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
967 SNDRV_PCM_INFO_BLOCK_TRANSFER |
968 SNDRV_PCM_INFO_MMAP_VALID |
969 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
970 .formats = SNDRV_PCM_FMTBIT_S32_LE,
971 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_192000,
972 .rate_min = 8000,
973 .rate_max = 192000,
974 .channels_min = 2,
975 .channels_max = 2,
976 .buffer_bytes_max = (1UL << 18), /* 16bits dword */
977 .period_bytes_min = 2 * 4 * 2,
978 .period_bytes_max = (1UL << 18),
979 .periods_min = 2,
980 .periods_max = 1024,
981};
982
983/*
984 * set rate constraints
985 */
d16be8ed 986static void set_std_hw_rates(struct snd_ice1712 *ice)
1da177e4 987{
1da177e4
LT		 988 if (ice->eeprom.data[ICE_EEP2_ACLINK] & VT1724_CFG_PRO_I2S) {
989 /* I2S */
990 /* VT1720 doesn't support more than 96kHz */
991 if ((ice->eeprom.data[ICE_EEP2_I2S] & 0x08) && !ice->vt1720)
d16be8ed
PH		 992 ice->hw_rates = &hw_constraints_rates_192;
993 else
994 ice->hw_rates = &hw_constraints_rates_96;
995 } else {
1da177e4 996 /* ACLINK */
d16be8ed 997 ice->hw_rates = &hw_constraints_rates_48;
1da177e4 998 }
d16be8ed
PH		 999}
1000
1001static int set_rate_constraints(struct snd_ice1712 *ice,
1002 struct snd_pcm_substream *substream)
1003{
1004 struct snd_pcm_runtime *runtime = substream->runtime;
1005
1006 runtime->hw.rate_min = ice->hw_rates->list[0];
1007 runtime->hw.rate_max = ice->hw_rates->list[ice->hw_rates->count - 1];
1008 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
1009 return snd_pcm_hw_constraint_list(runtime, 0,
1010 SNDRV_PCM_HW_PARAM_RATE,
1011 ice->hw_rates);
1da177e4
LT		 1012}
1013
1014/* multi-channel playback needs alignment 8x32bit regardless of the channels
1015 * actually used
1016 */
1017#define VT1724_BUFFER_ALIGN 0x20
1018
ab0c7d72 1019static int snd_vt1724_playback_pro_open(struct snd_pcm_substream *substream)
1da177e4 1020{
ab0c7d72
TI		 1021 struct snd_pcm_runtime *runtime = substream->runtime;
1022 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
a6b936b9 1023 int chs, num_indeps;
1da177e4 1024
32b47da0 1025 runtime->private_data = (void *)&vt1724_playback_pro_reg;
1da177e4
LT		 1026 ice->playback_pro_substream = substream;
1027 runtime->hw = snd_vt1724_playback_pro;
1028 snd_pcm_set_sync(substream);
1029 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1030 set_rate_constraints(ice, substream);
62932df8 1031 mutex_lock(&ice->open_mutex);
1da177e4 1032 /* calculate the currently available channels */
a6b936b9
TI		 1033 num_indeps = ice->num_total_dacs / 2 - 1;
1034 for (chs = 0; chs < num_indeps; chs++) {
1da177e4
LT		 1035 if (ice->pcm_reserved[chs])
1036 break;
1037 }
1038 chs = (chs + 1) * 2;
1039 runtime->hw.channels_max = chs;
1040 if (chs > 2) /* channels must be even */
1041 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 2);
62932df8 1042 mutex_unlock(&ice->open_mutex);
1da177e4
LT		 1043 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1044 VT1724_BUFFER_ALIGN);
1045 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1046 VT1724_BUFFER_ALIGN);
1ff97cb9
PH		 1047 if (ice->pro_open)
1048 ice->pro_open(ice, substream);
1da177e4
LT		 1049 return 0;
1050}
1051
ab0c7d72 1052static int snd_vt1724_capture_pro_open(struct snd_pcm_substream *substream)
1da177e4 1053{
ab0c7d72
TI		 1054 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1055 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1056
32b47da0 1057 runtime->private_data = (void *)&vt1724_capture_pro_reg;
1da177e4
LT		 1058 ice->capture_pro_substream = substream;
1059 runtime->hw = snd_vt1724_2ch_stereo;
1060 snd_pcm_set_sync(substream);
1061 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1062 set_rate_constraints(ice, substream);
1063 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1064 VT1724_BUFFER_ALIGN);
1065 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1066 VT1724_BUFFER_ALIGN);
1ff97cb9
PH		 1067 if (ice->pro_open)
1068 ice->pro_open(ice, substream);
1da177e4
LT		 1069 return 0;
1070}
1071
ab0c7d72 1072static int snd_vt1724_playback_pro_close(struct snd_pcm_substream *substream)
1da177e4 1073{
ab0c7d72 1074 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 1075
1076 if (PRO_RATE_RESET)
d16be8ed 1077 snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
1da177e4
LT		 1078 ice->playback_pro_substream = NULL;
1079
1080 return 0;
1081}
1082
ab0c7d72 1083static int snd_vt1724_capture_pro_close(struct snd_pcm_substream *substream)
1da177e4 1084{
ab0c7d72 1085 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 1086
1087 if (PRO_RATE_RESET)
d16be8ed 1088 snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
1da177e4
LT		 1089 ice->capture_pro_substream = NULL;
1090 return 0;
1091}
1092
ab0c7d72 1093static struct snd_pcm_ops snd_vt1724_playback_pro_ops = {
1da177e4
LT		 1094 .open = snd_vt1724_playback_pro_open,
1095 .close = snd_vt1724_playback_pro_close,
1096 .ioctl = snd_pcm_lib_ioctl,
1097 .hw_params = snd_vt1724_pcm_hw_params,
1098 .hw_free = snd_vt1724_pcm_hw_free,
1099 .prepare = snd_vt1724_playback_pro_prepare,
1100 .trigger = snd_vt1724_pcm_trigger,
1101 .pointer = snd_vt1724_playback_pro_pointer,
1102};
1103
ab0c7d72 1104static struct snd_pcm_ops snd_vt1724_capture_pro_ops = {
1da177e4
LT		 1105 .open = snd_vt1724_capture_pro_open,
1106 .close = snd_vt1724_capture_pro_close,
1107 .ioctl = snd_pcm_lib_ioctl,
1108 .hw_params = snd_vt1724_pcm_hw_params,
1109 .hw_free = snd_vt1724_pcm_hw_free,
1110 .prepare = snd_vt1724_pcm_prepare,
1111 .trigger = snd_vt1724_pcm_trigger,
1112 .pointer = snd_vt1724_pcm_pointer,
1113};
1114
1de9fdc2 1115static int __devinit snd_vt1724_pcm_profi(struct snd_ice1712 *ice, int device)
1da177e4 1116{
ab0c7d72 1117 struct snd_pcm *pcm;
1da177e4
LT		 1118 int err;
1119
1120 err = snd_pcm_new(ice->card, "ICE1724", device, 1, 1, &pcm);
1121 if (err < 0)
1122 return err;
1123
1124 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_vt1724_playback_pro_ops);
1125 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_vt1724_capture_pro_ops);
1126
1127 pcm->private_data = ice;
1128 pcm->info_flags = 0;
1129 strcpy(pcm->name, "ICE1724");
1130
1131 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
ab0c7d72
TI		 1132 snd_dma_pci_data(ice->pci),
1133 256*1024, 256*1024);
1da177e4
LT		 1134
1135 ice->pcm_pro = pcm;
1136
1137 return 0;
1138}
1139
1140
1141/*
1142 * SPDIF PCM
1143 */
1144
1da177e4 1145/* update spdif control bits; call with reg_lock */
ab0c7d72 1146static void update_spdif_bits(struct snd_ice1712 *ice, unsigned int val)
1da177e4
LT		 1147{
1148 unsigned char cbit, disabled;
1149
1150 cbit = inb(ICEREG1724(ice, SPDIF_CFG));
1151 disabled = cbit & ~VT1724_CFG_SPDIF_OUT_EN;
1152 if (cbit != disabled)
1153 outb(disabled, ICEREG1724(ice, SPDIF_CFG));
1154 outw(val, ICEMT1724(ice, SPDIF_CTRL));
1155 if (cbit != disabled)
1156 outb(cbit, ICEREG1724(ice, SPDIF_CFG));
1157 outw(val, ICEMT1724(ice, SPDIF_CTRL));
1158}
1159
1160/* update SPDIF control bits according to the given rate */
ab0c7d72 1161static void update_spdif_rate(struct snd_ice1712 *ice, unsigned int rate)
1da177e4
LT		 1162{
1163 unsigned int val, nval;
1164 unsigned long flags;
1165
1166 spin_lock_irqsave(&ice->reg_lock, flags);
1167 nval = val = inw(ICEMT1724(ice, SPDIF_CTRL));
1168 nval &= ~(7 << 12);
1169 switch (rate) {
1170 case 44100: break;
1171 case 48000: nval |= 2 << 12; break;
1172 case 32000: nval |= 3 << 12; break;
2dfbeca9
TI		 1173 case 88200: nval |= 4 << 12; break;
1174 case 96000: nval |= 5 << 12; break;
1175 case 192000: nval |= 6 << 12; break;
1176 case 176400: nval |= 7 << 12; break;
1da177e4
LT		 1177 }
1178 if (val != nval)
1179 update_spdif_bits(ice, nval);
1180 spin_unlock_irqrestore(&ice->reg_lock, flags);
1181}
1182
ab0c7d72 1183static int snd_vt1724_playback_spdif_prepare(struct snd_pcm_substream *substream)
1da177e4 1184{
ab0c7d72 1185 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1de9fdc2 1186 if (!ice->force_pdma4)
1da177e4
LT		 1187 update_spdif_rate(ice, substream->runtime->rate);
1188 return snd_vt1724_pcm_prepare(substream);
1189}
1190
ab0c7d72 1191static int snd_vt1724_playback_spdif_open(struct snd_pcm_substream *substream)
1da177e4 1192{
ab0c7d72
TI		 1193 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1194 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1195
32b47da0 1196 runtime->private_data = (void *)&vt1724_playback_spdif_reg;
1da177e4
LT		 1197 ice->playback_con_substream = substream;
1198 if (ice->force_pdma4) {
1199 runtime->hw = snd_vt1724_2ch_stereo;
1200 set_rate_constraints(ice, substream);
1201 } else
1202 runtime->hw = snd_vt1724_spdif;
1203 snd_pcm_set_sync(substream);
1204 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1205 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1206 VT1724_BUFFER_ALIGN);
1207 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1208 VT1724_BUFFER_ALIGN);
c93f5a1e
TI		 1209 if (ice->spdif.ops.open)
1210 ice->spdif.ops.open(ice, substream);
1da177e4
LT		 1211 return 0;
1212}
1213
ab0c7d72 1214static int snd_vt1724_playback_spdif_close(struct snd_pcm_substream *substream)
1da177e4 1215{
ab0c7d72 1216 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 1217
1218 if (PRO_RATE_RESET)
d16be8ed 1219 snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
1da177e4 1220 ice->playback_con_substream = NULL;
c93f5a1e
TI		 1221 if (ice->spdif.ops.close)
1222 ice->spdif.ops.close(ice, substream);
1da177e4
LT		 1223
1224 return 0;
1225}
1226
ab0c7d72 1227static int snd_vt1724_capture_spdif_open(struct snd_pcm_substream *substream)
1da177e4 1228{
ab0c7d72
TI		 1229 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1230 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1231
32b47da0 1232 runtime->private_data = (void *)&vt1724_capture_spdif_reg;
1da177e4
LT		 1233 ice->capture_con_substream = substream;
1234 if (ice->force_rdma1) {
1235 runtime->hw = snd_vt1724_2ch_stereo;
1236 set_rate_constraints(ice, substream);
1237 } else
1238 runtime->hw = snd_vt1724_spdif;
1239 snd_pcm_set_sync(substream);
1240 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1241 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1242 VT1724_BUFFER_ALIGN);
1243 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1244 VT1724_BUFFER_ALIGN);
c93f5a1e
TI		 1245 if (ice->spdif.ops.open)
1246 ice->spdif.ops.open(ice, substream);
1da177e4
LT		 1247 return 0;
1248}
1249
ab0c7d72 1250static int snd_vt1724_capture_spdif_close(struct snd_pcm_substream *substream)
1da177e4 1251{
ab0c7d72 1252 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 1253
1254 if (PRO_RATE_RESET)
d16be8ed 1255 snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
1da177e4 1256 ice->capture_con_substream = NULL;
c93f5a1e
TI		 1257 if (ice->spdif.ops.close)
1258 ice->spdif.ops.close(ice, substream);
1da177e4
LT		 1259
1260 return 0;
1261}
1262
ab0c7d72 1263static struct snd_pcm_ops snd_vt1724_playback_spdif_ops = {
1da177e4
LT		 1264 .open = snd_vt1724_playback_spdif_open,
1265 .close = snd_vt1724_playback_spdif_close,
1266 .ioctl = snd_pcm_lib_ioctl,
1267 .hw_params = snd_vt1724_pcm_hw_params,
1268 .hw_free = snd_vt1724_pcm_hw_free,
1269 .prepare = snd_vt1724_playback_spdif_prepare,
1270 .trigger = snd_vt1724_pcm_trigger,
1271 .pointer = snd_vt1724_pcm_pointer,
1272};
1273
ab0c7d72 1274static struct snd_pcm_ops snd_vt1724_capture_spdif_ops = {
1da177e4
LT		 1275 .open = snd_vt1724_capture_spdif_open,
1276 .close = snd_vt1724_capture_spdif_close,
1277 .ioctl = snd_pcm_lib_ioctl,
1278 .hw_params = snd_vt1724_pcm_hw_params,
1279 .hw_free = snd_vt1724_pcm_hw_free,
1280 .prepare = snd_vt1724_pcm_prepare,
1281 .trigger = snd_vt1724_pcm_trigger,
1282 .pointer = snd_vt1724_pcm_pointer,
1283};
1284
1285
1de9fdc2 1286static int __devinit snd_vt1724_pcm_spdif(struct snd_ice1712 *ice, int device)
1da177e4
LT		 1287{
1288 char *name;
ab0c7d72 1289 struct snd_pcm *pcm;
1da177e4
LT		 1290 int play, capt;
1291 int err;
1292
1293 if (ice->force_pdma4 ||
1294 (ice->eeprom.data[ICE_EEP2_SPDIF] & VT1724_CFG_SPDIF_OUT_INT)) {
1295 play = 1;
1296 ice->has_spdif = 1;
1297 } else
1298 play = 0;
1299 if (ice->force_rdma1 ||
1300 (ice->eeprom.data[ICE_EEP2_SPDIF] & VT1724_CFG_SPDIF_IN)) {
1301 capt = 1;
1302 ice->has_spdif = 1;
1303 } else
1304 capt = 0;
1de9fdc2 1305 if (!play && !capt)
1da177e4
LT		 1306 return 0; /* no spdif device */
1307
1308 if (ice->force_pdma4 || ice->force_rdma1)
1309 name = "ICE1724 Secondary";
1310 else
8eca7538 1311 name = "ICE1724 IEC958";
1da177e4
LT		 1312 err = snd_pcm_new(ice->card, name, device, play, capt, &pcm);
1313 if (err < 0)
1314 return err;
1315
1316 if (play)
1317 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1318 &snd_vt1724_playback_spdif_ops);
1319 if (capt)
1320 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
1321 &snd_vt1724_capture_spdif_ops);
1322
1323 pcm->private_data = ice;
1324 pcm->info_flags = 0;
1325 strcpy(pcm->name, name);
1326
1327 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
ab0c7d72
TI		 1328 snd_dma_pci_data(ice->pci),
1329 64*1024, 64*1024);
1da177e4
LT		 1330
1331 ice->pcm = pcm;
1332
1333 return 0;
1334}
1335
1336
1337/*
1338 * independent surround PCMs
1339 */
1340
32b47da0 1341static const struct vt1724_pcm_reg vt1724_playback_dma_regs[3] = {
1da177e4
LT		 1342 {
1343 .addr = VT1724_MT_PDMA1_ADDR,
1344 .size = VT1724_MT_PDMA1_SIZE,
1345 .count = VT1724_MT_PDMA1_COUNT,
1346 .start = VT1724_PDMA1_START,
1347 },
1348 {
1349 .addr = VT1724_MT_PDMA2_ADDR,
1350 .size = VT1724_MT_PDMA2_SIZE,
1351 .count = VT1724_MT_PDMA2_COUNT,
1352 .start = VT1724_PDMA2_START,
1353 },
1354 {
1355 .addr = VT1724_MT_PDMA3_ADDR,
1356 .size = VT1724_MT_PDMA3_SIZE,
1357 .count = VT1724_MT_PDMA3_COUNT,
1358 .start = VT1724_PDMA3_START,
1359 },
1360};
1361
ab0c7d72 1362static int snd_vt1724_playback_indep_prepare(struct snd_pcm_substream *substream)
1da177e4 1363{
ab0c7d72 1364 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 1365 unsigned char val;
1366
1367 spin_lock_irq(&ice->reg_lock);
1368 val = 3 - substream->number;
1369 if (inb(ICEMT1724(ice, BURST)) < val)
1370 outb(val, ICEMT1724(ice, BURST));
1371 spin_unlock_irq(&ice->reg_lock);
1372 return snd_vt1724_pcm_prepare(substream);
1373}
1374
ab0c7d72 1375static int snd_vt1724_playback_indep_open(struct snd_pcm_substream *substream)
1da177e4 1376{
ab0c7d72
TI		 1377 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1378 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1379
62932df8 1380 mutex_lock(&ice->open_mutex);
1da177e4
LT		 1381 /* already used by PDMA0? */
1382 if (ice->pcm_reserved[substream->number]) {
62932df8 1383 mutex_unlock(&ice->open_mutex);
1da177e4
LT		 1384 return -EBUSY; /* FIXME: should handle blocking mode properly */
1385 }
62932df8 1386 mutex_unlock(&ice->open_mutex);
32b47da0 1387 runtime->private_data = (void *)&vt1724_playback_dma_regs[substream->number];
1da177e4
LT		 1388 ice->playback_con_substream_ds[substream->number] = substream;
1389 runtime->hw = snd_vt1724_2ch_stereo;
1390 snd_pcm_set_sync(substream);
1391 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1392 set_rate_constraints(ice, substream);
1393 return 0;
1394}
1395
ab0c7d72 1396static int snd_vt1724_playback_indep_close(struct snd_pcm_substream *substream)
1da177e4 1397{
ab0c7d72 1398 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 1399
1400 if (PRO_RATE_RESET)
d16be8ed 1401 snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
1da177e4
LT		 1402 ice->playback_con_substream_ds[substream->number] = NULL;
1403 ice->pcm_reserved[substream->number] = NULL;
1404
1405 return 0;
1406}
1407
ab0c7d72 1408static struct snd_pcm_ops snd_vt1724_playback_indep_ops = {
1da177e4
LT		 1409 .open = snd_vt1724_playback_indep_open,
1410 .close = snd_vt1724_playback_indep_close,
1411 .ioctl = snd_pcm_lib_ioctl,
1412 .hw_params = snd_vt1724_pcm_hw_params,
1413 .hw_free = snd_vt1724_pcm_hw_free,
1414 .prepare = snd_vt1724_playback_indep_prepare,
1415 .trigger = snd_vt1724_pcm_trigger,
1416 .pointer = snd_vt1724_pcm_pointer,
1417};
1418
1419
1de9fdc2 1420static int __devinit snd_vt1724_pcm_indep(struct snd_ice1712 *ice, int device)
1da177e4 1421{
ab0c7d72 1422 struct snd_pcm *pcm;
1da177e4
LT		 1423 int play;
1424 int err;
1425
1426 play = ice->num_total_dacs / 2 - 1;
1427 if (play <= 0)
1428 return 0;
1429
1430 err = snd_pcm_new(ice->card, "ICE1724 Surrounds", device, play, 0, &pcm);
1431 if (err < 0)
1432 return err;
1433
1434 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1435 &snd_vt1724_playback_indep_ops);
1436
1437 pcm->private_data = ice;
1438 pcm->info_flags = 0;
1439 strcpy(pcm->name, "ICE1724 Surround PCM");
1440
1441 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
ab0c7d72
TI		 1442 snd_dma_pci_data(ice->pci),
1443 64*1024, 64*1024);
1da177e4
LT		 1444
1445 ice->pcm_ds = pcm;
1446
1447 return 0;
1448}
1449
1450
1451/*
1452 * Mixer section
1453 */
1454
1de9fdc2 1455static int __devinit snd_vt1724_ac97_mixer(struct snd_ice1712 *ice)
1da177e4
LT		 1456{
1457 int err;
1458
1de9fdc2 1459 if (!(ice->eeprom.data[ICE_EEP2_ACLINK] & VT1724_CFG_PRO_I2S)) {
ab0c7d72
TI		 1460 struct snd_ac97_bus *pbus;
1461 struct snd_ac97_template ac97;
1462 static struct snd_ac97_bus_ops ops = {
1da177e4
LT		 1463 .write = snd_vt1724_ac97_write,
1464 .read = snd_vt1724_ac97_read,
1465 };
1466
1467 /* cold reset */
1468 outb(inb(ICEMT1724(ice, AC97_CMD)) | 0x80, ICEMT1724(ice, AC97_CMD));
1469 mdelay(5); /* FIXME */
1470 outb(inb(ICEMT1724(ice, AC97_CMD)) & ~0x80, ICEMT1724(ice, AC97_CMD));
1471
1de9fdc2
AB		 1472 err = snd_ac97_bus(ice->card, 0, &ops, NULL, &pbus);
1473 if (err < 0)
1da177e4
LT		 1474 return err;
1475 memset(&ac97, 0, sizeof(ac97));
1476 ac97.private_data = ice;
1de9fdc2
AB		 1477 err = snd_ac97_mixer(pbus, &ac97, &ice->ac97);
1478 if (err < 0)
1da177e4
LT		 1479 printk(KERN_WARNING "ice1712: cannot initialize pro ac97, skipped\n");
1480 else
1481 return 0;
1482 }
1483 /* I2S mixer only */
1484 strcat(ice->card->mixername, "ICE1724 - multitrack");
1485 return 0;
1486}
1487
1488/*
1489 *
1490 */
1491
ab0c7d72 1492static inline unsigned int eeprom_triple(struct snd_ice1712 *ice, int idx)
1da177e4
LT		 1493{
1494 return (unsigned int)ice->eeprom.data[idx] | \
1495 ((unsigned int)ice->eeprom.data[idx + 1] << 8) | \
1496 ((unsigned int)ice->eeprom.data[idx + 2] << 16);
1497}
1498
1de9fdc2 1499static void snd_vt1724_proc_read(struct snd_info_entry *entry,
ab0c7d72 1500 struct snd_info_buffer *buffer)
1da177e4 1501{
ab0c7d72 1502 struct snd_ice1712 *ice = entry->private_data;
1da177e4
LT		 1503 unsigned int idx;
1504
1505 snd_iprintf(buffer, "%s\n\n", ice->card->longname);
1506 snd_iprintf(buffer, "EEPROM:\n");
1507
1508 snd_iprintf(buffer, " Subvendor : 0x%x\n", ice->eeprom.subvendor);
1509 snd_iprintf(buffer, " Size : %i bytes\n", ice->eeprom.size);
1510 snd_iprintf(buffer, " Version : %i\n", ice->eeprom.version);
ab0c7d72
TI		 1511 snd_iprintf(buffer, " System Config : 0x%x\n",
1512 ice->eeprom.data[ICE_EEP2_SYSCONF]);
1513 snd_iprintf(buffer, " ACLink : 0x%x\n",
1514 ice->eeprom.data[ICE_EEP2_ACLINK]);
1515 snd_iprintf(buffer, " I2S : 0x%x\n",
1516 ice->eeprom.data[ICE_EEP2_I2S]);
1517 snd_iprintf(buffer, " S/PDIF : 0x%x\n",
1518 ice->eeprom.data[ICE_EEP2_SPDIF]);
1519 snd_iprintf(buffer, " GPIO direction : 0x%x\n",
1520 ice->eeprom.gpiodir);
1521 snd_iprintf(buffer, " GPIO mask : 0x%x\n",
1522 ice->eeprom.gpiomask);
1523 snd_iprintf(buffer, " GPIO state : 0x%x\n",
1524 ice->eeprom.gpiostate);
1da177e4 1525 for (idx = 0x12; idx < ice->eeprom.size; idx++)
ab0c7d72
TI		 1526 snd_iprintf(buffer, " Extra #%02i : 0x%x\n",
1527 idx, ice->eeprom.data[idx]);
1da177e4
LT		 1528
1529 snd_iprintf(buffer, "\nRegisters:\n");
1530
ab0c7d72
TI		 1531 snd_iprintf(buffer, " PSDOUT03 : 0x%08x\n",
1532 (unsigned)inl(ICEMT1724(ice, ROUTE_PLAYBACK)));
1da177e4 1533 for (idx = 0x0; idx < 0x20 ; idx++)
ab0c7d72
TI		 1534 snd_iprintf(buffer, " CCS%02x : 0x%02x\n",
1535 idx, inb(ice->port+idx));
1da177e4 1536 for (idx = 0x0; idx < 0x30 ; idx++)
ab0c7d72
TI		 1537 snd_iprintf(buffer, " MT%02x : 0x%02x\n",
1538 idx, inb(ice->profi_port+idx));
1da177e4
LT		 1539}
1540
1de9fdc2 1541static void __devinit snd_vt1724_proc_init(struct snd_ice1712 *ice)
1da177e4 1542{
ab0c7d72 1543 struct snd_info_entry *entry;
1da177e4 1544
1de9fdc2 1545 if (!snd_card_proc_new(ice->card, "ice1724", &entry))
bf850204 1546 snd_info_set_text_ops(entry, ice, snd_vt1724_proc_read);
1da177e4
LT		 1547}
1548
1549/*
1550 *
1551 */
1552
ab0c7d72
TI		 1553static int snd_vt1724_eeprom_info(struct snd_kcontrol *kcontrol,
1554 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1555{
1556 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
ab0c7d72 1557 uinfo->count = sizeof(struct snd_ice1712_eeprom);
1da177e4
LT		 1558 return 0;
1559}
1560
ab0c7d72
TI		 1561static int snd_vt1724_eeprom_get(struct snd_kcontrol *kcontrol,
1562 struct snd_ctl_elem_value *ucontrol)
1da177e4 1563{
ab0c7d72 1564 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1de9fdc2 1565
1da177e4
LT		 1566 memcpy(ucontrol->value.bytes.data, &ice->eeprom, sizeof(ice->eeprom));
1567 return 0;
1568}
1569
1b60f6b0 1570static struct snd_kcontrol_new snd_vt1724_eeprom __devinitdata = {
1da177e4
LT		 1571 .iface = SNDRV_CTL_ELEM_IFACE_CARD,
1572 .name = "ICE1724 EEPROM",
1573 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1574 .info = snd_vt1724_eeprom_info,
1575 .get = snd_vt1724_eeprom_get
1576};
1577
1578/*
1579 */
ab0c7d72
TI		 1580static int snd_vt1724_spdif_info(struct snd_kcontrol *kcontrol,
1581 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1582{
1583 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1584 uinfo->count = 1;
1585 return 0;
1586}
1587
ab0c7d72 1588static unsigned int encode_spdif_bits(struct snd_aes_iec958 *diga)
1da177e4 1589{
2dfbeca9 1590 unsigned int val, rbits;
1da177e4
LT		 1591
1592 val = diga->status[0] & 0x03; /* professional, non-audio */
1593 if (val & 0x01) {
1594 /* professional */
ab0c7d72
TI		 1595 if ((diga->status[0] & IEC958_AES0_PRO_EMPHASIS) ==
1596 IEC958_AES0_PRO_EMPHASIS_5015)
1da177e4 1597 val |= 1U << 3;
2dfbeca9
TI		 1598 rbits = (diga->status[4] >> 3) & 0x0f;
1599 if (rbits) {
1600 switch (rbits) {
1601 case 2: val |= 5 << 12; break; /* 96k */
1602 case 3: val |= 6 << 12; break; /* 192k */
1603 case 10: val |= 4 << 12; break; /* 88.2k */
1604 case 11: val |= 7 << 12; break; /* 176.4k */
1605 }
1606 } else {
1607 switch (diga->status[0] & IEC958_AES0_PRO_FS) {
1608 case IEC958_AES0_PRO_FS_44100:
1609 break;
1610 case IEC958_AES0_PRO_FS_32000:
1611 val |= 3U << 12;
1612 break;
1613 default:
1614 val |= 2U << 12;
1615 break;
1616 }
1da177e4
LT		 1617 }
1618 } else {
1619 /* consumer */
1620 val |= diga->status[1] & 0x04; /* copyright */
ab0c7d72
TI		 1621 if ((diga->status[0] & IEC958_AES0_CON_EMPHASIS) ==
1622 IEC958_AES0_CON_EMPHASIS_5015)
1da177e4
LT		 1623 val |= 1U << 3;
1624 val |= (unsigned int)(diga->status[1] & 0x3f) << 4; /* category */
1625 val |= (unsigned int)(diga->status[3] & IEC958_AES3_CON_FS) << 12; /* fs */
1626 }
1627 return val;
1628}
1629
ab0c7d72 1630static void decode_spdif_bits(struct snd_aes_iec958 *diga, unsigned int val)
1da177e4
LT		 1631{
1632 memset(diga->status, 0, sizeof(diga->status));
1633 diga->status[0] = val & 0x03; /* professional, non-audio */
1634 if (val & 0x01) {
1635 /* professional */
1636 if (val & (1U << 3))
1637 diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_5015;
1638 switch ((val >> 12) & 0x7) {
1639 case 0:
1640 break;
1641 case 2:
1642 diga->status[0] |= IEC958_AES0_PRO_FS_32000;
1643 break;
1644 default:
1645 diga->status[0] |= IEC958_AES0_PRO_FS_48000;
1646 break;
1647 }
1648 } else {
1649 /* consumer */
1650 diga->status[0] |= val & (1U << 2); /* copyright */
1651 if (val & (1U << 3))
1652 diga->status[0] |= IEC958_AES0_CON_EMPHASIS_5015;
1653 diga->status[1] |= (val >> 4) & 0x3f; /* category */
1654 diga->status[3] |= (val >> 12) & 0x07; /* fs */
1655 }
1656}
1657
ab0c7d72
TI		 1658static int snd_vt1724_spdif_default_get(struct snd_kcontrol *kcontrol,
1659 struct snd_ctl_elem_value *ucontrol)
1da177e4 1660{
ab0c7d72 1661 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1662 unsigned int val;
1663 val = inw(ICEMT1724(ice, SPDIF_CTRL));
1664 decode_spdif_bits(&ucontrol->value.iec958, val);
1665 return 0;
1666}
1667
ab0c7d72
TI		 1668static int snd_vt1724_spdif_default_put(struct snd_kcontrol *kcontrol,
1669 struct snd_ctl_elem_value *ucontrol)
1da177e4 1670{
ab0c7d72 1671 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1672 unsigned int val, old;
1673
1674 val = encode_spdif_bits(&ucontrol->value.iec958);
1675 spin_lock_irq(&ice->reg_lock);
1676 old = inw(ICEMT1724(ice, SPDIF_CTRL));
1677 if (val != old)
1678 update_spdif_bits(ice, val);
1679 spin_unlock_irq(&ice->reg_lock);
1de9fdc2 1680 return val != old;
1da177e4
LT		 1681}
1682
1b60f6b0 1683static struct snd_kcontrol_new snd_vt1724_spdif_default __devinitdata =
1da177e4
LT		 1684{
1685 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1de9fdc2 1686 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1da177e4
LT		 1687 .info = snd_vt1724_spdif_info,
1688 .get = snd_vt1724_spdif_default_get,
1689 .put = snd_vt1724_spdif_default_put
1690};
1691
ab0c7d72
TI		 1692static int snd_vt1724_spdif_maskc_get(struct snd_kcontrol *kcontrol,
1693 struct snd_ctl_elem_value *ucontrol)
1da177e4
LT		 1694{
1695 ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
1696 IEC958_AES0_PROFESSIONAL |
1697 IEC958_AES0_CON_NOT_COPYRIGHT |
1698 IEC958_AES0_CON_EMPHASIS;
1699 ucontrol->value.iec958.status[1] = IEC958_AES1_CON_ORIGINAL |
1700 IEC958_AES1_CON_CATEGORY;
1701 ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS;
1702 return 0;
1703}
1704
ab0c7d72
TI		 1705static int snd_vt1724_spdif_maskp_get(struct snd_kcontrol *kcontrol,
1706 struct snd_ctl_elem_value *ucontrol)
1da177e4
LT		 1707{
1708 ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
1709 IEC958_AES0_PROFESSIONAL |
1710 IEC958_AES0_PRO_FS |
1711 IEC958_AES0_PRO_EMPHASIS;
1712 return 0;
1713}
1714
1b60f6b0 1715static struct snd_kcontrol_new snd_vt1724_spdif_maskc __devinitdata =
1da177e4
LT		 1716{
1717 .access = SNDRV_CTL_ELEM_ACCESS_READ,
67ed4161 1718 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1de9fdc2 1719 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
1da177e4
LT		 1720 .info = snd_vt1724_spdif_info,
1721 .get = snd_vt1724_spdif_maskc_get,
1722};
1723
1b60f6b0 1724static struct snd_kcontrol_new snd_vt1724_spdif_maskp __devinitdata =
1da177e4
LT		 1725{
1726 .access = SNDRV_CTL_ELEM_ACCESS_READ,
67ed4161 1727 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1de9fdc2 1728 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
1da177e4
LT		 1729 .info = snd_vt1724_spdif_info,
1730 .get = snd_vt1724_spdif_maskp_get,
1731};
1732
a5ce8890 1733#define snd_vt1724_spdif_sw_info snd_ctl_boolean_mono_info
1da177e4 1734
ab0c7d72
TI		 1735static int snd_vt1724_spdif_sw_get(struct snd_kcontrol *kcontrol,
1736 struct snd_ctl_elem_value *ucontrol)
1da177e4 1737{
ab0c7d72
TI		 1738 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1739 ucontrol->value.integer.value[0] = inb(ICEREG1724(ice, SPDIF_CFG)) &
1740 VT1724_CFG_SPDIF_OUT_EN ? 1 : 0;
1da177e4
LT		 1741 return 0;
1742}
1743
ab0c7d72
TI		 1744static int snd_vt1724_spdif_sw_put(struct snd_kcontrol *kcontrol,
1745 struct snd_ctl_elem_value *ucontrol)
1da177e4 1746{
ab0c7d72 1747 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1748 unsigned char old, val;
1749
1750 spin_lock_irq(&ice->reg_lock);
1751 old = val = inb(ICEREG1724(ice, SPDIF_CFG));
1752 val &= ~VT1724_CFG_SPDIF_OUT_EN;
1753 if (ucontrol->value.integer.value[0])
1754 val |= VT1724_CFG_SPDIF_OUT_EN;
1755 if (old != val)
1756 outb(val, ICEREG1724(ice, SPDIF_CFG));
1757 spin_unlock_irq(&ice->reg_lock);
1758 return old != val;
1759}
1760
1b60f6b0 1761static struct snd_kcontrol_new snd_vt1724_spdif_switch __devinitdata =
1da177e4
LT		 1762{
1763 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1764 /* FIXME: the following conflict with IEC958 Playback Route */
1de9fdc2
AB		 1765 /* .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, SWITCH), */
1766 .name = SNDRV_CTL_NAME_IEC958("Output ", NONE, SWITCH),
1da177e4
LT		 1767 .info = snd_vt1724_spdif_sw_info,
1768 .get = snd_vt1724_spdif_sw_get,
1769 .put = snd_vt1724_spdif_sw_put
1770};
1771
1772
1773#if 0 /* NOT USED YET */
1774/*
1775 * GPIO access from extern
1776 */
1777
a5ce8890 1778#define snd_vt1724_gpio_info snd_ctl_boolean_mono_info
1da177e4 1779
ab0c7d72
TI		 1780int snd_vt1724_gpio_get(struct snd_kcontrol *kcontrol,
1781 struct snd_ctl_elem_value *ucontrol)
1da177e4 1782{
ab0c7d72 1783 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1784 int shift = kcontrol->private_value & 0xff;
1785 int invert = (kcontrol->private_value & (1<<24)) ? 1 : 0;
1de9fdc2 1786
1da177e4 1787 snd_ice1712_save_gpio_status(ice);
ab0c7d72
TI		 1788 ucontrol->value.integer.value[0] =
1789 (snd_ice1712_gpio_read(ice) & (1 << shift) ? 1 : 0) ^ invert;
1da177e4
LT		 1790 snd_ice1712_restore_gpio_status(ice);
1791 return 0;
1792}
1793
ab0c7d72
TI		 1794int snd_ice1712_gpio_put(struct snd_kcontrol *kcontrol,
1795 struct snd_ctl_elem_value *ucontrol)
1da177e4 1796{
ab0c7d72 1797 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1798 int shift = kcontrol->private_value & 0xff;
1799 int invert = (kcontrol->private_value & (1<<24)) ? mask : 0;
1800 unsigned int val, nval;
1801
1802 if (kcontrol->private_value & (1 << 31))
1803 return -EPERM;
1804 nval = (ucontrol->value.integer.value[0] ? (1 << shift) : 0) ^ invert;
1805 snd_ice1712_save_gpio_status(ice);
1806 val = snd_ice1712_gpio_read(ice);
1807 nval |= val & ~(1 << shift);
1808 if (val != nval)
1809 snd_ice1712_gpio_write(ice, nval);
1810 snd_ice1712_restore_gpio_status(ice);
1811 return val != nval;
1812}
1813#endif /* NOT USED YET */
1814
1815/*
1816 * rate
1817 */
ab0c7d72
TI		 1818static int snd_vt1724_pro_internal_clock_info(struct snd_kcontrol *kcontrol,
1819 struct snd_ctl_elem_info *uinfo)
1da177e4 1820{
ab0c7d72 1821 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1ff97cb9 1822 int hw_rates_count = ice->hw_rates->count;
1da177e4
LT		 1823 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1824 uinfo->count = 1;
1ff97cb9
PH		 1825
1826 uinfo->value.enumerated.items = hw_rates_count + ice->ext_clock_count;
1827 /* upper limit - keep at top */
1da177e4
LT		 1828 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1829 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1ff97cb9
PH		 1830 if (uinfo->value.enumerated.item >= hw_rates_count)
1831 /* ext_clock items */
1832 strcpy(uinfo->value.enumerated.name,
1833 ice->ext_clock_names[
1834 uinfo->value.enumerated.item - hw_rates_count]);
d16be8ed 1835 else
1ff97cb9 1836 /* int clock items */
d16be8ed
PH		 1837 sprintf(uinfo->value.enumerated.name, "%d",
1838 ice->hw_rates->list[uinfo->value.enumerated.item]);
1da177e4
LT		 1839 return 0;
1840}
1841
ab0c7d72
TI		 1842static int snd_vt1724_pro_internal_clock_get(struct snd_kcontrol *kcontrol,
1843 struct snd_ctl_elem_value *ucontrol)
1da177e4 1844{
ab0c7d72 1845 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
d16be8ed 1846 unsigned int i, rate;
1de9fdc2 1847
1da177e4 1848 spin_lock_irq(&ice->reg_lock);
d16be8ed 1849 if (ice->is_spdif_master(ice)) {
1ff97cb9
PH		 1850 ucontrol->value.enumerated.item[0] = ice->hw_rates->count +
1851 ice->get_spdif_master_type(ice);
1da177e4 1852 } else {
d16be8ed
PH		 1853 rate = ice->get_rate(ice);
1854 ucontrol->value.enumerated.item[0] = 0;
1855 for (i = 0; i < ice->hw_rates->count; i++) {
1856 if (ice->hw_rates->list[i] == rate) {
1857 ucontrol->value.enumerated.item[0] = i;
1858 break;
1859 }
1da177e4 1860 }
1da177e4
LT		 1861 }
1862 spin_unlock_irq(&ice->reg_lock);
1863 return 0;
1864}
1865
1ff97cb9
PH		 1866static int stdclock_get_spdif_master_type(struct snd_ice1712 *ice)
1867{
1868 /* standard external clock - only single type - SPDIF IN */
1869 return 0;
1870}
1871
d16be8ed 1872/* setting clock to external - SPDIF */
1ff97cb9 1873static int stdclock_set_spdif_clock(struct snd_ice1712 *ice, int type)
d16be8ed
PH		 1874{
1875 unsigned char oval;
1876 unsigned char i2s_oval;
1877 oval = inb(ICEMT1724(ice, RATE));
1878 outb(oval | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));
1879 /* setting 256fs */
1880 i2s_oval = inb(ICEMT1724(ice, I2S_FORMAT));
1881 outb(i2s_oval & ~VT1724_MT_I2S_MCLK_128X, ICEMT1724(ice, I2S_FORMAT));
1ff97cb9 1882 return 0;
d16be8ed
PH		 1883}
1884
1ff97cb9 1885
ab0c7d72
TI		 1886static int snd_vt1724_pro_internal_clock_put(struct snd_kcontrol *kcontrol,
1887 struct snd_ctl_elem_value *ucontrol)
1da177e4 1888{
ab0c7d72 1889 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
d16be8ed
PH		 1890 unsigned int old_rate, new_rate;
1891 unsigned int item = ucontrol->value.enumerated.item[0];
1ff97cb9 1892 unsigned int first_ext_clock = ice->hw_rates->count;
d16be8ed 1893
1ff97cb9 1894 if (item > first_ext_clock + ice->ext_clock_count - 1)
d16be8ed 1895 return -EINVAL;
1da177e4 1896
1ff97cb9 1897 /* if rate = 0 => external clock */
1da177e4 1898 spin_lock_irq(&ice->reg_lock);
d16be8ed
PH		 1899 if (ice->is_spdif_master(ice))
1900 old_rate = 0;
1901 else
1902 old_rate = ice->get_rate(ice);
1ff97cb9
PH		 1903 if (item >= first_ext_clock) {
1904 /* switching to external clock */
1905 ice->set_spdif_clock(ice, item - first_ext_clock);
d16be8ed 1906 new_rate = 0;
1da177e4 1907 } else {
d16be8ed
PH		 1908 /* internal on-card clock */
1909 new_rate = ice->hw_rates->list[item];
1910 ice->pro_rate_default = new_rate;
1911 spin_unlock_irq(&ice->reg_lock);
1912 snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 1);
1913 spin_lock_irq(&ice->reg_lock);
1da177e4 1914 }
1da177e4
LT		 1915 spin_unlock_irq(&ice->reg_lock);
1916
1ff97cb9 1917 /* the first switch to the ext. clock mode? */
d16be8ed 1918 if (old_rate != new_rate && !new_rate) {
1da177e4 1919 /* notify akm chips as well */
d16be8ed
PH		 1920 unsigned int i;
1921 if (ice->gpio.set_pro_rate)
1922 ice->gpio.set_pro_rate(ice, 0);
1923 for (i = 0; i < ice->akm_codecs; i++) {
1924 if (ice->akm[i].ops.set_rate_val)
1925 ice->akm[i].ops.set_rate_val(&ice->akm[i], 0);
1da177e4
LT		 1926 }
1927 }
d16be8ed 1928 return old_rate != new_rate;
1da177e4
LT		 1929}
1930
1b60f6b0 1931static struct snd_kcontrol_new snd_vt1724_pro_internal_clock __devinitdata = {
1da177e4
LT		 1932 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1933 .name = "Multi Track Internal Clock",
1934 .info = snd_vt1724_pro_internal_clock_info,
1935 .get = snd_vt1724_pro_internal_clock_get,
1936 .put = snd_vt1724_pro_internal_clock_put
1937};
1938
a5ce8890 1939#define snd_vt1724_pro_rate_locking_info snd_ctl_boolean_mono_info
1da177e4 1940
ab0c7d72
TI		 1941static int snd_vt1724_pro_rate_locking_get(struct snd_kcontrol *kcontrol,
1942 struct snd_ctl_elem_value *ucontrol)
1da177e4
LT		 1943{
1944 ucontrol->value.integer.value[0] = PRO_RATE_LOCKED;
1945 return 0;
1946}
1947
ab0c7d72
TI		 1948static int snd_vt1724_pro_rate_locking_put(struct snd_kcontrol *kcontrol,
1949 struct snd_ctl_elem_value *ucontrol)
1da177e4 1950{
ab0c7d72 1951 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1952 int change = 0, nval;
1953
1954 nval = ucontrol->value.integer.value[0] ? 1 : 0;
1955 spin_lock_irq(&ice->reg_lock);
1956 change = PRO_RATE_LOCKED != nval;
1957 PRO_RATE_LOCKED = nval;
1958 spin_unlock_irq(&ice->reg_lock);
1959 return change;
1960}
1961
1b60f6b0 1962static struct snd_kcontrol_new snd_vt1724_pro_rate_locking __devinitdata = {
1da177e4
LT		 1963 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1964 .name = "Multi Track Rate Locking",
1965 .info = snd_vt1724_pro_rate_locking_info,
1966 .get = snd_vt1724_pro_rate_locking_get,
1967 .put = snd_vt1724_pro_rate_locking_put
1968};
1969
a5ce8890 1970#define snd_vt1724_pro_rate_reset_info snd_ctl_boolean_mono_info
1da177e4 1971
ab0c7d72
TI		 1972static int snd_vt1724_pro_rate_reset_get(struct snd_kcontrol *kcontrol,
1973 struct snd_ctl_elem_value *ucontrol)
1da177e4
LT		 1974{
1975 ucontrol->value.integer.value[0] = PRO_RATE_RESET ? 1 : 0;
1976 return 0;
1977}
1978
ab0c7d72
TI		 1979static int snd_vt1724_pro_rate_reset_put(struct snd_kcontrol *kcontrol,
1980 struct snd_ctl_elem_value *ucontrol)
1da177e4 1981{
ab0c7d72 1982 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1983 int change = 0, nval;
1984
1985 nval = ucontrol->value.integer.value[0] ? 1 : 0;
1986 spin_lock_irq(&ice->reg_lock);
1987 change = PRO_RATE_RESET != nval;
1988 PRO_RATE_RESET = nval;
1989 spin_unlock_irq(&ice->reg_lock);
1990 return change;
1991}
1992
1b60f6b0 1993static struct snd_kcontrol_new snd_vt1724_pro_rate_reset __devinitdata = {
1da177e4
LT		 1994 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1995 .name = "Multi Track Rate Reset",
1996 .info = snd_vt1724_pro_rate_reset_info,
1997 .get = snd_vt1724_pro_rate_reset_get,
1998 .put = snd_vt1724_pro_rate_reset_put
1999};
2000
2001
2002/*
2003 * routing
2004 */
ab0c7d72
TI		 2005static int snd_vt1724_pro_route_info(struct snd_kcontrol *kcontrol,
2006 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 2007{
2008 static char *texts[] = {
2009 "PCM Out", /* 0 */
2010 "H/W In 0", "H/W In 1", /* 1-2 */
2011 "IEC958 In L", "IEC958 In R", /* 3-4 */
2012 };
1de9fdc2 2013
1da177e4
LT		 2014 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2015 uinfo->count = 1;
2016 uinfo->value.enumerated.items = 5;
2017 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2018 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2019 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2020 return 0;
2021}
2022
2023static inline int analog_route_shift(int idx)
2024{
2025 return (idx % 2) * 12 + ((idx / 2) * 3) + 8;
2026}
2027
2028static inline int digital_route_shift(int idx)
2029{
2030 return idx * 3;
2031}
2032
2bf864ac 2033int snd_ice1724_get_route_val(struct snd_ice1712 *ice, int shift)
1da177e4
LT		 2034{
2035 unsigned long val;
2036 unsigned char eitem;
32b47da0 2037 static const unsigned char xlate[8] = {
1da177e4
LT		 2038 0, 255, 1, 2, 255, 255, 3, 4,
2039 };
2040
2041 val = inl(ICEMT1724(ice, ROUTE_PLAYBACK));
2042 val >>= shift;
1de9fdc2 2043 val &= 7; /* we now have 3 bits per output */
1da177e4
LT		 2044 eitem = xlate[val];
2045 if (eitem == 255) {
2046 snd_BUG();
2047 return 0;
2048 }
2049 return eitem;
2050}
2051
2bf864ac
TI		 2052int snd_ice1724_put_route_val(struct snd_ice1712 *ice, unsigned int val,
2053 int shift)
1da177e4
LT		 2054{
2055 unsigned int old_val, nval;
2056 int change;
32b47da0 2057 static const unsigned char xroute[8] = {
1da177e4
LT		 2058 0, /* PCM */
2059 2, /* PSDIN0 Left */
2060 3, /* PSDIN0 Right */
2061 6, /* SPDIN Left */
2062 7, /* SPDIN Right */
2063 };
2064
2065 nval = xroute[val % 5];
2066 val = old_val = inl(ICEMT1724(ice, ROUTE_PLAYBACK));
2067 val &= ~(0x07 << shift);
2068 val |= nval << shift;
2069 change = val != old_val;
2070 if (change)
2071 outl(val, ICEMT1724(ice, ROUTE_PLAYBACK));
2072 return change;
2073}
2074
ab0c7d72
TI		 2075static int snd_vt1724_pro_route_analog_get(struct snd_kcontrol *kcontrol,
2076 struct snd_ctl_elem_value *ucontrol)
1da177e4 2077{
ab0c7d72 2078 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4 2079 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
ab0c7d72 2080 ucontrol->value.enumerated.item[0] =
2bf864ac 2081 snd_ice1724_get_route_val(ice, analog_route_shift(idx));
1da177e4
LT		 2082 return 0;
2083}
2084
ab0c7d72
TI		 2085static int snd_vt1724_pro_route_analog_put(struct snd_kcontrol *kcontrol,
2086 struct snd_ctl_elem_value *ucontrol)
1da177e4 2087{
ab0c7d72 2088 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4 2089 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2bf864ac
TI		 2090 return snd_ice1724_put_route_val(ice,
2091 ucontrol->value.enumerated.item[0],
2092 analog_route_shift(idx));
1da177e4
LT		 2093}
2094
ab0c7d72
TI		 2095static int snd_vt1724_pro_route_spdif_get(struct snd_kcontrol *kcontrol,
2096 struct snd_ctl_elem_value *ucontrol)
1da177e4 2097{
ab0c7d72 2098 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4 2099 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
ab0c7d72 2100 ucontrol->value.enumerated.item[0] =
2bf864ac 2101 snd_ice1724_get_route_val(ice, digital_route_shift(idx));
1da177e4
LT		 2102 return 0;
2103}
2104
ab0c7d72
TI		 2105static int snd_vt1724_pro_route_spdif_put(struct snd_kcontrol *kcontrol,
2106 struct snd_ctl_elem_value *ucontrol)
1da177e4 2107{
ab0c7d72 2108 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4 2109 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2bf864ac
TI		 2110 return snd_ice1724_put_route_val(ice,
2111 ucontrol->value.enumerated.item[0],
2112 digital_route_shift(idx));
1da177e4
LT		 2113}
2114
2bf864ac
TI		 2115static struct snd_kcontrol_new snd_vt1724_mixer_pro_analog_route __devinitdata =
2116{
1da177e4
LT		 2117 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2118 .name = "H/W Playback Route",
2119 .info = snd_vt1724_pro_route_info,
2120 .get = snd_vt1724_pro_route_analog_get,
2121 .put = snd_vt1724_pro_route_analog_put,
2122};
2123
1b60f6b0 2124static struct snd_kcontrol_new snd_vt1724_mixer_pro_spdif_route __devinitdata = {
1da177e4 2125 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1de9fdc2 2126 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, NONE) "Route",
1da177e4
LT		 2127 .info = snd_vt1724_pro_route_info,
2128 .get = snd_vt1724_pro_route_spdif_get,
2129 .put = snd_vt1724_pro_route_spdif_put,
2130 .count = 2,
2131};
2132
2133
ab0c7d72
TI		 2134static int snd_vt1724_pro_peak_info(struct snd_kcontrol *kcontrol,
2135 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 2136{
2137 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2138 uinfo->count = 22; /* FIXME: for compatibility with ice1712... */
2139 uinfo->value.integer.min = 0;
2140 uinfo->value.integer.max = 255;
2141 return 0;
2142}
2143
ab0c7d72
TI		 2144static int snd_vt1724_pro_peak_get(struct snd_kcontrol *kcontrol,
2145 struct snd_ctl_elem_value *ucontrol)
1da177e4 2146{
ab0c7d72 2147 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4 2148 int idx;
1de9fdc2 2149
1da177e4
LT		 2150 spin_lock_irq(&ice->reg_lock);
2151 for (idx = 0; idx < 22; idx++) {
2152 outb(idx, ICEMT1724(ice, MONITOR_PEAKINDEX));
ab0c7d72
TI		 2153 ucontrol->value.integer.value[idx] =
2154 inb(ICEMT1724(ice, MONITOR_PEAKDATA));
1da177e4
LT		 2155 }
2156 spin_unlock_irq(&ice->reg_lock);
2157 return 0;
2158}
2159
1b60f6b0 2160static struct snd_kcontrol_new snd_vt1724_mixer_pro_peak __devinitdata = {
1da177e4
LT		 2161 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2162 .name = "Multi Track Peak",
2163 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
2164 .info = snd_vt1724_pro_peak_info,
2165 .get = snd_vt1724_pro_peak_get
2166};
2167
2168/*
2169 *
2170 */
2171
1b60f6b0 2172static struct snd_ice1712_card_info no_matched __devinitdata;
1da177e4 2173
1b60f6b0 2174static struct snd_ice1712_card_info *card_tables[] __devinitdata = {
1da177e4 2175 snd_vt1724_revo_cards,
1de9fdc2 2176 snd_vt1724_amp_cards,
1da177e4
LT		 2177 snd_vt1724_aureon_cards,
2178 snd_vt1720_mobo_cards,
2179 snd_vt1720_pontis_cards,
6b8d6e55 2180 snd_vt1724_prodigy_hifi_cards,
1da177e4
LT		 2181 snd_vt1724_prodigy192_cards,
2182 snd_vt1724_juli_cards,
72cbfd45 2183 snd_vt1724_maya44_cards,
1da177e4 2184 snd_vt1724_phase_cards,
f6cdab5f 2185 snd_vt1724_wtm_cards,
f31639b8 2186 snd_vt1724_se_cards,
1da177e4
LT		 2187 NULL,
2188};
2189
2190
2191/*
2192 */
2193
ab0c7d72 2194static void wait_i2c_busy(struct snd_ice1712 *ice)
1da177e4
LT		 2195{
2196 int t = 0x10000;
2197 while ((inb(ICEREG1724(ice, I2C_CTRL)) & VT1724_I2C_BUSY) && t--)
2198 ;
2199 if (t == -1)
2200 printk(KERN_ERR "ice1724: i2c busy timeout\n");
2201}
2202
ab0c7d72
TI		 2203unsigned char snd_vt1724_read_i2c(struct snd_ice1712 *ice,
2204 unsigned char dev, unsigned char addr)
1da177e4
LT		 2205{
2206 unsigned char val;
2207
62932df8 2208 mutex_lock(&ice->i2c_mutex);
acec30ff 2209 wait_i2c_busy(ice);
1da177e4
LT		 2210 outb(addr, ICEREG1724(ice, I2C_BYTE_ADDR));
2211 outb(dev & ~VT1724_I2C_WRITE, ICEREG1724(ice, I2C_DEV_ADDR));
2212 wait_i2c_busy(ice);
2213 val = inb(ICEREG1724(ice, I2C_DATA));
62932df8 2214 mutex_unlock(&ice->i2c_mutex);
e2ea7cfc
TI		 2215 /*
2216 printk(KERN_DEBUG "i2c_read: [0x%x,0x%x] = 0x%x\n", dev, addr, val);
2217 */
1da177e4
LT		 2218 return val;
2219}
2220
ab0c7d72
TI		 2221void snd_vt1724_write_i2c(struct snd_ice1712 *ice,
2222 unsigned char dev, unsigned char addr, unsigned char data)
1da177e4 2223{
62932df8 2224 mutex_lock(&ice->i2c_mutex);
1da177e4 2225 wait_i2c_busy(ice);
e2ea7cfc
TI		 2226 /*
2227 printk(KERN_DEBUG "i2c_write: [0x%x,0x%x] = 0x%x\n", dev, addr, data);
2228 */
1da177e4
LT		 2229 outb(addr, ICEREG1724(ice, I2C_BYTE_ADDR));
2230 outb(data, ICEREG1724(ice, I2C_DATA));
2231 outb(dev | VT1724_I2C_WRITE, ICEREG1724(ice, I2C_DEV_ADDR));
2232 wait_i2c_busy(ice);
62932df8 2233 mutex_unlock(&ice->i2c_mutex);
1da177e4
LT		 2234}
2235
ab0c7d72
TI		 2236static int __devinit snd_vt1724_read_eeprom(struct snd_ice1712 *ice,
2237 const char *modelname)
1da177e4
LT		 2238{
2239 const int dev = 0xa0; /* EEPROM device address */
2240 unsigned int i, size;
1b60f6b0 2241 struct snd_ice1712_card_info * const *tbl, *c;
1da177e4 2242
1de9fdc2 2243 if (!modelname || !*modelname) {
1da177e4
LT		 2244 ice->eeprom.subvendor = 0;
2245 if ((inb(ICEREG1724(ice, I2C_CTRL)) & VT1724_I2C_EEPROM) != 0)
2246 ice->eeprom.subvendor =
2247 (snd_vt1724_read_i2c(ice, dev, 0x00) << 0) |
1de9fdc2
AB		 2248 (snd_vt1724_read_i2c(ice, dev, 0x01) << 8) |
2249 (snd_vt1724_read_i2c(ice, dev, 0x02) << 16) |
1da177e4 2250 (snd_vt1724_read_i2c(ice, dev, 0x03) << 24);
ab0c7d72
TI		 2251 if (ice->eeprom.subvendor == 0 ||
2252 ice->eeprom.subvendor == (unsigned int)-1) {
2253 /* invalid subvendor from EEPROM, try the PCI
2254 * subststem ID instead
2255 */
1da177e4 2256 u16 vendor, device;
ab0c7d72
TI		 2257 pci_read_config_word(ice->pci, PCI_SUBSYSTEM_VENDOR_ID,
2258 &vendor);
1da177e4 2259 pci_read_config_word(ice->pci, PCI_SUBSYSTEM_ID, &device);
ab0c7d72
TI		 2260 ice->eeprom.subvendor =
2261 ((unsigned int)swab16(vendor) << 16) | swab16(device);
2262 if (ice->eeprom.subvendor == 0 ||
2263 ice->eeprom.subvendor == (unsigned int)-1) {
1da177e4
LT		 2264 printk(KERN_ERR "ice1724: No valid ID is found\n");
2265 return -ENXIO;
2266 }
2267 }
2268 }
2269 for (tbl = card_tables; *tbl; tbl++) {
2270 for (c = *tbl; c->subvendor; c++) {
ab0c7d72 2271 if (modelname && c->model &&
1de9fdc2 2272 !strcmp(modelname, c->model)) {
ab0c7d72
TI		 2273 printk(KERN_INFO "ice1724: Using board model %s\n",
2274 c->name);
1da177e4
LT		 2275 ice->eeprom.subvendor = c->subvendor;
2276 } else if (c->subvendor != ice->eeprom.subvendor)
2277 continue;
1de9fdc2 2278 if (!c->eeprom_size || !c->eeprom_data)
1da177e4
LT		 2279 goto found;
2280 /* if the EEPROM is given by the driver, use it */
2281 snd_printdd("using the defined eeprom..\n");
2282 ice->eeprom.version = 2;
2283 ice->eeprom.size = c->eeprom_size + 6;
2284 memcpy(ice->eeprom.data, c->eeprom_data, c->eeprom_size);
2285 goto read_skipped;
2286 }
2287 }
ab0c7d72
TI		 2288 printk(KERN_WARNING "ice1724: No matching model found for ID 0x%x\n",
2289 ice->eeprom.subvendor);
1da177e4
LT		 2290
2291 found:
2292 ice->eeprom.size = snd_vt1724_read_i2c(ice, dev, 0x04);
2293 if (ice->eeprom.size < 6)
2294 ice->eeprom.size = 32;
2295 else if (ice->eeprom.size > 32) {
ab0c7d72
TI		 2296 printk(KERN_ERR "ice1724: Invalid EEPROM (size = %i)\n",
2297 ice->eeprom.size);
1da177e4
LT		 2298 return -EIO;
2299 }
2300 ice->eeprom.version = snd_vt1724_read_i2c(ice, dev, 0x05);
2301 if (ice->eeprom.version != 2)
ab0c7d72
TI		 2302 printk(KERN_WARNING "ice1724: Invalid EEPROM version %i\n",
2303 ice->eeprom.version);
1da177e4
LT		 2304 size = ice->eeprom.size - 6;
2305 for (i = 0; i < size; i++)
2306 ice->eeprom.data[i] = snd_vt1724_read_i2c(ice, dev, i + 6);
2307
2308 read_skipped:
2309 ice->eeprom.gpiomask = eeprom_triple(ice, ICE_EEP2_GPIO_MASK);
2310 ice->eeprom.gpiostate = eeprom_triple(ice, ICE_EEP2_GPIO_STATE);
2311 ice->eeprom.gpiodir = eeprom_triple(ice, ICE_EEP2_GPIO_DIR);
2312
2313 return 0;
2314}
2315
2316
2317
cd775387 2318static void snd_vt1724_chip_reset(struct snd_ice1712 *ice)
1da177e4
LT		 2319{
2320 outb(VT1724_RESET , ICEREG1724(ice, CONTROL));
d82b64f4 2321 inb(ICEREG1724(ice, CONTROL)); /* pci posting flush */
988f0664 2322 msleep(10);
1da177e4 2323 outb(0, ICEREG1724(ice, CONTROL));
d82b64f4 2324 inb(ICEREG1724(ice, CONTROL)); /* pci posting flush */
988f0664
KW		 2325 msleep(10);
2326}
2327
b40e9538 2328static int snd_vt1724_chip_init(struct snd_ice1712 *ice)
988f0664 2329{
1da177e4
LT		 2330 outb(ice->eeprom.data[ICE_EEP2_SYSCONF], ICEREG1724(ice, SYS_CFG));
2331 outb(ice->eeprom.data[ICE_EEP2_ACLINK], ICEREG1724(ice, AC97_CFG));
2332 outb(ice->eeprom.data[ICE_EEP2_I2S], ICEREG1724(ice, I2S_FEATURES));
2333 outb(ice->eeprom.data[ICE_EEP2_SPDIF], ICEREG1724(ice, SPDIF_CFG));
2334
2335 ice->gpio.write_mask = ice->eeprom.gpiomask;
2336 ice->gpio.direction = ice->eeprom.gpiodir;
2337 snd_vt1724_set_gpio_mask(ice, ice->eeprom.gpiomask);
2338 snd_vt1724_set_gpio_dir(ice, ice->eeprom.gpiodir);
2339 snd_vt1724_set_gpio_data(ice, ice->eeprom.gpiostate);
2340
2341 outb(0, ICEREG1724(ice, POWERDOWN));
2342
b40e9538
IC		 2343 /* MPU_RX and TX irq masks are cleared later dynamically */
2344 outb(VT1724_IRQ_MPU_RX | VT1724_IRQ_MPU_TX , ICEREG1724(ice, IRQMASK));
2345
2346 /* don't handle FIFO overrun/underruns (just yet),
2347 * since they cause machine lockups
2348 */
2349 outb(VT1724_MULTI_FIFO_ERR, ICEMT1724(ice, DMA_INT_MASK));
2350
1da177e4
LT		 2351 return 0;
2352}
2353
ab0c7d72 2354static int __devinit snd_vt1724_spdif_build_controls(struct snd_ice1712 *ice)
1da177e4
LT		 2355{
2356 int err;
ab0c7d72 2357 struct snd_kcontrol *kctl;
1da177e4 2358
da3cec35
TI		 2359 if (snd_BUG_ON(!ice->pcm))
2360 return -EIO;
1da177e4 2361
2bf864ac
TI		 2362 if (!ice->own_routing) {
2363 err = snd_ctl_add(ice->card,
2364 snd_ctl_new1(&snd_vt1724_mixer_pro_spdif_route, ice));
2365 if (err < 0)
2366 return err;
2367 }
1da177e4
LT		 2368
2369 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_spdif_switch, ice));
2370 if (err < 0)
2371 return err;
2372
2373 err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_vt1724_spdif_default, ice));
2374 if (err < 0)
2375 return err;
2376 kctl->id.device = ice->pcm->device;
2377 err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_vt1724_spdif_maskc, ice));
2378 if (err < 0)
2379 return err;
2380 kctl->id.device = ice->pcm->device;
2381 err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_vt1724_spdif_maskp, ice));
2382 if (err < 0)
2383 return err;
2384 kctl->id.device = ice->pcm->device;
2385#if 0 /* use default only */
2386 err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_vt1724_spdif_stream, ice));
2387 if (err < 0)
2388 return err;
2389 kctl->id.device = ice->pcm->device;
2390 ice->spdif.stream_ctl = kctl;
2391#endif
2392 return 0;
2393}
2394
2395
ab0c7d72 2396static int __devinit snd_vt1724_build_controls(struct snd_ice1712 *ice)
1da177e4
LT		 2397{
2398 int err;
2399
2400 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_eeprom, ice));
2401 if (err < 0)
2402 return err;
2403 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_pro_internal_clock, ice));
2404 if (err < 0)
2405 return err;
2406
2407 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_pro_rate_locking, ice));
2408 if (err < 0)
2409 return err;
2410 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_pro_rate_reset, ice));
2411 if (err < 0)
2412 return err;
2413
2bf864ac 2414 if (!ice->own_routing && ice->num_total_dacs > 0) {
ab0c7d72 2415 struct snd_kcontrol_new tmp = snd_vt1724_mixer_pro_analog_route;
1da177e4
LT		 2416 tmp.count = ice->num_total_dacs;
2417 if (ice->vt1720 && tmp.count > 2)
2418 tmp.count = 2;
2419 err = snd_ctl_add(ice->card, snd_ctl_new1(&tmp, ice));
2420 if (err < 0)
2421 return err;
2422 }
2423
2424 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_mixer_pro_peak, ice));
2425 if (err < 0)
2426 return err;
2427
2428 return 0;
2429}
2430
ab0c7d72 2431static int snd_vt1724_free(struct snd_ice1712 *ice)
1da177e4 2432{
1de9fdc2 2433 if (!ice->port)
1da177e4
LT		 2434 goto __hw_end;
2435 /* mask all interrupts */
2436 outb(0xff, ICEMT1724(ice, DMA_INT_MASK));
2437 outb(0xff, ICEREG1724(ice, IRQMASK));
2438 /* --- */
1de9fdc2 2439__hw_end:
f000fd80 2440 if (ice->irq >= 0)
ab0c7d72 2441 free_irq(ice->irq, ice);
1da177e4
LT		 2442 pci_release_regions(ice->pci);
2443 snd_ice1712_akm4xxx_free(ice);
2444 pci_disable_device(ice->pci);
7cda8ba9 2445 kfree(ice->spec);
1da177e4
LT		 2446 kfree(ice);
2447 return 0;
2448}
2449
ab0c7d72 2450static int snd_vt1724_dev_free(struct snd_device *device)
1da177e4 2451{
ab0c7d72 2452 struct snd_ice1712 *ice = device->device_data;
1da177e4
LT		 2453 return snd_vt1724_free(ice);
2454}
2455
ab0c7d72 2456static int __devinit snd_vt1724_create(struct snd_card *card,
1da177e4
LT		 2457 struct pci_dev *pci,
2458 const char *modelname,
1de9fdc2 2459 struct snd_ice1712 **r_ice1712)
1da177e4 2460{
ab0c7d72 2461 struct snd_ice1712 *ice;
1da177e4 2462 int err;
ab0c7d72 2463 static struct snd_device_ops ops = {
1da177e4
LT		 2464 .dev_free = snd_vt1724_dev_free,
2465 };
2466
2467 *r_ice1712 = NULL;
2468
1de9fdc2
AB		 2469 /* enable PCI device */
2470 err = pci_enable_device(pci);
2471 if (err < 0)
1da177e4
LT		 2472 return err;
2473
e560d8d8 2474 ice = kzalloc(sizeof(*ice), GFP_KERNEL);
1da177e4
LT		 2475 if (ice == NULL) {
2476 pci_disable_device(pci);
2477 return -ENOMEM;
2478 }
2479 ice->vt1724 = 1;
2480 spin_lock_init(&ice->reg_lock);
62932df8
IM		 2481 mutex_init(&ice->gpio_mutex);
2482 mutex_init(&ice->open_mutex);
2483 mutex_init(&ice->i2c_mutex);
1da177e4 2484 ice->gpio.set_mask = snd_vt1724_set_gpio_mask;
49470306 2485 ice->gpio.get_mask = snd_vt1724_get_gpio_mask;
1da177e4 2486 ice->gpio.set_dir = snd_vt1724_set_gpio_dir;
49470306 2487 ice->gpio.get_dir = snd_vt1724_get_gpio_dir;
1da177e4
LT		 2488 ice->gpio.set_data = snd_vt1724_set_gpio_data;
2489 ice->gpio.get_data = snd_vt1724_get_gpio_data;
2490 ice->card = card;
2491 ice->pci = pci;
2492 ice->irq = -1;
2493 pci_set_master(pci);
2494 snd_vt1724_proc_init(ice);
2495 synchronize_irq(pci->irq);
2496
b40e9538
IC		 2497 card->private_data = ice;
2498
1de9fdc2
AB		 2499 err = pci_request_regions(pci, "ICE1724");
2500 if (err < 0) {
1da177e4
LT		 2501 kfree(ice);
2502 pci_disable_device(pci);
2503 return err;
2504 }
2505 ice->port = pci_resource_start(pci, 0);
2506 ice->profi_port = pci_resource_start(pci, 1);
2507
ab0c7d72 2508 if (request_irq(pci->irq, snd_vt1724_interrupt,
437a5a46 2509 IRQF_SHARED, "ICE1724", ice)) {
99b359ba 2510 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1da177e4
LT		 2511 snd_vt1724_free(ice);
2512 return -EIO;
2513 }
2514
2515 ice->irq = pci->irq;
2516
988f0664 2517 snd_vt1724_chip_reset(ice);
1da177e4
LT		 2518 if (snd_vt1724_read_eeprom(ice, modelname) < 0) {
2519 snd_vt1724_free(ice);
2520 return -EIO;
2521 }
2522 if (snd_vt1724_chip_init(ice) < 0) {
2523 snd_vt1724_free(ice);
2524 return -EIO;
2525 }
2526
1de9fdc2
AB		 2527 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ice, &ops);
2528 if (err < 0) {
1da177e4 2529 snd_vt1724_free(ice);
1de9fdc2 2530 return err;
1da177e4
LT		 2531 }
2532
2533 snd_card_set_dev(card, &pci->dev);
2534
2535 *r_ice1712 = ice;
2536 return 0;
2537}
2538
2539
2540/*
2541 *
2542 * Registration
2543 *
2544 */
2545
2546static int __devinit snd_vt1724_probe(struct pci_dev *pci,
2547 const struct pci_device_id *pci_id)
2548{
2549 static int dev;
ab0c7d72
TI		 2550 struct snd_card *card;
2551 struct snd_ice1712 *ice;
1da177e4 2552 int pcm_dev = 0, err;
1b60f6b0 2553 struct snd_ice1712_card_info * const *tbl, *c;
1da177e4
LT		 2554
2555 if (dev >= SNDRV_CARDS)
2556 return -ENODEV;
2557 if (!enable[dev]) {
2558 dev++;
2559 return -ENOENT;
2560 }
2561
e58de7ba
TI		 2562 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2563 if (err < 0)
2564 return err;
1da177e4
LT		 2565
2566 strcpy(card->driver, "ICE1724");
2567 strcpy(card->shortname, "ICEnsemble ICE1724");
1de9fdc2
AB		 2568
2569 err = snd_vt1724_create(card, pci, model[dev], &ice);
2570 if (err < 0) {
1da177e4
LT		 2571 snd_card_free(card);
2572 return err;
2573 }
2574
1ff97cb9
PH		 2575 /* field init before calling chip_init */
2576 ice->ext_clock_count = 0;
2577
1da177e4
LT		 2578 for (tbl = card_tables; *tbl; tbl++) {
2579 for (c = *tbl; c->subvendor; c++) {
2580 if (c->subvendor == ice->eeprom.subvendor) {
2581 strcpy(card->shortname, c->name);
2582 if (c->driver) /* specific driver? */
2583 strcpy(card->driver, c->driver);
2584 if (c->chip_init) {
1de9fdc2
AB		 2585 err = c->chip_init(ice);
2586 if (err < 0) {
1da177e4
LT		 2587 snd_card_free(card);
2588 return err;
2589 }
2590 }
2591 goto __found;
2592 }
2593 }
2594 }
2595 c = &no_matched;
1de9fdc2
AB		 2596__found:
2597 /*
2598 * VT1724 has separate DMAs for the analog and the SPDIF streams while
2599 * ICE1712 has only one for both (mixed up).
2600 *
2601 * Confusingly the analog PCM is named "professional" here because it
2602 * was called so in ice1712 driver, and vt1724 driver is derived from
2603 * ice1712 driver.
2604 */
d16be8ed
PH		 2605 ice->pro_rate_default = PRO_RATE_DEFAULT;
2606 if (!ice->is_spdif_master)
2607 ice->is_spdif_master = stdclock_is_spdif_master;
2608 if (!ice->get_rate)
2609 ice->get_rate = stdclock_get_rate;
2610 if (!ice->set_rate)
2611 ice->set_rate = stdclock_set_rate;
2612 if (!ice->set_mclk)
2613 ice->set_mclk = stdclock_set_mclk;
2614 if (!ice->set_spdif_clock)
2615 ice->set_spdif_clock = stdclock_set_spdif_clock;
1ff97cb9
PH		 2616 if (!ice->get_spdif_master_type)
2617 ice->get_spdif_master_type = stdclock_get_spdif_master_type;
2618 if (!ice->ext_clock_names)
2619 ice->ext_clock_names = ext_clock_names;
2620 if (!ice->ext_clock_count)
2621 ice->ext_clock_count = ARRAY_SIZE(ext_clock_names);
2622
d16be8ed
PH		 2623 if (!ice->hw_rates)
2624 set_std_hw_rates(ice);
1da177e4 2625
1de9fdc2
AB		 2626 err = snd_vt1724_pcm_profi(ice, pcm_dev++);
2627 if (err < 0) {
1da177e4
LT		 2628 snd_card_free(card);
2629 return err;
2630 }
1de9fdc2
AB		 2631
2632 err = snd_vt1724_pcm_spdif(ice, pcm_dev++);
2633 if (err < 0) {
1da177e4
LT		 2634 snd_card_free(card);
2635 return err;
2636 }
1de9fdc2
AB		 2637
2638 err = snd_vt1724_pcm_indep(ice, pcm_dev++);
2639 if (err < 0) {
1da177e4
LT		 2640 snd_card_free(card);
2641 return err;
2642 }
2643
1de9fdc2
AB		 2644 err = snd_vt1724_ac97_mixer(ice);
2645 if (err < 0) {
1da177e4
LT		 2646 snd_card_free(card);
2647 return err;
2648 }
2649
1de9fdc2
AB		 2650 err = snd_vt1724_build_controls(ice);
2651 if (err < 0) {
1da177e4
LT		 2652 snd_card_free(card);
2653 return err;
2654 }
2655
2656 if (ice->pcm && ice->has_spdif) { /* has SPDIF I/O */
1de9fdc2
AB		 2657 err = snd_vt1724_spdif_build_controls(ice);
2658 if (err < 0) {
1da177e4
LT		 2659 snd_card_free(card);
2660 return err;
2661 }
2662 }
2663
2664 if (c->build_controls) {
1de9fdc2
AB		 2665 err = c->build_controls(ice);
2666 if (err < 0) {
1da177e4
LT		 2667 snd_card_free(card);
2668 return err;
2669 }
2670 }
2671
1de9fdc2 2672 if (!c->no_mpu401) {
1da177e4 2673 if (ice->eeprom.data[ICE_EEP2_SYSCONF] & VT1724_CFG_MPU401) {
aea3bfbc
CL		 2674 struct snd_rawmidi *rmidi;
2675
2676 err = snd_rawmidi_new(card, "MIDI", 0, 1, 1, &rmidi);
2677 if (err < 0) {
1da177e4
LT		 2678 snd_card_free(card);
2679 return err;
2680 }
aea3bfbc
CL		 2681 ice->rmidi[0] = rmidi;
2682 rmidi->private_data = ice;
2683 strcpy(rmidi->name, "ICE1724 MIDI");
2684 rmidi->info_flags = SNDRV_RAWMIDI_INFO_OUTPUT |
2685 SNDRV_RAWMIDI_INFO_INPUT |
2686 SNDRV_RAWMIDI_INFO_DUPLEX;
2687 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT,
2688 &vt1724_midi_output_ops);
2689 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT,
2690 &vt1724_midi_input_ops);
2691
3a841d51
TI		 2692 /* set watermarks */
2693 outb(VT1724_MPU_RX_FIFO | 0x1,
2694 ICEREG1724(ice, MPU_FIFO_WM));
2695 outb(0x1, ICEREG1724(ice, MPU_FIFO_WM));
aea3bfbc
CL		 2696 /* set UART mode */
2697 outb(VT1724_MPU_UART, ICEREG1724(ice, MPU_CTRL));
1da177e4
LT		 2698 }
2699 }
2700
2701 sprintf(card->longname, "%s at 0x%lx, irq %i",
2702 card->shortname, ice->port, ice->irq);
2703
1de9fdc2
AB		 2704 err = snd_card_register(card);
2705 if (err < 0) {
1da177e4
LT		 2706 snd_card_free(card);
2707 return err;
2708 }
2709 pci_set_drvdata(pci, card);
2710 dev++;
2711 return 0;
2712}
2713
2714static void __devexit snd_vt1724_remove(struct pci_dev *pci)
2715{
2716 snd_card_free(pci_get_drvdata(pci));
2717 pci_set_drvdata(pci, NULL);
2718}
2719
b40e9538
IC		 2720#ifdef CONFIG_PM
2721static int snd_vt1724_suspend(struct pci_dev *pci, pm_message_t state)
2722{
2723 struct snd_card *card = pci_get_drvdata(pci);
2724 struct snd_ice1712 *ice = card->private_data;
2725
2726 if (!ice->pm_suspend_enabled)
2727 return 0;
2728
2729 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2730
2731 snd_pcm_suspend_all(ice->pcm);
2732 snd_pcm_suspend_all(ice->pcm_pro);
2733 snd_pcm_suspend_all(ice->pcm_ds);
2734 snd_ac97_suspend(ice->ac97);
2735
2736 spin_lock_irq(&ice->reg_lock);
2737 ice->pm_saved_is_spdif_master = ice->is_spdif_master(ice);
2738 ice->pm_saved_spdif_ctrl = inw(ICEMT1724(ice, SPDIF_CTRL));
2739 ice->pm_saved_spdif_cfg = inb(ICEREG1724(ice, SPDIF_CFG));
2740 ice->pm_saved_route = inl(ICEMT1724(ice, ROUTE_PLAYBACK));
2741 spin_unlock_irq(&ice->reg_lock);
2742
2743 if (ice->pm_suspend)
2744 ice->pm_suspend(ice);
2745
2746 pci_disable_device(pci);
2747 pci_save_state(pci);
2748 pci_set_power_state(pci, pci_choose_state(pci, state));
2749 return 0;
2750}
2751
2752static int snd_vt1724_resume(struct pci_dev *pci)
2753{
2754 struct snd_card *card = pci_get_drvdata(pci);
2755 struct snd_ice1712 *ice = card->private_data;
2756
2757 if (!ice->pm_suspend_enabled)
2758 return 0;
2759
2760 pci_set_power_state(pci, PCI_D0);
2761 pci_restore_state(pci);
2762
2763 if (pci_enable_device(pci) < 0) {
2764 snd_card_disconnect(card);
2765 return -EIO;
2766 }
2767
2768 pci_set_master(pci);
2769
2770 snd_vt1724_chip_reset(ice);
2771
2772 if (snd_vt1724_chip_init(ice) < 0) {
2773 snd_card_disconnect(card);
2774 return -EIO;
2775 }
2776
2777 if (ice->pm_resume)
2778 ice->pm_resume(ice);
2779
2780 if (ice->pm_saved_is_spdif_master) {
2781 /* switching to external clock via SPDIF */
1ff97cb9 2782 ice->set_spdif_clock(ice, 0);
b40e9538
IC		 2783 } else {
2784 /* internal on-card clock */
2785 snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 1);
2786 }
2787
2788 update_spdif_bits(ice, ice->pm_saved_spdif_ctrl);
2789
2790 outb(ice->pm_saved_spdif_cfg, ICEREG1724(ice, SPDIF_CFG));
2791 outl(ice->pm_saved_route, ICEMT1724(ice, ROUTE_PLAYBACK));
2792
2793 if (ice->ac97)
2794 snd_ac97_resume(ice->ac97);
2795
2796 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2797 return 0;
2798}
2799#endif
2800
1da177e4
LT		 2801static struct pci_driver driver = {
2802 .name = "ICE1724",
2803 .id_table = snd_vt1724_ids,
2804 .probe = snd_vt1724_probe,
2805 .remove = __devexit_p(snd_vt1724_remove),
b40e9538
IC		 2806#ifdef CONFIG_PM
2807 .suspend = snd_vt1724_suspend,
2808 .resume = snd_vt1724_resume,
2809#endif
1da177e4
LT		 2810};
2811
2812static int __init alsa_card_ice1724_init(void)
2813{
01d25d46 2814 return pci_register_driver(&driver);
1da177e4
LT		 2815}
2816
2817static void __exit alsa_card_ice1724_exit(void)
2818{
2819 pci_unregister_driver(&driver);
2820}
2821
2822module_init(alsa_card_ice1724_init)
2823module_exit(alsa_card_ice1724_exit)
Linux kernel - Deliverables
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