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ASoC: fsi: use dmaengine_prep_dma_cyclic() for DMA transfer
[deliverable/linux.git] / sound / pci / ice1712 / quartet.c
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6ef80706
PH		 1/*
2 * ALSA driver for ICEnsemble VT1724 (Envy24HT)
3 *
4 * Lowlevel functions for Infrasonic Quartet
5 *
6 * Copyright (c) 2009 Pavel Hofman <pavel.hofman@ivitera.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
6ef80706
PH		 25#include <linux/delay.h>
26#include <linux/interrupt.h>
27#include <linux/init.h>
28#include <linux/slab.h>
29#include <sound/core.h>
30#include <sound/tlv.h>
31#include <sound/info.h>
32
33#include "ice1712.h"
34#include "envy24ht.h"
35#include <sound/ak4113.h>
36#include "quartet.h"
37
38struct qtet_spec {
39 struct ak4113 *ak4113;
40 unsigned int scr; /* system control register */
41 unsigned int mcr; /* monitoring control register */
42 unsigned int cpld; /* cpld register */
43};
44
45struct qtet_kcontrol_private {
46 unsigned int bit;
47 void (*set_register)(struct snd_ice1712 *ice, unsigned int val);
48 unsigned int (*get_register)(struct snd_ice1712 *ice);
a2af050f 49 unsigned char * const texts[2];
6ef80706
PH		 50};
51
52enum {
53 IN12_SEL = 0,
54 IN34_SEL,
55 AIN34_SEL,
56 COAX_OUT,
57 IN12_MON12,
58 IN12_MON34,
59 IN34_MON12,
60 IN34_MON34,
61 OUT12_MON34,
62 OUT34_MON12,
63};
64
a2af050f 65static const char * const ext_clock_names[3] = {"IEC958 In", "Word Clock 1xFS",
6ef80706
PH		 66 "Word Clock 256xFS"};
67
68/* chip address on I2C bus */
69#define AK4113_ADDR 0x26 /* S/PDIF receiver */
70
71/* chip address on SPI bus */
72#define AK4620_ADDR 0x02 /* ADC/DAC */
73
74
75/*
76 * GPIO pins
77 */
78
79/* GPIO0 - O - DATA0, def. 0 */
80#define GPIO_D0 (1<<0)
81/* GPIO1 - I/O - DATA1, Jack Detect Input0 (0:present, 1:missing), def. 1 */
82#define GPIO_D1_JACKDTC0 (1<<1)
83/* GPIO2 - I/O - DATA2, Jack Detect Input1 (0:present, 1:missing), def. 1 */
84#define GPIO_D2_JACKDTC1 (1<<2)
85/* GPIO3 - I/O - DATA3, def. 1 */
86#define GPIO_D3 (1<<3)
87/* GPIO4 - I/O - DATA4, SPI CDTO, def. 1 */
88#define GPIO_D4_SPI_CDTO (1<<4)
89/* GPIO5 - I/O - DATA5, SPI CCLK, def. 1 */
90#define GPIO_D5_SPI_CCLK (1<<5)
91/* GPIO6 - I/O - DATA6, Cable Detect Input (0:detected, 1:not detected */
92#define GPIO_D6_CD (1<<6)
93/* GPIO7 - I/O - DATA7, Device Detect Input (0:detected, 1:not detected */
94#define GPIO_D7_DD (1<<7)
95/* GPIO8 - O - CPLD Chip Select, def. 1 */
96#define GPIO_CPLD_CSN (1<<8)
97/* GPIO9 - O - CPLD register read/write (0:write, 1:read), def. 0 */
98#define GPIO_CPLD_RW (1<<9)
99/* GPIO10 - O - SPI Chip Select for CODEC#0, def. 1 */
100#define GPIO_SPI_CSN0 (1<<10)
101/* GPIO11 - O - SPI Chip Select for CODEC#1, def. 1 */
102#define GPIO_SPI_CSN1 (1<<11)
103/* GPIO12 - O - Ex. Register Output Enable (0:enable, 1:disable), def. 1,
104 * init 0 */
105#define GPIO_EX_GPIOE (1<<12)
106/* GPIO13 - O - Ex. Register0 Chip Select for System Control Register,
107 * def. 1 */
108#define GPIO_SCR (1<<13)
109/* GPIO14 - O - Ex. Register1 Chip Select for Monitor Control Register,
110 * def. 1 */
111#define GPIO_MCR (1<<14)
112
113#define GPIO_SPI_ALL (GPIO_D4_SPI_CDTO | GPIO_D5_SPI_CCLK |\
114 GPIO_SPI_CSN0 | GPIO_SPI_CSN1)
115
116#define GPIO_DATA_MASK (GPIO_D0 | GPIO_D1_JACKDTC0 | \
117 GPIO_D2_JACKDTC1 | GPIO_D3 | \
118 GPIO_D4_SPI_CDTO | GPIO_D5_SPI_CCLK | \
119 GPIO_D6_CD | GPIO_D7_DD)
120
121/* System Control Register GPIO_SCR data bits */
122/* Mic/Line select relay (0:line, 1:mic) */
123#define SCR_RELAY GPIO_D0
124/* Phantom power drive control (0:5V, 1:48V) */
125#define SCR_PHP_V GPIO_D1_JACKDTC0
126/* H/W mute control (0:Normal, 1:Mute) */
127#define SCR_MUTE GPIO_D2_JACKDTC1
128/* Phantom power control (0:Phantom on, 1:off) */
129#define SCR_PHP GPIO_D3
130/* Analog input 1/2 Source Select */
131#define SCR_AIN12_SEL0 GPIO_D4_SPI_CDTO
132#define SCR_AIN12_SEL1 GPIO_D5_SPI_CCLK
133/* Analog input 3/4 Source Select (0:line, 1:hi-z) */
134#define SCR_AIN34_SEL GPIO_D6_CD
135/* Codec Power Down (0:power down, 1:normal) */
136#define SCR_CODEC_PDN GPIO_D7_DD
137
138#define SCR_AIN12_LINE (0)
139#define SCR_AIN12_MIC (SCR_AIN12_SEL0)
140#define SCR_AIN12_LOWCUT (SCR_AIN12_SEL1 | SCR_AIN12_SEL0)
141
142/* Monitor Control Register GPIO_MCR data bits */
143/* Input 1/2 to Monitor 1/2 (0:off, 1:on) */
144#define MCR_IN12_MON12 GPIO_D0
145/* Input 1/2 to Monitor 3/4 (0:off, 1:on) */
146#define MCR_IN12_MON34 GPIO_D1_JACKDTC0
147/* Input 3/4 to Monitor 1/2 (0:off, 1:on) */
148#define MCR_IN34_MON12 GPIO_D2_JACKDTC1
149/* Input 3/4 to Monitor 3/4 (0:off, 1:on) */
150#define MCR_IN34_MON34 GPIO_D3
151/* Output to Monitor 1/2 (0:off, 1:on) */
152#define MCR_OUT34_MON12 GPIO_D4_SPI_CDTO
153/* Output to Monitor 3/4 (0:off, 1:on) */
154#define MCR_OUT12_MON34 GPIO_D5_SPI_CCLK
155
156/* CPLD Register DATA bits */
157/* Clock Rate Select */
158#define CPLD_CKS0 GPIO_D0
159#define CPLD_CKS1 GPIO_D1_JACKDTC0
160#define CPLD_CKS2 GPIO_D2_JACKDTC1
161/* Sync Source Select (0:Internal, 1:External) */
162#define CPLD_SYNC_SEL GPIO_D3
163/* Word Clock FS Select (0:FS, 1:256FS) */
164#define CPLD_WORD_SEL GPIO_D4_SPI_CDTO
165/* Coaxial Output Source (IS-Link) (0:SPDIF, 1:I2S) */
166#define CPLD_COAX_OUT GPIO_D5_SPI_CCLK
167/* Input 1/2 Source Select (0:Analog12, 1:An34) */
168#define CPLD_IN12_SEL GPIO_D6_CD
169/* Input 3/4 Source Select (0:Analog34, 1:Digital In) */
170#define CPLD_IN34_SEL GPIO_D7_DD
171
172/* internal clock (CPLD_SYNC_SEL = 0) options */
173#define CPLD_CKS_44100HZ (0)
174#define CPLD_CKS_48000HZ (CPLD_CKS0)
175#define CPLD_CKS_88200HZ (CPLD_CKS1)
176#define CPLD_CKS_96000HZ (CPLD_CKS1 | CPLD_CKS0)
177#define CPLD_CKS_176400HZ (CPLD_CKS2)
178#define CPLD_CKS_192000HZ (CPLD_CKS2 | CPLD_CKS0)
179
180#define CPLD_CKS_MASK (CPLD_CKS0 | CPLD_CKS1 | CPLD_CKS2)
181
182/* external clock (CPLD_SYNC_SEL = 1) options */
183/* external clock - SPDIF */
184#define CPLD_EXT_SPDIF (0 | CPLD_SYNC_SEL)
185/* external clock - WordClock 1xfs */
186#define CPLD_EXT_WORDCLOCK_1FS (CPLD_CKS1 | CPLD_SYNC_SEL)
187/* external clock - WordClock 256xfs */
188#define CPLD_EXT_WORDCLOCK_256FS (CPLD_CKS1 | CPLD_WORD_SEL |\
189 CPLD_SYNC_SEL)
190
191#define EXT_SPDIF_TYPE 0
192#define EXT_WORDCLOCK_1FS_TYPE 1
193#define EXT_WORDCLOCK_256FS_TYPE 2
194
195#define AK4620_DFS0 (1<<0)
196#define AK4620_DFS1 (1<<1)
197#define AK4620_CKS0 (1<<2)
198#define AK4620_CKS1 (1<<3)
199/* Clock and Format Control register */
200#define AK4620_DFS_REG 0x02
201
202/* Deem and Volume Control register */
203#define AK4620_DEEMVOL_REG 0x03
204#define AK4620_SMUTE (1<<7)
205
512a4cb9 206#ifdef CONFIG_PROC_FS
6ef80706
PH		 207/*
208 * Conversion from int value to its binary form. Used for debugging.
209 * The output buffer must be allocated prior to calling the function.
210 */
211static char *get_binary(char *buffer, int value)
212{
213 int i, j, pos;
214 pos = 0;
215 for (i = 0; i < 4; ++i) {
216 for (j = 0; j < 8; ++j) {
217 if (value & (1 << (31-(i*8 + j))))
218 buffer[pos] = '1';
219 else
220 buffer[pos] = '0';
221 pos++;
222 }
223 if (i < 3) {
224 buffer[pos] = ' ';
225 pos++;
226 }
227 }
228 buffer[pos] = '\0';
229 return buffer;
230}
512a4cb9 231#endif /* CONFIG_PROC_FS */
6ef80706
PH		 232
233/*
234 * Initial setup of the conversion array GPIO <-> rate
235 */
236static unsigned int qtet_rates[] = {
237 44100, 48000, 88200,
238 96000, 176400, 192000,
239};
240
241static unsigned int cks_vals[] = {
242 CPLD_CKS_44100HZ, CPLD_CKS_48000HZ, CPLD_CKS_88200HZ,
243 CPLD_CKS_96000HZ, CPLD_CKS_176400HZ, CPLD_CKS_192000HZ,
244};
245
246static struct snd_pcm_hw_constraint_list qtet_rates_info = {
247 .count = ARRAY_SIZE(qtet_rates),
248 .list = qtet_rates,
249 .mask = 0,
250};
251
252static void qtet_ak4113_write(void *private_data, unsigned char reg,
253 unsigned char val)
254{
255 snd_vt1724_write_i2c((struct snd_ice1712 *)private_data, AK4113_ADDR,
256 reg, val);
257}
258
259static unsigned char qtet_ak4113_read(void *private_data, unsigned char reg)
260{
261 return snd_vt1724_read_i2c((struct snd_ice1712 *)private_data,
262 AK4113_ADDR, reg);
263}
264
265
266/*
267 * AK4620 section
268 */
269
270/*
271 * Write data to addr register of ak4620
272 */
273static void qtet_akm_write(struct snd_akm4xxx *ak, int chip,
274 unsigned char addr, unsigned char data)
275{
276 unsigned int tmp, orig_dir;
277 int idx;
278 unsigned int addrdata;
279 struct snd_ice1712 *ice = ak->private_data[0];
280
281 if (snd_BUG_ON(chip < 0 || chip >= 4))
282 return;
6dfb5aff 283 /*dev_dbg(ice->card->dev, "Writing to AK4620: chip=%d, addr=0x%x,
6ef80706
PH		 284 data=0x%x\n", chip, addr, data);*/
285 orig_dir = ice->gpio.get_dir(ice);
286 ice->gpio.set_dir(ice, orig_dir | GPIO_SPI_ALL);
287 /* set mask - only SPI bits */
288 ice->gpio.set_mask(ice, ~GPIO_SPI_ALL);
289
290 tmp = ice->gpio.get_data(ice);
291 /* high all */
292 tmp |= GPIO_SPI_ALL;
293 ice->gpio.set_data(ice, tmp);
294 udelay(100);
295 /* drop chip select */
296 if (chip)
297 /* CODEC 1 */
298 tmp &= ~GPIO_SPI_CSN1;
299 else
300 tmp &= ~GPIO_SPI_CSN0;
301 ice->gpio.set_data(ice, tmp);
302 udelay(100);
303
304 /* build I2C address + data byte */
305 addrdata = (AK4620_ADDR << 6) | 0x20 | (addr & 0x1f);
306 addrdata = (addrdata << 8) | data;
307 for (idx = 15; idx >= 0; idx--) {
308 /* drop clock */
309 tmp &= ~GPIO_D5_SPI_CCLK;
310 ice->gpio.set_data(ice, tmp);
311 udelay(100);
312 /* set data */
313 if (addrdata & (1 << idx))
314 tmp |= GPIO_D4_SPI_CDTO;
315 else
316 tmp &= ~GPIO_D4_SPI_CDTO;
317 ice->gpio.set_data(ice, tmp);
318 udelay(100);
319 /* raise clock */
320 tmp |= GPIO_D5_SPI_CCLK;
321 ice->gpio.set_data(ice, tmp);
322 udelay(100);
323 }
324 /* all back to 1 */
325 tmp |= GPIO_SPI_ALL;
326 ice->gpio.set_data(ice, tmp);
327 udelay(100);
328
329 /* return all gpios to non-writable */
330 ice->gpio.set_mask(ice, 0xffffff);
331 /* restore GPIOs direction */
332 ice->gpio.set_dir(ice, orig_dir);
333}
334
335static void qtet_akm_set_regs(struct snd_akm4xxx *ak, unsigned char addr,
336 unsigned char mask, unsigned char value)
337{
338 unsigned char tmp;
339 int chip;
340 for (chip = 0; chip < ak->num_chips; chip++) {
341 tmp = snd_akm4xxx_get(ak, chip, addr);
342 /* clear the bits */
343 tmp &= ~mask;
344 /* set the new bits */
345 tmp |= value;
346 snd_akm4xxx_write(ak, chip, addr, tmp);
347 }
348}
349
350/*
351 * change the rate of AK4620
352 */
353static void qtet_akm_set_rate_val(struct snd_akm4xxx *ak, unsigned int rate)
354{
355 unsigned char ak4620_dfs;
356
357 if (rate == 0) /* no hint - S/PDIF input is master or the new spdif
358 input rate undetected, simply return */
359 return;
360
361 /* adjust DFS on codecs - see datasheet */
362 if (rate > 108000)
363 ak4620_dfs = AK4620_DFS1 | AK4620_CKS1;
364 else if (rate > 54000)
365 ak4620_dfs = AK4620_DFS0 | AK4620_CKS0;
366 else
367 ak4620_dfs = 0;
368
369 /* set new value */
370 qtet_akm_set_regs(ak, AK4620_DFS_REG, AK4620_DFS0 | AK4620_DFS1 |
371 AK4620_CKS0 | AK4620_CKS1, ak4620_dfs);
372}
373
374#define AK_CONTROL(xname, xch) { .name = xname, .num_channels = xch }
375
376#define PCM_12_PLAYBACK_VOLUME "PCM 1/2 Playback Volume"
377#define PCM_34_PLAYBACK_VOLUME "PCM 3/4 Playback Volume"
378#define PCM_12_CAPTURE_VOLUME "PCM 1/2 Capture Volume"
379#define PCM_34_CAPTURE_VOLUME "PCM 3/4 Capture Volume"
380
381static const struct snd_akm4xxx_dac_channel qtet_dac[] = {
382 AK_CONTROL(PCM_12_PLAYBACK_VOLUME, 2),
383 AK_CONTROL(PCM_34_PLAYBACK_VOLUME, 2),
384};
385
386static const struct snd_akm4xxx_adc_channel qtet_adc[] = {
387 AK_CONTROL(PCM_12_CAPTURE_VOLUME, 2),
388 AK_CONTROL(PCM_34_CAPTURE_VOLUME, 2),
389};
390
e23e7a14 391static struct snd_akm4xxx akm_qtet_dac = {
6ef80706
PH		 392 .type = SND_AK4620,
393 .num_dacs = 4, /* DAC1 - Output 12
394 */
395 .num_adcs = 4, /* ADC1 - Input 12
396 */
397 .ops = {
398 .write = qtet_akm_write,
399 .set_rate_val = qtet_akm_set_rate_val,
400 },
401 .dac_info = qtet_dac,
402 .adc_info = qtet_adc,
403};
404
405/* Communication routines with the CPLD */
406
407
408/* Writes data to external register reg, both reg and data are
409 * GPIO representations */
410static void reg_write(struct snd_ice1712 *ice, unsigned int reg,
411 unsigned int data)
412{
413 unsigned int tmp;
414
415 mutex_lock(&ice->gpio_mutex);
416 /* set direction of used GPIOs*/
417 /* all outputs */
418 tmp = 0x00ffff;
419 ice->gpio.set_dir(ice, tmp);
420 /* mask - writable bits */
421 ice->gpio.set_mask(ice, ~(tmp));
422 /* write the data */
423 tmp = ice->gpio.get_data(ice);
424 tmp &= ~GPIO_DATA_MASK;
425 tmp |= data;
426 ice->gpio.set_data(ice, tmp);
427 udelay(100);
428 /* drop output enable */
429 tmp &= ~GPIO_EX_GPIOE;
430 ice->gpio.set_data(ice, tmp);
431 udelay(100);
432 /* drop the register gpio */
433 tmp &= ~reg;
434 ice->gpio.set_data(ice, tmp);
435 udelay(100);
436 /* raise the register GPIO */
437 tmp |= reg;
438 ice->gpio.set_data(ice, tmp);
439 udelay(100);
440
441 /* raise all data gpios */
442 tmp |= GPIO_DATA_MASK;
443 ice->gpio.set_data(ice, tmp);
444 /* mask - immutable bits */
445 ice->gpio.set_mask(ice, 0xffffff);
446 /* outputs only 8-15 */
447 ice->gpio.set_dir(ice, 0x00ff00);
448 mutex_unlock(&ice->gpio_mutex);
449}
450
451static unsigned int get_scr(struct snd_ice1712 *ice)
452{
453 struct qtet_spec *spec = ice->spec;
454 return spec->scr;
455}
456
457static unsigned int get_mcr(struct snd_ice1712 *ice)
458{
459 struct qtet_spec *spec = ice->spec;
460 return spec->mcr;
461}
462
463static unsigned int get_cpld(struct snd_ice1712 *ice)
464{
465 struct qtet_spec *spec = ice->spec;
466 return spec->cpld;
467}
468
469static void set_scr(struct snd_ice1712 *ice, unsigned int val)
470{
471 struct qtet_spec *spec = ice->spec;
472 reg_write(ice, GPIO_SCR, val);
473 spec->scr = val;
474}
475
476static void set_mcr(struct snd_ice1712 *ice, unsigned int val)
477{
478 struct qtet_spec *spec = ice->spec;
479 reg_write(ice, GPIO_MCR, val);
480 spec->mcr = val;
481}
482
483static void set_cpld(struct snd_ice1712 *ice, unsigned int val)
484{
485 struct qtet_spec *spec = ice->spec;
486 reg_write(ice, GPIO_CPLD_CSN, val);
487 spec->cpld = val;
488}
489#ifdef CONFIG_PROC_FS
490static void proc_regs_read(struct snd_info_entry *entry,
491 struct snd_info_buffer *buffer)
492{
493 struct snd_ice1712 *ice = entry->private_data;
494 char bin_buffer[36];
495
496 snd_iprintf(buffer, "SCR: %s\n", get_binary(bin_buffer,
497 get_scr(ice)));
498 snd_iprintf(buffer, "MCR: %s\n", get_binary(bin_buffer,
499 get_mcr(ice)));
500 snd_iprintf(buffer, "CPLD: %s\n", get_binary(bin_buffer,
501 get_cpld(ice)));
502}
503
504static void proc_init(struct snd_ice1712 *ice)
505{
506 struct snd_info_entry *entry;
507 if (!snd_card_proc_new(ice->card, "quartet", &entry))
508 snd_info_set_text_ops(entry, ice, proc_regs_read);
509}
510#else /* !CONFIG_PROC_FS */
511static void proc_init(struct snd_ice1712 *ice) {}
512#endif
513
514static int qtet_mute_get(struct snd_kcontrol *kcontrol,
515 struct snd_ctl_elem_value *ucontrol)
516{
517 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
518 unsigned int val;
519 val = get_scr(ice) & SCR_MUTE;
520 ucontrol->value.integer.value[0] = (val) ? 0 : 1;
521 return 0;
522}
523
524static int qtet_mute_put(struct snd_kcontrol *kcontrol,
525 struct snd_ctl_elem_value *ucontrol)
526{
527 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
528 unsigned int old, new, smute;
529 old = get_scr(ice) & SCR_MUTE;
530 if (ucontrol->value.integer.value[0]) {
531 /* unmute */
532 new = 0;
533 /* un-smuting DAC */
534 smute = 0;
535 } else {
536 /* mute */
537 new = SCR_MUTE;
538 /* smuting DAC */
539 smute = AK4620_SMUTE;
540 }
541 if (old != new) {
542 struct snd_akm4xxx *ak = ice->akm;
543 set_scr(ice, (get_scr(ice) & ~SCR_MUTE) | new);
544 /* set smute */
545 qtet_akm_set_regs(ak, AK4620_DEEMVOL_REG, AK4620_SMUTE, smute);
546 return 1;
547 }
548 /* no change */
549 return 0;
550}
551
552static int qtet_ain12_enum_info(struct snd_kcontrol *kcontrol,
553 struct snd_ctl_elem_info *uinfo)
554{
a2af050f
TI		 555 static const char * const texts[3] =
556 {"Line In 1/2", "Mic", "Mic + Low-cut"};
6ef80706
PH		 557 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
558 uinfo->count = 1;
559 uinfo->value.enumerated.items = ARRAY_SIZE(texts);
560
561 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
562 uinfo->value.enumerated.item =
563 uinfo->value.enumerated.items - 1;
564 strcpy(uinfo->value.enumerated.name,
565 texts[uinfo->value.enumerated.item]);
566
567 return 0;
568}
569
570static int qtet_ain12_sw_get(struct snd_kcontrol *kcontrol,
571 struct snd_ctl_elem_value *ucontrol)
572{
573 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
574 unsigned int val, result;
575 val = get_scr(ice) & (SCR_AIN12_SEL1 | SCR_AIN12_SEL0);
576 switch (val) {
577 case SCR_AIN12_LINE:
578 result = 0;
579 break;
580 case SCR_AIN12_MIC:
581 result = 1;
582 break;
583 case SCR_AIN12_LOWCUT:
584 result = 2;
585 break;
586 default:
587 /* BUG - no other combinations allowed */
588 snd_BUG();
589 result = 0;
590 }
591 ucontrol->value.integer.value[0] = result;
592 return 0;
593}
594
595static int qtet_ain12_sw_put(struct snd_kcontrol *kcontrol,
596 struct snd_ctl_elem_value *ucontrol)
597{
598 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
599 unsigned int old, new, tmp, masked_old;
600 old = new = get_scr(ice);
601 masked_old = old & (SCR_AIN12_SEL1 | SCR_AIN12_SEL0);
602 tmp = ucontrol->value.integer.value[0];
603 if (tmp == 2)
604 tmp = 3; /* binary 10 is not supported */
605 tmp <<= 4; /* shifting to SCR_AIN12_SEL0 */
606 if (tmp != masked_old) {
607 /* change requested */
608 switch (tmp) {
609 case SCR_AIN12_LINE:
610 new = old & ~(SCR_AIN12_SEL1 | SCR_AIN12_SEL0);
611 set_scr(ice, new);
612 /* turn off relay */
613 new &= ~SCR_RELAY;
614 set_scr(ice, new);
615 break;
616 case SCR_AIN12_MIC:
617 /* turn on relay */
618 new = old | SCR_RELAY;
619 set_scr(ice, new);
620 new = (new & ~SCR_AIN12_SEL1) | SCR_AIN12_SEL0;
621 set_scr(ice, new);
622 break;
623 case SCR_AIN12_LOWCUT:
624 /* turn on relay */
625 new = old | SCR_RELAY;
626 set_scr(ice, new);
627 new |= SCR_AIN12_SEL1 | SCR_AIN12_SEL0;
628 set_scr(ice, new);
629 break;
630 default:
631 snd_BUG();
632 }
633 return 1;
634 }
635 /* no change */
636 return 0;
637}
638
639static int qtet_php_get(struct snd_kcontrol *kcontrol,
640 struct snd_ctl_elem_value *ucontrol)
641{
642 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
643 unsigned int val;
644 /* if phantom voltage =48V, phantom on */
645 val = get_scr(ice) & SCR_PHP_V;
646 ucontrol->value.integer.value[0] = val ? 1 : 0;
647 return 0;
648}
649
650static int qtet_php_put(struct snd_kcontrol *kcontrol,
651 struct snd_ctl_elem_value *ucontrol)
652{
653 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
654 unsigned int old, new;
655 old = new = get_scr(ice);
656 if (ucontrol->value.integer.value[0] /* phantom on requested */
657 && (~old & SCR_PHP_V)) /* 0 = voltage 5V */ {
658 /* is off, turn on */
659 /* turn voltage on first, = 1 */
660 new = old | SCR_PHP_V;
661 set_scr(ice, new);
662 /* turn phantom on, = 0 */
663 new &= ~SCR_PHP;
664 set_scr(ice, new);
665 } else if (!ucontrol->value.integer.value[0] && (old & SCR_PHP_V)) {
666 /* phantom off requested and 1 = voltage 48V */
667 /* is on, turn off */
668 /* turn voltage off first, = 0 */
669 new = old & ~SCR_PHP_V;
670 set_scr(ice, new);
671 /* turn phantom off, = 1 */
672 new |= SCR_PHP;
673 set_scr(ice, new);
674 }
675 if (old != new)
676 return 1;
677 /* no change */
678 return 0;
679}
680
681#define PRIV_SW(xid, xbit, xreg) [xid] = {.bit = xbit,\
682 .set_register = set_##xreg,\
683 .get_register = get_##xreg, }
684
685
686#define PRIV_ENUM2(xid, xbit, xreg, xtext1, xtext2) [xid] = {.bit = xbit,\
687 .set_register = set_##xreg,\
688 .get_register = get_##xreg,\
689 .texts = {xtext1, xtext2} }
690
691static struct qtet_kcontrol_private qtet_privates[] = {
692 PRIV_ENUM2(IN12_SEL, CPLD_IN12_SEL, cpld, "An In 1/2", "An In 3/4"),
693 PRIV_ENUM2(IN34_SEL, CPLD_IN34_SEL, cpld, "An In 3/4", "IEC958 In"),
694 PRIV_ENUM2(AIN34_SEL, SCR_AIN34_SEL, scr, "Line In 3/4", "Hi-Z"),
695 PRIV_ENUM2(COAX_OUT, CPLD_COAX_OUT, cpld, "IEC958", "I2S"),
696 PRIV_SW(IN12_MON12, MCR_IN12_MON12, mcr),
697 PRIV_SW(IN12_MON34, MCR_IN12_MON34, mcr),
698 PRIV_SW(IN34_MON12, MCR_IN34_MON12, mcr),
699 PRIV_SW(IN34_MON34, MCR_IN34_MON34, mcr),
700 PRIV_SW(OUT12_MON34, MCR_OUT12_MON34, mcr),
701 PRIV_SW(OUT34_MON12, MCR_OUT34_MON12, mcr),
702};
703
704static int qtet_enum_info(struct snd_kcontrol *kcontrol,
705 struct snd_ctl_elem_info *uinfo)
706{
707 struct qtet_kcontrol_private private =
708 qtet_privates[kcontrol->private_value];
709 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
710 uinfo->count = 1;
711 uinfo->value.enumerated.items = ARRAY_SIZE(private.texts);
712
713 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
714 uinfo->value.enumerated.item =
715 uinfo->value.enumerated.items - 1;
716 strcpy(uinfo->value.enumerated.name,
717 private.texts[uinfo->value.enumerated.item]);
718
719 return 0;
720}
721
722static int qtet_sw_get(struct snd_kcontrol *kcontrol,
723 struct snd_ctl_elem_value *ucontrol)
724{
725 struct qtet_kcontrol_private private =
726 qtet_privates[kcontrol->private_value];
727 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
728 ucontrol->value.integer.value[0] =
729 (private.get_register(ice) & private.bit) ? 1 : 0;
730 return 0;
731}
732
733static int qtet_sw_put(struct snd_kcontrol *kcontrol,
734 struct snd_ctl_elem_value *ucontrol)
735{
736 struct qtet_kcontrol_private private =
737 qtet_privates[kcontrol->private_value];
738 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
739 unsigned int old, new;
740 old = private.get_register(ice);
741 if (ucontrol->value.integer.value[0])
742 new = old | private.bit;
743 else
744 new = old & ~private.bit;
745 if (old != new) {
746 private.set_register(ice, new);
747 return 1;
748 }
749 /* no change */
750 return 0;
751}
752
753#define qtet_sw_info snd_ctl_boolean_mono_info
754
755#define QTET_CONTROL(xname, xtype, xpriv) \
756 {.iface = SNDRV_CTL_ELEM_IFACE_MIXER,\
757 .name = xname,\
758 .info = qtet_##xtype##_info,\
759 .get = qtet_sw_get,\
760 .put = qtet_sw_put,\
761 .private_value = xpriv }
762
e23e7a14 763static struct snd_kcontrol_new qtet_controls[] = {
6ef80706
PH		 764 {
765 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
766 .name = "Master Playback Switch",
767 .info = qtet_sw_info,
768 .get = qtet_mute_get,
769 .put = qtet_mute_put,
770 .private_value = 0
771 },
772 {
773 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
774 .name = "Phantom Power",
775 .info = qtet_sw_info,
776 .get = qtet_php_get,
777 .put = qtet_php_put,
778 .private_value = 0
779 },
780 {
781 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
782 .name = "Analog In 1/2 Capture Switch",
783 .info = qtet_ain12_enum_info,
784 .get = qtet_ain12_sw_get,
785 .put = qtet_ain12_sw_put,
786 .private_value = 0
787 },
788 QTET_CONTROL("Analog In 3/4 Capture Switch", enum, AIN34_SEL),
789 QTET_CONTROL("PCM In 1/2 Capture Switch", enum, IN12_SEL),
790 QTET_CONTROL("PCM In 3/4 Capture Switch", enum, IN34_SEL),
791 QTET_CONTROL("Coax Output Source", enum, COAX_OUT),
792 QTET_CONTROL("Analog In 1/2 to Monitor 1/2", sw, IN12_MON12),
793 QTET_CONTROL("Analog In 1/2 to Monitor 3/4", sw, IN12_MON34),
794 QTET_CONTROL("Analog In 3/4 to Monitor 1/2", sw, IN34_MON12),
795 QTET_CONTROL("Analog In 3/4 to Monitor 3/4", sw, IN34_MON34),
796 QTET_CONTROL("Output 1/2 to Monitor 3/4", sw, OUT12_MON34),
797 QTET_CONTROL("Output 3/4 to Monitor 1/2", sw, OUT34_MON12),
798};
799
e23e7a14 800static char *slave_vols[] = {
6ef80706
PH		 801 PCM_12_PLAYBACK_VOLUME,
802 PCM_34_PLAYBACK_VOLUME,
803 NULL
804};
805
e23e7a14 806static
6ef80706
PH		 807DECLARE_TLV_DB_SCALE(qtet_master_db_scale, -6350, 50, 1);
808
e23e7a14
BP		 809static struct snd_kcontrol *ctl_find(struct snd_card *card,
810 const char *name)
6ef80706
PH		 811{
812 struct snd_ctl_elem_id sid;
813 memset(&sid, 0, sizeof(sid));
814 /* FIXME: strcpy is bad. */
815 strcpy(sid.name, name);
816 sid.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
817 return snd_ctl_find_id(card, &sid);
818}
819
e23e7a14
BP		 820static void add_slaves(struct snd_card *card,
821 struct snd_kcontrol *master, char * const *list)
6ef80706
PH		 822{
823 for (; *list; list++) {
824 struct snd_kcontrol *slave = ctl_find(card, *list);
825 if (slave)
826 snd_ctl_add_slave(master, slave);
827 }
828}
829
e23e7a14 830static int qtet_add_controls(struct snd_ice1712 *ice)
6ef80706
PH		 831{
832 struct qtet_spec *spec = ice->spec;
833 int err, i;
834 struct snd_kcontrol *vmaster;
835 err = snd_ice1712_akm4xxx_build_controls(ice);
836 if (err < 0)
837 return err;
838 for (i = 0; i < ARRAY_SIZE(qtet_controls); i++) {
839 err = snd_ctl_add(ice->card,
840 snd_ctl_new1(&qtet_controls[i], ice));
841 if (err < 0)
842 return err;
843 }
844
845 /* Create virtual master control */
846 vmaster = snd_ctl_make_virtual_master("Master Playback Volume",
847 qtet_master_db_scale);
848 if (!vmaster)
849 return -ENOMEM;
850 add_slaves(ice->card, vmaster, slave_vols);
851 err = snd_ctl_add(ice->card, vmaster);
852 if (err < 0)
853 return err;
854 /* only capture SPDIF over AK4113 */
855 err = snd_ak4113_build(spec->ak4113,
856 ice->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
857 if (err < 0)
858 return err;
859 return 0;
860}
861
862static inline int qtet_is_spdif_master(struct snd_ice1712 *ice)
863{
864 /* CPLD_SYNC_SEL: 0 = internal, 1 = external (i.e. spdif master) */
865 return (get_cpld(ice) & CPLD_SYNC_SEL) ? 1 : 0;
866}
867
868static unsigned int qtet_get_rate(struct snd_ice1712 *ice)
869{
870 int i;
871 unsigned char result;
872
873 result = get_cpld(ice) & CPLD_CKS_MASK;
874 for (i = 0; i < ARRAY_SIZE(cks_vals); i++)
875 if (cks_vals[i] == result)
876 return qtet_rates[i];
877 return 0;
878}
879
880static int get_cks_val(int rate)
881{
882 int i;
883 for (i = 0; i < ARRAY_SIZE(qtet_rates); i++)
884 if (qtet_rates[i] == rate)
885 return cks_vals[i];
886 return 0;
887}
888
889/* setting new rate */
890static void qtet_set_rate(struct snd_ice1712 *ice, unsigned int rate)
891{
892 unsigned int new;
893 unsigned char val;
894 /* switching ice1724 to external clock - supplied by ext. circuits */
895 val = inb(ICEMT1724(ice, RATE));
896 outb(val | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));
897
898 new = (get_cpld(ice) & ~CPLD_CKS_MASK) | get_cks_val(rate);
899 /* switch to internal clock, drop CPLD_SYNC_SEL */
900 new &= ~CPLD_SYNC_SEL;
6dfb5aff 901 /* dev_dbg(ice->card->dev, "QT - set_rate: old %x, new %x\n",
6ef80706
PH		 902 get_cpld(ice), new); */
903 set_cpld(ice, new);
904}
905
906static inline unsigned char qtet_set_mclk(struct snd_ice1712 *ice,
907 unsigned int rate)
908{
909 /* no change in master clock */
910 return 0;
911}
912
913/* setting clock to external - SPDIF */
914static int qtet_set_spdif_clock(struct snd_ice1712 *ice, int type)
915{
916 unsigned int old, new;
917
918 old = new = get_cpld(ice);
919 new &= ~(CPLD_CKS_MASK | CPLD_WORD_SEL);
920 switch (type) {
921 case EXT_SPDIF_TYPE:
922 new |= CPLD_EXT_SPDIF;
923 break;
924 case EXT_WORDCLOCK_1FS_TYPE:
925 new |= CPLD_EXT_WORDCLOCK_1FS;
926 break;
927 case EXT_WORDCLOCK_256FS_TYPE:
928 new |= CPLD_EXT_WORDCLOCK_256FS;
929 break;
930 default:
931 snd_BUG();
932 }
933 if (old != new) {
934 set_cpld(ice, new);
935 /* changed */
936 return 1;
937 }
938 return 0;
939}
940
941static int qtet_get_spdif_master_type(struct snd_ice1712 *ice)
942{
943 unsigned int val;
944 int result;
945 val = get_cpld(ice);
946 /* checking only rate/clock-related bits */
947 val &= (CPLD_CKS_MASK | CPLD_WORD_SEL | CPLD_SYNC_SEL);
948 if (!(val & CPLD_SYNC_SEL)) {
949 /* switched to internal clock, is not any external type */
950 result = -1;
951 } else {
952 switch (val) {
953 case (CPLD_EXT_SPDIF):
954 result = EXT_SPDIF_TYPE;
955 break;
956 case (CPLD_EXT_WORDCLOCK_1FS):
957 result = EXT_WORDCLOCK_1FS_TYPE;
958 break;
959 case (CPLD_EXT_WORDCLOCK_256FS):
960 result = EXT_WORDCLOCK_256FS_TYPE;
961 break;
962 default:
963 /* undefined combination of external clock setup */
964 snd_BUG();
965 result = 0;
966 }
967 }
968 return result;
969}
970
971/* Called when ak4113 detects change in the input SPDIF stream */
972static void qtet_ak4113_change(struct ak4113 *ak4113, unsigned char c0,
973 unsigned char c1)
974{
975 struct snd_ice1712 *ice = ak4113->change_callback_private;
976 int rate;
977 if ((qtet_get_spdif_master_type(ice) == EXT_SPDIF_TYPE) &&
978 c1) {
979 /* only for SPDIF master mode, rate was changed */
980 rate = snd_ak4113_external_rate(ak4113);
6dfb5aff 981 /* dev_dbg(ice->card->dev, "ak4113 - input rate changed to %d\n",
6ef80706
PH		 982 rate); */
983 qtet_akm_set_rate_val(ice->akm, rate);
984 }
985}
986
987/*
988 * If clock slaved to SPDIF-IN, setting runtime rate
989 * to the detected external rate
990 */
991static void qtet_spdif_in_open(struct snd_ice1712 *ice,
992 struct snd_pcm_substream *substream)
993{
994 struct qtet_spec *spec = ice->spec;
995 struct snd_pcm_runtime *runtime = substream->runtime;
996 int rate;
997
998 if (qtet_get_spdif_master_type(ice) != EXT_SPDIF_TYPE)
999 /* not external SPDIF, no rate limitation */
1000 return;
1001 /* only external SPDIF can detect incoming sample rate */
1002 rate = snd_ak4113_external_rate(spec->ak4113);
1003 if (rate >= runtime->hw.rate_min && rate <= runtime->hw.rate_max) {
1004 runtime->hw.rate_min = rate;
1005 runtime->hw.rate_max = rate;
1006 }
1007}
1008
1009/*
1010 * initialize the chip
1011 */
e23e7a14 1012static int qtet_init(struct snd_ice1712 *ice)
6ef80706
PH		 1013{
1014 static const unsigned char ak4113_init_vals[] = {
1015 /* AK4113_REG_PWRDN */ AK4113_RST | AK4113_PWN |
1016 AK4113_OCKS0 | AK4113_OCKS1,
1017 /* AK4113_REQ_FORMAT */ AK4113_DIF_I24I2S | AK4113_VTX |
1018 AK4113_DEM_OFF | AK4113_DEAU,
1019 /* AK4113_REG_IO0 */ AK4113_OPS2 | AK4113_TXE |
1020 AK4113_XTL_24_576M,
1021 /* AK4113_REG_IO1 */ AK4113_EFH_1024LRCLK | AK4113_IPS(0),
1022 /* AK4113_REG_INT0_MASK */ 0,
1023 /* AK4113_REG_INT1_MASK */ 0,
1024 /* AK4113_REG_DATDTS */ 0,
1025 };
1026 int err;
1027 struct qtet_spec *spec;
1028 struct snd_akm4xxx *ak;
1029 unsigned char val;
1030
1031 /* switching ice1724 to external clock - supplied by ext. circuits */
1032 val = inb(ICEMT1724(ice, RATE));
1033 outb(val | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));
1034
1035 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1036 if (!spec)
1037 return -ENOMEM;
1038 /* qtet is clocked by Xilinx array */
1039 ice->hw_rates = &qtet_rates_info;
1040 ice->is_spdif_master = qtet_is_spdif_master;
1041 ice->get_rate = qtet_get_rate;
1042 ice->set_rate = qtet_set_rate;
1043 ice->set_mclk = qtet_set_mclk;
1044 ice->set_spdif_clock = qtet_set_spdif_clock;
1045 ice->get_spdif_master_type = qtet_get_spdif_master_type;
1046 ice->ext_clock_names = ext_clock_names;
1047 ice->ext_clock_count = ARRAY_SIZE(ext_clock_names);
1048 /* since Qtet can detect correct SPDIF-in rate, all streams can be
1049 * limited to this specific rate */
1050 ice->spdif.ops.open = ice->pro_open = qtet_spdif_in_open;
1051 ice->spec = spec;
1052
1053 /* Mute Off */
1054 /* SCR Initialize*/
1055 /* keep codec power down first */
1056 set_scr(ice, SCR_PHP);
1057 udelay(1);
1058 /* codec power up */
1059 set_scr(ice, SCR_PHP | SCR_CODEC_PDN);
1060
1061 /* MCR Initialize */
1062 set_mcr(ice, 0);
1063
1064 /* CPLD Initialize */
1065 set_cpld(ice, 0);
1066
1067
1068 ice->num_total_dacs = 2;
1069 ice->num_total_adcs = 2;
1070
1071 ice->akm = kcalloc(2, sizeof(struct snd_akm4xxx), GFP_KERNEL);
1072 ak = ice->akm;
1073 if (!ak)
1074 return -ENOMEM;
1075 /* only one codec with two chips */
1076 ice->akm_codecs = 1;
1077 err = snd_ice1712_akm4xxx_init(ak, &akm_qtet_dac, NULL, ice);
1078 if (err < 0)
1079 return err;
1080 err = snd_ak4113_create(ice->card,
1081 qtet_ak4113_read,
1082 qtet_ak4113_write,
1083 ak4113_init_vals,
1084 ice, &spec->ak4113);
1085 if (err < 0)
1086 return err;
1087 /* callback for codecs rate setting */
1088 spec->ak4113->change_callback = qtet_ak4113_change;
1089 spec->ak4113->change_callback_private = ice;
1090 /* AK41143 in Quartet can detect external rate correctly
1091 * (i.e. check_flags = 0) */
1092 spec->ak4113->check_flags = 0;
1093
1094 proc_init(ice);
1095
1096 qtet_set_rate(ice, 44100);
1097 return 0;
1098}
1099
e23e7a14 1100static unsigned char qtet_eeprom[] = {
6ef80706
PH		 1101 [ICE_EEP2_SYSCONF] = 0x28, /* clock 256(24MHz), mpu401, 1xADC,
1102 1xDACs, SPDIF in */
1103 [ICE_EEP2_ACLINK] = 0x80, /* I2S */
1104 [ICE_EEP2_I2S] = 0x78, /* 96k, 24bit, 192k */
1105 [ICE_EEP2_SPDIF] = 0xc3, /* out-en, out-int, in, out-ext */
1106 [ICE_EEP2_GPIO_DIR] = 0x00, /* 0-7 inputs, switched to output
1107 only during output operations */
1108 [ICE_EEP2_GPIO_DIR1] = 0xff, /* 8-15 outputs */
1109 [ICE_EEP2_GPIO_DIR2] = 0x00,
1110 [ICE_EEP2_GPIO_MASK] = 0xff, /* changed only for OUT operations */
1111 [ICE_EEP2_GPIO_MASK1] = 0x00,
1112 [ICE_EEP2_GPIO_MASK2] = 0xff,
1113
1114 [ICE_EEP2_GPIO_STATE] = 0x00, /* inputs */
1115 [ICE_EEP2_GPIO_STATE1] = 0x7d, /* all 1, but GPIO_CPLD_RW
1116 and GPIO15 always zero */
1117 [ICE_EEP2_GPIO_STATE2] = 0x00, /* inputs */
1118};
1119
1120/* entry point */
e23e7a14 1121struct snd_ice1712_card_info snd_vt1724_qtet_cards[] = {
6ef80706
PH		 1122 {
1123 .subvendor = VT1724_SUBDEVICE_QTET,
1124 .name = "Infrasonic Quartet",
1125 .model = "quartet",
1126 .chip_init = qtet_init,
1127 .build_controls = qtet_add_controls,
1128 .eeprom_size = sizeof(qtet_eeprom),
1129 .eeprom_data = qtet_eeprom,
1130 },
1131 { } /* terminator */
1132};
Linux kernel - Deliverables
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