Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * ALSA driver for Intel ICH (i8x0) chipsets | |
3 | * | |
c1017a4c | 4 | * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz> |
1da177e4 LT |
5 | * |
6 | * | |
7 | * This code also contains alpha support for SiS 735 chipsets provided | |
8 | * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet | |
9 | * for SiS735, so the code is not fully functional. | |
10 | * | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
25 | ||
26 | * | |
27 | */ | |
28 | ||
6cbbfe1c | 29 | #include <linux/io.h> |
1da177e4 LT |
30 | #include <linux/delay.h> |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/init.h> | |
33 | #include <linux/pci.h> | |
34 | #include <linux/slab.h> | |
65a77217 | 35 | #include <linux/module.h> |
1da177e4 LT |
36 | #include <sound/core.h> |
37 | #include <sound/pcm.h> | |
38 | #include <sound/ac97_codec.h> | |
39 | #include <sound/info.h> | |
40 | #include <sound/initval.h> | |
41 | /* for 440MX workaround */ | |
42 | #include <asm/pgtable.h> | |
43 | #include <asm/cacheflush.h> | |
44 | ||
228cf793 | 45 | #ifdef CONFIG_KVM_GUEST |
700cc5c9 | 46 | #include <linux/kvm_para.h> |
228cf793 KO |
47 | #else |
48 | #define kvm_para_available() (0) | |
49 | #endif | |
50 | ||
c1017a4c | 51 | MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>"); |
1da177e4 LT |
52 | MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455"); |
53 | MODULE_LICENSE("GPL"); | |
54 | MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH}," | |
55 | "{Intel,82901AB-ICH0}," | |
56 | "{Intel,82801BA-ICH2}," | |
57 | "{Intel,82801CA-ICH3}," | |
58 | "{Intel,82801DB-ICH4}," | |
59 | "{Intel,ICH5}," | |
60 | "{Intel,ICH6}," | |
61 | "{Intel,ICH7}," | |
62 | "{Intel,6300ESB}," | |
c4c8ea94 | 63 | "{Intel,ESB2}," |
1da177e4 LT |
64 | "{Intel,MX440}," |
65 | "{SiS,SI7012}," | |
66 | "{NVidia,nForce Audio}," | |
67 | "{NVidia,nForce2 Audio}," | |
a2854dc5 AB |
68 | "{NVidia,nForce3 Audio}," |
69 | "{NVidia,MCP04}," | |
70 | "{NVidia,MCP501}," | |
71 | "{NVidia,CK804}," | |
72 | "{NVidia,CK8}," | |
73 | "{NVidia,CK8S}," | |
1da177e4 LT |
74 | "{AMD,AMD768}," |
75 | "{AMD,AMD8111}," | |
76 | "{ALI,M5455}}"); | |
77 | ||
b7fe4622 CL |
78 | static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */ |
79 | static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */ | |
6581f4e7 | 80 | static int ac97_clock; |
b7fe4622 | 81 | static char *ac97_quirk; |
a67ff6a5 | 82 | static bool buggy_semaphore; |
beef08a5 | 83 | static int buggy_irq = -1; /* auto-check */ |
a67ff6a5 | 84 | static bool xbox; |
a9e99660 | 85 | static int spdif_aclink = -1; |
228cf793 | 86 | static int inside_vm = -1; |
b7fe4622 CL |
87 | |
88 | module_param(index, int, 0444); | |
1da177e4 | 89 | MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard."); |
b7fe4622 | 90 | module_param(id, charp, 0444); |
1da177e4 | 91 | MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard."); |
b7fe4622 | 92 | module_param(ac97_clock, int, 0444); |
2b3b5485 | 93 | MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = whitelist + auto-detect, 1 = force autodetect)."); |
b7fe4622 | 94 | module_param(ac97_quirk, charp, 0444); |
1da177e4 | 95 | MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware."); |
b7fe4622 | 96 | module_param(buggy_semaphore, bool, 0444); |
a06147d2 | 97 | MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores."); |
69116f27 | 98 | module_param(buggy_irq, bint, 0444); |
1da177e4 | 99 | MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards."); |
b7fe4622 | 100 | module_param(xbox, bool, 0444); |
1da177e4 | 101 | MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection."); |
a9e99660 TI |
102 | module_param(spdif_aclink, int, 0444); |
103 | MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link."); | |
69116f27 | 104 | module_param(inside_vm, bint, 0444); |
228cf793 | 105 | MODULE_PARM_DESC(inside_vm, "KVM/Parallels optimization."); |
1da177e4 | 106 | |
2b3e584b | 107 | /* just for backward compatibility */ |
a67ff6a5 | 108 | static bool enable; |
698444f3 | 109 | module_param(enable, bool, 0444); |
2b3e584b TI |
110 | static int joystick; |
111 | module_param(joystick, int, 0444); | |
112 | ||
1da177e4 LT |
113 | /* |
114 | * Direct registers | |
115 | */ | |
1da177e4 LT |
116 | enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE }; |
117 | ||
118 | #define ICHREG(x) ICH_REG_##x | |
119 | ||
120 | #define DEFINE_REGSET(name,base) \ | |
121 | enum { \ | |
122 | ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \ | |
123 | ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \ | |
124 | ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \ | |
125 | ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \ | |
126 | ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \ | |
127 | ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \ | |
128 | ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \ | |
129 | }; | |
130 | ||
131 | /* busmaster blocks */ | |
132 | DEFINE_REGSET(OFF, 0); /* offset */ | |
133 | DEFINE_REGSET(PI, 0x00); /* PCM in */ | |
134 | DEFINE_REGSET(PO, 0x10); /* PCM out */ | |
135 | DEFINE_REGSET(MC, 0x20); /* Mic in */ | |
136 | ||
137 | /* ICH4 busmaster blocks */ | |
138 | DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */ | |
139 | DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */ | |
140 | DEFINE_REGSET(SP, 0x60); /* SPDIF out */ | |
141 | ||
142 | /* values for each busmaster block */ | |
143 | ||
144 | /* LVI */ | |
145 | #define ICH_REG_LVI_MASK 0x1f | |
146 | ||
147 | /* SR */ | |
148 | #define ICH_FIFOE 0x10 /* FIFO error */ | |
149 | #define ICH_BCIS 0x08 /* buffer completion interrupt status */ | |
150 | #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */ | |
151 | #define ICH_CELV 0x02 /* current equals last valid */ | |
152 | #define ICH_DCH 0x01 /* DMA controller halted */ | |
153 | ||
154 | /* PIV */ | |
155 | #define ICH_REG_PIV_MASK 0x1f /* mask */ | |
156 | ||
157 | /* CR */ | |
158 | #define ICH_IOCE 0x10 /* interrupt on completion enable */ | |
159 | #define ICH_FEIE 0x08 /* fifo error interrupt enable */ | |
160 | #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */ | |
161 | #define ICH_RESETREGS 0x02 /* reset busmaster registers */ | |
162 | #define ICH_STARTBM 0x01 /* start busmaster operation */ | |
163 | ||
164 | ||
165 | /* global block */ | |
166 | #define ICH_REG_GLOB_CNT 0x2c /* dword - global control */ | |
167 | #define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */ | |
168 | #define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */ | |
169 | #define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */ | |
170 | #define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */ | |
171 | #define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */ | |
172 | #define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */ | |
4235a317 TI |
173 | #define ICH_PCM_246_MASK 0x00300000 /* chan mask (not all chips) */ |
174 | #define ICH_PCM_8 0x00300000 /* 8 channels (not all chips) */ | |
1da177e4 LT |
175 | #define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */ |
176 | #define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */ | |
177 | #define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */ | |
178 | #define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */ | |
179 | #define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */ | |
180 | #define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */ | |
181 | #define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */ | |
182 | #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */ | |
183 | #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */ | |
184 | #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */ | |
185 | #define ICH_ACLINK 0x00000008 /* AClink shut off */ | |
186 | #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */ | |
187 | #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */ | |
188 | #define ICH_GIE 0x00000001 /* GPI interrupt enable */ | |
189 | #define ICH_REG_GLOB_STA 0x30 /* dword - global status */ | |
190 | #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */ | |
191 | #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */ | |
192 | #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */ | |
193 | #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */ | |
194 | #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */ | |
195 | #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */ | |
196 | #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */ | |
197 | #define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */ | |
198 | #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */ | |
84a43bd5 TI |
199 | #define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */ |
200 | #define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */ | |
1da177e4 LT |
201 | #define ICH_MD3 0x00020000 /* modem power down semaphore */ |
202 | #define ICH_AD3 0x00010000 /* audio power down semaphore */ | |
203 | #define ICH_RCS 0x00008000 /* read completion status */ | |
204 | #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */ | |
205 | #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */ | |
206 | #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */ | |
207 | #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */ | |
208 | #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */ | |
209 | #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */ | |
210 | #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */ | |
211 | #define ICH_MCINT 0x00000080 /* MIC capture interrupt */ | |
212 | #define ICH_POINT 0x00000040 /* playback interrupt */ | |
213 | #define ICH_PIINT 0x00000020 /* capture interrupt */ | |
214 | #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */ | |
215 | #define ICH_MOINT 0x00000004 /* modem playback interrupt */ | |
216 | #define ICH_MIINT 0x00000002 /* modem capture interrupt */ | |
217 | #define ICH_GSCI 0x00000001 /* GPI status change interrupt */ | |
218 | #define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */ | |
219 | #define ICH_CAS 0x01 /* codec access semaphore */ | |
220 | #define ICH_REG_SDM 0x80 | |
221 | #define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */ | |
222 | #define ICH_DI2L_SHIFT 6 | |
223 | #define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */ | |
224 | #define ICH_DI1L_SHIFT 4 | |
225 | #define ICH_SE 0x00000008 /* steer enable */ | |
226 | #define ICH_LDI_MASK 0x00000003 /* last codec read data input */ | |
227 | ||
228 | #define ICH_MAX_FRAGS 32 /* max hw frags */ | |
229 | ||
230 | ||
231 | /* | |
232 | * registers for Ali5455 | |
233 | */ | |
234 | ||
235 | /* ALi 5455 busmaster blocks */ | |
236 | DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */ | |
237 | DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */ | |
238 | DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */ | |
239 | DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */ | |
240 | DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */ | |
241 | DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */ | |
242 | DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */ | |
243 | DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */ | |
244 | DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */ | |
245 | DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */ | |
246 | DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */ | |
247 | ||
248 | enum { | |
249 | ICH_REG_ALI_SCR = 0x00, /* System Control Register */ | |
250 | ICH_REG_ALI_SSR = 0x04, /* System Status Register */ | |
251 | ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */ | |
252 | ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */ | |
253 | ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */ | |
254 | ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */ | |
255 | ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */ | |
256 | ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */ | |
257 | ICH_REG_ALI_CPR = 0x20, /* Command Port Register */ | |
258 | ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */ | |
259 | ICH_REG_ALI_SPR = 0x24, /* Status Port Register */ | |
260 | ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */ | |
261 | ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */ | |
262 | ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */ | |
263 | ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */ | |
264 | ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */ | |
265 | ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */ | |
266 | ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */ | |
267 | ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */ | |
268 | ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */ | |
269 | ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */ | |
270 | }; | |
271 | ||
272 | #define ALI_CAS_SEM_BUSY 0x80000000 | |
273 | #define ALI_CPR_ADDR_SECONDARY 0x100 | |
274 | #define ALI_CPR_ADDR_READ 0x80 | |
275 | #define ALI_CSPSR_CODEC_READY 0x08 | |
276 | #define ALI_CSPSR_READ_OK 0x02 | |
277 | #define ALI_CSPSR_WRITE_OK 0x01 | |
278 | ||
279 | /* interrupts for the whole chip by interrupt status register finish */ | |
280 | ||
281 | #define ALI_INT_MICIN2 (1<<26) | |
282 | #define ALI_INT_PCMIN2 (1<<25) | |
283 | #define ALI_INT_I2SIN (1<<24) | |
284 | #define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */ | |
285 | #define ALI_INT_SPDIFIN (1<<22) | |
286 | #define ALI_INT_LFEOUT (1<<21) | |
287 | #define ALI_INT_CENTEROUT (1<<20) | |
288 | #define ALI_INT_CODECSPDIFOUT (1<<19) | |
289 | #define ALI_INT_MICIN (1<<18) | |
290 | #define ALI_INT_PCMOUT (1<<17) | |
291 | #define ALI_INT_PCMIN (1<<16) | |
292 | #define ALI_INT_CPRAIS (1<<7) /* command port available */ | |
293 | #define ALI_INT_SPRAIS (1<<5) /* status port available */ | |
294 | #define ALI_INT_GPIO (1<<1) | |
6b75a9d8 TI |
295 | #define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\ |
296 | ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN) | |
1da177e4 LT |
297 | |
298 | #define ICH_ALI_SC_RESET (1<<31) /* master reset */ | |
299 | #define ICH_ALI_SC_AC97_DBL (1<<30) | |
300 | #define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */ | |
301 | #define ICH_ALI_SC_IN_BITS (3<<18) | |
302 | #define ICH_ALI_SC_OUT_BITS (3<<16) | |
303 | #define ICH_ALI_SC_6CH_CFG (3<<14) | |
304 | #define ICH_ALI_SC_PCM_4 (1<<8) | |
305 | #define ICH_ALI_SC_PCM_6 (2<<8) | |
306 | #define ICH_ALI_SC_PCM_246_MASK (3<<8) | |
307 | ||
308 | #define ICH_ALI_SS_SEC_ID (3<<5) | |
309 | #define ICH_ALI_SS_PRI_ID (3<<3) | |
310 | ||
311 | #define ICH_ALI_IF_AC97SP (1<<21) | |
312 | #define ICH_ALI_IF_MC (1<<20) | |
313 | #define ICH_ALI_IF_PI (1<<19) | |
314 | #define ICH_ALI_IF_MC2 (1<<18) | |
315 | #define ICH_ALI_IF_PI2 (1<<17) | |
316 | #define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */ | |
317 | #define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */ | |
318 | #define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */ | |
319 | #define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */ | |
320 | #define ICH_ALI_IF_PO_SPDF (1<<3) | |
321 | #define ICH_ALI_IF_PO (1<<1) | |
322 | ||
323 | /* | |
324 | * | |
325 | */ | |
326 | ||
6b75a9d8 TI |
327 | enum { |
328 | ICHD_PCMIN, | |
329 | ICHD_PCMOUT, | |
330 | ICHD_MIC, | |
331 | ICHD_MIC2, | |
332 | ICHD_PCM2IN, | |
333 | ICHD_SPBAR, | |
334 | ICHD_LAST = ICHD_SPBAR | |
335 | }; | |
336 | enum { | |
337 | NVD_PCMIN, | |
338 | NVD_PCMOUT, | |
339 | NVD_MIC, | |
340 | NVD_SPBAR, | |
341 | NVD_LAST = NVD_SPBAR | |
342 | }; | |
343 | enum { | |
344 | ALID_PCMIN, | |
345 | ALID_PCMOUT, | |
346 | ALID_MIC, | |
347 | ALID_AC97SPDIFOUT, | |
348 | ALID_SPDIFIN, | |
349 | ALID_SPDIFOUT, | |
350 | ALID_LAST = ALID_SPDIFOUT | |
351 | }; | |
1da177e4 | 352 | |
6b75a9d8 | 353 | #define get_ichdev(substream) (substream->runtime->private_data) |
1da177e4 | 354 | |
6b75a9d8 | 355 | struct ichdev { |
1da177e4 LT |
356 | unsigned int ichd; /* ich device number */ |
357 | unsigned long reg_offset; /* offset to bmaddr */ | |
358 | u32 *bdbar; /* CPU address (32bit) */ | |
359 | unsigned int bdbar_addr; /* PCI bus address (32bit) */ | |
6b75a9d8 | 360 | struct snd_pcm_substream *substream; |
1da177e4 LT |
361 | unsigned int physbuf; /* physical address (32bit) */ |
362 | unsigned int size; | |
363 | unsigned int fragsize; | |
364 | unsigned int fragsize1; | |
365 | unsigned int position; | |
366 | unsigned int pos_shift; | |
da2436a2 | 367 | unsigned int last_pos; |
1da177e4 LT |
368 | int frags; |
369 | int lvi; | |
370 | int lvi_frag; | |
371 | int civ; | |
372 | int ack; | |
373 | int ack_reload; | |
374 | unsigned int ack_bit; | |
375 | unsigned int roff_sr; | |
376 | unsigned int roff_picb; | |
377 | unsigned int int_sta_mask; /* interrupt status mask */ | |
378 | unsigned int ali_slot; /* ALI DMA slot */ | |
379 | struct ac97_pcm *pcm; | |
380 | int pcm_open_flag; | |
381 | unsigned int page_attr_changed: 1; | |
1cfe43d2 | 382 | unsigned int suspended: 1; |
6b75a9d8 | 383 | }; |
1da177e4 | 384 | |
6b75a9d8 | 385 | struct intel8x0 { |
1da177e4 LT |
386 | unsigned int device_type; |
387 | ||
388 | int irq; | |
389 | ||
3388c37e TI |
390 | void __iomem *addr; |
391 | void __iomem *bmaddr; | |
1da177e4 LT |
392 | |
393 | struct pci_dev *pci; | |
6b75a9d8 | 394 | struct snd_card *card; |
1da177e4 LT |
395 | |
396 | int pcm_devs; | |
6b75a9d8 TI |
397 | struct snd_pcm *pcm[6]; |
398 | struct ichdev ichd[6]; | |
1da177e4 LT |
399 | |
400 | unsigned multi4: 1, | |
401 | multi6: 1, | |
4235a317 | 402 | multi8 :1, |
1da177e4 LT |
403 | dra: 1, |
404 | smp20bit: 1; | |
405 | unsigned in_ac97_init: 1, | |
406 | in_sdin_init: 1; | |
407 | unsigned in_measurement: 1; /* during ac97 clock measurement */ | |
408 | unsigned fix_nocache: 1; /* workaround for 440MX */ | |
409 | unsigned buggy_irq: 1; /* workaround for buggy mobos */ | |
410 | unsigned xbox: 1; /* workaround for Xbox AC'97 detection */ | |
a06147d2 | 411 | unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */ |
228cf793 | 412 | unsigned inside_vm: 1; /* enable VM optimization */ |
1da177e4 LT |
413 | |
414 | int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */ | |
52b72388 | 415 | unsigned int sdm_saved; /* SDM reg value */ |
1da177e4 | 416 | |
6b75a9d8 TI |
417 | struct snd_ac97_bus *ac97_bus; |
418 | struct snd_ac97 *ac97[3]; | |
1da177e4 | 419 | unsigned int ac97_sdin[3]; |
84a43bd5 TI |
420 | unsigned int max_codecs, ncodecs; |
421 | unsigned int *codec_bit; | |
422 | unsigned int codec_isr_bits; | |
423 | unsigned int codec_ready_bits; | |
1da177e4 LT |
424 | |
425 | spinlock_t reg_lock; | |
426 | ||
427 | u32 bdbars_count; | |
428 | struct snd_dma_buffer bdbars; | |
429 | u32 int_sta_reg; /* interrupt status register */ | |
430 | u32 int_sta_mask; /* interrupt status mask */ | |
431 | }; | |
432 | ||
9baa3c34 | 433 | static const struct pci_device_id snd_intel8x0_ids[] = { |
28d27aae JP |
434 | { PCI_VDEVICE(INTEL, 0x2415), DEVICE_INTEL }, /* 82801AA */ |
435 | { PCI_VDEVICE(INTEL, 0x2425), DEVICE_INTEL }, /* 82901AB */ | |
436 | { PCI_VDEVICE(INTEL, 0x2445), DEVICE_INTEL }, /* 82801BA */ | |
437 | { PCI_VDEVICE(INTEL, 0x2485), DEVICE_INTEL }, /* ICH3 */ | |
438 | { PCI_VDEVICE(INTEL, 0x24c5), DEVICE_INTEL_ICH4 }, /* ICH4 */ | |
439 | { PCI_VDEVICE(INTEL, 0x24d5), DEVICE_INTEL_ICH4 }, /* ICH5 */ | |
440 | { PCI_VDEVICE(INTEL, 0x25a6), DEVICE_INTEL_ICH4 }, /* ESB */ | |
441 | { PCI_VDEVICE(INTEL, 0x266e), DEVICE_INTEL_ICH4 }, /* ICH6 */ | |
442 | { PCI_VDEVICE(INTEL, 0x27de), DEVICE_INTEL_ICH4 }, /* ICH7 */ | |
443 | { PCI_VDEVICE(INTEL, 0x2698), DEVICE_INTEL_ICH4 }, /* ESB2 */ | |
444 | { PCI_VDEVICE(INTEL, 0x7195), DEVICE_INTEL }, /* 440MX */ | |
445 | { PCI_VDEVICE(SI, 0x7012), DEVICE_SIS }, /* SI7012 */ | |
446 | { PCI_VDEVICE(NVIDIA, 0x01b1), DEVICE_NFORCE }, /* NFORCE */ | |
447 | { PCI_VDEVICE(NVIDIA, 0x003a), DEVICE_NFORCE }, /* MCP04 */ | |
448 | { PCI_VDEVICE(NVIDIA, 0x006a), DEVICE_NFORCE }, /* NFORCE2 */ | |
449 | { PCI_VDEVICE(NVIDIA, 0x0059), DEVICE_NFORCE }, /* CK804 */ | |
450 | { PCI_VDEVICE(NVIDIA, 0x008a), DEVICE_NFORCE }, /* CK8 */ | |
451 | { PCI_VDEVICE(NVIDIA, 0x00da), DEVICE_NFORCE }, /* NFORCE3 */ | |
452 | { PCI_VDEVICE(NVIDIA, 0x00ea), DEVICE_NFORCE }, /* CK8S */ | |
453 | { PCI_VDEVICE(NVIDIA, 0x026b), DEVICE_NFORCE }, /* MCP51 */ | |
454 | { PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL }, /* AMD8111 */ | |
455 | { PCI_VDEVICE(AMD, 0x7445), DEVICE_INTEL }, /* AMD768 */ | |
456 | { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI }, /* Ali5455 */ | |
1da177e4 LT |
457 | { 0, } |
458 | }; | |
459 | ||
460 | MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids); | |
461 | ||
462 | /* | |
463 | * Lowlevel I/O - busmaster | |
464 | */ | |
465 | ||
3388c37e | 466 | static inline u8 igetbyte(struct intel8x0 *chip, u32 offset) |
1da177e4 | 467 | { |
3388c37e | 468 | return ioread8(chip->bmaddr + offset); |
1da177e4 LT |
469 | } |
470 | ||
3388c37e | 471 | static inline u16 igetword(struct intel8x0 *chip, u32 offset) |
1da177e4 | 472 | { |
3388c37e | 473 | return ioread16(chip->bmaddr + offset); |
1da177e4 LT |
474 | } |
475 | ||
3388c37e | 476 | static inline u32 igetdword(struct intel8x0 *chip, u32 offset) |
1da177e4 | 477 | { |
3388c37e | 478 | return ioread32(chip->bmaddr + offset); |
1da177e4 LT |
479 | } |
480 | ||
3388c37e | 481 | static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val) |
1da177e4 | 482 | { |
3388c37e | 483 | iowrite8(val, chip->bmaddr + offset); |
1da177e4 LT |
484 | } |
485 | ||
3388c37e | 486 | static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val) |
1da177e4 | 487 | { |
3388c37e | 488 | iowrite16(val, chip->bmaddr + offset); |
1da177e4 LT |
489 | } |
490 | ||
3388c37e | 491 | static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val) |
1da177e4 | 492 | { |
3388c37e | 493 | iowrite32(val, chip->bmaddr + offset); |
1da177e4 LT |
494 | } |
495 | ||
496 | /* | |
497 | * Lowlevel I/O - AC'97 registers | |
498 | */ | |
499 | ||
3388c37e | 500 | static inline u16 iagetword(struct intel8x0 *chip, u32 offset) |
1da177e4 | 501 | { |
3388c37e | 502 | return ioread16(chip->addr + offset); |
1da177e4 LT |
503 | } |
504 | ||
3388c37e | 505 | static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val) |
1da177e4 | 506 | { |
3388c37e | 507 | iowrite16(val, chip->addr + offset); |
1da177e4 LT |
508 | } |
509 | ||
510 | /* | |
511 | * Basic I/O | |
512 | */ | |
513 | ||
514 | /* | |
515 | * access to AC97 codec via normal i/o (for ICH and SIS7012) | |
516 | */ | |
517 | ||
6b75a9d8 | 518 | static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec) |
1da177e4 LT |
519 | { |
520 | int time; | |
521 | ||
522 | if (codec > 2) | |
523 | return -EIO; | |
524 | if (chip->in_sdin_init) { | |
525 | /* we don't know the ready bit assignment at the moment */ | |
526 | /* so we check any */ | |
84a43bd5 | 527 | codec = chip->codec_isr_bits; |
1da177e4 | 528 | } else { |
84a43bd5 | 529 | codec = chip->codec_bit[chip->ac97_sdin[codec]]; |
1da177e4 LT |
530 | } |
531 | ||
532 | /* codec ready ? */ | |
533 | if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0) | |
534 | return -EIO; | |
535 | ||
a06147d2 TI |
536 | if (chip->buggy_semaphore) |
537 | return 0; /* just ignore ... */ | |
538 | ||
1da177e4 LT |
539 | /* Anyone holding a semaphore for 1 msec should be shot... */ |
540 | time = 100; | |
541 | do { | |
542 | if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS)) | |
543 | return 0; | |
544 | udelay(10); | |
545 | } while (time--); | |
546 | ||
25985edc | 547 | /* access to some forbidden (non existent) ac97 registers will not |
1da177e4 LT |
548 | * reset the semaphore. So even if you don't get the semaphore, still |
549 | * continue the access. We don't need the semaphore anyway. */ | |
f493e7bc TI |
550 | dev_err(chip->card->dev, |
551 | "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n", | |
1da177e4 LT |
552 | igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA))); |
553 | iagetword(chip, 0); /* clear semaphore flag */ | |
554 | /* I don't care about the semaphore */ | |
555 | return -EBUSY; | |
556 | } | |
557 | ||
6b75a9d8 | 558 | static void snd_intel8x0_codec_write(struct snd_ac97 *ac97, |
1da177e4 LT |
559 | unsigned short reg, |
560 | unsigned short val) | |
561 | { | |
6b75a9d8 | 562 | struct intel8x0 *chip = ac97->private_data; |
1da177e4 LT |
563 | |
564 | if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) { | |
565 | if (! chip->in_ac97_init) | |
f493e7bc TI |
566 | dev_err(chip->card->dev, |
567 | "codec_write %d: semaphore is not ready for register 0x%x\n", | |
568 | ac97->num, reg); | |
1da177e4 LT |
569 | } |
570 | iaputword(chip, reg + ac97->num * 0x80, val); | |
571 | } | |
572 | ||
6b75a9d8 | 573 | static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97, |
1da177e4 LT |
574 | unsigned short reg) |
575 | { | |
6b75a9d8 | 576 | struct intel8x0 *chip = ac97->private_data; |
1da177e4 LT |
577 | unsigned short res; |
578 | unsigned int tmp; | |
579 | ||
580 | if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) { | |
581 | if (! chip->in_ac97_init) | |
f493e7bc TI |
582 | dev_err(chip->card->dev, |
583 | "codec_read %d: semaphore is not ready for register 0x%x\n", | |
584 | ac97->num, reg); | |
1da177e4 LT |
585 | res = 0xffff; |
586 | } else { | |
587 | res = iagetword(chip, reg + ac97->num * 0x80); | |
588 | if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) { | |
589 | /* reset RCS and preserve other R/WC bits */ | |
6b75a9d8 | 590 | iputdword(chip, ICHREG(GLOB_STA), tmp & |
84a43bd5 | 591 | ~(chip->codec_ready_bits | ICH_GSCI)); |
1da177e4 | 592 | if (! chip->in_ac97_init) |
f493e7bc TI |
593 | dev_err(chip->card->dev, |
594 | "codec_read %d: read timeout for register 0x%x\n", | |
595 | ac97->num, reg); | |
1da177e4 LT |
596 | res = 0xffff; |
597 | } | |
598 | } | |
599 | return res; | |
600 | } | |
601 | ||
e23e7a14 BP |
602 | static void snd_intel8x0_codec_read_test(struct intel8x0 *chip, |
603 | unsigned int codec) | |
1da177e4 LT |
604 | { |
605 | unsigned int tmp; | |
606 | ||
607 | if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) { | |
608 | iagetword(chip, codec * 0x80); | |
609 | if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) { | |
610 | /* reset RCS and preserve other R/WC bits */ | |
6b75a9d8 | 611 | iputdword(chip, ICHREG(GLOB_STA), tmp & |
84a43bd5 | 612 | ~(chip->codec_ready_bits | ICH_GSCI)); |
1da177e4 LT |
613 | } |
614 | } | |
615 | } | |
616 | ||
617 | /* | |
618 | * access to AC97 for Ali5455 | |
619 | */ | |
6b75a9d8 | 620 | static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask) |
1da177e4 LT |
621 | { |
622 | int count = 0; | |
623 | for (count = 0; count < 0x7f; count++) { | |
624 | int val = igetbyte(chip, ICHREG(ALI_CSPSR)); | |
625 | if (val & mask) | |
626 | return 0; | |
627 | } | |
79ba34b9 | 628 | if (! chip->in_ac97_init) |
f493e7bc | 629 | dev_warn(chip->card->dev, "AC97 codec ready timeout.\n"); |
1da177e4 LT |
630 | return -EBUSY; |
631 | } | |
632 | ||
6b75a9d8 | 633 | static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip) |
1da177e4 LT |
634 | { |
635 | int time = 100; | |
79ba34b9 TI |
636 | if (chip->buggy_semaphore) |
637 | return 0; /* just ignore ... */ | |
67d8a3c1 | 638 | while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY)) |
1da177e4 | 639 | udelay(1); |
79ba34b9 | 640 | if (! time && ! chip->in_ac97_init) |
f493e7bc | 641 | dev_warn(chip->card->dev, "ali_codec_semaphore timeout\n"); |
1da177e4 LT |
642 | return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY); |
643 | } | |
644 | ||
6b75a9d8 | 645 | static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg) |
1da177e4 | 646 | { |
6b75a9d8 | 647 | struct intel8x0 *chip = ac97->private_data; |
1da177e4 LT |
648 | unsigned short data = 0xffff; |
649 | ||
650 | if (snd_intel8x0_ali_codec_semaphore(chip)) | |
651 | goto __err; | |
652 | reg |= ALI_CPR_ADDR_READ; | |
653 | if (ac97->num) | |
654 | reg |= ALI_CPR_ADDR_SECONDARY; | |
655 | iputword(chip, ICHREG(ALI_CPR_ADDR), reg); | |
656 | if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK)) | |
657 | goto __err; | |
658 | data = igetword(chip, ICHREG(ALI_SPR)); | |
659 | __err: | |
660 | return data; | |
661 | } | |
662 | ||
6b75a9d8 TI |
663 | static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg, |
664 | unsigned short val) | |
1da177e4 | 665 | { |
6b75a9d8 | 666 | struct intel8x0 *chip = ac97->private_data; |
1da177e4 LT |
667 | |
668 | if (snd_intel8x0_ali_codec_semaphore(chip)) | |
669 | return; | |
670 | iputword(chip, ICHREG(ALI_CPR), val); | |
671 | if (ac97->num) | |
672 | reg |= ALI_CPR_ADDR_SECONDARY; | |
673 | iputword(chip, ICHREG(ALI_CPR_ADDR), reg); | |
674 | snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK); | |
675 | } | |
676 | ||
677 | ||
678 | /* | |
679 | * DMA I/O | |
680 | */ | |
6b75a9d8 | 681 | static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev) |
1da177e4 LT |
682 | { |
683 | int idx; | |
684 | u32 *bdbar = ichdev->bdbar; | |
685 | unsigned long port = ichdev->reg_offset; | |
686 | ||
687 | iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr); | |
688 | if (ichdev->size == ichdev->fragsize) { | |
689 | ichdev->ack_reload = ichdev->ack = 2; | |
690 | ichdev->fragsize1 = ichdev->fragsize >> 1; | |
691 | for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) { | |
692 | bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf); | |
693 | bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ | |
694 | ichdev->fragsize1 >> ichdev->pos_shift); | |
695 | bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1)); | |
696 | bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */ | |
697 | ichdev->fragsize1 >> ichdev->pos_shift); | |
698 | } | |
699 | ichdev->frags = 2; | |
700 | } else { | |
701 | ichdev->ack_reload = ichdev->ack = 1; | |
702 | ichdev->fragsize1 = ichdev->fragsize; | |
703 | for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) { | |
6b75a9d8 TI |
704 | bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + |
705 | (((idx >> 1) * ichdev->fragsize) % | |
706 | ichdev->size)); | |
1da177e4 LT |
707 | bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ |
708 | ichdev->fragsize >> ichdev->pos_shift); | |
6b75a9d8 | 709 | #if 0 |
f493e7bc | 710 | dev_dbg(chip->card->dev, "bdbar[%i] = 0x%x [0x%x]\n", |
6b75a9d8 TI |
711 | idx + 0, bdbar[idx + 0], bdbar[idx + 1]); |
712 | #endif | |
1da177e4 LT |
713 | } |
714 | ichdev->frags = ichdev->size / ichdev->fragsize; | |
715 | } | |
716 | iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK); | |
717 | ichdev->civ = 0; | |
718 | iputbyte(chip, port + ICH_REG_OFF_CIV, 0); | |
719 | ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags; | |
720 | ichdev->position = 0; | |
721 | #if 0 | |
f493e7bc TI |
722 | dev_dbg(chip->card->dev, |
723 | "lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n", | |
14ab0861 TI |
724 | ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, |
725 | ichdev->fragsize1); | |
1da177e4 LT |
726 | #endif |
727 | /* clear interrupts */ | |
728 | iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); | |
729 | } | |
730 | ||
731 | #ifdef __i386__ | |
732 | /* | |
733 | * Intel 82443MX running a 100MHz processor system bus has a hardware bug, | |
734 | * which aborts PCI busmaster for audio transfer. A workaround is to set | |
735 | * the pages as non-cached. For details, see the errata in | |
631dd1a8 | 736 | * http://download.intel.com/design/chipsets/specupdt/24505108.pdf |
1da177e4 LT |
737 | */ |
738 | static void fill_nocache(void *buf, int size, int nocache) | |
739 | { | |
740 | size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT; | |
6d238cc4 AV |
741 | if (nocache) |
742 | set_pages_uc(virt_to_page(buf), size); | |
743 | else | |
744 | set_pages_wb(virt_to_page(buf), size); | |
1da177e4 LT |
745 | } |
746 | #else | |
6d238cc4 | 747 | #define fill_nocache(buf, size, nocache) do { ; } while (0) |
1da177e4 LT |
748 | #endif |
749 | ||
750 | /* | |
751 | * Interrupt handler | |
752 | */ | |
753 | ||
6b75a9d8 | 754 | static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev) |
1da177e4 LT |
755 | { |
756 | unsigned long port = ichdev->reg_offset; | |
883be793 | 757 | unsigned long flags; |
1da177e4 LT |
758 | int status, civ, i, step; |
759 | int ack = 0; | |
760 | ||
883be793 | 761 | spin_lock_irqsave(&chip->reg_lock, flags); |
1da177e4 LT |
762 | status = igetbyte(chip, port + ichdev->roff_sr); |
763 | civ = igetbyte(chip, port + ICH_REG_OFF_CIV); | |
764 | if (!(status & ICH_BCIS)) { | |
765 | step = 0; | |
766 | } else if (civ == ichdev->civ) { | |
767 | // snd_printd("civ same %d\n", civ); | |
768 | step = 1; | |
769 | ichdev->civ++; | |
770 | ichdev->civ &= ICH_REG_LVI_MASK; | |
771 | } else { | |
772 | step = civ - ichdev->civ; | |
773 | if (step < 0) | |
774 | step += ICH_REG_LVI_MASK + 1; | |
775 | // if (step != 1) | |
776 | // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ); | |
777 | ichdev->civ = civ; | |
778 | } | |
779 | ||
780 | ichdev->position += step * ichdev->fragsize1; | |
781 | if (! chip->in_measurement) | |
782 | ichdev->position %= ichdev->size; | |
783 | ichdev->lvi += step; | |
784 | ichdev->lvi &= ICH_REG_LVI_MASK; | |
785 | iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi); | |
786 | for (i = 0; i < step; i++) { | |
787 | ichdev->lvi_frag++; | |
788 | ichdev->lvi_frag %= ichdev->frags; | |
789 | ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1); | |
6b75a9d8 | 790 | #if 0 |
f493e7bc TI |
791 | dev_dbg(chip->card->dev, |
792 | "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", | |
6b75a9d8 TI |
793 | ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], |
794 | ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), | |
795 | inl(port + 4), inb(port + ICH_REG_OFF_CR)); | |
796 | #endif | |
1da177e4 LT |
797 | if (--ichdev->ack == 0) { |
798 | ichdev->ack = ichdev->ack_reload; | |
799 | ack = 1; | |
800 | } | |
801 | } | |
883be793 | 802 | spin_unlock_irqrestore(&chip->reg_lock, flags); |
1da177e4 LT |
803 | if (ack && ichdev->substream) { |
804 | snd_pcm_period_elapsed(ichdev->substream); | |
805 | } | |
806 | iputbyte(chip, port + ichdev->roff_sr, | |
807 | status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI)); | |
808 | } | |
809 | ||
7d12e780 | 810 | static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id) |
1da177e4 | 811 | { |
6b75a9d8 TI |
812 | struct intel8x0 *chip = dev_id; |
813 | struct ichdev *ichdev; | |
1da177e4 LT |
814 | unsigned int status; |
815 | unsigned int i; | |
816 | ||
817 | status = igetdword(chip, chip->int_sta_reg); | |
818 | if (status == 0xffffffff) /* we are not yet resumed */ | |
819 | return IRQ_NONE; | |
820 | ||
821 | if ((status & chip->int_sta_mask) == 0) { | |
822 | if (status) { | |
823 | /* ack */ | |
824 | iputdword(chip, chip->int_sta_reg, status); | |
825 | if (! chip->buggy_irq) | |
826 | status = 0; | |
827 | } | |
828 | return IRQ_RETVAL(status); | |
829 | } | |
830 | ||
831 | for (i = 0; i < chip->bdbars_count; i++) { | |
832 | ichdev = &chip->ichd[i]; | |
833 | if (status & ichdev->int_sta_mask) | |
834 | snd_intel8x0_update(chip, ichdev); | |
835 | } | |
836 | ||
837 | /* ack them */ | |
838 | iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask); | |
839 | ||
840 | return IRQ_HANDLED; | |
841 | } | |
842 | ||
843 | /* | |
844 | * PCM part | |
845 | */ | |
846 | ||
6b75a9d8 | 847 | static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd) |
1da177e4 | 848 | { |
6b75a9d8 TI |
849 | struct intel8x0 *chip = snd_pcm_substream_chip(substream); |
850 | struct ichdev *ichdev = get_ichdev(substream); | |
1da177e4 LT |
851 | unsigned char val = 0; |
852 | unsigned long port = ichdev->reg_offset; | |
853 | ||
854 | switch (cmd) { | |
1da177e4 | 855 | case SNDRV_PCM_TRIGGER_RESUME: |
1cfe43d2 TI |
856 | ichdev->suspended = 0; |
857 | /* fallthru */ | |
858 | case SNDRV_PCM_TRIGGER_START: | |
da2436a2 | 859 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
1da177e4 | 860 | val = ICH_IOCE | ICH_STARTBM; |
da2436a2 | 861 | ichdev->last_pos = ichdev->position; |
1da177e4 | 862 | break; |
1da177e4 | 863 | case SNDRV_PCM_TRIGGER_SUSPEND: |
1cfe43d2 TI |
864 | ichdev->suspended = 1; |
865 | /* fallthru */ | |
866 | case SNDRV_PCM_TRIGGER_STOP: | |
1da177e4 LT |
867 | val = 0; |
868 | break; | |
869 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
870 | val = ICH_IOCE; | |
871 | break; | |
1da177e4 LT |
872 | default: |
873 | return -EINVAL; | |
874 | } | |
875 | iputbyte(chip, port + ICH_REG_OFF_CR, val); | |
876 | if (cmd == SNDRV_PCM_TRIGGER_STOP) { | |
877 | /* wait until DMA stopped */ | |
878 | while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ; | |
879 | /* reset whole DMA things */ | |
880 | iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); | |
881 | } | |
882 | return 0; | |
883 | } | |
884 | ||
6b75a9d8 | 885 | static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd) |
1da177e4 | 886 | { |
6b75a9d8 TI |
887 | struct intel8x0 *chip = snd_pcm_substream_chip(substream); |
888 | struct ichdev *ichdev = get_ichdev(substream); | |
1da177e4 | 889 | unsigned long port = ichdev->reg_offset; |
6b75a9d8 TI |
890 | static int fiforeg[] = { |
891 | ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3) | |
892 | }; | |
1da177e4 LT |
893 | unsigned int val, fifo; |
894 | ||
895 | val = igetdword(chip, ICHREG(ALI_DMACR)); | |
896 | switch (cmd) { | |
1cfe43d2 TI |
897 | case SNDRV_PCM_TRIGGER_RESUME: |
898 | ichdev->suspended = 0; | |
899 | /* fallthru */ | |
1da177e4 LT |
900 | case SNDRV_PCM_TRIGGER_START: |
901 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
1da177e4 LT |
902 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
903 | /* clear FIFO for synchronization of channels */ | |
904 | fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]); | |
905 | fifo &= ~(0xff << (ichdev->ali_slot % 4)); | |
906 | fifo |= 0x83 << (ichdev->ali_slot % 4); | |
907 | iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo); | |
908 | } | |
909 | iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE); | |
910 | val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */ | |
6b75a9d8 TI |
911 | /* start DMA */ |
912 | iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot)); | |
1da177e4 | 913 | break; |
1cfe43d2 TI |
914 | case SNDRV_PCM_TRIGGER_SUSPEND: |
915 | ichdev->suspended = 1; | |
916 | /* fallthru */ | |
1da177e4 LT |
917 | case SNDRV_PCM_TRIGGER_STOP: |
918 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
6b75a9d8 TI |
919 | /* pause */ |
920 | iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16))); | |
1da177e4 LT |
921 | iputbyte(chip, port + ICH_REG_OFF_CR, 0); |
922 | while (igetbyte(chip, port + ICH_REG_OFF_CR)) | |
923 | ; | |
924 | if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) | |
925 | break; | |
926 | /* reset whole DMA things */ | |
927 | iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); | |
928 | /* clear interrupts */ | |
6b75a9d8 TI |
929 | iputbyte(chip, port + ICH_REG_OFF_SR, |
930 | igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e); | |
1da177e4 LT |
931 | iputdword(chip, ICHREG(ALI_INTERRUPTSR), |
932 | igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask); | |
933 | break; | |
934 | default: | |
935 | return -EINVAL; | |
936 | } | |
937 | return 0; | |
938 | } | |
939 | ||
6b75a9d8 TI |
940 | static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream, |
941 | struct snd_pcm_hw_params *hw_params) | |
1da177e4 | 942 | { |
6b75a9d8 TI |
943 | struct intel8x0 *chip = snd_pcm_substream_chip(substream); |
944 | struct ichdev *ichdev = get_ichdev(substream); | |
945 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
946 | int dbl = params_rate(hw_params) > 48000; |
947 | int err; | |
948 | ||
949 | if (chip->fix_nocache && ichdev->page_attr_changed) { | |
950 | fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */ | |
951 | ichdev->page_attr_changed = 0; | |
952 | } | |
953 | err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); | |
954 | if (err < 0) | |
955 | return err; | |
956 | if (chip->fix_nocache) { | |
957 | if (runtime->dma_area && ! ichdev->page_attr_changed) { | |
958 | fill_nocache(runtime->dma_area, runtime->dma_bytes, 1); | |
959 | ichdev->page_attr_changed = 1; | |
960 | } | |
961 | } | |
962 | if (ichdev->pcm_open_flag) { | |
963 | snd_ac97_pcm_close(ichdev->pcm); | |
964 | ichdev->pcm_open_flag = 0; | |
965 | } | |
966 | err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params), | |
967 | params_channels(hw_params), | |
968 | ichdev->pcm->r[dbl].slots); | |
969 | if (err >= 0) { | |
970 | ichdev->pcm_open_flag = 1; | |
971 | /* Force SPDIF setting */ | |
972 | if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0) | |
6b75a9d8 TI |
973 | snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF, |
974 | params_rate(hw_params)); | |
1da177e4 LT |
975 | } |
976 | return err; | |
977 | } | |
978 | ||
6b75a9d8 | 979 | static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream) |
1da177e4 | 980 | { |
6b75a9d8 TI |
981 | struct intel8x0 *chip = snd_pcm_substream_chip(substream); |
982 | struct ichdev *ichdev = get_ichdev(substream); | |
1da177e4 LT |
983 | |
984 | if (ichdev->pcm_open_flag) { | |
985 | snd_ac97_pcm_close(ichdev->pcm); | |
986 | ichdev->pcm_open_flag = 0; | |
987 | } | |
988 | if (chip->fix_nocache && ichdev->page_attr_changed) { | |
989 | fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0); | |
990 | ichdev->page_attr_changed = 0; | |
991 | } | |
992 | return snd_pcm_lib_free_pages(substream); | |
993 | } | |
994 | ||
6b75a9d8 TI |
995 | static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip, |
996 | struct snd_pcm_runtime *runtime) | |
1da177e4 LT |
997 | { |
998 | unsigned int cnt; | |
999 | int dbl = runtime->rate > 48000; | |
1cfe43d2 TI |
1000 | |
1001 | spin_lock_irq(&chip->reg_lock); | |
1da177e4 LT |
1002 | switch (chip->device_type) { |
1003 | case DEVICE_ALI: | |
1004 | cnt = igetdword(chip, ICHREG(ALI_SCR)); | |
1005 | cnt &= ~ICH_ALI_SC_PCM_246_MASK; | |
1006 | if (runtime->channels == 4 || dbl) | |
1007 | cnt |= ICH_ALI_SC_PCM_4; | |
1008 | else if (runtime->channels == 6) | |
1009 | cnt |= ICH_ALI_SC_PCM_6; | |
1010 | iputdword(chip, ICHREG(ALI_SCR), cnt); | |
1011 | break; | |
1012 | case DEVICE_SIS: | |
1013 | cnt = igetdword(chip, ICHREG(GLOB_CNT)); | |
1014 | cnt &= ~ICH_SIS_PCM_246_MASK; | |
1015 | if (runtime->channels == 4 || dbl) | |
1016 | cnt |= ICH_SIS_PCM_4; | |
1017 | else if (runtime->channels == 6) | |
1018 | cnt |= ICH_SIS_PCM_6; | |
1019 | iputdword(chip, ICHREG(GLOB_CNT), cnt); | |
1020 | break; | |
1021 | default: | |
1022 | cnt = igetdword(chip, ICHREG(GLOB_CNT)); | |
1023 | cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT); | |
1024 | if (runtime->channels == 4 || dbl) | |
1025 | cnt |= ICH_PCM_4; | |
1026 | else if (runtime->channels == 6) | |
1027 | cnt |= ICH_PCM_6; | |
4235a317 TI |
1028 | else if (runtime->channels == 8) |
1029 | cnt |= ICH_PCM_8; | |
1da177e4 LT |
1030 | if (chip->device_type == DEVICE_NFORCE) { |
1031 | /* reset to 2ch once to keep the 6 channel data in alignment, | |
1032 | * to start from Front Left always | |
1033 | */ | |
1034 | if (cnt & ICH_PCM_246_MASK) { | |
1035 | iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK); | |
1036 | spin_unlock_irq(&chip->reg_lock); | |
1037 | msleep(50); /* grrr... */ | |
1038 | spin_lock_irq(&chip->reg_lock); | |
1039 | } | |
1040 | } else if (chip->device_type == DEVICE_INTEL_ICH4) { | |
1041 | if (runtime->sample_bits > 16) | |
1042 | cnt |= ICH_PCM_20BIT; | |
1043 | } | |
1044 | iputdword(chip, ICHREG(GLOB_CNT), cnt); | |
1045 | break; | |
1046 | } | |
1cfe43d2 | 1047 | spin_unlock_irq(&chip->reg_lock); |
1da177e4 LT |
1048 | } |
1049 | ||
6b75a9d8 | 1050 | static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 1051 | { |
6b75a9d8 TI |
1052 | struct intel8x0 *chip = snd_pcm_substream_chip(substream); |
1053 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1054 | struct ichdev *ichdev = get_ichdev(substream); | |
1da177e4 LT |
1055 | |
1056 | ichdev->physbuf = runtime->dma_addr; | |
1057 | ichdev->size = snd_pcm_lib_buffer_bytes(substream); | |
1058 | ichdev->fragsize = snd_pcm_lib_period_bytes(substream); | |
1da177e4 LT |
1059 | if (ichdev->ichd == ICHD_PCMOUT) { |
1060 | snd_intel8x0_setup_pcm_out(chip, runtime); | |
1cfe43d2 | 1061 | if (chip->device_type == DEVICE_INTEL_ICH4) |
1da177e4 | 1062 | ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1; |
1da177e4 LT |
1063 | } |
1064 | snd_intel8x0_setup_periods(chip, ichdev); | |
1da177e4 LT |
1065 | return 0; |
1066 | } | |
1067 | ||
6b75a9d8 | 1068 | static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 1069 | { |
6b75a9d8 TI |
1070 | struct intel8x0 *chip = snd_pcm_substream_chip(substream); |
1071 | struct ichdev *ichdev = get_ichdev(substream); | |
1da177e4 | 1072 | size_t ptr1, ptr; |
da2436a2 | 1073 | int civ, timeout = 10; |
1da177e4 LT |
1074 | unsigned int position; |
1075 | ||
1076 | spin_lock(&chip->reg_lock); | |
1077 | do { | |
1078 | civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV); | |
1079 | ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb); | |
1080 | position = ichdev->position; | |
1081 | if (ptr1 == 0) { | |
1082 | udelay(10); | |
1083 | continue; | |
1084 | } | |
228cf793 KO |
1085 | if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV)) |
1086 | continue; | |
5a9a5179 DL |
1087 | |
1088 | /* IO read operation is very expensive inside virtual machine | |
1089 | * as it is emulated. The probability that subsequent PICB read | |
1090 | * will return different result is high enough to loop till | |
1091 | * timeout here. | |
1092 | * Same CIV is strict enough condition to be sure that PICB | |
1093 | * is valid inside VM on emulated card. */ | |
228cf793 KO |
1094 | if (chip->inside_vm) |
1095 | break; | |
1096 | if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb)) | |
1da177e4 LT |
1097 | break; |
1098 | } while (timeout--); | |
f708eb1d | 1099 | ptr = ichdev->last_pos; |
da2436a2 JK |
1100 | if (ptr1 != 0) { |
1101 | ptr1 <<= ichdev->pos_shift; | |
1102 | ptr = ichdev->fragsize1 - ptr1; | |
1103 | ptr += position; | |
f708eb1d TI |
1104 | if (ptr < ichdev->last_pos) { |
1105 | unsigned int pos_base, last_base; | |
1106 | pos_base = position / ichdev->fragsize1; | |
1107 | last_base = ichdev->last_pos / ichdev->fragsize1; | |
1108 | /* another sanity check; ptr1 can go back to full | |
1109 | * before the base position is updated | |
1110 | */ | |
1111 | if (pos_base == last_base) | |
1112 | ptr = ichdev->last_pos; | |
1113 | } | |
da2436a2 | 1114 | } |
f708eb1d | 1115 | ichdev->last_pos = ptr; |
1da177e4 LT |
1116 | spin_unlock(&chip->reg_lock); |
1117 | if (ptr >= ichdev->size) | |
1118 | return 0; | |
1119 | return bytes_to_frames(substream->runtime, ptr); | |
1120 | } | |
1121 | ||
6b75a9d8 | 1122 | static struct snd_pcm_hardware snd_intel8x0_stream = |
1da177e4 LT |
1123 | { |
1124 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | | |
1125 | SNDRV_PCM_INFO_BLOCK_TRANSFER | | |
1126 | SNDRV_PCM_INFO_MMAP_VALID | | |
1127 | SNDRV_PCM_INFO_PAUSE | | |
1128 | SNDRV_PCM_INFO_RESUME), | |
1129 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
1130 | .rates = SNDRV_PCM_RATE_48000, | |
1131 | .rate_min = 48000, | |
1132 | .rate_max = 48000, | |
1133 | .channels_min = 2, | |
1134 | .channels_max = 2, | |
1135 | .buffer_bytes_max = 128 * 1024, | |
1136 | .period_bytes_min = 32, | |
1137 | .period_bytes_max = 128 * 1024, | |
1138 | .periods_min = 1, | |
1139 | .periods_max = 1024, | |
1140 | .fifo_size = 0, | |
1141 | }; | |
1142 | ||
1143 | static unsigned int channels4[] = { | |
1144 | 2, 4, | |
1145 | }; | |
1146 | ||
6b75a9d8 | 1147 | static struct snd_pcm_hw_constraint_list hw_constraints_channels4 = { |
1da177e4 LT |
1148 | .count = ARRAY_SIZE(channels4), |
1149 | .list = channels4, | |
1150 | .mask = 0, | |
1151 | }; | |
1152 | ||
1153 | static unsigned int channels6[] = { | |
1154 | 2, 4, 6, | |
1155 | }; | |
1156 | ||
6b75a9d8 | 1157 | static struct snd_pcm_hw_constraint_list hw_constraints_channels6 = { |
1da177e4 LT |
1158 | .count = ARRAY_SIZE(channels6), |
1159 | .list = channels6, | |
1160 | .mask = 0, | |
1161 | }; | |
1162 | ||
4235a317 TI |
1163 | static unsigned int channels8[] = { |
1164 | 2, 4, 6, 8, | |
1165 | }; | |
1166 | ||
1167 | static struct snd_pcm_hw_constraint_list hw_constraints_channels8 = { | |
1168 | .count = ARRAY_SIZE(channels8), | |
1169 | .list = channels8, | |
1170 | .mask = 0, | |
1171 | }; | |
1172 | ||
6b75a9d8 | 1173 | static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev) |
1da177e4 | 1174 | { |
6b75a9d8 TI |
1175 | struct intel8x0 *chip = snd_pcm_substream_chip(substream); |
1176 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
1177 | int err; |
1178 | ||
1179 | ichdev->substream = substream; | |
1180 | runtime->hw = snd_intel8x0_stream; | |
1181 | runtime->hw.rates = ichdev->pcm->rates; | |
1182 | snd_pcm_limit_hw_rates(runtime); | |
1183 | if (chip->device_type == DEVICE_SIS) { | |
1184 | runtime->hw.buffer_bytes_max = 64*1024; | |
1185 | runtime->hw.period_bytes_max = 64*1024; | |
1186 | } | |
1187 | if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0) | |
1188 | return err; | |
1189 | runtime->private_data = ichdev; | |
1190 | return 0; | |
1191 | } | |
1192 | ||
6b75a9d8 | 1193 | static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream) |
1da177e4 | 1194 | { |
6b75a9d8 TI |
1195 | struct intel8x0 *chip = snd_pcm_substream_chip(substream); |
1196 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
1197 | int err; |
1198 | ||
1199 | err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]); | |
1200 | if (err < 0) | |
1201 | return err; | |
1202 | ||
4235a317 TI |
1203 | if (chip->multi8) { |
1204 | runtime->hw.channels_max = 8; | |
1205 | snd_pcm_hw_constraint_list(runtime, 0, | |
1206 | SNDRV_PCM_HW_PARAM_CHANNELS, | |
1207 | &hw_constraints_channels8); | |
1208 | } else if (chip->multi6) { | |
1da177e4 | 1209 | runtime->hw.channels_max = 6; |
6b75a9d8 TI |
1210 | snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, |
1211 | &hw_constraints_channels6); | |
1da177e4 LT |
1212 | } else if (chip->multi4) { |
1213 | runtime->hw.channels_max = 4; | |
6b75a9d8 TI |
1214 | snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, |
1215 | &hw_constraints_channels4); | |
1da177e4 LT |
1216 | } |
1217 | if (chip->dra) { | |
1218 | snd_ac97_pcm_double_rate_rules(runtime); | |
1219 | } | |
1220 | if (chip->smp20bit) { | |
1221 | runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE; | |
1222 | snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20); | |
1223 | } | |
1224 | return 0; | |
1225 | } | |
1226 | ||
6b75a9d8 | 1227 | static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream) |
1da177e4 | 1228 | { |
6b75a9d8 | 1229 | struct intel8x0 *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1230 | |
1231 | chip->ichd[ICHD_PCMOUT].substream = NULL; | |
1232 | return 0; | |
1233 | } | |
1234 | ||
6b75a9d8 | 1235 | static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream) |
1da177e4 | 1236 | { |
6b75a9d8 | 1237 | struct intel8x0 *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1238 | |
1239 | return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]); | |
1240 | } | |
1241 | ||
6b75a9d8 | 1242 | static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream) |
1da177e4 | 1243 | { |
6b75a9d8 | 1244 | struct intel8x0 *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1245 | |
1246 | chip->ichd[ICHD_PCMIN].substream = NULL; | |
1247 | return 0; | |
1248 | } | |
1249 | ||
6b75a9d8 | 1250 | static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream) |
1da177e4 | 1251 | { |
6b75a9d8 | 1252 | struct intel8x0 *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1253 | |
1254 | return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]); | |
1255 | } | |
1256 | ||
6b75a9d8 | 1257 | static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream) |
1da177e4 | 1258 | { |
6b75a9d8 | 1259 | struct intel8x0 *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1260 | |
1261 | chip->ichd[ICHD_MIC].substream = NULL; | |
1262 | return 0; | |
1263 | } | |
1264 | ||
6b75a9d8 | 1265 | static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream) |
1da177e4 | 1266 | { |
6b75a9d8 | 1267 | struct intel8x0 *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1268 | |
1269 | return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]); | |
1270 | } | |
1271 | ||
6b75a9d8 | 1272 | static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream) |
1da177e4 | 1273 | { |
6b75a9d8 | 1274 | struct intel8x0 *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1275 | |
1276 | chip->ichd[ICHD_MIC2].substream = NULL; | |
1277 | return 0; | |
1278 | } | |
1279 | ||
6b75a9d8 | 1280 | static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream) |
1da177e4 | 1281 | { |
6b75a9d8 | 1282 | struct intel8x0 *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1283 | |
1284 | return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]); | |
1285 | } | |
1286 | ||
6b75a9d8 | 1287 | static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream) |
1da177e4 | 1288 | { |
6b75a9d8 | 1289 | struct intel8x0 *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1290 | |
1291 | chip->ichd[ICHD_PCM2IN].substream = NULL; | |
1292 | return 0; | |
1293 | } | |
1294 | ||
6b75a9d8 | 1295 | static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream) |
1da177e4 | 1296 | { |
6b75a9d8 | 1297 | struct intel8x0 *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1298 | int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR; |
1299 | ||
1300 | return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]); | |
1301 | } | |
1302 | ||
6b75a9d8 | 1303 | static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream) |
1da177e4 | 1304 | { |
6b75a9d8 | 1305 | struct intel8x0 *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1306 | int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR; |
1307 | ||
1308 | chip->ichd[idx].substream = NULL; | |
1309 | return 0; | |
1310 | } | |
1311 | ||
6b75a9d8 | 1312 | static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream) |
1da177e4 | 1313 | { |
6b75a9d8 | 1314 | struct intel8x0 *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1315 | unsigned int val; |
1316 | ||
1317 | spin_lock_irq(&chip->reg_lock); | |
1318 | val = igetdword(chip, ICHREG(ALI_INTERFACECR)); | |
1319 | val |= ICH_ALI_IF_AC97SP; | |
1320 | iputdword(chip, ICHREG(ALI_INTERFACECR), val); | |
1321 | /* also needs to set ALI_SC_CODEC_SPDF correctly */ | |
1322 | spin_unlock_irq(&chip->reg_lock); | |
1323 | ||
1324 | return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]); | |
1325 | } | |
1326 | ||
6b75a9d8 | 1327 | static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream) |
1da177e4 | 1328 | { |
6b75a9d8 | 1329 | struct intel8x0 *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1330 | unsigned int val; |
1331 | ||
1332 | chip->ichd[ALID_AC97SPDIFOUT].substream = NULL; | |
1333 | spin_lock_irq(&chip->reg_lock); | |
1334 | val = igetdword(chip, ICHREG(ALI_INTERFACECR)); | |
1335 | val &= ~ICH_ALI_IF_AC97SP; | |
1336 | iputdword(chip, ICHREG(ALI_INTERFACECR), val); | |
1337 | spin_unlock_irq(&chip->reg_lock); | |
1338 | ||
1339 | return 0; | |
1340 | } | |
1341 | ||
1a183131 | 1342 | #if 0 // NYI |
6b75a9d8 | 1343 | static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream) |
1da177e4 | 1344 | { |
6b75a9d8 | 1345 | struct intel8x0 *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1346 | |
1347 | return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]); | |
1348 | } | |
1349 | ||
6b75a9d8 | 1350 | static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream) |
1da177e4 | 1351 | { |
6b75a9d8 | 1352 | struct intel8x0 *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1353 | |
1354 | chip->ichd[ALID_SPDIFIN].substream = NULL; | |
1355 | return 0; | |
1356 | } | |
1357 | ||
6b75a9d8 | 1358 | static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream) |
1da177e4 | 1359 | { |
6b75a9d8 | 1360 | struct intel8x0 *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1361 | |
1362 | return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]); | |
1363 | } | |
1364 | ||
6b75a9d8 | 1365 | static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream) |
1da177e4 | 1366 | { |
6b75a9d8 | 1367 | struct intel8x0 *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1368 | |
1369 | chip->ichd[ALID_SPDIFOUT].substream = NULL; | |
1370 | return 0; | |
1371 | } | |
1372 | #endif | |
1373 | ||
6b75a9d8 | 1374 | static struct snd_pcm_ops snd_intel8x0_playback_ops = { |
1da177e4 LT |
1375 | .open = snd_intel8x0_playback_open, |
1376 | .close = snd_intel8x0_playback_close, | |
1377 | .ioctl = snd_pcm_lib_ioctl, | |
1378 | .hw_params = snd_intel8x0_hw_params, | |
1379 | .hw_free = snd_intel8x0_hw_free, | |
1380 | .prepare = snd_intel8x0_pcm_prepare, | |
1381 | .trigger = snd_intel8x0_pcm_trigger, | |
1382 | .pointer = snd_intel8x0_pcm_pointer, | |
1383 | }; | |
1384 | ||
6b75a9d8 | 1385 | static struct snd_pcm_ops snd_intel8x0_capture_ops = { |
1da177e4 LT |
1386 | .open = snd_intel8x0_capture_open, |
1387 | .close = snd_intel8x0_capture_close, | |
1388 | .ioctl = snd_pcm_lib_ioctl, | |
1389 | .hw_params = snd_intel8x0_hw_params, | |
1390 | .hw_free = snd_intel8x0_hw_free, | |
1391 | .prepare = snd_intel8x0_pcm_prepare, | |
1392 | .trigger = snd_intel8x0_pcm_trigger, | |
1393 | .pointer = snd_intel8x0_pcm_pointer, | |
1394 | }; | |
1395 | ||
6b75a9d8 | 1396 | static struct snd_pcm_ops snd_intel8x0_capture_mic_ops = { |
1da177e4 LT |
1397 | .open = snd_intel8x0_mic_open, |
1398 | .close = snd_intel8x0_mic_close, | |
1399 | .ioctl = snd_pcm_lib_ioctl, | |
1400 | .hw_params = snd_intel8x0_hw_params, | |
1401 | .hw_free = snd_intel8x0_hw_free, | |
1402 | .prepare = snd_intel8x0_pcm_prepare, | |
1403 | .trigger = snd_intel8x0_pcm_trigger, | |
1404 | .pointer = snd_intel8x0_pcm_pointer, | |
1405 | }; | |
1406 | ||
6b75a9d8 | 1407 | static struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = { |
1da177e4 LT |
1408 | .open = snd_intel8x0_mic2_open, |
1409 | .close = snd_intel8x0_mic2_close, | |
1410 | .ioctl = snd_pcm_lib_ioctl, | |
1411 | .hw_params = snd_intel8x0_hw_params, | |
1412 | .hw_free = snd_intel8x0_hw_free, | |
1413 | .prepare = snd_intel8x0_pcm_prepare, | |
1414 | .trigger = snd_intel8x0_pcm_trigger, | |
1415 | .pointer = snd_intel8x0_pcm_pointer, | |
1416 | }; | |
1417 | ||
6b75a9d8 | 1418 | static struct snd_pcm_ops snd_intel8x0_capture2_ops = { |
1da177e4 LT |
1419 | .open = snd_intel8x0_capture2_open, |
1420 | .close = snd_intel8x0_capture2_close, | |
1421 | .ioctl = snd_pcm_lib_ioctl, | |
1422 | .hw_params = snd_intel8x0_hw_params, | |
1423 | .hw_free = snd_intel8x0_hw_free, | |
1424 | .prepare = snd_intel8x0_pcm_prepare, | |
1425 | .trigger = snd_intel8x0_pcm_trigger, | |
1426 | .pointer = snd_intel8x0_pcm_pointer, | |
1427 | }; | |
1428 | ||
6b75a9d8 | 1429 | static struct snd_pcm_ops snd_intel8x0_spdif_ops = { |
1da177e4 LT |
1430 | .open = snd_intel8x0_spdif_open, |
1431 | .close = snd_intel8x0_spdif_close, | |
1432 | .ioctl = snd_pcm_lib_ioctl, | |
1433 | .hw_params = snd_intel8x0_hw_params, | |
1434 | .hw_free = snd_intel8x0_hw_free, | |
1435 | .prepare = snd_intel8x0_pcm_prepare, | |
1436 | .trigger = snd_intel8x0_pcm_trigger, | |
1437 | .pointer = snd_intel8x0_pcm_pointer, | |
1438 | }; | |
1439 | ||
6b75a9d8 | 1440 | static struct snd_pcm_ops snd_intel8x0_ali_playback_ops = { |
1da177e4 LT |
1441 | .open = snd_intel8x0_playback_open, |
1442 | .close = snd_intel8x0_playback_close, | |
1443 | .ioctl = snd_pcm_lib_ioctl, | |
1444 | .hw_params = snd_intel8x0_hw_params, | |
1445 | .hw_free = snd_intel8x0_hw_free, | |
1446 | .prepare = snd_intel8x0_pcm_prepare, | |
1447 | .trigger = snd_intel8x0_ali_trigger, | |
1448 | .pointer = snd_intel8x0_pcm_pointer, | |
1449 | }; | |
1450 | ||
6b75a9d8 | 1451 | static struct snd_pcm_ops snd_intel8x0_ali_capture_ops = { |
1da177e4 LT |
1452 | .open = snd_intel8x0_capture_open, |
1453 | .close = snd_intel8x0_capture_close, | |
1454 | .ioctl = snd_pcm_lib_ioctl, | |
1455 | .hw_params = snd_intel8x0_hw_params, | |
1456 | .hw_free = snd_intel8x0_hw_free, | |
1457 | .prepare = snd_intel8x0_pcm_prepare, | |
1458 | .trigger = snd_intel8x0_ali_trigger, | |
1459 | .pointer = snd_intel8x0_pcm_pointer, | |
1460 | }; | |
1461 | ||
6b75a9d8 | 1462 | static struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = { |
1da177e4 LT |
1463 | .open = snd_intel8x0_mic_open, |
1464 | .close = snd_intel8x0_mic_close, | |
1465 | .ioctl = snd_pcm_lib_ioctl, | |
1466 | .hw_params = snd_intel8x0_hw_params, | |
1467 | .hw_free = snd_intel8x0_hw_free, | |
1468 | .prepare = snd_intel8x0_pcm_prepare, | |
1469 | .trigger = snd_intel8x0_ali_trigger, | |
1470 | .pointer = snd_intel8x0_pcm_pointer, | |
1471 | }; | |
1472 | ||
6b75a9d8 | 1473 | static struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = { |
1da177e4 LT |
1474 | .open = snd_intel8x0_ali_ac97spdifout_open, |
1475 | .close = snd_intel8x0_ali_ac97spdifout_close, | |
1476 | .ioctl = snd_pcm_lib_ioctl, | |
1477 | .hw_params = snd_intel8x0_hw_params, | |
1478 | .hw_free = snd_intel8x0_hw_free, | |
1479 | .prepare = snd_intel8x0_pcm_prepare, | |
1480 | .trigger = snd_intel8x0_ali_trigger, | |
1481 | .pointer = snd_intel8x0_pcm_pointer, | |
1482 | }; | |
1483 | ||
1a183131 | 1484 | #if 0 // NYI |
6b75a9d8 | 1485 | static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = { |
1da177e4 LT |
1486 | .open = snd_intel8x0_ali_spdifin_open, |
1487 | .close = snd_intel8x0_ali_spdifin_close, | |
1488 | .ioctl = snd_pcm_lib_ioctl, | |
1489 | .hw_params = snd_intel8x0_hw_params, | |
1490 | .hw_free = snd_intel8x0_hw_free, | |
1491 | .prepare = snd_intel8x0_pcm_prepare, | |
1492 | .trigger = snd_intel8x0_pcm_trigger, | |
1493 | .pointer = snd_intel8x0_pcm_pointer, | |
1494 | }; | |
1495 | ||
6b75a9d8 | 1496 | static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = { |
1da177e4 LT |
1497 | .open = snd_intel8x0_ali_spdifout_open, |
1498 | .close = snd_intel8x0_ali_spdifout_close, | |
1499 | .ioctl = snd_pcm_lib_ioctl, | |
1500 | .hw_params = snd_intel8x0_hw_params, | |
1501 | .hw_free = snd_intel8x0_hw_free, | |
1502 | .prepare = snd_intel8x0_pcm_prepare, | |
1503 | .trigger = snd_intel8x0_pcm_trigger, | |
1504 | .pointer = snd_intel8x0_pcm_pointer, | |
1505 | }; | |
1506 | #endif // NYI | |
1507 | ||
1508 | struct ich_pcm_table { | |
1509 | char *suffix; | |
6b75a9d8 TI |
1510 | struct snd_pcm_ops *playback_ops; |
1511 | struct snd_pcm_ops *capture_ops; | |
1da177e4 LT |
1512 | size_t prealloc_size; |
1513 | size_t prealloc_max_size; | |
1514 | int ac97_idx; | |
1515 | }; | |
1516 | ||
e23e7a14 BP |
1517 | static int snd_intel8x0_pcm1(struct intel8x0 *chip, int device, |
1518 | struct ich_pcm_table *rec) | |
1da177e4 | 1519 | { |
6b75a9d8 | 1520 | struct snd_pcm *pcm; |
1da177e4 LT |
1521 | int err; |
1522 | char name[32]; | |
1523 | ||
1524 | if (rec->suffix) | |
1525 | sprintf(name, "Intel ICH - %s", rec->suffix); | |
1526 | else | |
1527 | strcpy(name, "Intel ICH"); | |
1528 | err = snd_pcm_new(chip->card, name, device, | |
1529 | rec->playback_ops ? 1 : 0, | |
1530 | rec->capture_ops ? 1 : 0, &pcm); | |
1531 | if (err < 0) | |
1532 | return err; | |
1533 | ||
1534 | if (rec->playback_ops) | |
1535 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops); | |
1536 | if (rec->capture_ops) | |
1537 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops); | |
1538 | ||
1539 | pcm->private_data = chip; | |
1540 | pcm->info_flags = 0; | |
1541 | if (rec->suffix) | |
1542 | sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix); | |
1543 | else | |
1544 | strcpy(pcm->name, chip->card->shortname); | |
1545 | chip->pcm[device] = pcm; | |
1546 | ||
6b75a9d8 TI |
1547 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, |
1548 | snd_dma_pci_data(chip->pci), | |
1da177e4 LT |
1549 | rec->prealloc_size, rec->prealloc_max_size); |
1550 | ||
791b3f59 TI |
1551 | if (rec->playback_ops && |
1552 | rec->playback_ops->open == snd_intel8x0_playback_open) { | |
e36e3b86 TI |
1553 | struct snd_pcm_chmap *chmap; |
1554 | int chs = 2; | |
791b3f59 TI |
1555 | if (chip->multi8) |
1556 | chs = 8; | |
1557 | else if (chip->multi6) | |
1558 | chs = 6; | |
1559 | else if (chip->multi4) | |
1560 | chs = 4; | |
e36e3b86 TI |
1561 | err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, |
1562 | snd_pcm_alt_chmaps, chs, 0, | |
1563 | &chmap); | |
1564 | if (err < 0) | |
1565 | return err; | |
1566 | chmap->channel_mask = SND_PCM_CHMAP_MASK_2468; | |
1567 | chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap; | |
1568 | } | |
1569 | ||
1da177e4 LT |
1570 | return 0; |
1571 | } | |
1572 | ||
e23e7a14 | 1573 | static struct ich_pcm_table intel_pcms[] = { |
1da177e4 LT |
1574 | { |
1575 | .playback_ops = &snd_intel8x0_playback_ops, | |
1576 | .capture_ops = &snd_intel8x0_capture_ops, | |
1577 | .prealloc_size = 64 * 1024, | |
1578 | .prealloc_max_size = 128 * 1024, | |
1579 | }, | |
1580 | { | |
1581 | .suffix = "MIC ADC", | |
1582 | .capture_ops = &snd_intel8x0_capture_mic_ops, | |
1583 | .prealloc_size = 0, | |
1584 | .prealloc_max_size = 128 * 1024, | |
1585 | .ac97_idx = ICHD_MIC, | |
1586 | }, | |
1587 | { | |
1588 | .suffix = "MIC2 ADC", | |
1589 | .capture_ops = &snd_intel8x0_capture_mic2_ops, | |
1590 | .prealloc_size = 0, | |
1591 | .prealloc_max_size = 128 * 1024, | |
1592 | .ac97_idx = ICHD_MIC2, | |
1593 | }, | |
1594 | { | |
1595 | .suffix = "ADC2", | |
1596 | .capture_ops = &snd_intel8x0_capture2_ops, | |
1597 | .prealloc_size = 0, | |
1598 | .prealloc_max_size = 128 * 1024, | |
1599 | .ac97_idx = ICHD_PCM2IN, | |
1600 | }, | |
1601 | { | |
1602 | .suffix = "IEC958", | |
1603 | .playback_ops = &snd_intel8x0_spdif_ops, | |
1604 | .prealloc_size = 64 * 1024, | |
1605 | .prealloc_max_size = 128 * 1024, | |
1606 | .ac97_idx = ICHD_SPBAR, | |
1607 | }, | |
1608 | }; | |
1609 | ||
e23e7a14 | 1610 | static struct ich_pcm_table nforce_pcms[] = { |
1da177e4 LT |
1611 | { |
1612 | .playback_ops = &snd_intel8x0_playback_ops, | |
1613 | .capture_ops = &snd_intel8x0_capture_ops, | |
1614 | .prealloc_size = 64 * 1024, | |
1615 | .prealloc_max_size = 128 * 1024, | |
1616 | }, | |
1617 | { | |
1618 | .suffix = "MIC ADC", | |
1619 | .capture_ops = &snd_intel8x0_capture_mic_ops, | |
1620 | .prealloc_size = 0, | |
1621 | .prealloc_max_size = 128 * 1024, | |
1622 | .ac97_idx = NVD_MIC, | |
1623 | }, | |
1624 | { | |
1625 | .suffix = "IEC958", | |
1626 | .playback_ops = &snd_intel8x0_spdif_ops, | |
1627 | .prealloc_size = 64 * 1024, | |
1628 | .prealloc_max_size = 128 * 1024, | |
1629 | .ac97_idx = NVD_SPBAR, | |
1630 | }, | |
1631 | }; | |
1632 | ||
e23e7a14 | 1633 | static struct ich_pcm_table ali_pcms[] = { |
1da177e4 LT |
1634 | { |
1635 | .playback_ops = &snd_intel8x0_ali_playback_ops, | |
1636 | .capture_ops = &snd_intel8x0_ali_capture_ops, | |
1637 | .prealloc_size = 64 * 1024, | |
1638 | .prealloc_max_size = 128 * 1024, | |
1639 | }, | |
1640 | { | |
1641 | .suffix = "MIC ADC", | |
1642 | .capture_ops = &snd_intel8x0_ali_capture_mic_ops, | |
1643 | .prealloc_size = 0, | |
1644 | .prealloc_max_size = 128 * 1024, | |
1645 | .ac97_idx = ALID_MIC, | |
1646 | }, | |
1647 | { | |
1648 | .suffix = "IEC958", | |
1649 | .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops, | |
1a183131 | 1650 | /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */ |
1da177e4 LT |
1651 | .prealloc_size = 64 * 1024, |
1652 | .prealloc_max_size = 128 * 1024, | |
1653 | .ac97_idx = ALID_AC97SPDIFOUT, | |
1654 | }, | |
1655 | #if 0 // NYI | |
1656 | { | |
1657 | .suffix = "HW IEC958", | |
1658 | .playback_ops = &snd_intel8x0_ali_spdifout_ops, | |
1659 | .prealloc_size = 64 * 1024, | |
1660 | .prealloc_max_size = 128 * 1024, | |
1661 | }, | |
1662 | #endif | |
1663 | }; | |
1664 | ||
e23e7a14 | 1665 | static int snd_intel8x0_pcm(struct intel8x0 *chip) |
1da177e4 LT |
1666 | { |
1667 | int i, tblsize, device, err; | |
1668 | struct ich_pcm_table *tbl, *rec; | |
1669 | ||
1670 | switch (chip->device_type) { | |
1671 | case DEVICE_INTEL_ICH4: | |
1672 | tbl = intel_pcms; | |
1673 | tblsize = ARRAY_SIZE(intel_pcms); | |
a9e99660 TI |
1674 | if (spdif_aclink) |
1675 | tblsize--; | |
1da177e4 LT |
1676 | break; |
1677 | case DEVICE_NFORCE: | |
1678 | tbl = nforce_pcms; | |
1679 | tblsize = ARRAY_SIZE(nforce_pcms); | |
a9e99660 TI |
1680 | if (spdif_aclink) |
1681 | tblsize--; | |
1da177e4 LT |
1682 | break; |
1683 | case DEVICE_ALI: | |
1684 | tbl = ali_pcms; | |
1685 | tblsize = ARRAY_SIZE(ali_pcms); | |
1686 | break; | |
1687 | default: | |
1688 | tbl = intel_pcms; | |
1689 | tblsize = 2; | |
1690 | break; | |
1691 | } | |
1692 | ||
1693 | device = 0; | |
1694 | for (i = 0; i < tblsize; i++) { | |
1695 | rec = tbl + i; | |
1696 | if (i > 0 && rec->ac97_idx) { | |
1697 | /* activate PCM only when associated AC'97 codec */ | |
1698 | if (! chip->ichd[rec->ac97_idx].pcm) | |
1699 | continue; | |
1700 | } | |
1701 | err = snd_intel8x0_pcm1(chip, device, rec); | |
1702 | if (err < 0) | |
1703 | return err; | |
1704 | device++; | |
1705 | } | |
1706 | ||
1707 | chip->pcm_devs = device; | |
1708 | return 0; | |
1709 | } | |
1710 | ||
1711 | ||
1712 | /* | |
1713 | * Mixer part | |
1714 | */ | |
1715 | ||
6b75a9d8 | 1716 | static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus) |
1da177e4 | 1717 | { |
6b75a9d8 | 1718 | struct intel8x0 *chip = bus->private_data; |
1da177e4 LT |
1719 | chip->ac97_bus = NULL; |
1720 | } | |
1721 | ||
6b75a9d8 | 1722 | static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97) |
1da177e4 | 1723 | { |
6b75a9d8 | 1724 | struct intel8x0 *chip = ac97->private_data; |
1da177e4 LT |
1725 | chip->ac97[ac97->num] = NULL; |
1726 | } | |
1727 | ||
e23e7a14 | 1728 | static struct ac97_pcm ac97_pcm_defs[] = { |
1da177e4 LT |
1729 | /* front PCM */ |
1730 | { | |
1731 | .exclusive = 1, | |
1732 | .r = { { | |
1733 | .slots = (1 << AC97_SLOT_PCM_LEFT) | | |
1734 | (1 << AC97_SLOT_PCM_RIGHT) | | |
1735 | (1 << AC97_SLOT_PCM_CENTER) | | |
1736 | (1 << AC97_SLOT_PCM_SLEFT) | | |
1737 | (1 << AC97_SLOT_PCM_SRIGHT) | | |
1738 | (1 << AC97_SLOT_LFE) | |
1739 | }, | |
1740 | { | |
1741 | .slots = (1 << AC97_SLOT_PCM_LEFT) | | |
1742 | (1 << AC97_SLOT_PCM_RIGHT) | | |
1743 | (1 << AC97_SLOT_PCM_LEFT_0) | | |
1744 | (1 << AC97_SLOT_PCM_RIGHT_0) | |
1745 | } | |
1746 | } | |
1747 | }, | |
1748 | /* PCM IN #1 */ | |
1749 | { | |
1750 | .stream = 1, | |
1751 | .exclusive = 1, | |
1752 | .r = { { | |
1753 | .slots = (1 << AC97_SLOT_PCM_LEFT) | | |
1754 | (1 << AC97_SLOT_PCM_RIGHT) | |
1755 | } | |
1756 | } | |
1757 | }, | |
1758 | /* MIC IN #1 */ | |
1759 | { | |
1760 | .stream = 1, | |
1761 | .exclusive = 1, | |
1762 | .r = { { | |
1763 | .slots = (1 << AC97_SLOT_MIC) | |
1764 | } | |
1765 | } | |
1766 | }, | |
1767 | /* S/PDIF PCM */ | |
1768 | { | |
1769 | .exclusive = 1, | |
1770 | .spdif = 1, | |
1771 | .r = { { | |
1772 | .slots = (1 << AC97_SLOT_SPDIF_LEFT2) | | |
1773 | (1 << AC97_SLOT_SPDIF_RIGHT2) | |
1774 | } | |
1775 | } | |
1776 | }, | |
1777 | /* PCM IN #2 */ | |
1778 | { | |
1779 | .stream = 1, | |
1780 | .exclusive = 1, | |
1781 | .r = { { | |
1782 | .slots = (1 << AC97_SLOT_PCM_LEFT) | | |
1783 | (1 << AC97_SLOT_PCM_RIGHT) | |
1784 | } | |
1785 | } | |
1786 | }, | |
1787 | /* MIC IN #2 */ | |
1788 | { | |
1789 | .stream = 1, | |
1790 | .exclusive = 1, | |
1791 | .r = { { | |
1792 | .slots = (1 << AC97_SLOT_MIC) | |
1793 | } | |
1794 | } | |
1795 | }, | |
1796 | }; | |
1797 | ||
eab0fbfa | 1798 | static const struct ac97_quirk ac97_quirks[] = { |
0d9ac27a TI |
1799 | { |
1800 | .subvendor = 0x0e11, | |
1801 | .subdevice = 0x000e, | |
1802 | .name = "Compaq Deskpro EN", /* AD1885 */ | |
1803 | .type = AC97_TUNE_HP_ONLY | |
1804 | }, | |
1da177e4 | 1805 | { |
6fd8b87f JCD |
1806 | .subvendor = 0x0e11, |
1807 | .subdevice = 0x008a, | |
1da177e4 LT |
1808 | .name = "Compaq Evo W4000", /* AD1885 */ |
1809 | .type = AC97_TUNE_HP_ONLY | |
1810 | }, | |
1811 | { | |
6fd8b87f JCD |
1812 | .subvendor = 0x0e11, |
1813 | .subdevice = 0x00b8, | |
1da177e4 LT |
1814 | .name = "Compaq Evo D510C", |
1815 | .type = AC97_TUNE_HP_ONLY | |
1816 | }, | |
1817 | { | |
6fd8b87f JCD |
1818 | .subvendor = 0x0e11, |
1819 | .subdevice = 0x0860, | |
1da177e4 LT |
1820 | .name = "HP/Compaq nx7010", |
1821 | .type = AC97_TUNE_MUTE_LED | |
1822 | }, | |
9c77b846 DC |
1823 | { |
1824 | .subvendor = 0x1014, | |
1825 | .subdevice = 0x0534, | |
1826 | .name = "ThinkPad X31", | |
1827 | .type = AC97_TUNE_INV_EAPD | |
1828 | }, | |
1da177e4 | 1829 | { |
6fd8b87f JCD |
1830 | .subvendor = 0x1014, |
1831 | .subdevice = 0x1f00, | |
1da177e4 LT |
1832 | .name = "MS-9128", |
1833 | .type = AC97_TUNE_ALC_JACK | |
1834 | }, | |
5d529390 TI |
1835 | { |
1836 | .subvendor = 0x1014, | |
1837 | .subdevice = 0x0267, | |
1838 | .name = "IBM NetVista A30p", /* AD1981B */ | |
1839 | .type = AC97_TUNE_HP_ONLY | |
b6a370b6 TI |
1840 | }, |
1841 | { | |
1842 | .subvendor = 0x1025, | |
1843 | .subdevice = 0x0082, | |
1844 | .name = "Acer Travelmate 2310", | |
1845 | .type = AC97_TUNE_HP_ONLY | |
5d529390 | 1846 | }, |
72c8986c DS |
1847 | { |
1848 | .subvendor = 0x1025, | |
1849 | .subdevice = 0x0083, | |
1850 | .name = "Acer Aspire 3003LCi", | |
1851 | .type = AC97_TUNE_HP_ONLY | |
1852 | }, | |
1da177e4 | 1853 | { |
6fd8b87f JCD |
1854 | .subvendor = 0x1028, |
1855 | .subdevice = 0x00d8, | |
1da177e4 LT |
1856 | .name = "Dell Precision 530", /* AD1885 */ |
1857 | .type = AC97_TUNE_HP_ONLY | |
1858 | }, | |
1859 | { | |
6fd8b87f JCD |
1860 | .subvendor = 0x1028, |
1861 | .subdevice = 0x010d, | |
1da177e4 LT |
1862 | .name = "Dell", /* which model? AD1885 */ |
1863 | .type = AC97_TUNE_HP_ONLY | |
1864 | }, | |
1865 | { | |
6fd8b87f JCD |
1866 | .subvendor = 0x1028, |
1867 | .subdevice = 0x0126, | |
1da177e4 LT |
1868 | .name = "Dell Optiplex GX260", /* AD1981A */ |
1869 | .type = AC97_TUNE_HP_ONLY | |
1870 | }, | |
1871 | { | |
6fd8b87f JCD |
1872 | .subvendor = 0x1028, |
1873 | .subdevice = 0x012c, | |
1da177e4 LT |
1874 | .name = "Dell Precision 650", /* AD1981A */ |
1875 | .type = AC97_TUNE_HP_ONLY | |
1876 | }, | |
1877 | { | |
6fd8b87f JCD |
1878 | .subvendor = 0x1028, |
1879 | .subdevice = 0x012d, | |
1da177e4 LT |
1880 | .name = "Dell Precision 450", /* AD1981B*/ |
1881 | .type = AC97_TUNE_HP_ONLY | |
1882 | }, | |
1883 | { | |
6fd8b87f JCD |
1884 | .subvendor = 0x1028, |
1885 | .subdevice = 0x0147, | |
1da177e4 LT |
1886 | .name = "Dell", /* which model? AD1981B*/ |
1887 | .type = AC97_TUNE_HP_ONLY | |
1888 | }, | |
c9fe51c4 CB |
1889 | { |
1890 | .subvendor = 0x1028, | |
1891 | .subdevice = 0x0151, | |
1892 | .name = "Dell Optiplex GX270", /* AD1981B */ | |
1893 | .type = AC97_TUNE_HP_ONLY | |
1894 | }, | |
1781a9af DC |
1895 | { |
1896 | .subvendor = 0x1028, | |
1897 | .subdevice = 0x014e, | |
1898 | .name = "Dell D800", /* STAC9750/51 */ | |
1899 | .type = AC97_TUNE_HP_ONLY | |
1900 | }, | |
1da177e4 | 1901 | { |
6fd8b87f JCD |
1902 | .subvendor = 0x1028, |
1903 | .subdevice = 0x0163, | |
1da177e4 LT |
1904 | .name = "Dell Unknown", /* STAC9750/51 */ |
1905 | .type = AC97_TUNE_HP_ONLY | |
1906 | }, | |
c8283425 DC |
1907 | { |
1908 | .subvendor = 0x1028, | |
1909 | .subdevice = 0x016a, | |
1910 | .name = "Dell Inspiron 8600", /* STAC9750/51 */ | |
1911 | .type = AC97_TUNE_HP_ONLY | |
0613a594 DC |
1912 | }, |
1913 | { | |
1914 | .subvendor = 0x1028, | |
1915 | .subdevice = 0x0182, | |
1916 | .name = "Dell Latitude D610", /* STAC9750/51 */ | |
1917 | .type = AC97_TUNE_HP_ONLY | |
c8283425 | 1918 | }, |
8286c53e DC |
1919 | { |
1920 | .subvendor = 0x1028, | |
1921 | .subdevice = 0x0186, | |
1922 | .name = "Dell Latitude D810", /* cf. Malone #41015 */ | |
1923 | .type = AC97_TUNE_HP_MUTE_LED | |
1924 | }, | |
1925 | { | |
1926 | .subvendor = 0x1028, | |
1927 | .subdevice = 0x0188, | |
1928 | .name = "Dell Inspiron 6000", | |
1929 | .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */ | |
1930 | }, | |
f21169aa DC |
1931 | { |
1932 | .subvendor = 0x1028, | |
1933 | .subdevice = 0x0189, | |
1934 | .name = "Dell Inspiron 9300", | |
1935 | .type = AC97_TUNE_HP_MUTE_LED | |
1936 | }, | |
6d6f9156 KL |
1937 | { |
1938 | .subvendor = 0x1028, | |
1939 | .subdevice = 0x0191, | |
1940 | .name = "Dell Inspiron 8600", | |
1941 | .type = AC97_TUNE_HP_ONLY | |
1942 | }, | |
1da177e4 | 1943 | { |
6fd8b87f JCD |
1944 | .subvendor = 0x103c, |
1945 | .subdevice = 0x006d, | |
1da177e4 LT |
1946 | .name = "HP zv5000", |
1947 | .type = AC97_TUNE_MUTE_LED /*AD1981B*/ | |
1948 | }, | |
1949 | { /* FIXME: which codec? */ | |
6fd8b87f JCD |
1950 | .subvendor = 0x103c, |
1951 | .subdevice = 0x00c3, | |
1da177e4 LT |
1952 | .name = "HP xw6000", |
1953 | .type = AC97_TUNE_HP_ONLY | |
1954 | }, | |
1955 | { | |
6fd8b87f JCD |
1956 | .subvendor = 0x103c, |
1957 | .subdevice = 0x088c, | |
1da177e4 | 1958 | .name = "HP nc8000", |
8286c53e | 1959 | .type = AC97_TUNE_HP_MUTE_LED |
1da177e4 LT |
1960 | }, |
1961 | { | |
6fd8b87f JCD |
1962 | .subvendor = 0x103c, |
1963 | .subdevice = 0x0890, | |
1da177e4 LT |
1964 | .name = "HP nc6000", |
1965 | .type = AC97_TUNE_MUTE_LED | |
1966 | }, | |
1967 | { | |
6fd8b87f JCD |
1968 | .subvendor = 0x103c, |
1969 | .subdevice = 0x129d, | |
1da177e4 LT |
1970 | .name = "HP xw8000", |
1971 | .type = AC97_TUNE_HP_ONLY | |
1972 | }, | |
a0faefed MG |
1973 | { |
1974 | .subvendor = 0x103c, | |
1975 | .subdevice = 0x0938, | |
1976 | .name = "HP nc4200", | |
1977 | .type = AC97_TUNE_HP_MUTE_LED | |
1978 | }, | |
1979 | { | |
1980 | .subvendor = 0x103c, | |
1981 | .subdevice = 0x099c, | |
d82ed2ff | 1982 | .name = "HP nx6110/nc6120", |
a0faefed MG |
1983 | .type = AC97_TUNE_HP_MUTE_LED |
1984 | }, | |
1985 | { | |
1986 | .subvendor = 0x103c, | |
1987 | .subdevice = 0x0944, | |
1988 | .name = "HP nc6220", | |
1989 | .type = AC97_TUNE_HP_MUTE_LED | |
1990 | }, | |
1991 | { | |
1992 | .subvendor = 0x103c, | |
1993 | .subdevice = 0x0934, | |
1994 | .name = "HP nc8220", | |
1995 | .type = AC97_TUNE_HP_MUTE_LED | |
1996 | }, | |
1da177e4 | 1997 | { |
6fd8b87f JCD |
1998 | .subvendor = 0x103c, |
1999 | .subdevice = 0x12f1, | |
1da177e4 LT |
2000 | .name = "HP xw8200", /* AD1981B*/ |
2001 | .type = AC97_TUNE_HP_ONLY | |
2002 | }, | |
2003 | { | |
6fd8b87f JCD |
2004 | .subvendor = 0x103c, |
2005 | .subdevice = 0x12f2, | |
1da177e4 LT |
2006 | .name = "HP xw6200", |
2007 | .type = AC97_TUNE_HP_ONLY | |
2008 | }, | |
2009 | { | |
6fd8b87f JCD |
2010 | .subvendor = 0x103c, |
2011 | .subdevice = 0x3008, | |
1da177e4 LT |
2012 | .name = "HP xw4200", /* AD1981B*/ |
2013 | .type = AC97_TUNE_HP_ONLY | |
2014 | }, | |
7e6c3989 DC |
2015 | { |
2016 | .subvendor = 0x104d, | |
2017 | .subdevice = 0x8144, | |
2018 | .name = "Sony", | |
2019 | .type = AC97_TUNE_INV_EAPD | |
2020 | }, | |
1da177e4 | 2021 | { |
6fd8b87f JCD |
2022 | .subvendor = 0x104d, |
2023 | .subdevice = 0x8197, | |
1da177e4 LT |
2024 | .name = "Sony S1XP", |
2025 | .type = AC97_TUNE_INV_EAPD | |
2026 | }, | |
5da5b6f9 DC |
2027 | { |
2028 | .subvendor = 0x104d, | |
2029 | .subdevice = 0x81c0, | |
2030 | .name = "Sony VAIO VGN-T350P", /*AD1981B*/ | |
2031 | .type = AC97_TUNE_INV_EAPD | |
2032 | }, | |
ebb6f6ac DC |
2033 | { |
2034 | .subvendor = 0x104d, | |
2035 | .subdevice = 0x81c5, | |
2036 | .name = "Sony VAIO VGN-B1VP", /*AD1981B*/ | |
2037 | .type = AC97_TUNE_INV_EAPD | |
2038 | }, | |
1da177e4 | 2039 | { |
6fd8b87f JCD |
2040 | .subvendor = 0x1043, |
2041 | .subdevice = 0x80f3, | |
1da177e4 LT |
2042 | .name = "ASUS ICH5/AD1985", |
2043 | .type = AC97_TUNE_AD_SHARING | |
2044 | }, | |
2045 | { | |
6fd8b87f JCD |
2046 | .subvendor = 0x10cf, |
2047 | .subdevice = 0x11c3, | |
1da177e4 LT |
2048 | .name = "Fujitsu-Siemens E4010", |
2049 | .type = AC97_TUNE_HP_ONLY | |
2050 | }, | |
98c7f212 TI |
2051 | { |
2052 | .subvendor = 0x10cf, | |
2053 | .subdevice = 0x1225, | |
2054 | .name = "Fujitsu-Siemens T3010", | |
2055 | .type = AC97_TUNE_HP_ONLY | |
2056 | }, | |
1da177e4 | 2057 | { |
6fd8b87f JCD |
2058 | .subvendor = 0x10cf, |
2059 | .subdevice = 0x1253, | |
1da177e4 LT |
2060 | .name = "Fujitsu S6210", /* STAC9750/51 */ |
2061 | .type = AC97_TUNE_HP_ONLY | |
2062 | }, | |
37c34ffb TI |
2063 | { |
2064 | .subvendor = 0x10cf, | |
2065 | .subdevice = 0x127d, | |
2066 | .name = "Fujitsu Lifebook P7010", | |
2067 | .type = AC97_TUNE_HP_ONLY | |
2068 | }, | |
8286c53e DC |
2069 | { |
2070 | .subvendor = 0x10cf, | |
2071 | .subdevice = 0x127e, | |
2072 | .name = "Fujitsu Lifebook C1211D", | |
2073 | .type = AC97_TUNE_HP_ONLY | |
2074 | }, | |
9970dce5 TI |
2075 | { |
2076 | .subvendor = 0x10cf, | |
2077 | .subdevice = 0x12ec, | |
2078 | .name = "Fujitsu-Siemens 4010", | |
2079 | .type = AC97_TUNE_HP_ONLY | |
2080 | }, | |
2eb061f4 JK |
2081 | { |
2082 | .subvendor = 0x10cf, | |
2083 | .subdevice = 0x12f2, | |
2084 | .name = "Fujitsu-Siemens Celsius H320", | |
2085 | .type = AC97_TUNE_SWAP_HP | |
2086 | }, | |
1da177e4 | 2087 | { |
6fd8b87f JCD |
2088 | .subvendor = 0x10f1, |
2089 | .subdevice = 0x2665, | |
1da177e4 LT |
2090 | .name = "Fujitsu-Siemens Celsius", /* AD1981? */ |
2091 | .type = AC97_TUNE_HP_ONLY | |
2092 | }, | |
2093 | { | |
6fd8b87f JCD |
2094 | .subvendor = 0x10f1, |
2095 | .subdevice = 0x2885, | |
1da177e4 LT |
2096 | .name = "AMD64 Mobo", /* ALC650 */ |
2097 | .type = AC97_TUNE_HP_ONLY | |
2098 | }, | |
4f42bcc1 TI |
2099 | { |
2100 | .subvendor = 0x10f1, | |
2101 | .subdevice = 0x2895, | |
2102 | .name = "Tyan Thunder K8WE", | |
2103 | .type = AC97_TUNE_HP_ONLY | |
2104 | }, | |
6c504447 KP |
2105 | { |
2106 | .subvendor = 0x10f7, | |
2107 | .subdevice = 0x834c, | |
2108 | .name = "Panasonic CF-R4", | |
2109 | .type = AC97_TUNE_HP_ONLY, | |
2110 | }, | |
1da177e4 | 2111 | { |
6fd8b87f JCD |
2112 | .subvendor = 0x110a, |
2113 | .subdevice = 0x0056, | |
1da177e4 LT |
2114 | .name = "Fujitsu-Siemens Scenic", /* AD1981? */ |
2115 | .type = AC97_TUNE_HP_ONLY | |
2116 | }, | |
2117 | { | |
6fd8b87f JCD |
2118 | .subvendor = 0x11d4, |
2119 | .subdevice = 0x5375, | |
1da177e4 LT |
2120 | .name = "ADI AD1985 (discrete)", |
2121 | .type = AC97_TUNE_HP_ONLY | |
2122 | }, | |
2123 | { | |
6fd8b87f JCD |
2124 | .subvendor = 0x1462, |
2125 | .subdevice = 0x5470, | |
1da177e4 LT |
2126 | .name = "MSI P4 ATX 645 Ultra", |
2127 | .type = AC97_TUNE_HP_ONLY | |
2128 | }, | |
27c3afe6 DC |
2129 | { |
2130 | .subvendor = 0x161f, | |
2131 | .subdevice = 0x202f, | |
2132 | .name = "Gateway M520", | |
2133 | .type = AC97_TUNE_INV_EAPD | |
2134 | }, | |
bbb3c644 DC |
2135 | { |
2136 | .subvendor = 0x161f, | |
2137 | .subdevice = 0x203a, | |
2138 | .name = "Gateway 4525GZ", /* AD1981B */ | |
2139 | .type = AC97_TUNE_INV_EAPD | |
2140 | }, | |
1da177e4 | 2141 | { |
6fd8b87f JCD |
2142 | .subvendor = 0x1734, |
2143 | .subdevice = 0x0088, | |
1da177e4 LT |
2144 | .name = "Fujitsu-Siemens D1522", /* AD1981 */ |
2145 | .type = AC97_TUNE_HP_ONLY | |
2146 | }, | |
2147 | { | |
6fd8b87f JCD |
2148 | .subvendor = 0x8086, |
2149 | .subdevice = 0x2000, | |
1da177e4 LT |
2150 | .mask = 0xfff0, |
2151 | .name = "Intel ICH5/AD1985", | |
2152 | .type = AC97_TUNE_AD_SHARING | |
2153 | }, | |
2154 | { | |
6fd8b87f JCD |
2155 | .subvendor = 0x8086, |
2156 | .subdevice = 0x4000, | |
1da177e4 LT |
2157 | .mask = 0xfff0, |
2158 | .name = "Intel ICH5/AD1985", | |
2159 | .type = AC97_TUNE_AD_SHARING | |
2160 | }, | |
2161 | { | |
6fd8b87f JCD |
2162 | .subvendor = 0x8086, |
2163 | .subdevice = 0x4856, | |
1da177e4 LT |
2164 | .name = "Intel D845WN (82801BA)", |
2165 | .type = AC97_TUNE_SWAP_HP | |
2166 | }, | |
2167 | { | |
6fd8b87f JCD |
2168 | .subvendor = 0x8086, |
2169 | .subdevice = 0x4d44, | |
1da177e4 LT |
2170 | .name = "Intel D850EMV2", /* AD1885 */ |
2171 | .type = AC97_TUNE_HP_ONLY | |
2172 | }, | |
2173 | { | |
6fd8b87f JCD |
2174 | .subvendor = 0x8086, |
2175 | .subdevice = 0x4d56, | |
1da177e4 LT |
2176 | .name = "Intel ICH/AD1885", |
2177 | .type = AC97_TUNE_HP_ONLY | |
2178 | }, | |
2179 | { | |
6fd8b87f JCD |
2180 | .subvendor = 0x8086, |
2181 | .subdevice = 0x6000, | |
1da177e4 LT |
2182 | .mask = 0xfff0, |
2183 | .name = "Intel ICH5/AD1985", | |
2184 | .type = AC97_TUNE_AD_SHARING | |
2185 | }, | |
2186 | { | |
6fd8b87f JCD |
2187 | .subvendor = 0x8086, |
2188 | .subdevice = 0xe000, | |
1da177e4 LT |
2189 | .mask = 0xfff0, |
2190 | .name = "Intel ICH5/AD1985", | |
2191 | .type = AC97_TUNE_AD_SHARING | |
2192 | }, | |
2193 | #if 0 /* FIXME: this seems wrong on most boards */ | |
2194 | { | |
6fd8b87f JCD |
2195 | .subvendor = 0x8086, |
2196 | .subdevice = 0xa000, | |
1da177e4 LT |
2197 | .mask = 0xfff0, |
2198 | .name = "Intel ICH5/AD1985", | |
2199 | .type = AC97_TUNE_HP_ONLY | |
2200 | }, | |
2201 | #endif | |
2202 | { } /* terminator */ | |
2203 | }; | |
2204 | ||
e23e7a14 BP |
2205 | static int snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock, |
2206 | const char *quirk_override) | |
1da177e4 | 2207 | { |
6b75a9d8 TI |
2208 | struct snd_ac97_bus *pbus; |
2209 | struct snd_ac97_template ac97; | |
1da177e4 LT |
2210 | int err; |
2211 | unsigned int i, codecs; | |
2212 | unsigned int glob_sta = 0; | |
6b75a9d8 TI |
2213 | struct snd_ac97_bus_ops *ops; |
2214 | static struct snd_ac97_bus_ops standard_bus_ops = { | |
1da177e4 LT |
2215 | .write = snd_intel8x0_codec_write, |
2216 | .read = snd_intel8x0_codec_read, | |
2217 | }; | |
6b75a9d8 | 2218 | static struct snd_ac97_bus_ops ali_bus_ops = { |
1da177e4 LT |
2219 | .write = snd_intel8x0_ali_codec_write, |
2220 | .read = snd_intel8x0_ali_codec_read, | |
2221 | }; | |
2222 | ||
2223 | chip->spdif_idx = -1; /* use PCMOUT (or disabled) */ | |
a9e99660 TI |
2224 | if (!spdif_aclink) { |
2225 | switch (chip->device_type) { | |
2226 | case DEVICE_NFORCE: | |
2227 | chip->spdif_idx = NVD_SPBAR; | |
2228 | break; | |
2229 | case DEVICE_ALI: | |
2230 | chip->spdif_idx = ALID_AC97SPDIFOUT; | |
2231 | break; | |
2232 | case DEVICE_INTEL_ICH4: | |
2233 | chip->spdif_idx = ICHD_SPBAR; | |
2234 | break; | |
395d9dd5 | 2235 | } |
a9e99660 | 2236 | } |
1da177e4 LT |
2237 | |
2238 | chip->in_ac97_init = 1; | |
2239 | ||
2240 | memset(&ac97, 0, sizeof(ac97)); | |
2241 | ac97.private_data = chip; | |
2242 | ac97.private_free = snd_intel8x0_mixer_free_ac97; | |
f1a63a38 | 2243 | ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE; |
1da177e4 LT |
2244 | if (chip->xbox) |
2245 | ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR; | |
2246 | if (chip->device_type != DEVICE_ALI) { | |
2247 | glob_sta = igetdword(chip, ICHREG(GLOB_STA)); | |
2248 | ops = &standard_bus_ops; | |
84a43bd5 TI |
2249 | chip->in_sdin_init = 1; |
2250 | codecs = 0; | |
2251 | for (i = 0; i < chip->max_codecs; i++) { | |
2252 | if (! (glob_sta & chip->codec_bit[i])) | |
2253 | continue; | |
2254 | if (chip->device_type == DEVICE_INTEL_ICH4) { | |
2255 | snd_intel8x0_codec_read_test(chip, codecs); | |
2256 | chip->ac97_sdin[codecs] = | |
2257 | igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK; | |
da3cec35 TI |
2258 | if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3)) |
2259 | chip->ac97_sdin[codecs] = 0; | |
84a43bd5 TI |
2260 | } else |
2261 | chip->ac97_sdin[codecs] = i; | |
2262 | codecs++; | |
1da177e4 | 2263 | } |
84a43bd5 TI |
2264 | chip->in_sdin_init = 0; |
2265 | if (! codecs) | |
2266 | codecs = 1; | |
1da177e4 LT |
2267 | } else { |
2268 | ops = &ali_bus_ops; | |
2269 | codecs = 1; | |
2270 | /* detect the secondary codec */ | |
2271 | for (i = 0; i < 100; i++) { | |
2272 | unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR)); | |
2273 | if (reg & 0x40) { | |
2274 | codecs = 2; | |
2275 | break; | |
2276 | } | |
2277 | iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40); | |
2278 | udelay(1); | |
2279 | } | |
2280 | } | |
2281 | if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0) | |
2282 | goto __err; | |
2283 | pbus->private_free = snd_intel8x0_mixer_free_ac97_bus; | |
1da177e4 LT |
2284 | if (ac97_clock >= 8000 && ac97_clock <= 48000) |
2285 | pbus->clock = ac97_clock; | |
2286 | /* FIXME: my test board doesn't work well with VRA... */ | |
2287 | if (chip->device_type == DEVICE_ALI) | |
2288 | pbus->no_vra = 1; | |
2289 | else | |
2290 | pbus->dra = 1; | |
2291 | chip->ac97_bus = pbus; | |
84a43bd5 | 2292 | chip->ncodecs = codecs; |
1da177e4 LT |
2293 | |
2294 | ac97.pci = chip->pci; | |
2295 | for (i = 0; i < codecs; i++) { | |
2296 | ac97.num = i; | |
2297 | if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) { | |
2298 | if (err != -EACCES) | |
f493e7bc TI |
2299 | dev_err(chip->card->dev, |
2300 | "Unable to initialize codec #%d\n", i); | |
1da177e4 LT |
2301 | if (i == 0) |
2302 | goto __err; | |
1da177e4 LT |
2303 | } |
2304 | } | |
2305 | /* tune up the primary codec */ | |
2306 | snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override); | |
2307 | /* enable separate SDINs for ICH4 */ | |
2308 | if (chip->device_type == DEVICE_INTEL_ICH4) | |
2309 | pbus->isdin = 1; | |
2310 | /* find the available PCM streams */ | |
2311 | i = ARRAY_SIZE(ac97_pcm_defs); | |
2312 | if (chip->device_type != DEVICE_INTEL_ICH4) | |
2313 | i -= 2; /* do not allocate PCM2IN and MIC2 */ | |
2314 | if (chip->spdif_idx < 0) | |
2315 | i--; /* do not allocate S/PDIF */ | |
2316 | err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs); | |
2317 | if (err < 0) | |
2318 | goto __err; | |
2319 | chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0]; | |
2320 | chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1]; | |
2321 | chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2]; | |
2322 | if (chip->spdif_idx >= 0) | |
2323 | chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3]; | |
2324 | if (chip->device_type == DEVICE_INTEL_ICH4) { | |
2325 | chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4]; | |
2326 | chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5]; | |
2327 | } | |
2328 | /* enable separate SDINs for ICH4 */ | |
2329 | if (chip->device_type == DEVICE_INTEL_ICH4) { | |
2330 | struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm; | |
2331 | u8 tmp = igetbyte(chip, ICHREG(SDM)); | |
2332 | tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK); | |
2333 | if (pcm) { | |
2334 | tmp |= ICH_SE; /* steer enable for multiple SDINs */ | |
2335 | tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT; | |
2336 | for (i = 1; i < 4; i++) { | |
2337 | if (pcm->r[0].codec[i]) { | |
2338 | tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT; | |
2339 | break; | |
2340 | } | |
2341 | } | |
2342 | } else { | |
2343 | tmp &= ~ICH_SE; /* steer disable */ | |
2344 | } | |
2345 | iputbyte(chip, ICHREG(SDM), tmp); | |
2346 | } | |
2347 | if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) { | |
2348 | chip->multi4 = 1; | |
4235a317 | 2349 | if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) { |
1da177e4 | 2350 | chip->multi6 = 1; |
4235a317 TI |
2351 | if (chip->ac97[0]->flags & AC97_HAS_8CH) |
2352 | chip->multi8 = 1; | |
2353 | } | |
1da177e4 LT |
2354 | } |
2355 | if (pbus->pcms[0].r[1].rslots[0]) { | |
2356 | chip->dra = 1; | |
2357 | } | |
2358 | if (chip->device_type == DEVICE_INTEL_ICH4) { | |
2359 | if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20) | |
2360 | chip->smp20bit = 1; | |
2361 | } | |
a9e99660 | 2362 | if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) { |
1da177e4 LT |
2363 | /* 48kHz only */ |
2364 | chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000; | |
2365 | } | |
a9e99660 | 2366 | if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) { |
1da177e4 LT |
2367 | /* use slot 10/11 for SPDIF */ |
2368 | u32 val; | |
2369 | val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK; | |
2370 | val |= ICH_PCM_SPDIF_1011; | |
2371 | iputdword(chip, ICHREG(GLOB_CNT), val); | |
2372 | snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4); | |
2373 | } | |
2374 | chip->in_ac97_init = 0; | |
2375 | return 0; | |
2376 | ||
2377 | __err: | |
2378 | /* clear the cold-reset bit for the next chance */ | |
2379 | if (chip->device_type != DEVICE_ALI) | |
6b75a9d8 TI |
2380 | iputdword(chip, ICHREG(GLOB_CNT), |
2381 | igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD); | |
1da177e4 LT |
2382 | return err; |
2383 | } | |
2384 | ||
2385 | ||
2386 | /* | |
2387 | * | |
2388 | */ | |
2389 | ||
6b75a9d8 | 2390 | static void do_ali_reset(struct intel8x0 *chip) |
1da177e4 LT |
2391 | { |
2392 | iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET); | |
2393 | iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383); | |
2394 | iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383); | |
2395 | iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383); | |
2396 | iputdword(chip, ICHREG(ALI_INTERFACECR), | |
d78bec21 | 2397 | ICH_ALI_IF_PI|ICH_ALI_IF_PO); |
1da177e4 LT |
2398 | iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000); |
2399 | iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000); | |
2400 | } | |
2401 | ||
e3e9c5e7 TLSC |
2402 | #ifdef CONFIG_SND_AC97_POWER_SAVE |
2403 | static struct snd_pci_quirk ich_chip_reset_mode[] = { | |
2404 | SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1), | |
2405 | { } /* end */ | |
2406 | }; | |
1da177e4 | 2407 | |
e3e9c5e7 TLSC |
2408 | static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip) |
2409 | { | |
2410 | unsigned int cnt; | |
1da177e4 | 2411 | /* ACLink on, 2 channels */ |
e3e9c5e7 TLSC |
2412 | |
2413 | if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode)) | |
2414 | return -EIO; | |
2415 | ||
1da177e4 LT |
2416 | cnt = igetdword(chip, ICHREG(GLOB_CNT)); |
2417 | cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK); | |
e3e9c5e7 | 2418 | |
6dbe6628 TI |
2419 | /* do cold reset - the full ac97 powerdown may leave the controller |
2420 | * in a warm state but actually it cannot communicate with the codec. | |
2421 | */ | |
2422 | iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD); | |
2423 | cnt = igetdword(chip, ICHREG(GLOB_CNT)); | |
2424 | udelay(10); | |
2425 | iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD); | |
2426 | msleep(1); | |
e3e9c5e7 TLSC |
2427 | return 0; |
2428 | } | |
2429 | #define snd_intel8x0_ich_chip_can_cold_reset(chip) \ | |
2430 | (!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode)) | |
6dbe6628 | 2431 | #else |
e1672800 | 2432 | #define snd_intel8x0_ich_chip_cold_reset(chip) 0 |
e3e9c5e7 TLSC |
2433 | #define snd_intel8x0_ich_chip_can_cold_reset(chip) (0) |
2434 | #endif | |
2435 | ||
2436 | static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip) | |
2437 | { | |
2438 | unsigned long end_time; | |
2439 | unsigned int cnt; | |
2440 | /* ACLink on, 2 channels */ | |
2441 | cnt = igetdword(chip, ICHREG(GLOB_CNT)); | |
2442 | cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK); | |
1da177e4 LT |
2443 | /* finish cold or do warm reset */ |
2444 | cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM; | |
2445 | iputdword(chip, ICHREG(GLOB_CNT), cnt); | |
2446 | end_time = (jiffies + (HZ / 4)) + 1; | |
2447 | do { | |
2448 | if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0) | |
e3e9c5e7 | 2449 | return 0; |
954bea35 | 2450 | schedule_timeout_uninterruptible(1); |
1da177e4 | 2451 | } while (time_after_eq(end_time, jiffies)); |
f493e7bc | 2452 | dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n", |
6b75a9d8 | 2453 | igetdword(chip, ICHREG(GLOB_CNT))); |
1da177e4 | 2454 | return -EIO; |
e3e9c5e7 TLSC |
2455 | } |
2456 | ||
2457 | static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing) | |
2458 | { | |
2459 | unsigned long end_time; | |
2460 | unsigned int status, nstatus; | |
2461 | unsigned int cnt; | |
2462 | int err; | |
2463 | ||
2464 | /* put logic to right state */ | |
2465 | /* first clear status bits */ | |
2466 | status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT; | |
2467 | if (chip->device_type == DEVICE_NFORCE) | |
2468 | status |= ICH_NVSPINT; | |
2469 | cnt = igetdword(chip, ICHREG(GLOB_STA)); | |
2470 | iputdword(chip, ICHREG(GLOB_STA), cnt & status); | |
2471 | ||
2472 | if (snd_intel8x0_ich_chip_can_cold_reset(chip)) | |
2473 | err = snd_intel8x0_ich_chip_cold_reset(chip); | |
2474 | else | |
2475 | err = snd_intel8x0_ich_chip_reset(chip); | |
2476 | if (err < 0) | |
2477 | return err; | |
1da177e4 | 2478 | |
1da177e4 LT |
2479 | if (probing) { |
2480 | /* wait for any codec ready status. | |
2481 | * Once it becomes ready it should remain ready | |
2482 | * as long as we do not disable the ac97 link. | |
2483 | */ | |
2484 | end_time = jiffies + HZ; | |
2485 | do { | |
6b75a9d8 | 2486 | status = igetdword(chip, ICHREG(GLOB_STA)) & |
84a43bd5 | 2487 | chip->codec_isr_bits; |
1da177e4 LT |
2488 | if (status) |
2489 | break; | |
954bea35 | 2490 | schedule_timeout_uninterruptible(1); |
1da177e4 LT |
2491 | } while (time_after_eq(end_time, jiffies)); |
2492 | if (! status) { | |
2493 | /* no codec is found */ | |
f493e7bc TI |
2494 | dev_err(chip->card->dev, |
2495 | "codec_ready: codec is not ready [0x%x]\n", | |
6b75a9d8 | 2496 | igetdword(chip, ICHREG(GLOB_STA))); |
1da177e4 LT |
2497 | return -EIO; |
2498 | } | |
2499 | ||
1da177e4 LT |
2500 | /* wait for other codecs ready status. */ |
2501 | end_time = jiffies + HZ / 4; | |
84a43bd5 TI |
2502 | while (status != chip->codec_isr_bits && |
2503 | time_after_eq(end_time, jiffies)) { | |
954bea35 | 2504 | schedule_timeout_uninterruptible(1); |
84a43bd5 TI |
2505 | status |= igetdword(chip, ICHREG(GLOB_STA)) & |
2506 | chip->codec_isr_bits; | |
1da177e4 LT |
2507 | } |
2508 | ||
2509 | } else { | |
2510 | /* resume phase */ | |
2511 | int i; | |
2512 | status = 0; | |
84a43bd5 | 2513 | for (i = 0; i < chip->ncodecs; i++) |
1da177e4 | 2514 | if (chip->ac97[i]) |
84a43bd5 | 2515 | status |= chip->codec_bit[chip->ac97_sdin[i]]; |
1da177e4 LT |
2516 | /* wait until all the probed codecs are ready */ |
2517 | end_time = jiffies + HZ; | |
2518 | do { | |
6b75a9d8 | 2519 | nstatus = igetdword(chip, ICHREG(GLOB_STA)) & |
84a43bd5 | 2520 | chip->codec_isr_bits; |
1da177e4 LT |
2521 | if (status == nstatus) |
2522 | break; | |
954bea35 | 2523 | schedule_timeout_uninterruptible(1); |
1da177e4 LT |
2524 | } while (time_after_eq(end_time, jiffies)); |
2525 | } | |
2526 | ||
2527 | if (chip->device_type == DEVICE_SIS) { | |
2528 | /* unmute the output on SIS7012 */ | |
2529 | iputword(chip, 0x4c, igetword(chip, 0x4c) | 1); | |
2530 | } | |
a9e99660 | 2531 | if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) { |
1da177e4 LT |
2532 | /* enable SPDIF interrupt */ |
2533 | unsigned int val; | |
2534 | pci_read_config_dword(chip->pci, 0x4c, &val); | |
2535 | val |= 0x1000000; | |
2536 | pci_write_config_dword(chip->pci, 0x4c, val); | |
2537 | } | |
2538 | return 0; | |
2539 | } | |
2540 | ||
6b75a9d8 | 2541 | static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing) |
1da177e4 LT |
2542 | { |
2543 | u32 reg; | |
2544 | int i = 0; | |
2545 | ||
2546 | reg = igetdword(chip, ICHREG(ALI_SCR)); | |
2547 | if ((reg & 2) == 0) /* Cold required */ | |
2548 | reg |= 2; | |
2549 | else | |
2550 | reg |= 1; /* Warm */ | |
2551 | reg &= ~0x80000000; /* ACLink on */ | |
2552 | iputdword(chip, ICHREG(ALI_SCR), reg); | |
2553 | ||
2554 | for (i = 0; i < HZ / 2; i++) { | |
2555 | if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO)) | |
2556 | goto __ok; | |
954bea35 | 2557 | schedule_timeout_uninterruptible(1); |
1da177e4 | 2558 | } |
f493e7bc | 2559 | dev_err(chip->card->dev, "AC'97 reset failed.\n"); |
1da177e4 LT |
2560 | if (probing) |
2561 | return -EIO; | |
2562 | ||
2563 | __ok: | |
2564 | for (i = 0; i < HZ / 2; i++) { | |
2565 | reg = igetdword(chip, ICHREG(ALI_RTSR)); | |
2566 | if (reg & 0x80) /* primary codec */ | |
2567 | break; | |
2568 | iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80); | |
954bea35 | 2569 | schedule_timeout_uninterruptible(1); |
1da177e4 LT |
2570 | } |
2571 | ||
2572 | do_ali_reset(chip); | |
2573 | return 0; | |
2574 | } | |
2575 | ||
6b75a9d8 | 2576 | static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing) |
1da177e4 | 2577 | { |
253b999f | 2578 | unsigned int i, timeout; |
1da177e4 LT |
2579 | int err; |
2580 | ||
2581 | if (chip->device_type != DEVICE_ALI) { | |
2582 | if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0) | |
2583 | return err; | |
2584 | iagetword(chip, 0); /* clear semaphore flag */ | |
2585 | } else { | |
2586 | if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0) | |
2587 | return err; | |
2588 | } | |
2589 | ||
2590 | /* disable interrupts */ | |
2591 | for (i = 0; i < chip->bdbars_count; i++) | |
2592 | iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); | |
2593 | /* reset channels */ | |
2594 | for (i = 0; i < chip->bdbars_count; i++) | |
2595 | iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); | |
253b999f JK |
2596 | for (i = 0; i < chip->bdbars_count; i++) { |
2597 | timeout = 100000; | |
2598 | while (--timeout != 0) { | |
2599 | if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0) | |
2600 | break; | |
2601 | } | |
2602 | if (timeout == 0) | |
f493e7bc | 2603 | dev_err(chip->card->dev, "reset of registers failed?\n"); |
253b999f | 2604 | } |
1da177e4 LT |
2605 | /* initialize Buffer Descriptor Lists */ |
2606 | for (i = 0; i < chip->bdbars_count; i++) | |
6b75a9d8 TI |
2607 | iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, |
2608 | chip->ichd[i].bdbar_addr); | |
1da177e4 LT |
2609 | return 0; |
2610 | } | |
2611 | ||
6b75a9d8 | 2612 | static int snd_intel8x0_free(struct intel8x0 *chip) |
1da177e4 LT |
2613 | { |
2614 | unsigned int i; | |
2615 | ||
2616 | if (chip->irq < 0) | |
2617 | goto __hw_end; | |
2618 | /* disable interrupts */ | |
2619 | for (i = 0; i < chip->bdbars_count; i++) | |
2620 | iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); | |
2621 | /* reset channels */ | |
2622 | for (i = 0; i < chip->bdbars_count; i++) | |
2623 | iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); | |
a9e99660 | 2624 | if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) { |
1da177e4 LT |
2625 | /* stop the spdif interrupt */ |
2626 | unsigned int val; | |
2627 | pci_read_config_dword(chip->pci, 0x4c, &val); | |
2628 | val &= ~0x1000000; | |
2629 | pci_write_config_dword(chip->pci, 0x4c, val); | |
2630 | } | |
2631 | /* --- */ | |
f000fd80 | 2632 | |
1da177e4 LT |
2633 | __hw_end: |
2634 | if (chip->irq >= 0) | |
6b75a9d8 | 2635 | free_irq(chip->irq, chip); |
1da177e4 LT |
2636 | if (chip->bdbars.area) { |
2637 | if (chip->fix_nocache) | |
2638 | fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0); | |
2639 | snd_dma_free_pages(&chip->bdbars); | |
2640 | } | |
3388c37e TI |
2641 | if (chip->addr) |
2642 | pci_iounmap(chip->pci, chip->addr); | |
2643 | if (chip->bmaddr) | |
2644 | pci_iounmap(chip->pci, chip->bmaddr); | |
1da177e4 LT |
2645 | pci_release_regions(chip->pci); |
2646 | pci_disable_device(chip->pci); | |
2647 | kfree(chip); | |
2648 | return 0; | |
2649 | } | |
2650 | ||
c7561cd8 | 2651 | #ifdef CONFIG_PM_SLEEP |
1da177e4 LT |
2652 | /* |
2653 | * power management | |
2654 | */ | |
68cb2b55 | 2655 | static int intel8x0_suspend(struct device *dev) |
1da177e4 | 2656 | { |
68cb2b55 | 2657 | struct snd_card *card = dev_get_drvdata(dev); |
5809c6c4 | 2658 | struct intel8x0 *chip = card->private_data; |
1da177e4 LT |
2659 | int i; |
2660 | ||
5809c6c4 | 2661 | snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); |
1da177e4 LT |
2662 | for (i = 0; i < chip->pcm_devs; i++) |
2663 | snd_pcm_suspend_all(chip->pcm[i]); | |
2664 | /* clear nocache */ | |
2665 | if (chip->fix_nocache) { | |
2666 | for (i = 0; i < chip->bdbars_count; i++) { | |
6b75a9d8 | 2667 | struct ichdev *ichdev = &chip->ichd[i]; |
1da177e4 | 2668 | if (ichdev->substream && ichdev->page_attr_changed) { |
6b75a9d8 | 2669 | struct snd_pcm_runtime *runtime = ichdev->substream->runtime; |
1da177e4 LT |
2670 | if (runtime->dma_area) |
2671 | fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); | |
2672 | } | |
2673 | } | |
2674 | } | |
84a43bd5 | 2675 | for (i = 0; i < chip->ncodecs; i++) |
5809c6c4 | 2676 | snd_ac97_suspend(chip->ac97[i]); |
52b72388 TI |
2677 | if (chip->device_type == DEVICE_INTEL_ICH4) |
2678 | chip->sdm_saved = igetbyte(chip, ICHREG(SDM)); | |
adbedd34 | 2679 | |
30b35399 | 2680 | if (chip->irq >= 0) { |
6b75a9d8 | 2681 | free_irq(chip->irq, chip); |
30b35399 TI |
2682 | chip->irq = -1; |
2683 | } | |
1da177e4 LT |
2684 | return 0; |
2685 | } | |
2686 | ||
68cb2b55 | 2687 | static int intel8x0_resume(struct device *dev) |
1da177e4 | 2688 | { |
68cb2b55 TI |
2689 | struct pci_dev *pci = to_pci_dev(dev); |
2690 | struct snd_card *card = dev_get_drvdata(dev); | |
5809c6c4 | 2691 | struct intel8x0 *chip = card->private_data; |
1da177e4 LT |
2692 | int i; |
2693 | ||
2078f38c | 2694 | snd_intel8x0_chip_init(chip, 0); |
30b35399 | 2695 | if (request_irq(pci->irq, snd_intel8x0_interrupt, |
934c2b6d | 2696 | IRQF_SHARED, KBUILD_MODNAME, chip)) { |
f493e7bc TI |
2697 | dev_err(dev, "unable to grab IRQ %d, disabling device\n", |
2698 | pci->irq); | |
30b35399 TI |
2699 | snd_card_disconnect(card); |
2700 | return -EIO; | |
2701 | } | |
5809c6c4 | 2702 | chip->irq = pci->irq; |
90158b83 | 2703 | synchronize_irq(chip->irq); |
1da177e4 | 2704 | |
52b72388 | 2705 | /* re-initialize mixer stuff */ |
a9e99660 | 2706 | if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) { |
52b72388 TI |
2707 | /* enable separate SDINs for ICH4 */ |
2708 | iputbyte(chip, ICHREG(SDM), chip->sdm_saved); | |
2709 | /* use slot 10/11 for SPDIF */ | |
2710 | iputdword(chip, ICHREG(GLOB_CNT), | |
2711 | (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) | | |
2712 | ICH_PCM_SPDIF_1011); | |
2713 | } | |
2714 | ||
1da177e4 LT |
2715 | /* refill nocache */ |
2716 | if (chip->fix_nocache) | |
2717 | fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1); | |
2718 | ||
84a43bd5 | 2719 | for (i = 0; i < chip->ncodecs; i++) |
5809c6c4 | 2720 | snd_ac97_resume(chip->ac97[i]); |
1da177e4 LT |
2721 | |
2722 | /* refill nocache */ | |
2723 | if (chip->fix_nocache) { | |
2724 | for (i = 0; i < chip->bdbars_count; i++) { | |
6b75a9d8 | 2725 | struct ichdev *ichdev = &chip->ichd[i]; |
1da177e4 | 2726 | if (ichdev->substream && ichdev->page_attr_changed) { |
6b75a9d8 | 2727 | struct snd_pcm_runtime *runtime = ichdev->substream->runtime; |
1da177e4 LT |
2728 | if (runtime->dma_area) |
2729 | fill_nocache(runtime->dma_area, runtime->dma_bytes, 1); | |
2730 | } | |
2731 | } | |
2732 | } | |
2733 | ||
1cfe43d2 TI |
2734 | /* resume status */ |
2735 | for (i = 0; i < chip->bdbars_count; i++) { | |
6b75a9d8 | 2736 | struct ichdev *ichdev = &chip->ichd[i]; |
1cfe43d2 TI |
2737 | unsigned long port = ichdev->reg_offset; |
2738 | if (! ichdev->substream || ! ichdev->suspended) | |
2739 | continue; | |
2740 | if (ichdev->ichd == ICHD_PCMOUT) | |
2741 | snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime); | |
2742 | iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr); | |
2743 | iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi); | |
2744 | iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ); | |
2745 | iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); | |
2746 | } | |
2747 | ||
5809c6c4 | 2748 | snd_power_change_state(card, SNDRV_CTL_POWER_D0); |
1da177e4 LT |
2749 | return 0; |
2750 | } | |
68cb2b55 TI |
2751 | |
2752 | static SIMPLE_DEV_PM_OPS(intel8x0_pm, intel8x0_suspend, intel8x0_resume); | |
2753 | #define INTEL8X0_PM_OPS &intel8x0_pm | |
2754 | #else | |
2755 | #define INTEL8X0_PM_OPS NULL | |
c7561cd8 | 2756 | #endif /* CONFIG_PM_SLEEP */ |
1da177e4 LT |
2757 | |
2758 | #define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */ | |
2759 | ||
e23e7a14 | 2760 | static void intel8x0_measure_ac97_clock(struct intel8x0 *chip) |
1da177e4 | 2761 | { |
6b75a9d8 TI |
2762 | struct snd_pcm_substream *subs; |
2763 | struct ichdev *ichdev; | |
1da177e4 | 2764 | unsigned long port; |
920e4ae3 | 2765 | unsigned long pos, pos1, t; |
2ec775e7 | 2766 | int civ, timeout = 1000, attempt = 1; |
2afe8be8 | 2767 | ktime_t start_time, stop_time; |
1da177e4 LT |
2768 | |
2769 | if (chip->ac97_bus->clock != 48000) | |
2770 | return; /* specified in module option */ | |
2771 | ||
2ec775e7 | 2772 | __again: |
1da177e4 LT |
2773 | subs = chip->pcm[0]->streams[0].substream; |
2774 | if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) { | |
f493e7bc TI |
2775 | dev_warn(chip->card->dev, |
2776 | "no playback buffer allocated - aborting measure ac97 clock\n"); | |
1da177e4 LT |
2777 | return; |
2778 | } | |
2779 | ichdev = &chip->ichd[ICHD_PCMOUT]; | |
2780 | ichdev->physbuf = subs->dma_buffer.addr; | |
29dab4fd | 2781 | ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE; |
1da177e4 LT |
2782 | ichdev->substream = NULL; /* don't process interrupts */ |
2783 | ||
2784 | /* set rate */ | |
2785 | if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) { | |
f493e7bc TI |
2786 | dev_err(chip->card->dev, "cannot set ac97 rate: clock = %d\n", |
2787 | chip->ac97_bus->clock); | |
1da177e4 LT |
2788 | return; |
2789 | } | |
2790 | snd_intel8x0_setup_periods(chip, ichdev); | |
2791 | port = ichdev->reg_offset; | |
2792 | spin_lock_irq(&chip->reg_lock); | |
2793 | chip->in_measurement = 1; | |
2794 | /* trigger */ | |
2795 | if (chip->device_type != DEVICE_ALI) | |
2796 | iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM); | |
2797 | else { | |
2798 | iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE); | |
2799 | iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot); | |
2800 | } | |
2afe8be8 | 2801 | start_time = ktime_get(); |
1da177e4 | 2802 | spin_unlock_irq(&chip->reg_lock); |
ef21ca24 | 2803 | msleep(50); |
1da177e4 LT |
2804 | spin_lock_irq(&chip->reg_lock); |
2805 | /* check the position */ | |
920e4ae3 JK |
2806 | do { |
2807 | civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV); | |
2808 | pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb); | |
2809 | if (pos1 == 0) { | |
2810 | udelay(10); | |
2811 | continue; | |
2812 | } | |
2813 | if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) && | |
2814 | pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb)) | |
2815 | break; | |
2816 | } while (timeout--); | |
da2436a2 JK |
2817 | if (pos1 == 0) { /* oops, this value is not reliable */ |
2818 | pos = 0; | |
2819 | } else { | |
2820 | pos = ichdev->fragsize1; | |
2821 | pos -= pos1 << ichdev->pos_shift; | |
2822 | pos += ichdev->position; | |
2823 | } | |
1da177e4 | 2824 | chip->in_measurement = 0; |
2afe8be8 | 2825 | stop_time = ktime_get(); |
1da177e4 LT |
2826 | /* stop */ |
2827 | if (chip->device_type == DEVICE_ALI) { | |
d78bec21 | 2828 | iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16)); |
1da177e4 LT |
2829 | iputbyte(chip, port + ICH_REG_OFF_CR, 0); |
2830 | while (igetbyte(chip, port + ICH_REG_OFF_CR)) | |
2831 | ; | |
2832 | } else { | |
2833 | iputbyte(chip, port + ICH_REG_OFF_CR, 0); | |
2834 | while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) | |
2835 | ; | |
2836 | } | |
2837 | iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); | |
2838 | spin_unlock_irq(&chip->reg_lock); | |
2839 | ||
da2436a2 | 2840 | if (pos == 0) { |
f493e7bc TI |
2841 | dev_err(chip->card->dev, |
2842 | "measure - unreliable DMA position..\n"); | |
2ec775e7 | 2843 | __retry: |
30fd9940 JK |
2844 | if (attempt < 3) { |
2845 | msleep(300); | |
2ec775e7 JK |
2846 | attempt++; |
2847 | goto __again; | |
2848 | } | |
30fd9940 | 2849 | goto __end; |
da2436a2 JK |
2850 | } |
2851 | ||
920e4ae3 | 2852 | pos /= 4; |
2afe8be8 | 2853 | t = ktime_us_delta(stop_time, start_time); |
f493e7bc TI |
2854 | dev_info(chip->card->dev, |
2855 | "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos); | |
1da177e4 | 2856 | if (t == 0) { |
f493e7bc | 2857 | dev_err(chip->card->dev, "?? calculation error..\n"); |
2ec775e7 | 2858 | goto __retry; |
1da177e4 | 2859 | } |
920e4ae3 | 2860 | pos *= 1000; |
1da177e4 | 2861 | pos = (pos / t) * 1000 + ((pos % t) * 1000) / t; |
2ec775e7 | 2862 | if (pos < 40000 || pos >= 60000) { |
1da177e4 | 2863 | /* abnormal value. hw problem? */ |
f493e7bc | 2864 | dev_info(chip->card->dev, "measured clock %ld rejected\n", pos); |
2ec775e7 JK |
2865 | goto __retry; |
2866 | } else if (pos > 40500 && pos < 41500) | |
920e4ae3 JK |
2867 | /* first exception - 41000Hz reference clock */ |
2868 | chip->ac97_bus->clock = 41000; | |
29dab4fd | 2869 | else if (pos > 43600 && pos < 44600) |
920e4ae3 JK |
2870 | /* second exception - 44100HZ reference clock */ |
2871 | chip->ac97_bus->clock = 44100; | |
1da177e4 LT |
2872 | else if (pos < 47500 || pos > 48500) |
2873 | /* not 48000Hz, tuning the clock.. */ | |
2874 | chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos; | |
30fd9940 | 2875 | __end: |
f493e7bc | 2876 | dev_info(chip->card->dev, "clocking to %d\n", chip->ac97_bus->clock); |
6dbe6628 | 2877 | snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0); |
1da177e4 LT |
2878 | } |
2879 | ||
e23e7a14 | 2880 | static struct snd_pci_quirk intel8x0_clock_list[] = { |
d695e4ea TI |
2881 | SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000), |
2882 | SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100), | |
2883 | SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000), | |
78fad343 | 2884 | SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000), |
d695e4ea TI |
2885 | SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000), |
2886 | { } /* terminator */ | |
2b3b5485 JK |
2887 | }; |
2888 | ||
e23e7a14 | 2889 | static int intel8x0_in_clock_list(struct intel8x0 *chip) |
2b3b5485 JK |
2890 | { |
2891 | struct pci_dev *pci = chip->pci; | |
d695e4ea TI |
2892 | const struct snd_pci_quirk *wl; |
2893 | ||
2894 | wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list); | |
2895 | if (!wl) | |
2896 | return 0; | |
f493e7bc | 2897 | dev_info(chip->card->dev, "white list rate for %04x:%04x is %i\n", |
d695e4ea TI |
2898 | pci->subsystem_vendor, pci->subsystem_device, wl->value); |
2899 | chip->ac97_bus->clock = wl->value; | |
2900 | return 1; | |
2b3b5485 JK |
2901 | } |
2902 | ||
6b75a9d8 TI |
2903 | static void snd_intel8x0_proc_read(struct snd_info_entry * entry, |
2904 | struct snd_info_buffer *buffer) | |
1da177e4 | 2905 | { |
6b75a9d8 | 2906 | struct intel8x0 *chip = entry->private_data; |
1da177e4 LT |
2907 | unsigned int tmp; |
2908 | ||
2909 | snd_iprintf(buffer, "Intel8x0\n\n"); | |
2910 | if (chip->device_type == DEVICE_ALI) | |
2911 | return; | |
2912 | tmp = igetdword(chip, ICHREG(GLOB_STA)); | |
2913 | snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT))); | |
2914 | snd_iprintf(buffer, "Global status : 0x%08x\n", tmp); | |
2915 | if (chip->device_type == DEVICE_INTEL_ICH4) | |
2916 | snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM))); | |
84a43bd5 TI |
2917 | snd_iprintf(buffer, "AC'97 codecs ready :"); |
2918 | if (tmp & chip->codec_isr_bits) { | |
2919 | int i; | |
2920 | static const char *codecs[3] = { | |
2921 | "primary", "secondary", "tertiary" | |
2922 | }; | |
2923 | for (i = 0; i < chip->max_codecs; i++) | |
2924 | if (tmp & chip->codec_bit[i]) | |
2925 | snd_iprintf(buffer, " %s", codecs[i]); | |
2926 | } else | |
2927 | snd_iprintf(buffer, " none"); | |
2928 | snd_iprintf(buffer, "\n"); | |
2929 | if (chip->device_type == DEVICE_INTEL_ICH4 || | |
2930 | chip->device_type == DEVICE_SIS) | |
1da177e4 LT |
2931 | snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n", |
2932 | chip->ac97_sdin[0], | |
2933 | chip->ac97_sdin[1], | |
2934 | chip->ac97_sdin[2]); | |
2935 | } | |
2936 | ||
e23e7a14 | 2937 | static void snd_intel8x0_proc_init(struct intel8x0 *chip) |
1da177e4 | 2938 | { |
6b75a9d8 | 2939 | struct snd_info_entry *entry; |
1da177e4 LT |
2940 | |
2941 | if (! snd_card_proc_new(chip->card, "intel8x0", &entry)) | |
bf850204 | 2942 | snd_info_set_text_ops(entry, chip, snd_intel8x0_proc_read); |
1da177e4 LT |
2943 | } |
2944 | ||
6b75a9d8 | 2945 | static int snd_intel8x0_dev_free(struct snd_device *device) |
1da177e4 | 2946 | { |
6b75a9d8 | 2947 | struct intel8x0 *chip = device->device_data; |
1da177e4 LT |
2948 | return snd_intel8x0_free(chip); |
2949 | } | |
2950 | ||
2951 | struct ich_reg_info { | |
2952 | unsigned int int_sta_mask; | |
2953 | unsigned int offset; | |
2954 | }; | |
2955 | ||
84a43bd5 TI |
2956 | static unsigned int ich_codec_bits[3] = { |
2957 | ICH_PCR, ICH_SCR, ICH_TCR | |
2958 | }; | |
2959 | static unsigned int sis_codec_bits[3] = { | |
2960 | ICH_PCR, ICH_SCR, ICH_SIS_TCR | |
2961 | }; | |
2962 | ||
e23e7a14 | 2963 | static int snd_intel8x0_inside_vm(struct pci_dev *pci) |
65c397d6 | 2964 | { |
7fb4f392 KO |
2965 | int result = inside_vm; |
2966 | char *msg = NULL; | |
65c397d6 | 2967 | |
7fb4f392 KO |
2968 | /* check module parameter first (override detection) */ |
2969 | if (result >= 0) { | |
2970 | msg = result ? "enable (forced) VM" : "disable (forced) VM"; | |
2971 | goto fini; | |
2972 | } | |
2973 | ||
2974 | /* detect KVM and Parallels virtual environments */ | |
2975 | result = kvm_para_available(); | |
2976 | #ifdef X86_FEATURE_HYPERVISOR | |
2977 | result = result || boot_cpu_has(X86_FEATURE_HYPERVISOR); | |
65c397d6 | 2978 | #endif |
7fb4f392 KO |
2979 | if (!result) |
2980 | goto fini; | |
2981 | ||
2982 | /* check for known (emulated) devices */ | |
2983 | if (pci->subsystem_vendor == 0x1af4 && | |
2984 | pci->subsystem_device == 0x1100) { | |
2985 | /* KVM emulated sound, PCI SSID: 1af4:1100 */ | |
2986 | msg = "enable KVM"; | |
2987 | } else if (pci->subsystem_vendor == 0x1ab8) { | |
2988 | /* Parallels VM emulated sound, PCI SSID: 1ab8:xxxx */ | |
2989 | msg = "enable Parallels VM"; | |
2990 | } else { | |
2991 | msg = "disable (unknown or VT-d) VM"; | |
2992 | result = 0; | |
65c397d6 KO |
2993 | } |
2994 | ||
7fb4f392 KO |
2995 | fini: |
2996 | if (msg != NULL) | |
f493e7bc | 2997 | dev_info(&pci->dev, "%s optimization\n", msg); |
65c397d6 KO |
2998 | |
2999 | return result; | |
3000 | } | |
3001 | ||
e23e7a14 BP |
3002 | static int snd_intel8x0_create(struct snd_card *card, |
3003 | struct pci_dev *pci, | |
3004 | unsigned long device_type, | |
3005 | struct intel8x0 **r_intel8x0) | |
1da177e4 | 3006 | { |
6b75a9d8 | 3007 | struct intel8x0 *chip; |
1da177e4 LT |
3008 | int err; |
3009 | unsigned int i; | |
3010 | unsigned int int_sta_masks; | |
6b75a9d8 TI |
3011 | struct ichdev *ichdev; |
3012 | static struct snd_device_ops ops = { | |
1da177e4 LT |
3013 | .dev_free = snd_intel8x0_dev_free, |
3014 | }; | |
3015 | ||
3016 | static unsigned int bdbars[] = { | |
3017 | 3, /* DEVICE_INTEL */ | |
3018 | 6, /* DEVICE_INTEL_ICH4 */ | |
3019 | 3, /* DEVICE_SIS */ | |
3020 | 6, /* DEVICE_ALI */ | |
3021 | 4, /* DEVICE_NFORCE */ | |
3022 | }; | |
3023 | static struct ich_reg_info intel_regs[6] = { | |
3024 | { ICH_PIINT, 0 }, | |
3025 | { ICH_POINT, 0x10 }, | |
3026 | { ICH_MCINT, 0x20 }, | |
3027 | { ICH_M2INT, 0x40 }, | |
3028 | { ICH_P2INT, 0x50 }, | |
3029 | { ICH_SPINT, 0x60 }, | |
3030 | }; | |
3031 | static struct ich_reg_info nforce_regs[4] = { | |
3032 | { ICH_PIINT, 0 }, | |
3033 | { ICH_POINT, 0x10 }, | |
3034 | { ICH_MCINT, 0x20 }, | |
3035 | { ICH_NVSPINT, 0x70 }, | |
3036 | }; | |
3037 | static struct ich_reg_info ali_regs[6] = { | |
3038 | { ALI_INT_PCMIN, 0x40 }, | |
3039 | { ALI_INT_PCMOUT, 0x50 }, | |
3040 | { ALI_INT_MICIN, 0x60 }, | |
3041 | { ALI_INT_CODECSPDIFOUT, 0x70 }, | |
3042 | { ALI_INT_SPDIFIN, 0xa0 }, | |
3043 | { ALI_INT_SPDIFOUT, 0xb0 }, | |
3044 | }; | |
3045 | struct ich_reg_info *tbl; | |
3046 | ||
3047 | *r_intel8x0 = NULL; | |
3048 | ||
3049 | if ((err = pci_enable_device(pci)) < 0) | |
3050 | return err; | |
3051 | ||
e560d8d8 | 3052 | chip = kzalloc(sizeof(*chip), GFP_KERNEL); |
1da177e4 LT |
3053 | if (chip == NULL) { |
3054 | pci_disable_device(pci); | |
3055 | return -ENOMEM; | |
3056 | } | |
3057 | spin_lock_init(&chip->reg_lock); | |
3058 | chip->device_type = device_type; | |
3059 | chip->card = card; | |
3060 | chip->pci = pci; | |
3061 | chip->irq = -1; | |
c829b052 TI |
3062 | |
3063 | /* module parameters */ | |
3064 | chip->buggy_irq = buggy_irq; | |
3065 | chip->buggy_semaphore = buggy_semaphore; | |
3066 | if (xbox) | |
3067 | chip->xbox = 1; | |
1da177e4 | 3068 | |
7fb4f392 | 3069 | chip->inside_vm = snd_intel8x0_inside_vm(pci); |
228cf793 | 3070 | |
1da177e4 LT |
3071 | if (pci->vendor == PCI_VENDOR_ID_INTEL && |
3072 | pci->device == PCI_DEVICE_ID_INTEL_440MX) | |
3073 | chip->fix_nocache = 1; /* enable workaround */ | |
3074 | ||
1da177e4 LT |
3075 | if ((err = pci_request_regions(pci, card->shortname)) < 0) { |
3076 | kfree(chip); | |
3077 | pci_disable_device(pci); | |
3078 | return err; | |
3079 | } | |
3080 | ||
3081 | if (device_type == DEVICE_ALI) { | |
3082 | /* ALI5455 has no ac97 region */ | |
3388c37e | 3083 | chip->bmaddr = pci_iomap(pci, 0, 0); |
1da177e4 LT |
3084 | goto port_inited; |
3085 | } | |
3086 | ||
3388c37e TI |
3087 | if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */ |
3088 | chip->addr = pci_iomap(pci, 2, 0); | |
3089 | else | |
3090 | chip->addr = pci_iomap(pci, 0, 0); | |
3091 | if (!chip->addr) { | |
f493e7bc | 3092 | dev_err(card->dev, "AC'97 space ioremap problem\n"); |
3388c37e TI |
3093 | snd_intel8x0_free(chip); |
3094 | return -EIO; | |
3095 | } | |
3096 | if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */ | |
3097 | chip->bmaddr = pci_iomap(pci, 3, 0); | |
3098 | else | |
3099 | chip->bmaddr = pci_iomap(pci, 1, 0); | |
30477555 SW |
3100 | |
3101 | port_inited: | |
3388c37e | 3102 | if (!chip->bmaddr) { |
f493e7bc | 3103 | dev_err(card->dev, "Controller space ioremap problem\n"); |
3388c37e TI |
3104 | snd_intel8x0_free(chip); |
3105 | return -EIO; | |
1da177e4 | 3106 | } |
1da177e4 LT |
3107 | chip->bdbars_count = bdbars[device_type]; |
3108 | ||
3109 | /* initialize offsets */ | |
3110 | switch (device_type) { | |
3111 | case DEVICE_NFORCE: | |
3112 | tbl = nforce_regs; | |
3113 | break; | |
3114 | case DEVICE_ALI: | |
3115 | tbl = ali_regs; | |
3116 | break; | |
3117 | default: | |
3118 | tbl = intel_regs; | |
3119 | break; | |
3120 | } | |
3121 | for (i = 0; i < chip->bdbars_count; i++) { | |
3122 | ichdev = &chip->ichd[i]; | |
3123 | ichdev->ichd = i; | |
3124 | ichdev->reg_offset = tbl[i].offset; | |
3125 | ichdev->int_sta_mask = tbl[i].int_sta_mask; | |
3126 | if (device_type == DEVICE_SIS) { | |
3127 | /* SiS 7012 swaps the registers */ | |
3128 | ichdev->roff_sr = ICH_REG_OFF_PICB; | |
3129 | ichdev->roff_picb = ICH_REG_OFF_SR; | |
3130 | } else { | |
3131 | ichdev->roff_sr = ICH_REG_OFF_SR; | |
3132 | ichdev->roff_picb = ICH_REG_OFF_PICB; | |
3133 | } | |
3134 | if (device_type == DEVICE_ALI) | |
3135 | ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10; | |
3136 | /* SIS7012 handles the pcm data in bytes, others are in samples */ | |
3137 | ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1; | |
3138 | } | |
3139 | ||
3140 | /* allocate buffer descriptor lists */ | |
3141 | /* the start of each lists must be aligned to 8 bytes */ | |
3142 | if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci), | |
3143 | chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2, | |
3144 | &chip->bdbars) < 0) { | |
3145 | snd_intel8x0_free(chip); | |
f493e7bc | 3146 | dev_err(card->dev, "cannot allocate buffer descriptors\n"); |
1da177e4 LT |
3147 | return -ENOMEM; |
3148 | } | |
3149 | /* tables must be aligned to 8 bytes here, but the kernel pages | |
3150 | are much bigger, so we don't care (on i386) */ | |
3151 | /* workaround for 440MX */ | |
3152 | if (chip->fix_nocache) | |
3153 | fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1); | |
3154 | int_sta_masks = 0; | |
3155 | for (i = 0; i < chip->bdbars_count; i++) { | |
3156 | ichdev = &chip->ichd[i]; | |
beef08a5 TI |
3157 | ichdev->bdbar = ((u32 *)chip->bdbars.area) + |
3158 | (i * ICH_MAX_FRAGS * 2); | |
3159 | ichdev->bdbar_addr = chip->bdbars.addr + | |
3160 | (i * sizeof(u32) * ICH_MAX_FRAGS * 2); | |
1da177e4 LT |
3161 | int_sta_masks |= ichdev->int_sta_mask; |
3162 | } | |
beef08a5 TI |
3163 | chip->int_sta_reg = device_type == DEVICE_ALI ? |
3164 | ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA; | |
1da177e4 LT |
3165 | chip->int_sta_mask = int_sta_masks; |
3166 | ||
beef08a5 | 3167 | pci_set_master(pci); |
beef08a5 | 3168 | |
84a43bd5 TI |
3169 | switch(chip->device_type) { |
3170 | case DEVICE_INTEL_ICH4: | |
3171 | /* ICH4 can have three codecs */ | |
3172 | chip->max_codecs = 3; | |
3173 | chip->codec_bit = ich_codec_bits; | |
3174 | chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI; | |
3175 | break; | |
3176 | case DEVICE_SIS: | |
3177 | /* recent SIS7012 can have three codecs */ | |
3178 | chip->max_codecs = 3; | |
3179 | chip->codec_bit = sis_codec_bits; | |
3180 | chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI; | |
3181 | break; | |
3182 | default: | |
3183 | /* others up to two codecs */ | |
3184 | chip->max_codecs = 2; | |
3185 | chip->codec_bit = ich_codec_bits; | |
3186 | chip->codec_ready_bits = ICH_PRI | ICH_SRI; | |
3187 | break; | |
3188 | } | |
3189 | for (i = 0; i < chip->max_codecs; i++) | |
3190 | chip->codec_isr_bits |= chip->codec_bit[i]; | |
3191 | ||
1da177e4 LT |
3192 | if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) { |
3193 | snd_intel8x0_free(chip); | |
3194 | return err; | |
3195 | } | |
3196 | ||
2078f38c TI |
3197 | /* request irq after initializaing int_sta_mask, etc */ |
3198 | if (request_irq(pci->irq, snd_intel8x0_interrupt, | |
934c2b6d | 3199 | IRQF_SHARED, KBUILD_MODNAME, chip)) { |
f493e7bc | 3200 | dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); |
2078f38c TI |
3201 | snd_intel8x0_free(chip); |
3202 | return -EBUSY; | |
3203 | } | |
3204 | chip->irq = pci->irq; | |
3205 | ||
1da177e4 LT |
3206 | if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { |
3207 | snd_intel8x0_free(chip); | |
3208 | return err; | |
3209 | } | |
3210 | ||
1da177e4 LT |
3211 | *r_intel8x0 = chip; |
3212 | return 0; | |
3213 | } | |
3214 | ||
3215 | static struct shortname_table { | |
3216 | unsigned int id; | |
3217 | const char *s; | |
e23e7a14 | 3218 | } shortnames[] = { |
8cdfd251 TI |
3219 | { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" }, |
3220 | { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" }, | |
3221 | { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" }, | |
1da177e4 | 3222 | { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" }, |
8cdfd251 TI |
3223 | { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" }, |
3224 | { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" }, | |
3225 | { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" }, | |
1da177e4 LT |
3226 | { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" }, |
3227 | { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" }, | |
3228 | { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" }, | |
3437c5df | 3229 | { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" }, |
1da177e4 | 3230 | { PCI_DEVICE_ID_SI_7012, "SiS SI7012" }, |
8cdfd251 | 3231 | { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" }, |
1da177e4 LT |
3232 | { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" }, |
3233 | { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" }, | |
3234 | { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" }, | |
3235 | { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" }, | |
3236 | { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" }, | |
3237 | { 0x003a, "NVidia MCP04" }, | |
3238 | { 0x746d, "AMD AMD8111" }, | |
3239 | { 0x7445, "AMD AMD768" }, | |
3240 | { 0x5455, "ALi M5455" }, | |
3241 | { 0, NULL }, | |
3242 | }; | |
3243 | ||
e23e7a14 | 3244 | static struct snd_pci_quirk spdif_aclink_defaults[] = { |
a9e99660 TI |
3245 | SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1), |
3246 | { } /* end */ | |
3247 | }; | |
3248 | ||
3249 | /* look up white/black list for SPDIF over ac-link */ | |
e23e7a14 | 3250 | static int check_default_spdif_aclink(struct pci_dev *pci) |
a9e99660 TI |
3251 | { |
3252 | const struct snd_pci_quirk *w; | |
3253 | ||
3254 | w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults); | |
3255 | if (w) { | |
3256 | if (w->value) | |
f493e7bc TI |
3257 | dev_dbg(&pci->dev, |
3258 | "Using SPDIF over AC-Link for %s\n", | |
86b27237 | 3259 | snd_pci_quirk_name(w)); |
a9e99660 | 3260 | else |
f493e7bc TI |
3261 | dev_dbg(&pci->dev, |
3262 | "Using integrated SPDIF DMA for %s\n", | |
86b27237 | 3263 | snd_pci_quirk_name(w)); |
a9e99660 TI |
3264 | return w->value; |
3265 | } | |
3266 | return 0; | |
3267 | } | |
3268 | ||
e23e7a14 BP |
3269 | static int snd_intel8x0_probe(struct pci_dev *pci, |
3270 | const struct pci_device_id *pci_id) | |
1da177e4 | 3271 | { |
6b75a9d8 TI |
3272 | struct snd_card *card; |
3273 | struct intel8x0 *chip; | |
1da177e4 LT |
3274 | int err; |
3275 | struct shortname_table *name; | |
3276 | ||
60c5772b | 3277 | err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card); |
e58de7ba TI |
3278 | if (err < 0) |
3279 | return err; | |
1da177e4 | 3280 | |
a9e99660 TI |
3281 | if (spdif_aclink < 0) |
3282 | spdif_aclink = check_default_spdif_aclink(pci); | |
3283 | ||
3284 | strcpy(card->driver, "ICH"); | |
3285 | if (!spdif_aclink) { | |
3286 | switch (pci_id->driver_data) { | |
3287 | case DEVICE_NFORCE: | |
3288 | strcpy(card->driver, "NFORCE"); | |
3289 | break; | |
3290 | case DEVICE_INTEL_ICH4: | |
3291 | strcpy(card->driver, "ICH4"); | |
3292 | } | |
1da177e4 LT |
3293 | } |
3294 | ||
3295 | strcpy(card->shortname, "Intel ICH"); | |
3296 | for (name = shortnames; name->id; name++) { | |
3297 | if (pci->device == name->id) { | |
3298 | strcpy(card->shortname, name->s); | |
3299 | break; | |
3300 | } | |
3301 | } | |
3302 | ||
beef08a5 TI |
3303 | if (buggy_irq < 0) { |
3304 | /* some Nforce[2] and ICH boards have problems with IRQ handling. | |
3305 | * Needs to return IRQ_HANDLED for unknown irqs. | |
3306 | */ | |
3307 | if (pci_id->driver_data == DEVICE_NFORCE) | |
3308 | buggy_irq = 1; | |
3309 | else | |
3310 | buggy_irq = 0; | |
3311 | } | |
3312 | ||
a06147d2 | 3313 | if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data, |
c829b052 | 3314 | &chip)) < 0) { |
1da177e4 LT |
3315 | snd_card_free(card); |
3316 | return err; | |
3317 | } | |
5809c6c4 | 3318 | card->private_data = chip; |
1da177e4 | 3319 | |
b7fe4622 | 3320 | if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) { |
1da177e4 LT |
3321 | snd_card_free(card); |
3322 | return err; | |
3323 | } | |
3324 | if ((err = snd_intel8x0_pcm(chip)) < 0) { | |
3325 | snd_card_free(card); | |
3326 | return err; | |
3327 | } | |
3328 | ||
3329 | snd_intel8x0_proc_init(chip); | |
3330 | ||
3331 | snprintf(card->longname, sizeof(card->longname), | |
3388c37e TI |
3332 | "%s with %s at irq %i", card->shortname, |
3333 | snd_ac97_get_short_name(chip->ac97[0]), chip->irq); | |
1da177e4 | 3334 | |
2b3b5485 JK |
3335 | if (ac97_clock == 0 || ac97_clock == 1) { |
3336 | if (ac97_clock == 0) { | |
3337 | if (intel8x0_in_clock_list(chip) == 0) | |
3338 | intel8x0_measure_ac97_clock(chip); | |
3339 | } else { | |
3340 | intel8x0_measure_ac97_clock(chip); | |
3341 | } | |
3342 | } | |
1da177e4 LT |
3343 | |
3344 | if ((err = snd_card_register(card)) < 0) { | |
3345 | snd_card_free(card); | |
3346 | return err; | |
3347 | } | |
3348 | pci_set_drvdata(pci, card); | |
1da177e4 LT |
3349 | return 0; |
3350 | } | |
3351 | ||
e23e7a14 | 3352 | static void snd_intel8x0_remove(struct pci_dev *pci) |
1da177e4 LT |
3353 | { |
3354 | snd_card_free(pci_get_drvdata(pci)); | |
1da177e4 LT |
3355 | } |
3356 | ||
e9f66d9b | 3357 | static struct pci_driver intel8x0_driver = { |
3733e424 | 3358 | .name = KBUILD_MODNAME, |
1da177e4 LT |
3359 | .id_table = snd_intel8x0_ids, |
3360 | .probe = snd_intel8x0_probe, | |
e23e7a14 | 3361 | .remove = snd_intel8x0_remove, |
68cb2b55 TI |
3362 | .driver = { |
3363 | .pm = INTEL8X0_PM_OPS, | |
3364 | }, | |
1da177e4 LT |
3365 | }; |
3366 | ||
e9f66d9b | 3367 | module_pci_driver(intel8x0_driver); |