projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ALSA: hda - Mute the right widget in auto_mute_via_amp mode
[deliverable/linux.git] / sound / pci / rme96.c
CommitLineData
1da177e4
LT		 1/*
2 * ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio
3 * interfaces
4 *
5 * Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se>
6 *
7 * Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control
8 * code.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
1da177e4
LT		 26#include <linux/delay.h>
27#include <linux/init.h>
28#include <linux/interrupt.h>
29#include <linux/pci.h>
65a77217 30#include <linux/module.h>
1da177e4
LT		 31
32#include <sound/core.h>
33#include <sound/info.h>
34#include <sound/control.h>
35#include <sound/pcm.h>
36#include <sound/pcm_params.h>
37#include <sound/asoundef.h>
38#include <sound/initval.h>
39
40#include <asm/io.h>
41
42/* note, two last pcis should be equal, it is not a bug */
43
44MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>");
45MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, "
46 "Digi96/8 PAD");
47MODULE_LICENSE("GPL");
48MODULE_SUPPORTED_DEVICE("{{RME,Digi96},"
49 "{RME,Digi96/8},"
50 "{RME,Digi96/8 PRO},"
51 "{RME,Digi96/8 PST},"
52 "{RME,Digi96/8 PAD}}");
53
54static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
55static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
a67ff6a5 56static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
1da177e4
LT		 57
58module_param_array(index, int, NULL, 0444);
59MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard.");
60module_param_array(id, charp, NULL, 0444);
61MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard.");
62module_param_array(enable, bool, NULL, 0444);
63MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard.");
64
65/*
66 * Defines for RME Digi96 series, from internal RME reference documents
67 * dated 12.01.00
68 */
69
70#define RME96_SPDIF_NCHANNELS 2
71
72/* Playback and capture buffer size */
73#define RME96_BUFFER_SIZE 0x10000
74
75/* IO area size */
76#define RME96_IO_SIZE 0x60000
77
78/* IO area offsets */
79#define RME96_IO_PLAY_BUFFER 0x0
80#define RME96_IO_REC_BUFFER 0x10000
81#define RME96_IO_CONTROL_REGISTER 0x20000
82#define RME96_IO_ADDITIONAL_REG 0x20004
83#define RME96_IO_CONFIRM_PLAY_IRQ 0x20008
84#define RME96_IO_CONFIRM_REC_IRQ 0x2000C
85#define RME96_IO_SET_PLAY_POS 0x40000
86#define RME96_IO_RESET_PLAY_POS 0x4FFFC
87#define RME96_IO_SET_REC_POS 0x50000
88#define RME96_IO_RESET_REC_POS 0x5FFFC
89#define RME96_IO_GET_PLAY_POS 0x20000
90#define RME96_IO_GET_REC_POS 0x30000
91
92/* Write control register bits */
93#define RME96_WCR_START (1 << 0)
94#define RME96_WCR_START_2 (1 << 1)
95#define RME96_WCR_GAIN_0 (1 << 2)
96#define RME96_WCR_GAIN_1 (1 << 3)
97#define RME96_WCR_MODE24 (1 << 4)
98#define RME96_WCR_MODE24_2 (1 << 5)
99#define RME96_WCR_BM (1 << 6)
100#define RME96_WCR_BM_2 (1 << 7)
101#define RME96_WCR_ADAT (1 << 8)
102#define RME96_WCR_FREQ_0 (1 << 9)
103#define RME96_WCR_FREQ_1 (1 << 10)
104#define RME96_WCR_DS (1 << 11)
105#define RME96_WCR_PRO (1 << 12)
106#define RME96_WCR_EMP (1 << 13)
107#define RME96_WCR_SEL (1 << 14)
108#define RME96_WCR_MASTER (1 << 15)
109#define RME96_WCR_PD (1 << 16)
110#define RME96_WCR_INP_0 (1 << 17)
111#define RME96_WCR_INP_1 (1 << 18)
112#define RME96_WCR_THRU_0 (1 << 19)
113#define RME96_WCR_THRU_1 (1 << 20)
114#define RME96_WCR_THRU_2 (1 << 21)
115#define RME96_WCR_THRU_3 (1 << 22)
116#define RME96_WCR_THRU_4 (1 << 23)
117#define RME96_WCR_THRU_5 (1 << 24)
118#define RME96_WCR_THRU_6 (1 << 25)
119#define RME96_WCR_THRU_7 (1 << 26)
120#define RME96_WCR_DOLBY (1 << 27)
121#define RME96_WCR_MONITOR_0 (1 << 28)
122#define RME96_WCR_MONITOR_1 (1 << 29)
123#define RME96_WCR_ISEL (1 << 30)
124#define RME96_WCR_IDIS (1 << 31)
125
126#define RME96_WCR_BITPOS_GAIN_0 2
127#define RME96_WCR_BITPOS_GAIN_1 3
128#define RME96_WCR_BITPOS_FREQ_0 9
129#define RME96_WCR_BITPOS_FREQ_1 10
130#define RME96_WCR_BITPOS_INP_0 17
131#define RME96_WCR_BITPOS_INP_1 18
132#define RME96_WCR_BITPOS_MONITOR_0 28
133#define RME96_WCR_BITPOS_MONITOR_1 29
134
135/* Read control register bits */
136#define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF
137#define RME96_RCR_IRQ_2 (1 << 16)
138#define RME96_RCR_T_OUT (1 << 17)
139#define RME96_RCR_DEV_ID_0 (1 << 21)
140#define RME96_RCR_DEV_ID_1 (1 << 22)
141#define RME96_RCR_LOCK (1 << 23)
142#define RME96_RCR_VERF (1 << 26)
143#define RME96_RCR_F0 (1 << 27)
144#define RME96_RCR_F1 (1 << 28)
145#define RME96_RCR_F2 (1 << 29)
146#define RME96_RCR_AUTOSYNC (1 << 30)
147#define RME96_RCR_IRQ (1 << 31)
148
149#define RME96_RCR_BITPOS_F0 27
150#define RME96_RCR_BITPOS_F1 28
151#define RME96_RCR_BITPOS_F2 29
152
25985edc 153/* Additional register bits */
1da177e4
LT		 154#define RME96_AR_WSEL (1 << 0)
155#define RME96_AR_ANALOG (1 << 1)
156#define RME96_AR_FREQPAD_0 (1 << 2)
157#define RME96_AR_FREQPAD_1 (1 << 3)
158#define RME96_AR_FREQPAD_2 (1 << 4)
159#define RME96_AR_PD2 (1 << 5)
160#define RME96_AR_DAC_EN (1 << 6)
161#define RME96_AR_CLATCH (1 << 7)
162#define RME96_AR_CCLK (1 << 8)
163#define RME96_AR_CDATA (1 << 9)
164
165#define RME96_AR_BITPOS_F0 2
166#define RME96_AR_BITPOS_F1 3
167#define RME96_AR_BITPOS_F2 4
168
169/* Monitor tracks */
170#define RME96_MONITOR_TRACKS_1_2 0
171#define RME96_MONITOR_TRACKS_3_4 1
172#define RME96_MONITOR_TRACKS_5_6 2
173#define RME96_MONITOR_TRACKS_7_8 3
174
175/* Attenuation */
176#define RME96_ATTENUATION_0 0
177#define RME96_ATTENUATION_6 1
178#define RME96_ATTENUATION_12 2
179#define RME96_ATTENUATION_18 3
180
181/* Input types */
182#define RME96_INPUT_OPTICAL 0
183#define RME96_INPUT_COAXIAL 1
184#define RME96_INPUT_INTERNAL 2
185#define RME96_INPUT_XLR 3
186#define RME96_INPUT_ANALOG 4
187
188/* Clock modes */
189#define RME96_CLOCKMODE_SLAVE 0
190#define RME96_CLOCKMODE_MASTER 1
191#define RME96_CLOCKMODE_WORDCLOCK 2
192
193/* Block sizes in bytes */
194#define RME96_SMALL_BLOCK_SIZE 2048
195#define RME96_LARGE_BLOCK_SIZE 8192
196
197/* Volume control */
198#define RME96_AD1852_VOL_BITS 14
199#define RME96_AD1855_VOL_BITS 10
200
1da177e4 201
a3aefd88 202struct rme96 {
1da177e4
LT		 203 spinlock_t lock;
204 int irq;
205 unsigned long port;
206 void __iomem *iobase;
207
208 u32 wcreg; /* cached write control register value */
209 u32 wcreg_spdif; /* S/PDIF setup */
210 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */
211 u32 rcreg; /* cached read control register value */
212 u32 areg; /* cached additional register value */
213 u16 vol[2]; /* cached volume of analog output */
214
215 u8 rev; /* card revision number */
216
a3aefd88
TI		 217 struct snd_pcm_substream *playback_substream;
218 struct snd_pcm_substream *capture_substream;
1da177e4
LT		 219
220 int playback_frlog; /* log2 of framesize */
221 int capture_frlog;
222
223 size_t playback_periodsize; /* in bytes, zero if not used */
224 size_t capture_periodsize; /* in bytes, zero if not used */
225
a3aefd88
TI		 226 struct snd_card *card;
227 struct snd_pcm *spdif_pcm;
228 struct snd_pcm *adat_pcm;
1da177e4 229 struct pci_dev *pci;
a3aefd88
TI		 230 struct snd_kcontrol *spdif_ctl;
231};
1da177e4 232
cebe41d4 233static DEFINE_PCI_DEVICE_TABLE(snd_rme96_ids) = {
28d27aae
JP		 234 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96), 0, },
235 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8), 0, },
236 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PRO), 0, },
237 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST), 0, },
1da177e4
LT		 238 { 0, }
239};
240
241MODULE_DEVICE_TABLE(pci, snd_rme96_ids);
242
243#define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
244#define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
8b7fc421
RD		 245#define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
246#define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \
247 (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
1da177e4 248#define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4)
8b7fc421
RD		 249#define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \
250 ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2))
1da177e4
LT		 251#define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1)
252
253static int
a3aefd88 254snd_rme96_playback_prepare(struct snd_pcm_substream *substream);
1da177e4
LT		 255
256static int
a3aefd88 257snd_rme96_capture_prepare(struct snd_pcm_substream *substream);
1da177e4
LT		 258
259static int
a3aefd88 260snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 261 int cmd);
262
263static int
a3aefd88 264snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 265 int cmd);
266
267static snd_pcm_uframes_t
a3aefd88 268snd_rme96_playback_pointer(struct snd_pcm_substream *substream);
1da177e4
LT		 269
270static snd_pcm_uframes_t
a3aefd88 271snd_rme96_capture_pointer(struct snd_pcm_substream *substream);
1da177e4 272
e23e7a14 273static void snd_rme96_proc_init(struct rme96 *rme96);
1da177e4
LT		 274
275static int
a3aefd88
TI		 276snd_rme96_create_switches(struct snd_card *card,
277 struct rme96 *rme96);
1da177e4
LT		 278
279static int
a3aefd88 280snd_rme96_getinputtype(struct rme96 *rme96);
1da177e4
LT		 281
282static inline unsigned int
a3aefd88 283snd_rme96_playback_ptr(struct rme96 *rme96)
1da177e4
LT		 284{
285 return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
286 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog;
287}
288
289static inline unsigned int
a3aefd88 290snd_rme96_capture_ptr(struct rme96 *rme96)
1da177e4
LT		 291{
292 return (readl(rme96->iobase + RME96_IO_GET_REC_POS)
293 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog;
294}
295
1da177e4 296static int
a3aefd88 297snd_rme96_playback_silence(struct snd_pcm_substream *substream,
1da177e4
LT		 298 int channel, /* not used (interleaved data) */
299 snd_pcm_uframes_t pos,
300 snd_pcm_uframes_t count)
301{
a3aefd88 302 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 303 count <<= rme96->playback_frlog;
304 pos <<= rme96->playback_frlog;
305 memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
306 0, count);
307 return 0;
308}
309
310static int
a3aefd88 311snd_rme96_playback_copy(struct snd_pcm_substream *substream,
1da177e4
LT		 312 int channel, /* not used (interleaved data) */
313 snd_pcm_uframes_t pos,
314 void __user *src,
315 snd_pcm_uframes_t count)
316{
a3aefd88 317 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 318 count <<= rme96->playback_frlog;
319 pos <<= rme96->playback_frlog;
320 copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src,
321 count);
322 return 0;
323}
324
325static int
a3aefd88 326snd_rme96_capture_copy(struct snd_pcm_substream *substream,
1da177e4
LT		 327 int channel, /* not used (interleaved data) */
328 snd_pcm_uframes_t pos,
329 void __user *dst,
330 snd_pcm_uframes_t count)
331{
a3aefd88 332 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 333 count <<= rme96->capture_frlog;
334 pos <<= rme96->capture_frlog;
335 copy_to_user_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos,
336 count);
337 return 0;
338}
339
340/*
7f927fcc 341 * Digital output capabilities (S/PDIF)
1da177e4 342 */
a3aefd88 343static struct snd_pcm_hardware snd_rme96_playback_spdif_info =
1da177e4
LT		 344{
345 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
346 SNDRV_PCM_INFO_MMAP_VALID |
347 SNDRV_PCM_INFO_INTERLEAVED |
348 SNDRV_PCM_INFO_PAUSE),
349 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
350 SNDRV_PCM_FMTBIT_S32_LE),
351 .rates = (SNDRV_PCM_RATE_32000 |
352 SNDRV_PCM_RATE_44100 |
353 SNDRV_PCM_RATE_48000 |
354 SNDRV_PCM_RATE_64000 |
355 SNDRV_PCM_RATE_88200 |
356 SNDRV_PCM_RATE_96000),
357 .rate_min = 32000,
358 .rate_max = 96000,
359 .channels_min = 2,
360 .channels_max = 2,
361 .buffer_bytes_max = RME96_BUFFER_SIZE,
362 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
363 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
364 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
365 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
366 .fifo_size = 0,
367};
368
369/*
7f927fcc 370 * Digital input capabilities (S/PDIF)
1da177e4 371 */
a3aefd88 372static struct snd_pcm_hardware snd_rme96_capture_spdif_info =
1da177e4
LT		 373{
374 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
375 SNDRV_PCM_INFO_MMAP_VALID |
376 SNDRV_PCM_INFO_INTERLEAVED |
377 SNDRV_PCM_INFO_PAUSE),
378 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
379 SNDRV_PCM_FMTBIT_S32_LE),
380 .rates = (SNDRV_PCM_RATE_32000 |
381 SNDRV_PCM_RATE_44100 |
382 SNDRV_PCM_RATE_48000 |
383 SNDRV_PCM_RATE_64000 |
384 SNDRV_PCM_RATE_88200 |
385 SNDRV_PCM_RATE_96000),
386 .rate_min = 32000,
387 .rate_max = 96000,
388 .channels_min = 2,
389 .channels_max = 2,
390 .buffer_bytes_max = RME96_BUFFER_SIZE,
391 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
392 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
393 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
394 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
395 .fifo_size = 0,
396};
397
398/*
7f927fcc 399 * Digital output capabilities (ADAT)
1da177e4 400 */
a3aefd88 401static struct snd_pcm_hardware snd_rme96_playback_adat_info =
1da177e4
LT		 402{
403 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
404 SNDRV_PCM_INFO_MMAP_VALID |
405 SNDRV_PCM_INFO_INTERLEAVED |
406 SNDRV_PCM_INFO_PAUSE),
407 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
408 SNDRV_PCM_FMTBIT_S32_LE),
409 .rates = (SNDRV_PCM_RATE_44100 |
410 SNDRV_PCM_RATE_48000),
411 .rate_min = 44100,
412 .rate_max = 48000,
413 .channels_min = 8,
414 .channels_max = 8,
415 .buffer_bytes_max = RME96_BUFFER_SIZE,
416 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
417 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
418 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
419 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
420 .fifo_size = 0,
421};
422
423/*
7f927fcc 424 * Digital input capabilities (ADAT)
1da177e4 425 */
a3aefd88 426static struct snd_pcm_hardware snd_rme96_capture_adat_info =
1da177e4
LT		 427{
428 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
429 SNDRV_PCM_INFO_MMAP_VALID |
430 SNDRV_PCM_INFO_INTERLEAVED |
431 SNDRV_PCM_INFO_PAUSE),
432 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
433 SNDRV_PCM_FMTBIT_S32_LE),
434 .rates = (SNDRV_PCM_RATE_44100 |
435 SNDRV_PCM_RATE_48000),
436 .rate_min = 44100,
437 .rate_max = 48000,
438 .channels_min = 8,
439 .channels_max = 8,
440 .buffer_bytes_max = RME96_BUFFER_SIZE,
441 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
442 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
443 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
444 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
445 .fifo_size = 0,
446};
447
448/*
449 * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface
450 * of the AD1852 or AD1852 D/A converter on the board. CDATA must be set up
451 * on the falling edge of CCLK and be stable on the rising edge. The rising
452 * edge of CLATCH after the last data bit clocks in the whole data word.
453 * A fast processor could probably drive the SPI interface faster than the
454 * DAC can handle (3MHz for the 1855, unknown for the 1852). The udelay(1)
455 * limits the data rate to 500KHz and only causes a delay of 33 microsecs.
456 *
457 * NOTE: increased delay from 1 to 10, since there where problems setting
458 * the volume.
459 */
460static void
a3aefd88 461snd_rme96_write_SPI(struct rme96 *rme96, u16 val)
1da177e4
LT		 462{
463 int i;
464
465 for (i = 0; i < 16; i++) {
466 if (val & 0x8000) {
467 rme96->areg |= RME96_AR_CDATA;
468 } else {
469 rme96->areg &= ~RME96_AR_CDATA;
470 }
471 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH);
472 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
473 udelay(10);
474 rme96->areg |= RME96_AR_CCLK;
475 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
476 udelay(10);
477 val <<= 1;
478 }
479 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA);
480 rme96->areg |= RME96_AR_CLATCH;
481 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
482 udelay(10);
483 rme96->areg &= ~RME96_AR_CLATCH;
484 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
485}
486
487static void
a3aefd88 488snd_rme96_apply_dac_volume(struct rme96 *rme96)
1da177e4
LT		 489{
490 if (RME96_DAC_IS_1852(rme96)) {
491 snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0);
492 snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2);
493 } else if (RME96_DAC_IS_1855(rme96)) {
494 snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000);
495 snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400);
496 }
497}
498
499static void
a3aefd88 500snd_rme96_reset_dac(struct rme96 *rme96)
1da177e4
LT		 501{
502 writel(rme96->wcreg | RME96_WCR_PD,
503 rme96->iobase + RME96_IO_CONTROL_REGISTER);
504 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
505}
506
507static int
a3aefd88 508snd_rme96_getmontracks(struct rme96 *rme96)
1da177e4
LT		 509{
510 return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
511 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
512}
513
514static int
a3aefd88 515snd_rme96_setmontracks(struct rme96 *rme96,
1da177e4
LT		 516 int montracks)
517{
518 if (montracks & 1) {
519 rme96->wcreg |= RME96_WCR_MONITOR_0;
520 } else {
521 rme96->wcreg &= ~RME96_WCR_MONITOR_0;
522 }
523 if (montracks & 2) {
524 rme96->wcreg |= RME96_WCR_MONITOR_1;
525 } else {
526 rme96->wcreg &= ~RME96_WCR_MONITOR_1;
527 }
528 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
529 return 0;
530}
531
532static int
a3aefd88 533snd_rme96_getattenuation(struct rme96 *rme96)
1da177e4
LT		 534{
535 return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
536 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
537}
538
539static int
a3aefd88 540snd_rme96_setattenuation(struct rme96 *rme96,
1da177e4
LT		 541 int attenuation)
542{
543 switch (attenuation) {
544 case 0:
545 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
546 ~RME96_WCR_GAIN_1;
547 break;
548 case 1:
549 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
550 ~RME96_WCR_GAIN_1;
551 break;
552 case 2:
553 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
554 RME96_WCR_GAIN_1;
555 break;
556 case 3:
557 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
558 RME96_WCR_GAIN_1;
559 break;
560 default:
561 return -EINVAL;
562 }
563 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
564 return 0;
565}
566
567static int
a3aefd88 568snd_rme96_capture_getrate(struct rme96 *rme96,
1da177e4
LT		 569 int *is_adat)
570{
571 int n, rate;
572
573 *is_adat = 0;
574 if (rme96->areg & RME96_AR_ANALOG) {
575 /* Analog input, overrides S/PDIF setting */
576 n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) +
577 (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1);
578 switch (n) {
579 case 1:
580 rate = 32000;
581 break;
582 case 2:
583 rate = 44100;
584 break;
585 case 3:
586 rate = 48000;
587 break;
588 default:
589 return -1;
590 }
591 return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate;
592 }
593
594 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
595 if (rme96->rcreg & RME96_RCR_LOCK) {
596 /* ADAT rate */
597 *is_adat = 1;
598 if (rme96->rcreg & RME96_RCR_T_OUT) {
599 return 48000;
600 }
601 return 44100;
602 }
603
604 if (rme96->rcreg & RME96_RCR_VERF) {
605 return -1;
606 }
607
608 /* S/PDIF rate */
609 n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) +
610 (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) +
611 (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2);
612
613 switch (n) {
614 case 0:
615 if (rme96->rcreg & RME96_RCR_T_OUT) {
616 return 64000;
617 }
618 return -1;
619 case 3: return 96000;
620 case 4: return 88200;
621 case 5: return 48000;
622 case 6: return 44100;
623 case 7: return 32000;
624 default:
625 break;
626 }
627 return -1;
628}
629
630static int
a3aefd88 631snd_rme96_playback_getrate(struct rme96 *rme96)
1da177e4
LT		 632{
633 int rate, dummy;
634
635 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
636 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
637 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
638 {
639 /* slave clock */
640 return rate;
641 }
642 rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
643 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
644 switch (rate) {
645 case 1:
646 rate = 32000;
647 break;
648 case 2:
649 rate = 44100;
650 break;
651 case 3:
652 rate = 48000;
653 break;
654 default:
655 return -1;
656 }
657 return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
658}
659
660static int
a3aefd88 661snd_rme96_playback_setrate(struct rme96 *rme96,
1da177e4
LT		 662 int rate)
663{
664 int ds;
665
666 ds = rme96->wcreg & RME96_WCR_DS;
667 switch (rate) {
668 case 32000:
669 rme96->wcreg &= ~RME96_WCR_DS;
670 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
671 ~RME96_WCR_FREQ_1;
672 break;
673 case 44100:
674 rme96->wcreg &= ~RME96_WCR_DS;
675 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
676 ~RME96_WCR_FREQ_0;
677 break;
678 case 48000:
679 rme96->wcreg &= ~RME96_WCR_DS;
680 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
681 RME96_WCR_FREQ_1;
682 break;
683 case 64000:
684 rme96->wcreg |= RME96_WCR_DS;
685 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
686 ~RME96_WCR_FREQ_1;
687 break;
688 case 88200:
689 rme96->wcreg |= RME96_WCR_DS;
690 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
691 ~RME96_WCR_FREQ_0;
692 break;
693 case 96000:
694 rme96->wcreg |= RME96_WCR_DS;
695 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
696 RME96_WCR_FREQ_1;
697 break;
698 default:
699 return -EINVAL;
700 }
701 if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
702 (ds && !(rme96->wcreg & RME96_WCR_DS)))
703 {
704 /* change to/from double-speed: reset the DAC (if available) */
705 snd_rme96_reset_dac(rme96);
706 } else {
707 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
708 }
709 return 0;
710}
711
712static int
a3aefd88 713snd_rme96_capture_analog_setrate(struct rme96 *rme96,
1da177e4
LT		 714 int rate)
715{
716 switch (rate) {
717 case 32000:
718 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
719 ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
720 break;
721 case 44100:
722 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
723 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
724 break;
725 case 48000:
726 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
727 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
728 break;
729 case 64000:
730 if (rme96->rev < 4) {
731 return -EINVAL;
732 }
733 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
734 ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
735 break;
736 case 88200:
737 if (rme96->rev < 4) {
738 return -EINVAL;
739 }
740 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
741 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
742 break;
743 case 96000:
744 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
745 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
746 break;
747 default:
748 return -EINVAL;
749 }
750 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
751 return 0;
752}
753
754static int
a3aefd88 755snd_rme96_setclockmode(struct rme96 *rme96,
1da177e4
LT		 756 int mode)
757{
758 switch (mode) {
759 case RME96_CLOCKMODE_SLAVE:
760 /* AutoSync */
761 rme96->wcreg &= ~RME96_WCR_MASTER;
762 rme96->areg &= ~RME96_AR_WSEL;
763 break;
764 case RME96_CLOCKMODE_MASTER:
765 /* Internal */
766 rme96->wcreg |= RME96_WCR_MASTER;
767 rme96->areg &= ~RME96_AR_WSEL;
768 break;
769 case RME96_CLOCKMODE_WORDCLOCK:
770 /* Word clock is a master mode */
771 rme96->wcreg |= RME96_WCR_MASTER;
772 rme96->areg |= RME96_AR_WSEL;
773 break;
774 default:
775 return -EINVAL;
776 }
777 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
778 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
779 return 0;
780}
781
782static int
a3aefd88 783snd_rme96_getclockmode(struct rme96 *rme96)
1da177e4
LT		 784{
785 if (rme96->areg & RME96_AR_WSEL) {
786 return RME96_CLOCKMODE_WORDCLOCK;
787 }
788 return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
789 RME96_CLOCKMODE_SLAVE;
790}
791
792static int
a3aefd88 793snd_rme96_setinputtype(struct rme96 *rme96,
1da177e4
LT		 794 int type)
795{
796 int n;
797
798 switch (type) {
799 case RME96_INPUT_OPTICAL:
800 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
801 ~RME96_WCR_INP_1;
802 break;
803 case RME96_INPUT_COAXIAL:
804 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
805 ~RME96_WCR_INP_1;
806 break;
807 case RME96_INPUT_INTERNAL:
808 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
809 RME96_WCR_INP_1;
810 break;
811 case RME96_INPUT_XLR:
8b7fc421
RD		 812 if ((rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
813 rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PRO) ||
814 (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
1da177e4
LT		 815 rme96->rev > 4))
816 {
817 /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */
818 return -EINVAL;
819 }
820 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
821 RME96_WCR_INP_1;
822 break;
823 case RME96_INPUT_ANALOG:
824 if (!RME96_HAS_ANALOG_IN(rme96)) {
825 return -EINVAL;
826 }
827 rme96->areg |= RME96_AR_ANALOG;
828 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
829 if (rme96->rev < 4) {
830 /*
831 * Revision less than 004 does not support 64 and
832 * 88.2 kHz
833 */
834 if (snd_rme96_capture_getrate(rme96, &n) == 88200) {
835 snd_rme96_capture_analog_setrate(rme96, 44100);
836 }
837 if (snd_rme96_capture_getrate(rme96, &n) == 64000) {
838 snd_rme96_capture_analog_setrate(rme96, 32000);
839 }
840 }
841 return 0;
842 default:
843 return -EINVAL;
844 }
845 if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) {
846 rme96->areg &= ~RME96_AR_ANALOG;
847 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
848 }
849 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
850 return 0;
851}
852
853static int
a3aefd88 854snd_rme96_getinputtype(struct rme96 *rme96)
1da177e4
LT		 855{
856 if (rme96->areg & RME96_AR_ANALOG) {
857 return RME96_INPUT_ANALOG;
858 }
859 return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
860 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
861}
862
863static void
a3aefd88 864snd_rme96_setframelog(struct rme96 *rme96,
1da177e4
LT		 865 int n_channels,
866 int is_playback)
867{
868 int frlog;
869
870 if (n_channels == 2) {
871 frlog = 1;
872 } else {
873 /* assume 8 channels */
874 frlog = 3;
875 }
876 if (is_playback) {
877 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
878 rme96->playback_frlog = frlog;
879 } else {
880 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
881 rme96->capture_frlog = frlog;
882 }
883}
884
885static int
a3aefd88 886snd_rme96_playback_setformat(struct rme96 *rme96,
1da177e4
LT		 887 int format)
888{
889 switch (format) {
890 case SNDRV_PCM_FORMAT_S16_LE:
891 rme96->wcreg &= ~RME96_WCR_MODE24;
892 break;
893 case SNDRV_PCM_FORMAT_S32_LE:
894 rme96->wcreg |= RME96_WCR_MODE24;
895 break;
896 default:
897 return -EINVAL;
898 }
899 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
900 return 0;
901}
902
903static int
a3aefd88 904snd_rme96_capture_setformat(struct rme96 *rme96,
1da177e4
LT		 905 int format)
906{
907 switch (format) {
908 case SNDRV_PCM_FORMAT_S16_LE:
909 rme96->wcreg &= ~RME96_WCR_MODE24_2;
910 break;
911 case SNDRV_PCM_FORMAT_S32_LE:
912 rme96->wcreg |= RME96_WCR_MODE24_2;
913 break;
914 default:
915 return -EINVAL;
916 }
917 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
918 return 0;
919}
920
921static void
a3aefd88 922snd_rme96_set_period_properties(struct rme96 *rme96,
1da177e4
LT		 923 size_t period_bytes)
924{
925 switch (period_bytes) {
926 case RME96_LARGE_BLOCK_SIZE:
927 rme96->wcreg &= ~RME96_WCR_ISEL;
928 break;
929 case RME96_SMALL_BLOCK_SIZE:
930 rme96->wcreg |= RME96_WCR_ISEL;
931 break;
932 default:
933 snd_BUG();
934 break;
935 }
936 rme96->wcreg &= ~RME96_WCR_IDIS;
937 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
938}
939
940static int
a3aefd88
TI		 941snd_rme96_playback_hw_params(struct snd_pcm_substream *substream,
942 struct snd_pcm_hw_params *params)
1da177e4 943{
a3aefd88
TI		 944 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
945 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 946 int err, rate, dummy;
947
4d23359b
CL		 948 runtime->dma_area = (void __force *)(rme96->iobase +
949 RME96_IO_PLAY_BUFFER);
1da177e4
LT		 950 runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER;
951 runtime->dma_bytes = RME96_BUFFER_SIZE;
952
953 spin_lock_irq(&rme96->lock);
954 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
955 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
956 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
957 {
958 /* slave clock */
959 if ((int)params_rate(params) != rate) {
960 spin_unlock_irq(&rme96->lock);
961 return -EIO;
962 }
963 } else if ((err = snd_rme96_playback_setrate(rme96, params_rate(params))) < 0) {
964 spin_unlock_irq(&rme96->lock);
965 return err;
966 }
967 if ((err = snd_rme96_playback_setformat(rme96, params_format(params))) < 0) {
968 spin_unlock_irq(&rme96->lock);
969 return err;
970 }
971 snd_rme96_setframelog(rme96, params_channels(params), 1);
972 if (rme96->capture_periodsize != 0) {
973 if (params_period_size(params) << rme96->playback_frlog !=
974 rme96->capture_periodsize)
975 {
976 spin_unlock_irq(&rme96->lock);
977 return -EBUSY;
978 }
979 }
980 rme96->playback_periodsize =
981 params_period_size(params) << rme96->playback_frlog;
982 snd_rme96_set_period_properties(rme96, rme96->playback_periodsize);
983 /* S/PDIF setup */
984 if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {
985 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
986 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
987 }
988 spin_unlock_irq(&rme96->lock);
989
990 return 0;
991}
992
993static int
a3aefd88
TI		 994snd_rme96_capture_hw_params(struct snd_pcm_substream *substream,
995 struct snd_pcm_hw_params *params)
1da177e4 996{
a3aefd88
TI		 997 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
998 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 999 int err, isadat, rate;
1000
4d23359b
CL		 1001 runtime->dma_area = (void __force *)(rme96->iobase +
1002 RME96_IO_REC_BUFFER);
1da177e4
LT		 1003 runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER;
1004 runtime->dma_bytes = RME96_BUFFER_SIZE;
1005
1006 spin_lock_irq(&rme96->lock);
1007 if ((err = snd_rme96_capture_setformat(rme96, params_format(params))) < 0) {
1008 spin_unlock_irq(&rme96->lock);
1009 return err;
1010 }
1011 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1012 if ((err = snd_rme96_capture_analog_setrate(rme96,
1013 params_rate(params))) < 0)
1014 {
1015 spin_unlock_irq(&rme96->lock);
1016 return err;
1017 }
1018 } else if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1019 if ((int)params_rate(params) != rate) {
1020 spin_unlock_irq(&rme96->lock);
1021 return -EIO;
1022 }
1023 if ((isadat && runtime->hw.channels_min == 2) ||
1024 (!isadat && runtime->hw.channels_min == 8))
1025 {
1026 spin_unlock_irq(&rme96->lock);
1027 return -EIO;
1028 }
1029 }
1030 snd_rme96_setframelog(rme96, params_channels(params), 0);
1031 if (rme96->playback_periodsize != 0) {
1032 if (params_period_size(params) << rme96->capture_frlog !=
1033 rme96->playback_periodsize)
1034 {
1035 spin_unlock_irq(&rme96->lock);
1036 return -EBUSY;
1037 }
1038 }
1039 rme96->capture_periodsize =
1040 params_period_size(params) << rme96->capture_frlog;
1041 snd_rme96_set_period_properties(rme96, rme96->capture_periodsize);
1042 spin_unlock_irq(&rme96->lock);
1043
1044 return 0;
1045}
1046
1047static void
a3aefd88 1048snd_rme96_playback_start(struct rme96 *rme96,
1da177e4
LT		 1049 int from_pause)
1050{
1051 if (!from_pause) {
1052 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1053 }
1054
1055 rme96->wcreg |= RME96_WCR_START;
1056 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1057}
1058
1059static void
a3aefd88 1060snd_rme96_capture_start(struct rme96 *rme96,
1da177e4
LT		 1061 int from_pause)
1062{
1063 if (!from_pause) {
1064 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1065 }
1066
1067 rme96->wcreg |= RME96_WCR_START_2;
1068 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1069}
1070
1071static void
a3aefd88 1072snd_rme96_playback_stop(struct rme96 *rme96)
1da177e4
LT		 1073{
1074 /*
1075 * Check if there is an unconfirmed IRQ, if so confirm it, or else
1076 * the hardware will not stop generating interrupts
1077 */
1078 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1079 if (rme96->rcreg & RME96_RCR_IRQ) {
1080 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1081 }
1082 rme96->wcreg &= ~RME96_WCR_START;
1083 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1084}
1085
1086static void
a3aefd88 1087snd_rme96_capture_stop(struct rme96 *rme96)
1da177e4
LT		 1088{
1089 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1090 if (rme96->rcreg & RME96_RCR_IRQ_2) {
1091 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1092 }
1093 rme96->wcreg &= ~RME96_WCR_START_2;
1094 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1095}
1096
1097static irqreturn_t
1098snd_rme96_interrupt(int irq,
7d12e780 1099 void *dev_id)
1da177e4 1100{
a3aefd88 1101 struct rme96 *rme96 = (struct rme96 *)dev_id;
1da177e4
LT		 1102
1103 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1104 /* fastpath out, to ease interrupt sharing */
1105 if (!((rme96->rcreg & RME96_RCR_IRQ) ||
1106 (rme96->rcreg & RME96_RCR_IRQ_2)))
1107 {
1108 return IRQ_NONE;
1109 }
1110
1111 if (rme96->rcreg & RME96_RCR_IRQ) {
1112 /* playback */
1113 snd_pcm_period_elapsed(rme96->playback_substream);
1114 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1115 }
1116 if (rme96->rcreg & RME96_RCR_IRQ_2) {
1117 /* capture */
1118 snd_pcm_period_elapsed(rme96->capture_substream);
1119 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1120 }
1121 return IRQ_HANDLED;
1122}
1123
1124static unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE };
1125
a3aefd88 1126static struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
1da177e4
LT		 1127 .count = ARRAY_SIZE(period_bytes),
1128 .list = period_bytes,
1129 .mask = 0
1130};
1131
2ce7fb57
TI		 1132static void
1133rme96_set_buffer_size_constraint(struct rme96 *rme96,
1134 struct snd_pcm_runtime *runtime)
1135{
1136 unsigned int size;
1137
1138 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1139 RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1140 if ((size = rme96->playback_periodsize) != 0 ||
1141 (size = rme96->capture_periodsize) != 0)
1142 snd_pcm_hw_constraint_minmax(runtime,
1143 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1144 size, size);
1145 else
1146 snd_pcm_hw_constraint_list(runtime, 0,
1147 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1148 &hw_constraints_period_bytes);
1149}
1150
1da177e4 1151static int
a3aefd88 1152snd_rme96_playback_spdif_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1153{
1154 int rate, dummy;
a3aefd88
TI		 1155 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1156 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1157
1da177e4
LT		 1158 spin_lock_irq(&rme96->lock);
1159 if (rme96->playback_substream != NULL) {
1160 spin_unlock_irq(&rme96->lock);
1161 return -EBUSY;
1162 }
1163 rme96->wcreg &= ~RME96_WCR_ADAT;
1164 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1165 rme96->playback_substream = substream;
1166 spin_unlock_irq(&rme96->lock);
1167
1168 runtime->hw = snd_rme96_playback_spdif_info;
1169 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1170 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1171 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1172 {
1173 /* slave clock */
918f3a0e 1174 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1da177e4
LT		 1175 runtime->hw.rate_min = rate;
1176 runtime->hw.rate_max = rate;
1177 }
2ce7fb57 1178 rme96_set_buffer_size_constraint(rme96, runtime);
1da177e4
LT		 1179
1180 rme96->wcreg_spdif_stream = rme96->wcreg_spdif;
1181 rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1182 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1183 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1184 return 0;
1185}
1186
1187static int
a3aefd88 1188snd_rme96_capture_spdif_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1189{
1190 int isadat, rate;
a3aefd88
TI		 1191 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1192 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1193
1da177e4
LT		 1194 runtime->hw = snd_rme96_capture_spdif_info;
1195 if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1196 (rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0)
1197 {
1198 if (isadat) {
1199 return -EIO;
1200 }
918f3a0e 1201 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1da177e4
LT		 1202 runtime->hw.rate_min = rate;
1203 runtime->hw.rate_max = rate;
1204 }
1205
1206 spin_lock_irq(&rme96->lock);
1207 if (rme96->capture_substream != NULL) {
1208 spin_unlock_irq(&rme96->lock);
1209 return -EBUSY;
1210 }
1211 rme96->capture_substream = substream;
1212 spin_unlock_irq(&rme96->lock);
1213
2ce7fb57 1214 rme96_set_buffer_size_constraint(rme96, runtime);
1da177e4
LT		 1215 return 0;
1216}
1217
1218static int
a3aefd88 1219snd_rme96_playback_adat_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1220{
1221 int rate, dummy;
a3aefd88
TI		 1222 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1223 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1224
1da177e4
LT		 1225 spin_lock_irq(&rme96->lock);
1226 if (rme96->playback_substream != NULL) {
1227 spin_unlock_irq(&rme96->lock);
1228 return -EBUSY;
1229 }
1230 rme96->wcreg |= RME96_WCR_ADAT;
1231 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1232 rme96->playback_substream = substream;
1233 spin_unlock_irq(&rme96->lock);
1234
1235 runtime->hw = snd_rme96_playback_adat_info;
1236 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1237 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1238 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1239 {
1240 /* slave clock */
918f3a0e 1241 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1da177e4
LT		 1242 runtime->hw.rate_min = rate;
1243 runtime->hw.rate_max = rate;
1244 }
2ce7fb57 1245 rme96_set_buffer_size_constraint(rme96, runtime);
1da177e4
LT		 1246 return 0;
1247}
1248
1249static int
a3aefd88 1250snd_rme96_capture_adat_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1251{
1252 int isadat, rate;
a3aefd88
TI		 1253 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1254 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1255
1da177e4
LT		 1256 runtime->hw = snd_rme96_capture_adat_info;
1257 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1258 /* makes no sense to use analog input. Note that analog
1259 expension cards AEB4/8-I are RME96_INPUT_INTERNAL */
1260 return -EIO;
1261 }
1262 if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1263 if (!isadat) {
1264 return -EIO;
1265 }
918f3a0e 1266 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1da177e4
LT		 1267 runtime->hw.rate_min = rate;
1268 runtime->hw.rate_max = rate;
1269 }
1270
1271 spin_lock_irq(&rme96->lock);
1272 if (rme96->capture_substream != NULL) {
1273 spin_unlock_irq(&rme96->lock);
1274 return -EBUSY;
1275 }
1276 rme96->capture_substream = substream;
1277 spin_unlock_irq(&rme96->lock);
1278
2ce7fb57 1279 rme96_set_buffer_size_constraint(rme96, runtime);
1da177e4
LT		 1280 return 0;
1281}
1282
1283static int
a3aefd88 1284snd_rme96_playback_close(struct snd_pcm_substream *substream)
1da177e4 1285{
a3aefd88 1286 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1287 int spdif = 0;
1288
1289 spin_lock_irq(&rme96->lock);
1290 if (RME96_ISPLAYING(rme96)) {
1291 snd_rme96_playback_stop(rme96);
1292 }
1293 rme96->playback_substream = NULL;
1294 rme96->playback_periodsize = 0;
1295 spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;
1296 spin_unlock_irq(&rme96->lock);
1297 if (spdif) {
1298 rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1299 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1300 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1301 }
1302 return 0;
1303}
1304
1305static int
a3aefd88 1306snd_rme96_capture_close(struct snd_pcm_substream *substream)
1da177e4 1307{
a3aefd88 1308 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1309
1310 spin_lock_irq(&rme96->lock);
1311 if (RME96_ISRECORDING(rme96)) {
1312 snd_rme96_capture_stop(rme96);
1313 }
1314 rme96->capture_substream = NULL;
1315 rme96->capture_periodsize = 0;
1316 spin_unlock_irq(&rme96->lock);
1317 return 0;
1318}
1319
1320static int
a3aefd88 1321snd_rme96_playback_prepare(struct snd_pcm_substream *substream)
1da177e4 1322{
a3aefd88 1323 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1324
1325 spin_lock_irq(&rme96->lock);
1326 if (RME96_ISPLAYING(rme96)) {
1327 snd_rme96_playback_stop(rme96);
1328 }
1329 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1330 spin_unlock_irq(&rme96->lock);
1331 return 0;
1332}
1333
1334static int
a3aefd88 1335snd_rme96_capture_prepare(struct snd_pcm_substream *substream)
1da177e4 1336{
a3aefd88 1337 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1338
1339 spin_lock_irq(&rme96->lock);
1340 if (RME96_ISRECORDING(rme96)) {
1341 snd_rme96_capture_stop(rme96);
1342 }
1343 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1344 spin_unlock_irq(&rme96->lock);
1345 return 0;
1346}
1347
1348static int
a3aefd88 1349snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 1350 int cmd)
1351{
a3aefd88 1352 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1353
1354 switch (cmd) {
1355 case SNDRV_PCM_TRIGGER_START:
1356 if (!RME96_ISPLAYING(rme96)) {
1357 if (substream != rme96->playback_substream) {
1358 return -EBUSY;
1359 }
1360 snd_rme96_playback_start(rme96, 0);
1361 }
1362 break;
1363
1364 case SNDRV_PCM_TRIGGER_STOP:
1365 if (RME96_ISPLAYING(rme96)) {
1366 if (substream != rme96->playback_substream) {
1367 return -EBUSY;
1368 }
1369 snd_rme96_playback_stop(rme96);
1370 }
1371 break;
1372
1373 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1374 if (RME96_ISPLAYING(rme96)) {
1375 snd_rme96_playback_stop(rme96);
1376 }
1377 break;
1378
1379 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1380 if (!RME96_ISPLAYING(rme96)) {
1381 snd_rme96_playback_start(rme96, 1);
1382 }
1383 break;
1384
1385 default:
1386 return -EINVAL;
1387 }
1388 return 0;
1389}
1390
1391static int
a3aefd88 1392snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 1393 int cmd)
1394{
a3aefd88 1395 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1396
1397 switch (cmd) {
1398 case SNDRV_PCM_TRIGGER_START:
1399 if (!RME96_ISRECORDING(rme96)) {
1400 if (substream != rme96->capture_substream) {
1401 return -EBUSY;
1402 }
1403 snd_rme96_capture_start(rme96, 0);
1404 }
1405 break;
1406
1407 case SNDRV_PCM_TRIGGER_STOP:
1408 if (RME96_ISRECORDING(rme96)) {
1409 if (substream != rme96->capture_substream) {
1410 return -EBUSY;
1411 }
1412 snd_rme96_capture_stop(rme96);
1413 }
1414 break;
1415
1416 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1417 if (RME96_ISRECORDING(rme96)) {
1418 snd_rme96_capture_stop(rme96);
1419 }
1420 break;
1421
1422 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1423 if (!RME96_ISRECORDING(rme96)) {
1424 snd_rme96_capture_start(rme96, 1);
1425 }
1426 break;
1427
1428 default:
1429 return -EINVAL;
1430 }
1431
1432 return 0;
1433}
1434
1435static snd_pcm_uframes_t
a3aefd88 1436snd_rme96_playback_pointer(struct snd_pcm_substream *substream)
1da177e4 1437{
a3aefd88 1438 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1439 return snd_rme96_playback_ptr(rme96);
1440}
1441
1442static snd_pcm_uframes_t
a3aefd88 1443snd_rme96_capture_pointer(struct snd_pcm_substream *substream)
1da177e4 1444{
a3aefd88 1445 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1446 return snd_rme96_capture_ptr(rme96);
1447}
1448
a3aefd88 1449static struct snd_pcm_ops snd_rme96_playback_spdif_ops = {
1da177e4
LT		 1450 .open = snd_rme96_playback_spdif_open,
1451 .close = snd_rme96_playback_close,
1452 .ioctl = snd_pcm_lib_ioctl,
1453 .hw_params = snd_rme96_playback_hw_params,
1454 .prepare = snd_rme96_playback_prepare,
1455 .trigger = snd_rme96_playback_trigger,
1456 .pointer = snd_rme96_playback_pointer,
1457 .copy = snd_rme96_playback_copy,
1458 .silence = snd_rme96_playback_silence,
1459 .mmap = snd_pcm_lib_mmap_iomem,
1460};
1461
a3aefd88 1462static struct snd_pcm_ops snd_rme96_capture_spdif_ops = {
1da177e4
LT		 1463 .open = snd_rme96_capture_spdif_open,
1464 .close = snd_rme96_capture_close,
1465 .ioctl = snd_pcm_lib_ioctl,
1466 .hw_params = snd_rme96_capture_hw_params,
1467 .prepare = snd_rme96_capture_prepare,
1468 .trigger = snd_rme96_capture_trigger,
1469 .pointer = snd_rme96_capture_pointer,
1470 .copy = snd_rme96_capture_copy,
1471 .mmap = snd_pcm_lib_mmap_iomem,
1472};
1473
a3aefd88 1474static struct snd_pcm_ops snd_rme96_playback_adat_ops = {
1da177e4
LT		 1475 .open = snd_rme96_playback_adat_open,
1476 .close = snd_rme96_playback_close,
1477 .ioctl = snd_pcm_lib_ioctl,
1478 .hw_params = snd_rme96_playback_hw_params,
1479 .prepare = snd_rme96_playback_prepare,
1480 .trigger = snd_rme96_playback_trigger,
1481 .pointer = snd_rme96_playback_pointer,
1482 .copy = snd_rme96_playback_copy,
1483 .silence = snd_rme96_playback_silence,
1484 .mmap = snd_pcm_lib_mmap_iomem,
1485};
1486
a3aefd88 1487static struct snd_pcm_ops snd_rme96_capture_adat_ops = {
1da177e4
LT		 1488 .open = snd_rme96_capture_adat_open,
1489 .close = snd_rme96_capture_close,
1490 .ioctl = snd_pcm_lib_ioctl,
1491 .hw_params = snd_rme96_capture_hw_params,
1492 .prepare = snd_rme96_capture_prepare,
1493 .trigger = snd_rme96_capture_trigger,
1494 .pointer = snd_rme96_capture_pointer,
1495 .copy = snd_rme96_capture_copy,
1496 .mmap = snd_pcm_lib_mmap_iomem,
1497};
1498
1499static void
1500snd_rme96_free(void *private_data)
1501{
a3aefd88 1502 struct rme96 *rme96 = (struct rme96 *)private_data;
1da177e4
LT		 1503
1504 if (rme96 == NULL) {
1505 return;
1506 }
1507 if (rme96->irq >= 0) {
1508 snd_rme96_playback_stop(rme96);
1509 snd_rme96_capture_stop(rme96);
1510 rme96->areg &= ~RME96_AR_DAC_EN;
1511 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1512 free_irq(rme96->irq, (void *)rme96);
1513 rme96->irq = -1;
1514 }
1515 if (rme96->iobase) {
1516 iounmap(rme96->iobase);
1517 rme96->iobase = NULL;
1518 }
1519 if (rme96->port) {
1520 pci_release_regions(rme96->pci);
1521 rme96->port = 0;
1522 }
1523 pci_disable_device(rme96->pci);
1524}
1525
1526static void
a3aefd88 1527snd_rme96_free_spdif_pcm(struct snd_pcm *pcm)
1da177e4 1528{
9fe856e4 1529 struct rme96 *rme96 = pcm->private_data;
1da177e4
LT		 1530 rme96->spdif_pcm = NULL;
1531}
1532
1533static void
a3aefd88 1534snd_rme96_free_adat_pcm(struct snd_pcm *pcm)
1da177e4 1535{
9fe856e4 1536 struct rme96 *rme96 = pcm->private_data;
1da177e4
LT		 1537 rme96->adat_pcm = NULL;
1538}
1539
e23e7a14 1540static int
a3aefd88 1541snd_rme96_create(struct rme96 *rme96)
1da177e4
LT		 1542{
1543 struct pci_dev *pci = rme96->pci;
1544 int err;
1545
1546 rme96->irq = -1;
1547 spin_lock_init(&rme96->lock);
1548
1549 if ((err = pci_enable_device(pci)) < 0)
1550 return err;
1551
1552 if ((err = pci_request_regions(pci, "RME96")) < 0)
1553 return err;
1554 rme96->port = pci_resource_start(rme96->pci, 0);
1555
44977b71
HH		 1556 rme96->iobase = ioremap_nocache(rme96->port, RME96_IO_SIZE);
1557 if (!rme96->iobase) {
688956f2
TI		 1558 snd_printk(KERN_ERR "unable to remap memory region 0x%lx-0x%lx\n", rme96->port, rme96->port + RME96_IO_SIZE - 1);
1559 return -ENOMEM;
1560 }
1561
437a5a46 1562 if (request_irq(pci->irq, snd_rme96_interrupt, IRQF_SHARED,
934c2b6d 1563 KBUILD_MODNAME, rme96)) {
99b359ba 1564 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1da177e4
LT		 1565 return -EBUSY;
1566 }
1567 rme96->irq = pci->irq;
1568
1da177e4
LT		 1569 /* read the card's revision number */
1570 pci_read_config_byte(pci, 8, &rme96->rev);
1571
1572 /* set up ALSA pcm device for S/PDIF */
1573 if ((err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0,
1574 1, 1, &rme96->spdif_pcm)) < 0)
1575 {
1576 return err;
1577 }
1578 rme96->spdif_pcm->private_data = rme96;
1579 rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm;
1580 strcpy(rme96->spdif_pcm->name, "Digi96 IEC958");
1581 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops);
1582 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops);
1583
1584 rme96->spdif_pcm->info_flags = 0;
1585
1586 /* set up ALSA pcm device for ADAT */
8b7fc421 1587 if (pci->device == PCI_DEVICE_ID_RME_DIGI96) {
1da177e4
LT		 1588 /* ADAT is not available on the base model */
1589 rme96->adat_pcm = NULL;
1590 } else {
1591 if ((err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1,
1592 1, 1, &rme96->adat_pcm)) < 0)
1593 {
1594 return err;
1595 }
1596 rme96->adat_pcm->private_data = rme96;
1597 rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm;
1598 strcpy(rme96->adat_pcm->name, "Digi96 ADAT");
1599 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops);
1600 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops);
1601
1602 rme96->adat_pcm->info_flags = 0;
1603 }
1604
1605 rme96->playback_periodsize = 0;
1606 rme96->capture_periodsize = 0;
1607
1608 /* make sure playback/capture is stopped, if by some reason active */
1609 snd_rme96_playback_stop(rme96);
1610 snd_rme96_capture_stop(rme96);
1611
1612 /* set default values in registers */
1613 rme96->wcreg =
1614 RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */
1615 RME96_WCR_SEL | /* normal playback */
1616 RME96_WCR_MASTER | /* set to master clock mode */
1617 RME96_WCR_INP_0; /* set coaxial input */
1618
1619 rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */
1620
1621 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1622 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1623
1624 /* reset the ADC */
1625 writel(rme96->areg | RME96_AR_PD2,
1626 rme96->iobase + RME96_IO_ADDITIONAL_REG);
1627 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1628
1629 /* reset and enable the DAC (order is important). */
1630 snd_rme96_reset_dac(rme96);
1631 rme96->areg |= RME96_AR_DAC_EN;
1632 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1633
1634 /* reset playback and record buffer pointers */
1635 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1636 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1637
1638 /* reset volume */
1639 rme96->vol[0] = rme96->vol[1] = 0;
1640 if (RME96_HAS_ANALOG_OUT(rme96)) {
1641 snd_rme96_apply_dac_volume(rme96);
1642 }
1643
1644 /* init switch interface */
1645 if ((err = snd_rme96_create_switches(rme96->card, rme96)) < 0) {
1646 return err;
1647 }
1648
1649 /* init proc interface */
1650 snd_rme96_proc_init(rme96);
1651
1652 return 0;
1653}
1654
1655/*
1656 * proc interface
1657 */
1658
1659static void
a3aefd88 1660snd_rme96_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
1da177e4
LT		 1661{
1662 int n;
9fe856e4 1663 struct rme96 *rme96 = entry->private_data;
1da177e4
LT		 1664
1665 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1666
1667 snd_iprintf(buffer, rme96->card->longname);
1668 snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1);
1669
1670 snd_iprintf(buffer, "\nGeneral settings\n");
1671 if (rme96->wcreg & RME96_WCR_IDIS) {
1672 snd_iprintf(buffer, " period size: N/A (interrupts "
1673 "disabled)\n");
1674 } else if (rme96->wcreg & RME96_WCR_ISEL) {
1675 snd_iprintf(buffer, " period size: 2048 bytes\n");
1676 } else {
1677 snd_iprintf(buffer, " period size: 8192 bytes\n");
1678 }
1679 snd_iprintf(buffer, "\nInput settings\n");
1680 switch (snd_rme96_getinputtype(rme96)) {
1681 case RME96_INPUT_OPTICAL:
1682 snd_iprintf(buffer, " input: optical");
1683 break;
1684 case RME96_INPUT_COAXIAL:
1685 snd_iprintf(buffer, " input: coaxial");
1686 break;
1687 case RME96_INPUT_INTERNAL:
1688 snd_iprintf(buffer, " input: internal");
1689 break;
1690 case RME96_INPUT_XLR:
1691 snd_iprintf(buffer, " input: XLR");
1692 break;
1693 case RME96_INPUT_ANALOG:
1694 snd_iprintf(buffer, " input: analog");
1695 break;
1696 }
1697 if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1698 snd_iprintf(buffer, "\n sample rate: no valid signal\n");
1699 } else {
1700 if (n) {
1701 snd_iprintf(buffer, " (8 channels)\n");
1702 } else {
1703 snd_iprintf(buffer, " (2 channels)\n");
1704 }
1705 snd_iprintf(buffer, " sample rate: %d Hz\n",
1706 snd_rme96_capture_getrate(rme96, &n));
1707 }
1708 if (rme96->wcreg & RME96_WCR_MODE24_2) {
1709 snd_iprintf(buffer, " sample format: 24 bit\n");
1710 } else {
1711 snd_iprintf(buffer, " sample format: 16 bit\n");
1712 }
1713
1714 snd_iprintf(buffer, "\nOutput settings\n");
1715 if (rme96->wcreg & RME96_WCR_SEL) {
1716 snd_iprintf(buffer, " output signal: normal playback\n");
1717 } else {
1718 snd_iprintf(buffer, " output signal: same as input\n");
1719 }
1720 snd_iprintf(buffer, " sample rate: %d Hz\n",
1721 snd_rme96_playback_getrate(rme96));
1722 if (rme96->wcreg & RME96_WCR_MODE24) {
1723 snd_iprintf(buffer, " sample format: 24 bit\n");
1724 } else {
1725 snd_iprintf(buffer, " sample format: 16 bit\n");
1726 }
1727 if (rme96->areg & RME96_AR_WSEL) {
1728 snd_iprintf(buffer, " sample clock source: word clock\n");
1729 } else if (rme96->wcreg & RME96_WCR_MASTER) {
1730 snd_iprintf(buffer, " sample clock source: internal\n");
1731 } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1732 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to analog input setting)\n");
1733 } else if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1734 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to no valid signal)\n");
1735 } else {
1736 snd_iprintf(buffer, " sample clock source: autosync\n");
1737 }
1738 if (rme96->wcreg & RME96_WCR_PRO) {
1739 snd_iprintf(buffer, " format: AES/EBU (professional)\n");
1740 } else {
1741 snd_iprintf(buffer, " format: IEC958 (consumer)\n");
1742 }
1743 if (rme96->wcreg & RME96_WCR_EMP) {
1744 snd_iprintf(buffer, " emphasis: on\n");
1745 } else {
1746 snd_iprintf(buffer, " emphasis: off\n");
1747 }
1748 if (rme96->wcreg & RME96_WCR_DOLBY) {
1749 snd_iprintf(buffer, " non-audio (dolby): on\n");
1750 } else {
1751 snd_iprintf(buffer, " non-audio (dolby): off\n");
1752 }
1753 if (RME96_HAS_ANALOG_IN(rme96)) {
1754 snd_iprintf(buffer, "\nAnalog output settings\n");
1755 switch (snd_rme96_getmontracks(rme96)) {
1756 case RME96_MONITOR_TRACKS_1_2:
1757 snd_iprintf(buffer, " monitored ADAT tracks: 1+2\n");
1758 break;
1759 case RME96_MONITOR_TRACKS_3_4:
1760 snd_iprintf(buffer, " monitored ADAT tracks: 3+4\n");
1761 break;
1762 case RME96_MONITOR_TRACKS_5_6:
1763 snd_iprintf(buffer, " monitored ADAT tracks: 5+6\n");
1764 break;
1765 case RME96_MONITOR_TRACKS_7_8:
1766 snd_iprintf(buffer, " monitored ADAT tracks: 7+8\n");
1767 break;
1768 }
1769 switch (snd_rme96_getattenuation(rme96)) {
1770 case RME96_ATTENUATION_0:
1771 snd_iprintf(buffer, " attenuation: 0 dB\n");
1772 break;
1773 case RME96_ATTENUATION_6:
1774 snd_iprintf(buffer, " attenuation: -6 dB\n");
1775 break;
1776 case RME96_ATTENUATION_12:
1777 snd_iprintf(buffer, " attenuation: -12 dB\n");
1778 break;
1779 case RME96_ATTENUATION_18:
1780 snd_iprintf(buffer, " attenuation: -18 dB\n");
1781 break;
1782 }
1783 snd_iprintf(buffer, " volume left: %u\n", rme96->vol[0]);
1784 snd_iprintf(buffer, " volume right: %u\n", rme96->vol[1]);
1785 }
1786}
1787
e23e7a14 1788static void snd_rme96_proc_init(struct rme96 *rme96)
1da177e4 1789{
a3aefd88 1790 struct snd_info_entry *entry;
1da177e4
LT		 1791
1792 if (! snd_card_proc_new(rme96->card, "rme96", &entry))
bf850204 1793 snd_info_set_text_ops(entry, rme96, snd_rme96_proc_read);
1da177e4
LT		 1794}
1795
1796/*
1797 * control interface
1798 */
1799
a5ce8890
TI		 1800#define snd_rme96_info_loopback_control snd_ctl_boolean_mono_info
1801
1da177e4 1802static int
a3aefd88 1803snd_rme96_get_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1804{
a3aefd88 1805 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1806
1807 spin_lock_irq(&rme96->lock);
1808 ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;
1809 spin_unlock_irq(&rme96->lock);
1810 return 0;
1811}
1812static int
a3aefd88 1813snd_rme96_put_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1814{
a3aefd88 1815 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1816 unsigned int val;
1817 int change;
1818
1819 val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL;
1820 spin_lock_irq(&rme96->lock);
1821 val = (rme96->wcreg & ~RME96_WCR_SEL) | val;
1822 change = val != rme96->wcreg;
1823 rme96->wcreg = val;
1824 writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1825 spin_unlock_irq(&rme96->lock);
1826 return change;
1827}
1828
1829static int
a3aefd88 1830snd_rme96_info_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1831{
1832 static char *_texts[5] = { "Optical", "Coaxial", "Internal", "XLR", "Analog" };
a3aefd88 1833 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1834 char *texts[5] = { _texts[0], _texts[1], _texts[2], _texts[3], _texts[4] };
1835
1836 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1837 uinfo->count = 1;
1838 switch (rme96->pci->device) {
8b7fc421
RD		 1839 case PCI_DEVICE_ID_RME_DIGI96:
1840 case PCI_DEVICE_ID_RME_DIGI96_8:
1da177e4
LT		 1841 uinfo->value.enumerated.items = 3;
1842 break;
8b7fc421 1843 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1da177e4
LT		 1844 uinfo->value.enumerated.items = 4;
1845 break;
8b7fc421 1846 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1da177e4
LT		 1847 if (rme96->rev > 4) {
1848 /* PST */
1849 uinfo->value.enumerated.items = 4;
1850 texts[3] = _texts[4]; /* Analog instead of XLR */
1851 } else {
1852 /* PAD */
1853 uinfo->value.enumerated.items = 5;
1854 }
1855 break;
1856 default:
1857 snd_BUG();
1858 break;
1859 }
1860 if (uinfo->value.enumerated.item > uinfo->value.enumerated.items - 1) {
1861 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1862 }
1863 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1864 return 0;
1865}
1866static int
a3aefd88 1867snd_rme96_get_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1868{
a3aefd88 1869 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1870 unsigned int items = 3;
1871
1872 spin_lock_irq(&rme96->lock);
1873 ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96);
1874
1875 switch (rme96->pci->device) {
8b7fc421
RD		 1876 case PCI_DEVICE_ID_RME_DIGI96:
1877 case PCI_DEVICE_ID_RME_DIGI96_8:
1da177e4
LT		 1878 items = 3;
1879 break;
8b7fc421 1880 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1da177e4
LT		 1881 items = 4;
1882 break;
8b7fc421 1883 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1da177e4
LT		 1884 if (rme96->rev > 4) {
1885 /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */
1886 if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) {
1887 ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR;
1888 }
1889 items = 4;
1890 } else {
1891 items = 5;
1892 }
1893 break;
1894 default:
1895 snd_BUG();
1896 break;
1897 }
1898 if (ucontrol->value.enumerated.item[0] >= items) {
1899 ucontrol->value.enumerated.item[0] = items - 1;
1900 }
1901
1902 spin_unlock_irq(&rme96->lock);
1903 return 0;
1904}
1905static int
a3aefd88 1906snd_rme96_put_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1907{
a3aefd88 1908 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1909 unsigned int val;
1910 int change, items = 3;
1911
1912 switch (rme96->pci->device) {
8b7fc421
RD		 1913 case PCI_DEVICE_ID_RME_DIGI96:
1914 case PCI_DEVICE_ID_RME_DIGI96_8:
1da177e4
LT		 1915 items = 3;
1916 break;
8b7fc421 1917 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1da177e4
LT		 1918 items = 4;
1919 break;
8b7fc421 1920 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1da177e4
LT		 1921 if (rme96->rev > 4) {
1922 items = 4;
1923 } else {
1924 items = 5;
1925 }
1926 break;
1927 default:
1928 snd_BUG();
1929 break;
1930 }
1931 val = ucontrol->value.enumerated.item[0] % items;
1932
1933 /* special case for PST */
8b7fc421 1934 if (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4) {
1da177e4
LT		 1935 if (val == RME96_INPUT_XLR) {
1936 val = RME96_INPUT_ANALOG;
1937 }
1938 }
1939
1940 spin_lock_irq(&rme96->lock);
1941 change = (int)val != snd_rme96_getinputtype(rme96);
1942 snd_rme96_setinputtype(rme96, val);
1943 spin_unlock_irq(&rme96->lock);
1944 return change;
1945}
1946
1947static int
a3aefd88 1948snd_rme96_info_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1949{
1950 static char *texts[3] = { "AutoSync", "Internal", "Word" };
1951
1952 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1953 uinfo->count = 1;
1954 uinfo->value.enumerated.items = 3;
1955 if (uinfo->value.enumerated.item > 2) {
1956 uinfo->value.enumerated.item = 2;
1957 }
1958 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1959 return 0;
1960}
1961static int
a3aefd88 1962snd_rme96_get_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1963{
a3aefd88 1964 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1965
1966 spin_lock_irq(&rme96->lock);
1967 ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96);
1968 spin_unlock_irq(&rme96->lock);
1969 return 0;
1970}
1971static int
a3aefd88 1972snd_rme96_put_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1973{
a3aefd88 1974 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1975 unsigned int val;
1976 int change;
1977
1978 val = ucontrol->value.enumerated.item[0] % 3;
1979 spin_lock_irq(&rme96->lock);
1980 change = (int)val != snd_rme96_getclockmode(rme96);
1981 snd_rme96_setclockmode(rme96, val);
1982 spin_unlock_irq(&rme96->lock);
1983 return change;
1984}
1985
1986static int
a3aefd88 1987snd_rme96_info_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1988{
1989 static char *texts[4] = { "0 dB", "-6 dB", "-12 dB", "-18 dB" };
1990
1991 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1992 uinfo->count = 1;
1993 uinfo->value.enumerated.items = 4;
1994 if (uinfo->value.enumerated.item > 3) {
1995 uinfo->value.enumerated.item = 3;
1996 }
1997 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1998 return 0;
1999}
2000static int
a3aefd88 2001snd_rme96_get_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2002{
a3aefd88 2003 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2004
2005 spin_lock_irq(&rme96->lock);
2006 ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96);
2007 spin_unlock_irq(&rme96->lock);
2008 return 0;
2009}
2010static int
a3aefd88 2011snd_rme96_put_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2012{
a3aefd88 2013 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2014 unsigned int val;
2015 int change;
2016
2017 val = ucontrol->value.enumerated.item[0] % 4;
2018 spin_lock_irq(&rme96->lock);
2019
2020 change = (int)val != snd_rme96_getattenuation(rme96);
2021 snd_rme96_setattenuation(rme96, val);
2022 spin_unlock_irq(&rme96->lock);
2023 return change;
2024}
2025
2026static int
a3aefd88 2027snd_rme96_info_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 2028{
2029 static char *texts[4] = { "1+2", "3+4", "5+6", "7+8" };
2030
2031 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2032 uinfo->count = 1;
2033 uinfo->value.enumerated.items = 4;
2034 if (uinfo->value.enumerated.item > 3) {
2035 uinfo->value.enumerated.item = 3;
2036 }
2037 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2038 return 0;
2039}
2040static int
a3aefd88 2041snd_rme96_get_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2042{
a3aefd88 2043 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2044
2045 spin_lock_irq(&rme96->lock);
2046 ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96);
2047 spin_unlock_irq(&rme96->lock);
2048 return 0;
2049}
2050static int
a3aefd88 2051snd_rme96_put_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2052{
a3aefd88 2053 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2054 unsigned int val;
2055 int change;
2056
2057 val = ucontrol->value.enumerated.item[0] % 4;
2058 spin_lock_irq(&rme96->lock);
2059 change = (int)val != snd_rme96_getmontracks(rme96);
2060 snd_rme96_setmontracks(rme96, val);
2061 spin_unlock_irq(&rme96->lock);
2062 return change;
2063}
2064
a3aefd88 2065static u32 snd_rme96_convert_from_aes(struct snd_aes_iec958 *aes)
1da177e4
LT		 2066{
2067 u32 val = 0;
2068 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0;
2069 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0;
2070 if (val & RME96_WCR_PRO)
2071 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2072 else
2073 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2074 return val;
2075}
2076
a3aefd88 2077static void snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1da177e4
LT		 2078{
2079 aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
2080 ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0);
2081 if (val & RME96_WCR_PRO)
2082 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
2083 else
2084 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
2085}
2086
a3aefd88 2087static int snd_rme96_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 2088{
2089 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2090 uinfo->count = 1;
2091 return 0;
2092}
2093
a3aefd88 2094static int snd_rme96_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2095{
a3aefd88 2096 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2097
2098 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif);
2099 return 0;
2100}
2101
a3aefd88 2102static int snd_rme96_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2103{
a3aefd88 2104 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2105 int change;
2106 u32 val;
2107
2108 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2109 spin_lock_irq(&rme96->lock);
2110 change = val != rme96->wcreg_spdif;
2111 rme96->wcreg_spdif = val;
2112 spin_unlock_irq(&rme96->lock);
2113 return change;
2114}
2115
a3aefd88 2116static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 2117{
2118 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2119 uinfo->count = 1;
2120 return 0;
2121}
2122
a3aefd88 2123static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2124{
a3aefd88 2125 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2126
2127 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream);
2128 return 0;
2129}
2130
a3aefd88 2131static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2132{
a3aefd88 2133 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2134 int change;
2135 u32 val;
2136
2137 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2138 spin_lock_irq(&rme96->lock);
2139 change = val != rme96->wcreg_spdif_stream;
2140 rme96->wcreg_spdif_stream = val;
2141 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
2142 rme96->wcreg |= val;
2143 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
2144 spin_unlock_irq(&rme96->lock);
2145 return change;
2146}
2147
a3aefd88 2148static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 2149{
2150 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2151 uinfo->count = 1;
2152 return 0;
2153}
2154
a3aefd88 2155static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4
LT		 2156{
2157 ucontrol->value.iec958.status[0] = kcontrol->private_value;
2158 return 0;
2159}
2160
2161static int
a3aefd88 2162snd_rme96_dac_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4 2163{
a3aefd88 2164 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2165
2166 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2167 uinfo->count = 2;
2168 uinfo->value.integer.min = 0;
2169 uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96);
2170 return 0;
2171}
2172
2173static int
a3aefd88 2174snd_rme96_dac_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
1da177e4 2175{
a3aefd88 2176 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2177
2178 spin_lock_irq(&rme96->lock);
2179 u->value.integer.value[0] = rme96->vol[0];
2180 u->value.integer.value[1] = rme96->vol[1];
2181 spin_unlock_irq(&rme96->lock);
2182
2183 return 0;
2184}
2185
2186static int
a3aefd88 2187snd_rme96_dac_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
1da177e4 2188{
a3aefd88 2189 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4 2190 int change = 0;
4e98d6a7 2191 unsigned int vol, maxvol;
1da177e4 2192
4e98d6a7
TI		 2193
2194 if (!RME96_HAS_ANALOG_OUT(rme96))
1da177e4 2195 return -EINVAL;
4e98d6a7 2196 maxvol = RME96_185X_MAX_OUT(rme96);
1da177e4 2197 spin_lock_irq(&rme96->lock);
4e98d6a7
TI		 2198 vol = u->value.integer.value[0];
2199 if (vol != rme96->vol[0] && vol <= maxvol) {
2200 rme96->vol[0] = vol;
2201 change = 1;
2202 }
2203 vol = u->value.integer.value[1];
2204 if (vol != rme96->vol[1] && vol <= maxvol) {
2205 rme96->vol[1] = vol;
2206 change = 1;
1da177e4 2207 }
4e98d6a7
TI		 2208 if (change)
2209 snd_rme96_apply_dac_volume(rme96);
1da177e4
LT		 2210 spin_unlock_irq(&rme96->lock);
2211
2212 return change;
2213}
2214
a3aefd88 2215static struct snd_kcontrol_new snd_rme96_controls[] = {
1da177e4
LT		 2216{
2217 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2218 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2219 .info = snd_rme96_control_spdif_info,
2220 .get = snd_rme96_control_spdif_get,
2221 .put = snd_rme96_control_spdif_put
2222},
2223{
2224 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2225 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2226 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2227 .info = snd_rme96_control_spdif_stream_info,
2228 .get = snd_rme96_control_spdif_stream_get,
2229 .put = snd_rme96_control_spdif_stream_put
2230},
2231{
2232 .access = SNDRV_CTL_ELEM_ACCESS_READ,
67ed4161 2233 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT		 2234 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2235 .info = snd_rme96_control_spdif_mask_info,
2236 .get = snd_rme96_control_spdif_mask_get,
2237 .private_value = IEC958_AES0_NONAUDIO |
2238 IEC958_AES0_PROFESSIONAL |
2239 IEC958_AES0_CON_EMPHASIS
2240},
2241{
2242 .access = SNDRV_CTL_ELEM_ACCESS_READ,
67ed4161 2243 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT		 2244 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2245 .info = snd_rme96_control_spdif_mask_info,
2246 .get = snd_rme96_control_spdif_mask_get,
2247 .private_value = IEC958_AES0_NONAUDIO |
2248 IEC958_AES0_PROFESSIONAL |
2249 IEC958_AES0_PRO_EMPHASIS
2250},
2251{
2252 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2253 .name = "Input Connector",
2254 .info = snd_rme96_info_inputtype_control,
2255 .get = snd_rme96_get_inputtype_control,
2256 .put = snd_rme96_put_inputtype_control
2257},
2258{
2259 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2260 .name = "Loopback Input",
2261 .info = snd_rme96_info_loopback_control,
2262 .get = snd_rme96_get_loopback_control,
2263 .put = snd_rme96_put_loopback_control
2264},
2265{
2266 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2267 .name = "Sample Clock Source",
2268 .info = snd_rme96_info_clockmode_control,
2269 .get = snd_rme96_get_clockmode_control,
2270 .put = snd_rme96_put_clockmode_control
2271},
2272{
2273 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2274 .name = "Monitor Tracks",
2275 .info = snd_rme96_info_montracks_control,
2276 .get = snd_rme96_get_montracks_control,
2277 .put = snd_rme96_put_montracks_control
2278},
2279{
2280 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2281 .name = "Attenuation",
2282 .info = snd_rme96_info_attenuation_control,
2283 .get = snd_rme96_get_attenuation_control,
2284 .put = snd_rme96_put_attenuation_control
2285},
2286{
2287 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2288 .name = "DAC Playback Volume",
2289 .info = snd_rme96_dac_volume_info,
2290 .get = snd_rme96_dac_volume_get,
2291 .put = snd_rme96_dac_volume_put
2292}
2293};
2294
2295static int
a3aefd88
TI		 2296snd_rme96_create_switches(struct snd_card *card,
2297 struct rme96 *rme96)
1da177e4
LT		 2298{
2299 int idx, err;
a3aefd88 2300 struct snd_kcontrol *kctl;
1da177e4
LT		 2301
2302 for (idx = 0; idx < 7; idx++) {
2303 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2304 return err;
2305 if (idx == 1) /* IEC958 (S/PDIF) Stream */
2306 rme96->spdif_ctl = kctl;
2307 }
2308
2309 if (RME96_HAS_ANALOG_OUT(rme96)) {
2310 for (idx = 7; idx < 10; idx++)
2311 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2312 return err;
2313 }
2314
2315 return 0;
2316}
2317
2318/*
2319 * Card initialisation
2320 */
2321
a3aefd88 2322static void snd_rme96_card_free(struct snd_card *card)
1da177e4
LT		 2323{
2324 snd_rme96_free(card->private_data);
2325}
2326
e23e7a14 2327static int
1da177e4
LT		 2328snd_rme96_probe(struct pci_dev *pci,
2329 const struct pci_device_id *pci_id)
2330{
2331 static int dev;
a3aefd88
TI		 2332 struct rme96 *rme96;
2333 struct snd_card *card;
1da177e4
LT		 2334 int err;
2335 u8 val;
2336
2337 if (dev >= SNDRV_CARDS) {
2338 return -ENODEV;
2339 }
2340 if (!enable[dev]) {
2341 dev++;
2342 return -ENOENT;
2343 }
e58de7ba
TI		 2344 err = snd_card_create(index[dev], id[dev], THIS_MODULE,
2345 sizeof(struct rme96), &card);
2346 if (err < 0)
2347 return err;
1da177e4 2348 card->private_free = snd_rme96_card_free;
9fe856e4 2349 rme96 = card->private_data;
1da177e4
LT		 2350 rme96->card = card;
2351 rme96->pci = pci;
2352 snd_card_set_dev(card, &pci->dev);
2353 if ((err = snd_rme96_create(rme96)) < 0) {
2354 snd_card_free(card);
2355 return err;
2356 }
2357
2358 strcpy(card->driver, "Digi96");
2359 switch (rme96->pci->device) {
8b7fc421 2360 case PCI_DEVICE_ID_RME_DIGI96:
1da177e4
LT		 2361 strcpy(card->shortname, "RME Digi96");
2362 break;
8b7fc421 2363 case PCI_DEVICE_ID_RME_DIGI96_8:
1da177e4
LT		 2364 strcpy(card->shortname, "RME Digi96/8");
2365 break;
8b7fc421 2366 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1da177e4
LT		 2367 strcpy(card->shortname, "RME Digi96/8 PRO");
2368 break;
8b7fc421 2369 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1da177e4
LT		 2370 pci_read_config_byte(rme96->pci, 8, &val);
2371 if (val < 5) {
2372 strcpy(card->shortname, "RME Digi96/8 PAD");
2373 } else {
2374 strcpy(card->shortname, "RME Digi96/8 PST");
2375 }
2376 break;
2377 }
2378 sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname,
2379 rme96->port, rme96->irq);
2380
2381 if ((err = snd_card_register(card)) < 0) {
2382 snd_card_free(card);
2383 return err;
2384 }
2385 pci_set_drvdata(pci, card);
2386 dev++;
2387 return 0;
2388}
2389
e23e7a14 2390static void snd_rme96_remove(struct pci_dev *pci)
1da177e4
LT		 2391{
2392 snd_card_free(pci_get_drvdata(pci));
1da177e4
LT		 2393}
2394
e9f66d9b 2395static struct pci_driver rme96_driver = {
3733e424 2396 .name = KBUILD_MODNAME,
1da177e4
LT		 2397 .id_table = snd_rme96_ids,
2398 .probe = snd_rme96_probe,
e23e7a14 2399 .remove = snd_rme96_remove,
1da177e4
LT		 2400};
2401
e9f66d9b 2402module_pci_driver(rme96_driver);
Linux kernel - Deliverables
This page took 1.08116 seconds and 5 git commands to generate.