Commit | Line | Data |
---|---|---|
ef5fa1a4 | 1 | /* |
763f356c TI |
2 | * ALSA driver for RME Hammerfall DSP MADI audio interface(s) |
3 | * | |
4 | * Copyright (c) 2003 Winfried Ritsch (IEM) | |
5 | * code based on hdsp.c Paul Davis | |
6 | * Marcus Andersson | |
7 | * Thomas Charbonnel | |
3cee5a60 RB |
8 | * Modified 2006-06-01 for AES32 support by Remy Bruno |
9 | * <remy.bruno@trinnov.com> | |
763f356c | 10 | * |
0dca1793 AK |
11 | * Modified 2009-04-13 for proper metering by Florian Faber |
12 | * <faber@faberman.de> | |
13 | * | |
14 | * Modified 2009-04-14 for native float support by Florian Faber | |
15 | * <faber@faberman.de> | |
16 | * | |
17 | * Modified 2009-04-26 fixed bug in rms metering by Florian Faber | |
18 | * <faber@faberman.de> | |
19 | * | |
20 | * Modified 2009-04-30 added hw serial number support by Florian Faber | |
21 | * | |
22 | * Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth | |
23 | * | |
24 | * Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth | |
25 | * | |
763f356c TI |
26 | * This program is free software; you can redistribute it and/or modify |
27 | * it under the terms of the GNU General Public License as published by | |
28 | * the Free Software Foundation; either version 2 of the License, or | |
29 | * (at your option) any later version. | |
30 | * | |
31 | * This program is distributed in the hope that it will be useful, | |
32 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
33 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
34 | * GNU General Public License for more details. | |
35 | * | |
36 | * You should have received a copy of the GNU General Public License | |
37 | * along with this program; if not, write to the Free Software | |
38 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
39 | * | |
40 | */ | |
763f356c TI |
41 | #include <linux/init.h> |
42 | #include <linux/delay.h> | |
43 | #include <linux/interrupt.h> | |
65a77217 | 44 | #include <linux/module.h> |
763f356c TI |
45 | #include <linux/slab.h> |
46 | #include <linux/pci.h> | |
3f7440a6 | 47 | #include <linux/math64.h> |
763f356c TI |
48 | #include <asm/io.h> |
49 | ||
50 | #include <sound/core.h> | |
51 | #include <sound/control.h> | |
52 | #include <sound/pcm.h> | |
0dca1793 | 53 | #include <sound/pcm_params.h> |
763f356c TI |
54 | #include <sound/info.h> |
55 | #include <sound/asoundef.h> | |
56 | #include <sound/rawmidi.h> | |
57 | #include <sound/hwdep.h> | |
58 | #include <sound/initval.h> | |
59 | ||
60 | #include <sound/hdspm.h> | |
61 | ||
62 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ | |
63 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ | |
a67ff6a5 | 64 | static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */ |
763f356c | 65 | |
763f356c TI |
66 | module_param_array(index, int, NULL, 0444); |
67 | MODULE_PARM_DESC(index, "Index value for RME HDSPM interface."); | |
68 | ||
69 | module_param_array(id, charp, NULL, 0444); | |
70 | MODULE_PARM_DESC(id, "ID string for RME HDSPM interface."); | |
71 | ||
72 | module_param_array(enable, bool, NULL, 0444); | |
73 | MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards."); | |
74 | ||
763f356c TI |
75 | |
76 | MODULE_AUTHOR | |
0dca1793 AK |
77 | ( |
78 | "Winfried Ritsch <ritsch_AT_iem.at>, " | |
79 | "Paul Davis <paul@linuxaudiosystems.com>, " | |
80 | "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, " | |
81 | "Remy Bruno <remy.bruno@trinnov.com>, " | |
82 | "Florian Faber <faberman@linuxproaudio.org>, " | |
83 | "Adrian Knoth <adi@drcomp.erfurt.thur.de>" | |
84 | ); | |
763f356c TI |
85 | MODULE_DESCRIPTION("RME HDSPM"); |
86 | MODULE_LICENSE("GPL"); | |
87 | MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}"); | |
88 | ||
0dca1793 | 89 | /* --- Write registers. --- |
763f356c TI |
90 | These are defined as byte-offsets from the iobase value. */ |
91 | ||
0dca1793 AK |
92 | #define HDSPM_WR_SETTINGS 0 |
93 | #define HDSPM_outputBufferAddress 32 | |
94 | #define HDSPM_inputBufferAddress 36 | |
763f356c TI |
95 | #define HDSPM_controlRegister 64 |
96 | #define HDSPM_interruptConfirmation 96 | |
97 | #define HDSPM_control2Reg 256 /* not in specs ???????? */ | |
ffb2c3c0 | 98 | #define HDSPM_freqReg 256 /* for AES32 */ |
0dca1793 AK |
99 | #define HDSPM_midiDataOut0 352 /* just believe in old code */ |
100 | #define HDSPM_midiDataOut1 356 | |
ffb2c3c0 | 101 | #define HDSPM_eeprom_wr 384 /* for AES32 */ |
763f356c TI |
102 | |
103 | /* DMA enable for 64 channels, only Bit 0 is relevant */ | |
0dca1793 | 104 | #define HDSPM_outputEnableBase 512 /* 512-767 input DMA */ |
763f356c TI |
105 | #define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */ |
106 | ||
0dca1793 | 107 | /* 16 page addresses for each of the 64 channels DMA buffer in and out |
763f356c TI |
108 | (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */ |
109 | #define HDSPM_pageAddressBufferOut 8192 | |
110 | #define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4) | |
111 | ||
112 | #define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */ | |
113 | ||
114 | #define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */ | |
115 | ||
116 | /* --- Read registers. --- | |
117 | These are defined as byte-offsets from the iobase value */ | |
118 | #define HDSPM_statusRegister 0 | |
3cee5a60 RB |
119 | /*#define HDSPM_statusRegister2 96 */ |
120 | /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at | |
121 | * offset 192, for AES32 *and* MADI | |
122 | * => need to check that offset 192 is working on MADI */ | |
123 | #define HDSPM_statusRegister2 192 | |
124 | #define HDSPM_timecodeRegister 128 | |
763f356c | 125 | |
0dca1793 AK |
126 | /* AIO, RayDAT */ |
127 | #define HDSPM_RD_STATUS_0 0 | |
128 | #define HDSPM_RD_STATUS_1 64 | |
129 | #define HDSPM_RD_STATUS_2 128 | |
130 | #define HDSPM_RD_STATUS_3 192 | |
131 | ||
132 | #define HDSPM_RD_TCO 256 | |
133 | #define HDSPM_RD_PLL_FREQ 512 | |
134 | #define HDSPM_WR_TCO 128 | |
135 | ||
136 | #define HDSPM_TCO1_TCO_lock 0x00000001 | |
137 | #define HDSPM_TCO1_WCK_Input_Range_LSB 0x00000002 | |
138 | #define HDSPM_TCO1_WCK_Input_Range_MSB 0x00000004 | |
139 | #define HDSPM_TCO1_LTC_Input_valid 0x00000008 | |
140 | #define HDSPM_TCO1_WCK_Input_valid 0x00000010 | |
141 | #define HDSPM_TCO1_Video_Input_Format_NTSC 0x00000020 | |
142 | #define HDSPM_TCO1_Video_Input_Format_PAL 0x00000040 | |
143 | ||
144 | #define HDSPM_TCO1_set_TC 0x00000100 | |
145 | #define HDSPM_TCO1_set_drop_frame_flag 0x00000200 | |
146 | #define HDSPM_TCO1_LTC_Format_LSB 0x00000400 | |
147 | #define HDSPM_TCO1_LTC_Format_MSB 0x00000800 | |
148 | ||
149 | #define HDSPM_TCO2_TC_run 0x00010000 | |
150 | #define HDSPM_TCO2_WCK_IO_ratio_LSB 0x00020000 | |
151 | #define HDSPM_TCO2_WCK_IO_ratio_MSB 0x00040000 | |
152 | #define HDSPM_TCO2_set_num_drop_frames_LSB 0x00080000 | |
153 | #define HDSPM_TCO2_set_num_drop_frames_MSB 0x00100000 | |
154 | #define HDSPM_TCO2_set_jam_sync 0x00200000 | |
155 | #define HDSPM_TCO2_set_flywheel 0x00400000 | |
156 | ||
157 | #define HDSPM_TCO2_set_01_4 0x01000000 | |
158 | #define HDSPM_TCO2_set_pull_down 0x02000000 | |
159 | #define HDSPM_TCO2_set_pull_up 0x04000000 | |
160 | #define HDSPM_TCO2_set_freq 0x08000000 | |
161 | #define HDSPM_TCO2_set_term_75R 0x10000000 | |
162 | #define HDSPM_TCO2_set_input_LSB 0x20000000 | |
163 | #define HDSPM_TCO2_set_input_MSB 0x40000000 | |
164 | #define HDSPM_TCO2_set_freq_from_app 0x80000000 | |
165 | ||
166 | ||
167 | #define HDSPM_midiDataOut0 352 | |
168 | #define HDSPM_midiDataOut1 356 | |
169 | #define HDSPM_midiDataOut2 368 | |
170 | ||
763f356c TI |
171 | #define HDSPM_midiDataIn0 360 |
172 | #define HDSPM_midiDataIn1 364 | |
0dca1793 AK |
173 | #define HDSPM_midiDataIn2 372 |
174 | #define HDSPM_midiDataIn3 376 | |
763f356c TI |
175 | |
176 | /* status is data bytes in MIDI-FIFO (0-128) */ | |
0dca1793 AK |
177 | #define HDSPM_midiStatusOut0 384 |
178 | #define HDSPM_midiStatusOut1 388 | |
179 | #define HDSPM_midiStatusOut2 400 | |
180 | ||
181 | #define HDSPM_midiStatusIn0 392 | |
182 | #define HDSPM_midiStatusIn1 396 | |
183 | #define HDSPM_midiStatusIn2 404 | |
184 | #define HDSPM_midiStatusIn3 408 | |
763f356c TI |
185 | |
186 | ||
187 | /* the meters are regular i/o-mapped registers, but offset | |
188 | considerably from the rest. the peak registers are reset | |
0dca1793 | 189 | when read; the least-significant 4 bits are full-scale counters; |
763f356c TI |
190 | the actual peak value is in the most-significant 24 bits. |
191 | */ | |
0dca1793 AK |
192 | |
193 | #define HDSPM_MADI_INPUT_PEAK 4096 | |
194 | #define HDSPM_MADI_PLAYBACK_PEAK 4352 | |
195 | #define HDSPM_MADI_OUTPUT_PEAK 4608 | |
196 | ||
197 | #define HDSPM_MADI_INPUT_RMS_L 6144 | |
198 | #define HDSPM_MADI_PLAYBACK_RMS_L 6400 | |
199 | #define HDSPM_MADI_OUTPUT_RMS_L 6656 | |
200 | ||
201 | #define HDSPM_MADI_INPUT_RMS_H 7168 | |
202 | #define HDSPM_MADI_PLAYBACK_RMS_H 7424 | |
203 | #define HDSPM_MADI_OUTPUT_RMS_H 7680 | |
763f356c TI |
204 | |
205 | /* --- Control Register bits --------- */ | |
206 | #define HDSPM_Start (1<<0) /* start engine */ | |
207 | ||
208 | #define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */ | |
209 | #define HDSPM_Latency1 (1<<2) /* where n is defined */ | |
210 | #define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */ | |
211 | ||
0dca1793 AK |
212 | #define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Autosync */ |
213 | #define HDSPM_c0Master 0x1 /* Master clock bit in settings | |
214 | register [RayDAT, AIO] */ | |
763f356c TI |
215 | |
216 | #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */ | |
217 | ||
218 | #define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */ | |
219 | #define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */ | |
220 | #define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */ | |
3cee5a60 | 221 | #define HDSPM_QuadSpeed (1<<31) /* quad speed bit */ |
763f356c | 222 | |
3cee5a60 | 223 | #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */ |
763f356c | 224 | #define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1, |
3cee5a60 RB |
225 | 56channelMODE=0 */ /* MADI ONLY*/ |
226 | #define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */ | |
763f356c | 227 | |
0dca1793 | 228 | #define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode, |
3cee5a60 RB |
229 | 0=off, 1=on */ /* MADI ONLY */ |
230 | #define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */ | |
763f356c | 231 | |
ef5fa1a4 TI |
232 | #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax |
233 | * -- MADI ONLY | |
234 | */ | |
763f356c TI |
235 | #define HDSPM_InputSelect1 (1<<15) /* should be 0 */ |
236 | ||
3cee5a60 RB |
237 | #define HDSPM_SyncRef2 (1<<13) |
238 | #define HDSPM_SyncRef3 (1<<25) | |
763f356c | 239 | |
3cee5a60 | 240 | #define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */ |
0dca1793 | 241 | #define HDSPM_clr_tms (1<<19) /* clear track marker, do not use |
763f356c TI |
242 | AES additional bits in |
243 | lower 5 Audiodatabits ??? */ | |
3cee5a60 RB |
244 | #define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */ |
245 | #define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */ | |
763f356c | 246 | |
0dca1793 AK |
247 | #define HDSPM_Midi0InterruptEnable 0x0400000 |
248 | #define HDSPM_Midi1InterruptEnable 0x0800000 | |
249 | #define HDSPM_Midi2InterruptEnable 0x0200000 | |
250 | #define HDSPM_Midi3InterruptEnable 0x4000000 | |
763f356c TI |
251 | |
252 | #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */ | |
0dca1793 | 253 | #define HDSPe_FLOAT_FORMAT 0x2000000 |
763f356c | 254 | |
3cee5a60 RB |
255 | #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */ |
256 | #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */ | |
257 | #define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */ | |
258 | ||
259 | #define HDSPM_wclk_sel (1<<30) | |
763f356c TI |
260 | |
261 | /* --- bit helper defines */ | |
262 | #define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2) | |
ef5fa1a4 TI |
263 | #define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|\ |
264 | HDSPM_DoubleSpeed|HDSPM_QuadSpeed) | |
763f356c TI |
265 | #define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1) |
266 | #define HDSPM_InputOptical 0 | |
267 | #define HDSPM_InputCoaxial (HDSPM_InputSelect0) | |
ef5fa1a4 TI |
268 | #define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|\ |
269 | HDSPM_SyncRef2|HDSPM_SyncRef3) | |
763f356c | 270 | |
0dca1793 AK |
271 | #define HDSPM_c0_SyncRef0 0x2 |
272 | #define HDSPM_c0_SyncRef1 0x4 | |
273 | #define HDSPM_c0_SyncRef2 0x8 | |
274 | #define HDSPM_c0_SyncRef3 0x10 | |
275 | #define HDSPM_c0_SyncRefMask (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\ | |
276 | HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3) | |
277 | ||
278 | #define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */ | |
279 | #define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */ | |
280 | #define HDSPM_SYNC_FROM_TCO 2 | |
281 | #define HDSPM_SYNC_FROM_SYNC_IN 3 | |
763f356c TI |
282 | |
283 | #define HDSPM_Frequency32KHz HDSPM_Frequency0 | |
284 | #define HDSPM_Frequency44_1KHz HDSPM_Frequency1 | |
285 | #define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0) | |
286 | #define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0) | |
287 | #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1) | |
ef5fa1a4 TI |
288 | #define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|\ |
289 | HDSPM_Frequency0) | |
3cee5a60 RB |
290 | #define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0) |
291 | #define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1) | |
ef5fa1a4 TI |
292 | #define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|\ |
293 | HDSPM_Frequency0) | |
763f356c | 294 | |
763f356c TI |
295 | |
296 | /* Synccheck Status */ | |
297 | #define HDSPM_SYNC_CHECK_NO_LOCK 0 | |
298 | #define HDSPM_SYNC_CHECK_LOCK 1 | |
299 | #define HDSPM_SYNC_CHECK_SYNC 2 | |
300 | ||
301 | /* AutoSync References - used by "autosync_ref" control switch */ | |
302 | #define HDSPM_AUTOSYNC_FROM_WORD 0 | |
303 | #define HDSPM_AUTOSYNC_FROM_MADI 1 | |
0dca1793 AK |
304 | #define HDSPM_AUTOSYNC_FROM_TCO 2 |
305 | #define HDSPM_AUTOSYNC_FROM_SYNC_IN 3 | |
306 | #define HDSPM_AUTOSYNC_FROM_NONE 4 | |
763f356c TI |
307 | |
308 | /* Possible sources of MADI input */ | |
309 | #define HDSPM_OPTICAL 0 /* optical */ | |
310 | #define HDSPM_COAXIAL 1 /* BNC */ | |
311 | ||
312 | #define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask) | |
0dca1793 | 313 | #define hdspm_decode_latency(x) ((((x) & HDSPM_LatencyMask)>>1)) |
763f356c TI |
314 | |
315 | #define hdspm_encode_in(x) (((x)&0x3)<<14) | |
316 | #define hdspm_decode_in(x) (((x)>>14)&0x3) | |
317 | ||
318 | /* --- control2 register bits --- */ | |
319 | #define HDSPM_TMS (1<<0) | |
320 | #define HDSPM_TCK (1<<1) | |
321 | #define HDSPM_TDI (1<<2) | |
322 | #define HDSPM_JTAG (1<<3) | |
323 | #define HDSPM_PWDN (1<<4) | |
324 | #define HDSPM_PROGRAM (1<<5) | |
325 | #define HDSPM_CONFIG_MODE_0 (1<<6) | |
326 | #define HDSPM_CONFIG_MODE_1 (1<<7) | |
327 | /*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/ | |
328 | #define HDSPM_BIGENDIAN_MODE (1<<9) | |
329 | #define HDSPM_RD_MULTIPLE (1<<10) | |
330 | ||
3cee5a60 | 331 | /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and |
ef5fa1a4 TI |
332 | that do not conflict with specific bits for AES32 seem to be valid also |
333 | for the AES32 | |
334 | */ | |
763f356c | 335 | #define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */ |
ef5fa1a4 TI |
336 | #define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */ |
337 | #define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1 | |
338 | * (like inp0) | |
339 | */ | |
0dca1793 | 340 | |
763f356c | 341 | #define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */ |
0dca1793 AK |
342 | #define HDSPM_madiSync (1<<18) /* MADI is in sync */ |
343 | ||
344 | #define HDSPM_tcoLock 0x00000020 /* Optional TCO locked status FOR HDSPe MADI! */ | |
345 | #define HDSPM_tcoSync 0x10000000 /* Optional TCO sync status */ | |
346 | ||
347 | #define HDSPM_syncInLock 0x00010000 /* Sync In lock status FOR HDSPe MADI! */ | |
348 | #define HDSPM_syncInSync 0x00020000 /* Sync In sync status FOR HDSPe MADI! */ | |
763f356c TI |
349 | |
350 | #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */ | |
0dca1793 AK |
351 | /* since 64byte accurate, last 6 bits are not used */ |
352 | ||
353 | ||
763f356c | 354 | |
763f356c TI |
355 | #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */ |
356 | ||
357 | #define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */ | |
358 | #define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */ | |
359 | #define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */ | |
360 | #define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */ | |
361 | ||
ef5fa1a4 TI |
362 | #define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with |
363 | * Interrupt | |
364 | */ | |
0dca1793 AK |
365 | #define HDSPM_tco_detect 0x08000000 |
366 | #define HDSPM_tco_lock 0x20000000 | |
367 | ||
368 | #define HDSPM_s2_tco_detect 0x00000040 | |
369 | #define HDSPM_s2_AEBO_D 0x00000080 | |
370 | #define HDSPM_s2_AEBI_D 0x00000100 | |
371 | ||
372 | ||
373 | #define HDSPM_midi0IRQPending 0x40000000 | |
374 | #define HDSPM_midi1IRQPending 0x80000000 | |
375 | #define HDSPM_midi2IRQPending 0x20000000 | |
376 | #define HDSPM_midi2IRQPendingAES 0x00000020 | |
377 | #define HDSPM_midi3IRQPending 0x00200000 | |
763f356c TI |
378 | |
379 | /* --- status bit helpers */ | |
ef5fa1a4 TI |
380 | #define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|\ |
381 | HDSPM_madiFreq2|HDSPM_madiFreq3) | |
763f356c TI |
382 | #define HDSPM_madiFreq32 (HDSPM_madiFreq0) |
383 | #define HDSPM_madiFreq44_1 (HDSPM_madiFreq1) | |
384 | #define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1) | |
385 | #define HDSPM_madiFreq64 (HDSPM_madiFreq2) | |
386 | #define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2) | |
387 | #define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2) | |
388 | #define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2) | |
389 | #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3) | |
390 | #define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0) | |
391 | ||
3cee5a60 | 392 | /* Status2 Register bits */ /* MADI ONLY */ |
763f356c | 393 | |
25985edc | 394 | #define HDSPM_version0 (1<<0) /* not really defined but I guess */ |
763f356c TI |
395 | #define HDSPM_version1 (1<<1) /* in former cards it was ??? */ |
396 | #define HDSPM_version2 (1<<2) | |
397 | ||
398 | #define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */ | |
399 | #define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */ | |
400 | ||
401 | #define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */ | |
402 | #define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */ | |
403 | #define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, */ | |
404 | /* missing Bit for 111=128, 1000=176.4, 1001=192 */ | |
405 | ||
0dca1793 AK |
406 | #define HDSPM_SyncRef0 0x10000 /* Sync Reference */ |
407 | #define HDSPM_SyncRef1 0x20000 | |
408 | ||
409 | #define HDSPM_SelSyncRef0 (1<<8) /* AutoSync Source */ | |
763f356c TI |
410 | #define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */ |
411 | #define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */ | |
412 | ||
413 | #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync) | |
414 | ||
415 | #define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2) | |
416 | #define HDSPM_wcFreq32 (HDSPM_wc_freq0) | |
417 | #define HDSPM_wcFreq44_1 (HDSPM_wc_freq1) | |
418 | #define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1) | |
419 | #define HDSPM_wcFreq64 (HDSPM_wc_freq2) | |
420 | #define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2) | |
421 | #define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2) | |
422 | ||
0dca1793 AK |
423 | #define HDSPM_status1_F_0 0x0400000 |
424 | #define HDSPM_status1_F_1 0x0800000 | |
425 | #define HDSPM_status1_F_2 0x1000000 | |
426 | #define HDSPM_status1_F_3 0x2000000 | |
427 | #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3) | |
428 | ||
763f356c | 429 | |
ef5fa1a4 TI |
430 | #define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ |
431 | HDSPM_SelSyncRef2) | |
763f356c TI |
432 | #define HDSPM_SelSyncRef_WORD 0 |
433 | #define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0) | |
0dca1793 AK |
434 | #define HDSPM_SelSyncRef_TCO (HDSPM_SelSyncRef1) |
435 | #define HDSPM_SelSyncRef_SyncIn (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1) | |
ef5fa1a4 TI |
436 | #define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ |
437 | HDSPM_SelSyncRef2) | |
763f356c | 438 | |
3cee5a60 RB |
439 | /* |
440 | For AES32, bits for status, status2 and timecode are different | |
441 | */ | |
442 | /* status */ | |
443 | #define HDSPM_AES32_wcLock 0x0200000 | |
444 | #define HDSPM_AES32_wcFreq_bit 22 | |
0dca1793 | 445 | /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function |
3cee5a60 RB |
446 | HDSPM_bit2freq */ |
447 | #define HDSPM_AES32_syncref_bit 16 | |
448 | /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */ | |
449 | ||
450 | #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0 | |
451 | #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1 | |
452 | #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2 | |
453 | #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3 | |
454 | #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4 | |
455 | #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5 | |
456 | #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6 | |
457 | #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7 | |
458 | #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8 | |
6534599d | 459 | #define HDSPM_AES32_AUTOSYNC_FROM_NONE 9 |
3cee5a60 RB |
460 | |
461 | /* status2 */ | |
462 | /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */ | |
463 | #define HDSPM_LockAES 0x80 | |
464 | #define HDSPM_LockAES1 0x80 | |
465 | #define HDSPM_LockAES2 0x40 | |
466 | #define HDSPM_LockAES3 0x20 | |
467 | #define HDSPM_LockAES4 0x10 | |
468 | #define HDSPM_LockAES5 0x8 | |
469 | #define HDSPM_LockAES6 0x4 | |
470 | #define HDSPM_LockAES7 0x2 | |
471 | #define HDSPM_LockAES8 0x1 | |
472 | /* | |
473 | Timecode | |
474 | After windows driver sources, bits 4*i to 4*i+3 give the input frequency on | |
475 | AES i+1 | |
476 | bits 3210 | |
477 | 0001 32kHz | |
478 | 0010 44.1kHz | |
479 | 0011 48kHz | |
480 | 0100 64kHz | |
481 | 0101 88.2kHz | |
482 | 0110 96kHz | |
483 | 0111 128kHz | |
484 | 1000 176.4kHz | |
485 | 1001 192kHz | |
486 | NB: Timecode register doesn't seem to work on AES32 card revision 230 | |
487 | */ | |
488 | ||
763f356c TI |
489 | /* Mixer Values */ |
490 | #define UNITY_GAIN 32768 /* = 65536/2 */ | |
491 | #define MINUS_INFINITY_GAIN 0 | |
492 | ||
763f356c TI |
493 | /* Number of channels for different Speed Modes */ |
494 | #define MADI_SS_CHANNELS 64 | |
495 | #define MADI_DS_CHANNELS 32 | |
496 | #define MADI_QS_CHANNELS 16 | |
497 | ||
0dca1793 AK |
498 | #define RAYDAT_SS_CHANNELS 36 |
499 | #define RAYDAT_DS_CHANNELS 20 | |
500 | #define RAYDAT_QS_CHANNELS 12 | |
501 | ||
502 | #define AIO_IN_SS_CHANNELS 14 | |
503 | #define AIO_IN_DS_CHANNELS 10 | |
504 | #define AIO_IN_QS_CHANNELS 8 | |
505 | #define AIO_OUT_SS_CHANNELS 16 | |
506 | #define AIO_OUT_DS_CHANNELS 12 | |
507 | #define AIO_OUT_QS_CHANNELS 10 | |
508 | ||
d2d10a21 AK |
509 | #define AES32_CHANNELS 16 |
510 | ||
763f356c TI |
511 | /* the size of a substream (1 mono data stream) */ |
512 | #define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024) | |
513 | #define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES) | |
514 | ||
515 | /* the size of the area we need to allocate for DMA transfers. the | |
516 | size is the same regardless of the number of channels, and | |
0dca1793 | 517 | also the latency to use. |
763f356c TI |
518 | for one direction !!! |
519 | */ | |
ffb2c3c0 | 520 | #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES) |
763f356c TI |
521 | #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024) |
522 | ||
0dca1793 AK |
523 | #define HDSPM_RAYDAT_REV 211 |
524 | #define HDSPM_AIO_REV 212 | |
525 | #define HDSPM_MADIFACE_REV 213 | |
3cee5a60 | 526 | |
6534599d RB |
527 | /* speed factor modes */ |
528 | #define HDSPM_SPEED_SINGLE 0 | |
529 | #define HDSPM_SPEED_DOUBLE 1 | |
530 | #define HDSPM_SPEED_QUAD 2 | |
0dca1793 | 531 | |
6534599d RB |
532 | /* names for speed modes */ |
533 | static char *hdspm_speed_names[] = { "single", "double", "quad" }; | |
534 | ||
0dca1793 AK |
535 | static char *texts_autosync_aes_tco[] = { "Word Clock", |
536 | "AES1", "AES2", "AES3", "AES4", | |
537 | "AES5", "AES6", "AES7", "AES8", | |
538 | "TCO" }; | |
539 | static char *texts_autosync_aes[] = { "Word Clock", | |
540 | "AES1", "AES2", "AES3", "AES4", | |
541 | "AES5", "AES6", "AES7", "AES8" }; | |
542 | static char *texts_autosync_madi_tco[] = { "Word Clock", | |
543 | "MADI", "TCO", "Sync In" }; | |
544 | static char *texts_autosync_madi[] = { "Word Clock", | |
545 | "MADI", "Sync In" }; | |
546 | ||
547 | static char *texts_autosync_raydat_tco[] = { | |
548 | "Word Clock", | |
549 | "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", | |
550 | "AES", "SPDIF", "TCO", "Sync In" | |
551 | }; | |
552 | static char *texts_autosync_raydat[] = { | |
553 | "Word Clock", | |
554 | "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", | |
555 | "AES", "SPDIF", "Sync In" | |
556 | }; | |
557 | static char *texts_autosync_aio_tco[] = { | |
558 | "Word Clock", | |
559 | "ADAT", "AES", "SPDIF", "TCO", "Sync In" | |
560 | }; | |
561 | static char *texts_autosync_aio[] = { "Word Clock", | |
562 | "ADAT", "AES", "SPDIF", "Sync In" }; | |
563 | ||
564 | static char *texts_freq[] = { | |
565 | "No Lock", | |
566 | "32 kHz", | |
567 | "44.1 kHz", | |
568 | "48 kHz", | |
569 | "64 kHz", | |
570 | "88.2 kHz", | |
571 | "96 kHz", | |
572 | "128 kHz", | |
573 | "176.4 kHz", | |
574 | "192 kHz" | |
575 | }; | |
576 | ||
0dca1793 AK |
577 | static char *texts_ports_madi[] = { |
578 | "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6", | |
579 | "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12", | |
580 | "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18", | |
581 | "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24", | |
582 | "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30", | |
583 | "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36", | |
584 | "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42", | |
585 | "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48", | |
586 | "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54", | |
587 | "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60", | |
588 | "MADI.61", "MADI.62", "MADI.63", "MADI.64", | |
589 | }; | |
590 | ||
591 | ||
592 | static char *texts_ports_raydat_ss[] = { | |
593 | "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6", | |
594 | "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", | |
595 | "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2", | |
596 | "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8", | |
597 | "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6", | |
598 | "ADAT4.7", "ADAT4.8", | |
599 | "AES.L", "AES.R", | |
600 | "SPDIF.L", "SPDIF.R" | |
601 | }; | |
602 | ||
603 | static char *texts_ports_raydat_ds[] = { | |
604 | "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", | |
605 | "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", | |
606 | "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4", | |
607 | "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", | |
608 | "AES.L", "AES.R", | |
609 | "SPDIF.L", "SPDIF.R" | |
610 | }; | |
611 | ||
612 | static char *texts_ports_raydat_qs[] = { | |
613 | "ADAT1.1", "ADAT1.2", | |
614 | "ADAT2.1", "ADAT2.2", | |
615 | "ADAT3.1", "ADAT3.2", | |
616 | "ADAT4.1", "ADAT4.2", | |
617 | "AES.L", "AES.R", | |
618 | "SPDIF.L", "SPDIF.R" | |
619 | }; | |
620 | ||
621 | ||
622 | static char *texts_ports_aio_in_ss[] = { | |
623 | "Analogue.L", "Analogue.R", | |
624 | "AES.L", "AES.R", | |
625 | "SPDIF.L", "SPDIF.R", | |
626 | "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", | |
627 | "ADAT.7", "ADAT.8" | |
628 | }; | |
629 | ||
630 | static char *texts_ports_aio_out_ss[] = { | |
631 | "Analogue.L", "Analogue.R", | |
632 | "AES.L", "AES.R", | |
633 | "SPDIF.L", "SPDIF.R", | |
634 | "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", | |
635 | "ADAT.7", "ADAT.8", | |
636 | "Phone.L", "Phone.R" | |
637 | }; | |
638 | ||
639 | static char *texts_ports_aio_in_ds[] = { | |
640 | "Analogue.L", "Analogue.R", | |
641 | "AES.L", "AES.R", | |
642 | "SPDIF.L", "SPDIF.R", | |
643 | "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4" | |
644 | }; | |
645 | ||
646 | static char *texts_ports_aio_out_ds[] = { | |
647 | "Analogue.L", "Analogue.R", | |
648 | "AES.L", "AES.R", | |
649 | "SPDIF.L", "SPDIF.R", | |
650 | "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", | |
651 | "Phone.L", "Phone.R" | |
652 | }; | |
653 | ||
654 | static char *texts_ports_aio_in_qs[] = { | |
655 | "Analogue.L", "Analogue.R", | |
656 | "AES.L", "AES.R", | |
657 | "SPDIF.L", "SPDIF.R", | |
658 | "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4" | |
659 | }; | |
660 | ||
661 | static char *texts_ports_aio_out_qs[] = { | |
662 | "Analogue.L", "Analogue.R", | |
663 | "AES.L", "AES.R", | |
664 | "SPDIF.L", "SPDIF.R", | |
665 | "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", | |
666 | "Phone.L", "Phone.R" | |
667 | }; | |
668 | ||
432d2500 AK |
669 | static char *texts_ports_aes32[] = { |
670 | "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7", | |
671 | "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14", | |
672 | "AES.15", "AES.16" | |
673 | }; | |
674 | ||
55a57606 AK |
675 | /* These tables map the ALSA channels 1..N to the channels that we |
676 | need to use in order to find the relevant channel buffer. RME | |
677 | refers to this kind of mapping as between "the ADAT channel and | |
678 | the DMA channel." We index it using the logical audio channel, | |
679 | and the value is the DMA channel (i.e. channel buffer number) | |
680 | where the data for that channel can be read/written from/to. | |
681 | */ | |
682 | ||
683 | static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = { | |
684 | 0, 1, 2, 3, 4, 5, 6, 7, | |
685 | 8, 9, 10, 11, 12, 13, 14, 15, | |
686 | 16, 17, 18, 19, 20, 21, 22, 23, | |
687 | 24, 25, 26, 27, 28, 29, 30, 31, | |
688 | 32, 33, 34, 35, 36, 37, 38, 39, | |
689 | 40, 41, 42, 43, 44, 45, 46, 47, | |
690 | 48, 49, 50, 51, 52, 53, 54, 55, | |
691 | 56, 57, 58, 59, 60, 61, 62, 63 | |
692 | }; | |
693 | ||
55a57606 AK |
694 | static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = { |
695 | 4, 5, 6, 7, 8, 9, 10, 11, /* ADAT 1 */ | |
696 | 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */ | |
697 | 20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */ | |
698 | 28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */ | |
699 | 0, 1, /* AES */ | |
700 | 2, 3, /* SPDIF */ | |
701 | -1, -1, -1, -1, | |
702 | -1, -1, -1, -1, -1, -1, -1, -1, | |
703 | -1, -1, -1, -1, -1, -1, -1, -1, | |
704 | -1, -1, -1, -1, -1, -1, -1, -1, | |
705 | }; | |
706 | ||
707 | static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = { | |
708 | 4, 5, 6, 7, /* ADAT 1 */ | |
709 | 8, 9, 10, 11, /* ADAT 2 */ | |
710 | 12, 13, 14, 15, /* ADAT 3 */ | |
711 | 16, 17, 18, 19, /* ADAT 4 */ | |
712 | 0, 1, /* AES */ | |
713 | 2, 3, /* SPDIF */ | |
714 | -1, -1, -1, -1, | |
715 | -1, -1, -1, -1, -1, -1, -1, -1, | |
716 | -1, -1, -1, -1, -1, -1, -1, -1, | |
717 | -1, -1, -1, -1, -1, -1, -1, -1, | |
718 | -1, -1, -1, -1, -1, -1, -1, -1, | |
719 | -1, -1, -1, -1, -1, -1, -1, -1, | |
720 | }; | |
721 | ||
722 | static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = { | |
723 | 4, 5, /* ADAT 1 */ | |
724 | 6, 7, /* ADAT 2 */ | |
725 | 8, 9, /* ADAT 3 */ | |
726 | 10, 11, /* ADAT 4 */ | |
727 | 0, 1, /* AES */ | |
728 | 2, 3, /* SPDIF */ | |
729 | -1, -1, -1, -1, | |
730 | -1, -1, -1, -1, -1, -1, -1, -1, | |
731 | -1, -1, -1, -1, -1, -1, -1, -1, | |
732 | -1, -1, -1, -1, -1, -1, -1, -1, | |
733 | -1, -1, -1, -1, -1, -1, -1, -1, | |
734 | -1, -1, -1, -1, -1, -1, -1, -1, | |
735 | -1, -1, -1, -1, -1, -1, -1, -1, | |
736 | }; | |
737 | ||
738 | static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = { | |
739 | 0, 1, /* line in */ | |
740 | 8, 9, /* aes in, */ | |
741 | 10, 11, /* spdif in */ | |
742 | 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */ | |
743 | -1, -1, | |
744 | -1, -1, -1, -1, -1, -1, -1, -1, | |
745 | -1, -1, -1, -1, -1, -1, -1, -1, | |
746 | -1, -1, -1, -1, -1, -1, -1, -1, | |
747 | -1, -1, -1, -1, -1, -1, -1, -1, | |
748 | -1, -1, -1, -1, -1, -1, -1, -1, | |
749 | -1, -1, -1, -1, -1, -1, -1, -1, | |
750 | }; | |
751 | ||
752 | static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = { | |
753 | 0, 1, /* line out */ | |
754 | 8, 9, /* aes out */ | |
755 | 10, 11, /* spdif out */ | |
756 | 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */ | |
757 | 6, 7, /* phone out */ | |
758 | -1, -1, -1, -1, -1, -1, -1, -1, | |
759 | -1, -1, -1, -1, -1, -1, -1, -1, | |
760 | -1, -1, -1, -1, -1, -1, -1, -1, | |
761 | -1, -1, -1, -1, -1, -1, -1, -1, | |
762 | -1, -1, -1, -1, -1, -1, -1, -1, | |
763 | -1, -1, -1, -1, -1, -1, -1, -1, | |
764 | }; | |
765 | ||
766 | static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = { | |
767 | 0, 1, /* line in */ | |
768 | 8, 9, /* aes in */ | |
769 | 10, 11, /* spdif in */ | |
770 | 12, 14, 16, 18, /* adat in */ | |
771 | -1, -1, -1, -1, -1, -1, | |
772 | -1, -1, -1, -1, -1, -1, -1, -1, | |
773 | -1, -1, -1, -1, -1, -1, -1, -1, | |
774 | -1, -1, -1, -1, -1, -1, -1, -1, | |
775 | -1, -1, -1, -1, -1, -1, -1, -1, | |
776 | -1, -1, -1, -1, -1, -1, -1, -1, | |
777 | -1, -1, -1, -1, -1, -1, -1, -1 | |
778 | }; | |
779 | ||
780 | static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = { | |
781 | 0, 1, /* line out */ | |
782 | 8, 9, /* aes out */ | |
783 | 10, 11, /* spdif out */ | |
784 | 12, 14, 16, 18, /* adat out */ | |
785 | 6, 7, /* phone out */ | |
786 | -1, -1, -1, -1, | |
787 | -1, -1, -1, -1, -1, -1, -1, -1, | |
788 | -1, -1, -1, -1, -1, -1, -1, -1, | |
789 | -1, -1, -1, -1, -1, -1, -1, -1, | |
790 | -1, -1, -1, -1, -1, -1, -1, -1, | |
791 | -1, -1, -1, -1, -1, -1, -1, -1, | |
792 | -1, -1, -1, -1, -1, -1, -1, -1 | |
793 | }; | |
794 | ||
795 | static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = { | |
796 | 0, 1, /* line in */ | |
797 | 8, 9, /* aes in */ | |
798 | 10, 11, /* spdif in */ | |
799 | 12, 16, /* adat in */ | |
800 | -1, -1, -1, -1, -1, -1, -1, -1, | |
801 | -1, -1, -1, -1, -1, -1, -1, -1, | |
802 | -1, -1, -1, -1, -1, -1, -1, -1, | |
803 | -1, -1, -1, -1, -1, -1, -1, -1, | |
804 | -1, -1, -1, -1, -1, -1, -1, -1, | |
805 | -1, -1, -1, -1, -1, -1, -1, -1, | |
806 | -1, -1, -1, -1, -1, -1, -1, -1 | |
807 | }; | |
808 | ||
809 | static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = { | |
810 | 0, 1, /* line out */ | |
811 | 8, 9, /* aes out */ | |
812 | 10, 11, /* spdif out */ | |
813 | 12, 16, /* adat out */ | |
814 | 6, 7, /* phone out */ | |
815 | -1, -1, -1, -1, -1, -1, | |
816 | -1, -1, -1, -1, -1, -1, -1, -1, | |
817 | -1, -1, -1, -1, -1, -1, -1, -1, | |
818 | -1, -1, -1, -1, -1, -1, -1, -1, | |
819 | -1, -1, -1, -1, -1, -1, -1, -1, | |
820 | -1, -1, -1, -1, -1, -1, -1, -1, | |
821 | -1, -1, -1, -1, -1, -1, -1, -1 | |
822 | }; | |
823 | ||
432d2500 AK |
824 | static char channel_map_aes32[HDSPM_MAX_CHANNELS] = { |
825 | 0, 1, 2, 3, 4, 5, 6, 7, | |
826 | 8, 9, 10, 11, 12, 13, 14, 15, | |
827 | -1, -1, -1, -1, -1, -1, -1, -1, | |
828 | -1, -1, -1, -1, -1, -1, -1, -1, | |
829 | -1, -1, -1, -1, -1, -1, -1, -1, | |
830 | -1, -1, -1, -1, -1, -1, -1, -1, | |
831 | -1, -1, -1, -1, -1, -1, -1, -1, | |
832 | -1, -1, -1, -1, -1, -1, -1, -1 | |
833 | }; | |
834 | ||
98274f07 TI |
835 | struct hdspm_midi { |
836 | struct hdspm *hdspm; | |
763f356c | 837 | int id; |
98274f07 TI |
838 | struct snd_rawmidi *rmidi; |
839 | struct snd_rawmidi_substream *input; | |
840 | struct snd_rawmidi_substream *output; | |
763f356c TI |
841 | char istimer; /* timer in use */ |
842 | struct timer_list timer; | |
843 | spinlock_t lock; | |
844 | int pending; | |
0dca1793 AK |
845 | int dataIn; |
846 | int statusIn; | |
847 | int dataOut; | |
848 | int statusOut; | |
849 | int ie; | |
850 | int irq; | |
851 | }; | |
852 | ||
853 | struct hdspm_tco { | |
854 | int input; | |
855 | int framerate; | |
856 | int wordclock; | |
857 | int samplerate; | |
858 | int pull; | |
859 | int term; /* 0 = off, 1 = on */ | |
763f356c TI |
860 | }; |
861 | ||
98274f07 | 862 | struct hdspm { |
763f356c | 863 | spinlock_t lock; |
ef5fa1a4 TI |
864 | /* only one playback and/or capture stream */ |
865 | struct snd_pcm_substream *capture_substream; | |
866 | struct snd_pcm_substream *playback_substream; | |
763f356c TI |
867 | |
868 | char *card_name; /* for procinfo */ | |
3cee5a60 RB |
869 | unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/ |
870 | ||
0dca1793 | 871 | uint8_t io_type; |
763f356c | 872 | |
763f356c TI |
873 | int monitor_outs; /* set up monitoring outs init flag */ |
874 | ||
875 | u32 control_register; /* cached value */ | |
876 | u32 control2_register; /* cached value */ | |
0dca1793 | 877 | u32 settings_register; |
763f356c | 878 | |
0dca1793 | 879 | struct hdspm_midi midi[4]; |
763f356c TI |
880 | struct tasklet_struct midi_tasklet; |
881 | ||
882 | size_t period_bytes; | |
0dca1793 AK |
883 | unsigned char ss_in_channels; |
884 | unsigned char ds_in_channels; | |
885 | unsigned char qs_in_channels; | |
886 | unsigned char ss_out_channels; | |
887 | unsigned char ds_out_channels; | |
888 | unsigned char qs_out_channels; | |
889 | ||
890 | unsigned char max_channels_in; | |
891 | unsigned char max_channels_out; | |
892 | ||
286bed0f TI |
893 | signed char *channel_map_in; |
894 | signed char *channel_map_out; | |
0dca1793 | 895 | |
286bed0f TI |
896 | signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs; |
897 | signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs; | |
0dca1793 AK |
898 | |
899 | char **port_names_in; | |
900 | char **port_names_out; | |
901 | ||
902 | char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs; | |
903 | char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs; | |
763f356c TI |
904 | |
905 | unsigned char *playback_buffer; /* suitably aligned address */ | |
906 | unsigned char *capture_buffer; /* suitably aligned address */ | |
907 | ||
908 | pid_t capture_pid; /* process id which uses capture */ | |
909 | pid_t playback_pid; /* process id which uses capture */ | |
910 | int running; /* running status */ | |
911 | ||
912 | int last_external_sample_rate; /* samplerate mystic ... */ | |
913 | int last_internal_sample_rate; | |
914 | int system_sample_rate; | |
915 | ||
763f356c TI |
916 | int dev; /* Hardware vars... */ |
917 | int irq; | |
918 | unsigned long port; | |
919 | void __iomem *iobase; | |
920 | ||
921 | int irq_count; /* for debug */ | |
0dca1793 | 922 | int midiPorts; |
763f356c | 923 | |
98274f07 TI |
924 | struct snd_card *card; /* one card */ |
925 | struct snd_pcm *pcm; /* has one pcm */ | |
926 | struct snd_hwdep *hwdep; /* and a hwdep for additional ioctl */ | |
763f356c TI |
927 | struct pci_dev *pci; /* and an pci info */ |
928 | ||
929 | /* Mixer vars */ | |
ef5fa1a4 TI |
930 | /* fast alsa mixer */ |
931 | struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS]; | |
932 | /* but input to much, so not used */ | |
933 | struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS]; | |
25985edc | 934 | /* full mixer accessible over mixer ioctl or hwdep-device */ |
ef5fa1a4 | 935 | struct hdspm_mixer *mixer; |
763f356c | 936 | |
0dca1793 | 937 | struct hdspm_tco *tco; /* NULL if no TCO detected */ |
763f356c | 938 | |
0dca1793 AK |
939 | char **texts_autosync; |
940 | int texts_autosync_items; | |
763f356c | 941 | |
0dca1793 | 942 | cycles_t last_interrupt; |
730a5865 | 943 | |
7d53a631 AK |
944 | unsigned int serial; |
945 | ||
730a5865 | 946 | struct hdspm_peak_rms peak_rms; |
763f356c TI |
947 | }; |
948 | ||
763f356c | 949 | |
cebe41d4 | 950 | static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = { |
763f356c TI |
951 | { |
952 | .vendor = PCI_VENDOR_ID_XILINX, | |
953 | .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI, | |
954 | .subvendor = PCI_ANY_ID, | |
955 | .subdevice = PCI_ANY_ID, | |
956 | .class = 0, | |
957 | .class_mask = 0, | |
958 | .driver_data = 0}, | |
959 | {0,} | |
960 | }; | |
961 | ||
962 | MODULE_DEVICE_TABLE(pci, snd_hdspm_ids); | |
963 | ||
964 | /* prototypes */ | |
98274f07 TI |
965 | static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card, |
966 | struct hdspm * hdspm); | |
967 | static int __devinit snd_hdspm_create_pcm(struct snd_card *card, | |
968 | struct hdspm * hdspm); | |
969 | ||
0dca1793 AK |
970 | static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm); |
971 | static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm); | |
972 | static int hdspm_autosync_ref(struct hdspm *hdspm); | |
973 | static int snd_hdspm_set_defaults(struct hdspm *hdspm); | |
21a164df | 974 | static int hdspm_system_clock_mode(struct hdspm *hdspm); |
0dca1793 | 975 | static void hdspm_set_sgbuf(struct hdspm *hdspm, |
77a23f26 | 976 | struct snd_pcm_substream *substream, |
763f356c TI |
977 | unsigned int reg, int channels); |
978 | ||
3cee5a60 RB |
979 | static inline int HDSPM_bit2freq(int n) |
980 | { | |
62cef821 DV |
981 | static const int bit2freq_tab[] = { |
982 | 0, 32000, 44100, 48000, 64000, 88200, | |
3cee5a60 RB |
983 | 96000, 128000, 176400, 192000 }; |
984 | if (n < 1 || n > 9) | |
985 | return 0; | |
986 | return bit2freq_tab[n]; | |
987 | } | |
988 | ||
0dca1793 | 989 | /* Write/read to/from HDSPM with Adresses in Bytes |
763f356c TI |
990 | not words but only 32Bit writes are allowed */ |
991 | ||
98274f07 | 992 | static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg, |
763f356c TI |
993 | unsigned int val) |
994 | { | |
995 | writel(val, hdspm->iobase + reg); | |
996 | } | |
997 | ||
98274f07 | 998 | static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg) |
763f356c TI |
999 | { |
1000 | return readl(hdspm->iobase + reg); | |
1001 | } | |
1002 | ||
0dca1793 AK |
1003 | /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader |
1004 | mixer is write only on hardware so we have to cache him for read | |
763f356c TI |
1005 | each fader is a u32, but uses only the first 16 bit */ |
1006 | ||
98274f07 | 1007 | static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan, |
763f356c TI |
1008 | unsigned int in) |
1009 | { | |
5bab2482 | 1010 | if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) |
763f356c TI |
1011 | return 0; |
1012 | ||
1013 | return hdspm->mixer->ch[chan].in[in]; | |
1014 | } | |
1015 | ||
98274f07 | 1016 | static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan, |
763f356c TI |
1017 | unsigned int pb) |
1018 | { | |
5bab2482 | 1019 | if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) |
763f356c TI |
1020 | return 0; |
1021 | return hdspm->mixer->ch[chan].pb[pb]; | |
1022 | } | |
1023 | ||
62cef821 | 1024 | static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan, |
763f356c TI |
1025 | unsigned int in, unsigned short data) |
1026 | { | |
1027 | if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) | |
1028 | return -1; | |
1029 | ||
1030 | hdspm_write(hdspm, | |
1031 | HDSPM_MADI_mixerBase + | |
1032 | ((in + 128 * chan) * sizeof(u32)), | |
1033 | (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF)); | |
1034 | return 0; | |
1035 | } | |
1036 | ||
62cef821 | 1037 | static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan, |
763f356c TI |
1038 | unsigned int pb, unsigned short data) |
1039 | { | |
1040 | if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) | |
1041 | return -1; | |
1042 | ||
1043 | hdspm_write(hdspm, | |
1044 | HDSPM_MADI_mixerBase + | |
1045 | ((64 + pb + 128 * chan) * sizeof(u32)), | |
1046 | (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF)); | |
1047 | return 0; | |
1048 | } | |
1049 | ||
1050 | ||
1051 | /* enable DMA for specific channels, now available for DSP-MADI */ | |
98274f07 | 1052 | static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v) |
763f356c TI |
1053 | { |
1054 | hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v); | |
1055 | } | |
1056 | ||
98274f07 | 1057 | static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v) |
763f356c TI |
1058 | { |
1059 | hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v); | |
1060 | } | |
1061 | ||
1062 | /* check if same process is writing and reading */ | |
62cef821 | 1063 | static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm) |
763f356c TI |
1064 | { |
1065 | unsigned long flags; | |
1066 | int ret = 1; | |
1067 | ||
1068 | spin_lock_irqsave(&hdspm->lock, flags); | |
1069 | if ((hdspm->playback_pid != hdspm->capture_pid) && | |
1070 | (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) { | |
1071 | ret = 0; | |
1072 | } | |
1073 | spin_unlock_irqrestore(&hdspm->lock, flags); | |
1074 | return ret; | |
1075 | } | |
1076 | ||
1077 | /* check for external sample rate */ | |
62cef821 | 1078 | static int hdspm_external_sample_rate(struct hdspm *hdspm) |
763f356c | 1079 | { |
0dca1793 AK |
1080 | unsigned int status, status2, timecode; |
1081 | int syncref, rate = 0, rate_bits; | |
3cee5a60 | 1082 | |
0dca1793 AK |
1083 | switch (hdspm->io_type) { |
1084 | case AES32: | |
1085 | status2 = hdspm_read(hdspm, HDSPM_statusRegister2); | |
1086 | status = hdspm_read(hdspm, HDSPM_statusRegister); | |
7c4a95b5 | 1087 | timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); |
0dca1793 AK |
1088 | |
1089 | syncref = hdspm_autosync_ref(hdspm); | |
3cee5a60 RB |
1090 | |
1091 | if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD && | |
1092 | status & HDSPM_AES32_wcLock) | |
0dca1793 AK |
1093 | return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF); |
1094 | ||
3cee5a60 | 1095 | if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 && |
0dca1793 AK |
1096 | syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 && |
1097 | status2 & (HDSPM_LockAES >> | |
1098 | (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1))) | |
1099 | return HDSPM_bit2freq((timecode >> (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF); | |
3cee5a60 | 1100 | return 0; |
0dca1793 AK |
1101 | break; |
1102 | ||
1103 | case MADIface: | |
1104 | status = hdspm_read(hdspm, HDSPM_statusRegister); | |
1105 | ||
1106 | if (!(status & HDSPM_madiLock)) { | |
1107 | rate = 0; /* no lock */ | |
1108 | } else { | |
1109 | switch (status & (HDSPM_status1_freqMask)) { | |
1110 | case HDSPM_status1_F_0*1: | |
1111 | rate = 32000; break; | |
1112 | case HDSPM_status1_F_0*2: | |
1113 | rate = 44100; break; | |
1114 | case HDSPM_status1_F_0*3: | |
1115 | rate = 48000; break; | |
1116 | case HDSPM_status1_F_0*4: | |
1117 | rate = 64000; break; | |
1118 | case HDSPM_status1_F_0*5: | |
1119 | rate = 88200; break; | |
1120 | case HDSPM_status1_F_0*6: | |
1121 | rate = 96000; break; | |
1122 | case HDSPM_status1_F_0*7: | |
1123 | rate = 128000; break; | |
1124 | case HDSPM_status1_F_0*8: | |
1125 | rate = 176400; break; | |
1126 | case HDSPM_status1_F_0*9: | |
1127 | rate = 192000; break; | |
1128 | default: | |
1129 | rate = 0; break; | |
1130 | } | |
1131 | } | |
1132 | ||
1133 | break; | |
1134 | ||
1135 | case MADI: | |
1136 | case AIO: | |
1137 | case RayDAT: | |
1138 | status2 = hdspm_read(hdspm, HDSPM_statusRegister2); | |
1139 | status = hdspm_read(hdspm, HDSPM_statusRegister); | |
1140 | rate = 0; | |
763f356c | 1141 | |
3cee5a60 RB |
1142 | /* if wordclock has synced freq and wordclock is valid */ |
1143 | if ((status2 & HDSPM_wcLock) != 0 && | |
fedf1535 | 1144 | (status2 & HDSPM_SelSyncRef0) == 0) { |
763f356c | 1145 | |
3cee5a60 | 1146 | rate_bits = status2 & HDSPM_wcFreqMask; |
763f356c | 1147 | |
0dca1793 | 1148 | |
3cee5a60 RB |
1149 | switch (rate_bits) { |
1150 | case HDSPM_wcFreq32: | |
1151 | rate = 32000; | |
1152 | break; | |
1153 | case HDSPM_wcFreq44_1: | |
1154 | rate = 44100; | |
1155 | break; | |
1156 | case HDSPM_wcFreq48: | |
1157 | rate = 48000; | |
1158 | break; | |
1159 | case HDSPM_wcFreq64: | |
1160 | rate = 64000; | |
1161 | break; | |
1162 | case HDSPM_wcFreq88_2: | |
1163 | rate = 88200; | |
1164 | break; | |
1165 | case HDSPM_wcFreq96: | |
1166 | rate = 96000; | |
1167 | break; | |
3cee5a60 RB |
1168 | default: |
1169 | rate = 0; | |
1170 | break; | |
1171 | } | |
763f356c | 1172 | } |
763f356c | 1173 | |
ef5fa1a4 TI |
1174 | /* if rate detected and Syncref is Word than have it, |
1175 | * word has priority to MADI | |
1176 | */ | |
3cee5a60 | 1177 | if (rate != 0 && |
0dca1793 | 1178 | (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD) |
3cee5a60 | 1179 | return rate; |
763f356c | 1180 | |
0dca1793 | 1181 | /* maybe a madi input (which is taken if sel sync is madi) */ |
3cee5a60 RB |
1182 | if (status & HDSPM_madiLock) { |
1183 | rate_bits = status & HDSPM_madiFreqMask; | |
763f356c | 1184 | |
3cee5a60 RB |
1185 | switch (rate_bits) { |
1186 | case HDSPM_madiFreq32: | |
1187 | rate = 32000; | |
1188 | break; | |
1189 | case HDSPM_madiFreq44_1: | |
1190 | rate = 44100; | |
1191 | break; | |
1192 | case HDSPM_madiFreq48: | |
1193 | rate = 48000; | |
1194 | break; | |
1195 | case HDSPM_madiFreq64: | |
1196 | rate = 64000; | |
1197 | break; | |
1198 | case HDSPM_madiFreq88_2: | |
1199 | rate = 88200; | |
1200 | break; | |
1201 | case HDSPM_madiFreq96: | |
1202 | rate = 96000; | |
1203 | break; | |
1204 | case HDSPM_madiFreq128: | |
1205 | rate = 128000; | |
1206 | break; | |
1207 | case HDSPM_madiFreq176_4: | |
1208 | rate = 176400; | |
1209 | break; | |
1210 | case HDSPM_madiFreq192: | |
1211 | rate = 192000; | |
1212 | break; | |
1213 | default: | |
1214 | rate = 0; | |
1215 | break; | |
1216 | } | |
d12c51d8 AK |
1217 | |
1218 | /* QS and DS rates normally can not be detected | |
1219 | * automatically by the card. Only exception is MADI | |
1220 | * in 96k frame mode. | |
1221 | * | |
1222 | * So if we read SS values (32 .. 48k), check for | |
1223 | * user-provided DS/QS bits in the control register | |
1224 | * and multiply the base frequency accordingly. | |
1225 | */ | |
1226 | if (rate <= 48000) { | |
1227 | if (hdspm->control_register & HDSPM_QuadSpeed) | |
1228 | rate *= 4; | |
1229 | else if (hdspm->control_register & | |
1230 | HDSPM_DoubleSpeed) | |
1231 | rate *= 2; | |
1232 | } | |
763f356c | 1233 | } |
0dca1793 | 1234 | break; |
763f356c | 1235 | } |
0dca1793 AK |
1236 | |
1237 | return rate; | |
763f356c TI |
1238 | } |
1239 | ||
7cb155ff AK |
1240 | /* return latency in samples per period */ |
1241 | static int hdspm_get_latency(struct hdspm *hdspm) | |
1242 | { | |
1243 | int n; | |
1244 | ||
1245 | n = hdspm_decode_latency(hdspm->control_register); | |
1246 | ||
1247 | /* Special case for new RME cards with 32 samples period size. | |
1248 | * The three latency bits in the control register | |
1249 | * (HDSP_LatencyMask) encode latency values of 64 samples as | |
1250 | * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7 | |
1251 | * denotes 8192 samples, but on new cards like RayDAT or AIO, | |
1252 | * it corresponds to 32 samples. | |
1253 | */ | |
1254 | if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type)) | |
1255 | n = -1; | |
1256 | ||
1257 | return 1 << (n + 6); | |
1258 | } | |
1259 | ||
763f356c | 1260 | /* Latency function */ |
0dca1793 | 1261 | static inline void hdspm_compute_period_size(struct hdspm *hdspm) |
763f356c | 1262 | { |
7cb155ff | 1263 | hdspm->period_bytes = 4 * hdspm_get_latency(hdspm); |
763f356c TI |
1264 | } |
1265 | ||
0dca1793 AK |
1266 | |
1267 | static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm) | |
763f356c TI |
1268 | { |
1269 | int position; | |
1270 | ||
1271 | position = hdspm_read(hdspm, HDSPM_statusRegister); | |
483cee77 AK |
1272 | |
1273 | switch (hdspm->io_type) { | |
1274 | case RayDAT: | |
1275 | case AIO: | |
1276 | position &= HDSPM_BufferPositionMask; | |
1277 | position /= 4; /* Bytes per sample */ | |
1278 | break; | |
1279 | default: | |
1280 | position = (position & HDSPM_BufferID) ? | |
1281 | (hdspm->period_bytes / 4) : 0; | |
1282 | } | |
763f356c TI |
1283 | |
1284 | return position; | |
1285 | } | |
1286 | ||
1287 | ||
98274f07 | 1288 | static inline void hdspm_start_audio(struct hdspm * s) |
763f356c TI |
1289 | { |
1290 | s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start); | |
1291 | hdspm_write(s, HDSPM_controlRegister, s->control_register); | |
1292 | } | |
1293 | ||
98274f07 | 1294 | static inline void hdspm_stop_audio(struct hdspm * s) |
763f356c TI |
1295 | { |
1296 | s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable); | |
1297 | hdspm_write(s, HDSPM_controlRegister, s->control_register); | |
1298 | } | |
1299 | ||
1300 | /* should I silence all or only opened ones ? doit all for first even is 4MB*/ | |
62cef821 | 1301 | static void hdspm_silence_playback(struct hdspm *hdspm) |
763f356c TI |
1302 | { |
1303 | int i; | |
1304 | int n = hdspm->period_bytes; | |
1305 | void *buf = hdspm->playback_buffer; | |
1306 | ||
3cee5a60 RB |
1307 | if (buf == NULL) |
1308 | return; | |
763f356c TI |
1309 | |
1310 | for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { | |
1311 | memset(buf, 0, n); | |
1312 | buf += HDSPM_CHANNEL_BUFFER_BYTES; | |
1313 | } | |
1314 | } | |
1315 | ||
0dca1793 | 1316 | static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames) |
763f356c TI |
1317 | { |
1318 | int n; | |
1319 | ||
1320 | spin_lock_irq(&s->lock); | |
1321 | ||
2e610270 AK |
1322 | if (32 == frames) { |
1323 | /* Special case for new RME cards like RayDAT/AIO which | |
1324 | * support period sizes of 32 samples. Since latency is | |
1325 | * encoded in the three bits of HDSP_LatencyMask, we can only | |
1326 | * have values from 0 .. 7. While 0 still means 64 samples and | |
1327 | * 6 represents 4096 samples on all cards, 7 represents 8192 | |
1328 | * on older cards and 32 samples on new cards. | |
1329 | * | |
1330 | * In other words, period size in samples is calculated by | |
1331 | * 2^(n+6) with n ranging from 0 .. 7. | |
1332 | */ | |
1333 | n = 7; | |
1334 | } else { | |
1335 | frames >>= 7; | |
1336 | n = 0; | |
1337 | while (frames) { | |
1338 | n++; | |
1339 | frames >>= 1; | |
1340 | } | |
763f356c | 1341 | } |
2e610270 | 1342 | |
763f356c TI |
1343 | s->control_register &= ~HDSPM_LatencyMask; |
1344 | s->control_register |= hdspm_encode_latency(n); | |
1345 | ||
1346 | hdspm_write(s, HDSPM_controlRegister, s->control_register); | |
1347 | ||
1348 | hdspm_compute_period_size(s); | |
1349 | ||
1350 | spin_unlock_irq(&s->lock); | |
1351 | ||
1352 | return 0; | |
1353 | } | |
1354 | ||
0dca1793 AK |
1355 | static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period) |
1356 | { | |
1357 | u64 freq_const; | |
1358 | ||
1359 | if (period == 0) | |
1360 | return 0; | |
1361 | ||
1362 | switch (hdspm->io_type) { | |
1363 | case MADI: | |
1364 | case AES32: | |
1365 | freq_const = 110069313433624ULL; | |
1366 | break; | |
1367 | case RayDAT: | |
1368 | case AIO: | |
1369 | freq_const = 104857600000000ULL; | |
1370 | break; | |
1371 | case MADIface: | |
1372 | freq_const = 131072000000000ULL; | |
3d56c8e6 TI |
1373 | break; |
1374 | default: | |
1375 | snd_BUG(); | |
1376 | return 0; | |
0dca1793 AK |
1377 | } |
1378 | ||
1379 | return div_u64(freq_const, period); | |
1380 | } | |
1381 | ||
1382 | ||
ffb2c3c0 RB |
1383 | static void hdspm_set_dds_value(struct hdspm *hdspm, int rate) |
1384 | { | |
1385 | u64 n; | |
0dca1793 | 1386 | |
ffb2c3c0 RB |
1387 | if (rate >= 112000) |
1388 | rate /= 4; | |
1389 | else if (rate >= 56000) | |
1390 | rate /= 2; | |
1391 | ||
0dca1793 AK |
1392 | switch (hdspm->io_type) { |
1393 | case MADIface: | |
3d56c8e6 TI |
1394 | n = 131072000000000ULL; /* 125 MHz */ |
1395 | break; | |
0dca1793 AK |
1396 | case MADI: |
1397 | case AES32: | |
3d56c8e6 TI |
1398 | n = 110069313433624ULL; /* 105 MHz */ |
1399 | break; | |
0dca1793 AK |
1400 | case RayDAT: |
1401 | case AIO: | |
3d56c8e6 TI |
1402 | n = 104857600000000ULL; /* 100 MHz */ |
1403 | break; | |
1404 | default: | |
1405 | snd_BUG(); | |
1406 | return; | |
0dca1793 AK |
1407 | } |
1408 | ||
3f7440a6 | 1409 | n = div_u64(n, rate); |
ffb2c3c0 | 1410 | /* n should be less than 2^32 for being written to FREQ register */ |
da3cec35 | 1411 | snd_BUG_ON(n >> 32); |
ffb2c3c0 RB |
1412 | hdspm_write(hdspm, HDSPM_freqReg, (u32)n); |
1413 | } | |
763f356c TI |
1414 | |
1415 | /* dummy set rate lets see what happens */ | |
98274f07 | 1416 | static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally) |
763f356c | 1417 | { |
763f356c TI |
1418 | int current_rate; |
1419 | int rate_bits; | |
1420 | int not_set = 0; | |
6534599d | 1421 | int current_speed, target_speed; |
763f356c TI |
1422 | |
1423 | /* ASSUMPTION: hdspm->lock is either set, or there is no need for | |
1424 | it (e.g. during module initialization). | |
1425 | */ | |
1426 | ||
1427 | if (!(hdspm->control_register & HDSPM_ClockModeMaster)) { | |
1428 | ||
0dca1793 | 1429 | /* SLAVE --- */ |
763f356c TI |
1430 | if (called_internally) { |
1431 | ||
0dca1793 AK |
1432 | /* request from ctl or card initialization |
1433 | just make a warning an remember setting | |
1434 | for future master mode switching */ | |
1435 | ||
ef5fa1a4 TI |
1436 | snd_printk(KERN_WARNING "HDSPM: " |
1437 | "Warning: device is not running " | |
1438 | "as a clock master.\n"); | |
763f356c TI |
1439 | not_set = 1; |
1440 | } else { | |
1441 | ||
1442 | /* hw_param request while in AutoSync mode */ | |
1443 | int external_freq = | |
1444 | hdspm_external_sample_rate(hdspm); | |
1445 | ||
ef5fa1a4 TI |
1446 | if (hdspm_autosync_ref(hdspm) == |
1447 | HDSPM_AUTOSYNC_FROM_NONE) { | |
763f356c | 1448 | |
ef5fa1a4 TI |
1449 | snd_printk(KERN_WARNING "HDSPM: " |
1450 | "Detected no Externel Sync \n"); | |
763f356c TI |
1451 | not_set = 1; |
1452 | ||
1453 | } else if (rate != external_freq) { | |
1454 | ||
ef5fa1a4 TI |
1455 | snd_printk(KERN_WARNING "HDSPM: " |
1456 | "Warning: No AutoSync source for " | |
1457 | "requested rate\n"); | |
763f356c TI |
1458 | not_set = 1; |
1459 | } | |
1460 | } | |
1461 | } | |
1462 | ||
1463 | current_rate = hdspm->system_sample_rate; | |
1464 | ||
1465 | /* Changing between Singe, Double and Quad speed is not | |
1466 | allowed if any substreams are open. This is because such a change | |
1467 | causes a shift in the location of the DMA buffers and a reduction | |
1468 | in the number of available buffers. | |
1469 | ||
1470 | Note that a similar but essentially insoluble problem exists for | |
1471 | externally-driven rate changes. All we can do is to flag rate | |
0dca1793 | 1472 | changes in the read/write routines. |
763f356c TI |
1473 | */ |
1474 | ||
6534599d RB |
1475 | if (current_rate <= 48000) |
1476 | current_speed = HDSPM_SPEED_SINGLE; | |
1477 | else if (current_rate <= 96000) | |
1478 | current_speed = HDSPM_SPEED_DOUBLE; | |
1479 | else | |
1480 | current_speed = HDSPM_SPEED_QUAD; | |
1481 | ||
1482 | if (rate <= 48000) | |
1483 | target_speed = HDSPM_SPEED_SINGLE; | |
1484 | else if (rate <= 96000) | |
1485 | target_speed = HDSPM_SPEED_DOUBLE; | |
1486 | else | |
1487 | target_speed = HDSPM_SPEED_QUAD; | |
3cee5a60 | 1488 | |
763f356c TI |
1489 | switch (rate) { |
1490 | case 32000: | |
763f356c TI |
1491 | rate_bits = HDSPM_Frequency32KHz; |
1492 | break; | |
1493 | case 44100: | |
763f356c TI |
1494 | rate_bits = HDSPM_Frequency44_1KHz; |
1495 | break; | |
1496 | case 48000: | |
763f356c TI |
1497 | rate_bits = HDSPM_Frequency48KHz; |
1498 | break; | |
1499 | case 64000: | |
763f356c TI |
1500 | rate_bits = HDSPM_Frequency64KHz; |
1501 | break; | |
1502 | case 88200: | |
763f356c TI |
1503 | rate_bits = HDSPM_Frequency88_2KHz; |
1504 | break; | |
1505 | case 96000: | |
763f356c TI |
1506 | rate_bits = HDSPM_Frequency96KHz; |
1507 | break; | |
3cee5a60 | 1508 | case 128000: |
3cee5a60 RB |
1509 | rate_bits = HDSPM_Frequency128KHz; |
1510 | break; | |
1511 | case 176400: | |
3cee5a60 RB |
1512 | rate_bits = HDSPM_Frequency176_4KHz; |
1513 | break; | |
1514 | case 192000: | |
3cee5a60 RB |
1515 | rate_bits = HDSPM_Frequency192KHz; |
1516 | break; | |
763f356c TI |
1517 | default: |
1518 | return -EINVAL; | |
1519 | } | |
1520 | ||
6534599d | 1521 | if (current_speed != target_speed |
763f356c TI |
1522 | && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) { |
1523 | snd_printk | |
ef5fa1a4 | 1524 | (KERN_ERR "HDSPM: " |
6534599d | 1525 | "cannot change from %s speed to %s speed mode " |
ef5fa1a4 | 1526 | "(capture PID = %d, playback PID = %d)\n", |
6534599d RB |
1527 | hdspm_speed_names[current_speed], |
1528 | hdspm_speed_names[target_speed], | |
763f356c TI |
1529 | hdspm->capture_pid, hdspm->playback_pid); |
1530 | return -EBUSY; | |
1531 | } | |
1532 | ||
1533 | hdspm->control_register &= ~HDSPM_FrequencyMask; | |
1534 | hdspm->control_register |= rate_bits; | |
1535 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
1536 | ||
ffb2c3c0 RB |
1537 | /* For AES32, need to set DDS value in FREQ register |
1538 | For MADI, also apparently */ | |
1539 | hdspm_set_dds_value(hdspm, rate); | |
0dca1793 AK |
1540 | |
1541 | if (AES32 == hdspm->io_type && rate != current_rate) | |
ffb2c3c0 | 1542 | hdspm_write(hdspm, HDSPM_eeprom_wr, 0); |
763f356c TI |
1543 | |
1544 | hdspm->system_sample_rate = rate; | |
1545 | ||
0dca1793 AK |
1546 | if (rate <= 48000) { |
1547 | hdspm->channel_map_in = hdspm->channel_map_in_ss; | |
1548 | hdspm->channel_map_out = hdspm->channel_map_out_ss; | |
1549 | hdspm->max_channels_in = hdspm->ss_in_channels; | |
1550 | hdspm->max_channels_out = hdspm->ss_out_channels; | |
1551 | hdspm->port_names_in = hdspm->port_names_in_ss; | |
1552 | hdspm->port_names_out = hdspm->port_names_out_ss; | |
1553 | } else if (rate <= 96000) { | |
1554 | hdspm->channel_map_in = hdspm->channel_map_in_ds; | |
1555 | hdspm->channel_map_out = hdspm->channel_map_out_ds; | |
1556 | hdspm->max_channels_in = hdspm->ds_in_channels; | |
1557 | hdspm->max_channels_out = hdspm->ds_out_channels; | |
1558 | hdspm->port_names_in = hdspm->port_names_in_ds; | |
1559 | hdspm->port_names_out = hdspm->port_names_out_ds; | |
1560 | } else { | |
1561 | hdspm->channel_map_in = hdspm->channel_map_in_qs; | |
1562 | hdspm->channel_map_out = hdspm->channel_map_out_qs; | |
1563 | hdspm->max_channels_in = hdspm->qs_in_channels; | |
1564 | hdspm->max_channels_out = hdspm->qs_out_channels; | |
1565 | hdspm->port_names_in = hdspm->port_names_in_qs; | |
1566 | hdspm->port_names_out = hdspm->port_names_out_qs; | |
1567 | } | |
1568 | ||
763f356c TI |
1569 | if (not_set != 0) |
1570 | return -1; | |
1571 | ||
1572 | return 0; | |
1573 | } | |
1574 | ||
1575 | /* mainly for init to 0 on load */ | |
98274f07 | 1576 | static void all_in_all_mixer(struct hdspm * hdspm, int sgain) |
763f356c TI |
1577 | { |
1578 | int i, j; | |
ef5fa1a4 TI |
1579 | unsigned int gain; |
1580 | ||
1581 | if (sgain > UNITY_GAIN) | |
1582 | gain = UNITY_GAIN; | |
1583 | else if (sgain < 0) | |
1584 | gain = 0; | |
1585 | else | |
1586 | gain = sgain; | |
763f356c TI |
1587 | |
1588 | for (i = 0; i < HDSPM_MIXER_CHANNELS; i++) | |
1589 | for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) { | |
1590 | hdspm_write_in_gain(hdspm, i, j, gain); | |
1591 | hdspm_write_pb_gain(hdspm, i, j, gain); | |
1592 | } | |
1593 | } | |
1594 | ||
1595 | /*---------------------------------------------------------------------------- | |
1596 | MIDI | |
1597 | ----------------------------------------------------------------------------*/ | |
1598 | ||
ef5fa1a4 TI |
1599 | static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm, |
1600 | int id) | |
763f356c TI |
1601 | { |
1602 | /* the hardware already does the relevant bit-mask with 0xff */ | |
0dca1793 | 1603 | return hdspm_read(hdspm, hdspm->midi[id].dataIn); |
763f356c TI |
1604 | } |
1605 | ||
ef5fa1a4 TI |
1606 | static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id, |
1607 | int val) | |
763f356c TI |
1608 | { |
1609 | /* the hardware already does the relevant bit-mask with 0xff */ | |
0dca1793 | 1610 | return hdspm_write(hdspm, hdspm->midi[id].dataOut, val); |
763f356c TI |
1611 | } |
1612 | ||
98274f07 | 1613 | static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id) |
763f356c | 1614 | { |
0dca1793 | 1615 | return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF; |
763f356c TI |
1616 | } |
1617 | ||
98274f07 | 1618 | static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id) |
763f356c TI |
1619 | { |
1620 | int fifo_bytes_used; | |
1621 | ||
0dca1793 | 1622 | fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF; |
763f356c TI |
1623 | |
1624 | if (fifo_bytes_used < 128) | |
1625 | return 128 - fifo_bytes_used; | |
1626 | else | |
1627 | return 0; | |
1628 | } | |
1629 | ||
62cef821 | 1630 | static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id) |
763f356c TI |
1631 | { |
1632 | while (snd_hdspm_midi_input_available (hdspm, id)) | |
1633 | snd_hdspm_midi_read_byte (hdspm, id); | |
1634 | } | |
1635 | ||
98274f07 | 1636 | static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi) |
763f356c TI |
1637 | { |
1638 | unsigned long flags; | |
1639 | int n_pending; | |
1640 | int to_write; | |
1641 | int i; | |
1642 | unsigned char buf[128]; | |
1643 | ||
1644 | /* Output is not interrupt driven */ | |
0dca1793 | 1645 | |
763f356c | 1646 | spin_lock_irqsave (&hmidi->lock, flags); |
ef5fa1a4 TI |
1647 | if (hmidi->output && |
1648 | !snd_rawmidi_transmit_empty (hmidi->output)) { | |
1649 | n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm, | |
1650 | hmidi->id); | |
1651 | if (n_pending > 0) { | |
1652 | if (n_pending > (int)sizeof (buf)) | |
1653 | n_pending = sizeof (buf); | |
0dca1793 | 1654 | |
ef5fa1a4 TI |
1655 | to_write = snd_rawmidi_transmit (hmidi->output, buf, |
1656 | n_pending); | |
1657 | if (to_write > 0) { | |
0dca1793 | 1658 | for (i = 0; i < to_write; ++i) |
ef5fa1a4 TI |
1659 | snd_hdspm_midi_write_byte (hmidi->hdspm, |
1660 | hmidi->id, | |
1661 | buf[i]); | |
763f356c TI |
1662 | } |
1663 | } | |
1664 | } | |
1665 | spin_unlock_irqrestore (&hmidi->lock, flags); | |
1666 | return 0; | |
1667 | } | |
1668 | ||
98274f07 | 1669 | static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi) |
763f356c | 1670 | { |
ef5fa1a4 TI |
1671 | unsigned char buf[128]; /* this buffer is designed to match the MIDI |
1672 | * input FIFO size | |
1673 | */ | |
763f356c TI |
1674 | unsigned long flags; |
1675 | int n_pending; | |
1676 | int i; | |
1677 | ||
1678 | spin_lock_irqsave (&hmidi->lock, flags); | |
ef5fa1a4 TI |
1679 | n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id); |
1680 | if (n_pending > 0) { | |
763f356c | 1681 | if (hmidi->input) { |
ef5fa1a4 | 1682 | if (n_pending > (int)sizeof (buf)) |
763f356c | 1683 | n_pending = sizeof (buf); |
ef5fa1a4 TI |
1684 | for (i = 0; i < n_pending; ++i) |
1685 | buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm, | |
1686 | hmidi->id); | |
1687 | if (n_pending) | |
1688 | snd_rawmidi_receive (hmidi->input, buf, | |
1689 | n_pending); | |
763f356c TI |
1690 | } else { |
1691 | /* flush the MIDI input FIFO */ | |
ef5fa1a4 TI |
1692 | while (n_pending--) |
1693 | snd_hdspm_midi_read_byte (hmidi->hdspm, | |
1694 | hmidi->id); | |
763f356c TI |
1695 | } |
1696 | } | |
1697 | hmidi->pending = 0; | |
c0da0014 | 1698 | spin_unlock_irqrestore(&hmidi->lock, flags); |
0dca1793 | 1699 | |
c0da0014 | 1700 | spin_lock_irqsave(&hmidi->hdspm->lock, flags); |
0dca1793 | 1701 | hmidi->hdspm->control_register |= hmidi->ie; |
ef5fa1a4 TI |
1702 | hdspm_write(hmidi->hdspm, HDSPM_controlRegister, |
1703 | hmidi->hdspm->control_register); | |
c0da0014 | 1704 | spin_unlock_irqrestore(&hmidi->hdspm->lock, flags); |
0dca1793 | 1705 | |
763f356c TI |
1706 | return snd_hdspm_midi_output_write (hmidi); |
1707 | } | |
1708 | ||
ef5fa1a4 TI |
1709 | static void |
1710 | snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) | |
763f356c | 1711 | { |
98274f07 TI |
1712 | struct hdspm *hdspm; |
1713 | struct hdspm_midi *hmidi; | |
763f356c | 1714 | unsigned long flags; |
763f356c | 1715 | |
ef5fa1a4 | 1716 | hmidi = substream->rmidi->private_data; |
763f356c | 1717 | hdspm = hmidi->hdspm; |
0dca1793 | 1718 | |
763f356c TI |
1719 | spin_lock_irqsave (&hdspm->lock, flags); |
1720 | if (up) { | |
0dca1793 | 1721 | if (!(hdspm->control_register & hmidi->ie)) { |
763f356c | 1722 | snd_hdspm_flush_midi_input (hdspm, hmidi->id); |
0dca1793 | 1723 | hdspm->control_register |= hmidi->ie; |
763f356c TI |
1724 | } |
1725 | } else { | |
0dca1793 | 1726 | hdspm->control_register &= ~hmidi->ie; |
763f356c TI |
1727 | } |
1728 | ||
1729 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
1730 | spin_unlock_irqrestore (&hdspm->lock, flags); | |
1731 | } | |
1732 | ||
1733 | static void snd_hdspm_midi_output_timer(unsigned long data) | |
1734 | { | |
98274f07 | 1735 | struct hdspm_midi *hmidi = (struct hdspm_midi *) data; |
763f356c | 1736 | unsigned long flags; |
0dca1793 | 1737 | |
763f356c TI |
1738 | snd_hdspm_midi_output_write(hmidi); |
1739 | spin_lock_irqsave (&hmidi->lock, flags); | |
1740 | ||
1741 | /* this does not bump hmidi->istimer, because the | |
1742 | kernel automatically removed the timer when it | |
1743 | expired, and we are now adding it back, thus | |
0dca1793 | 1744 | leaving istimer wherever it was set before. |
763f356c TI |
1745 | */ |
1746 | ||
1747 | if (hmidi->istimer) { | |
1748 | hmidi->timer.expires = 1 + jiffies; | |
1749 | add_timer(&hmidi->timer); | |
1750 | } | |
1751 | ||
1752 | spin_unlock_irqrestore (&hmidi->lock, flags); | |
1753 | } | |
1754 | ||
ef5fa1a4 TI |
1755 | static void |
1756 | snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) | |
763f356c | 1757 | { |
98274f07 | 1758 | struct hdspm_midi *hmidi; |
763f356c TI |
1759 | unsigned long flags; |
1760 | ||
ef5fa1a4 | 1761 | hmidi = substream->rmidi->private_data; |
763f356c TI |
1762 | spin_lock_irqsave (&hmidi->lock, flags); |
1763 | if (up) { | |
1764 | if (!hmidi->istimer) { | |
1765 | init_timer(&hmidi->timer); | |
1766 | hmidi->timer.function = snd_hdspm_midi_output_timer; | |
1767 | hmidi->timer.data = (unsigned long) hmidi; | |
1768 | hmidi->timer.expires = 1 + jiffies; | |
1769 | add_timer(&hmidi->timer); | |
1770 | hmidi->istimer++; | |
1771 | } | |
1772 | } else { | |
ef5fa1a4 | 1773 | if (hmidi->istimer && --hmidi->istimer <= 0) |
763f356c | 1774 | del_timer (&hmidi->timer); |
763f356c TI |
1775 | } |
1776 | spin_unlock_irqrestore (&hmidi->lock, flags); | |
1777 | if (up) | |
1778 | snd_hdspm_midi_output_write(hmidi); | |
1779 | } | |
1780 | ||
98274f07 | 1781 | static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream) |
763f356c | 1782 | { |
98274f07 | 1783 | struct hdspm_midi *hmidi; |
763f356c | 1784 | |
ef5fa1a4 | 1785 | hmidi = substream->rmidi->private_data; |
763f356c TI |
1786 | spin_lock_irq (&hmidi->lock); |
1787 | snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id); | |
1788 | hmidi->input = substream; | |
1789 | spin_unlock_irq (&hmidi->lock); | |
1790 | ||
1791 | return 0; | |
1792 | } | |
1793 | ||
98274f07 | 1794 | static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream) |
763f356c | 1795 | { |
98274f07 | 1796 | struct hdspm_midi *hmidi; |
763f356c | 1797 | |
ef5fa1a4 | 1798 | hmidi = substream->rmidi->private_data; |
763f356c TI |
1799 | spin_lock_irq (&hmidi->lock); |
1800 | hmidi->output = substream; | |
1801 | spin_unlock_irq (&hmidi->lock); | |
1802 | ||
1803 | return 0; | |
1804 | } | |
1805 | ||
98274f07 | 1806 | static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream) |
763f356c | 1807 | { |
98274f07 | 1808 | struct hdspm_midi *hmidi; |
763f356c TI |
1809 | |
1810 | snd_hdspm_midi_input_trigger (substream, 0); | |
1811 | ||
ef5fa1a4 | 1812 | hmidi = substream->rmidi->private_data; |
763f356c TI |
1813 | spin_lock_irq (&hmidi->lock); |
1814 | hmidi->input = NULL; | |
1815 | spin_unlock_irq (&hmidi->lock); | |
1816 | ||
1817 | return 0; | |
1818 | } | |
1819 | ||
98274f07 | 1820 | static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream) |
763f356c | 1821 | { |
98274f07 | 1822 | struct hdspm_midi *hmidi; |
763f356c TI |
1823 | |
1824 | snd_hdspm_midi_output_trigger (substream, 0); | |
1825 | ||
ef5fa1a4 | 1826 | hmidi = substream->rmidi->private_data; |
763f356c TI |
1827 | spin_lock_irq (&hmidi->lock); |
1828 | hmidi->output = NULL; | |
1829 | spin_unlock_irq (&hmidi->lock); | |
1830 | ||
1831 | return 0; | |
1832 | } | |
1833 | ||
98274f07 | 1834 | static struct snd_rawmidi_ops snd_hdspm_midi_output = |
763f356c TI |
1835 | { |
1836 | .open = snd_hdspm_midi_output_open, | |
1837 | .close = snd_hdspm_midi_output_close, | |
1838 | .trigger = snd_hdspm_midi_output_trigger, | |
1839 | }; | |
1840 | ||
98274f07 | 1841 | static struct snd_rawmidi_ops snd_hdspm_midi_input = |
763f356c TI |
1842 | { |
1843 | .open = snd_hdspm_midi_input_open, | |
1844 | .close = snd_hdspm_midi_input_close, | |
1845 | .trigger = snd_hdspm_midi_input_trigger, | |
1846 | }; | |
1847 | ||
ef5fa1a4 TI |
1848 | static int __devinit snd_hdspm_create_midi (struct snd_card *card, |
1849 | struct hdspm *hdspm, int id) | |
763f356c TI |
1850 | { |
1851 | int err; | |
1852 | char buf[32]; | |
1853 | ||
1854 | hdspm->midi[id].id = id; | |
763f356c | 1855 | hdspm->midi[id].hdspm = hdspm; |
763f356c TI |
1856 | spin_lock_init (&hdspm->midi[id].lock); |
1857 | ||
0dca1793 AK |
1858 | if (0 == id) { |
1859 | if (MADIface == hdspm->io_type) { | |
1860 | /* MIDI-over-MADI on HDSPe MADIface */ | |
1861 | hdspm->midi[0].dataIn = HDSPM_midiDataIn2; | |
1862 | hdspm->midi[0].statusIn = HDSPM_midiStatusIn2; | |
1863 | hdspm->midi[0].dataOut = HDSPM_midiDataOut2; | |
1864 | hdspm->midi[0].statusOut = HDSPM_midiStatusOut2; | |
1865 | hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable; | |
1866 | hdspm->midi[0].irq = HDSPM_midi2IRQPending; | |
1867 | } else { | |
1868 | hdspm->midi[0].dataIn = HDSPM_midiDataIn0; | |
1869 | hdspm->midi[0].statusIn = HDSPM_midiStatusIn0; | |
1870 | hdspm->midi[0].dataOut = HDSPM_midiDataOut0; | |
1871 | hdspm->midi[0].statusOut = HDSPM_midiStatusOut0; | |
1872 | hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable; | |
1873 | hdspm->midi[0].irq = HDSPM_midi0IRQPending; | |
1874 | } | |
1875 | } else if (1 == id) { | |
1876 | hdspm->midi[1].dataIn = HDSPM_midiDataIn1; | |
1877 | hdspm->midi[1].statusIn = HDSPM_midiStatusIn1; | |
1878 | hdspm->midi[1].dataOut = HDSPM_midiDataOut1; | |
1879 | hdspm->midi[1].statusOut = HDSPM_midiStatusOut1; | |
1880 | hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable; | |
1881 | hdspm->midi[1].irq = HDSPM_midi1IRQPending; | |
1882 | } else if ((2 == id) && (MADI == hdspm->io_type)) { | |
1883 | /* MIDI-over-MADI on HDSPe MADI */ | |
1884 | hdspm->midi[2].dataIn = HDSPM_midiDataIn2; | |
1885 | hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; | |
1886 | hdspm->midi[2].dataOut = HDSPM_midiDataOut2; | |
1887 | hdspm->midi[2].statusOut = HDSPM_midiStatusOut2; | |
1888 | hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; | |
1889 | hdspm->midi[2].irq = HDSPM_midi2IRQPending; | |
1890 | } else if (2 == id) { | |
1891 | /* TCO MTC, read only */ | |
1892 | hdspm->midi[2].dataIn = HDSPM_midiDataIn2; | |
1893 | hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; | |
1894 | hdspm->midi[2].dataOut = -1; | |
1895 | hdspm->midi[2].statusOut = -1; | |
1896 | hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; | |
1897 | hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES; | |
1898 | } else if (3 == id) { | |
1899 | /* TCO MTC on HDSPe MADI */ | |
1900 | hdspm->midi[3].dataIn = HDSPM_midiDataIn3; | |
1901 | hdspm->midi[3].statusIn = HDSPM_midiStatusIn3; | |
1902 | hdspm->midi[3].dataOut = -1; | |
1903 | hdspm->midi[3].statusOut = -1; | |
1904 | hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable; | |
1905 | hdspm->midi[3].irq = HDSPM_midi3IRQPending; | |
1906 | } | |
1907 | ||
1908 | if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) || | |
1909 | (MADIface == hdspm->io_type)))) { | |
1910 | if ((id == 0) && (MADIface == hdspm->io_type)) { | |
1911 | sprintf(buf, "%s MIDIoverMADI", card->shortname); | |
1912 | } else if ((id == 2) && (MADI == hdspm->io_type)) { | |
1913 | sprintf(buf, "%s MIDIoverMADI", card->shortname); | |
1914 | } else { | |
1915 | sprintf(buf, "%s MIDI %d", card->shortname, id+1); | |
1916 | } | |
1917 | err = snd_rawmidi_new(card, buf, id, 1, 1, | |
1918 | &hdspm->midi[id].rmidi); | |
1919 | if (err < 0) | |
1920 | return err; | |
763f356c | 1921 | |
0dca1793 AK |
1922 | sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d", |
1923 | card->id, id+1); | |
1924 | hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; | |
1925 | ||
1926 | snd_rawmidi_set_ops(hdspm->midi[id].rmidi, | |
1927 | SNDRV_RAWMIDI_STREAM_OUTPUT, | |
1928 | &snd_hdspm_midi_output); | |
1929 | snd_rawmidi_set_ops(hdspm->midi[id].rmidi, | |
1930 | SNDRV_RAWMIDI_STREAM_INPUT, | |
1931 | &snd_hdspm_midi_input); | |
1932 | ||
1933 | hdspm->midi[id].rmidi->info_flags |= | |
1934 | SNDRV_RAWMIDI_INFO_OUTPUT | | |
1935 | SNDRV_RAWMIDI_INFO_INPUT | | |
1936 | SNDRV_RAWMIDI_INFO_DUPLEX; | |
1937 | } else { | |
1938 | /* TCO MTC, read only */ | |
1939 | sprintf(buf, "%s MTC %d", card->shortname, id+1); | |
1940 | err = snd_rawmidi_new(card, buf, id, 1, 1, | |
1941 | &hdspm->midi[id].rmidi); | |
1942 | if (err < 0) | |
1943 | return err; | |
1944 | ||
1945 | sprintf(hdspm->midi[id].rmidi->name, | |
1946 | "%s MTC %d", card->id, id+1); | |
1947 | hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; | |
763f356c | 1948 | |
0dca1793 AK |
1949 | snd_rawmidi_set_ops(hdspm->midi[id].rmidi, |
1950 | SNDRV_RAWMIDI_STREAM_INPUT, | |
1951 | &snd_hdspm_midi_input); | |
763f356c | 1952 | |
0dca1793 AK |
1953 | hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT; |
1954 | } | |
763f356c TI |
1955 | |
1956 | return 0; | |
1957 | } | |
1958 | ||
1959 | ||
1960 | static void hdspm_midi_tasklet(unsigned long arg) | |
1961 | { | |
98274f07 | 1962 | struct hdspm *hdspm = (struct hdspm *)arg; |
0dca1793 AK |
1963 | int i = 0; |
1964 | ||
1965 | while (i < hdspm->midiPorts) { | |
1966 | if (hdspm->midi[i].pending) | |
1967 | snd_hdspm_midi_input_read(&hdspm->midi[i]); | |
1968 | ||
1969 | i++; | |
1970 | } | |
1971 | } | |
763f356c TI |
1972 | |
1973 | ||
1974 | /*----------------------------------------------------------------------------- | |
1975 | Status Interface | |
1976 | ----------------------------------------------------------------------------*/ | |
1977 | ||
1978 | /* get the system sample rate which is set */ | |
1979 | ||
0dca1793 AK |
1980 | |
1981 | /** | |
1982 | * Calculate the real sample rate from the | |
1983 | * current DDS value. | |
1984 | **/ | |
1985 | static int hdspm_get_system_sample_rate(struct hdspm *hdspm) | |
1986 | { | |
1987 | unsigned int period, rate; | |
1988 | ||
1989 | period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); | |
1990 | rate = hdspm_calc_dds_value(hdspm, period); | |
1991 | ||
a97bda7d | 1992 | if (rate > 207000) { |
21a164df AK |
1993 | /* Unreasonable high sample rate as seen on PCI MADI cards. */ |
1994 | if (0 == hdspm_system_clock_mode(hdspm)) { | |
1995 | /* master mode, return internal sample rate */ | |
1996 | rate = hdspm->system_sample_rate; | |
1997 | } else { | |
1998 | /* slave mode, return external sample rate */ | |
1999 | rate = hdspm_external_sample_rate(hdspm); | |
2000 | } | |
a97bda7d AK |
2001 | } |
2002 | ||
0dca1793 AK |
2003 | return rate; |
2004 | } | |
2005 | ||
2006 | ||
763f356c | 2007 | #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \ |
f27a64f9 AK |
2008 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
2009 | .name = xname, \ | |
2010 | .index = xindex, \ | |
2011 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ | |
2012 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
2013 | .info = snd_hdspm_info_system_sample_rate, \ | |
2014 | .put = snd_hdspm_put_system_sample_rate, \ | |
2015 | .get = snd_hdspm_get_system_sample_rate \ | |
763f356c TI |
2016 | } |
2017 | ||
98274f07 TI |
2018 | static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol, |
2019 | struct snd_ctl_elem_info *uinfo) | |
763f356c TI |
2020 | { |
2021 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
2022 | uinfo->count = 1; | |
0dca1793 AK |
2023 | uinfo->value.integer.min = 27000; |
2024 | uinfo->value.integer.max = 207000; | |
2025 | uinfo->value.integer.step = 1; | |
763f356c TI |
2026 | return 0; |
2027 | } | |
2028 | ||
0dca1793 | 2029 | |
98274f07 TI |
2030 | static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol, |
2031 | struct snd_ctl_elem_value * | |
763f356c TI |
2032 | ucontrol) |
2033 | { | |
98274f07 | 2034 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c | 2035 | |
0dca1793 AK |
2036 | ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm); |
2037 | return 0; | |
2038 | } | |
2039 | ||
41285a98 AK |
2040 | static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol *kcontrol, |
2041 | struct snd_ctl_elem_value * | |
2042 | ucontrol) | |
2043 | { | |
2044 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
2045 | ||
2046 | hdspm_set_dds_value(hdspm, ucontrol->value.enumerated.item[0]); | |
2047 | return 0; | |
2048 | } | |
2049 | ||
0dca1793 AK |
2050 | |
2051 | /** | |
2052 | * Returns the WordClock sample rate class for the given card. | |
2053 | **/ | |
2054 | static int hdspm_get_wc_sample_rate(struct hdspm *hdspm) | |
2055 | { | |
2056 | int status; | |
2057 | ||
2058 | switch (hdspm->io_type) { | |
2059 | case RayDAT: | |
2060 | case AIO: | |
2061 | status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); | |
2062 | return (status >> 16) & 0xF; | |
2063 | break; | |
2064 | default: | |
2065 | break; | |
2066 | } | |
2067 | ||
2068 | ||
2069 | return 0; | |
2070 | } | |
2071 | ||
2072 | ||
2073 | /** | |
2074 | * Returns the TCO sample rate class for the given card. | |
2075 | **/ | |
2076 | static int hdspm_get_tco_sample_rate(struct hdspm *hdspm) | |
2077 | { | |
2078 | int status; | |
2079 | ||
2080 | if (hdspm->tco) { | |
2081 | switch (hdspm->io_type) { | |
2082 | case RayDAT: | |
2083 | case AIO: | |
2084 | status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); | |
2085 | return (status >> 20) & 0xF; | |
2086 | break; | |
2087 | default: | |
2088 | break; | |
2089 | } | |
2090 | } | |
2091 | ||
2092 | return 0; | |
2093 | } | |
2094 | ||
2095 | ||
2096 | /** | |
2097 | * Returns the SYNC_IN sample rate class for the given card. | |
2098 | **/ | |
2099 | static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm) | |
2100 | { | |
2101 | int status; | |
2102 | ||
2103 | if (hdspm->tco) { | |
2104 | switch (hdspm->io_type) { | |
2105 | case RayDAT: | |
2106 | case AIO: | |
2107 | status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); | |
2108 | return (status >> 12) & 0xF; | |
2109 | break; | |
2110 | default: | |
2111 | break; | |
2112 | } | |
2113 | } | |
2114 | ||
763f356c TI |
2115 | return 0; |
2116 | } | |
2117 | ||
0dca1793 AK |
2118 | |
2119 | /** | |
2120 | * Returns the sample rate class for input source <idx> for | |
2121 | * 'new style' cards like the AIO and RayDAT. | |
2122 | **/ | |
2123 | static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx) | |
2124 | { | |
2125 | int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); | |
2126 | ||
2127 | return (status >> (idx*4)) & 0xF; | |
2128 | } | |
2129 | ||
2130 | ||
2131 | ||
763f356c | 2132 | #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \ |
0dca1793 AK |
2133 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
2134 | .name = xname, \ | |
2135 | .private_value = xindex, \ | |
2136 | .access = SNDRV_CTL_ELEM_ACCESS_READ, \ | |
2137 | .info = snd_hdspm_info_autosync_sample_rate, \ | |
2138 | .get = snd_hdspm_get_autosync_sample_rate \ | |
763f356c TI |
2139 | } |
2140 | ||
0dca1793 | 2141 | |
98274f07 TI |
2142 | static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, |
2143 | struct snd_ctl_elem_info *uinfo) | |
763f356c | 2144 | { |
763f356c TI |
2145 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; |
2146 | uinfo->count = 1; | |
2147 | uinfo->value.enumerated.items = 10; | |
0dca1793 | 2148 | |
763f356c | 2149 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) |
0dca1793 | 2150 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; |
763f356c | 2151 | strcpy(uinfo->value.enumerated.name, |
0dca1793 | 2152 | texts_freq[uinfo->value.enumerated.item]); |
763f356c TI |
2153 | return 0; |
2154 | } | |
2155 | ||
0dca1793 | 2156 | |
98274f07 TI |
2157 | static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, |
2158 | struct snd_ctl_elem_value * | |
763f356c TI |
2159 | ucontrol) |
2160 | { | |
98274f07 | 2161 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c | 2162 | |
0dca1793 AK |
2163 | switch (hdspm->io_type) { |
2164 | case RayDAT: | |
2165 | switch (kcontrol->private_value) { | |
2166 | case 0: | |
2167 | ucontrol->value.enumerated.item[0] = | |
2168 | hdspm_get_wc_sample_rate(hdspm); | |
2169 | break; | |
2170 | case 7: | |
2171 | ucontrol->value.enumerated.item[0] = | |
2172 | hdspm_get_tco_sample_rate(hdspm); | |
2173 | break; | |
2174 | case 8: | |
2175 | ucontrol->value.enumerated.item[0] = | |
2176 | hdspm_get_sync_in_sample_rate(hdspm); | |
2177 | break; | |
2178 | default: | |
2179 | ucontrol->value.enumerated.item[0] = | |
2180 | hdspm_get_s1_sample_rate(hdspm, | |
2181 | kcontrol->private_value-1); | |
2182 | } | |
d681deaa | 2183 | break; |
763f356c | 2184 | |
0dca1793 AK |
2185 | case AIO: |
2186 | switch (kcontrol->private_value) { | |
2187 | case 0: /* WC */ | |
2188 | ucontrol->value.enumerated.item[0] = | |
2189 | hdspm_get_wc_sample_rate(hdspm); | |
2190 | break; | |
2191 | case 4: /* TCO */ | |
2192 | ucontrol->value.enumerated.item[0] = | |
2193 | hdspm_get_tco_sample_rate(hdspm); | |
2194 | break; | |
2195 | case 5: /* SYNC_IN */ | |
2196 | ucontrol->value.enumerated.item[0] = | |
2197 | hdspm_get_sync_in_sample_rate(hdspm); | |
2198 | break; | |
2199 | default: | |
2200 | ucontrol->value.enumerated.item[0] = | |
2201 | hdspm_get_s1_sample_rate(hdspm, | |
2202 | ucontrol->id.index-1); | |
2203 | } | |
d681deaa | 2204 | break; |
7c4a95b5 AK |
2205 | |
2206 | case AES32: | |
2207 | ||
2208 | switch (kcontrol->private_value) { | |
2209 | case 0: /* WC */ | |
2210 | ucontrol->value.enumerated.item[0] = | |
2211 | hdspm_get_wc_sample_rate(hdspm); | |
2212 | break; | |
2213 | case 9: /* TCO */ | |
2214 | ucontrol->value.enumerated.item[0] = | |
2215 | hdspm_get_tco_sample_rate(hdspm); | |
2216 | break; | |
2217 | case 10: /* SYNC_IN */ | |
2218 | ucontrol->value.enumerated.item[0] = | |
2219 | hdspm_get_sync_in_sample_rate(hdspm); | |
2220 | break; | |
2221 | default: /* AES1 to AES8 */ | |
2222 | ucontrol->value.enumerated.item[0] = | |
2223 | hdspm_get_s1_sample_rate(hdspm, | |
2224 | kcontrol->private_value-1); | |
2225 | break; | |
7c4a95b5 | 2226 | } |
d681deaa | 2227 | break; |
b8812c55 AK |
2228 | |
2229 | case MADI: | |
2230 | case MADIface: | |
2231 | { | |
2232 | int rate = hdspm_external_sample_rate(hdspm); | |
2233 | int i, selected_rate = 0; | |
2234 | for (i = 1; i < 10; i++) | |
2235 | if (HDSPM_bit2freq(i) == rate) { | |
2236 | selected_rate = i; | |
2237 | break; | |
2238 | } | |
2239 | ucontrol->value.enumerated.item[0] = selected_rate; | |
2240 | } | |
2241 | break; | |
2242 | ||
763f356c | 2243 | default: |
0dca1793 | 2244 | break; |
763f356c | 2245 | } |
763f356c | 2246 | |
0dca1793 | 2247 | return 0; |
763f356c TI |
2248 | } |
2249 | ||
2250 | ||
0dca1793 AK |
2251 | #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \ |
2252 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
2253 | .name = xname, \ | |
2254 | .index = xindex, \ | |
2255 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ | |
2256 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
2257 | .info = snd_hdspm_info_system_clock_mode, \ | |
2258 | .get = snd_hdspm_get_system_clock_mode, \ | |
2259 | .put = snd_hdspm_put_system_clock_mode, \ | |
2260 | } | |
2261 | ||
2262 | ||
2263 | /** | |
2264 | * Returns the system clock mode for the given card. | |
2265 | * @returns 0 - master, 1 - slave | |
2266 | **/ | |
2267 | static int hdspm_system_clock_mode(struct hdspm *hdspm) | |
2268 | { | |
2269 | switch (hdspm->io_type) { | |
2270 | case AIO: | |
2271 | case RayDAT: | |
2272 | if (hdspm->settings_register & HDSPM_c0Master) | |
2273 | return 0; | |
2274 | break; | |
763f356c | 2275 | |
0dca1793 AK |
2276 | default: |
2277 | if (hdspm->control_register & HDSPM_ClockModeMaster) | |
2278 | return 0; | |
2279 | } | |
763f356c | 2280 | |
763f356c TI |
2281 | return 1; |
2282 | } | |
2283 | ||
0dca1793 AK |
2284 | |
2285 | /** | |
2286 | * Sets the system clock mode. | |
2287 | * @param mode 0 - master, 1 - slave | |
2288 | **/ | |
2289 | static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode) | |
2290 | { | |
2291 | switch (hdspm->io_type) { | |
2292 | case AIO: | |
2293 | case RayDAT: | |
2294 | if (0 == mode) | |
2295 | hdspm->settings_register |= HDSPM_c0Master; | |
2296 | else | |
2297 | hdspm->settings_register &= ~HDSPM_c0Master; | |
2298 | ||
2299 | hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); | |
2300 | break; | |
2301 | ||
2302 | default: | |
2303 | if (0 == mode) | |
2304 | hdspm->control_register |= HDSPM_ClockModeMaster; | |
2305 | else | |
2306 | hdspm->control_register &= ~HDSPM_ClockModeMaster; | |
2307 | ||
2308 | hdspm_write(hdspm, HDSPM_controlRegister, | |
2309 | hdspm->control_register); | |
2310 | } | |
2311 | } | |
2312 | ||
2313 | ||
2314 | static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol, | |
98274f07 | 2315 | struct snd_ctl_elem_info *uinfo) |
763f356c | 2316 | { |
0dca1793 | 2317 | static char *texts[] = { "Master", "AutoSync" }; |
763f356c TI |
2318 | |
2319 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
2320 | uinfo->count = 1; | |
2321 | uinfo->value.enumerated.items = 2; | |
2322 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
2323 | uinfo->value.enumerated.item = | |
2324 | uinfo->value.enumerated.items - 1; | |
2325 | strcpy(uinfo->value.enumerated.name, | |
2326 | texts[uinfo->value.enumerated.item]); | |
2327 | return 0; | |
2328 | } | |
2329 | ||
98274f07 TI |
2330 | static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol, |
2331 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 2332 | { |
98274f07 | 2333 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c | 2334 | |
0dca1793 | 2335 | ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm); |
763f356c TI |
2336 | return 0; |
2337 | } | |
2338 | ||
0dca1793 AK |
2339 | static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol, |
2340 | struct snd_ctl_elem_value *ucontrol) | |
2341 | { | |
2342 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
2343 | int val; | |
2344 | ||
2345 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
2346 | return -EBUSY; | |
2347 | ||
2348 | val = ucontrol->value.enumerated.item[0]; | |
2349 | if (val < 0) | |
2350 | val = 0; | |
2351 | else if (val > 1) | |
2352 | val = 1; | |
2353 | ||
2354 | hdspm_set_system_clock_mode(hdspm, val); | |
2355 | ||
2356 | return 0; | |
2357 | } | |
2358 | ||
2359 | ||
2360 | #define HDSPM_INTERNAL_CLOCK(xname, xindex) \ | |
2361 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
2362 | .name = xname, \ | |
2363 | .index = xindex, \ | |
2364 | .info = snd_hdspm_info_clock_source, \ | |
2365 | .get = snd_hdspm_get_clock_source, \ | |
2366 | .put = snd_hdspm_put_clock_source \ | |
763f356c TI |
2367 | } |
2368 | ||
0dca1793 | 2369 | |
98274f07 | 2370 | static int hdspm_clock_source(struct hdspm * hdspm) |
763f356c | 2371 | { |
0dca1793 AK |
2372 | switch (hdspm->system_sample_rate) { |
2373 | case 32000: return 0; | |
2374 | case 44100: return 1; | |
2375 | case 48000: return 2; | |
2376 | case 64000: return 3; | |
2377 | case 88200: return 4; | |
2378 | case 96000: return 5; | |
2379 | case 128000: return 6; | |
2380 | case 176400: return 7; | |
2381 | case 192000: return 8; | |
763f356c | 2382 | } |
0dca1793 AK |
2383 | |
2384 | return -1; | |
763f356c TI |
2385 | } |
2386 | ||
98274f07 | 2387 | static int hdspm_set_clock_source(struct hdspm * hdspm, int mode) |
763f356c TI |
2388 | { |
2389 | int rate; | |
2390 | switch (mode) { | |
0dca1793 AK |
2391 | case 0: |
2392 | rate = 32000; break; | |
2393 | case 1: | |
2394 | rate = 44100; break; | |
2395 | case 2: | |
2396 | rate = 48000; break; | |
2397 | case 3: | |
2398 | rate = 64000; break; | |
2399 | case 4: | |
2400 | rate = 88200; break; | |
2401 | case 5: | |
2402 | rate = 96000; break; | |
2403 | case 6: | |
2404 | rate = 128000; break; | |
2405 | case 7: | |
2406 | rate = 176400; break; | |
2407 | case 8: | |
2408 | rate = 192000; break; | |
763f356c | 2409 | default: |
0dca1793 | 2410 | rate = 48000; |
763f356c | 2411 | } |
763f356c TI |
2412 | hdspm_set_rate(hdspm, rate, 1); |
2413 | return 0; | |
2414 | } | |
2415 | ||
98274f07 TI |
2416 | static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol, |
2417 | struct snd_ctl_elem_info *uinfo) | |
763f356c | 2418 | { |
763f356c TI |
2419 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; |
2420 | uinfo->count = 1; | |
0dca1793 | 2421 | uinfo->value.enumerated.items = 9; |
763f356c TI |
2422 | |
2423 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
2424 | uinfo->value.enumerated.item = | |
2425 | uinfo->value.enumerated.items - 1; | |
2426 | ||
2427 | strcpy(uinfo->value.enumerated.name, | |
0dca1793 | 2428 | texts_freq[uinfo->value.enumerated.item+1]); |
763f356c TI |
2429 | |
2430 | return 0; | |
2431 | } | |
2432 | ||
98274f07 TI |
2433 | static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol, |
2434 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 2435 | { |
98274f07 | 2436 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
2437 | |
2438 | ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm); | |
2439 | return 0; | |
2440 | } | |
2441 | ||
98274f07 TI |
2442 | static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol, |
2443 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 2444 | { |
98274f07 | 2445 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
2446 | int change; |
2447 | int val; | |
2448 | ||
2449 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
2450 | return -EBUSY; | |
2451 | val = ucontrol->value.enumerated.item[0]; | |
2452 | if (val < 0) | |
2453 | val = 0; | |
6534599d RB |
2454 | if (val > 9) |
2455 | val = 9; | |
763f356c TI |
2456 | spin_lock_irq(&hdspm->lock); |
2457 | if (val != hdspm_clock_source(hdspm)) | |
2458 | change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0; | |
2459 | else | |
2460 | change = 0; | |
2461 | spin_unlock_irq(&hdspm->lock); | |
2462 | return change; | |
2463 | } | |
2464 | ||
763f356c | 2465 | |
0dca1793 | 2466 | #define HDSPM_PREF_SYNC_REF(xname, xindex) \ |
f27a64f9 | 2467 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
0dca1793 AK |
2468 | .name = xname, \ |
2469 | .index = xindex, \ | |
2470 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ | |
2471 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
2472 | .info = snd_hdspm_info_pref_sync_ref, \ | |
2473 | .get = snd_hdspm_get_pref_sync_ref, \ | |
2474 | .put = snd_hdspm_put_pref_sync_ref \ | |
2475 | } | |
2476 | ||
2477 | ||
2478 | /** | |
2479 | * Returns the current preferred sync reference setting. | |
2480 | * The semantics of the return value are depending on the | |
2481 | * card, please see the comments for clarification. | |
2482 | **/ | |
98274f07 | 2483 | static int hdspm_pref_sync_ref(struct hdspm * hdspm) |
763f356c | 2484 | { |
0dca1793 AK |
2485 | switch (hdspm->io_type) { |
2486 | case AES32: | |
3cee5a60 | 2487 | switch (hdspm->control_register & HDSPM_SyncRefMask) { |
0dca1793 AK |
2488 | case 0: return 0; /* WC */ |
2489 | case HDSPM_SyncRef0: return 1; /* AES 1 */ | |
2490 | case HDSPM_SyncRef1: return 2; /* AES 2 */ | |
2491 | case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */ | |
2492 | case HDSPM_SyncRef2: return 4; /* AES 4 */ | |
2493 | case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */ | |
2494 | case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */ | |
2495 | case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0: | |
2496 | return 7; /* AES 7 */ | |
2497 | case HDSPM_SyncRef3: return 8; /* AES 8 */ | |
2498 | case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */ | |
3cee5a60 | 2499 | } |
0dca1793 AK |
2500 | break; |
2501 | ||
2502 | case MADI: | |
2503 | case MADIface: | |
2504 | if (hdspm->tco) { | |
2505 | switch (hdspm->control_register & HDSPM_SyncRefMask) { | |
2506 | case 0: return 0; /* WC */ | |
2507 | case HDSPM_SyncRef0: return 1; /* MADI */ | |
2508 | case HDSPM_SyncRef1: return 2; /* TCO */ | |
2509 | case HDSPM_SyncRef1+HDSPM_SyncRef0: | |
2510 | return 3; /* SYNC_IN */ | |
2511 | } | |
2512 | } else { | |
2513 | switch (hdspm->control_register & HDSPM_SyncRefMask) { | |
2514 | case 0: return 0; /* WC */ | |
2515 | case HDSPM_SyncRef0: return 1; /* MADI */ | |
2516 | case HDSPM_SyncRef1+HDSPM_SyncRef0: | |
2517 | return 2; /* SYNC_IN */ | |
2518 | } | |
2519 | } | |
2520 | break; | |
2521 | ||
2522 | case RayDAT: | |
2523 | if (hdspm->tco) { | |
2524 | switch ((hdspm->settings_register & | |
2525 | HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { | |
2526 | case 0: return 0; /* WC */ | |
2527 | case 3: return 1; /* ADAT 1 */ | |
2528 | case 4: return 2; /* ADAT 2 */ | |
2529 | case 5: return 3; /* ADAT 3 */ | |
2530 | case 6: return 4; /* ADAT 4 */ | |
2531 | case 1: return 5; /* AES */ | |
2532 | case 2: return 6; /* SPDIF */ | |
2533 | case 9: return 7; /* TCO */ | |
2534 | case 10: return 8; /* SYNC_IN */ | |
2535 | } | |
2536 | } else { | |
2537 | switch ((hdspm->settings_register & | |
2538 | HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { | |
2539 | case 0: return 0; /* WC */ | |
2540 | case 3: return 1; /* ADAT 1 */ | |
2541 | case 4: return 2; /* ADAT 2 */ | |
2542 | case 5: return 3; /* ADAT 3 */ | |
2543 | case 6: return 4; /* ADAT 4 */ | |
2544 | case 1: return 5; /* AES */ | |
2545 | case 2: return 6; /* SPDIF */ | |
2546 | case 10: return 7; /* SYNC_IN */ | |
2547 | } | |
3cee5a60 | 2548 | } |
0dca1793 AK |
2549 | |
2550 | break; | |
2551 | ||
2552 | case AIO: | |
2553 | if (hdspm->tco) { | |
2554 | switch ((hdspm->settings_register & | |
2555 | HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { | |
2556 | case 0: return 0; /* WC */ | |
2557 | case 3: return 1; /* ADAT */ | |
2558 | case 1: return 2; /* AES */ | |
2559 | case 2: return 3; /* SPDIF */ | |
2560 | case 9: return 4; /* TCO */ | |
2561 | case 10: return 5; /* SYNC_IN */ | |
2562 | } | |
2563 | } else { | |
2564 | switch ((hdspm->settings_register & | |
2565 | HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { | |
2566 | case 0: return 0; /* WC */ | |
2567 | case 3: return 1; /* ADAT */ | |
2568 | case 1: return 2; /* AES */ | |
2569 | case 2: return 3; /* SPDIF */ | |
2570 | case 10: return 4; /* SYNC_IN */ | |
2571 | } | |
2572 | } | |
2573 | ||
2574 | break; | |
763f356c TI |
2575 | } |
2576 | ||
0dca1793 | 2577 | return -1; |
763f356c TI |
2578 | } |
2579 | ||
0dca1793 AK |
2580 | |
2581 | /** | |
2582 | * Set the preferred sync reference to <pref>. The semantics | |
2583 | * of <pref> are depending on the card type, see the comments | |
2584 | * for clarification. | |
2585 | **/ | |
98274f07 | 2586 | static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref) |
763f356c | 2587 | { |
0dca1793 | 2588 | int p = 0; |
763f356c | 2589 | |
0dca1793 AK |
2590 | switch (hdspm->io_type) { |
2591 | case AES32: | |
2592 | hdspm->control_register &= ~HDSPM_SyncRefMask; | |
3cee5a60 | 2593 | switch (pref) { |
0dca1793 AK |
2594 | case 0: /* WC */ |
2595 | break; | |
2596 | case 1: /* AES 1 */ | |
2597 | hdspm->control_register |= HDSPM_SyncRef0; | |
2598 | break; | |
2599 | case 2: /* AES 2 */ | |
2600 | hdspm->control_register |= HDSPM_SyncRef1; | |
2601 | break; | |
2602 | case 3: /* AES 3 */ | |
2603 | hdspm->control_register |= | |
2604 | HDSPM_SyncRef1+HDSPM_SyncRef0; | |
2605 | break; | |
2606 | case 4: /* AES 4 */ | |
2607 | hdspm->control_register |= HDSPM_SyncRef2; | |
2608 | break; | |
2609 | case 5: /* AES 5 */ | |
2610 | hdspm->control_register |= | |
2611 | HDSPM_SyncRef2+HDSPM_SyncRef0; | |
2612 | break; | |
2613 | case 6: /* AES 6 */ | |
2614 | hdspm->control_register |= | |
2615 | HDSPM_SyncRef2+HDSPM_SyncRef1; | |
2616 | break; | |
2617 | case 7: /* AES 7 */ | |
2618 | hdspm->control_register |= | |
2619 | HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0; | |
3cee5a60 | 2620 | break; |
0dca1793 AK |
2621 | case 8: /* AES 8 */ |
2622 | hdspm->control_register |= HDSPM_SyncRef3; | |
2623 | break; | |
2624 | case 9: /* TCO */ | |
2625 | hdspm->control_register |= | |
2626 | HDSPM_SyncRef3+HDSPM_SyncRef0; | |
3cee5a60 RB |
2627 | break; |
2628 | default: | |
2629 | return -1; | |
2630 | } | |
0dca1793 AK |
2631 | |
2632 | break; | |
2633 | ||
2634 | case MADI: | |
2635 | case MADIface: | |
2636 | hdspm->control_register &= ~HDSPM_SyncRefMask; | |
2637 | if (hdspm->tco) { | |
2638 | switch (pref) { | |
2639 | case 0: /* WC */ | |
2640 | break; | |
2641 | case 1: /* MADI */ | |
2642 | hdspm->control_register |= HDSPM_SyncRef0; | |
2643 | break; | |
2644 | case 2: /* TCO */ | |
2645 | hdspm->control_register |= HDSPM_SyncRef1; | |
2646 | break; | |
2647 | case 3: /* SYNC_IN */ | |
2648 | hdspm->control_register |= | |
2649 | HDSPM_SyncRef0+HDSPM_SyncRef1; | |
2650 | break; | |
2651 | default: | |
2652 | return -1; | |
2653 | } | |
2654 | } else { | |
2655 | switch (pref) { | |
2656 | case 0: /* WC */ | |
2657 | break; | |
2658 | case 1: /* MADI */ | |
2659 | hdspm->control_register |= HDSPM_SyncRef0; | |
2660 | break; | |
2661 | case 2: /* SYNC_IN */ | |
2662 | hdspm->control_register |= | |
2663 | HDSPM_SyncRef0+HDSPM_SyncRef1; | |
2664 | break; | |
2665 | default: | |
2666 | return -1; | |
2667 | } | |
2668 | } | |
2669 | ||
2670 | break; | |
2671 | ||
2672 | case RayDAT: | |
2673 | if (hdspm->tco) { | |
2674 | switch (pref) { | |
2675 | case 0: p = 0; break; /* WC */ | |
2676 | case 1: p = 3; break; /* ADAT 1 */ | |
2677 | case 2: p = 4; break; /* ADAT 2 */ | |
2678 | case 3: p = 5; break; /* ADAT 3 */ | |
2679 | case 4: p = 6; break; /* ADAT 4 */ | |
2680 | case 5: p = 1; break; /* AES */ | |
2681 | case 6: p = 2; break; /* SPDIF */ | |
2682 | case 7: p = 9; break; /* TCO */ | |
2683 | case 8: p = 10; break; /* SYNC_IN */ | |
2684 | default: return -1; | |
2685 | } | |
2686 | } else { | |
2687 | switch (pref) { | |
2688 | case 0: p = 0; break; /* WC */ | |
2689 | case 1: p = 3; break; /* ADAT 1 */ | |
2690 | case 2: p = 4; break; /* ADAT 2 */ | |
2691 | case 3: p = 5; break; /* ADAT 3 */ | |
2692 | case 4: p = 6; break; /* ADAT 4 */ | |
2693 | case 5: p = 1; break; /* AES */ | |
2694 | case 6: p = 2; break; /* SPDIF */ | |
2695 | case 7: p = 10; break; /* SYNC_IN */ | |
2696 | default: return -1; | |
2697 | } | |
2698 | } | |
2699 | break; | |
2700 | ||
2701 | case AIO: | |
2702 | if (hdspm->tco) { | |
2703 | switch (pref) { | |
2704 | case 0: p = 0; break; /* WC */ | |
2705 | case 1: p = 3; break; /* ADAT */ | |
2706 | case 2: p = 1; break; /* AES */ | |
2707 | case 3: p = 2; break; /* SPDIF */ | |
2708 | case 4: p = 9; break; /* TCO */ | |
2709 | case 5: p = 10; break; /* SYNC_IN */ | |
2710 | default: return -1; | |
2711 | } | |
2712 | } else { | |
2713 | switch (pref) { | |
2714 | case 0: p = 0; break; /* WC */ | |
2715 | case 1: p = 3; break; /* ADAT */ | |
2716 | case 2: p = 1; break; /* AES */ | |
2717 | case 3: p = 2; break; /* SPDIF */ | |
2718 | case 4: p = 10; break; /* SYNC_IN */ | |
2719 | default: return -1; | |
2720 | } | |
2721 | } | |
2722 | break; | |
763f356c | 2723 | } |
0dca1793 AK |
2724 | |
2725 | switch (hdspm->io_type) { | |
2726 | case RayDAT: | |
2727 | case AIO: | |
2728 | hdspm->settings_register &= ~HDSPM_c0_SyncRefMask; | |
2729 | hdspm->settings_register |= HDSPM_c0_SyncRef0 * p; | |
2730 | hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); | |
2731 | break; | |
2732 | ||
2733 | case MADI: | |
2734 | case MADIface: | |
2735 | case AES32: | |
2736 | hdspm_write(hdspm, HDSPM_controlRegister, | |
2737 | hdspm->control_register); | |
2738 | } | |
2739 | ||
763f356c TI |
2740 | return 0; |
2741 | } | |
2742 | ||
0dca1793 | 2743 | |
98274f07 TI |
2744 | static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol, |
2745 | struct snd_ctl_elem_info *uinfo) | |
763f356c | 2746 | { |
3cee5a60 | 2747 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c | 2748 | |
0dca1793 AK |
2749 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; |
2750 | uinfo->count = 1; | |
2751 | uinfo->value.enumerated.items = hdspm->texts_autosync_items; | |
3cee5a60 | 2752 | |
0dca1793 AK |
2753 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) |
2754 | uinfo->value.enumerated.item = | |
2755 | uinfo->value.enumerated.items - 1; | |
3cee5a60 | 2756 | |
0dca1793 AK |
2757 | strcpy(uinfo->value.enumerated.name, |
2758 | hdspm->texts_autosync[uinfo->value.enumerated.item]); | |
3cee5a60 | 2759 | |
763f356c TI |
2760 | return 0; |
2761 | } | |
2762 | ||
98274f07 TI |
2763 | static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol, |
2764 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 2765 | { |
98274f07 | 2766 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
0dca1793 | 2767 | int psf = hdspm_pref_sync_ref(hdspm); |
763f356c | 2768 | |
0dca1793 AK |
2769 | if (psf >= 0) { |
2770 | ucontrol->value.enumerated.item[0] = psf; | |
2771 | return 0; | |
2772 | } | |
2773 | ||
2774 | return -1; | |
763f356c TI |
2775 | } |
2776 | ||
98274f07 TI |
2777 | static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol, |
2778 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 2779 | { |
98274f07 | 2780 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
0dca1793 | 2781 | int val, change = 0; |
763f356c TI |
2782 | |
2783 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
2784 | return -EBUSY; | |
2785 | ||
0dca1793 AK |
2786 | val = ucontrol->value.enumerated.item[0]; |
2787 | ||
2788 | if (val < 0) | |
2789 | val = 0; | |
2790 | else if (val >= hdspm->texts_autosync_items) | |
2791 | val = hdspm->texts_autosync_items-1; | |
763f356c TI |
2792 | |
2793 | spin_lock_irq(&hdspm->lock); | |
0dca1793 AK |
2794 | if (val != hdspm_pref_sync_ref(hdspm)) |
2795 | change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0; | |
2796 | ||
763f356c TI |
2797 | spin_unlock_irq(&hdspm->lock); |
2798 | return change; | |
2799 | } | |
2800 | ||
0dca1793 | 2801 | |
763f356c | 2802 | #define HDSPM_AUTOSYNC_REF(xname, xindex) \ |
f27a64f9 AK |
2803 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
2804 | .name = xname, \ | |
2805 | .index = xindex, \ | |
2806 | .access = SNDRV_CTL_ELEM_ACCESS_READ, \ | |
2807 | .info = snd_hdspm_info_autosync_ref, \ | |
2808 | .get = snd_hdspm_get_autosync_ref, \ | |
763f356c TI |
2809 | } |
2810 | ||
0dca1793 | 2811 | static int hdspm_autosync_ref(struct hdspm *hdspm) |
763f356c | 2812 | { |
0dca1793 | 2813 | if (AES32 == hdspm->io_type) { |
3cee5a60 | 2814 | unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister); |
0dca1793 AK |
2815 | unsigned int syncref = |
2816 | (status >> HDSPM_AES32_syncref_bit) & 0xF; | |
3cee5a60 RB |
2817 | if (syncref == 0) |
2818 | return HDSPM_AES32_AUTOSYNC_FROM_WORD; | |
2819 | if (syncref <= 8) | |
2820 | return syncref; | |
2821 | return HDSPM_AES32_AUTOSYNC_FROM_NONE; | |
0dca1793 | 2822 | } else if (MADI == hdspm->io_type) { |
3cee5a60 RB |
2823 | /* This looks at the autosync selected sync reference */ |
2824 | unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2); | |
2825 | ||
2826 | switch (status2 & HDSPM_SelSyncRefMask) { | |
2827 | case HDSPM_SelSyncRef_WORD: | |
2828 | return HDSPM_AUTOSYNC_FROM_WORD; | |
2829 | case HDSPM_SelSyncRef_MADI: | |
2830 | return HDSPM_AUTOSYNC_FROM_MADI; | |
0dca1793 AK |
2831 | case HDSPM_SelSyncRef_TCO: |
2832 | return HDSPM_AUTOSYNC_FROM_TCO; | |
2833 | case HDSPM_SelSyncRef_SyncIn: | |
2834 | return HDSPM_AUTOSYNC_FROM_SYNC_IN; | |
3cee5a60 RB |
2835 | case HDSPM_SelSyncRef_NVALID: |
2836 | return HDSPM_AUTOSYNC_FROM_NONE; | |
2837 | default: | |
2838 | return 0; | |
2839 | } | |
763f356c | 2840 | |
763f356c | 2841 | } |
0dca1793 | 2842 | return 0; |
763f356c TI |
2843 | } |
2844 | ||
0dca1793 | 2845 | |
98274f07 TI |
2846 | static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol, |
2847 | struct snd_ctl_elem_info *uinfo) | |
763f356c | 2848 | { |
3cee5a60 | 2849 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c | 2850 | |
0dca1793 | 2851 | if (AES32 == hdspm->io_type) { |
3cee5a60 RB |
2852 | static char *texts[] = { "WordClock", "AES1", "AES2", "AES3", |
2853 | "AES4", "AES5", "AES6", "AES7", "AES8", "None"}; | |
2854 | ||
2855 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
2856 | uinfo->count = 1; | |
2857 | uinfo->value.enumerated.items = 10; | |
ef5fa1a4 TI |
2858 | if (uinfo->value.enumerated.item >= |
2859 | uinfo->value.enumerated.items) | |
3cee5a60 RB |
2860 | uinfo->value.enumerated.item = |
2861 | uinfo->value.enumerated.items - 1; | |
2862 | strcpy(uinfo->value.enumerated.name, | |
2863 | texts[uinfo->value.enumerated.item]); | |
0dca1793 AK |
2864 | } else if (MADI == hdspm->io_type) { |
2865 | static char *texts[] = {"Word Clock", "MADI", "TCO", | |
2866 | "Sync In", "None" }; | |
3cee5a60 RB |
2867 | |
2868 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
2869 | uinfo->count = 1; | |
0dca1793 | 2870 | uinfo->value.enumerated.items = 5; |
ef5fa1a4 | 2871 | if (uinfo->value.enumerated.item >= |
0dca1793 | 2872 | uinfo->value.enumerated.items) |
3cee5a60 RB |
2873 | uinfo->value.enumerated.item = |
2874 | uinfo->value.enumerated.items - 1; | |
2875 | strcpy(uinfo->value.enumerated.name, | |
2876 | texts[uinfo->value.enumerated.item]); | |
2877 | } | |
763f356c TI |
2878 | return 0; |
2879 | } | |
2880 | ||
98274f07 TI |
2881 | static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol, |
2882 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 2883 | { |
98274f07 | 2884 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c | 2885 | |
6534599d | 2886 | ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm); |
763f356c TI |
2887 | return 0; |
2888 | } | |
2889 | ||
bf0ff87b AK |
2890 | #define HDSPM_TOGGLE_SETTING(xname, xindex) \ |
2891 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
2892 | .name = xname, \ | |
2893 | .private_value = xindex, \ | |
2894 | .info = snd_hdspm_info_toggle_setting, \ | |
2895 | .get = snd_hdspm_get_toggle_setting, \ | |
2896 | .put = snd_hdspm_put_toggle_setting \ | |
2897 | } | |
2898 | ||
2899 | static int hdspm_toggle_setting(struct hdspm *hdspm, u32 regmask) | |
2900 | { | |
2901 | return (hdspm->control_register & regmask) ? 1 : 0; | |
2902 | } | |
2903 | ||
2904 | static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out) | |
2905 | { | |
2906 | if (out) | |
2907 | hdspm->control_register |= regmask; | |
2908 | else | |
2909 | hdspm->control_register &= ~regmask; | |
2910 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
2911 | ||
2912 | return 0; | |
2913 | } | |
2914 | ||
2915 | #define snd_hdspm_info_toggle_setting snd_ctl_boolean_mono_info | |
2916 | ||
2917 | static int snd_hdspm_get_toggle_setting(struct snd_kcontrol *kcontrol, | |
2918 | struct snd_ctl_elem_value *ucontrol) | |
2919 | { | |
2920 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
2921 | u32 regmask = kcontrol->private_value; | |
2922 | ||
2923 | spin_lock_irq(&hdspm->lock); | |
2924 | ucontrol->value.integer.value[0] = hdspm_toggle_setting(hdspm, regmask); | |
2925 | spin_unlock_irq(&hdspm->lock); | |
2926 | return 0; | |
2927 | } | |
2928 | ||
2929 | static int snd_hdspm_put_toggle_setting(struct snd_kcontrol *kcontrol, | |
2930 | struct snd_ctl_elem_value *ucontrol) | |
2931 | { | |
2932 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
2933 | u32 regmask = kcontrol->private_value; | |
2934 | int change; | |
2935 | unsigned int val; | |
2936 | ||
2937 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
2938 | return -EBUSY; | |
2939 | val = ucontrol->value.integer.value[0] & 1; | |
2940 | spin_lock_irq(&hdspm->lock); | |
2941 | change = (int) val != hdspm_toggle_setting(hdspm, regmask); | |
2942 | hdspm_set_toggle_setting(hdspm, regmask, val); | |
2943 | spin_unlock_irq(&hdspm->lock); | |
2944 | return change; | |
2945 | } | |
2946 | ||
0dca1793 | 2947 | |
763f356c | 2948 | #define HDSPM_LINE_OUT(xname, xindex) \ |
f27a64f9 AK |
2949 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
2950 | .name = xname, \ | |
2951 | .index = xindex, \ | |
2952 | .info = snd_hdspm_info_line_out, \ | |
2953 | .get = snd_hdspm_get_line_out, \ | |
2954 | .put = snd_hdspm_put_line_out \ | |
763f356c TI |
2955 | } |
2956 | ||
98274f07 | 2957 | static int hdspm_line_out(struct hdspm * hdspm) |
763f356c TI |
2958 | { |
2959 | return (hdspm->control_register & HDSPM_LineOut) ? 1 : 0; | |
2960 | } | |
2961 | ||
2962 | ||
98274f07 | 2963 | static int hdspm_set_line_output(struct hdspm * hdspm, int out) |
763f356c TI |
2964 | { |
2965 | if (out) | |
2966 | hdspm->control_register |= HDSPM_LineOut; | |
2967 | else | |
2968 | hdspm->control_register &= ~HDSPM_LineOut; | |
2969 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
2970 | ||
2971 | return 0; | |
2972 | } | |
2973 | ||
a5ce8890 | 2974 | #define snd_hdspm_info_line_out snd_ctl_boolean_mono_info |
763f356c | 2975 | |
98274f07 TI |
2976 | static int snd_hdspm_get_line_out(struct snd_kcontrol *kcontrol, |
2977 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 2978 | { |
98274f07 | 2979 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
2980 | |
2981 | spin_lock_irq(&hdspm->lock); | |
2982 | ucontrol->value.integer.value[0] = hdspm_line_out(hdspm); | |
2983 | spin_unlock_irq(&hdspm->lock); | |
2984 | return 0; | |
2985 | } | |
2986 | ||
98274f07 TI |
2987 | static int snd_hdspm_put_line_out(struct snd_kcontrol *kcontrol, |
2988 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 2989 | { |
98274f07 | 2990 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
2991 | int change; |
2992 | unsigned int val; | |
2993 | ||
2994 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
2995 | return -EBUSY; | |
2996 | val = ucontrol->value.integer.value[0] & 1; | |
2997 | spin_lock_irq(&hdspm->lock); | |
2998 | change = (int) val != hdspm_line_out(hdspm); | |
2999 | hdspm_set_line_output(hdspm, val); | |
3000 | spin_unlock_irq(&hdspm->lock); | |
3001 | return change; | |
3002 | } | |
3003 | ||
0dca1793 | 3004 | |
763f356c | 3005 | #define HDSPM_TX_64(xname, xindex) \ |
f27a64f9 AK |
3006 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
3007 | .name = xname, \ | |
3008 | .index = xindex, \ | |
3009 | .info = snd_hdspm_info_tx_64, \ | |
3010 | .get = snd_hdspm_get_tx_64, \ | |
3011 | .put = snd_hdspm_put_tx_64 \ | |
763f356c TI |
3012 | } |
3013 | ||
98274f07 | 3014 | static int hdspm_tx_64(struct hdspm * hdspm) |
763f356c TI |
3015 | { |
3016 | return (hdspm->control_register & HDSPM_TX_64ch) ? 1 : 0; | |
3017 | } | |
3018 | ||
98274f07 | 3019 | static int hdspm_set_tx_64(struct hdspm * hdspm, int out) |
763f356c TI |
3020 | { |
3021 | if (out) | |
3022 | hdspm->control_register |= HDSPM_TX_64ch; | |
3023 | else | |
3024 | hdspm->control_register &= ~HDSPM_TX_64ch; | |
3025 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
3026 | ||
3027 | return 0; | |
3028 | } | |
3029 | ||
a5ce8890 | 3030 | #define snd_hdspm_info_tx_64 snd_ctl_boolean_mono_info |
763f356c | 3031 | |
98274f07 TI |
3032 | static int snd_hdspm_get_tx_64(struct snd_kcontrol *kcontrol, |
3033 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 3034 | { |
98274f07 | 3035 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
3036 | |
3037 | spin_lock_irq(&hdspm->lock); | |
3038 | ucontrol->value.integer.value[0] = hdspm_tx_64(hdspm); | |
3039 | spin_unlock_irq(&hdspm->lock); | |
3040 | return 0; | |
3041 | } | |
3042 | ||
98274f07 TI |
3043 | static int snd_hdspm_put_tx_64(struct snd_kcontrol *kcontrol, |
3044 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 3045 | { |
98274f07 | 3046 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
3047 | int change; |
3048 | unsigned int val; | |
3049 | ||
3050 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
3051 | return -EBUSY; | |
3052 | val = ucontrol->value.integer.value[0] & 1; | |
3053 | spin_lock_irq(&hdspm->lock); | |
3054 | change = (int) val != hdspm_tx_64(hdspm); | |
3055 | hdspm_set_tx_64(hdspm, val); | |
3056 | spin_unlock_irq(&hdspm->lock); | |
3057 | return change; | |
3058 | } | |
3059 | ||
0dca1793 | 3060 | |
763f356c | 3061 | #define HDSPM_C_TMS(xname, xindex) \ |
f27a64f9 AK |
3062 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
3063 | .name = xname, \ | |
3064 | .index = xindex, \ | |
3065 | .info = snd_hdspm_info_c_tms, \ | |
3066 | .get = snd_hdspm_get_c_tms, \ | |
3067 | .put = snd_hdspm_put_c_tms \ | |
763f356c TI |
3068 | } |
3069 | ||
98274f07 | 3070 | static int hdspm_c_tms(struct hdspm * hdspm) |
763f356c TI |
3071 | { |
3072 | return (hdspm->control_register & HDSPM_clr_tms) ? 1 : 0; | |
3073 | } | |
3074 | ||
98274f07 | 3075 | static int hdspm_set_c_tms(struct hdspm * hdspm, int out) |
763f356c TI |
3076 | { |
3077 | if (out) | |
3078 | hdspm->control_register |= HDSPM_clr_tms; | |
3079 | else | |
3080 | hdspm->control_register &= ~HDSPM_clr_tms; | |
3081 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
3082 | ||
3083 | return 0; | |
3084 | } | |
3085 | ||
a5ce8890 | 3086 | #define snd_hdspm_info_c_tms snd_ctl_boolean_mono_info |
763f356c | 3087 | |
98274f07 TI |
3088 | static int snd_hdspm_get_c_tms(struct snd_kcontrol *kcontrol, |
3089 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 3090 | { |
98274f07 | 3091 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
3092 | |
3093 | spin_lock_irq(&hdspm->lock); | |
3094 | ucontrol->value.integer.value[0] = hdspm_c_tms(hdspm); | |
3095 | spin_unlock_irq(&hdspm->lock); | |
3096 | return 0; | |
3097 | } | |
3098 | ||
98274f07 TI |
3099 | static int snd_hdspm_put_c_tms(struct snd_kcontrol *kcontrol, |
3100 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 3101 | { |
98274f07 | 3102 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
3103 | int change; |
3104 | unsigned int val; | |
3105 | ||
3106 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
3107 | return -EBUSY; | |
3108 | val = ucontrol->value.integer.value[0] & 1; | |
3109 | spin_lock_irq(&hdspm->lock); | |
3110 | change = (int) val != hdspm_c_tms(hdspm); | |
3111 | hdspm_set_c_tms(hdspm, val); | |
3112 | spin_unlock_irq(&hdspm->lock); | |
3113 | return change; | |
3114 | } | |
3115 | ||
0dca1793 | 3116 | |
763f356c | 3117 | #define HDSPM_SAFE_MODE(xname, xindex) \ |
f27a64f9 AK |
3118 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
3119 | .name = xname, \ | |
3120 | .index = xindex, \ | |
3121 | .info = snd_hdspm_info_safe_mode, \ | |
3122 | .get = snd_hdspm_get_safe_mode, \ | |
3123 | .put = snd_hdspm_put_safe_mode \ | |
763f356c TI |
3124 | } |
3125 | ||
3cee5a60 RB |
3126 | static int hdspm_safe_mode(struct hdspm * hdspm) |
3127 | { | |
3128 | return (hdspm->control_register & HDSPM_AutoInp) ? 1 : 0; | |
3129 | } | |
3130 | ||
3131 | static int hdspm_set_safe_mode(struct hdspm * hdspm, int out) | |
3132 | { | |
3133 | if (out) | |
3134 | hdspm->control_register |= HDSPM_AutoInp; | |
3135 | else | |
3136 | hdspm->control_register &= ~HDSPM_AutoInp; | |
3137 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
3138 | ||
3139 | return 0; | |
3140 | } | |
3141 | ||
a5ce8890 | 3142 | #define snd_hdspm_info_safe_mode snd_ctl_boolean_mono_info |
3cee5a60 RB |
3143 | |
3144 | static int snd_hdspm_get_safe_mode(struct snd_kcontrol *kcontrol, | |
3145 | struct snd_ctl_elem_value *ucontrol) | |
3146 | { | |
3147 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
3148 | ||
3149 | spin_lock_irq(&hdspm->lock); | |
3150 | ucontrol->value.integer.value[0] = hdspm_safe_mode(hdspm); | |
3151 | spin_unlock_irq(&hdspm->lock); | |
3152 | return 0; | |
3153 | } | |
3154 | ||
3155 | static int snd_hdspm_put_safe_mode(struct snd_kcontrol *kcontrol, | |
3156 | struct snd_ctl_elem_value *ucontrol) | |
3157 | { | |
3158 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
3159 | int change; | |
3160 | unsigned int val; | |
3161 | ||
3162 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
3163 | return -EBUSY; | |
3164 | val = ucontrol->value.integer.value[0] & 1; | |
3165 | spin_lock_irq(&hdspm->lock); | |
3166 | change = (int) val != hdspm_safe_mode(hdspm); | |
3167 | hdspm_set_safe_mode(hdspm, val); | |
3168 | spin_unlock_irq(&hdspm->lock); | |
3169 | return change; | |
3170 | } | |
3171 | ||
0dca1793 | 3172 | |
3cee5a60 | 3173 | #define HDSPM_EMPHASIS(xname, xindex) \ |
f27a64f9 AK |
3174 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
3175 | .name = xname, \ | |
3176 | .index = xindex, \ | |
3177 | .info = snd_hdspm_info_emphasis, \ | |
3178 | .get = snd_hdspm_get_emphasis, \ | |
3179 | .put = snd_hdspm_put_emphasis \ | |
3cee5a60 RB |
3180 | } |
3181 | ||
3182 | static int hdspm_emphasis(struct hdspm * hdspm) | |
3183 | { | |
3184 | return (hdspm->control_register & HDSPM_Emphasis) ? 1 : 0; | |
3185 | } | |
3186 | ||
3187 | static int hdspm_set_emphasis(struct hdspm * hdspm, int emp) | |
3188 | { | |
3189 | if (emp) | |
3190 | hdspm->control_register |= HDSPM_Emphasis; | |
3191 | else | |
3192 | hdspm->control_register &= ~HDSPM_Emphasis; | |
3193 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
3194 | ||
3195 | return 0; | |
3196 | } | |
3197 | ||
a5ce8890 | 3198 | #define snd_hdspm_info_emphasis snd_ctl_boolean_mono_info |
3cee5a60 RB |
3199 | |
3200 | static int snd_hdspm_get_emphasis(struct snd_kcontrol *kcontrol, | |
3201 | struct snd_ctl_elem_value *ucontrol) | |
3202 | { | |
3203 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
3204 | ||
3205 | spin_lock_irq(&hdspm->lock); | |
3206 | ucontrol->value.enumerated.item[0] = hdspm_emphasis(hdspm); | |
3207 | spin_unlock_irq(&hdspm->lock); | |
3208 | return 0; | |
3209 | } | |
3210 | ||
3211 | static int snd_hdspm_put_emphasis(struct snd_kcontrol *kcontrol, | |
3212 | struct snd_ctl_elem_value *ucontrol) | |
3213 | { | |
3214 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
3215 | int change; | |
3216 | unsigned int val; | |
3217 | ||
3218 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
3219 | return -EBUSY; | |
3220 | val = ucontrol->value.integer.value[0] & 1; | |
3221 | spin_lock_irq(&hdspm->lock); | |
3222 | change = (int) val != hdspm_emphasis(hdspm); | |
3223 | hdspm_set_emphasis(hdspm, val); | |
3224 | spin_unlock_irq(&hdspm->lock); | |
3225 | return change; | |
3226 | } | |
3227 | ||
0dca1793 | 3228 | |
3cee5a60 | 3229 | #define HDSPM_DOLBY(xname, xindex) \ |
f27a64f9 AK |
3230 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
3231 | .name = xname, \ | |
3232 | .index = xindex, \ | |
3233 | .info = snd_hdspm_info_dolby, \ | |
3234 | .get = snd_hdspm_get_dolby, \ | |
3235 | .put = snd_hdspm_put_dolby \ | |
3cee5a60 RB |
3236 | } |
3237 | ||
3238 | static int hdspm_dolby(struct hdspm * hdspm) | |
3239 | { | |
3240 | return (hdspm->control_register & HDSPM_Dolby) ? 1 : 0; | |
3241 | } | |
3242 | ||
3243 | static int hdspm_set_dolby(struct hdspm * hdspm, int dol) | |
3244 | { | |
3245 | if (dol) | |
3246 | hdspm->control_register |= HDSPM_Dolby; | |
3247 | else | |
3248 | hdspm->control_register &= ~HDSPM_Dolby; | |
3249 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
3250 | ||
3251 | return 0; | |
3252 | } | |
3253 | ||
a5ce8890 | 3254 | #define snd_hdspm_info_dolby snd_ctl_boolean_mono_info |
3cee5a60 RB |
3255 | |
3256 | static int snd_hdspm_get_dolby(struct snd_kcontrol *kcontrol, | |
3257 | struct snd_ctl_elem_value *ucontrol) | |
3258 | { | |
3259 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
3260 | ||
3261 | spin_lock_irq(&hdspm->lock); | |
3262 | ucontrol->value.enumerated.item[0] = hdspm_dolby(hdspm); | |
3263 | spin_unlock_irq(&hdspm->lock); | |
3264 | return 0; | |
3265 | } | |
3266 | ||
3267 | static int snd_hdspm_put_dolby(struct snd_kcontrol *kcontrol, | |
3268 | struct snd_ctl_elem_value *ucontrol) | |
3269 | { | |
3270 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
3271 | int change; | |
3272 | unsigned int val; | |
3273 | ||
3274 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
3275 | return -EBUSY; | |
3276 | val = ucontrol->value.integer.value[0] & 1; | |
3277 | spin_lock_irq(&hdspm->lock); | |
3278 | change = (int) val != hdspm_dolby(hdspm); | |
3279 | hdspm_set_dolby(hdspm, val); | |
3280 | spin_unlock_irq(&hdspm->lock); | |
3281 | return change; | |
3282 | } | |
3283 | ||
0dca1793 | 3284 | |
3cee5a60 | 3285 | #define HDSPM_PROFESSIONAL(xname, xindex) \ |
f27a64f9 AK |
3286 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
3287 | .name = xname, \ | |
3288 | .index = xindex, \ | |
3289 | .info = snd_hdspm_info_professional, \ | |
3290 | .get = snd_hdspm_get_professional, \ | |
3291 | .put = snd_hdspm_put_professional \ | |
3cee5a60 RB |
3292 | } |
3293 | ||
3294 | static int hdspm_professional(struct hdspm * hdspm) | |
3295 | { | |
3296 | return (hdspm->control_register & HDSPM_Professional) ? 1 : 0; | |
3297 | } | |
3298 | ||
3299 | static int hdspm_set_professional(struct hdspm * hdspm, int dol) | |
3300 | { | |
3301 | if (dol) | |
3302 | hdspm->control_register |= HDSPM_Professional; | |
3303 | else | |
3304 | hdspm->control_register &= ~HDSPM_Professional; | |
3305 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
3306 | ||
3307 | return 0; | |
3308 | } | |
3309 | ||
a5ce8890 | 3310 | #define snd_hdspm_info_professional snd_ctl_boolean_mono_info |
3cee5a60 RB |
3311 | |
3312 | static int snd_hdspm_get_professional(struct snd_kcontrol *kcontrol, | |
3313 | struct snd_ctl_elem_value *ucontrol) | |
3314 | { | |
3315 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
3316 | ||
3317 | spin_lock_irq(&hdspm->lock); | |
3318 | ucontrol->value.enumerated.item[0] = hdspm_professional(hdspm); | |
3319 | spin_unlock_irq(&hdspm->lock); | |
3320 | return 0; | |
3321 | } | |
3322 | ||
3323 | static int snd_hdspm_put_professional(struct snd_kcontrol *kcontrol, | |
3324 | struct snd_ctl_elem_value *ucontrol) | |
3325 | { | |
3326 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
3327 | int change; | |
3328 | unsigned int val; | |
3329 | ||
3330 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
3331 | return -EBUSY; | |
3332 | val = ucontrol->value.integer.value[0] & 1; | |
3333 | spin_lock_irq(&hdspm->lock); | |
3334 | change = (int) val != hdspm_professional(hdspm); | |
3335 | hdspm_set_professional(hdspm, val); | |
3336 | spin_unlock_irq(&hdspm->lock); | |
3337 | return change; | |
3338 | } | |
3339 | ||
3340 | #define HDSPM_INPUT_SELECT(xname, xindex) \ | |
f27a64f9 AK |
3341 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
3342 | .name = xname, \ | |
3343 | .index = xindex, \ | |
3344 | .info = snd_hdspm_info_input_select, \ | |
3345 | .get = snd_hdspm_get_input_select, \ | |
3346 | .put = snd_hdspm_put_input_select \ | |
3cee5a60 RB |
3347 | } |
3348 | ||
3349 | static int hdspm_input_select(struct hdspm * hdspm) | |
3350 | { | |
3351 | return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0; | |
3352 | } | |
3353 | ||
3354 | static int hdspm_set_input_select(struct hdspm * hdspm, int out) | |
3355 | { | |
3356 | if (out) | |
3357 | hdspm->control_register |= HDSPM_InputSelect0; | |
3358 | else | |
3359 | hdspm->control_register &= ~HDSPM_InputSelect0; | |
3360 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
3361 | ||
3362 | return 0; | |
3363 | } | |
3364 | ||
3365 | static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol, | |
3366 | struct snd_ctl_elem_info *uinfo) | |
3367 | { | |
3368 | static char *texts[] = { "optical", "coaxial" }; | |
3369 | ||
3370 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
3371 | uinfo->count = 1; | |
3372 | uinfo->value.enumerated.items = 2; | |
3373 | ||
3374 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
3375 | uinfo->value.enumerated.item = | |
3376 | uinfo->value.enumerated.items - 1; | |
3377 | strcpy(uinfo->value.enumerated.name, | |
3378 | texts[uinfo->value.enumerated.item]); | |
3379 | ||
3380 | return 0; | |
3381 | } | |
3382 | ||
3383 | static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol, | |
3384 | struct snd_ctl_elem_value *ucontrol) | |
3385 | { | |
3386 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
3387 | ||
3388 | spin_lock_irq(&hdspm->lock); | |
3389 | ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm); | |
3390 | spin_unlock_irq(&hdspm->lock); | |
3391 | return 0; | |
3392 | } | |
3393 | ||
3394 | static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol, | |
3395 | struct snd_ctl_elem_value *ucontrol) | |
3396 | { | |
3397 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
3398 | int change; | |
3399 | unsigned int val; | |
3400 | ||
3401 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
3402 | return -EBUSY; | |
3403 | val = ucontrol->value.integer.value[0] & 1; | |
3404 | spin_lock_irq(&hdspm->lock); | |
3405 | change = (int) val != hdspm_input_select(hdspm); | |
3406 | hdspm_set_input_select(hdspm, val); | |
3407 | spin_unlock_irq(&hdspm->lock); | |
3408 | return change; | |
3409 | } | |
3410 | ||
0dca1793 | 3411 | |
3cee5a60 | 3412 | #define HDSPM_DS_WIRE(xname, xindex) \ |
f27a64f9 AK |
3413 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
3414 | .name = xname, \ | |
3415 | .index = xindex, \ | |
3416 | .info = snd_hdspm_info_ds_wire, \ | |
3417 | .get = snd_hdspm_get_ds_wire, \ | |
3418 | .put = snd_hdspm_put_ds_wire \ | |
3cee5a60 RB |
3419 | } |
3420 | ||
3421 | static int hdspm_ds_wire(struct hdspm * hdspm) | |
763f356c | 3422 | { |
3cee5a60 | 3423 | return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0; |
763f356c TI |
3424 | } |
3425 | ||
3cee5a60 | 3426 | static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds) |
763f356c | 3427 | { |
3cee5a60 RB |
3428 | if (ds) |
3429 | hdspm->control_register |= HDSPM_DS_DoubleWire; | |
763f356c | 3430 | else |
3cee5a60 | 3431 | hdspm->control_register &= ~HDSPM_DS_DoubleWire; |
763f356c TI |
3432 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); |
3433 | ||
3434 | return 0; | |
3435 | } | |
3436 | ||
3cee5a60 RB |
3437 | static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol, |
3438 | struct snd_ctl_elem_info *uinfo) | |
763f356c | 3439 | { |
3cee5a60 RB |
3440 | static char *texts[] = { "Single", "Double" }; |
3441 | ||
3442 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
763f356c | 3443 | uinfo->count = 1; |
3cee5a60 RB |
3444 | uinfo->value.enumerated.items = 2; |
3445 | ||
3446 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
3447 | uinfo->value.enumerated.item = | |
3448 | uinfo->value.enumerated.items - 1; | |
3449 | strcpy(uinfo->value.enumerated.name, | |
3450 | texts[uinfo->value.enumerated.item]); | |
3451 | ||
763f356c TI |
3452 | return 0; |
3453 | } | |
3454 | ||
3cee5a60 RB |
3455 | static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol, |
3456 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 3457 | { |
98274f07 | 3458 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
3459 | |
3460 | spin_lock_irq(&hdspm->lock); | |
3cee5a60 | 3461 | ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm); |
763f356c TI |
3462 | spin_unlock_irq(&hdspm->lock); |
3463 | return 0; | |
3464 | } | |
3465 | ||
3cee5a60 RB |
3466 | static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol, |
3467 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 3468 | { |
98274f07 | 3469 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
3470 | int change; |
3471 | unsigned int val; | |
3472 | ||
3473 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
3474 | return -EBUSY; | |
3475 | val = ucontrol->value.integer.value[0] & 1; | |
3476 | spin_lock_irq(&hdspm->lock); | |
3cee5a60 RB |
3477 | change = (int) val != hdspm_ds_wire(hdspm); |
3478 | hdspm_set_ds_wire(hdspm, val); | |
763f356c TI |
3479 | spin_unlock_irq(&hdspm->lock); |
3480 | return change; | |
3481 | } | |
3482 | ||
0dca1793 | 3483 | |
3cee5a60 | 3484 | #define HDSPM_QS_WIRE(xname, xindex) \ |
f27a64f9 AK |
3485 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
3486 | .name = xname, \ | |
3487 | .index = xindex, \ | |
3488 | .info = snd_hdspm_info_qs_wire, \ | |
3489 | .get = snd_hdspm_get_qs_wire, \ | |
3490 | .put = snd_hdspm_put_qs_wire \ | |
763f356c TI |
3491 | } |
3492 | ||
3cee5a60 | 3493 | static int hdspm_qs_wire(struct hdspm * hdspm) |
763f356c | 3494 | { |
3cee5a60 RB |
3495 | if (hdspm->control_register & HDSPM_QS_DoubleWire) |
3496 | return 1; | |
3497 | if (hdspm->control_register & HDSPM_QS_QuadWire) | |
3498 | return 2; | |
3499 | return 0; | |
763f356c TI |
3500 | } |
3501 | ||
3cee5a60 | 3502 | static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode) |
763f356c | 3503 | { |
3cee5a60 RB |
3504 | hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire); |
3505 | switch (mode) { | |
3506 | case 0: | |
3507 | break; | |
3508 | case 1: | |
3509 | hdspm->control_register |= HDSPM_QS_DoubleWire; | |
3510 | break; | |
3511 | case 2: | |
3512 | hdspm->control_register |= HDSPM_QS_QuadWire; | |
3513 | break; | |
3514 | } | |
763f356c TI |
3515 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); |
3516 | ||
3517 | return 0; | |
3518 | } | |
3519 | ||
3cee5a60 | 3520 | static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol, |
98274f07 | 3521 | struct snd_ctl_elem_info *uinfo) |
763f356c | 3522 | { |
3cee5a60 | 3523 | static char *texts[] = { "Single", "Double", "Quad" }; |
763f356c TI |
3524 | |
3525 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
3526 | uinfo->count = 1; | |
3cee5a60 | 3527 | uinfo->value.enumerated.items = 3; |
763f356c TI |
3528 | |
3529 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
3530 | uinfo->value.enumerated.item = | |
3531 | uinfo->value.enumerated.items - 1; | |
3532 | strcpy(uinfo->value.enumerated.name, | |
3533 | texts[uinfo->value.enumerated.item]); | |
3534 | ||
3535 | return 0; | |
3536 | } | |
3537 | ||
3cee5a60 | 3538 | static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol, |
98274f07 | 3539 | struct snd_ctl_elem_value *ucontrol) |
763f356c | 3540 | { |
98274f07 | 3541 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
3542 | |
3543 | spin_lock_irq(&hdspm->lock); | |
3cee5a60 | 3544 | ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm); |
763f356c TI |
3545 | spin_unlock_irq(&hdspm->lock); |
3546 | return 0; | |
3547 | } | |
3548 | ||
3cee5a60 | 3549 | static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol, |
98274f07 | 3550 | struct snd_ctl_elem_value *ucontrol) |
763f356c | 3551 | { |
98274f07 | 3552 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c | 3553 | int change; |
3cee5a60 | 3554 | int val; |
763f356c TI |
3555 | |
3556 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
3557 | return -EBUSY; | |
3cee5a60 RB |
3558 | val = ucontrol->value.integer.value[0]; |
3559 | if (val < 0) | |
3560 | val = 0; | |
3561 | if (val > 2) | |
3562 | val = 2; | |
763f356c | 3563 | spin_lock_irq(&hdspm->lock); |
ef5fa1a4 | 3564 | change = val != hdspm_qs_wire(hdspm); |
3cee5a60 | 3565 | hdspm_set_qs_wire(hdspm, val); |
763f356c TI |
3566 | spin_unlock_irq(&hdspm->lock); |
3567 | return change; | |
3568 | } | |
3569 | ||
700d1ef3 AK |
3570 | #define HDSPM_MADI_SPEEDMODE(xname, xindex) \ |
3571 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
3572 | .name = xname, \ | |
3573 | .index = xindex, \ | |
3574 | .info = snd_hdspm_info_madi_speedmode, \ | |
3575 | .get = snd_hdspm_get_madi_speedmode, \ | |
3576 | .put = snd_hdspm_put_madi_speedmode \ | |
3577 | } | |
3578 | ||
3579 | static int hdspm_madi_speedmode(struct hdspm *hdspm) | |
3580 | { | |
3581 | if (hdspm->control_register & HDSPM_QuadSpeed) | |
3582 | return 2; | |
3583 | if (hdspm->control_register & HDSPM_DoubleSpeed) | |
3584 | return 1; | |
3585 | return 0; | |
3586 | } | |
3587 | ||
3588 | static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode) | |
3589 | { | |
3590 | hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed); | |
3591 | switch (mode) { | |
3592 | case 0: | |
3593 | break; | |
3594 | case 1: | |
3595 | hdspm->control_register |= HDSPM_DoubleSpeed; | |
3596 | break; | |
3597 | case 2: | |
3598 | hdspm->control_register |= HDSPM_QuadSpeed; | |
3599 | break; | |
3600 | } | |
3601 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
3602 | ||
3603 | return 0; | |
3604 | } | |
3605 | ||
3606 | static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol, | |
3607 | struct snd_ctl_elem_info *uinfo) | |
3608 | { | |
3609 | static char *texts[] = { "Single", "Double", "Quad" }; | |
3610 | ||
3611 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
3612 | uinfo->count = 1; | |
3613 | uinfo->value.enumerated.items = 3; | |
3614 | ||
3615 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
3616 | uinfo->value.enumerated.item = | |
3617 | uinfo->value.enumerated.items - 1; | |
3618 | strcpy(uinfo->value.enumerated.name, | |
3619 | texts[uinfo->value.enumerated.item]); | |
3620 | ||
3621 | return 0; | |
3622 | } | |
3623 | ||
3624 | static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol, | |
3625 | struct snd_ctl_elem_value *ucontrol) | |
3626 | { | |
3627 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
3628 | ||
3629 | spin_lock_irq(&hdspm->lock); | |
3630 | ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm); | |
3631 | spin_unlock_irq(&hdspm->lock); | |
3632 | return 0; | |
3633 | } | |
3634 | ||
3635 | static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol, | |
3636 | struct snd_ctl_elem_value *ucontrol) | |
3637 | { | |
3638 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
3639 | int change; | |
3640 | int val; | |
3641 | ||
3642 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
3643 | return -EBUSY; | |
3644 | val = ucontrol->value.integer.value[0]; | |
3645 | if (val < 0) | |
3646 | val = 0; | |
3647 | if (val > 2) | |
3648 | val = 2; | |
3649 | spin_lock_irq(&hdspm->lock); | |
3650 | change = val != hdspm_madi_speedmode(hdspm); | |
3651 | hdspm_set_madi_speedmode(hdspm, val); | |
3652 | spin_unlock_irq(&hdspm->lock); | |
3653 | return change; | |
3654 | } | |
763f356c TI |
3655 | |
3656 | #define HDSPM_MIXER(xname, xindex) \ | |
f27a64f9 AK |
3657 | { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ |
3658 | .name = xname, \ | |
3659 | .index = xindex, \ | |
3660 | .device = 0, \ | |
3661 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ | |
3662 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
3663 | .info = snd_hdspm_info_mixer, \ | |
3664 | .get = snd_hdspm_get_mixer, \ | |
3665 | .put = snd_hdspm_put_mixer \ | |
763f356c TI |
3666 | } |
3667 | ||
98274f07 TI |
3668 | static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol, |
3669 | struct snd_ctl_elem_info *uinfo) | |
763f356c TI |
3670 | { |
3671 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
3672 | uinfo->count = 3; | |
3673 | uinfo->value.integer.min = 0; | |
3674 | uinfo->value.integer.max = 65535; | |
3675 | uinfo->value.integer.step = 1; | |
3676 | return 0; | |
3677 | } | |
3678 | ||
98274f07 TI |
3679 | static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol, |
3680 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 3681 | { |
98274f07 | 3682 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
3683 | int source; |
3684 | int destination; | |
3685 | ||
3686 | source = ucontrol->value.integer.value[0]; | |
3687 | if (source < 0) | |
3688 | source = 0; | |
3689 | else if (source >= 2 * HDSPM_MAX_CHANNELS) | |
3690 | source = 2 * HDSPM_MAX_CHANNELS - 1; | |
3691 | ||
3692 | destination = ucontrol->value.integer.value[1]; | |
3693 | if (destination < 0) | |
3694 | destination = 0; | |
3695 | else if (destination >= HDSPM_MAX_CHANNELS) | |
3696 | destination = HDSPM_MAX_CHANNELS - 1; | |
3697 | ||
3698 | spin_lock_irq(&hdspm->lock); | |
3699 | if (source >= HDSPM_MAX_CHANNELS) | |
3700 | ucontrol->value.integer.value[2] = | |
3701 | hdspm_read_pb_gain(hdspm, destination, | |
3702 | source - HDSPM_MAX_CHANNELS); | |
3703 | else | |
3704 | ucontrol->value.integer.value[2] = | |
3705 | hdspm_read_in_gain(hdspm, destination, source); | |
3706 | ||
3707 | spin_unlock_irq(&hdspm->lock); | |
3708 | ||
3709 | return 0; | |
3710 | } | |
3711 | ||
98274f07 TI |
3712 | static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol, |
3713 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 3714 | { |
98274f07 | 3715 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
3716 | int change; |
3717 | int source; | |
3718 | int destination; | |
3719 | int gain; | |
3720 | ||
3721 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
3722 | return -EBUSY; | |
3723 | ||
3724 | source = ucontrol->value.integer.value[0]; | |
3725 | destination = ucontrol->value.integer.value[1]; | |
3726 | ||
3727 | if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS) | |
3728 | return -1; | |
3729 | if (destination < 0 || destination >= HDSPM_MAX_CHANNELS) | |
3730 | return -1; | |
3731 | ||
3732 | gain = ucontrol->value.integer.value[2]; | |
3733 | ||
3734 | spin_lock_irq(&hdspm->lock); | |
3735 | ||
3736 | if (source >= HDSPM_MAX_CHANNELS) | |
3737 | change = gain != hdspm_read_pb_gain(hdspm, destination, | |
3738 | source - | |
3739 | HDSPM_MAX_CHANNELS); | |
3740 | else | |
ef5fa1a4 TI |
3741 | change = gain != hdspm_read_in_gain(hdspm, destination, |
3742 | source); | |
763f356c TI |
3743 | |
3744 | if (change) { | |
3745 | if (source >= HDSPM_MAX_CHANNELS) | |
3746 | hdspm_write_pb_gain(hdspm, destination, | |
3747 | source - HDSPM_MAX_CHANNELS, | |
3748 | gain); | |
3749 | else | |
3750 | hdspm_write_in_gain(hdspm, destination, source, | |
3751 | gain); | |
3752 | } | |
3753 | spin_unlock_irq(&hdspm->lock); | |
3754 | ||
3755 | return change; | |
3756 | } | |
3757 | ||
3758 | /* The simple mixer control(s) provide gain control for the | |
3759 | basic 1:1 mappings of playback streams to output | |
0dca1793 | 3760 | streams. |
763f356c TI |
3761 | */ |
3762 | ||
3763 | #define HDSPM_PLAYBACK_MIXER \ | |
f27a64f9 AK |
3764 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
3765 | .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \ | |
3766 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
3767 | .info = snd_hdspm_info_playback_mixer, \ | |
3768 | .get = snd_hdspm_get_playback_mixer, \ | |
3769 | .put = snd_hdspm_put_playback_mixer \ | |
763f356c TI |
3770 | } |
3771 | ||
98274f07 TI |
3772 | static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol, |
3773 | struct snd_ctl_elem_info *uinfo) | |
763f356c TI |
3774 | { |
3775 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
3776 | uinfo->count = 1; | |
3777 | uinfo->value.integer.min = 0; | |
0dca1793 | 3778 | uinfo->value.integer.max = 64; |
763f356c TI |
3779 | uinfo->value.integer.step = 1; |
3780 | return 0; | |
3781 | } | |
3782 | ||
98274f07 TI |
3783 | static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol, |
3784 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 3785 | { |
98274f07 | 3786 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c | 3787 | int channel; |
763f356c TI |
3788 | |
3789 | channel = ucontrol->id.index - 1; | |
3790 | ||
da3cec35 TI |
3791 | if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS)) |
3792 | return -EINVAL; | |
763f356c | 3793 | |
763f356c TI |
3794 | spin_lock_irq(&hdspm->lock); |
3795 | ucontrol->value.integer.value[0] = | |
0dca1793 | 3796 | (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN; |
763f356c TI |
3797 | spin_unlock_irq(&hdspm->lock); |
3798 | ||
763f356c TI |
3799 | return 0; |
3800 | } | |
3801 | ||
98274f07 TI |
3802 | static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol, |
3803 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 3804 | { |
98274f07 | 3805 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
3806 | int change; |
3807 | int channel; | |
763f356c TI |
3808 | int gain; |
3809 | ||
3810 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
3811 | return -EBUSY; | |
3812 | ||
3813 | channel = ucontrol->id.index - 1; | |
3814 | ||
da3cec35 TI |
3815 | if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS)) |
3816 | return -EINVAL; | |
763f356c | 3817 | |
0dca1793 | 3818 | gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64; |
763f356c TI |
3819 | |
3820 | spin_lock_irq(&hdspm->lock); | |
3821 | change = | |
0dca1793 AK |
3822 | gain != hdspm_read_pb_gain(hdspm, channel, |
3823 | channel); | |
763f356c | 3824 | if (change) |
0dca1793 | 3825 | hdspm_write_pb_gain(hdspm, channel, channel, |
763f356c TI |
3826 | gain); |
3827 | spin_unlock_irq(&hdspm->lock); | |
3828 | return change; | |
3829 | } | |
3830 | ||
0dca1793 AK |
3831 | #define HDSPM_SYNC_CHECK(xname, xindex) \ |
3832 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
3833 | .name = xname, \ | |
3834 | .private_value = xindex, \ | |
3835 | .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
3836 | .info = snd_hdspm_info_sync_check, \ | |
3837 | .get = snd_hdspm_get_sync_check \ | |
763f356c TI |
3838 | } |
3839 | ||
0dca1793 | 3840 | |
98274f07 TI |
3841 | static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol, |
3842 | struct snd_ctl_elem_info *uinfo) | |
763f356c | 3843 | { |
0dca1793 | 3844 | static char *texts[] = { "No Lock", "Lock", "Sync", "N/A" }; |
763f356c TI |
3845 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; |
3846 | uinfo->count = 1; | |
0dca1793 | 3847 | uinfo->value.enumerated.items = 4; |
763f356c TI |
3848 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) |
3849 | uinfo->value.enumerated.item = | |
0dca1793 | 3850 | uinfo->value.enumerated.items - 1; |
763f356c | 3851 | strcpy(uinfo->value.enumerated.name, |
0dca1793 | 3852 | texts[uinfo->value.enumerated.item]); |
763f356c TI |
3853 | return 0; |
3854 | } | |
3855 | ||
0dca1793 | 3856 | static int hdspm_wc_sync_check(struct hdspm *hdspm) |
763f356c | 3857 | { |
0dca1793 AK |
3858 | int status, status2; |
3859 | ||
3860 | switch (hdspm->io_type) { | |
3861 | case AES32: | |
3862 | status = hdspm_read(hdspm, HDSPM_statusRegister); | |
3863 | if (status & HDSPM_wcSync) | |
763f356c | 3864 | return 2; |
0dca1793 AK |
3865 | else if (status & HDSPM_wcLock) |
3866 | return 1; | |
3cee5a60 | 3867 | return 0; |
0dca1793 AK |
3868 | break; |
3869 | ||
3870 | case MADI: | |
3871 | status2 = hdspm_read(hdspm, HDSPM_statusRegister2); | |
3cee5a60 RB |
3872 | if (status2 & HDSPM_wcLock) { |
3873 | if (status2 & HDSPM_wcSync) | |
3874 | return 2; | |
3875 | else | |
3876 | return 1; | |
3877 | } | |
3878 | return 0; | |
0dca1793 | 3879 | break; |
763f356c | 3880 | |
0dca1793 AK |
3881 | case RayDAT: |
3882 | case AIO: | |
3883 | status = hdspm_read(hdspm, HDSPM_statusRegister); | |
763f356c | 3884 | |
0dca1793 AK |
3885 | if (status & 0x2000000) |
3886 | return 2; | |
3887 | else if (status & 0x1000000) | |
3888 | return 1; | |
3889 | return 0; | |
763f356c | 3890 | |
0dca1793 | 3891 | break; |
763f356c | 3892 | |
0dca1793 AK |
3893 | case MADIface: |
3894 | break; | |
3895 | } | |
3896 | ||
3897 | ||
3898 | return 3; | |
763f356c TI |
3899 | } |
3900 | ||
0dca1793 AK |
3901 | |
3902 | static int hdspm_madi_sync_check(struct hdspm *hdspm) | |
763f356c TI |
3903 | { |
3904 | int status = hdspm_read(hdspm, HDSPM_statusRegister); | |
3905 | if (status & HDSPM_madiLock) { | |
3906 | if (status & HDSPM_madiSync) | |
3907 | return 2; | |
3908 | else | |
3909 | return 1; | |
3910 | } | |
3911 | return 0; | |
3912 | } | |
3913 | ||
763f356c | 3914 | |
0dca1793 AK |
3915 | static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx) |
3916 | { | |
3917 | int status, lock, sync; | |
763f356c | 3918 | |
0dca1793 | 3919 | status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); |
763f356c | 3920 | |
0dca1793 AK |
3921 | lock = (status & (0x1<<idx)) ? 1 : 0; |
3922 | sync = (status & (0x100<<idx)) ? 1 : 0; | |
3cee5a60 | 3923 | |
0dca1793 | 3924 | if (lock && sync) |
3cee5a60 | 3925 | return 2; |
0dca1793 AK |
3926 | else if (lock) |
3927 | return 1; | |
3cee5a60 RB |
3928 | return 0; |
3929 | } | |
3930 | ||
0dca1793 AK |
3931 | |
3932 | static int hdspm_sync_in_sync_check(struct hdspm *hdspm) | |
3933 | { | |
3934 | int status, lock = 0, sync = 0; | |
3935 | ||
3936 | switch (hdspm->io_type) { | |
3937 | case RayDAT: | |
3938 | case AIO: | |
3939 | status = hdspm_read(hdspm, HDSPM_RD_STATUS_3); | |
3940 | lock = (status & 0x400) ? 1 : 0; | |
3941 | sync = (status & 0x800) ? 1 : 0; | |
3942 | break; | |
3943 | ||
3944 | case MADI: | |
2e0452f5 AK |
3945 | status = hdspm_read(hdspm, HDSPM_statusRegister); |
3946 | lock = (status & HDSPM_syncInLock) ? 1 : 0; | |
3947 | sync = (status & HDSPM_syncInSync) ? 1 : 0; | |
3948 | break; | |
3949 | ||
0dca1793 AK |
3950 | case AES32: |
3951 | status = hdspm_read(hdspm, HDSPM_statusRegister2); | |
9a215f47 AK |
3952 | lock = (status & 0x100000) ? 1 : 0; |
3953 | sync = (status & 0x200000) ? 1 : 0; | |
0dca1793 AK |
3954 | break; |
3955 | ||
3956 | case MADIface: | |
3957 | break; | |
3958 | } | |
3959 | ||
3960 | if (lock && sync) | |
3961 | return 2; | |
3962 | else if (lock) | |
3963 | return 1; | |
3964 | ||
3965 | return 0; | |
3966 | } | |
3967 | ||
3968 | static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx) | |
3969 | { | |
3970 | int status2, lock, sync; | |
3971 | status2 = hdspm_read(hdspm, HDSPM_statusRegister2); | |
3972 | ||
3973 | lock = (status2 & (0x0080 >> idx)) ? 1 : 0; | |
3974 | sync = (status2 & (0x8000 >> idx)) ? 1 : 0; | |
3975 | ||
3976 | if (sync) | |
3977 | return 2; | |
3978 | else if (lock) | |
3979 | return 1; | |
3980 | return 0; | |
3981 | } | |
3982 | ||
3983 | ||
3984 | static int hdspm_tco_sync_check(struct hdspm *hdspm) | |
3985 | { | |
3986 | int status; | |
3987 | ||
3988 | if (hdspm->tco) { | |
3989 | switch (hdspm->io_type) { | |
3990 | case MADI: | |
3991 | case AES32: | |
3992 | status = hdspm_read(hdspm, HDSPM_statusRegister); | |
3993 | if (status & HDSPM_tcoLock) { | |
3994 | if (status & HDSPM_tcoSync) | |
3995 | return 2; | |
3996 | else | |
3997 | return 1; | |
3998 | } | |
3999 | return 0; | |
4000 | ||
4001 | break; | |
4002 | ||
4003 | case RayDAT: | |
4004 | case AIO: | |
4005 | status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); | |
4006 | ||
4007 | if (status & 0x8000000) | |
4008 | return 2; /* Sync */ | |
4009 | if (status & 0x4000000) | |
4010 | return 1; /* Lock */ | |
4011 | return 0; /* No signal */ | |
4012 | break; | |
4013 | ||
4014 | default: | |
4015 | break; | |
4016 | } | |
4017 | } | |
4018 | ||
4019 | return 3; /* N/A */ | |
4020 | } | |
4021 | ||
4022 | ||
4023 | static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol, | |
4024 | struct snd_ctl_elem_value *ucontrol) | |
4025 | { | |
4026 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
4027 | int val = -1; | |
4028 | ||
4029 | switch (hdspm->io_type) { | |
4030 | case RayDAT: | |
4031 | switch (kcontrol->private_value) { | |
4032 | case 0: /* WC */ | |
4033 | val = hdspm_wc_sync_check(hdspm); break; | |
4034 | case 7: /* TCO */ | |
4035 | val = hdspm_tco_sync_check(hdspm); break; | |
4036 | case 8: /* SYNC IN */ | |
4037 | val = hdspm_sync_in_sync_check(hdspm); break; | |
4038 | default: | |
d1a3c98d AK |
4039 | val = hdspm_s1_sync_check(hdspm, |
4040 | kcontrol->private_value-1); | |
0dca1793 | 4041 | } |
fba30fd3 | 4042 | break; |
0dca1793 AK |
4043 | |
4044 | case AIO: | |
4045 | switch (kcontrol->private_value) { | |
4046 | case 0: /* WC */ | |
4047 | val = hdspm_wc_sync_check(hdspm); break; | |
4048 | case 4: /* TCO */ | |
4049 | val = hdspm_tco_sync_check(hdspm); break; | |
4050 | case 5: /* SYNC IN */ | |
4051 | val = hdspm_sync_in_sync_check(hdspm); break; | |
4052 | default: | |
4053 | val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1); | |
4054 | } | |
fba30fd3 | 4055 | break; |
0dca1793 AK |
4056 | |
4057 | case MADI: | |
4058 | switch (kcontrol->private_value) { | |
4059 | case 0: /* WC */ | |
4060 | val = hdspm_wc_sync_check(hdspm); break; | |
4061 | case 1: /* MADI */ | |
4062 | val = hdspm_madi_sync_check(hdspm); break; | |
4063 | case 2: /* TCO */ | |
4064 | val = hdspm_tco_sync_check(hdspm); break; | |
4065 | case 3: /* SYNC_IN */ | |
4066 | val = hdspm_sync_in_sync_check(hdspm); break; | |
4067 | } | |
fba30fd3 | 4068 | break; |
0dca1793 AK |
4069 | |
4070 | case MADIface: | |
4071 | val = hdspm_madi_sync_check(hdspm); /* MADI */ | |
4072 | break; | |
4073 | ||
4074 | case AES32: | |
4075 | switch (kcontrol->private_value) { | |
4076 | case 0: /* WC */ | |
4077 | val = hdspm_wc_sync_check(hdspm); break; | |
4078 | case 9: /* TCO */ | |
4079 | val = hdspm_tco_sync_check(hdspm); break; | |
4080 | case 10 /* SYNC IN */: | |
4081 | val = hdspm_sync_in_sync_check(hdspm); break; | |
7c4a95b5 | 4082 | default: /* AES1 to AES8 */ |
0dca1793 | 4083 | val = hdspm_aes_sync_check(hdspm, |
7c4a95b5 | 4084 | kcontrol->private_value-1); |
0dca1793 | 4085 | } |
fba30fd3 | 4086 | break; |
0dca1793 AK |
4087 | |
4088 | } | |
4089 | ||
4090 | if (-1 == val) | |
4091 | val = 3; | |
4092 | ||
4093 | ucontrol->value.enumerated.item[0] = val; | |
4094 | return 0; | |
4095 | } | |
4096 | ||
4097 | ||
4098 | ||
4099 | /** | |
4100 | * TCO controls | |
4101 | **/ | |
4102 | static void hdspm_tco_write(struct hdspm *hdspm) | |
4103 | { | |
4104 | unsigned int tc[4] = { 0, 0, 0, 0}; | |
4105 | ||
4106 | switch (hdspm->tco->input) { | |
4107 | case 0: | |
4108 | tc[2] |= HDSPM_TCO2_set_input_MSB; | |
4109 | break; | |
4110 | case 1: | |
4111 | tc[2] |= HDSPM_TCO2_set_input_LSB; | |
4112 | break; | |
4113 | default: | |
4114 | break; | |
4115 | } | |
4116 | ||
4117 | switch (hdspm->tco->framerate) { | |
4118 | case 1: | |
4119 | tc[1] |= HDSPM_TCO1_LTC_Format_LSB; | |
4120 | break; | |
4121 | case 2: | |
4122 | tc[1] |= HDSPM_TCO1_LTC_Format_MSB; | |
4123 | break; | |
4124 | case 3: | |
4125 | tc[1] |= HDSPM_TCO1_LTC_Format_MSB + | |
4126 | HDSPM_TCO1_set_drop_frame_flag; | |
4127 | break; | |
4128 | case 4: | |
4129 | tc[1] |= HDSPM_TCO1_LTC_Format_LSB + | |
4130 | HDSPM_TCO1_LTC_Format_MSB; | |
4131 | break; | |
4132 | case 5: | |
4133 | tc[1] |= HDSPM_TCO1_LTC_Format_LSB + | |
4134 | HDSPM_TCO1_LTC_Format_MSB + | |
4135 | HDSPM_TCO1_set_drop_frame_flag; | |
4136 | break; | |
4137 | default: | |
4138 | break; | |
4139 | } | |
4140 | ||
4141 | switch (hdspm->tco->wordclock) { | |
4142 | case 1: | |
4143 | tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB; | |
4144 | break; | |
4145 | case 2: | |
4146 | tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB; | |
4147 | break; | |
4148 | default: | |
4149 | break; | |
4150 | } | |
4151 | ||
4152 | switch (hdspm->tco->samplerate) { | |
4153 | case 1: | |
4154 | tc[2] |= HDSPM_TCO2_set_freq; | |
4155 | break; | |
4156 | case 2: | |
4157 | tc[2] |= HDSPM_TCO2_set_freq_from_app; | |
4158 | break; | |
4159 | default: | |
4160 | break; | |
4161 | } | |
4162 | ||
4163 | switch (hdspm->tco->pull) { | |
4164 | case 1: | |
4165 | tc[2] |= HDSPM_TCO2_set_pull_up; | |
4166 | break; | |
4167 | case 2: | |
4168 | tc[2] |= HDSPM_TCO2_set_pull_down; | |
4169 | break; | |
4170 | case 3: | |
4171 | tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4; | |
4172 | break; | |
4173 | case 4: | |
4174 | tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4; | |
4175 | break; | |
4176 | default: | |
4177 | break; | |
4178 | } | |
4179 | ||
4180 | if (1 == hdspm->tco->term) { | |
4181 | tc[2] |= HDSPM_TCO2_set_term_75R; | |
4182 | } | |
4183 | ||
4184 | hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]); | |
4185 | hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]); | |
4186 | hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]); | |
4187 | hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]); | |
4188 | } | |
4189 | ||
4190 | ||
4191 | #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \ | |
4192 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
4193 | .name = xname, \ | |
4194 | .index = xindex, \ | |
4195 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ | |
4196 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
4197 | .info = snd_hdspm_info_tco_sample_rate, \ | |
4198 | .get = snd_hdspm_get_tco_sample_rate, \ | |
4199 | .put = snd_hdspm_put_tco_sample_rate \ | |
4200 | } | |
4201 | ||
4202 | static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol, | |
4203 | struct snd_ctl_elem_info *uinfo) | |
4204 | { | |
4205 | static char *texts[] = { "44.1 kHz", "48 kHz" }; | |
4206 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
4207 | uinfo->count = 1; | |
4208 | uinfo->value.enumerated.items = 2; | |
4209 | ||
4210 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
4211 | uinfo->value.enumerated.item = | |
4212 | uinfo->value.enumerated.items - 1; | |
4213 | ||
4214 | strcpy(uinfo->value.enumerated.name, | |
4215 | texts[uinfo->value.enumerated.item]); | |
4216 | ||
4217 | return 0; | |
4218 | } | |
4219 | ||
4220 | static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol, | |
4221 | struct snd_ctl_elem_value *ucontrol) | |
4222 | { | |
4223 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
4224 | ||
4225 | ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate; | |
4226 | ||
4227 | return 0; | |
4228 | } | |
4229 | ||
4230 | static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol, | |
4231 | struct snd_ctl_elem_value *ucontrol) | |
4232 | { | |
4233 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
4234 | ||
4235 | if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) { | |
4236 | hdspm->tco->samplerate = ucontrol->value.enumerated.item[0]; | |
4237 | ||
4238 | hdspm_tco_write(hdspm); | |
4239 | ||
4240 | return 1; | |
4241 | } | |
4242 | ||
4243 | return 0; | |
4244 | } | |
4245 | ||
4246 | ||
4247 | #define HDSPM_TCO_PULL(xname, xindex) \ | |
4248 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
4249 | .name = xname, \ | |
4250 | .index = xindex, \ | |
4251 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ | |
4252 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
4253 | .info = snd_hdspm_info_tco_pull, \ | |
4254 | .get = snd_hdspm_get_tco_pull, \ | |
4255 | .put = snd_hdspm_put_tco_pull \ | |
4256 | } | |
4257 | ||
4258 | static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol, | |
4259 | struct snd_ctl_elem_info *uinfo) | |
4260 | { | |
4261 | static char *texts[] = { "0", "+ 0.1 %", "- 0.1 %", "+ 4 %", "- 4 %" }; | |
4262 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
4263 | uinfo->count = 1; | |
4264 | uinfo->value.enumerated.items = 5; | |
4265 | ||
4266 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
4267 | uinfo->value.enumerated.item = | |
4268 | uinfo->value.enumerated.items - 1; | |
4269 | ||
4270 | strcpy(uinfo->value.enumerated.name, | |
4271 | texts[uinfo->value.enumerated.item]); | |
4272 | ||
4273 | return 0; | |
4274 | } | |
4275 | ||
4276 | static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol, | |
4277 | struct snd_ctl_elem_value *ucontrol) | |
4278 | { | |
4279 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
4280 | ||
4281 | ucontrol->value.enumerated.item[0] = hdspm->tco->pull; | |
4282 | ||
4283 | return 0; | |
4284 | } | |
4285 | ||
4286 | static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol, | |
4287 | struct snd_ctl_elem_value *ucontrol) | |
4288 | { | |
4289 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
4290 | ||
4291 | if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) { | |
4292 | hdspm->tco->pull = ucontrol->value.enumerated.item[0]; | |
4293 | ||
4294 | hdspm_tco_write(hdspm); | |
4295 | ||
4296 | return 1; | |
4297 | } | |
4298 | ||
4299 | return 0; | |
4300 | } | |
4301 | ||
4302 | #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \ | |
4303 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
4304 | .name = xname, \ | |
4305 | .index = xindex, \ | |
4306 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ | |
4307 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
4308 | .info = snd_hdspm_info_tco_wck_conversion, \ | |
4309 | .get = snd_hdspm_get_tco_wck_conversion, \ | |
4310 | .put = snd_hdspm_put_tco_wck_conversion \ | |
4311 | } | |
4312 | ||
4313 | static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol, | |
4314 | struct snd_ctl_elem_info *uinfo) | |
4315 | { | |
4316 | static char *texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" }; | |
4317 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
4318 | uinfo->count = 1; | |
4319 | uinfo->value.enumerated.items = 3; | |
4320 | ||
4321 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
4322 | uinfo->value.enumerated.item = | |
4323 | uinfo->value.enumerated.items - 1; | |
4324 | ||
4325 | strcpy(uinfo->value.enumerated.name, | |
4326 | texts[uinfo->value.enumerated.item]); | |
4327 | ||
4328 | return 0; | |
4329 | } | |
4330 | ||
4331 | static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol, | |
4332 | struct snd_ctl_elem_value *ucontrol) | |
4333 | { | |
4334 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
4335 | ||
4336 | ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock; | |
4337 | ||
4338 | return 0; | |
4339 | } | |
4340 | ||
4341 | static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol, | |
4342 | struct snd_ctl_elem_value *ucontrol) | |
4343 | { | |
4344 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
4345 | ||
4346 | if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) { | |
4347 | hdspm->tco->wordclock = ucontrol->value.enumerated.item[0]; | |
4348 | ||
4349 | hdspm_tco_write(hdspm); | |
4350 | ||
4351 | return 1; | |
4352 | } | |
4353 | ||
4354 | return 0; | |
4355 | } | |
4356 | ||
4357 | ||
4358 | #define HDSPM_TCO_FRAME_RATE(xname, xindex) \ | |
4359 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
4360 | .name = xname, \ | |
4361 | .index = xindex, \ | |
4362 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ | |
4363 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
4364 | .info = snd_hdspm_info_tco_frame_rate, \ | |
4365 | .get = snd_hdspm_get_tco_frame_rate, \ | |
4366 | .put = snd_hdspm_put_tco_frame_rate \ | |
4367 | } | |
4368 | ||
4369 | static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol, | |
4370 | struct snd_ctl_elem_info *uinfo) | |
4371 | { | |
4372 | static char *texts[] = { "24 fps", "25 fps", "29.97fps", | |
4373 | "29.97 dfps", "30 fps", "30 dfps" }; | |
4374 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
4375 | uinfo->count = 1; | |
4376 | uinfo->value.enumerated.items = 6; | |
4377 | ||
4378 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
4379 | uinfo->value.enumerated.item = | |
4380 | uinfo->value.enumerated.items - 1; | |
4381 | ||
4382 | strcpy(uinfo->value.enumerated.name, | |
4383 | texts[uinfo->value.enumerated.item]); | |
4384 | ||
4385 | return 0; | |
4386 | } | |
4387 | ||
4388 | static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol, | |
3cee5a60 RB |
4389 | struct snd_ctl_elem_value *ucontrol) |
4390 | { | |
3cee5a60 RB |
4391 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
4392 | ||
0dca1793 | 4393 | ucontrol->value.enumerated.item[0] = hdspm->tco->framerate; |
3cee5a60 | 4394 | |
3cee5a60 RB |
4395 | return 0; |
4396 | } | |
763f356c | 4397 | |
0dca1793 AK |
4398 | static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol, |
4399 | struct snd_ctl_elem_value *ucontrol) | |
4400 | { | |
4401 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
763f356c | 4402 | |
0dca1793 AK |
4403 | if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) { |
4404 | hdspm->tco->framerate = ucontrol->value.enumerated.item[0]; | |
763f356c | 4405 | |
0dca1793 AK |
4406 | hdspm_tco_write(hdspm); |
4407 | ||
4408 | return 1; | |
4409 | } | |
4410 | ||
4411 | return 0; | |
4412 | } | |
763f356c | 4413 | |
0dca1793 AK |
4414 | |
4415 | #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \ | |
4416 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
4417 | .name = xname, \ | |
4418 | .index = xindex, \ | |
4419 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ | |
4420 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
4421 | .info = snd_hdspm_info_tco_sync_source, \ | |
4422 | .get = snd_hdspm_get_tco_sync_source, \ | |
4423 | .put = snd_hdspm_put_tco_sync_source \ | |
4424 | } | |
4425 | ||
4426 | static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol, | |
4427 | struct snd_ctl_elem_info *uinfo) | |
4428 | { | |
4429 | static char *texts[] = { "LTC", "Video", "WCK" }; | |
4430 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
4431 | uinfo->count = 1; | |
4432 | uinfo->value.enumerated.items = 3; | |
4433 | ||
4434 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
4435 | uinfo->value.enumerated.item = | |
4436 | uinfo->value.enumerated.items - 1; | |
4437 | ||
4438 | strcpy(uinfo->value.enumerated.name, | |
4439 | texts[uinfo->value.enumerated.item]); | |
4440 | ||
4441 | return 0; | |
4442 | } | |
4443 | ||
4444 | static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol, | |
4445 | struct snd_ctl_elem_value *ucontrol) | |
4446 | { | |
4447 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
4448 | ||
4449 | ucontrol->value.enumerated.item[0] = hdspm->tco->input; | |
4450 | ||
4451 | return 0; | |
4452 | } | |
4453 | ||
4454 | static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol, | |
4455 | struct snd_ctl_elem_value *ucontrol) | |
4456 | { | |
4457 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
4458 | ||
4459 | if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) { | |
4460 | hdspm->tco->input = ucontrol->value.enumerated.item[0]; | |
4461 | ||
4462 | hdspm_tco_write(hdspm); | |
4463 | ||
4464 | return 1; | |
4465 | } | |
4466 | ||
4467 | return 0; | |
4468 | } | |
4469 | ||
4470 | ||
4471 | #define HDSPM_TCO_WORD_TERM(xname, xindex) \ | |
4472 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
4473 | .name = xname, \ | |
4474 | .index = xindex, \ | |
4475 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ | |
4476 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
4477 | .info = snd_hdspm_info_tco_word_term, \ | |
4478 | .get = snd_hdspm_get_tco_word_term, \ | |
4479 | .put = snd_hdspm_put_tco_word_term \ | |
4480 | } | |
4481 | ||
4482 | static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol, | |
4483 | struct snd_ctl_elem_info *uinfo) | |
4484 | { | |
4485 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; | |
4486 | uinfo->count = 1; | |
4487 | uinfo->value.integer.min = 0; | |
4488 | uinfo->value.integer.max = 1; | |
4489 | ||
4490 | return 0; | |
4491 | } | |
4492 | ||
4493 | ||
4494 | static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol, | |
4495 | struct snd_ctl_elem_value *ucontrol) | |
4496 | { | |
4497 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
4498 | ||
4499 | ucontrol->value.enumerated.item[0] = hdspm->tco->term; | |
4500 | ||
4501 | return 0; | |
4502 | } | |
4503 | ||
4504 | ||
4505 | static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol, | |
4506 | struct snd_ctl_elem_value *ucontrol) | |
4507 | { | |
4508 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
4509 | ||
4510 | if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) { | |
4511 | hdspm->tco->term = ucontrol->value.enumerated.item[0]; | |
4512 | ||
4513 | hdspm_tco_write(hdspm); | |
4514 | ||
4515 | return 1; | |
4516 | } | |
4517 | ||
4518 | return 0; | |
4519 | } | |
4520 | ||
4521 | ||
4522 | ||
4523 | ||
4524 | static struct snd_kcontrol_new snd_hdspm_controls_madi[] = { | |
4525 | HDSPM_MIXER("Mixer", 0), | |
4526 | HDSPM_INTERNAL_CLOCK("Internal Clock", 0), | |
763f356c TI |
4527 | HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), |
4528 | HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), | |
4529 | HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), | |
4530 | HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), | |
b8812c55 | 4531 | HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), |
0dca1793 AK |
4532 | HDSPM_SYNC_CHECK("WC SyncCheck", 0), |
4533 | HDSPM_SYNC_CHECK("MADI SyncCheck", 1), | |
930f4ff0 | 4534 | HDSPM_SYNC_CHECK("TCO SyncCheck", 2), |
0dca1793 | 4535 | HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3), |
763f356c TI |
4536 | HDSPM_LINE_OUT("Line Out", 0), |
4537 | HDSPM_TX_64("TX 64 channels mode", 0), | |
4538 | HDSPM_C_TMS("Clear Track Marker", 0), | |
4539 | HDSPM_SAFE_MODE("Safe Mode", 0), | |
700d1ef3 AK |
4540 | HDSPM_INPUT_SELECT("Input Select", 0), |
4541 | HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0) | |
0dca1793 AK |
4542 | }; |
4543 | ||
4544 | ||
4545 | static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = { | |
4546 | HDSPM_MIXER("Mixer", 0), | |
4547 | HDSPM_INTERNAL_CLOCK("Internal Clock", 0), | |
4548 | HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), | |
4549 | HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), | |
4550 | HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), | |
4551 | HDSPM_SYNC_CHECK("MADI SyncCheck", 0), | |
4552 | HDSPM_TX_64("TX 64 channels mode", 0), | |
4553 | HDSPM_C_TMS("Clear Track Marker", 0), | |
700d1ef3 AK |
4554 | HDSPM_SAFE_MODE("Safe Mode", 0), |
4555 | HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0) | |
763f356c TI |
4556 | }; |
4557 | ||
0dca1793 AK |
4558 | static struct snd_kcontrol_new snd_hdspm_controls_aio[] = { |
4559 | HDSPM_MIXER("Mixer", 0), | |
4560 | HDSPM_INTERNAL_CLOCK("Internal Clock", 0), | |
4561 | HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), | |
4562 | HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), | |
4563 | HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), | |
4564 | HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), | |
4565 | HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), | |
4566 | HDSPM_SYNC_CHECK("WC SyncCheck", 0), | |
4567 | HDSPM_SYNC_CHECK("AES SyncCheck", 1), | |
4568 | HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2), | |
4569 | HDSPM_SYNC_CHECK("ADAT SyncCheck", 3), | |
4570 | HDSPM_SYNC_CHECK("TCO SyncCheck", 4), | |
4571 | HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5), | |
4572 | HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), | |
4573 | HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1), | |
4574 | HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2), | |
4575 | HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3), | |
4576 | HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4), | |
4577 | HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5) | |
4578 | ||
4579 | /* | |
4580 | HDSPM_INPUT_SELECT("Input Select", 0), | |
4581 | HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0), | |
4582 | HDSPM_PROFESSIONAL("SPDIF Out Professional", 0); | |
4583 | HDSPM_SPDIF_IN("SPDIF In", 0); | |
4584 | HDSPM_BREAKOUT_CABLE("Breakout Cable", 0); | |
4585 | HDSPM_INPUT_LEVEL("Input Level", 0); | |
4586 | HDSPM_OUTPUT_LEVEL("Output Level", 0); | |
4587 | HDSPM_PHONES("Phones", 0); | |
4588 | */ | |
4589 | }; | |
3cee5a60 | 4590 | |
0dca1793 AK |
4591 | static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = { |
4592 | HDSPM_MIXER("Mixer", 0), | |
4593 | HDSPM_INTERNAL_CLOCK("Internal Clock", 0), | |
4594 | HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0), | |
4595 | HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0), | |
4596 | HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), | |
4597 | HDSPM_SYNC_CHECK("WC SyncCheck", 0), | |
4598 | HDSPM_SYNC_CHECK("AES SyncCheck", 1), | |
4599 | HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2), | |
4600 | HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3), | |
4601 | HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4), | |
4602 | HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5), | |
4603 | HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6), | |
4604 | HDSPM_SYNC_CHECK("TCO SyncCheck", 7), | |
4605 | HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8), | |
4606 | HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), | |
4607 | HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1), | |
4608 | HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2), | |
4609 | HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3), | |
4610 | HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4), | |
4611 | HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5), | |
4612 | HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6), | |
4613 | HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7), | |
4614 | HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8) | |
4615 | }; | |
4616 | ||
4617 | static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = { | |
3cee5a60 | 4618 | HDSPM_MIXER("Mixer", 0), |
0dca1793 | 4619 | HDSPM_INTERNAL_CLOCK("Internal Clock", 0), |
3cee5a60 RB |
4620 | HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), |
4621 | HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), | |
4622 | HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), | |
4623 | HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), | |
3cee5a60 | 4624 | HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), |
0dca1793 AK |
4625 | HDSPM_SYNC_CHECK("WC Sync Check", 0), |
4626 | HDSPM_SYNC_CHECK("AES1 Sync Check", 1), | |
4627 | HDSPM_SYNC_CHECK("AES2 Sync Check", 2), | |
4628 | HDSPM_SYNC_CHECK("AES3 Sync Check", 3), | |
4629 | HDSPM_SYNC_CHECK("AES4 Sync Check", 4), | |
4630 | HDSPM_SYNC_CHECK("AES5 Sync Check", 5), | |
4631 | HDSPM_SYNC_CHECK("AES6 Sync Check", 6), | |
4632 | HDSPM_SYNC_CHECK("AES7 Sync Check", 7), | |
4633 | HDSPM_SYNC_CHECK("AES8 Sync Check", 8), | |
4634 | HDSPM_SYNC_CHECK("TCO Sync Check", 9), | |
4635 | HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10), | |
4636 | HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), | |
4637 | HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1), | |
4638 | HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2), | |
4639 | HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3), | |
4640 | HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4), | |
4641 | HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5), | |
4642 | HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6), | |
4643 | HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7), | |
4644 | HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8), | |
4645 | HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9), | |
4646 | HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10), | |
3cee5a60 RB |
4647 | HDSPM_LINE_OUT("Line Out", 0), |
4648 | HDSPM_EMPHASIS("Emphasis", 0), | |
4649 | HDSPM_DOLBY("Non Audio", 0), | |
4650 | HDSPM_PROFESSIONAL("Professional", 0), | |
4651 | HDSPM_C_TMS("Clear Track Marker", 0), | |
4652 | HDSPM_DS_WIRE("Double Speed Wire Mode", 0), | |
4653 | HDSPM_QS_WIRE("Quad Speed Wire Mode", 0), | |
4654 | }; | |
4655 | ||
0dca1793 AK |
4656 | |
4657 | ||
4658 | /* Control elements for the optional TCO module */ | |
4659 | static struct snd_kcontrol_new snd_hdspm_controls_tco[] = { | |
4660 | HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0), | |
4661 | HDSPM_TCO_PULL("TCO Pull", 0), | |
4662 | HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0), | |
4663 | HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0), | |
4664 | HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0), | |
4665 | HDSPM_TCO_WORD_TERM("TCO Word Term", 0) | |
4666 | }; | |
4667 | ||
4668 | ||
98274f07 | 4669 | static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER; |
763f356c TI |
4670 | |
4671 | ||
98274f07 | 4672 | static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm) |
763f356c TI |
4673 | { |
4674 | int i; | |
4675 | ||
0dca1793 | 4676 | for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) { |
763f356c TI |
4677 | if (hdspm->system_sample_rate > 48000) { |
4678 | hdspm->playback_mixer_ctls[i]->vd[0].access = | |
0dca1793 AK |
4679 | SNDRV_CTL_ELEM_ACCESS_INACTIVE | |
4680 | SNDRV_CTL_ELEM_ACCESS_READ | | |
4681 | SNDRV_CTL_ELEM_ACCESS_VOLATILE; | |
763f356c TI |
4682 | } else { |
4683 | hdspm->playback_mixer_ctls[i]->vd[0].access = | |
0dca1793 AK |
4684 | SNDRV_CTL_ELEM_ACCESS_READWRITE | |
4685 | SNDRV_CTL_ELEM_ACCESS_VOLATILE; | |
763f356c TI |
4686 | } |
4687 | snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE | | |
0dca1793 AK |
4688 | SNDRV_CTL_EVENT_MASK_INFO, |
4689 | &hdspm->playback_mixer_ctls[i]->id); | |
763f356c TI |
4690 | } |
4691 | ||
4692 | return 0; | |
4693 | } | |
4694 | ||
4695 | ||
0dca1793 AK |
4696 | static int snd_hdspm_create_controls(struct snd_card *card, |
4697 | struct hdspm *hdspm) | |
763f356c TI |
4698 | { |
4699 | unsigned int idx, limit; | |
4700 | int err; | |
98274f07 | 4701 | struct snd_kcontrol *kctl; |
0dca1793 | 4702 | struct snd_kcontrol_new *list = NULL; |
763f356c | 4703 | |
0dca1793 AK |
4704 | switch (hdspm->io_type) { |
4705 | case MADI: | |
4706 | list = snd_hdspm_controls_madi; | |
4707 | limit = ARRAY_SIZE(snd_hdspm_controls_madi); | |
4708 | break; | |
4709 | case MADIface: | |
4710 | list = snd_hdspm_controls_madiface; | |
4711 | limit = ARRAY_SIZE(snd_hdspm_controls_madiface); | |
4712 | break; | |
4713 | case AIO: | |
4714 | list = snd_hdspm_controls_aio; | |
4715 | limit = ARRAY_SIZE(snd_hdspm_controls_aio); | |
4716 | break; | |
4717 | case RayDAT: | |
4718 | list = snd_hdspm_controls_raydat; | |
4719 | limit = ARRAY_SIZE(snd_hdspm_controls_raydat); | |
4720 | break; | |
4721 | case AES32: | |
4722 | list = snd_hdspm_controls_aes32; | |
4723 | limit = ARRAY_SIZE(snd_hdspm_controls_aes32); | |
4724 | break; | |
4725 | } | |
3cee5a60 | 4726 | |
0dca1793 AK |
4727 | if (NULL != list) { |
4728 | for (idx = 0; idx < limit; idx++) { | |
3cee5a60 | 4729 | err = snd_ctl_add(card, |
0dca1793 | 4730 | snd_ctl_new1(&list[idx], hdspm)); |
3cee5a60 RB |
4731 | if (err < 0) |
4732 | return err; | |
763f356c TI |
4733 | } |
4734 | } | |
4735 | ||
763f356c | 4736 | |
0dca1793 | 4737 | /* create simple 1:1 playback mixer controls */ |
763f356c | 4738 | snd_hdspm_playback_mixer.name = "Chn"; |
0dca1793 AK |
4739 | if (hdspm->system_sample_rate >= 128000) { |
4740 | limit = hdspm->qs_out_channels; | |
4741 | } else if (hdspm->system_sample_rate >= 64000) { | |
4742 | limit = hdspm->ds_out_channels; | |
4743 | } else { | |
4744 | limit = hdspm->ss_out_channels; | |
4745 | } | |
763f356c TI |
4746 | for (idx = 0; idx < limit; ++idx) { |
4747 | snd_hdspm_playback_mixer.index = idx + 1; | |
ef5fa1a4 TI |
4748 | kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm); |
4749 | err = snd_ctl_add(card, kctl); | |
4750 | if (err < 0) | |
763f356c | 4751 | return err; |
763f356c TI |
4752 | hdspm->playback_mixer_ctls[idx] = kctl; |
4753 | } | |
4754 | ||
0dca1793 AK |
4755 | |
4756 | if (hdspm->tco) { | |
4757 | /* add tco control elements */ | |
4758 | list = snd_hdspm_controls_tco; | |
4759 | limit = ARRAY_SIZE(snd_hdspm_controls_tco); | |
4760 | for (idx = 0; idx < limit; idx++) { | |
4761 | err = snd_ctl_add(card, | |
4762 | snd_ctl_new1(&list[idx], hdspm)); | |
4763 | if (err < 0) | |
4764 | return err; | |
4765 | } | |
4766 | } | |
4767 | ||
763f356c TI |
4768 | return 0; |
4769 | } | |
4770 | ||
4771 | /*------------------------------------------------------------ | |
0dca1793 | 4772 | /proc interface |
763f356c TI |
4773 | ------------------------------------------------------------*/ |
4774 | ||
4775 | static void | |
3cee5a60 RB |
4776 | snd_hdspm_proc_read_madi(struct snd_info_entry * entry, |
4777 | struct snd_info_buffer *buffer) | |
763f356c | 4778 | { |
ef5fa1a4 | 4779 | struct hdspm *hdspm = entry->private_data; |
0dca1793 AK |
4780 | unsigned int status, status2, control, freq; |
4781 | ||
763f356c TI |
4782 | char *pref_sync_ref; |
4783 | char *autosync_ref; | |
4784 | char *system_clock_mode; | |
763f356c | 4785 | char *insel; |
763f356c TI |
4786 | int x, x2; |
4787 | ||
0dca1793 AK |
4788 | /* TCO stuff */ |
4789 | int a, ltc, frames, seconds, minutes, hours; | |
4790 | unsigned int period; | |
4791 | u64 freq_const = 0; | |
4792 | u32 rate; | |
4793 | ||
763f356c TI |
4794 | status = hdspm_read(hdspm, HDSPM_statusRegister); |
4795 | status2 = hdspm_read(hdspm, HDSPM_statusRegister2); | |
0dca1793 AK |
4796 | control = hdspm->control_register; |
4797 | freq = hdspm_read(hdspm, HDSPM_timecodeRegister); | |
763f356c TI |
4798 | |
4799 | snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n", | |
0dca1793 AK |
4800 | hdspm->card_name, hdspm->card->number + 1, |
4801 | hdspm->firmware_rev, | |
4802 | (status2 & HDSPM_version0) | | |
4803 | (status2 & HDSPM_version1) | (status2 & | |
4804 | HDSPM_version2)); | |
4805 | ||
4806 | snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n", | |
4807 | (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF, | |
7d53a631 | 4808 | hdspm->serial); |
763f356c TI |
4809 | |
4810 | snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", | |
0dca1793 | 4811 | hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); |
763f356c TI |
4812 | |
4813 | snd_iprintf(buffer, "--- System ---\n"); | |
4814 | ||
4815 | snd_iprintf(buffer, | |
0dca1793 AK |
4816 | "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", |
4817 | status & HDSPM_audioIRQPending, | |
4818 | (status & HDSPM_midi0IRQPending) ? 1 : 0, | |
4819 | (status & HDSPM_midi1IRQPending) ? 1 : 0, | |
4820 | hdspm->irq_count); | |
763f356c | 4821 | snd_iprintf(buffer, |
0dca1793 AK |
4822 | "HW pointer: id = %d, rawptr = %d (%d->%d) " |
4823 | "estimated= %ld (bytes)\n", | |
4824 | ((status & HDSPM_BufferID) ? 1 : 0), | |
4825 | (status & HDSPM_BufferPositionMask), | |
4826 | (status & HDSPM_BufferPositionMask) % | |
4827 | (2 * (int)hdspm->period_bytes), | |
4828 | ((status & HDSPM_BufferPositionMask) - 64) % | |
4829 | (2 * (int)hdspm->period_bytes), | |
4830 | (long) hdspm_hw_pointer(hdspm) * 4); | |
763f356c TI |
4831 | |
4832 | snd_iprintf(buffer, | |
0dca1793 AK |
4833 | "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", |
4834 | hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, | |
4835 | hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, | |
4836 | hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, | |
4837 | hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); | |
763f356c | 4838 | snd_iprintf(buffer, |
0dca1793 AK |
4839 | "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n", |
4840 | hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF, | |
4841 | hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF); | |
4842 | snd_iprintf(buffer, | |
4843 | "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, " | |
4844 | "status2=0x%x\n", | |
4845 | hdspm->control_register, hdspm->control2_register, | |
4846 | status, status2); | |
4847 | if (status & HDSPM_tco_detect) { | |
4848 | snd_iprintf(buffer, "TCO module detected.\n"); | |
4849 | a = hdspm_read(hdspm, HDSPM_RD_TCO+4); | |
4850 | if (a & HDSPM_TCO1_LTC_Input_valid) { | |
4851 | snd_iprintf(buffer, " LTC valid, "); | |
4852 | switch (a & (HDSPM_TCO1_LTC_Format_LSB | | |
4853 | HDSPM_TCO1_LTC_Format_MSB)) { | |
4854 | case 0: | |
4855 | snd_iprintf(buffer, "24 fps, "); | |
4856 | break; | |
4857 | case HDSPM_TCO1_LTC_Format_LSB: | |
4858 | snd_iprintf(buffer, "25 fps, "); | |
4859 | break; | |
4860 | case HDSPM_TCO1_LTC_Format_MSB: | |
4861 | snd_iprintf(buffer, "29.97 fps, "); | |
4862 | break; | |
4863 | default: | |
4864 | snd_iprintf(buffer, "30 fps, "); | |
4865 | break; | |
4866 | } | |
4867 | if (a & HDSPM_TCO1_set_drop_frame_flag) { | |
4868 | snd_iprintf(buffer, "drop frame\n"); | |
4869 | } else { | |
4870 | snd_iprintf(buffer, "full frame\n"); | |
4871 | } | |
4872 | } else { | |
4873 | snd_iprintf(buffer, " no LTC\n"); | |
4874 | } | |
4875 | if (a & HDSPM_TCO1_Video_Input_Format_NTSC) { | |
4876 | snd_iprintf(buffer, " Video: NTSC\n"); | |
4877 | } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) { | |
4878 | snd_iprintf(buffer, " Video: PAL\n"); | |
4879 | } else { | |
4880 | snd_iprintf(buffer, " No video\n"); | |
4881 | } | |
4882 | if (a & HDSPM_TCO1_TCO_lock) { | |
4883 | snd_iprintf(buffer, " Sync: lock\n"); | |
4884 | } else { | |
4885 | snd_iprintf(buffer, " Sync: no lock\n"); | |
4886 | } | |
4887 | ||
4888 | switch (hdspm->io_type) { | |
4889 | case MADI: | |
4890 | case AES32: | |
4891 | freq_const = 110069313433624ULL; | |
4892 | break; | |
4893 | case RayDAT: | |
4894 | case AIO: | |
4895 | freq_const = 104857600000000ULL; | |
4896 | break; | |
4897 | case MADIface: | |
4898 | break; /* no TCO possible */ | |
4899 | } | |
4900 | ||
4901 | period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); | |
4902 | snd_iprintf(buffer, " period: %u\n", period); | |
4903 | ||
4904 | ||
4905 | /* rate = freq_const/period; */ | |
4906 | rate = div_u64(freq_const, period); | |
4907 | ||
4908 | if (control & HDSPM_QuadSpeed) { | |
4909 | rate *= 4; | |
4910 | } else if (control & HDSPM_DoubleSpeed) { | |
4911 | rate *= 2; | |
4912 | } | |
4913 | ||
4914 | snd_iprintf(buffer, " Frequency: %u Hz\n", | |
4915 | (unsigned int) rate); | |
4916 | ||
4917 | ltc = hdspm_read(hdspm, HDSPM_RD_TCO); | |
4918 | frames = ltc & 0xF; | |
4919 | ltc >>= 4; | |
4920 | frames += (ltc & 0x3) * 10; | |
4921 | ltc >>= 4; | |
4922 | seconds = ltc & 0xF; | |
4923 | ltc >>= 4; | |
4924 | seconds += (ltc & 0x7) * 10; | |
4925 | ltc >>= 4; | |
4926 | minutes = ltc & 0xF; | |
4927 | ltc >>= 4; | |
4928 | minutes += (ltc & 0x7) * 10; | |
4929 | ltc >>= 4; | |
4930 | hours = ltc & 0xF; | |
4931 | ltc >>= 4; | |
4932 | hours += (ltc & 0x3) * 10; | |
4933 | snd_iprintf(buffer, | |
4934 | " LTC In: %02d:%02d:%02d:%02d\n", | |
4935 | hours, minutes, seconds, frames); | |
4936 | ||
4937 | } else { | |
4938 | snd_iprintf(buffer, "No TCO module detected.\n"); | |
4939 | } | |
763f356c TI |
4940 | |
4941 | snd_iprintf(buffer, "--- Settings ---\n"); | |
4942 | ||
7cb155ff | 4943 | x = hdspm_get_latency(hdspm); |
763f356c TI |
4944 | |
4945 | snd_iprintf(buffer, | |
0dca1793 AK |
4946 | "Size (Latency): %d samples (2 periods of %lu bytes)\n", |
4947 | x, (unsigned long) hdspm->period_bytes); | |
763f356c | 4948 | |
0dca1793 AK |
4949 | snd_iprintf(buffer, "Line out: %s\n", |
4950 | (hdspm->control_register & HDSPM_LineOut) ? "on " : "off"); | |
763f356c TI |
4951 | |
4952 | switch (hdspm->control_register & HDSPM_InputMask) { | |
4953 | case HDSPM_InputOptical: | |
4954 | insel = "Optical"; | |
4955 | break; | |
4956 | case HDSPM_InputCoaxial: | |
4957 | insel = "Coaxial"; | |
4958 | break; | |
4959 | default: | |
ec8f53fb | 4960 | insel = "Unknown"; |
763f356c | 4961 | } |
763f356c TI |
4962 | |
4963 | snd_iprintf(buffer, | |
0dca1793 AK |
4964 | "ClearTrackMarker = %s, Transmit in %s Channel Mode, " |
4965 | "Auto Input %s\n", | |
4966 | (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off", | |
4967 | (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56", | |
4968 | (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off"); | |
4969 | ||
763f356c | 4970 | |
3cee5a60 | 4971 | if (!(hdspm->control_register & HDSPM_ClockModeMaster)) |
0dca1793 | 4972 | system_clock_mode = "AutoSync"; |
3cee5a60 | 4973 | else |
763f356c | 4974 | system_clock_mode = "Master"; |
0dca1793 | 4975 | snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode); |
763f356c TI |
4976 | |
4977 | switch (hdspm_pref_sync_ref(hdspm)) { | |
4978 | case HDSPM_SYNC_FROM_WORD: | |
4979 | pref_sync_ref = "Word Clock"; | |
4980 | break; | |
4981 | case HDSPM_SYNC_FROM_MADI: | |
4982 | pref_sync_ref = "MADI Sync"; | |
4983 | break; | |
0dca1793 AK |
4984 | case HDSPM_SYNC_FROM_TCO: |
4985 | pref_sync_ref = "TCO"; | |
4986 | break; | |
4987 | case HDSPM_SYNC_FROM_SYNC_IN: | |
4988 | pref_sync_ref = "Sync In"; | |
4989 | break; | |
763f356c TI |
4990 | default: |
4991 | pref_sync_ref = "XXXX Clock"; | |
4992 | break; | |
4993 | } | |
4994 | snd_iprintf(buffer, "Preferred Sync Reference: %s\n", | |
0dca1793 | 4995 | pref_sync_ref); |
763f356c TI |
4996 | |
4997 | snd_iprintf(buffer, "System Clock Frequency: %d\n", | |
0dca1793 | 4998 | hdspm->system_sample_rate); |
763f356c TI |
4999 | |
5000 | ||
5001 | snd_iprintf(buffer, "--- Status:\n"); | |
5002 | ||
5003 | x = status & HDSPM_madiSync; | |
5004 | x2 = status2 & HDSPM_wcSync; | |
5005 | ||
5006 | snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n", | |
0dca1793 AK |
5007 | (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") : |
5008 | "NoLock", | |
5009 | (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") : | |
5010 | "NoLock"); | |
763f356c TI |
5011 | |
5012 | switch (hdspm_autosync_ref(hdspm)) { | |
0dca1793 AK |
5013 | case HDSPM_AUTOSYNC_FROM_SYNC_IN: |
5014 | autosync_ref = "Sync In"; | |
5015 | break; | |
5016 | case HDSPM_AUTOSYNC_FROM_TCO: | |
5017 | autosync_ref = "TCO"; | |
5018 | break; | |
763f356c TI |
5019 | case HDSPM_AUTOSYNC_FROM_WORD: |
5020 | autosync_ref = "Word Clock"; | |
5021 | break; | |
5022 | case HDSPM_AUTOSYNC_FROM_MADI: | |
5023 | autosync_ref = "MADI Sync"; | |
5024 | break; | |
5025 | case HDSPM_AUTOSYNC_FROM_NONE: | |
5026 | autosync_ref = "Input not valid"; | |
5027 | break; | |
5028 | default: | |
5029 | autosync_ref = "---"; | |
5030 | break; | |
5031 | } | |
5032 | snd_iprintf(buffer, | |
0dca1793 AK |
5033 | "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n", |
5034 | autosync_ref, hdspm_external_sample_rate(hdspm), | |
5035 | (status & HDSPM_madiFreqMask) >> 22, | |
5036 | (status2 & HDSPM_wcFreqMask) >> 5); | |
763f356c TI |
5037 | |
5038 | snd_iprintf(buffer, "Input: %s, Mode=%s\n", | |
0dca1793 AK |
5039 | (status & HDSPM_AB_int) ? "Coax" : "Optical", |
5040 | (status & HDSPM_RX_64ch) ? "64 channels" : | |
5041 | "56 channels"); | |
763f356c TI |
5042 | |
5043 | snd_iprintf(buffer, "\n"); | |
5044 | } | |
5045 | ||
3cee5a60 RB |
5046 | static void |
5047 | snd_hdspm_proc_read_aes32(struct snd_info_entry * entry, | |
5048 | struct snd_info_buffer *buffer) | |
5049 | { | |
ef5fa1a4 | 5050 | struct hdspm *hdspm = entry->private_data; |
3cee5a60 RB |
5051 | unsigned int status; |
5052 | unsigned int status2; | |
5053 | unsigned int timecode; | |
5054 | int pref_syncref; | |
5055 | char *autosync_ref; | |
3cee5a60 RB |
5056 | int x; |
5057 | ||
5058 | status = hdspm_read(hdspm, HDSPM_statusRegister); | |
5059 | status2 = hdspm_read(hdspm, HDSPM_statusRegister2); | |
5060 | timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); | |
5061 | ||
5062 | snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n", | |
5063 | hdspm->card_name, hdspm->card->number + 1, | |
5064 | hdspm->firmware_rev); | |
5065 | ||
5066 | snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", | |
5067 | hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); | |
5068 | ||
5069 | snd_iprintf(buffer, "--- System ---\n"); | |
5070 | ||
5071 | snd_iprintf(buffer, | |
5072 | "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", | |
5073 | status & HDSPM_audioIRQPending, | |
5074 | (status & HDSPM_midi0IRQPending) ? 1 : 0, | |
5075 | (status & HDSPM_midi1IRQPending) ? 1 : 0, | |
5076 | hdspm->irq_count); | |
5077 | snd_iprintf(buffer, | |
ef5fa1a4 TI |
5078 | "HW pointer: id = %d, rawptr = %d (%d->%d) " |
5079 | "estimated= %ld (bytes)\n", | |
3cee5a60 RB |
5080 | ((status & HDSPM_BufferID) ? 1 : 0), |
5081 | (status & HDSPM_BufferPositionMask), | |
ef5fa1a4 TI |
5082 | (status & HDSPM_BufferPositionMask) % |
5083 | (2 * (int)hdspm->period_bytes), | |
5084 | ((status & HDSPM_BufferPositionMask) - 64) % | |
5085 | (2 * (int)hdspm->period_bytes), | |
3cee5a60 RB |
5086 | (long) hdspm_hw_pointer(hdspm) * 4); |
5087 | ||
5088 | snd_iprintf(buffer, | |
5089 | "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", | |
5090 | hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, | |
5091 | hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, | |
5092 | hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, | |
5093 | hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); | |
5094 | snd_iprintf(buffer, | |
0dca1793 AK |
5095 | "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n", |
5096 | hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF, | |
5097 | hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF); | |
5098 | snd_iprintf(buffer, | |
5099 | "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, " | |
5100 | "status2=0x%x\n", | |
5101 | hdspm->control_register, hdspm->control2_register, | |
5102 | status, status2); | |
3cee5a60 RB |
5103 | |
5104 | snd_iprintf(buffer, "--- Settings ---\n"); | |
5105 | ||
7cb155ff | 5106 | x = hdspm_get_latency(hdspm); |
3cee5a60 RB |
5107 | |
5108 | snd_iprintf(buffer, | |
5109 | "Size (Latency): %d samples (2 periods of %lu bytes)\n", | |
5110 | x, (unsigned long) hdspm->period_bytes); | |
5111 | ||
0dca1793 | 5112 | snd_iprintf(buffer, "Line out: %s\n", |
3cee5a60 | 5113 | (hdspm-> |
0dca1793 | 5114 | control_register & HDSPM_LineOut) ? "on " : "off"); |
3cee5a60 RB |
5115 | |
5116 | snd_iprintf(buffer, | |
5117 | "ClearTrackMarker %s, Emphasis %s, Dolby %s\n", | |
5118 | (hdspm-> | |
5119 | control_register & HDSPM_clr_tms) ? "on" : "off", | |
5120 | (hdspm-> | |
5121 | control_register & HDSPM_Emphasis) ? "on" : "off", | |
5122 | (hdspm-> | |
5123 | control_register & HDSPM_Dolby) ? "on" : "off"); | |
5124 | ||
3cee5a60 RB |
5125 | |
5126 | pref_syncref = hdspm_pref_sync_ref(hdspm); | |
5127 | if (pref_syncref == 0) | |
5128 | snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n"); | |
5129 | else | |
5130 | snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n", | |
5131 | pref_syncref); | |
5132 | ||
5133 | snd_iprintf(buffer, "System Clock Frequency: %d\n", | |
5134 | hdspm->system_sample_rate); | |
5135 | ||
5136 | snd_iprintf(buffer, "Double speed: %s\n", | |
5137 | hdspm->control_register & HDSPM_DS_DoubleWire? | |
5138 | "Double wire" : "Single wire"); | |
5139 | snd_iprintf(buffer, "Quad speed: %s\n", | |
5140 | hdspm->control_register & HDSPM_QS_DoubleWire? | |
5141 | "Double wire" : | |
5142 | hdspm->control_register & HDSPM_QS_QuadWire? | |
5143 | "Quad wire" : "Single wire"); | |
5144 | ||
5145 | snd_iprintf(buffer, "--- Status:\n"); | |
5146 | ||
5147 | snd_iprintf(buffer, "Word: %s Frequency: %d\n", | |
0dca1793 | 5148 | (status & HDSPM_AES32_wcLock) ? "Sync " : "No Lock", |
ef5fa1a4 | 5149 | HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF)); |
3cee5a60 RB |
5150 | |
5151 | for (x = 0; x < 8; x++) { | |
5152 | snd_iprintf(buffer, "AES%d: %s Frequency: %d\n", | |
ef5fa1a4 TI |
5153 | x+1, |
5154 | (status2 & (HDSPM_LockAES >> x)) ? | |
0dca1793 | 5155 | "Sync " : "No Lock", |
ef5fa1a4 | 5156 | HDSPM_bit2freq((timecode >> (4*x)) & 0xF)); |
3cee5a60 RB |
5157 | } |
5158 | ||
5159 | switch (hdspm_autosync_ref(hdspm)) { | |
0dca1793 AK |
5160 | case HDSPM_AES32_AUTOSYNC_FROM_NONE: |
5161 | autosync_ref = "None"; break; | |
5162 | case HDSPM_AES32_AUTOSYNC_FROM_WORD: | |
5163 | autosync_ref = "Word Clock"; break; | |
5164 | case HDSPM_AES32_AUTOSYNC_FROM_AES1: | |
5165 | autosync_ref = "AES1"; break; | |
5166 | case HDSPM_AES32_AUTOSYNC_FROM_AES2: | |
5167 | autosync_ref = "AES2"; break; | |
5168 | case HDSPM_AES32_AUTOSYNC_FROM_AES3: | |
5169 | autosync_ref = "AES3"; break; | |
5170 | case HDSPM_AES32_AUTOSYNC_FROM_AES4: | |
5171 | autosync_ref = "AES4"; break; | |
5172 | case HDSPM_AES32_AUTOSYNC_FROM_AES5: | |
5173 | autosync_ref = "AES5"; break; | |
5174 | case HDSPM_AES32_AUTOSYNC_FROM_AES6: | |
5175 | autosync_ref = "AES6"; break; | |
5176 | case HDSPM_AES32_AUTOSYNC_FROM_AES7: | |
5177 | autosync_ref = "AES7"; break; | |
5178 | case HDSPM_AES32_AUTOSYNC_FROM_AES8: | |
5179 | autosync_ref = "AES8"; break; | |
5180 | default: | |
5181 | autosync_ref = "---"; break; | |
3cee5a60 RB |
5182 | } |
5183 | snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref); | |
5184 | ||
5185 | snd_iprintf(buffer, "\n"); | |
5186 | } | |
5187 | ||
0dca1793 AK |
5188 | static void |
5189 | snd_hdspm_proc_read_raydat(struct snd_info_entry *entry, | |
5190 | struct snd_info_buffer *buffer) | |
5191 | { | |
5192 | struct hdspm *hdspm = entry->private_data; | |
5193 | unsigned int status1, status2, status3, control, i; | |
5194 | unsigned int lock, sync; | |
5195 | ||
5196 | status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */ | |
5197 | status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */ | |
5198 | status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */ | |
5199 | ||
5200 | control = hdspm->control_register; | |
5201 | ||
5202 | snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1); | |
5203 | snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2); | |
5204 | snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3); | |
5205 | ||
5206 | ||
5207 | snd_iprintf(buffer, "\n*** CLOCK MODE\n\n"); | |
5208 | ||
5209 | snd_iprintf(buffer, "Clock mode : %s\n", | |
5210 | (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave"); | |
5211 | snd_iprintf(buffer, "System frequency: %d Hz\n", | |
5212 | hdspm_get_system_sample_rate(hdspm)); | |
5213 | ||
5214 | snd_iprintf(buffer, "\n*** INPUT STATUS\n\n"); | |
5215 | ||
5216 | lock = 0x1; | |
5217 | sync = 0x100; | |
5218 | ||
5219 | for (i = 0; i < 8; i++) { | |
5220 | snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n", | |
5221 | i, | |
5222 | (status1 & lock) ? 1 : 0, | |
5223 | (status1 & sync) ? 1 : 0, | |
5224 | texts_freq[(status2 >> (i * 4)) & 0xF]); | |
5225 | ||
5226 | lock = lock<<1; | |
5227 | sync = sync<<1; | |
5228 | } | |
5229 | ||
5230 | snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n", | |
5231 | (status1 & 0x1000000) ? 1 : 0, | |
5232 | (status1 & 0x2000000) ? 1 : 0, | |
5233 | texts_freq[(status1 >> 16) & 0xF]); | |
5234 | ||
5235 | snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n", | |
5236 | (status1 & 0x4000000) ? 1 : 0, | |
5237 | (status1 & 0x8000000) ? 1 : 0, | |
5238 | texts_freq[(status1 >> 20) & 0xF]); | |
5239 | ||
5240 | snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n", | |
5241 | (status3 & 0x400) ? 1 : 0, | |
5242 | (status3 & 0x800) ? 1 : 0, | |
5243 | texts_freq[(status2 >> 12) & 0xF]); | |
5244 | ||
5245 | } | |
5246 | ||
3cee5a60 RB |
5247 | #ifdef CONFIG_SND_DEBUG |
5248 | static void | |
0dca1793 | 5249 | snd_hdspm_proc_read_debug(struct snd_info_entry *entry, |
3cee5a60 RB |
5250 | struct snd_info_buffer *buffer) |
5251 | { | |
ef5fa1a4 | 5252 | struct hdspm *hdspm = entry->private_data; |
3cee5a60 RB |
5253 | |
5254 | int j,i; | |
5255 | ||
ef5fa1a4 | 5256 | for (i = 0; i < 256 /* 1024*64 */; i += j) { |
3cee5a60 RB |
5257 | snd_iprintf(buffer, "0x%08X: ", i); |
5258 | for (j = 0; j < 16; j += 4) | |
5259 | snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j)); | |
5260 | snd_iprintf(buffer, "\n"); | |
5261 | } | |
5262 | } | |
5263 | #endif | |
5264 | ||
5265 | ||
0dca1793 AK |
5266 | static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry, |
5267 | struct snd_info_buffer *buffer) | |
5268 | { | |
5269 | struct hdspm *hdspm = entry->private_data; | |
5270 | int i; | |
5271 | ||
5272 | snd_iprintf(buffer, "# generated by hdspm\n"); | |
5273 | ||
5274 | for (i = 0; i < hdspm->max_channels_in; i++) { | |
5275 | snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]); | |
5276 | } | |
5277 | } | |
5278 | ||
5279 | static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry, | |
5280 | struct snd_info_buffer *buffer) | |
5281 | { | |
5282 | struct hdspm *hdspm = entry->private_data; | |
5283 | int i; | |
5284 | ||
5285 | snd_iprintf(buffer, "# generated by hdspm\n"); | |
5286 | ||
5287 | for (i = 0; i < hdspm->max_channels_out; i++) { | |
5288 | snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]); | |
5289 | } | |
5290 | } | |
5291 | ||
3cee5a60 | 5292 | |
0dca1793 | 5293 | static void __devinit snd_hdspm_proc_init(struct hdspm *hdspm) |
763f356c | 5294 | { |
98274f07 | 5295 | struct snd_info_entry *entry; |
763f356c | 5296 | |
0dca1793 AK |
5297 | if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) { |
5298 | switch (hdspm->io_type) { | |
5299 | case AES32: | |
5300 | snd_info_set_text_ops(entry, hdspm, | |
5301 | snd_hdspm_proc_read_aes32); | |
5302 | break; | |
5303 | case MADI: | |
5304 | snd_info_set_text_ops(entry, hdspm, | |
5305 | snd_hdspm_proc_read_madi); | |
5306 | break; | |
5307 | case MADIface: | |
5308 | /* snd_info_set_text_ops(entry, hdspm, | |
5309 | snd_hdspm_proc_read_madiface); */ | |
5310 | break; | |
5311 | case RayDAT: | |
5312 | snd_info_set_text_ops(entry, hdspm, | |
5313 | snd_hdspm_proc_read_raydat); | |
5314 | break; | |
5315 | case AIO: | |
5316 | break; | |
5317 | } | |
5318 | } | |
5319 | ||
5320 | if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) { | |
5321 | snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in); | |
5322 | } | |
5323 | ||
5324 | if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) { | |
5325 | snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out); | |
5326 | } | |
5327 | ||
3cee5a60 RB |
5328 | #ifdef CONFIG_SND_DEBUG |
5329 | /* debug file to read all hdspm registers */ | |
5330 | if (!snd_card_proc_new(hdspm->card, "debug", &entry)) | |
5331 | snd_info_set_text_ops(entry, hdspm, | |
5332 | snd_hdspm_proc_read_debug); | |
5333 | #endif | |
763f356c TI |
5334 | } |
5335 | ||
5336 | /*------------------------------------------------------------ | |
0dca1793 | 5337 | hdspm intitialize |
763f356c TI |
5338 | ------------------------------------------------------------*/ |
5339 | ||
98274f07 | 5340 | static int snd_hdspm_set_defaults(struct hdspm * hdspm) |
763f356c | 5341 | { |
763f356c | 5342 | /* ASSUMPTION: hdspm->lock is either held, or there is no need to |
561de31a | 5343 | hold it (e.g. during module initialization). |
0dca1793 | 5344 | */ |
763f356c TI |
5345 | |
5346 | /* set defaults: */ | |
5347 | ||
0dca1793 AK |
5348 | hdspm->settings_register = 0; |
5349 | ||
5350 | switch (hdspm->io_type) { | |
5351 | case MADI: | |
5352 | case MADIface: | |
5353 | hdspm->control_register = | |
5354 | 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000; | |
5355 | break; | |
5356 | ||
5357 | case RayDAT: | |
5358 | case AIO: | |
5359 | hdspm->settings_register = 0x1 + 0x1000; | |
5360 | /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0, | |
5361 | * line_out */ | |
5362 | hdspm->control_register = | |
5363 | 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000; | |
5364 | break; | |
5365 | ||
5366 | case AES32: | |
ef5fa1a4 TI |
5367 | hdspm->control_register = |
5368 | HDSPM_ClockModeMaster | /* Master Cloack Mode on */ | |
0dca1793 | 5369 | hdspm_encode_latency(7) | /* latency max=8192samples */ |
3cee5a60 RB |
5370 | HDSPM_SyncRef0 | /* AES1 is syncclock */ |
5371 | HDSPM_LineOut | /* Analog output in */ | |
5372 | HDSPM_Professional; /* Professional mode */ | |
0dca1793 AK |
5373 | break; |
5374 | } | |
763f356c TI |
5375 | |
5376 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
5377 | ||
0dca1793 | 5378 | if (AES32 == hdspm->io_type) { |
ffb2c3c0 | 5379 | /* No control2 register for AES32 */ |
763f356c | 5380 | #ifdef SNDRV_BIG_ENDIAN |
ffb2c3c0 | 5381 | hdspm->control2_register = HDSPM_BIGENDIAN_MODE; |
763f356c | 5382 | #else |
ffb2c3c0 | 5383 | hdspm->control2_register = 0; |
763f356c TI |
5384 | #endif |
5385 | ||
ffb2c3c0 RB |
5386 | hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register); |
5387 | } | |
763f356c TI |
5388 | hdspm_compute_period_size(hdspm); |
5389 | ||
5390 | /* silence everything */ | |
5391 | ||
5392 | all_in_all_mixer(hdspm, 0 * UNITY_GAIN); | |
5393 | ||
0dca1793 AK |
5394 | if (hdspm->io_type == AIO || hdspm->io_type == RayDAT) { |
5395 | hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); | |
763f356c TI |
5396 | } |
5397 | ||
5398 | /* set a default rate so that the channel map is set up. */ | |
0dca1793 | 5399 | hdspm_set_rate(hdspm, 48000, 1); |
763f356c TI |
5400 | |
5401 | return 0; | |
5402 | } | |
5403 | ||
5404 | ||
5405 | /*------------------------------------------------------------ | |
0dca1793 | 5406 | interrupt |
763f356c TI |
5407 | ------------------------------------------------------------*/ |
5408 | ||
7d12e780 | 5409 | static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id) |
763f356c | 5410 | { |
98274f07 | 5411 | struct hdspm *hdspm = (struct hdspm *) dev_id; |
763f356c | 5412 | unsigned int status; |
0dca1793 AK |
5413 | int i, audio, midi, schedule = 0; |
5414 | /* cycles_t now; */ | |
763f356c TI |
5415 | |
5416 | status = hdspm_read(hdspm, HDSPM_statusRegister); | |
5417 | ||
5418 | audio = status & HDSPM_audioIRQPending; | |
0dca1793 AK |
5419 | midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending | |
5420 | HDSPM_midi2IRQPending | HDSPM_midi3IRQPending); | |
5421 | ||
5422 | /* now = get_cycles(); */ | |
5423 | /** | |
5424 | * LAT_2..LAT_0 period counter (win) counter (mac) | |
5425 | * 6 4096 ~256053425 ~514672358 | |
5426 | * 5 2048 ~128024983 ~257373821 | |
5427 | * 4 1024 ~64023706 ~128718089 | |
5428 | * 3 512 ~32005945 ~64385999 | |
5429 | * 2 256 ~16003039 ~32260176 | |
5430 | * 1 128 ~7998738 ~16194507 | |
5431 | * 0 64 ~3998231 ~8191558 | |
5432 | **/ | |
5433 | /* | |
5434 | snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n", | |
5435 | now-hdspm->last_interrupt, status & 0xFFC0); | |
5436 | hdspm->last_interrupt = now; | |
5437 | */ | |
763f356c | 5438 | |
0dca1793 | 5439 | if (!audio && !midi) |
763f356c TI |
5440 | return IRQ_NONE; |
5441 | ||
5442 | hdspm_write(hdspm, HDSPM_interruptConfirmation, 0); | |
5443 | hdspm->irq_count++; | |
5444 | ||
763f356c TI |
5445 | |
5446 | if (audio) { | |
763f356c | 5447 | if (hdspm->capture_substream) |
ef5fa1a4 | 5448 | snd_pcm_period_elapsed(hdspm->capture_substream); |
763f356c TI |
5449 | |
5450 | if (hdspm->playback_substream) | |
ef5fa1a4 | 5451 | snd_pcm_period_elapsed(hdspm->playback_substream); |
763f356c TI |
5452 | } |
5453 | ||
0dca1793 AK |
5454 | if (midi) { |
5455 | i = 0; | |
5456 | while (i < hdspm->midiPorts) { | |
5457 | if ((hdspm_read(hdspm, | |
5458 | hdspm->midi[i].statusIn) & 0xff) && | |
5459 | (status & hdspm->midi[i].irq)) { | |
5460 | /* we disable interrupts for this input until | |
5461 | * processing is done | |
5462 | */ | |
5463 | hdspm->control_register &= ~hdspm->midi[i].ie; | |
5464 | hdspm_write(hdspm, HDSPM_controlRegister, | |
5465 | hdspm->control_register); | |
5466 | hdspm->midi[i].pending = 1; | |
5467 | schedule = 1; | |
5468 | } | |
5469 | ||
5470 | i++; | |
5471 | } | |
5472 | ||
5473 | if (schedule) | |
5474 | tasklet_hi_schedule(&hdspm->midi_tasklet); | |
763f356c | 5475 | } |
0dca1793 | 5476 | |
763f356c TI |
5477 | return IRQ_HANDLED; |
5478 | } | |
5479 | ||
5480 | /*------------------------------------------------------------ | |
0dca1793 | 5481 | pcm interface |
763f356c TI |
5482 | ------------------------------------------------------------*/ |
5483 | ||
5484 | ||
0dca1793 AK |
5485 | static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream |
5486 | *substream) | |
763f356c | 5487 | { |
98274f07 | 5488 | struct hdspm *hdspm = snd_pcm_substream_chip(substream); |
763f356c TI |
5489 | return hdspm_hw_pointer(hdspm); |
5490 | } | |
5491 | ||
763f356c | 5492 | |
98274f07 | 5493 | static int snd_hdspm_reset(struct snd_pcm_substream *substream) |
763f356c | 5494 | { |
98274f07 TI |
5495 | struct snd_pcm_runtime *runtime = substream->runtime; |
5496 | struct hdspm *hdspm = snd_pcm_substream_chip(substream); | |
5497 | struct snd_pcm_substream *other; | |
763f356c TI |
5498 | |
5499 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
5500 | other = hdspm->capture_substream; | |
5501 | else | |
5502 | other = hdspm->playback_substream; | |
5503 | ||
5504 | if (hdspm->running) | |
5505 | runtime->status->hw_ptr = hdspm_hw_pointer(hdspm); | |
5506 | else | |
5507 | runtime->status->hw_ptr = 0; | |
5508 | if (other) { | |
98274f07 TI |
5509 | struct snd_pcm_substream *s; |
5510 | struct snd_pcm_runtime *oruntime = other->runtime; | |
ef991b95 | 5511 | snd_pcm_group_for_each_entry(s, substream) { |
763f356c TI |
5512 | if (s == other) { |
5513 | oruntime->status->hw_ptr = | |
0dca1793 | 5514 | runtime->status->hw_ptr; |
763f356c TI |
5515 | break; |
5516 | } | |
5517 | } | |
5518 | } | |
5519 | return 0; | |
5520 | } | |
5521 | ||
98274f07 TI |
5522 | static int snd_hdspm_hw_params(struct snd_pcm_substream *substream, |
5523 | struct snd_pcm_hw_params *params) | |
763f356c | 5524 | { |
98274f07 | 5525 | struct hdspm *hdspm = snd_pcm_substream_chip(substream); |
763f356c TI |
5526 | int err; |
5527 | int i; | |
5528 | pid_t this_pid; | |
5529 | pid_t other_pid; | |
763f356c TI |
5530 | |
5531 | spin_lock_irq(&hdspm->lock); | |
5532 | ||
5533 | if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
5534 | this_pid = hdspm->playback_pid; | |
5535 | other_pid = hdspm->capture_pid; | |
5536 | } else { | |
5537 | this_pid = hdspm->capture_pid; | |
5538 | other_pid = hdspm->playback_pid; | |
5539 | } | |
5540 | ||
ef5fa1a4 | 5541 | if (other_pid > 0 && this_pid != other_pid) { |
763f356c TI |
5542 | |
5543 | /* The other stream is open, and not by the same | |
5544 | task as this one. Make sure that the parameters | |
5545 | that matter are the same. | |
0dca1793 | 5546 | */ |
763f356c TI |
5547 | |
5548 | if (params_rate(params) != hdspm->system_sample_rate) { | |
5549 | spin_unlock_irq(&hdspm->lock); | |
5550 | _snd_pcm_hw_param_setempty(params, | |
0dca1793 | 5551 | SNDRV_PCM_HW_PARAM_RATE); |
763f356c TI |
5552 | return -EBUSY; |
5553 | } | |
5554 | ||
5555 | if (params_period_size(params) != hdspm->period_bytes / 4) { | |
5556 | spin_unlock_irq(&hdspm->lock); | |
5557 | _snd_pcm_hw_param_setempty(params, | |
0dca1793 | 5558 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE); |
763f356c TI |
5559 | return -EBUSY; |
5560 | } | |
5561 | ||
5562 | } | |
5563 | /* We're fine. */ | |
5564 | spin_unlock_irq(&hdspm->lock); | |
5565 | ||
5566 | /* how to make sure that the rate matches an externally-set one ? */ | |
5567 | ||
5568 | spin_lock_irq(&hdspm->lock); | |
ef5fa1a4 TI |
5569 | err = hdspm_set_rate(hdspm, params_rate(params), 0); |
5570 | if (err < 0) { | |
0dca1793 | 5571 | snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err); |
763f356c TI |
5572 | spin_unlock_irq(&hdspm->lock); |
5573 | _snd_pcm_hw_param_setempty(params, | |
0dca1793 | 5574 | SNDRV_PCM_HW_PARAM_RATE); |
763f356c TI |
5575 | return err; |
5576 | } | |
5577 | spin_unlock_irq(&hdspm->lock); | |
5578 | ||
ef5fa1a4 | 5579 | err = hdspm_set_interrupt_interval(hdspm, |
0dca1793 | 5580 | params_period_size(params)); |
ef5fa1a4 | 5581 | if (err < 0) { |
0dca1793 | 5582 | snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err); |
763f356c | 5583 | _snd_pcm_hw_param_setempty(params, |
0dca1793 | 5584 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE); |
763f356c TI |
5585 | return err; |
5586 | } | |
5587 | ||
ef5fa1a4 TI |
5588 | /* Memory allocation, takashi's method, dont know if we should |
5589 | * spinlock | |
5590 | */ | |
763f356c | 5591 | /* malloc all buffer even if not enabled to get sure */ |
ffb2c3c0 RB |
5592 | /* Update for MADI rev 204: we need to allocate for all channels, |
5593 | * otherwise it doesn't work at 96kHz */ | |
0dca1793 | 5594 | |
763f356c | 5595 | err = |
0dca1793 AK |
5596 | snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES); |
5597 | if (err < 0) { | |
5598 | snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err); | |
763f356c | 5599 | return err; |
0dca1793 | 5600 | } |
763f356c | 5601 | |
763f356c TI |
5602 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
5603 | ||
77a23f26 | 5604 | hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut, |
763f356c TI |
5605 | params_channels(params)); |
5606 | ||
5607 | for (i = 0; i < params_channels(params); ++i) | |
5608 | snd_hdspm_enable_out(hdspm, i, 1); | |
5609 | ||
5610 | hdspm->playback_buffer = | |
0dca1793 | 5611 | (unsigned char *) substream->runtime->dma_area; |
54bf5dd9 | 5612 | snd_printdd("Allocated sample buffer for playback at %p\n", |
3cee5a60 | 5613 | hdspm->playback_buffer); |
763f356c | 5614 | } else { |
77a23f26 | 5615 | hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn, |
763f356c TI |
5616 | params_channels(params)); |
5617 | ||
5618 | for (i = 0; i < params_channels(params); ++i) | |
5619 | snd_hdspm_enable_in(hdspm, i, 1); | |
5620 | ||
5621 | hdspm->capture_buffer = | |
0dca1793 | 5622 | (unsigned char *) substream->runtime->dma_area; |
54bf5dd9 | 5623 | snd_printdd("Allocated sample buffer for capture at %p\n", |
3cee5a60 | 5624 | hdspm->capture_buffer); |
763f356c | 5625 | } |
0dca1793 | 5626 | |
3cee5a60 RB |
5627 | /* |
5628 | snd_printdd("Allocated sample buffer for %s at 0x%08X\n", | |
5629 | substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? | |
5630 | "playback" : "capture", | |
77a23f26 | 5631 | snd_pcm_sgbuf_get_addr(substream, 0)); |
0dca1793 | 5632 | */ |
ffb2c3c0 | 5633 | /* |
0dca1793 AK |
5634 | snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n", |
5635 | substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? | |
5636 | "playback" : "capture", | |
5637 | params_rate(params), params_channels(params), | |
5638 | params_buffer_size(params)); | |
5639 | */ | |
5640 | ||
5641 | ||
5642 | /* Switch to native float format if requested */ | |
5643 | if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) { | |
5644 | if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT)) | |
5645 | snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n"); | |
5646 | ||
5647 | hdspm->control_register |= HDSPe_FLOAT_FORMAT; | |
5648 | } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) { | |
5649 | if (hdspm->control_register & HDSPe_FLOAT_FORMAT) | |
5650 | snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n"); | |
5651 | ||
5652 | hdspm->control_register &= ~HDSPe_FLOAT_FORMAT; | |
5653 | } | |
5654 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
5655 | ||
763f356c TI |
5656 | return 0; |
5657 | } | |
5658 | ||
98274f07 | 5659 | static int snd_hdspm_hw_free(struct snd_pcm_substream *substream) |
763f356c TI |
5660 | { |
5661 | int i; | |
98274f07 | 5662 | struct hdspm *hdspm = snd_pcm_substream_chip(substream); |
763f356c TI |
5663 | |
5664 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
5665 | ||
0dca1793 | 5666 | /* params_channels(params) should be enough, |
763f356c | 5667 | but to get sure in case of error */ |
0dca1793 | 5668 | for (i = 0; i < hdspm->max_channels_out; ++i) |
763f356c TI |
5669 | snd_hdspm_enable_out(hdspm, i, 0); |
5670 | ||
5671 | hdspm->playback_buffer = NULL; | |
5672 | } else { | |
0dca1793 | 5673 | for (i = 0; i < hdspm->max_channels_in; ++i) |
763f356c TI |
5674 | snd_hdspm_enable_in(hdspm, i, 0); |
5675 | ||
5676 | hdspm->capture_buffer = NULL; | |
5677 | ||
5678 | } | |
5679 | ||
5680 | snd_pcm_lib_free_pages(substream); | |
5681 | ||
5682 | return 0; | |
5683 | } | |
5684 | ||
0dca1793 | 5685 | |
98274f07 | 5686 | static int snd_hdspm_channel_info(struct snd_pcm_substream *substream, |
0dca1793 | 5687 | struct snd_pcm_channel_info *info) |
763f356c | 5688 | { |
98274f07 | 5689 | struct hdspm *hdspm = snd_pcm_substream_chip(substream); |
763f356c | 5690 | |
0dca1793 AK |
5691 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
5692 | if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) { | |
5693 | snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel); | |
5694 | return -EINVAL; | |
5695 | } | |
763f356c | 5696 | |
0dca1793 AK |
5697 | if (hdspm->channel_map_out[info->channel] < 0) { |
5698 | snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel); | |
5699 | return -EINVAL; | |
5700 | } | |
5701 | ||
5702 | info->offset = hdspm->channel_map_out[info->channel] * | |
5703 | HDSPM_CHANNEL_BUFFER_BYTES; | |
5704 | } else { | |
5705 | if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) { | |
5706 | snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel); | |
5707 | return -EINVAL; | |
5708 | } | |
5709 | ||
5710 | if (hdspm->channel_map_in[info->channel] < 0) { | |
5711 | snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel); | |
5712 | return -EINVAL; | |
5713 | } | |
5714 | ||
5715 | info->offset = hdspm->channel_map_in[info->channel] * | |
5716 | HDSPM_CHANNEL_BUFFER_BYTES; | |
5717 | } | |
763f356c | 5718 | |
763f356c TI |
5719 | info->first = 0; |
5720 | info->step = 32; | |
5721 | return 0; | |
5722 | } | |
5723 | ||
0dca1793 | 5724 | |
98274f07 | 5725 | static int snd_hdspm_ioctl(struct snd_pcm_substream *substream, |
0dca1793 | 5726 | unsigned int cmd, void *arg) |
763f356c TI |
5727 | { |
5728 | switch (cmd) { | |
5729 | case SNDRV_PCM_IOCTL1_RESET: | |
ef5fa1a4 | 5730 | return snd_hdspm_reset(substream); |
763f356c TI |
5731 | |
5732 | case SNDRV_PCM_IOCTL1_CHANNEL_INFO: | |
0dca1793 AK |
5733 | { |
5734 | struct snd_pcm_channel_info *info = arg; | |
5735 | return snd_hdspm_channel_info(substream, info); | |
5736 | } | |
763f356c TI |
5737 | default: |
5738 | break; | |
5739 | } | |
5740 | ||
5741 | return snd_pcm_lib_ioctl(substream, cmd, arg); | |
5742 | } | |
5743 | ||
98274f07 | 5744 | static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd) |
763f356c | 5745 | { |
98274f07 TI |
5746 | struct hdspm *hdspm = snd_pcm_substream_chip(substream); |
5747 | struct snd_pcm_substream *other; | |
763f356c TI |
5748 | int running; |
5749 | ||
5750 | spin_lock(&hdspm->lock); | |
5751 | running = hdspm->running; | |
5752 | switch (cmd) { | |
5753 | case SNDRV_PCM_TRIGGER_START: | |
5754 | running |= 1 << substream->stream; | |
5755 | break; | |
5756 | case SNDRV_PCM_TRIGGER_STOP: | |
5757 | running &= ~(1 << substream->stream); | |
5758 | break; | |
5759 | default: | |
5760 | snd_BUG(); | |
5761 | spin_unlock(&hdspm->lock); | |
5762 | return -EINVAL; | |
5763 | } | |
5764 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
5765 | other = hdspm->capture_substream; | |
5766 | else | |
5767 | other = hdspm->playback_substream; | |
5768 | ||
5769 | if (other) { | |
98274f07 | 5770 | struct snd_pcm_substream *s; |
ef991b95 | 5771 | snd_pcm_group_for_each_entry(s, substream) { |
763f356c TI |
5772 | if (s == other) { |
5773 | snd_pcm_trigger_done(s, substream); | |
5774 | if (cmd == SNDRV_PCM_TRIGGER_START) | |
5775 | running |= 1 << s->stream; | |
5776 | else | |
5777 | running &= ~(1 << s->stream); | |
5778 | goto _ok; | |
5779 | } | |
5780 | } | |
5781 | if (cmd == SNDRV_PCM_TRIGGER_START) { | |
5782 | if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) | |
0dca1793 AK |
5783 | && substream->stream == |
5784 | SNDRV_PCM_STREAM_CAPTURE) | |
763f356c TI |
5785 | hdspm_silence_playback(hdspm); |
5786 | } else { | |
5787 | if (running && | |
0dca1793 | 5788 | substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
763f356c TI |
5789 | hdspm_silence_playback(hdspm); |
5790 | } | |
5791 | } else { | |
5792 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
5793 | hdspm_silence_playback(hdspm); | |
5794 | } | |
0dca1793 | 5795 | _ok: |
763f356c TI |
5796 | snd_pcm_trigger_done(substream, substream); |
5797 | if (!hdspm->running && running) | |
5798 | hdspm_start_audio(hdspm); | |
5799 | else if (hdspm->running && !running) | |
5800 | hdspm_stop_audio(hdspm); | |
5801 | hdspm->running = running; | |
5802 | spin_unlock(&hdspm->lock); | |
5803 | ||
5804 | return 0; | |
5805 | } | |
5806 | ||
98274f07 | 5807 | static int snd_hdspm_prepare(struct snd_pcm_substream *substream) |
763f356c TI |
5808 | { |
5809 | return 0; | |
5810 | } | |
5811 | ||
98274f07 | 5812 | static struct snd_pcm_hardware snd_hdspm_playback_subinfo = { |
763f356c TI |
5813 | .info = (SNDRV_PCM_INFO_MMAP | |
5814 | SNDRV_PCM_INFO_MMAP_VALID | | |
5815 | SNDRV_PCM_INFO_NONINTERLEAVED | | |
5816 | SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE), | |
5817 | .formats = SNDRV_PCM_FMTBIT_S32_LE, | |
5818 | .rates = (SNDRV_PCM_RATE_32000 | | |
5819 | SNDRV_PCM_RATE_44100 | | |
5820 | SNDRV_PCM_RATE_48000 | | |
5821 | SNDRV_PCM_RATE_64000 | | |
3cee5a60 RB |
5822 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | |
5823 | SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ), | |
763f356c | 5824 | .rate_min = 32000, |
3cee5a60 | 5825 | .rate_max = 192000, |
763f356c TI |
5826 | .channels_min = 1, |
5827 | .channels_max = HDSPM_MAX_CHANNELS, | |
5828 | .buffer_bytes_max = | |
5829 | HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, | |
1b6fa108 | 5830 | .period_bytes_min = (32 * 4), |
52e6fb48 | 5831 | .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS, |
763f356c | 5832 | .periods_min = 2, |
0dca1793 | 5833 | .periods_max = 512, |
763f356c TI |
5834 | .fifo_size = 0 |
5835 | }; | |
5836 | ||
98274f07 | 5837 | static struct snd_pcm_hardware snd_hdspm_capture_subinfo = { |
763f356c TI |
5838 | .info = (SNDRV_PCM_INFO_MMAP | |
5839 | SNDRV_PCM_INFO_MMAP_VALID | | |
5840 | SNDRV_PCM_INFO_NONINTERLEAVED | | |
5841 | SNDRV_PCM_INFO_SYNC_START), | |
5842 | .formats = SNDRV_PCM_FMTBIT_S32_LE, | |
5843 | .rates = (SNDRV_PCM_RATE_32000 | | |
5844 | SNDRV_PCM_RATE_44100 | | |
5845 | SNDRV_PCM_RATE_48000 | | |
5846 | SNDRV_PCM_RATE_64000 | | |
3cee5a60 RB |
5847 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | |
5848 | SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000), | |
763f356c | 5849 | .rate_min = 32000, |
3cee5a60 | 5850 | .rate_max = 192000, |
763f356c TI |
5851 | .channels_min = 1, |
5852 | .channels_max = HDSPM_MAX_CHANNELS, | |
5853 | .buffer_bytes_max = | |
5854 | HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, | |
1b6fa108 | 5855 | .period_bytes_min = (32 * 4), |
52e6fb48 | 5856 | .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS, |
763f356c | 5857 | .periods_min = 2, |
0dca1793 | 5858 | .periods_max = 512, |
763f356c TI |
5859 | .fifo_size = 0 |
5860 | }; | |
5861 | ||
0dca1793 AK |
5862 | static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params, |
5863 | struct snd_pcm_hw_rule *rule) | |
5864 | { | |
5865 | struct hdspm *hdspm = rule->private; | |
5866 | struct snd_interval *c = | |
5867 | hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); | |
5868 | struct snd_interval *r = | |
5869 | hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); | |
5870 | ||
5871 | if (r->min > 96000 && r->max <= 192000) { | |
5872 | struct snd_interval t = { | |
5873 | .min = hdspm->qs_in_channels, | |
5874 | .max = hdspm->qs_in_channels, | |
5875 | .integer = 1, | |
5876 | }; | |
5877 | return snd_interval_refine(c, &t); | |
5878 | } else if (r->min > 48000 && r->max <= 96000) { | |
5879 | struct snd_interval t = { | |
5880 | .min = hdspm->ds_in_channels, | |
5881 | .max = hdspm->ds_in_channels, | |
5882 | .integer = 1, | |
5883 | }; | |
5884 | return snd_interval_refine(c, &t); | |
5885 | } else if (r->max < 64000) { | |
5886 | struct snd_interval t = { | |
5887 | .min = hdspm->ss_in_channels, | |
5888 | .max = hdspm->ss_in_channels, | |
5889 | .integer = 1, | |
5890 | }; | |
5891 | return snd_interval_refine(c, &t); | |
5892 | } | |
5893 | ||
5894 | return 0; | |
5895 | } | |
763f356c | 5896 | |
0dca1793 | 5897 | static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params, |
98274f07 | 5898 | struct snd_pcm_hw_rule * rule) |
763f356c | 5899 | { |
98274f07 TI |
5900 | struct hdspm *hdspm = rule->private; |
5901 | struct snd_interval *c = | |
763f356c | 5902 | hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); |
98274f07 | 5903 | struct snd_interval *r = |
763f356c TI |
5904 | hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); |
5905 | ||
0dca1793 AK |
5906 | if (r->min > 96000 && r->max <= 192000) { |
5907 | struct snd_interval t = { | |
5908 | .min = hdspm->qs_out_channels, | |
5909 | .max = hdspm->qs_out_channels, | |
5910 | .integer = 1, | |
5911 | }; | |
5912 | return snd_interval_refine(c, &t); | |
5913 | } else if (r->min > 48000 && r->max <= 96000) { | |
98274f07 | 5914 | struct snd_interval t = { |
0dca1793 AK |
5915 | .min = hdspm->ds_out_channels, |
5916 | .max = hdspm->ds_out_channels, | |
763f356c TI |
5917 | .integer = 1, |
5918 | }; | |
5919 | return snd_interval_refine(c, &t); | |
5920 | } else if (r->max < 64000) { | |
98274f07 | 5921 | struct snd_interval t = { |
0dca1793 AK |
5922 | .min = hdspm->ss_out_channels, |
5923 | .max = hdspm->ss_out_channels, | |
763f356c TI |
5924 | .integer = 1, |
5925 | }; | |
5926 | return snd_interval_refine(c, &t); | |
0dca1793 | 5927 | } else { |
763f356c TI |
5928 | } |
5929 | return 0; | |
5930 | } | |
5931 | ||
0dca1793 | 5932 | static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params, |
98274f07 | 5933 | struct snd_pcm_hw_rule * rule) |
763f356c | 5934 | { |
98274f07 TI |
5935 | struct hdspm *hdspm = rule->private; |
5936 | struct snd_interval *c = | |
763f356c | 5937 | hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); |
98274f07 | 5938 | struct snd_interval *r = |
763f356c TI |
5939 | hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); |
5940 | ||
0dca1793 | 5941 | if (c->min >= hdspm->ss_in_channels) { |
98274f07 | 5942 | struct snd_interval t = { |
763f356c TI |
5943 | .min = 32000, |
5944 | .max = 48000, | |
5945 | .integer = 1, | |
5946 | }; | |
5947 | return snd_interval_refine(r, &t); | |
0dca1793 AK |
5948 | } else if (c->max <= hdspm->qs_in_channels) { |
5949 | struct snd_interval t = { | |
5950 | .min = 128000, | |
5951 | .max = 192000, | |
5952 | .integer = 1, | |
5953 | }; | |
5954 | return snd_interval_refine(r, &t); | |
5955 | } else if (c->max <= hdspm->ds_in_channels) { | |
98274f07 | 5956 | struct snd_interval t = { |
763f356c TI |
5957 | .min = 64000, |
5958 | .max = 96000, | |
5959 | .integer = 1, | |
5960 | }; | |
0dca1793 AK |
5961 | return snd_interval_refine(r, &t); |
5962 | } | |
5963 | ||
5964 | return 0; | |
5965 | } | |
5966 | static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params, | |
5967 | struct snd_pcm_hw_rule *rule) | |
5968 | { | |
5969 | struct hdspm *hdspm = rule->private; | |
5970 | struct snd_interval *c = | |
5971 | hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); | |
5972 | struct snd_interval *r = | |
5973 | hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); | |
763f356c | 5974 | |
0dca1793 AK |
5975 | if (c->min >= hdspm->ss_out_channels) { |
5976 | struct snd_interval t = { | |
5977 | .min = 32000, | |
5978 | .max = 48000, | |
5979 | .integer = 1, | |
5980 | }; | |
5981 | return snd_interval_refine(r, &t); | |
5982 | } else if (c->max <= hdspm->qs_out_channels) { | |
5983 | struct snd_interval t = { | |
5984 | .min = 128000, | |
5985 | .max = 192000, | |
5986 | .integer = 1, | |
5987 | }; | |
5988 | return snd_interval_refine(r, &t); | |
5989 | } else if (c->max <= hdspm->ds_out_channels) { | |
5990 | struct snd_interval t = { | |
5991 | .min = 64000, | |
5992 | .max = 96000, | |
5993 | .integer = 1, | |
5994 | }; | |
763f356c TI |
5995 | return snd_interval_refine(r, &t); |
5996 | } | |
0dca1793 | 5997 | |
763f356c TI |
5998 | return 0; |
5999 | } | |
6000 | ||
0dca1793 | 6001 | static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params, |
ffb2c3c0 RB |
6002 | struct snd_pcm_hw_rule *rule) |
6003 | { | |
6004 | unsigned int list[3]; | |
6005 | struct hdspm *hdspm = rule->private; | |
6006 | struct snd_interval *c = hw_param_interval(params, | |
6007 | SNDRV_PCM_HW_PARAM_CHANNELS); | |
0dca1793 AK |
6008 | |
6009 | list[0] = hdspm->qs_in_channels; | |
6010 | list[1] = hdspm->ds_in_channels; | |
6011 | list[2] = hdspm->ss_in_channels; | |
6012 | return snd_interval_list(c, 3, list, 0); | |
6013 | } | |
6014 | ||
6015 | static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params, | |
6016 | struct snd_pcm_hw_rule *rule) | |
6017 | { | |
6018 | unsigned int list[3]; | |
6019 | struct hdspm *hdspm = rule->private; | |
6020 | struct snd_interval *c = hw_param_interval(params, | |
6021 | SNDRV_PCM_HW_PARAM_CHANNELS); | |
6022 | ||
6023 | list[0] = hdspm->qs_out_channels; | |
6024 | list[1] = hdspm->ds_out_channels; | |
6025 | list[2] = hdspm->ss_out_channels; | |
6026 | return snd_interval_list(c, 3, list, 0); | |
ffb2c3c0 RB |
6027 | } |
6028 | ||
6029 | ||
ef5fa1a4 TI |
6030 | static unsigned int hdspm_aes32_sample_rates[] = { |
6031 | 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 | |
6032 | }; | |
ffb2c3c0 | 6033 | |
ef5fa1a4 TI |
6034 | static struct snd_pcm_hw_constraint_list |
6035 | hdspm_hw_constraints_aes32_sample_rates = { | |
ffb2c3c0 RB |
6036 | .count = ARRAY_SIZE(hdspm_aes32_sample_rates), |
6037 | .list = hdspm_aes32_sample_rates, | |
6038 | .mask = 0 | |
6039 | }; | |
6040 | ||
98274f07 | 6041 | static int snd_hdspm_playback_open(struct snd_pcm_substream *substream) |
763f356c | 6042 | { |
98274f07 TI |
6043 | struct hdspm *hdspm = snd_pcm_substream_chip(substream); |
6044 | struct snd_pcm_runtime *runtime = substream->runtime; | |
763f356c | 6045 | |
763f356c TI |
6046 | spin_lock_irq(&hdspm->lock); |
6047 | ||
6048 | snd_pcm_set_sync(substream); | |
6049 | ||
0dca1793 | 6050 | |
763f356c TI |
6051 | runtime->hw = snd_hdspm_playback_subinfo; |
6052 | ||
6053 | if (hdspm->capture_substream == NULL) | |
6054 | hdspm_stop_audio(hdspm); | |
6055 | ||
6056 | hdspm->playback_pid = current->pid; | |
6057 | hdspm->playback_substream = substream; | |
6058 | ||
6059 | spin_unlock_irq(&hdspm->lock); | |
6060 | ||
6061 | snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); | |
d877681d | 6062 | snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); |
763f356c | 6063 | |
0dca1793 AK |
6064 | switch (hdspm->io_type) { |
6065 | case AIO: | |
6066 | case RayDAT: | |
d877681d TI |
6067 | snd_pcm_hw_constraint_minmax(runtime, |
6068 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, | |
6069 | 32, 4096); | |
6070 | /* RayDAT & AIO have a fixed buffer of 16384 samples per channel */ | |
6071 | snd_pcm_hw_constraint_minmax(runtime, | |
6072 | SNDRV_PCM_HW_PARAM_BUFFER_SIZE, | |
6073 | 16384, 16384); | |
0dca1793 AK |
6074 | break; |
6075 | ||
6076 | default: | |
d877681d TI |
6077 | snd_pcm_hw_constraint_minmax(runtime, |
6078 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, | |
6079 | 64, 8192); | |
6080 | break; | |
0dca1793 | 6081 | } |
763f356c | 6082 | |
0dca1793 | 6083 | if (AES32 == hdspm->io_type) { |
3fa9e3d2 | 6084 | runtime->hw.rates |= SNDRV_PCM_RATE_KNOT; |
ffb2c3c0 RB |
6085 | snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, |
6086 | &hdspm_hw_constraints_aes32_sample_rates); | |
6087 | } else { | |
ffb2c3c0 | 6088 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, |
0dca1793 AK |
6089 | snd_hdspm_hw_rule_rate_out_channels, hdspm, |
6090 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); | |
ffb2c3c0 | 6091 | } |
88fabbfc AK |
6092 | |
6093 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, | |
6094 | snd_hdspm_hw_rule_out_channels, hdspm, | |
6095 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); | |
6096 | ||
6097 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, | |
6098 | snd_hdspm_hw_rule_out_channels_rate, hdspm, | |
6099 | SNDRV_PCM_HW_PARAM_RATE, -1); | |
6100 | ||
763f356c TI |
6101 | return 0; |
6102 | } | |
6103 | ||
98274f07 | 6104 | static int snd_hdspm_playback_release(struct snd_pcm_substream *substream) |
763f356c | 6105 | { |
98274f07 | 6106 | struct hdspm *hdspm = snd_pcm_substream_chip(substream); |
763f356c TI |
6107 | |
6108 | spin_lock_irq(&hdspm->lock); | |
6109 | ||
6110 | hdspm->playback_pid = -1; | |
6111 | hdspm->playback_substream = NULL; | |
6112 | ||
6113 | spin_unlock_irq(&hdspm->lock); | |
6114 | ||
6115 | return 0; | |
6116 | } | |
6117 | ||
6118 | ||
98274f07 | 6119 | static int snd_hdspm_capture_open(struct snd_pcm_substream *substream) |
763f356c | 6120 | { |
98274f07 TI |
6121 | struct hdspm *hdspm = snd_pcm_substream_chip(substream); |
6122 | struct snd_pcm_runtime *runtime = substream->runtime; | |
763f356c TI |
6123 | |
6124 | spin_lock_irq(&hdspm->lock); | |
6125 | snd_pcm_set_sync(substream); | |
6126 | runtime->hw = snd_hdspm_capture_subinfo; | |
6127 | ||
6128 | if (hdspm->playback_substream == NULL) | |
6129 | hdspm_stop_audio(hdspm); | |
6130 | ||
6131 | hdspm->capture_pid = current->pid; | |
6132 | hdspm->capture_substream = substream; | |
6133 | ||
6134 | spin_unlock_irq(&hdspm->lock); | |
6135 | ||
6136 | snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); | |
d877681d TI |
6137 | snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); |
6138 | ||
0dca1793 AK |
6139 | switch (hdspm->io_type) { |
6140 | case AIO: | |
6141 | case RayDAT: | |
d877681d TI |
6142 | snd_pcm_hw_constraint_minmax(runtime, |
6143 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, | |
6144 | 32, 4096); | |
6145 | snd_pcm_hw_constraint_minmax(runtime, | |
6146 | SNDRV_PCM_HW_PARAM_BUFFER_SIZE, | |
6147 | 16384, 16384); | |
6148 | break; | |
0dca1793 AK |
6149 | |
6150 | default: | |
d877681d TI |
6151 | snd_pcm_hw_constraint_minmax(runtime, |
6152 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, | |
6153 | 64, 8192); | |
6154 | break; | |
0dca1793 AK |
6155 | } |
6156 | ||
6157 | if (AES32 == hdspm->io_type) { | |
3fa9e3d2 | 6158 | runtime->hw.rates |= SNDRV_PCM_RATE_KNOT; |
ffb2c3c0 RB |
6159 | snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, |
6160 | &hdspm_hw_constraints_aes32_sample_rates); | |
6161 | } else { | |
ffb2c3c0 | 6162 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, |
88fabbfc AK |
6163 | snd_hdspm_hw_rule_rate_in_channels, hdspm, |
6164 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); | |
ffb2c3c0 | 6165 | } |
88fabbfc AK |
6166 | |
6167 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, | |
6168 | snd_hdspm_hw_rule_in_channels, hdspm, | |
6169 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); | |
6170 | ||
6171 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, | |
6172 | snd_hdspm_hw_rule_in_channels_rate, hdspm, | |
6173 | SNDRV_PCM_HW_PARAM_RATE, -1); | |
6174 | ||
763f356c TI |
6175 | return 0; |
6176 | } | |
6177 | ||
98274f07 | 6178 | static int snd_hdspm_capture_release(struct snd_pcm_substream *substream) |
763f356c | 6179 | { |
98274f07 | 6180 | struct hdspm *hdspm = snd_pcm_substream_chip(substream); |
763f356c TI |
6181 | |
6182 | spin_lock_irq(&hdspm->lock); | |
6183 | ||
6184 | hdspm->capture_pid = -1; | |
6185 | hdspm->capture_substream = NULL; | |
6186 | ||
6187 | spin_unlock_irq(&hdspm->lock); | |
6188 | return 0; | |
6189 | } | |
6190 | ||
0dca1793 AK |
6191 | static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file) |
6192 | { | |
6193 | /* we have nothing to initialize but the call is required */ | |
6194 | return 0; | |
6195 | } | |
6196 | ||
6197 | static inline int copy_u32_le(void __user *dest, void __iomem *src) | |
6198 | { | |
6199 | u32 val = readl(src); | |
6200 | return copy_to_user(dest, &val, 4); | |
6201 | } | |
6202 | ||
6203 | static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, | |
2ca595ab | 6204 | unsigned int cmd, unsigned long arg) |
763f356c | 6205 | { |
0dca1793 | 6206 | void __user *argp = (void __user *)arg; |
ef5fa1a4 | 6207 | struct hdspm *hdspm = hw->private_data; |
98274f07 | 6208 | struct hdspm_mixer_ioctl mixer; |
0dca1793 AK |
6209 | struct hdspm_config info; |
6210 | struct hdspm_status status; | |
98274f07 | 6211 | struct hdspm_version hdspm_version; |
730a5865 | 6212 | struct hdspm_peak_rms *levels; |
0dca1793 AK |
6213 | struct hdspm_ltc ltc; |
6214 | unsigned int statusregister; | |
6215 | long unsigned int s; | |
6216 | int i = 0; | |
763f356c TI |
6217 | |
6218 | switch (cmd) { | |
6219 | ||
763f356c | 6220 | case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS: |
730a5865 | 6221 | levels = &hdspm->peak_rms; |
0dca1793 | 6222 | for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { |
730a5865 | 6223 | levels->input_peaks[i] = |
0dca1793 AK |
6224 | readl(hdspm->iobase + |
6225 | HDSPM_MADI_INPUT_PEAK + i*4); | |
730a5865 | 6226 | levels->playback_peaks[i] = |
0dca1793 AK |
6227 | readl(hdspm->iobase + |
6228 | HDSPM_MADI_PLAYBACK_PEAK + i*4); | |
730a5865 | 6229 | levels->output_peaks[i] = |
0dca1793 AK |
6230 | readl(hdspm->iobase + |
6231 | HDSPM_MADI_OUTPUT_PEAK + i*4); | |
6232 | ||
730a5865 | 6233 | levels->input_rms[i] = |
0dca1793 AK |
6234 | ((uint64_t) readl(hdspm->iobase + |
6235 | HDSPM_MADI_INPUT_RMS_H + i*4) << 32) | | |
6236 | (uint64_t) readl(hdspm->iobase + | |
6237 | HDSPM_MADI_INPUT_RMS_L + i*4); | |
730a5865 | 6238 | levels->playback_rms[i] = |
0dca1793 AK |
6239 | ((uint64_t)readl(hdspm->iobase + |
6240 | HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) | | |
6241 | (uint64_t)readl(hdspm->iobase + | |
6242 | HDSPM_MADI_PLAYBACK_RMS_L + i*4); | |
730a5865 | 6243 | levels->output_rms[i] = |
0dca1793 AK |
6244 | ((uint64_t)readl(hdspm->iobase + |
6245 | HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) | | |
6246 | (uint64_t)readl(hdspm->iobase + | |
6247 | HDSPM_MADI_OUTPUT_RMS_L + i*4); | |
6248 | } | |
6249 | ||
6250 | if (hdspm->system_sample_rate > 96000) { | |
730a5865 | 6251 | levels->speed = qs; |
0dca1793 | 6252 | } else if (hdspm->system_sample_rate > 48000) { |
730a5865 | 6253 | levels->speed = ds; |
0dca1793 | 6254 | } else { |
730a5865 | 6255 | levels->speed = ss; |
0dca1793 | 6256 | } |
730a5865 | 6257 | levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2); |
0dca1793 | 6258 | |
730a5865 | 6259 | s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms)); |
0dca1793 AK |
6260 | if (0 != s) { |
6261 | /* snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu | |
6262 | [Levels]\n", sizeof(struct hdspm_peak_rms), s); | |
6263 | */ | |
763f356c | 6264 | return -EFAULT; |
0dca1793 AK |
6265 | } |
6266 | break; | |
6267 | ||
6268 | case SNDRV_HDSPM_IOCTL_GET_LTC: | |
6269 | ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO); | |
6270 | i = hdspm_read(hdspm, HDSPM_RD_TCO + 4); | |
6271 | if (i & HDSPM_TCO1_LTC_Input_valid) { | |
6272 | switch (i & (HDSPM_TCO1_LTC_Format_LSB | | |
6273 | HDSPM_TCO1_LTC_Format_MSB)) { | |
6274 | case 0: | |
6275 | ltc.format = fps_24; | |
6276 | break; | |
6277 | case HDSPM_TCO1_LTC_Format_LSB: | |
6278 | ltc.format = fps_25; | |
6279 | break; | |
6280 | case HDSPM_TCO1_LTC_Format_MSB: | |
6281 | ltc.format = fps_2997; | |
6282 | break; | |
6283 | default: | |
6284 | ltc.format = 30; | |
6285 | break; | |
6286 | } | |
6287 | if (i & HDSPM_TCO1_set_drop_frame_flag) { | |
6288 | ltc.frame = drop_frame; | |
6289 | } else { | |
6290 | ltc.frame = full_frame; | |
6291 | } | |
6292 | } else { | |
6293 | ltc.format = format_invalid; | |
6294 | ltc.frame = frame_invalid; | |
6295 | } | |
6296 | if (i & HDSPM_TCO1_Video_Input_Format_NTSC) { | |
6297 | ltc.input_format = ntsc; | |
6298 | } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) { | |
6299 | ltc.input_format = pal; | |
6300 | } else { | |
6301 | ltc.input_format = no_video; | |
6302 | } | |
6303 | ||
6304 | s = copy_to_user(argp, <c, sizeof(struct hdspm_ltc)); | |
6305 | if (0 != s) { | |
6306 | /* | |
6307 | snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */ | |
763f356c | 6308 | return -EFAULT; |
0dca1793 | 6309 | } |
763f356c TI |
6310 | |
6311 | break; | |
763f356c | 6312 | |
0dca1793 | 6313 | case SNDRV_HDSPM_IOCTL_GET_CONFIG: |
763f356c | 6314 | |
4ab69a2b | 6315 | memset(&info, 0, sizeof(info)); |
763f356c | 6316 | spin_lock_irq(&hdspm->lock); |
ef5fa1a4 TI |
6317 | info.pref_sync_ref = hdspm_pref_sync_ref(hdspm); |
6318 | info.wordclock_sync_check = hdspm_wc_sync_check(hdspm); | |
763f356c TI |
6319 | |
6320 | info.system_sample_rate = hdspm->system_sample_rate; | |
6321 | info.autosync_sample_rate = | |
0dca1793 | 6322 | hdspm_external_sample_rate(hdspm); |
ef5fa1a4 TI |
6323 | info.system_clock_mode = hdspm_system_clock_mode(hdspm); |
6324 | info.clock_source = hdspm_clock_source(hdspm); | |
6325 | info.autosync_ref = hdspm_autosync_ref(hdspm); | |
6326 | info.line_out = hdspm_line_out(hdspm); | |
763f356c TI |
6327 | info.passthru = 0; |
6328 | spin_unlock_irq(&hdspm->lock); | |
2ca595ab | 6329 | if (copy_to_user(argp, &info, sizeof(info))) |
763f356c TI |
6330 | return -EFAULT; |
6331 | break; | |
6332 | ||
0dca1793 | 6333 | case SNDRV_HDSPM_IOCTL_GET_STATUS: |
643d6bbb DC |
6334 | memset(&status, 0, sizeof(status)); |
6335 | ||
0dca1793 AK |
6336 | status.card_type = hdspm->io_type; |
6337 | ||
6338 | status.autosync_source = hdspm_autosync_ref(hdspm); | |
6339 | ||
6340 | status.card_clock = 110069313433624ULL; | |
6341 | status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); | |
6342 | ||
6343 | switch (hdspm->io_type) { | |
6344 | case MADI: | |
6345 | case MADIface: | |
6346 | status.card_specific.madi.sync_wc = | |
6347 | hdspm_wc_sync_check(hdspm); | |
6348 | status.card_specific.madi.sync_madi = | |
6349 | hdspm_madi_sync_check(hdspm); | |
6350 | status.card_specific.madi.sync_tco = | |
6351 | hdspm_tco_sync_check(hdspm); | |
6352 | status.card_specific.madi.sync_in = | |
6353 | hdspm_sync_in_sync_check(hdspm); | |
6354 | ||
6355 | statusregister = | |
6356 | hdspm_read(hdspm, HDSPM_statusRegister); | |
6357 | status.card_specific.madi.madi_input = | |
6358 | (statusregister & HDSPM_AB_int) ? 1 : 0; | |
6359 | status.card_specific.madi.channel_format = | |
9e6ff520 | 6360 | (statusregister & HDSPM_RX_64ch) ? 1 : 0; |
0dca1793 AK |
6361 | /* TODO: Mac driver sets it when f_s>48kHz */ |
6362 | status.card_specific.madi.frame_format = 0; | |
6363 | ||
6364 | default: | |
6365 | break; | |
6366 | } | |
6367 | ||
2ca595ab | 6368 | if (copy_to_user(argp, &status, sizeof(status))) |
0dca1793 AK |
6369 | return -EFAULT; |
6370 | ||
6371 | ||
6372 | break; | |
6373 | ||
763f356c | 6374 | case SNDRV_HDSPM_IOCTL_GET_VERSION: |
643d6bbb DC |
6375 | memset(&hdspm_version, 0, sizeof(hdspm_version)); |
6376 | ||
0dca1793 AK |
6377 | hdspm_version.card_type = hdspm->io_type; |
6378 | strncpy(hdspm_version.cardname, hdspm->card_name, | |
6379 | sizeof(hdspm_version.cardname)); | |
7d53a631 | 6380 | hdspm_version.serial = hdspm->serial; |
763f356c | 6381 | hdspm_version.firmware_rev = hdspm->firmware_rev; |
0dca1793 AK |
6382 | hdspm_version.addons = 0; |
6383 | if (hdspm->tco) | |
6384 | hdspm_version.addons |= HDSPM_ADDON_TCO; | |
6385 | ||
2ca595ab | 6386 | if (copy_to_user(argp, &hdspm_version, |
0dca1793 | 6387 | sizeof(hdspm_version))) |
763f356c TI |
6388 | return -EFAULT; |
6389 | break; | |
6390 | ||
6391 | case SNDRV_HDSPM_IOCTL_GET_MIXER: | |
2ca595ab | 6392 | if (copy_from_user(&mixer, argp, sizeof(mixer))) |
763f356c | 6393 | return -EFAULT; |
ef5fa1a4 | 6394 | if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer, |
0dca1793 | 6395 | sizeof(struct hdspm_mixer))) |
763f356c TI |
6396 | return -EFAULT; |
6397 | break; | |
6398 | ||
6399 | default: | |
6400 | return -EINVAL; | |
6401 | } | |
6402 | return 0; | |
6403 | } | |
6404 | ||
98274f07 | 6405 | static struct snd_pcm_ops snd_hdspm_playback_ops = { |
763f356c TI |
6406 | .open = snd_hdspm_playback_open, |
6407 | .close = snd_hdspm_playback_release, | |
6408 | .ioctl = snd_hdspm_ioctl, | |
6409 | .hw_params = snd_hdspm_hw_params, | |
6410 | .hw_free = snd_hdspm_hw_free, | |
6411 | .prepare = snd_hdspm_prepare, | |
6412 | .trigger = snd_hdspm_trigger, | |
6413 | .pointer = snd_hdspm_hw_pointer, | |
763f356c TI |
6414 | .page = snd_pcm_sgbuf_ops_page, |
6415 | }; | |
6416 | ||
98274f07 | 6417 | static struct snd_pcm_ops snd_hdspm_capture_ops = { |
763f356c TI |
6418 | .open = snd_hdspm_capture_open, |
6419 | .close = snd_hdspm_capture_release, | |
6420 | .ioctl = snd_hdspm_ioctl, | |
6421 | .hw_params = snd_hdspm_hw_params, | |
6422 | .hw_free = snd_hdspm_hw_free, | |
6423 | .prepare = snd_hdspm_prepare, | |
6424 | .trigger = snd_hdspm_trigger, | |
6425 | .pointer = snd_hdspm_hw_pointer, | |
763f356c TI |
6426 | .page = snd_pcm_sgbuf_ops_page, |
6427 | }; | |
6428 | ||
98274f07 TI |
6429 | static int __devinit snd_hdspm_create_hwdep(struct snd_card *card, |
6430 | struct hdspm * hdspm) | |
763f356c | 6431 | { |
98274f07 | 6432 | struct snd_hwdep *hw; |
763f356c TI |
6433 | int err; |
6434 | ||
ef5fa1a4 TI |
6435 | err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw); |
6436 | if (err < 0) | |
763f356c TI |
6437 | return err; |
6438 | ||
6439 | hdspm->hwdep = hw; | |
6440 | hw->private_data = hdspm; | |
6441 | strcpy(hw->name, "HDSPM hwdep interface"); | |
6442 | ||
0dca1793 | 6443 | hw->ops.open = snd_hdspm_hwdep_dummy_op; |
763f356c | 6444 | hw->ops.ioctl = snd_hdspm_hwdep_ioctl; |
8de5d6f1 | 6445 | hw->ops.ioctl_compat = snd_hdspm_hwdep_ioctl; |
0dca1793 | 6446 | hw->ops.release = snd_hdspm_hwdep_dummy_op; |
763f356c TI |
6447 | |
6448 | return 0; | |
6449 | } | |
6450 | ||
6451 | ||
6452 | /*------------------------------------------------------------ | |
0dca1793 | 6453 | memory interface |
763f356c | 6454 | ------------------------------------------------------------*/ |
0dca1793 | 6455 | static int __devinit snd_hdspm_preallocate_memory(struct hdspm *hdspm) |
763f356c TI |
6456 | { |
6457 | int err; | |
98274f07 | 6458 | struct snd_pcm *pcm; |
763f356c TI |
6459 | size_t wanted; |
6460 | ||
6461 | pcm = hdspm->pcm; | |
6462 | ||
3cee5a60 | 6463 | wanted = HDSPM_DMA_AREA_BYTES; |
763f356c | 6464 | |
ef5fa1a4 | 6465 | err = |
763f356c | 6466 | snd_pcm_lib_preallocate_pages_for_all(pcm, |
0dca1793 | 6467 | SNDRV_DMA_TYPE_DEV_SG, |
763f356c TI |
6468 | snd_dma_pci_data(hdspm->pci), |
6469 | wanted, | |
ef5fa1a4 TI |
6470 | wanted); |
6471 | if (err < 0) { | |
e2eba3e7 | 6472 | snd_printdd("Could not preallocate %zd Bytes\n", wanted); |
763f356c TI |
6473 | |
6474 | return err; | |
6475 | } else | |
e2eba3e7 | 6476 | snd_printdd(" Preallocated %zd Bytes\n", wanted); |
763f356c TI |
6477 | |
6478 | return 0; | |
6479 | } | |
6480 | ||
0dca1793 AK |
6481 | |
6482 | static void hdspm_set_sgbuf(struct hdspm *hdspm, | |
77a23f26 | 6483 | struct snd_pcm_substream *substream, |
763f356c TI |
6484 | unsigned int reg, int channels) |
6485 | { | |
6486 | int i; | |
0dca1793 AK |
6487 | |
6488 | /* continuous memory segment */ | |
763f356c TI |
6489 | for (i = 0; i < (channels * 16); i++) |
6490 | hdspm_write(hdspm, reg + 4 * i, | |
0dca1793 | 6491 | snd_pcm_sgbuf_get_addr(substream, 4096 * i)); |
763f356c TI |
6492 | } |
6493 | ||
0dca1793 | 6494 | |
763f356c | 6495 | /* ------------- ALSA Devices ---------------------------- */ |
98274f07 | 6496 | static int __devinit snd_hdspm_create_pcm(struct snd_card *card, |
0dca1793 | 6497 | struct hdspm *hdspm) |
763f356c | 6498 | { |
98274f07 | 6499 | struct snd_pcm *pcm; |
763f356c TI |
6500 | int err; |
6501 | ||
ef5fa1a4 TI |
6502 | err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm); |
6503 | if (err < 0) | |
763f356c TI |
6504 | return err; |
6505 | ||
6506 | hdspm->pcm = pcm; | |
6507 | pcm->private_data = hdspm; | |
6508 | strcpy(pcm->name, hdspm->card_name); | |
6509 | ||
6510 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, | |
6511 | &snd_hdspm_playback_ops); | |
6512 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, | |
6513 | &snd_hdspm_capture_ops); | |
6514 | ||
6515 | pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; | |
6516 | ||
ef5fa1a4 TI |
6517 | err = snd_hdspm_preallocate_memory(hdspm); |
6518 | if (err < 0) | |
763f356c TI |
6519 | return err; |
6520 | ||
6521 | return 0; | |
6522 | } | |
6523 | ||
98274f07 | 6524 | static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm) |
763f356c | 6525 | { |
7c7102b7 AK |
6526 | int i; |
6527 | ||
6528 | for (i = 0; i < hdspm->midiPorts; i++) | |
6529 | snd_hdspm_flush_midi_input(hdspm, i); | |
763f356c TI |
6530 | } |
6531 | ||
98274f07 TI |
6532 | static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card, |
6533 | struct hdspm * hdspm) | |
763f356c | 6534 | { |
0dca1793 | 6535 | int err, i; |
763f356c TI |
6536 | |
6537 | snd_printdd("Create card...\n"); | |
ef5fa1a4 TI |
6538 | err = snd_hdspm_create_pcm(card, hdspm); |
6539 | if (err < 0) | |
763f356c TI |
6540 | return err; |
6541 | ||
0dca1793 AK |
6542 | i = 0; |
6543 | while (i < hdspm->midiPorts) { | |
6544 | err = snd_hdspm_create_midi(card, hdspm, i); | |
6545 | if (err < 0) { | |
6546 | return err; | |
6547 | } | |
6548 | i++; | |
6549 | } | |
763f356c | 6550 | |
ef5fa1a4 TI |
6551 | err = snd_hdspm_create_controls(card, hdspm); |
6552 | if (err < 0) | |
763f356c TI |
6553 | return err; |
6554 | ||
ef5fa1a4 TI |
6555 | err = snd_hdspm_create_hwdep(card, hdspm); |
6556 | if (err < 0) | |
763f356c TI |
6557 | return err; |
6558 | ||
6559 | snd_printdd("proc init...\n"); | |
6560 | snd_hdspm_proc_init(hdspm); | |
6561 | ||
6562 | hdspm->system_sample_rate = -1; | |
6563 | hdspm->last_external_sample_rate = -1; | |
6564 | hdspm->last_internal_sample_rate = -1; | |
6565 | hdspm->playback_pid = -1; | |
6566 | hdspm->capture_pid = -1; | |
6567 | hdspm->capture_substream = NULL; | |
6568 | hdspm->playback_substream = NULL; | |
6569 | ||
6570 | snd_printdd("Set defaults...\n"); | |
ef5fa1a4 TI |
6571 | err = snd_hdspm_set_defaults(hdspm); |
6572 | if (err < 0) | |
763f356c TI |
6573 | return err; |
6574 | ||
6575 | snd_printdd("Update mixer controls...\n"); | |
6576 | hdspm_update_simple_mixer_controls(hdspm); | |
6577 | ||
6578 | snd_printdd("Initializeing complete ???\n"); | |
6579 | ||
ef5fa1a4 TI |
6580 | err = snd_card_register(card); |
6581 | if (err < 0) { | |
763f356c TI |
6582 | snd_printk(KERN_ERR "HDSPM: error registering card\n"); |
6583 | return err; | |
6584 | } | |
6585 | ||
6586 | snd_printdd("... yes now\n"); | |
6587 | ||
6588 | return 0; | |
6589 | } | |
6590 | ||
ef5fa1a4 | 6591 | static int __devinit snd_hdspm_create(struct snd_card *card, |
0dca1793 AK |
6592 | struct hdspm *hdspm) { |
6593 | ||
763f356c TI |
6594 | struct pci_dev *pci = hdspm->pci; |
6595 | int err; | |
763f356c TI |
6596 | unsigned long io_extent; |
6597 | ||
6598 | hdspm->irq = -1; | |
763f356c TI |
6599 | hdspm->card = card; |
6600 | ||
6601 | spin_lock_init(&hdspm->lock); | |
6602 | ||
763f356c | 6603 | pci_read_config_word(hdspm->pci, |
0dca1793 | 6604 | PCI_CLASS_REVISION, &hdspm->firmware_rev); |
3cee5a60 | 6605 | |
763f356c | 6606 | strcpy(card->mixername, "Xilinx FPGA"); |
0dca1793 AK |
6607 | strcpy(card->driver, "HDSPM"); |
6608 | ||
6609 | switch (hdspm->firmware_rev) { | |
0dca1793 AK |
6610 | case HDSPM_RAYDAT_REV: |
6611 | hdspm->io_type = RayDAT; | |
6612 | hdspm->card_name = "RME RayDAT"; | |
6613 | hdspm->midiPorts = 2; | |
6614 | break; | |
6615 | case HDSPM_AIO_REV: | |
6616 | hdspm->io_type = AIO; | |
6617 | hdspm->card_name = "RME AIO"; | |
6618 | hdspm->midiPorts = 1; | |
6619 | break; | |
6620 | case HDSPM_MADIFACE_REV: | |
6621 | hdspm->io_type = MADIface; | |
6622 | hdspm->card_name = "RME MADIface"; | |
6623 | hdspm->midiPorts = 1; | |
6624 | break; | |
5027f347 | 6625 | default: |
c09403dc AK |
6626 | if ((hdspm->firmware_rev == 0xf0) || |
6627 | ((hdspm->firmware_rev >= 0xe6) && | |
6628 | (hdspm->firmware_rev <= 0xea))) { | |
6629 | hdspm->io_type = AES32; | |
6630 | hdspm->card_name = "RME AES32"; | |
6631 | hdspm->midiPorts = 2; | |
05c7cc9c | 6632 | } else if ((hdspm->firmware_rev == 0xd2) || |
c09403dc AK |
6633 | ((hdspm->firmware_rev >= 0xc8) && |
6634 | (hdspm->firmware_rev <= 0xcf))) { | |
6635 | hdspm->io_type = MADI; | |
6636 | hdspm->card_name = "RME MADI"; | |
6637 | hdspm->midiPorts = 3; | |
6638 | } else { | |
6639 | snd_printk(KERN_ERR | |
6640 | "HDSPM: unknown firmware revision %x\n", | |
5027f347 | 6641 | hdspm->firmware_rev); |
c09403dc AK |
6642 | return -ENODEV; |
6643 | } | |
3cee5a60 | 6644 | } |
763f356c | 6645 | |
ef5fa1a4 TI |
6646 | err = pci_enable_device(pci); |
6647 | if (err < 0) | |
763f356c TI |
6648 | return err; |
6649 | ||
6650 | pci_set_master(hdspm->pci); | |
6651 | ||
ef5fa1a4 TI |
6652 | err = pci_request_regions(pci, "hdspm"); |
6653 | if (err < 0) | |
763f356c TI |
6654 | return err; |
6655 | ||
6656 | hdspm->port = pci_resource_start(pci, 0); | |
6657 | io_extent = pci_resource_len(pci, 0); | |
6658 | ||
6659 | snd_printdd("grabbed memory region 0x%lx-0x%lx\n", | |
0dca1793 | 6660 | hdspm->port, hdspm->port + io_extent - 1); |
763f356c | 6661 | |
ef5fa1a4 TI |
6662 | hdspm->iobase = ioremap_nocache(hdspm->port, io_extent); |
6663 | if (!hdspm->iobase) { | |
6664 | snd_printk(KERN_ERR "HDSPM: " | |
0dca1793 AK |
6665 | "unable to remap region 0x%lx-0x%lx\n", |
6666 | hdspm->port, hdspm->port + io_extent - 1); | |
763f356c TI |
6667 | return -EBUSY; |
6668 | } | |
6669 | snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n", | |
0dca1793 AK |
6670 | (unsigned long)hdspm->iobase, hdspm->port, |
6671 | hdspm->port + io_extent - 1); | |
763f356c TI |
6672 | |
6673 | if (request_irq(pci->irq, snd_hdspm_interrupt, | |
934c2b6d | 6674 | IRQF_SHARED, KBUILD_MODNAME, hdspm)) { |
763f356c TI |
6675 | snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq); |
6676 | return -EBUSY; | |
6677 | } | |
6678 | ||
6679 | snd_printdd("use IRQ %d\n", pci->irq); | |
6680 | ||
6681 | hdspm->irq = pci->irq; | |
763f356c | 6682 | |
e2eba3e7 | 6683 | snd_printdd("kmalloc Mixer memory of %zd Bytes\n", |
0dca1793 | 6684 | sizeof(struct hdspm_mixer)); |
ef5fa1a4 TI |
6685 | hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL); |
6686 | if (!hdspm->mixer) { | |
6687 | snd_printk(KERN_ERR "HDSPM: " | |
0dca1793 AK |
6688 | "unable to kmalloc Mixer memory of %d Bytes\n", |
6689 | (int)sizeof(struct hdspm_mixer)); | |
b17cbdd8 | 6690 | return -ENOMEM; |
763f356c TI |
6691 | } |
6692 | ||
0dca1793 AK |
6693 | hdspm->port_names_in = NULL; |
6694 | hdspm->port_names_out = NULL; | |
6695 | ||
6696 | switch (hdspm->io_type) { | |
6697 | case AES32: | |
d2d10a21 AK |
6698 | hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS; |
6699 | hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS; | |
6700 | hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS; | |
432d2500 AK |
6701 | |
6702 | hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = | |
6703 | channel_map_aes32; | |
6704 | hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = | |
6705 | channel_map_aes32; | |
6706 | hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = | |
6707 | channel_map_aes32; | |
6708 | hdspm->port_names_in_ss = hdspm->port_names_out_ss = | |
6709 | texts_ports_aes32; | |
6710 | hdspm->port_names_in_ds = hdspm->port_names_out_ds = | |
6711 | texts_ports_aes32; | |
6712 | hdspm->port_names_in_qs = hdspm->port_names_out_qs = | |
6713 | texts_ports_aes32; | |
6714 | ||
d2d10a21 AK |
6715 | hdspm->max_channels_out = hdspm->max_channels_in = |
6716 | AES32_CHANNELS; | |
432d2500 AK |
6717 | hdspm->port_names_in = hdspm->port_names_out = |
6718 | texts_ports_aes32; | |
6719 | hdspm->channel_map_in = hdspm->channel_map_out = | |
6720 | channel_map_aes32; | |
6721 | ||
0dca1793 AK |
6722 | break; |
6723 | ||
6724 | case MADI: | |
6725 | case MADIface: | |
6726 | hdspm->ss_in_channels = hdspm->ss_out_channels = | |
6727 | MADI_SS_CHANNELS; | |
6728 | hdspm->ds_in_channels = hdspm->ds_out_channels = | |
6729 | MADI_DS_CHANNELS; | |
6730 | hdspm->qs_in_channels = hdspm->qs_out_channels = | |
6731 | MADI_QS_CHANNELS; | |
6732 | ||
6733 | hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = | |
6734 | channel_map_unity_ss; | |
01e96078 | 6735 | hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = |
0dca1793 | 6736 | channel_map_unity_ss; |
01e96078 | 6737 | hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = |
0dca1793 AK |
6738 | channel_map_unity_ss; |
6739 | ||
6740 | hdspm->port_names_in_ss = hdspm->port_names_out_ss = | |
6741 | texts_ports_madi; | |
6742 | hdspm->port_names_in_ds = hdspm->port_names_out_ds = | |
6743 | texts_ports_madi; | |
6744 | hdspm->port_names_in_qs = hdspm->port_names_out_qs = | |
6745 | texts_ports_madi; | |
6746 | break; | |
6747 | ||
6748 | case AIO: | |
6749 | if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) { | |
6750 | snd_printk(KERN_INFO "HDSPM: AEB input board found, but not supported\n"); | |
6751 | } | |
6752 | ||
6753 | hdspm->ss_in_channels = AIO_IN_SS_CHANNELS; | |
6754 | hdspm->ds_in_channels = AIO_IN_DS_CHANNELS; | |
6755 | hdspm->qs_in_channels = AIO_IN_QS_CHANNELS; | |
6756 | hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS; | |
6757 | hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS; | |
6758 | hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS; | |
6759 | ||
6760 | hdspm->channel_map_out_ss = channel_map_aio_out_ss; | |
6761 | hdspm->channel_map_out_ds = channel_map_aio_out_ds; | |
6762 | hdspm->channel_map_out_qs = channel_map_aio_out_qs; | |
6763 | ||
6764 | hdspm->channel_map_in_ss = channel_map_aio_in_ss; | |
6765 | hdspm->channel_map_in_ds = channel_map_aio_in_ds; | |
6766 | hdspm->channel_map_in_qs = channel_map_aio_in_qs; | |
6767 | ||
6768 | hdspm->port_names_in_ss = texts_ports_aio_in_ss; | |
6769 | hdspm->port_names_out_ss = texts_ports_aio_out_ss; | |
6770 | hdspm->port_names_in_ds = texts_ports_aio_in_ds; | |
6771 | hdspm->port_names_out_ds = texts_ports_aio_out_ds; | |
6772 | hdspm->port_names_in_qs = texts_ports_aio_in_qs; | |
6773 | hdspm->port_names_out_qs = texts_ports_aio_out_qs; | |
6774 | ||
6775 | break; | |
6776 | ||
6777 | case RayDAT: | |
6778 | hdspm->ss_in_channels = hdspm->ss_out_channels = | |
6779 | RAYDAT_SS_CHANNELS; | |
6780 | hdspm->ds_in_channels = hdspm->ds_out_channels = | |
6781 | RAYDAT_DS_CHANNELS; | |
6782 | hdspm->qs_in_channels = hdspm->qs_out_channels = | |
6783 | RAYDAT_QS_CHANNELS; | |
6784 | ||
6785 | hdspm->max_channels_in = RAYDAT_SS_CHANNELS; | |
6786 | hdspm->max_channels_out = RAYDAT_SS_CHANNELS; | |
6787 | ||
6788 | hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = | |
6789 | channel_map_raydat_ss; | |
6790 | hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = | |
6791 | channel_map_raydat_ds; | |
6792 | hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = | |
6793 | channel_map_raydat_qs; | |
6794 | hdspm->channel_map_in = hdspm->channel_map_out = | |
6795 | channel_map_raydat_ss; | |
6796 | ||
6797 | hdspm->port_names_in_ss = hdspm->port_names_out_ss = | |
6798 | texts_ports_raydat_ss; | |
6799 | hdspm->port_names_in_ds = hdspm->port_names_out_ds = | |
6800 | texts_ports_raydat_ds; | |
6801 | hdspm->port_names_in_qs = hdspm->port_names_out_qs = | |
6802 | texts_ports_raydat_qs; | |
6803 | ||
6804 | ||
6805 | break; | |
6806 | ||
6807 | } | |
6808 | ||
6809 | /* TCO detection */ | |
6810 | switch (hdspm->io_type) { | |
6811 | case AIO: | |
6812 | case RayDAT: | |
6813 | if (hdspm_read(hdspm, HDSPM_statusRegister2) & | |
6814 | HDSPM_s2_tco_detect) { | |
6815 | hdspm->midiPorts++; | |
6816 | hdspm->tco = kzalloc(sizeof(struct hdspm_tco), | |
6817 | GFP_KERNEL); | |
6818 | if (NULL != hdspm->tco) { | |
6819 | hdspm_tco_write(hdspm); | |
6820 | } | |
6821 | snd_printk(KERN_INFO "HDSPM: AIO/RayDAT TCO module found\n"); | |
6822 | } else { | |
6823 | hdspm->tco = NULL; | |
6824 | } | |
6825 | break; | |
6826 | ||
6827 | case MADI: | |
6828 | if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) { | |
6829 | hdspm->midiPorts++; | |
6830 | hdspm->tco = kzalloc(sizeof(struct hdspm_tco), | |
6831 | GFP_KERNEL); | |
6832 | if (NULL != hdspm->tco) { | |
6833 | hdspm_tco_write(hdspm); | |
6834 | } | |
6835 | snd_printk(KERN_INFO "HDSPM: MADI TCO module found\n"); | |
6836 | } else { | |
6837 | hdspm->tco = NULL; | |
6838 | } | |
6839 | break; | |
6840 | ||
6841 | default: | |
6842 | hdspm->tco = NULL; | |
6843 | } | |
6844 | ||
6845 | /* texts */ | |
6846 | switch (hdspm->io_type) { | |
6847 | case AES32: | |
6848 | if (hdspm->tco) { | |
6849 | hdspm->texts_autosync = texts_autosync_aes_tco; | |
6850 | hdspm->texts_autosync_items = 10; | |
6851 | } else { | |
6852 | hdspm->texts_autosync = texts_autosync_aes; | |
6853 | hdspm->texts_autosync_items = 9; | |
6854 | } | |
6855 | break; | |
6856 | ||
6857 | case MADI: | |
6858 | if (hdspm->tco) { | |
6859 | hdspm->texts_autosync = texts_autosync_madi_tco; | |
6860 | hdspm->texts_autosync_items = 4; | |
6861 | } else { | |
6862 | hdspm->texts_autosync = texts_autosync_madi; | |
6863 | hdspm->texts_autosync_items = 3; | |
6864 | } | |
6865 | break; | |
6866 | ||
6867 | case MADIface: | |
6868 | ||
6869 | break; | |
6870 | ||
6871 | case RayDAT: | |
6872 | if (hdspm->tco) { | |
6873 | hdspm->texts_autosync = texts_autosync_raydat_tco; | |
6874 | hdspm->texts_autosync_items = 9; | |
6875 | } else { | |
6876 | hdspm->texts_autosync = texts_autosync_raydat; | |
6877 | hdspm->texts_autosync_items = 8; | |
6878 | } | |
6879 | break; | |
6880 | ||
6881 | case AIO: | |
6882 | if (hdspm->tco) { | |
6883 | hdspm->texts_autosync = texts_autosync_aio_tco; | |
6884 | hdspm->texts_autosync_items = 6; | |
6885 | } else { | |
6886 | hdspm->texts_autosync = texts_autosync_aio; | |
6887 | hdspm->texts_autosync_items = 5; | |
6888 | } | |
6889 | break; | |
6890 | ||
6891 | } | |
6892 | ||
6893 | tasklet_init(&hdspm->midi_tasklet, | |
6894 | hdspm_midi_tasklet, (unsigned long) hdspm); | |
763f356c | 6895 | |
f7de8ba3 AK |
6896 | |
6897 | if (hdspm->io_type != MADIface) { | |
6898 | hdspm->serial = (hdspm_read(hdspm, | |
6899 | HDSPM_midiStatusIn0)>>8) & 0xFFFFFF; | |
6900 | /* id contains either a user-provided value or the default | |
6901 | * NULL. If it's the default, we're safe to | |
6902 | * fill card->id with the serial number. | |
6903 | * | |
6904 | * If the serial number is 0xFFFFFF, then we're dealing with | |
6905 | * an old PCI revision that comes without a sane number. In | |
6906 | * this case, we don't set card->id to avoid collisions | |
6907 | * when running with multiple cards. | |
6908 | */ | |
6909 | if (NULL == id[hdspm->dev] && hdspm->serial != 0xFFFFFF) { | |
6910 | sprintf(card->id, "HDSPMx%06x", hdspm->serial); | |
6911 | snd_card_set_id(card, card->id); | |
6912 | } | |
6913 | } | |
6914 | ||
763f356c | 6915 | snd_printdd("create alsa devices.\n"); |
ef5fa1a4 TI |
6916 | err = snd_hdspm_create_alsa_devices(card, hdspm); |
6917 | if (err < 0) | |
763f356c TI |
6918 | return err; |
6919 | ||
6920 | snd_hdspm_initialize_midi_flush(hdspm); | |
6921 | ||
6922 | return 0; | |
6923 | } | |
6924 | ||
0dca1793 | 6925 | |
98274f07 | 6926 | static int snd_hdspm_free(struct hdspm * hdspm) |
763f356c TI |
6927 | { |
6928 | ||
6929 | if (hdspm->port) { | |
6930 | ||
6931 | /* stop th audio, and cancel all interrupts */ | |
6932 | hdspm->control_register &= | |
ef5fa1a4 | 6933 | ~(HDSPM_Start | HDSPM_AudioInterruptEnable | |
0dca1793 AK |
6934 | HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable | |
6935 | HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable); | |
763f356c TI |
6936 | hdspm_write(hdspm, HDSPM_controlRegister, |
6937 | hdspm->control_register); | |
6938 | } | |
6939 | ||
6940 | if (hdspm->irq >= 0) | |
6941 | free_irq(hdspm->irq, (void *) hdspm); | |
6942 | ||
fc58422a | 6943 | kfree(hdspm->mixer); |
763f356c TI |
6944 | |
6945 | if (hdspm->iobase) | |
6946 | iounmap(hdspm->iobase); | |
6947 | ||
763f356c TI |
6948 | if (hdspm->port) |
6949 | pci_release_regions(hdspm->pci); | |
6950 | ||
6951 | pci_disable_device(hdspm->pci); | |
6952 | return 0; | |
6953 | } | |
6954 | ||
0dca1793 | 6955 | |
98274f07 | 6956 | static void snd_hdspm_card_free(struct snd_card *card) |
763f356c | 6957 | { |
ef5fa1a4 | 6958 | struct hdspm *hdspm = card->private_data; |
763f356c TI |
6959 | |
6960 | if (hdspm) | |
6961 | snd_hdspm_free(hdspm); | |
6962 | } | |
6963 | ||
0dca1793 | 6964 | |
763f356c TI |
6965 | static int __devinit snd_hdspm_probe(struct pci_dev *pci, |
6966 | const struct pci_device_id *pci_id) | |
6967 | { | |
6968 | static int dev; | |
98274f07 TI |
6969 | struct hdspm *hdspm; |
6970 | struct snd_card *card; | |
763f356c TI |
6971 | int err; |
6972 | ||
6973 | if (dev >= SNDRV_CARDS) | |
6974 | return -ENODEV; | |
6975 | if (!enable[dev]) { | |
6976 | dev++; | |
6977 | return -ENOENT; | |
6978 | } | |
6979 | ||
e58de7ba | 6980 | err = snd_card_create(index[dev], id[dev], |
0dca1793 | 6981 | THIS_MODULE, sizeof(struct hdspm), &card); |
e58de7ba TI |
6982 | if (err < 0) |
6983 | return err; | |
763f356c | 6984 | |
ef5fa1a4 | 6985 | hdspm = card->private_data; |
763f356c TI |
6986 | card->private_free = snd_hdspm_card_free; |
6987 | hdspm->dev = dev; | |
6988 | hdspm->pci = pci; | |
6989 | ||
c187c041 TI |
6990 | snd_card_set_dev(card, &pci->dev); |
6991 | ||
0dca1793 | 6992 | err = snd_hdspm_create(card, hdspm); |
ef5fa1a4 | 6993 | if (err < 0) { |
763f356c TI |
6994 | snd_card_free(card); |
6995 | return err; | |
6996 | } | |
6997 | ||
0dca1793 AK |
6998 | if (hdspm->io_type != MADIface) { |
6999 | sprintf(card->shortname, "%s_%x", | |
7000 | hdspm->card_name, | |
7d53a631 | 7001 | hdspm->serial); |
0dca1793 AK |
7002 | sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d", |
7003 | hdspm->card_name, | |
7d53a631 | 7004 | hdspm->serial, |
0dca1793 AK |
7005 | hdspm->port, hdspm->irq); |
7006 | } else { | |
7007 | sprintf(card->shortname, "%s", hdspm->card_name); | |
7008 | sprintf(card->longname, "%s at 0x%lx, irq %d", | |
7009 | hdspm->card_name, hdspm->port, hdspm->irq); | |
7010 | } | |
763f356c | 7011 | |
ef5fa1a4 TI |
7012 | err = snd_card_register(card); |
7013 | if (err < 0) { | |
763f356c TI |
7014 | snd_card_free(card); |
7015 | return err; | |
7016 | } | |
7017 | ||
7018 | pci_set_drvdata(pci, card); | |
7019 | ||
7020 | dev++; | |
7021 | return 0; | |
7022 | } | |
7023 | ||
7024 | static void __devexit snd_hdspm_remove(struct pci_dev *pci) | |
7025 | { | |
7026 | snd_card_free(pci_get_drvdata(pci)); | |
7027 | pci_set_drvdata(pci, NULL); | |
7028 | } | |
7029 | ||
e9f66d9b | 7030 | static struct pci_driver hdspm_driver = { |
3733e424 | 7031 | .name = KBUILD_MODNAME, |
763f356c TI |
7032 | .id_table = snd_hdspm_ids, |
7033 | .probe = snd_hdspm_probe, | |
7034 | .remove = __devexit_p(snd_hdspm_remove), | |
7035 | }; | |
7036 | ||
e9f66d9b | 7037 | module_pci_driver(hdspm_driver); |