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[ALSA] hda-intel - Coding style fixes
[deliverable/linux.git] / sound / pci / rme9652 / hdspm.c
CommitLineData
763f356c
TI		 1/* -*- linux-c -*-
2 *
3 * ALSA driver for RME Hammerfall DSP MADI audio interface(s)
4 *
5 * Copyright (c) 2003 Winfried Ritsch (IEM)
6 * code based on hdsp.c Paul Davis
7 * Marcus Andersson
8 * Thomas Charbonnel
3cee5a60
RB		 9 * Modified 2006-06-01 for AES32 support by Remy Bruno
10 * <remy.bruno@trinnov.com>
763f356c
TI		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 */
27#include <sound/driver.h>
28#include <linux/init.h>
29#include <linux/delay.h>
30#include <linux/interrupt.h>
31#include <linux/moduleparam.h>
32#include <linux/slab.h>
33#include <linux/pci.h>
34#include <asm/io.h>
35
36#include <sound/core.h>
37#include <sound/control.h>
38#include <sound/pcm.h>
39#include <sound/info.h>
40#include <sound/asoundef.h>
41#include <sound/rawmidi.h>
42#include <sound/hwdep.h>
43#include <sound/initval.h>
44
45#include <sound/hdspm.h>
46
47static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
48static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
49static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
50
51/* Disable precise pointer at start */
52static int precise_ptr[SNDRV_CARDS];
53
54/* Send all playback to line outs */
55static int line_outs_monitor[SNDRV_CARDS];
56
57/* Enable Analog Outs on Channel 63/64 by default */
58static int enable_monitor[SNDRV_CARDS];
59
60module_param_array(index, int, NULL, 0444);
61MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
62
63module_param_array(id, charp, NULL, 0444);
64MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
65
66module_param_array(enable, bool, NULL, 0444);
67MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
68
69module_param_array(precise_ptr, bool, NULL, 0444);
e8da2fbc 70MODULE_PARM_DESC(precise_ptr, "Enable or disable precise pointer.");
763f356c
TI		 71
72module_param_array(line_outs_monitor, bool, NULL, 0444);
73MODULE_PARM_DESC(line_outs_monitor,
74 "Send playback streams to analog outs by default.");
75
76module_param_array(enable_monitor, bool, NULL, 0444);
77MODULE_PARM_DESC(enable_monitor,
78 "Enable Analog Out on Channel 63/64 by default.");
79
80MODULE_AUTHOR
81 ("Winfried Ritsch <ritsch_AT_iem.at>, Paul Davis <paul@linuxaudiosystems.com>, "
3cee5a60
RB		 82 "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
83 "Remy Bruno <remy.bruno@trinnov.com>");
763f356c
TI		 84MODULE_DESCRIPTION("RME HDSPM");
85MODULE_LICENSE("GPL");
86MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
87
88/* --- Write registers. ---
89 These are defined as byte-offsets from the iobase value. */
90
91#define HDSPM_controlRegister 64
92#define HDSPM_interruptConfirmation 96
93#define HDSPM_control2Reg 256 /* not in specs ???????? */
ffb2c3c0 94#define HDSPM_freqReg 256 /* for AES32 */
763f356c
TI		 95#define HDSPM_midiDataOut0 352 /* just believe in old code */
96#define HDSPM_midiDataOut1 356
ffb2c3c0 97#define HDSPM_eeprom_wr 384 /* for AES32 */
763f356c
TI		 98
99/* DMA enable for 64 channels, only Bit 0 is relevant */
100#define HDSPM_outputEnableBase 512 /* 512-767 input DMA */
101#define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */
102
103/* 16 page addresses for each of the 64 channels DMA buffer in and out
104 (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
105#define HDSPM_pageAddressBufferOut 8192
106#define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4)
107
108#define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */
109
110#define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */
111
112/* --- Read registers. ---
113 These are defined as byte-offsets from the iobase value */
114#define HDSPM_statusRegister 0
3cee5a60
RB		 115/*#define HDSPM_statusRegister2 96 */
116/* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
117 * offset 192, for AES32 *and* MADI
118 * => need to check that offset 192 is working on MADI */
119#define HDSPM_statusRegister2 192
120#define HDSPM_timecodeRegister 128
763f356c
TI		 121
122#define HDSPM_midiDataIn0 360
123#define HDSPM_midiDataIn1 364
124
125/* status is data bytes in MIDI-FIFO (0-128) */
126#define HDSPM_midiStatusOut0 384
127#define HDSPM_midiStatusOut1 388
128#define HDSPM_midiStatusIn0 392
129#define HDSPM_midiStatusIn1 396
130
131
132/* the meters are regular i/o-mapped registers, but offset
133 considerably from the rest. the peak registers are reset
134 when read; the least-significant 4 bits are full-scale counters;
135 the actual peak value is in the most-significant 24 bits.
136*/
137#define HDSPM_MADI_peakrmsbase 4096 /* 4096-8191 2x64x32Bit Meters */
138
139/* --- Control Register bits --------- */
140#define HDSPM_Start (1<<0) /* start engine */
141
142#define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */
143#define HDSPM_Latency1 (1<<2) /* where n is defined */
144#define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */
145
146#define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */
147
148#define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
149
150#define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
151#define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */
152#define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
3cee5a60 153#define HDSPM_QuadSpeed (1<<31) /* quad speed bit */
763f356c 154
3cee5a60 155#define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
763f356c 156#define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1,
3cee5a60
RB		 157 56channelMODE=0 */ /* MADI ONLY*/
158#define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */
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TI		 159
160#define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode,
3cee5a60
RB		 161 0=off, 1=on */ /* MADI ONLY */
162#define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
763f356c 163
3cee5a60 164#define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax */ /* MADI ONLY*/
763f356c
TI		 165#define HDSPM_InputSelect1 (1<<15) /* should be 0 */
166
167#define HDSPM_SyncRef0 (1<<16) /* 0=WOrd, 1=MADI */
3cee5a60
RB		 168#define HDSPM_SyncRef1 (1<<17) /* for AES32: SyncRefN codes the AES # */
169#define HDSPM_SyncRef2 (1<<13)
170#define HDSPM_SyncRef3 (1<<25)
763f356c 171
3cee5a60 172#define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */
763f356c
TI		 173#define HDSPM_clr_tms (1<<19) /* clear track marker, do not use
174 AES additional bits in
175 lower 5 Audiodatabits ??? */
3cee5a60
RB		 176#define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */
177#define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
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TI		 178
179#define HDSPM_Midi0InterruptEnable (1<<22)
180#define HDSPM_Midi1InterruptEnable (1<<23)
181
182#define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
183
3cee5a60
RB		 184#define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
185#define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
186#define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */
187
188#define HDSPM_wclk_sel (1<<30)
763f356c
TI		 189
190/* --- bit helper defines */
191#define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
3cee5a60 192#define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
763f356c
TI		 193#define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1)
194#define HDSPM_InputOptical 0
195#define HDSPM_InputCoaxial (HDSPM_InputSelect0)
3cee5a60 196#define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|HDSPM_SyncRef2|HDSPM_SyncRef3)
763f356c
TI		 197#define HDSPM_SyncRef_Word 0
198#define HDSPM_SyncRef_MADI (HDSPM_SyncRef0)
199
200#define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */
201#define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */
202
203#define HDSPM_Frequency32KHz HDSPM_Frequency0
204#define HDSPM_Frequency44_1KHz HDSPM_Frequency1
205#define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0)
206#define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0)
207#define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
208#define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|HDSPM_Frequency0)
3cee5a60
RB		 209#define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0)
210#define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1)
211#define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|HDSPM_Frequency0)
763f356c
TI		 212
213/* --- for internal discrimination */
214#define HDSPM_CLOCK_SOURCE_AUTOSYNC 0 /* Sample Clock Sources */
215#define HDSPM_CLOCK_SOURCE_INTERNAL_32KHZ 1
216#define HDSPM_CLOCK_SOURCE_INTERNAL_44_1KHZ 2
217#define HDSPM_CLOCK_SOURCE_INTERNAL_48KHZ 3
218#define HDSPM_CLOCK_SOURCE_INTERNAL_64KHZ 4
219#define HDSPM_CLOCK_SOURCE_INTERNAL_88_2KHZ 5
220#define HDSPM_CLOCK_SOURCE_INTERNAL_96KHZ 6
221#define HDSPM_CLOCK_SOURCE_INTERNAL_128KHZ 7
222#define HDSPM_CLOCK_SOURCE_INTERNAL_176_4KHZ 8
223#define HDSPM_CLOCK_SOURCE_INTERNAL_192KHZ 9
224
225/* Synccheck Status */
226#define HDSPM_SYNC_CHECK_NO_LOCK 0
227#define HDSPM_SYNC_CHECK_LOCK 1
228#define HDSPM_SYNC_CHECK_SYNC 2
229
230/* AutoSync References - used by "autosync_ref" control switch */
231#define HDSPM_AUTOSYNC_FROM_WORD 0
232#define HDSPM_AUTOSYNC_FROM_MADI 1
233#define HDSPM_AUTOSYNC_FROM_NONE 2
234
235/* Possible sources of MADI input */
236#define HDSPM_OPTICAL 0 /* optical */
237#define HDSPM_COAXIAL 1 /* BNC */
238
239#define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask)
240#define hdspm_decode_latency(x) (((x) & HDSPM_LatencyMask)>>1)
241
242#define hdspm_encode_in(x) (((x)&0x3)<<14)
243#define hdspm_decode_in(x) (((x)>>14)&0x3)
244
245/* --- control2 register bits --- */
246#define HDSPM_TMS (1<<0)
247#define HDSPM_TCK (1<<1)
248#define HDSPM_TDI (1<<2)
249#define HDSPM_JTAG (1<<3)
250#define HDSPM_PWDN (1<<4)
251#define HDSPM_PROGRAM (1<<5)
252#define HDSPM_CONFIG_MODE_0 (1<<6)
253#define HDSPM_CONFIG_MODE_1 (1<<7)
254/*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/
255#define HDSPM_BIGENDIAN_MODE (1<<9)
256#define HDSPM_RD_MULTIPLE (1<<10)
257
3cee5a60
RB		 258/* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
259 that do not conflict with specific bits for AES32 seem to be valid also for the AES32 */
763f356c
TI		 260#define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */
261#define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn. MODE=0 */
262#define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1 (like inp0) */
263#define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */
264
265#define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
266 /* since 64byte accurate last 6 bits
267 are not used */
268
269#define HDSPM_madiSync (1<<18) /* MADI is in sync */
270#define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
271
272#define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */
273#define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */
274#define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */
275#define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */
276
277#define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with Interrupt */
278#define HDSPM_midi0IRQPending (1<<30) /* MIDI IRQ is pending */
279#define HDSPM_midi1IRQPending (1<<31) /* and aktiv */
280
281/* --- status bit helpers */
282#define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2|HDSPM_madiFreq3)
283#define HDSPM_madiFreq32 (HDSPM_madiFreq0)
284#define HDSPM_madiFreq44_1 (HDSPM_madiFreq1)
285#define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1)
286#define HDSPM_madiFreq64 (HDSPM_madiFreq2)
287#define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2)
288#define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2)
289#define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
290#define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
291#define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0)
292
3cee5a60 293/* Status2 Register bits */ /* MADI ONLY */
763f356c
TI		 294
295#define HDSPM_version0 (1<<0) /* not realy defined but I guess */
296#define HDSPM_version1 (1<<1) /* in former cards it was ??? */
297#define HDSPM_version2 (1<<2)
298
299#define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */
300#define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */
301
302#define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */
303#define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */
304#define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, */
305/* missing Bit for 111=128, 1000=176.4, 1001=192 */
306
307#define HDSPM_SelSyncRef0 (1<<8) /* Sync Source in slave mode */
308#define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */
309#define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */
310
311#define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
312
313#define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
314#define HDSPM_wcFreq32 (HDSPM_wc_freq0)
315#define HDSPM_wcFreq44_1 (HDSPM_wc_freq1)
316#define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1)
317#define HDSPM_wcFreq64 (HDSPM_wc_freq2)
318#define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2)
319#define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2)
320
321
322#define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|HDSPM_SelSyncRef2)
323#define HDSPM_SelSyncRef_WORD 0
324#define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0)
325#define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|HDSPM_SelSyncRef2)
326
3cee5a60
RB		 327/*
328 For AES32, bits for status, status2 and timecode are different
329*/
330/* status */
331#define HDSPM_AES32_wcLock 0x0200000
332#define HDSPM_AES32_wcFreq_bit 22
333/* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
334 HDSPM_bit2freq */
335#define HDSPM_AES32_syncref_bit 16
336/* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
337
338#define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
339#define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
340#define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
341#define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
342#define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
343#define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
344#define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
345#define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
346#define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
347#define HDSPM_AES32_AUTOSYNC_FROM_NONE -1
348
349/* status2 */
350/* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
351#define HDSPM_LockAES 0x80
352#define HDSPM_LockAES1 0x80
353#define HDSPM_LockAES2 0x40
354#define HDSPM_LockAES3 0x20
355#define HDSPM_LockAES4 0x10
356#define HDSPM_LockAES5 0x8
357#define HDSPM_LockAES6 0x4
358#define HDSPM_LockAES7 0x2
359#define HDSPM_LockAES8 0x1
360/*
361 Timecode
362 After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
363 AES i+1
364 bits 3210
365 0001 32kHz
366 0010 44.1kHz
367 0011 48kHz
368 0100 64kHz
369 0101 88.2kHz
370 0110 96kHz
371 0111 128kHz
372 1000 176.4kHz
373 1001 192kHz
374 NB: Timecode register doesn't seem to work on AES32 card revision 230
375*/
376
763f356c
TI		 377/* Mixer Values */
378#define UNITY_GAIN 32768 /* = 65536/2 */
379#define MINUS_INFINITY_GAIN 0
380
763f356c
TI		 381/* Number of channels for different Speed Modes */
382#define MADI_SS_CHANNELS 64
383#define MADI_DS_CHANNELS 32
384#define MADI_QS_CHANNELS 16
385
386/* the size of a substream (1 mono data stream) */
387#define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024)
388#define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
389
390/* the size of the area we need to allocate for DMA transfers. the
391 size is the same regardless of the number of channels, and
392 also the latency to use.
393 for one direction !!!
394*/
ffb2c3c0 395#define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
763f356c
TI		 396#define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
397
3cee5a60
RB		 398/* revisions >= 230 indicate AES32 card */
399#define HDSPM_AESREVISION 230
400
98274f07
TI		 401struct hdspm_midi {
402 struct hdspm *hdspm;
763f356c 403 int id;
98274f07
TI		 404 struct snd_rawmidi *rmidi;
405 struct snd_rawmidi_substream *input;
406 struct snd_rawmidi_substream *output;
763f356c
TI		 407 char istimer; /* timer in use */
408 struct timer_list timer;
409 spinlock_t lock;
410 int pending;
411};
412
98274f07 413struct hdspm {
763f356c 414 spinlock_t lock;
98274f07
TI		 415 struct snd_pcm_substream *capture_substream; /* only one playback */
416 struct snd_pcm_substream *playback_substream; /* and/or capture stream */
763f356c
TI		 417
418 char *card_name; /* for procinfo */
3cee5a60
RB		 419 unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
420
421 unsigned char is_aes32; /* indicates if card is AES32 */
763f356c
TI		 422
423 int precise_ptr; /* use precise pointers, to be tested */
424 int monitor_outs; /* set up monitoring outs init flag */
425
426 u32 control_register; /* cached value */
427 u32 control2_register; /* cached value */
428
98274f07 429 struct hdspm_midi midi[2];
763f356c
TI		 430 struct tasklet_struct midi_tasklet;
431
432 size_t period_bytes;
433 unsigned char ss_channels; /* channels of card in single speed */
434 unsigned char ds_channels; /* Double Speed */
435 unsigned char qs_channels; /* Quad Speed */
436
437 unsigned char *playback_buffer; /* suitably aligned address */
438 unsigned char *capture_buffer; /* suitably aligned address */
439
440 pid_t capture_pid; /* process id which uses capture */
441 pid_t playback_pid; /* process id which uses capture */
442 int running; /* running status */
443
444 int last_external_sample_rate; /* samplerate mystic ... */
445 int last_internal_sample_rate;
446 int system_sample_rate;
447
448 char *channel_map; /* channel map for DS and Quadspeed */
449
450 int dev; /* Hardware vars... */
451 int irq;
452 unsigned long port;
453 void __iomem *iobase;
454
455 int irq_count; /* for debug */
456
98274f07
TI		 457 struct snd_card *card; /* one card */
458 struct snd_pcm *pcm; /* has one pcm */
459 struct snd_hwdep *hwdep; /* and a hwdep for additional ioctl */
763f356c
TI		 460 struct pci_dev *pci; /* and an pci info */
461
462 /* Mixer vars */
98274f07
TI		 463 struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS]; /* fast alsa mixer */
464 struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS]; /* but input to much, so not used */
465 struct hdspm_mixer *mixer; /* full mixer accessable over mixer ioctl or hwdep-device */
763f356c
TI		 466
467};
468
469/* These tables map the ALSA channels 1..N to the channels that we
470 need to use in order to find the relevant channel buffer. RME
471 refer to this kind of mapping as between "the ADAT channel and
472 the DMA channel." We index it using the logical audio channel,
473 and the value is the DMA channel (i.e. channel buffer number)
474 where the data for that channel can be read/written from/to.
475*/
476
477static char channel_map_madi_ss[HDSPM_MAX_CHANNELS] = {
478 0, 1, 2, 3, 4, 5, 6, 7,
479 8, 9, 10, 11, 12, 13, 14, 15,
480 16, 17, 18, 19, 20, 21, 22, 23,
481 24, 25, 26, 27, 28, 29, 30, 31,
482 32, 33, 34, 35, 36, 37, 38, 39,
483 40, 41, 42, 43, 44, 45, 46, 47,
484 48, 49, 50, 51, 52, 53, 54, 55,
485 56, 57, 58, 59, 60, 61, 62, 63
486};
487
763f356c 488
396c9b92 489static struct pci_device_id snd_hdspm_ids[] __devinitdata = {
763f356c
TI		 490 {
491 .vendor = PCI_VENDOR_ID_XILINX,
492 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
493 .subvendor = PCI_ANY_ID,
494 .subdevice = PCI_ANY_ID,
495 .class = 0,
496 .class_mask = 0,
497 .driver_data = 0},
498 {0,}
499};
500
501MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
502
503/* prototypes */
98274f07
TI		 504static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
505 struct hdspm * hdspm);
506static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
507 struct hdspm * hdspm);
508
509static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm);
510static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm);
511static int hdspm_autosync_ref(struct hdspm * hdspm);
512static int snd_hdspm_set_defaults(struct hdspm * hdspm);
513static void hdspm_set_sgbuf(struct hdspm * hdspm, struct snd_sg_buf *sgbuf,
763f356c
TI		 514 unsigned int reg, int channels);
515
3cee5a60
RB		 516static inline int HDSPM_bit2freq(int n)
517{
518 static int bit2freq_tab[] = { 0, 32000, 44100, 48000, 64000, 88200,
519 96000, 128000, 176400, 192000 };
520 if (n < 1 || n > 9)
521 return 0;
522 return bit2freq_tab[n];
523}
524
763f356c
TI		 525/* Write/read to/from HDSPM with Adresses in Bytes
526 not words but only 32Bit writes are allowed */
527
98274f07 528static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
763f356c
TI		 529 unsigned int val)
530{
531 writel(val, hdspm->iobase + reg);
532}
533
98274f07 534static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
763f356c
TI		 535{
536 return readl(hdspm->iobase + reg);
537}
538
539/* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
540 mixer is write only on hardware so we have to cache him for read
541 each fader is a u32, but uses only the first 16 bit */
542
98274f07 543static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
763f356c
TI		 544 unsigned int in)
545{
5bab2482 546 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
763f356c
TI		 547 return 0;
548
549 return hdspm->mixer->ch[chan].in[in];
550}
551
98274f07 552static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
763f356c
TI		 553 unsigned int pb)
554{
5bab2482 555 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
763f356c
TI		 556 return 0;
557 return hdspm->mixer->ch[chan].pb[pb];
558}
559
98274f07 560static inline int hdspm_write_in_gain(struct hdspm * hdspm, unsigned int chan,
763f356c
TI		 561 unsigned int in, unsigned short data)
562{
563 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
564 return -1;
565
566 hdspm_write(hdspm,
567 HDSPM_MADI_mixerBase +
568 ((in + 128 * chan) * sizeof(u32)),
569 (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
570 return 0;
571}
572
98274f07 573static inline int hdspm_write_pb_gain(struct hdspm * hdspm, unsigned int chan,
763f356c
TI		 574 unsigned int pb, unsigned short data)
575{
576 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
577 return -1;
578
579 hdspm_write(hdspm,
580 HDSPM_MADI_mixerBase +
581 ((64 + pb + 128 * chan) * sizeof(u32)),
582 (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
583 return 0;
584}
585
586
587/* enable DMA for specific channels, now available for DSP-MADI */
98274f07 588static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
763f356c
TI		 589{
590 hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
591}
592
98274f07 593static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
763f356c
TI		 594{
595 hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
596}
597
598/* check if same process is writing and reading */
98274f07 599static inline int snd_hdspm_use_is_exclusive(struct hdspm * hdspm)
763f356c
TI		 600{
601 unsigned long flags;
602 int ret = 1;
603
604 spin_lock_irqsave(&hdspm->lock, flags);
605 if ((hdspm->playback_pid != hdspm->capture_pid) &&
606 (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
607 ret = 0;
608 }
609 spin_unlock_irqrestore(&hdspm->lock, flags);
610 return ret;
611}
612
613/* check for external sample rate */
98274f07 614static inline int hdspm_external_sample_rate(struct hdspm * hdspm)
763f356c 615{
3cee5a60
RB		 616 if (hdspm->is_aes32) {
617 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
618 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
619 unsigned int timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
620
621 int syncref = hdspm_autosync_ref(hdspm);
622
623 if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD &&
624 status & HDSPM_AES32_wcLock)
625 return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF);
626 if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 &&
627 syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 &&
628 status2 & (HDSPM_LockAES >>
629 (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)))
630 return HDSPM_bit2freq((timecode >>
631 (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF);
632 return 0;
633 } else {
634 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
635 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
636 unsigned int rate_bits;
637 int rate = 0;
763f356c 638
3cee5a60
RB		 639 /* if wordclock has synced freq and wordclock is valid */
640 if ((status2 & HDSPM_wcLock) != 0 &&
641 (status & HDSPM_SelSyncRef0) == 0) {
763f356c 642
3cee5a60 643 rate_bits = status2 & HDSPM_wcFreqMask;
763f356c 644
3cee5a60
RB		 645 switch (rate_bits) {
646 case HDSPM_wcFreq32:
647 rate = 32000;
648 break;
649 case HDSPM_wcFreq44_1:
650 rate = 44100;
651 break;
652 case HDSPM_wcFreq48:
653 rate = 48000;
654 break;
655 case HDSPM_wcFreq64:
656 rate = 64000;
657 break;
658 case HDSPM_wcFreq88_2:
659 rate = 88200;
660 break;
661 case HDSPM_wcFreq96:
662 rate = 96000;
663 break;
664 /* Quadspeed Bit missing ???? */
665 default:
666 rate = 0;
667 break;
668 }
763f356c 669 }
763f356c 670
3cee5a60
RB		 671 /* if rate detected and Syncref is Word than have it, word has priority to MADI */
672 if (rate != 0 &&
673 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
674 return rate;
763f356c 675
3cee5a60
RB		 676 /* maby a madi input (which is taken if sel sync is madi) */
677 if (status & HDSPM_madiLock) {
678 rate_bits = status & HDSPM_madiFreqMask;
763f356c 679
3cee5a60
RB		 680 switch (rate_bits) {
681 case HDSPM_madiFreq32:
682 rate = 32000;
683 break;
684 case HDSPM_madiFreq44_1:
685 rate = 44100;
686 break;
687 case HDSPM_madiFreq48:
688 rate = 48000;
689 break;
690 case HDSPM_madiFreq64:
691 rate = 64000;
692 break;
693 case HDSPM_madiFreq88_2:
694 rate = 88200;
695 break;
696 case HDSPM_madiFreq96:
697 rate = 96000;
698 break;
699 case HDSPM_madiFreq128:
700 rate = 128000;
701 break;
702 case HDSPM_madiFreq176_4:
703 rate = 176400;
704 break;
705 case HDSPM_madiFreq192:
706 rate = 192000;
707 break;
708 default:
709 rate = 0;
710 break;
711 }
763f356c 712 }
3cee5a60 713 return rate;
763f356c 714 }
763f356c
TI		 715}
716
717/* Latency function */
98274f07 718static inline void hdspm_compute_period_size(struct hdspm * hdspm)
763f356c
TI		 719{
720 hdspm->period_bytes =
721 1 << ((hdspm_decode_latency(hdspm->control_register) + 8));
722}
723
98274f07 724static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm * hdspm)
763f356c
TI		 725{
726 int position;
727
728 position = hdspm_read(hdspm, HDSPM_statusRegister);
729
730 if (!hdspm->precise_ptr) {
731 return (position & HDSPM_BufferID) ? (hdspm->period_bytes /
732 4) : 0;
733 }
734
735 /* hwpointer comes in bytes and is 64Bytes accurate (by docu since PCI Burst)
736 i have experimented that it is at most 64 Byte to much for playing
737 so substraction of 64 byte should be ok for ALSA, but use it only
738 for application where you know what you do since if you come to
739 near with record pointer it can be a disaster */
740
741 position &= HDSPM_BufferPositionMask;
742 position = ((position - 64) % (2 * hdspm->period_bytes)) / 4;
743
744 return position;
745}
746
747
98274f07 748static inline void hdspm_start_audio(struct hdspm * s)
763f356c
TI		 749{
750 s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
751 hdspm_write(s, HDSPM_controlRegister, s->control_register);
752}
753
98274f07 754static inline void hdspm_stop_audio(struct hdspm * s)
763f356c
TI		 755{
756 s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
757 hdspm_write(s, HDSPM_controlRegister, s->control_register);
758}
759
760/* should I silence all or only opened ones ? doit all for first even is 4MB*/
98274f07 761static inline void hdspm_silence_playback(struct hdspm * hdspm)
763f356c
TI		 762{
763 int i;
764 int n = hdspm->period_bytes;
765 void *buf = hdspm->playback_buffer;
766
3cee5a60
RB		 767 if (buf == NULL)
768 return;
763f356c
TI		 769
770 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
771 memset(buf, 0, n);
772 buf += HDSPM_CHANNEL_BUFFER_BYTES;
773 }
774}
775
98274f07 776static int hdspm_set_interrupt_interval(struct hdspm * s, unsigned int frames)
763f356c
TI		 777{
778 int n;
779
780 spin_lock_irq(&s->lock);
781
782 frames >>= 7;
783 n = 0;
784 while (frames) {
785 n++;
786 frames >>= 1;
787 }
788 s->control_register &= ~HDSPM_LatencyMask;
789 s->control_register |= hdspm_encode_latency(n);
790
791 hdspm_write(s, HDSPM_controlRegister, s->control_register);
792
793 hdspm_compute_period_size(s);
794
795 spin_unlock_irq(&s->lock);
796
797 return 0;
798}
799
ffb2c3c0
RB		 800static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
801{
802 u64 n;
803 u32 r;
804
805 if (rate >= 112000)
806 rate /= 4;
807 else if (rate >= 56000)
808 rate /= 2;
809
810 /* RME says n = 104857600000000, but in the windows MADI driver, I see:
811// return 104857600000000 / rate; // 100 MHz
812 return 110100480000000 / rate; // 105 MHz
813 */
814 //n = 104857600000000ULL; /* = 2^20 * 10^8 */
815 n = 110100480000000ULL; /* Value checked for AES32 and MADI */
816 div64_32(&n, rate, &r);
817 /* n should be less than 2^32 for being written to FREQ register */
818 snd_assert((n >> 32) == 0);
819 hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
820}
763f356c
TI		 821
822/* dummy set rate lets see what happens */
98274f07 823static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
763f356c
TI		 824{
825 int reject_if_open = 0;
826 int current_rate;
827 int rate_bits;
828 int not_set = 0;
3cee5a60 829 int is_single, is_double, is_quad;
763f356c
TI		 830
831 /* ASSUMPTION: hdspm->lock is either set, or there is no need for
832 it (e.g. during module initialization).
833 */
834
835 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
836
837 /* SLAVE --- */
838 if (called_internally) {
839
840 /* request from ctl or card initialization
841 just make a warning an remember setting
842 for future master mode switching */
843
844 snd_printk
845 (KERN_WARNING "HDSPM: Warning: device is not running as a clock master.\n");
846 not_set = 1;
847 } else {
848
849 /* hw_param request while in AutoSync mode */
850 int external_freq =
851 hdspm_external_sample_rate(hdspm);
852
853 if ((hdspm_autosync_ref(hdspm) ==
854 HDSPM_AUTOSYNC_FROM_NONE)) {
855
856 snd_printk(KERN_WARNING "HDSPM: Detected no Externel Sync \n");
857 not_set = 1;
858
859 } else if (rate != external_freq) {
860
861 snd_printk
862 (KERN_WARNING "HDSPM: Warning: No AutoSync source for requested rate\n");
863 not_set = 1;
864 }
865 }
866 }
867
868 current_rate = hdspm->system_sample_rate;
869
870 /* Changing between Singe, Double and Quad speed is not
871 allowed if any substreams are open. This is because such a change
872 causes a shift in the location of the DMA buffers and a reduction
873 in the number of available buffers.
874
875 Note that a similar but essentially insoluble problem exists for
876 externally-driven rate changes. All we can do is to flag rate
877 changes in the read/write routines.
878 */
879
3cee5a60
RB		 880 is_single = (current_rate <= 48000);
881 is_double = (current_rate > 48000 && current_rate <= 96000);
882 is_quad = (current_rate > 96000);
883
763f356c
TI		 884 switch (rate) {
885 case 32000:
3cee5a60 886 if (!is_single)
763f356c 887 reject_if_open = 1;
763f356c
TI		 888 rate_bits = HDSPM_Frequency32KHz;
889 break;
890 case 44100:
3cee5a60 891 if (!is_single)
763f356c 892 reject_if_open = 1;
763f356c
TI		 893 rate_bits = HDSPM_Frequency44_1KHz;
894 break;
895 case 48000:
3cee5a60 896 if (!is_single)
763f356c 897 reject_if_open = 1;
763f356c
TI		 898 rate_bits = HDSPM_Frequency48KHz;
899 break;
900 case 64000:
3cee5a60 901 if (!is_double)
763f356c 902 reject_if_open = 1;
763f356c
TI		 903 rate_bits = HDSPM_Frequency64KHz;
904 break;
905 case 88200:
3cee5a60 906 if (!is_double)
763f356c 907 reject_if_open = 1;
763f356c
TI		 908 rate_bits = HDSPM_Frequency88_2KHz;
909 break;
910 case 96000:
3cee5a60 911 if (!is_double)
763f356c 912 reject_if_open = 1;
763f356c
TI		 913 rate_bits = HDSPM_Frequency96KHz;
914 break;
3cee5a60
RB		 915 case 128000:
916 if (!is_quad)
917 reject_if_open = 1;
918 rate_bits = HDSPM_Frequency128KHz;
919 break;
920 case 176400:
921 if (!is_quad)
922 reject_if_open = 1;
923 rate_bits = HDSPM_Frequency176_4KHz;
924 break;
925 case 192000:
926 if (!is_quad)
927 reject_if_open = 1;
928 rate_bits = HDSPM_Frequency192KHz;
929 break;
763f356c
TI		 930 default:
931 return -EINVAL;
932 }
933
934 if (reject_if_open
935 && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
936 snd_printk
937 (KERN_ERR "HDSPM: cannot change between single- and double-speed mode (capture PID = %d, playback PID = %d)\n",
938 hdspm->capture_pid, hdspm->playback_pid);
939 return -EBUSY;
940 }
941
942 hdspm->control_register &= ~HDSPM_FrequencyMask;
943 hdspm->control_register |= rate_bits;
944 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
945
ffb2c3c0
RB		 946 /* For AES32, need to set DDS value in FREQ register
947 For MADI, also apparently */
948 hdspm_set_dds_value(hdspm, rate);
949
950 if (hdspm->is_aes32 && rate != current_rate)
951 hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
952
953 /* For AES32 and for MADI (at least rev 204), channel_map needs to
954 * always be channel_map_madi_ss, whatever the sample rate */
955 hdspm->channel_map = channel_map_madi_ss;
763f356c
TI		 956
957 hdspm->system_sample_rate = rate;
958
959 if (not_set != 0)
960 return -1;
961
962 return 0;
963}
964
965/* mainly for init to 0 on load */
98274f07 966static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
763f356c
TI		 967{
968 int i, j;
969 unsigned int gain =
970 (sgain > UNITY_GAIN) ? UNITY_GAIN : (sgain < 0) ? 0 : sgain;
971
972 for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
973 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
974 hdspm_write_in_gain(hdspm, i, j, gain);
975 hdspm_write_pb_gain(hdspm, i, j, gain);
976 }
977}
978
979/*----------------------------------------------------------------------------
980 MIDI
981 ----------------------------------------------------------------------------*/
982
98274f07 983static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm, int id)
763f356c
TI		 984{
985 /* the hardware already does the relevant bit-mask with 0xff */
986 if (id)
987 return hdspm_read(hdspm, HDSPM_midiDataIn1);
988 else
989 return hdspm_read(hdspm, HDSPM_midiDataIn0);
990}
991
98274f07 992static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id, int val)
763f356c
TI		 993{
994 /* the hardware already does the relevant bit-mask with 0xff */
995 if (id)
996 return hdspm_write(hdspm, HDSPM_midiDataOut1, val);
997 else
998 return hdspm_write(hdspm, HDSPM_midiDataOut0, val);
999}
1000
98274f07 1001static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
763f356c
TI		 1002{
1003 if (id)
1004 return (hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xff);
1005 else
1006 return (hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xff);
1007}
1008
98274f07 1009static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
763f356c
TI		 1010{
1011 int fifo_bytes_used;
1012
1013 if (id)
1014 fifo_bytes_used = hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xff;
1015 else
1016 fifo_bytes_used = hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xff;
1017
1018 if (fifo_bytes_used < 128)
1019 return 128 - fifo_bytes_used;
1020 else
1021 return 0;
1022}
1023
98274f07 1024static inline void snd_hdspm_flush_midi_input (struct hdspm *hdspm, int id)
763f356c
TI		 1025{
1026 while (snd_hdspm_midi_input_available (hdspm, id))
1027 snd_hdspm_midi_read_byte (hdspm, id);
1028}
1029
98274f07 1030static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
763f356c
TI		 1031{
1032 unsigned long flags;
1033 int n_pending;
1034 int to_write;
1035 int i;
1036 unsigned char buf[128];
1037
1038 /* Output is not interrupt driven */
1039
1040 spin_lock_irqsave (&hmidi->lock, flags);
1041 if (hmidi->output) {
1042 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1043 if ((n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm, hmidi->id)) > 0) {
1044 if (n_pending > (int)sizeof (buf))
1045 n_pending = sizeof (buf);
1046
1047 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1048 for (i = 0; i < to_write; ++i)
1049 snd_hdspm_midi_write_byte (hmidi->hdspm, hmidi->id, buf[i]);
1050 }
1051 }
1052 }
1053 }
1054 spin_unlock_irqrestore (&hmidi->lock, flags);
1055 return 0;
1056}
1057
98274f07 1058static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
763f356c
TI		 1059{
1060 unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1061 unsigned long flags;
1062 int n_pending;
1063 int i;
1064
1065 spin_lock_irqsave (&hmidi->lock, flags);
1066 if ((n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id)) > 0) {
1067 if (hmidi->input) {
1068 if (n_pending > (int)sizeof (buf)) {
1069 n_pending = sizeof (buf);
1070 }
1071 for (i = 0; i < n_pending; ++i) {
1072 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm, hmidi->id);
1073 }
1074 if (n_pending) {
1075 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1076 }
1077 } else {
1078 /* flush the MIDI input FIFO */
1079 while (n_pending--) {
1080 snd_hdspm_midi_read_byte (hmidi->hdspm, hmidi->id);
1081 }
1082 }
1083 }
1084 hmidi->pending = 0;
1085 if (hmidi->id) {
1086 hmidi->hdspm->control_register |= HDSPM_Midi1InterruptEnable;
1087 } else {
1088 hmidi->hdspm->control_register |= HDSPM_Midi0InterruptEnable;
1089 }
1090 hdspm_write(hmidi->hdspm, HDSPM_controlRegister, hmidi->hdspm->control_register);
1091 spin_unlock_irqrestore (&hmidi->lock, flags);
1092 return snd_hdspm_midi_output_write (hmidi);
1093}
1094
98274f07 1095static void snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
763f356c 1096{
98274f07
TI		 1097 struct hdspm *hdspm;
1098 struct hdspm_midi *hmidi;
763f356c
TI		 1099 unsigned long flags;
1100 u32 ie;
1101
98274f07 1102 hmidi = (struct hdspm_midi *) substream->rmidi->private_data;
763f356c
TI		 1103 hdspm = hmidi->hdspm;
1104 ie = hmidi->id ? HDSPM_Midi1InterruptEnable : HDSPM_Midi0InterruptEnable;
1105 spin_lock_irqsave (&hdspm->lock, flags);
1106 if (up) {
1107 if (!(hdspm->control_register & ie)) {
1108 snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1109 hdspm->control_register |= ie;
1110 }
1111 } else {
1112 hdspm->control_register &= ~ie;
1113 }
1114
1115 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1116 spin_unlock_irqrestore (&hdspm->lock, flags);
1117}
1118
1119static void snd_hdspm_midi_output_timer(unsigned long data)
1120{
98274f07 1121 struct hdspm_midi *hmidi = (struct hdspm_midi *) data;
763f356c
TI		 1122 unsigned long flags;
1123
1124 snd_hdspm_midi_output_write(hmidi);
1125 spin_lock_irqsave (&hmidi->lock, flags);
1126
1127 /* this does not bump hmidi->istimer, because the
1128 kernel automatically removed the timer when it
1129 expired, and we are now adding it back, thus
1130 leaving istimer wherever it was set before.
1131 */
1132
1133 if (hmidi->istimer) {
1134 hmidi->timer.expires = 1 + jiffies;
1135 add_timer(&hmidi->timer);
1136 }
1137
1138 spin_unlock_irqrestore (&hmidi->lock, flags);
1139}
1140
98274f07 1141static void snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
763f356c 1142{
98274f07 1143 struct hdspm_midi *hmidi;
763f356c
TI		 1144 unsigned long flags;
1145
98274f07 1146 hmidi = (struct hdspm_midi *) substream->rmidi->private_data;
763f356c
TI		 1147 spin_lock_irqsave (&hmidi->lock, flags);
1148 if (up) {
1149 if (!hmidi->istimer) {
1150 init_timer(&hmidi->timer);
1151 hmidi->timer.function = snd_hdspm_midi_output_timer;
1152 hmidi->timer.data = (unsigned long) hmidi;
1153 hmidi->timer.expires = 1 + jiffies;
1154 add_timer(&hmidi->timer);
1155 hmidi->istimer++;
1156 }
1157 } else {
1158 if (hmidi->istimer && --hmidi->istimer <= 0) {
1159 del_timer (&hmidi->timer);
1160 }
1161 }
1162 spin_unlock_irqrestore (&hmidi->lock, flags);
1163 if (up)
1164 snd_hdspm_midi_output_write(hmidi);
1165}
1166
98274f07 1167static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
763f356c 1168{
98274f07 1169 struct hdspm_midi *hmidi;
763f356c 1170
98274f07 1171 hmidi = (struct hdspm_midi *) substream->rmidi->private_data;
763f356c
TI		 1172 spin_lock_irq (&hmidi->lock);
1173 snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
1174 hmidi->input = substream;
1175 spin_unlock_irq (&hmidi->lock);
1176
1177 return 0;
1178}
1179
98274f07 1180static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
763f356c 1181{
98274f07 1182 struct hdspm_midi *hmidi;
763f356c 1183
98274f07 1184 hmidi = (struct hdspm_midi *) substream->rmidi->private_data;
763f356c
TI		 1185 spin_lock_irq (&hmidi->lock);
1186 hmidi->output = substream;
1187 spin_unlock_irq (&hmidi->lock);
1188
1189 return 0;
1190}
1191
98274f07 1192static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
763f356c 1193{
98274f07 1194 struct hdspm_midi *hmidi;
763f356c
TI		 1195
1196 snd_hdspm_midi_input_trigger (substream, 0);
1197
98274f07 1198 hmidi = (struct hdspm_midi *) substream->rmidi->private_data;
763f356c
TI		 1199 spin_lock_irq (&hmidi->lock);
1200 hmidi->input = NULL;
1201 spin_unlock_irq (&hmidi->lock);
1202
1203 return 0;
1204}
1205
98274f07 1206static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
763f356c 1207{
98274f07 1208 struct hdspm_midi *hmidi;
763f356c
TI		 1209
1210 snd_hdspm_midi_output_trigger (substream, 0);
1211
98274f07 1212 hmidi = (struct hdspm_midi *) substream->rmidi->private_data;
763f356c
TI		 1213 spin_lock_irq (&hmidi->lock);
1214 hmidi->output = NULL;
1215 spin_unlock_irq (&hmidi->lock);
1216
1217 return 0;
1218}
1219
98274f07 1220static struct snd_rawmidi_ops snd_hdspm_midi_output =
763f356c
TI		 1221{
1222 .open = snd_hdspm_midi_output_open,
1223 .close = snd_hdspm_midi_output_close,
1224 .trigger = snd_hdspm_midi_output_trigger,
1225};
1226
98274f07 1227static struct snd_rawmidi_ops snd_hdspm_midi_input =
763f356c
TI		 1228{
1229 .open = snd_hdspm_midi_input_open,
1230 .close = snd_hdspm_midi_input_close,
1231 .trigger = snd_hdspm_midi_input_trigger,
1232};
1233
98274f07 1234static int __devinit snd_hdspm_create_midi (struct snd_card *card, struct hdspm *hdspm, int id)
763f356c
TI		 1235{
1236 int err;
1237 char buf[32];
1238
1239 hdspm->midi[id].id = id;
1240 hdspm->midi[id].rmidi = NULL;
1241 hdspm->midi[id].input = NULL;
1242 hdspm->midi[id].output = NULL;
1243 hdspm->midi[id].hdspm = hdspm;
1244 hdspm->midi[id].istimer = 0;
1245 hdspm->midi[id].pending = 0;
1246 spin_lock_init (&hdspm->midi[id].lock);
1247
1248 sprintf (buf, "%s MIDI %d", card->shortname, id+1);
1249 if ((err = snd_rawmidi_new (card, buf, id, 1, 1, &hdspm->midi[id].rmidi)) < 0)
1250 return err;
1251
1252 sprintf (hdspm->midi[id].rmidi->name, "%s MIDI %d", card->id, id+1);
1253 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1254
1255 snd_rawmidi_set_ops (hdspm->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdspm_midi_output);
1256 snd_rawmidi_set_ops (hdspm->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdspm_midi_input);
1257
1258 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1259 SNDRV_RAWMIDI_INFO_INPUT |
1260 SNDRV_RAWMIDI_INFO_DUPLEX;
1261
1262 return 0;
1263}
1264
1265
1266static void hdspm_midi_tasklet(unsigned long arg)
1267{
98274f07 1268 struct hdspm *hdspm = (struct hdspm *)arg;
763f356c
TI		 1269
1270 if (hdspm->midi[0].pending)
1271 snd_hdspm_midi_input_read (&hdspm->midi[0]);
1272 if (hdspm->midi[1].pending)
1273 snd_hdspm_midi_input_read (&hdspm->midi[1]);
1274}
1275
1276
1277/*-----------------------------------------------------------------------------
1278 Status Interface
1279 ----------------------------------------------------------------------------*/
1280
1281/* get the system sample rate which is set */
1282
1283#define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
67ed4161 1284{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
763f356c
TI		 1285 .name = xname, \
1286 .index = xindex, \
1287 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1288 .info = snd_hdspm_info_system_sample_rate, \
1289 .get = snd_hdspm_get_system_sample_rate \
1290}
1291
98274f07
TI		 1292static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
1293 struct snd_ctl_elem_info *uinfo)
763f356c
TI		 1294{
1295 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1296 uinfo->count = 1;
1297 return 0;
1298}
1299
98274f07
TI		 1300static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
1301 struct snd_ctl_elem_value *
763f356c
TI		 1302 ucontrol)
1303{
98274f07 1304 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c
TI		 1305
1306 ucontrol->value.enumerated.item[0] = hdspm->system_sample_rate;
1307 return 0;
1308}
1309
1310#define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
67ed4161 1311{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
763f356c
TI		 1312 .name = xname, \
1313 .index = xindex, \
1314 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1315 .info = snd_hdspm_info_autosync_sample_rate, \
1316 .get = snd_hdspm_get_autosync_sample_rate \
1317}
1318
98274f07
TI		 1319static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
1320 struct snd_ctl_elem_info *uinfo)
763f356c
TI		 1321{
1322 static char *texts[] = { "32000", "44100", "48000",
1323 "64000", "88200", "96000",
1324 "128000", "176400", "192000",
1325 "None"
1326 };
1327 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1328 uinfo->count = 1;
1329 uinfo->value.enumerated.items = 10;
1330 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1331 uinfo->value.enumerated.item =
1332 uinfo->value.enumerated.items - 1;
1333 strcpy(uinfo->value.enumerated.name,
1334 texts[uinfo->value.enumerated.item]);
1335 return 0;
1336}
1337
98274f07
TI		 1338static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
1339 struct snd_ctl_elem_value *
763f356c
TI		 1340 ucontrol)
1341{
98274f07 1342 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c
TI		 1343
1344 switch (hdspm_external_sample_rate(hdspm)) {
1345 case 32000:
1346 ucontrol->value.enumerated.item[0] = 0;
1347 break;
1348 case 44100:
1349 ucontrol->value.enumerated.item[0] = 1;
1350 break;
1351 case 48000:
1352 ucontrol->value.enumerated.item[0] = 2;
1353 break;
1354 case 64000:
1355 ucontrol->value.enumerated.item[0] = 3;
1356 break;
1357 case 88200:
1358 ucontrol->value.enumerated.item[0] = 4;
1359 break;
1360 case 96000:
1361 ucontrol->value.enumerated.item[0] = 5;
1362 break;
1363 case 128000:
1364 ucontrol->value.enumerated.item[0] = 6;
1365 break;
1366 case 176400:
1367 ucontrol->value.enumerated.item[0] = 7;
1368 break;
1369 case 192000:
1370 ucontrol->value.enumerated.item[0] = 8;
1371 break;
1372
1373 default:
1374 ucontrol->value.enumerated.item[0] = 9;
1375 }
1376 return 0;
1377}
1378
1379#define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
67ed4161 1380{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
763f356c
TI		 1381 .name = xname, \
1382 .index = xindex, \
1383 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1384 .info = snd_hdspm_info_system_clock_mode, \
1385 .get = snd_hdspm_get_system_clock_mode, \
1386}
1387
1388
1389
98274f07 1390static int hdspm_system_clock_mode(struct hdspm * hdspm)
763f356c
TI		 1391{
1392 /* Always reflect the hardware info, rme is never wrong !!!! */
1393
1394 if (hdspm->control_register & HDSPM_ClockModeMaster)
1395 return 0;
1396 return 1;
1397}
1398
98274f07
TI		 1399static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
1400 struct snd_ctl_elem_info *uinfo)
763f356c
TI		 1401{
1402 static char *texts[] = { "Master", "Slave" };
1403
1404 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1405 uinfo->count = 1;
1406 uinfo->value.enumerated.items = 2;
1407 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1408 uinfo->value.enumerated.item =
1409 uinfo->value.enumerated.items - 1;
1410 strcpy(uinfo->value.enumerated.name,
1411 texts[uinfo->value.enumerated.item]);
1412 return 0;
1413}
1414
98274f07
TI		 1415static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
1416 struct snd_ctl_elem_value *ucontrol)
763f356c 1417{
98274f07 1418 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c
TI		 1419
1420 ucontrol->value.enumerated.item[0] =
1421 hdspm_system_clock_mode(hdspm);
1422 return 0;
1423}
1424
1425#define HDSPM_CLOCK_SOURCE(xname, xindex) \
67ed4161 1426{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
763f356c
TI		 1427 .name = xname, \
1428 .index = xindex, \
1429 .info = snd_hdspm_info_clock_source, \
1430 .get = snd_hdspm_get_clock_source, \
1431 .put = snd_hdspm_put_clock_source \
1432}
1433
98274f07 1434static int hdspm_clock_source(struct hdspm * hdspm)
763f356c
TI		 1435{
1436 if (hdspm->control_register & HDSPM_ClockModeMaster) {
1437 switch (hdspm->system_sample_rate) {
1438 case 32000:
1439 return 1;
1440 case 44100:
1441 return 2;
1442 case 48000:
1443 return 3;
1444 case 64000:
1445 return 4;
1446 case 88200:
1447 return 5;
1448 case 96000:
1449 return 6;
1450 case 128000:
1451 return 7;
1452 case 176400:
1453 return 8;
1454 case 192000:
1455 return 9;
1456 default:
1457 return 3;
1458 }
1459 } else {
1460 return 0;
1461 }
1462}
1463
98274f07 1464static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
763f356c
TI		 1465{
1466 int rate;
1467 switch (mode) {
1468
1469 case HDSPM_CLOCK_SOURCE_AUTOSYNC:
1470 if (hdspm_external_sample_rate(hdspm) != 0) {
1471 hdspm->control_register &= ~HDSPM_ClockModeMaster;
1472 hdspm_write(hdspm, HDSPM_controlRegister,
1473 hdspm->control_register);
1474 return 0;
1475 }
1476 return -1;
1477 case HDSPM_CLOCK_SOURCE_INTERNAL_32KHZ:
1478 rate = 32000;
1479 break;
1480 case HDSPM_CLOCK_SOURCE_INTERNAL_44_1KHZ:
1481 rate = 44100;
1482 break;
1483 case HDSPM_CLOCK_SOURCE_INTERNAL_48KHZ:
1484 rate = 48000;
1485 break;
1486 case HDSPM_CLOCK_SOURCE_INTERNAL_64KHZ:
1487 rate = 64000;
1488 break;
1489 case HDSPM_CLOCK_SOURCE_INTERNAL_88_2KHZ:
1490 rate = 88200;
1491 break;
1492 case HDSPM_CLOCK_SOURCE_INTERNAL_96KHZ:
1493 rate = 96000;
1494 break;
1495 case HDSPM_CLOCK_SOURCE_INTERNAL_128KHZ:
1496 rate = 128000;
1497 break;
1498 case HDSPM_CLOCK_SOURCE_INTERNAL_176_4KHZ:
1499 rate = 176400;
1500 break;
1501 case HDSPM_CLOCK_SOURCE_INTERNAL_192KHZ:
1502 rate = 192000;
1503 break;
1504
1505 default:
1506 rate = 44100;
1507 }
1508 hdspm->control_register |= HDSPM_ClockModeMaster;
1509 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1510 hdspm_set_rate(hdspm, rate, 1);
1511 return 0;
1512}
1513
98274f07
TI		 1514static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
1515 struct snd_ctl_elem_info *uinfo)
763f356c
TI		 1516{
1517 static char *texts[] = { "AutoSync",
1518 "Internal 32.0 kHz", "Internal 44.1 kHz",
1519 "Internal 48.0 kHz",
1520 "Internal 64.0 kHz", "Internal 88.2 kHz",
1521 "Internal 96.0 kHz",
1522 "Internal 128.0 kHz", "Internal 176.4 kHz",
1523 "Internal 192.0 kHz"
1524 };
1525
1526 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1527 uinfo->count = 1;
1528 uinfo->value.enumerated.items = 10;
1529
1530 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1531 uinfo->value.enumerated.item =
1532 uinfo->value.enumerated.items - 1;
1533
1534 strcpy(uinfo->value.enumerated.name,
1535 texts[uinfo->value.enumerated.item]);
1536
1537 return 0;
1538}
1539
98274f07
TI		 1540static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
1541 struct snd_ctl_elem_value *ucontrol)
763f356c 1542{
98274f07 1543 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c
TI		 1544
1545 ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
1546 return 0;
1547}
1548
98274f07
TI		 1549static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
1550 struct snd_ctl_elem_value *ucontrol)
763f356c 1551{
98274f07 1552 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c
TI		 1553 int change;
1554 int val;
1555
1556 if (!snd_hdspm_use_is_exclusive(hdspm))
1557 return -EBUSY;
1558 val = ucontrol->value.enumerated.item[0];
1559 if (val < 0)
1560 val = 0;
1561 if (val > 6)
1562 val = 6;
1563 spin_lock_irq(&hdspm->lock);
1564 if (val != hdspm_clock_source(hdspm))
1565 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
1566 else
1567 change = 0;
1568 spin_unlock_irq(&hdspm->lock);
1569 return change;
1570}
1571
1572#define HDSPM_PREF_SYNC_REF(xname, xindex) \
67ed4161 1573{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
763f356c
TI		 1574 .name = xname, \
1575 .index = xindex, \
1576 .info = snd_hdspm_info_pref_sync_ref, \
1577 .get = snd_hdspm_get_pref_sync_ref, \
1578 .put = snd_hdspm_put_pref_sync_ref \
1579}
1580
98274f07 1581static int hdspm_pref_sync_ref(struct hdspm * hdspm)
763f356c
TI		 1582{
1583 /* Notice that this looks at the requested sync source,
1584 not the one actually in use.
1585 */
3cee5a60
RB		 1586 if (hdspm->is_aes32) {
1587 switch (hdspm->control_register & HDSPM_SyncRefMask) {
1588 /* number gives AES index, except for 0 which
1589 corresponds to WordClock */
1590 case 0: return 0;
1591 case HDSPM_SyncRef0: return 1;
1592 case HDSPM_SyncRef1: return 2;
1593 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3;
1594 case HDSPM_SyncRef2: return 4;
1595 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5;
1596 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6;
1597 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0: return 7;
1598 case HDSPM_SyncRef3: return 8;
1599 }
1600 } else {
1601 switch (hdspm->control_register & HDSPM_SyncRefMask) {
1602 case HDSPM_SyncRef_Word:
1603 return HDSPM_SYNC_FROM_WORD;
1604 case HDSPM_SyncRef_MADI:
1605 return HDSPM_SYNC_FROM_MADI;
1606 }
763f356c
TI		 1607 }
1608
1609 return HDSPM_SYNC_FROM_WORD;
1610}
1611
98274f07 1612static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
763f356c
TI		 1613{
1614 hdspm->control_register &= ~HDSPM_SyncRefMask;
1615
3cee5a60
RB		 1616 if (hdspm->is_aes32) {
1617 switch (pref) {
1618 case 0:
1619 hdspm->control_register |= 0;
1620 break;
1621 case 1:
1622 hdspm->control_register |= HDSPM_SyncRef0;
1623 break;
1624 case 2:
1625 hdspm->control_register |= HDSPM_SyncRef1;
1626 break;
1627 case 3:
1628 hdspm->control_register |= HDSPM_SyncRef1+HDSPM_SyncRef0;
1629 break;
1630 case 4:
1631 hdspm->control_register |= HDSPM_SyncRef2;
1632 break;
1633 case 5:
1634 hdspm->control_register |= HDSPM_SyncRef2+HDSPM_SyncRef0;
1635 break;
1636 case 6:
1637 hdspm->control_register |= HDSPM_SyncRef2+HDSPM_SyncRef1;
1638 break;
1639 case 7:
1640 hdspm->control_register |= HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
1641 break;
1642 case 8:
1643 hdspm->control_register |= HDSPM_SyncRef3;
1644 break;
1645 default:
1646 return -1;
1647 }
1648 } else {
1649 switch (pref) {
1650 case HDSPM_SYNC_FROM_MADI:
1651 hdspm->control_register |= HDSPM_SyncRef_MADI;
1652 break;
1653 case HDSPM_SYNC_FROM_WORD:
1654 hdspm->control_register |= HDSPM_SyncRef_Word;
1655 break;
1656 default:
1657 return -1;
1658 }
763f356c
TI		 1659 }
1660 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1661 return 0;
1662}
1663
98274f07
TI		 1664static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
1665 struct snd_ctl_elem_info *uinfo)
763f356c 1666{
3cee5a60 1667 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c 1668
3cee5a60
RB		 1669 if (hdspm->is_aes32) {
1670 static char *texts[] = { "Word", "AES1", "AES2", "AES3",
1671 "AES4", "AES5", "AES6", "AES7", "AES8" };
763f356c 1672
3cee5a60
RB		 1673 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1674 uinfo->count = 1;
763f356c 1675
3cee5a60
RB		 1676 uinfo->value.enumerated.items = 9;
1677
1678 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1679 uinfo->value.enumerated.item =
1680 uinfo->value.enumerated.items - 1;
1681 strcpy(uinfo->value.enumerated.name,
1682 texts[uinfo->value.enumerated.item]);
1683 } else {
1684 static char *texts[] = { "Word", "MADI" };
1685
1686 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1687 uinfo->count = 1;
1688
1689 uinfo->value.enumerated.items = 2;
1690
1691 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1692 uinfo->value.enumerated.item =
1693 uinfo->value.enumerated.items - 1;
1694 strcpy(uinfo->value.enumerated.name,
1695 texts[uinfo->value.enumerated.item]);
1696 }
763f356c
TI		 1697 return 0;
1698}
1699
98274f07
TI		 1700static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
1701 struct snd_ctl_elem_value *ucontrol)
763f356c 1702{
98274f07 1703 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c
TI		 1704
1705 ucontrol->value.enumerated.item[0] = hdspm_pref_sync_ref(hdspm);
1706 return 0;
1707}
1708
98274f07
TI		 1709static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
1710 struct snd_ctl_elem_value *ucontrol)
763f356c 1711{
98274f07 1712 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c
TI		 1713 int change, max;
1714 unsigned int val;
1715
3cee5a60 1716 max = hdspm->is_aes32 ? 9 : 2;
763f356c
TI		 1717
1718 if (!snd_hdspm_use_is_exclusive(hdspm))
1719 return -EBUSY;
1720
1721 val = ucontrol->value.enumerated.item[0] % max;
1722
1723 spin_lock_irq(&hdspm->lock);
1724 change = (int) val != hdspm_pref_sync_ref(hdspm);
1725 hdspm_set_pref_sync_ref(hdspm, val);
1726 spin_unlock_irq(&hdspm->lock);
1727 return change;
1728}
1729
1730#define HDSPM_AUTOSYNC_REF(xname, xindex) \
67ed4161 1731{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
763f356c
TI		 1732 .name = xname, \
1733 .index = xindex, \
1734 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1735 .info = snd_hdspm_info_autosync_ref, \
1736 .get = snd_hdspm_get_autosync_ref, \
1737}
1738
98274f07 1739static int hdspm_autosync_ref(struct hdspm * hdspm)
763f356c 1740{
3cee5a60
RB		 1741 if (hdspm->is_aes32) {
1742 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
1743 unsigned int syncref = (status >> HDSPM_AES32_syncref_bit) & 0xF;
1744 if (syncref == 0)
1745 return HDSPM_AES32_AUTOSYNC_FROM_WORD;
1746 if (syncref <= 8)
1747 return syncref;
1748 return HDSPM_AES32_AUTOSYNC_FROM_NONE;
1749 } else {
1750 /* This looks at the autosync selected sync reference */
1751 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1752
1753 switch (status2 & HDSPM_SelSyncRefMask) {
1754 case HDSPM_SelSyncRef_WORD:
1755 return HDSPM_AUTOSYNC_FROM_WORD;
1756 case HDSPM_SelSyncRef_MADI:
1757 return HDSPM_AUTOSYNC_FROM_MADI;
1758 case HDSPM_SelSyncRef_NVALID:
1759 return HDSPM_AUTOSYNC_FROM_NONE;
1760 default:
1761 return 0;
1762 }
763f356c 1763
763f356c
TI		 1764 return 0;
1765 }
763f356c
TI		 1766}
1767
98274f07
TI		 1768static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
1769 struct snd_ctl_elem_info *uinfo)
763f356c 1770{
3cee5a60 1771 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c 1772
3cee5a60
RB		 1773 if (hdspm->is_aes32) {
1774 static char *texts[] = { "WordClock", "AES1", "AES2", "AES3",
1775 "AES4", "AES5", "AES6", "AES7", "AES8", "None"};
1776
1777 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1778 uinfo->count = 1;
1779 uinfo->value.enumerated.items = 10;
1780 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1781 uinfo->value.enumerated.item =
1782 uinfo->value.enumerated.items - 1;
1783 strcpy(uinfo->value.enumerated.name,
1784 texts[uinfo->value.enumerated.item]);
1785 }
1786 else
1787 {
1788 static char *texts[] = { "WordClock", "MADI", "None" };
1789
1790 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1791 uinfo->count = 1;
1792 uinfo->value.enumerated.items = 3;
1793 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1794 uinfo->value.enumerated.item =
1795 uinfo->value.enumerated.items - 1;
1796 strcpy(uinfo->value.enumerated.name,
1797 texts[uinfo->value.enumerated.item]);
1798 }
763f356c
TI		 1799 return 0;
1800}
1801
98274f07
TI		 1802static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
1803 struct snd_ctl_elem_value *ucontrol)
763f356c 1804{
98274f07 1805 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c
TI		 1806
1807 ucontrol->value.enumerated.item[0] = hdspm_pref_sync_ref(hdspm);
1808 return 0;
1809}
1810
1811#define HDSPM_LINE_OUT(xname, xindex) \
67ed4161 1812{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
763f356c
TI		 1813 .name = xname, \
1814 .index = xindex, \
1815 .info = snd_hdspm_info_line_out, \
1816 .get = snd_hdspm_get_line_out, \
1817 .put = snd_hdspm_put_line_out \
1818}
1819
98274f07 1820static int hdspm_line_out(struct hdspm * hdspm)
763f356c
TI		 1821{
1822 return (hdspm->control_register & HDSPM_LineOut) ? 1 : 0;
1823}
1824
1825
98274f07 1826static int hdspm_set_line_output(struct hdspm * hdspm, int out)
763f356c
TI		 1827{
1828 if (out)
1829 hdspm->control_register |= HDSPM_LineOut;
1830 else
1831 hdspm->control_register &= ~HDSPM_LineOut;
1832 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1833
1834 return 0;
1835}
1836
a5ce8890 1837#define snd_hdspm_info_line_out snd_ctl_boolean_mono_info
763f356c 1838
98274f07
TI		 1839static int snd_hdspm_get_line_out(struct snd_kcontrol *kcontrol,
1840 struct snd_ctl_elem_value *ucontrol)
763f356c 1841{
98274f07 1842 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c
TI		 1843
1844 spin_lock_irq(&hdspm->lock);
1845 ucontrol->value.integer.value[0] = hdspm_line_out(hdspm);
1846 spin_unlock_irq(&hdspm->lock);
1847 return 0;
1848}
1849
98274f07
TI		 1850static int snd_hdspm_put_line_out(struct snd_kcontrol *kcontrol,
1851 struct snd_ctl_elem_value *ucontrol)
763f356c 1852{
98274f07 1853 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c
TI		 1854 int change;
1855 unsigned int val;
1856
1857 if (!snd_hdspm_use_is_exclusive(hdspm))
1858 return -EBUSY;
1859 val = ucontrol->value.integer.value[0] & 1;
1860 spin_lock_irq(&hdspm->lock);
1861 change = (int) val != hdspm_line_out(hdspm);
1862 hdspm_set_line_output(hdspm, val);
1863 spin_unlock_irq(&hdspm->lock);
1864 return change;
1865}
1866
1867#define HDSPM_TX_64(xname, xindex) \
67ed4161 1868{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
763f356c
TI		 1869 .name = xname, \
1870 .index = xindex, \
1871 .info = snd_hdspm_info_tx_64, \
1872 .get = snd_hdspm_get_tx_64, \
1873 .put = snd_hdspm_put_tx_64 \
1874}
1875
98274f07 1876static int hdspm_tx_64(struct hdspm * hdspm)
763f356c
TI		 1877{
1878 return (hdspm->control_register & HDSPM_TX_64ch) ? 1 : 0;
1879}
1880
98274f07 1881static int hdspm_set_tx_64(struct hdspm * hdspm, int out)
763f356c
TI		 1882{
1883 if (out)
1884 hdspm->control_register |= HDSPM_TX_64ch;
1885 else
1886 hdspm->control_register &= ~HDSPM_TX_64ch;
1887 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1888
1889 return 0;
1890}
1891
a5ce8890 1892#define snd_hdspm_info_tx_64 snd_ctl_boolean_mono_info
763f356c 1893
98274f07
TI		 1894static int snd_hdspm_get_tx_64(struct snd_kcontrol *kcontrol,
1895 struct snd_ctl_elem_value *ucontrol)
763f356c 1896{
98274f07 1897 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c
TI		 1898
1899 spin_lock_irq(&hdspm->lock);
1900 ucontrol->value.integer.value[0] = hdspm_tx_64(hdspm);
1901 spin_unlock_irq(&hdspm->lock);
1902 return 0;
1903}
1904
98274f07
TI		 1905static int snd_hdspm_put_tx_64(struct snd_kcontrol *kcontrol,
1906 struct snd_ctl_elem_value *ucontrol)
763f356c 1907{
98274f07 1908 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c
TI		 1909 int change;
1910 unsigned int val;
1911
1912 if (!snd_hdspm_use_is_exclusive(hdspm))
1913 return -EBUSY;
1914 val = ucontrol->value.integer.value[0] & 1;
1915 spin_lock_irq(&hdspm->lock);
1916 change = (int) val != hdspm_tx_64(hdspm);
1917 hdspm_set_tx_64(hdspm, val);
1918 spin_unlock_irq(&hdspm->lock);
1919 return change;
1920}
1921
1922#define HDSPM_C_TMS(xname, xindex) \
67ed4161 1923{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
763f356c
TI		 1924 .name = xname, \
1925 .index = xindex, \
1926 .info = snd_hdspm_info_c_tms, \
1927 .get = snd_hdspm_get_c_tms, \
1928 .put = snd_hdspm_put_c_tms \
1929}
1930
98274f07 1931static int hdspm_c_tms(struct hdspm * hdspm)
763f356c
TI		 1932{
1933 return (hdspm->control_register & HDSPM_clr_tms) ? 1 : 0;
1934}
1935
98274f07 1936static int hdspm_set_c_tms(struct hdspm * hdspm, int out)
763f356c
TI		 1937{
1938 if (out)
1939 hdspm->control_register |= HDSPM_clr_tms;
1940 else
1941 hdspm->control_register &= ~HDSPM_clr_tms;
1942 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1943
1944 return 0;
1945}
1946
a5ce8890 1947#define snd_hdspm_info_c_tms snd_ctl_boolean_mono_info
763f356c 1948
98274f07
TI		 1949static int snd_hdspm_get_c_tms(struct snd_kcontrol *kcontrol,
1950 struct snd_ctl_elem_value *ucontrol)
763f356c 1951{
98274f07 1952 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c
TI		 1953
1954 spin_lock_irq(&hdspm->lock);
1955 ucontrol->value.integer.value[0] = hdspm_c_tms(hdspm);
1956 spin_unlock_irq(&hdspm->lock);
1957 return 0;
1958}
1959
98274f07
TI		 1960static int snd_hdspm_put_c_tms(struct snd_kcontrol *kcontrol,
1961 struct snd_ctl_elem_value *ucontrol)
763f356c 1962{
98274f07 1963 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c
TI		 1964 int change;
1965 unsigned int val;
1966
1967 if (!snd_hdspm_use_is_exclusive(hdspm))
1968 return -EBUSY;
1969 val = ucontrol->value.integer.value[0] & 1;
1970 spin_lock_irq(&hdspm->lock);
1971 change = (int) val != hdspm_c_tms(hdspm);
1972 hdspm_set_c_tms(hdspm, val);
1973 spin_unlock_irq(&hdspm->lock);
1974 return change;
1975}
1976
1977#define HDSPM_SAFE_MODE(xname, xindex) \
67ed4161 1978{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
763f356c
TI		 1979 .name = xname, \
1980 .index = xindex, \
1981 .info = snd_hdspm_info_safe_mode, \
1982 .get = snd_hdspm_get_safe_mode, \
1983 .put = snd_hdspm_put_safe_mode \
1984}
1985
3cee5a60
RB		 1986static int hdspm_safe_mode(struct hdspm * hdspm)
1987{
1988 return (hdspm->control_register & HDSPM_AutoInp) ? 1 : 0;
1989}
1990
1991static int hdspm_set_safe_mode(struct hdspm * hdspm, int out)
1992{
1993 if (out)
1994 hdspm->control_register |= HDSPM_AutoInp;
1995 else
1996 hdspm->control_register &= ~HDSPM_AutoInp;
1997 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1998
1999 return 0;
2000}
2001
a5ce8890 2002#define snd_hdspm_info_safe_mode snd_ctl_boolean_mono_info
3cee5a60
RB		 2003
2004static int snd_hdspm_get_safe_mode(struct snd_kcontrol *kcontrol,
2005 struct snd_ctl_elem_value *ucontrol)
2006{
2007 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2008
2009 spin_lock_irq(&hdspm->lock);
2010 ucontrol->value.integer.value[0] = hdspm_safe_mode(hdspm);
2011 spin_unlock_irq(&hdspm->lock);
2012 return 0;
2013}
2014
2015static int snd_hdspm_put_safe_mode(struct snd_kcontrol *kcontrol,
2016 struct snd_ctl_elem_value *ucontrol)
2017{
2018 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2019 int change;
2020 unsigned int val;
2021
2022 if (!snd_hdspm_use_is_exclusive(hdspm))
2023 return -EBUSY;
2024 val = ucontrol->value.integer.value[0] & 1;
2025 spin_lock_irq(&hdspm->lock);
2026 change = (int) val != hdspm_safe_mode(hdspm);
2027 hdspm_set_safe_mode(hdspm, val);
2028 spin_unlock_irq(&hdspm->lock);
2029 return change;
2030}
2031
2032#define HDSPM_EMPHASIS(xname, xindex) \
2033{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2034 .name = xname, \
2035 .index = xindex, \
2036 .info = snd_hdspm_info_emphasis, \
2037 .get = snd_hdspm_get_emphasis, \
2038 .put = snd_hdspm_put_emphasis \
2039}
2040
2041static int hdspm_emphasis(struct hdspm * hdspm)
2042{
2043 return (hdspm->control_register & HDSPM_Emphasis) ? 1 : 0;
2044}
2045
2046static int hdspm_set_emphasis(struct hdspm * hdspm, int emp)
2047{
2048 if (emp)
2049 hdspm->control_register |= HDSPM_Emphasis;
2050 else
2051 hdspm->control_register &= ~HDSPM_Emphasis;
2052 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2053
2054 return 0;
2055}
2056
a5ce8890 2057#define snd_hdspm_info_emphasis snd_ctl_boolean_mono_info
3cee5a60
RB		 2058
2059static int snd_hdspm_get_emphasis(struct snd_kcontrol *kcontrol,
2060 struct snd_ctl_elem_value *ucontrol)
2061{
2062 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2063
2064 spin_lock_irq(&hdspm->lock);
2065 ucontrol->value.enumerated.item[0] = hdspm_emphasis(hdspm);
2066 spin_unlock_irq(&hdspm->lock);
2067 return 0;
2068}
2069
2070static int snd_hdspm_put_emphasis(struct snd_kcontrol *kcontrol,
2071 struct snd_ctl_elem_value *ucontrol)
2072{
2073 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2074 int change;
2075 unsigned int val;
2076
2077 if (!snd_hdspm_use_is_exclusive(hdspm))
2078 return -EBUSY;
2079 val = ucontrol->value.integer.value[0] & 1;
2080 spin_lock_irq(&hdspm->lock);
2081 change = (int) val != hdspm_emphasis(hdspm);
2082 hdspm_set_emphasis(hdspm, val);
2083 spin_unlock_irq(&hdspm->lock);
2084 return change;
2085}
2086
2087#define HDSPM_DOLBY(xname, xindex) \
2088{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2089 .name = xname, \
2090 .index = xindex, \
2091 .info = snd_hdspm_info_dolby, \
2092 .get = snd_hdspm_get_dolby, \
2093 .put = snd_hdspm_put_dolby \
2094}
2095
2096static int hdspm_dolby(struct hdspm * hdspm)
2097{
2098 return (hdspm->control_register & HDSPM_Dolby) ? 1 : 0;
2099}
2100
2101static int hdspm_set_dolby(struct hdspm * hdspm, int dol)
2102{
2103 if (dol)
2104 hdspm->control_register |= HDSPM_Dolby;
2105 else
2106 hdspm->control_register &= ~HDSPM_Dolby;
2107 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2108
2109 return 0;
2110}
2111
a5ce8890 2112#define snd_hdspm_info_dolby snd_ctl_boolean_mono_info
3cee5a60
RB		 2113
2114static int snd_hdspm_get_dolby(struct snd_kcontrol *kcontrol,
2115 struct snd_ctl_elem_value *ucontrol)
2116{
2117 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2118
2119 spin_lock_irq(&hdspm->lock);
2120 ucontrol->value.enumerated.item[0] = hdspm_dolby(hdspm);
2121 spin_unlock_irq(&hdspm->lock);
2122 return 0;
2123}
2124
2125static int snd_hdspm_put_dolby(struct snd_kcontrol *kcontrol,
2126 struct snd_ctl_elem_value *ucontrol)
2127{
2128 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2129 int change;
2130 unsigned int val;
2131
2132 if (!snd_hdspm_use_is_exclusive(hdspm))
2133 return -EBUSY;
2134 val = ucontrol->value.integer.value[0] & 1;
2135 spin_lock_irq(&hdspm->lock);
2136 change = (int) val != hdspm_dolby(hdspm);
2137 hdspm_set_dolby(hdspm, val);
2138 spin_unlock_irq(&hdspm->lock);
2139 return change;
2140}
2141
2142#define HDSPM_PROFESSIONAL(xname, xindex) \
2143{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2144 .name = xname, \
2145 .index = xindex, \
2146 .info = snd_hdspm_info_professional, \
2147 .get = snd_hdspm_get_professional, \
2148 .put = snd_hdspm_put_professional \
2149}
2150
2151static int hdspm_professional(struct hdspm * hdspm)
2152{
2153 return (hdspm->control_register & HDSPM_Professional) ? 1 : 0;
2154}
2155
2156static int hdspm_set_professional(struct hdspm * hdspm, int dol)
2157{
2158 if (dol)
2159 hdspm->control_register |= HDSPM_Professional;
2160 else
2161 hdspm->control_register &= ~HDSPM_Professional;
2162 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2163
2164 return 0;
2165}
2166
a5ce8890 2167#define snd_hdspm_info_professional snd_ctl_boolean_mono_info
3cee5a60
RB		 2168
2169static int snd_hdspm_get_professional(struct snd_kcontrol *kcontrol,
2170 struct snd_ctl_elem_value *ucontrol)
2171{
2172 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2173
2174 spin_lock_irq(&hdspm->lock);
2175 ucontrol->value.enumerated.item[0] = hdspm_professional(hdspm);
2176 spin_unlock_irq(&hdspm->lock);
2177 return 0;
2178}
2179
2180static int snd_hdspm_put_professional(struct snd_kcontrol *kcontrol,
2181 struct snd_ctl_elem_value *ucontrol)
2182{
2183 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2184 int change;
2185 unsigned int val;
2186
2187 if (!snd_hdspm_use_is_exclusive(hdspm))
2188 return -EBUSY;
2189 val = ucontrol->value.integer.value[0] & 1;
2190 spin_lock_irq(&hdspm->lock);
2191 change = (int) val != hdspm_professional(hdspm);
2192 hdspm_set_professional(hdspm, val);
2193 spin_unlock_irq(&hdspm->lock);
2194 return change;
2195}
2196
2197#define HDSPM_INPUT_SELECT(xname, xindex) \
2198{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2199 .name = xname, \
2200 .index = xindex, \
2201 .info = snd_hdspm_info_input_select, \
2202 .get = snd_hdspm_get_input_select, \
2203 .put = snd_hdspm_put_input_select \
2204}
2205
2206static int hdspm_input_select(struct hdspm * hdspm)
2207{
2208 return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
2209}
2210
2211static int hdspm_set_input_select(struct hdspm * hdspm, int out)
2212{
2213 if (out)
2214 hdspm->control_register |= HDSPM_InputSelect0;
2215 else
2216 hdspm->control_register &= ~HDSPM_InputSelect0;
2217 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2218
2219 return 0;
2220}
2221
2222static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
2223 struct snd_ctl_elem_info *uinfo)
2224{
2225 static char *texts[] = { "optical", "coaxial" };
2226
2227 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2228 uinfo->count = 1;
2229 uinfo->value.enumerated.items = 2;
2230
2231 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2232 uinfo->value.enumerated.item =
2233 uinfo->value.enumerated.items - 1;
2234 strcpy(uinfo->value.enumerated.name,
2235 texts[uinfo->value.enumerated.item]);
2236
2237 return 0;
2238}
2239
2240static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
2241 struct snd_ctl_elem_value *ucontrol)
2242{
2243 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2244
2245 spin_lock_irq(&hdspm->lock);
2246 ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
2247 spin_unlock_irq(&hdspm->lock);
2248 return 0;
2249}
2250
2251static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
2252 struct snd_ctl_elem_value *ucontrol)
2253{
2254 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2255 int change;
2256 unsigned int val;
2257
2258 if (!snd_hdspm_use_is_exclusive(hdspm))
2259 return -EBUSY;
2260 val = ucontrol->value.integer.value[0] & 1;
2261 spin_lock_irq(&hdspm->lock);
2262 change = (int) val != hdspm_input_select(hdspm);
2263 hdspm_set_input_select(hdspm, val);
2264 spin_unlock_irq(&hdspm->lock);
2265 return change;
2266}
2267
2268#define HDSPM_DS_WIRE(xname, xindex) \
2269{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2270 .name = xname, \
2271 .index = xindex, \
2272 .info = snd_hdspm_info_ds_wire, \
2273 .get = snd_hdspm_get_ds_wire, \
2274 .put = snd_hdspm_put_ds_wire \
2275}
2276
2277static int hdspm_ds_wire(struct hdspm * hdspm)
763f356c 2278{
3cee5a60 2279 return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
763f356c
TI		 2280}
2281
3cee5a60 2282static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
763f356c 2283{
3cee5a60
RB		 2284 if (ds)
2285 hdspm->control_register |= HDSPM_DS_DoubleWire;
763f356c 2286 else
3cee5a60 2287 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
763f356c
TI		 2288 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2289
2290 return 0;
2291}
2292
3cee5a60
RB		 2293static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
2294 struct snd_ctl_elem_info *uinfo)
763f356c 2295{
3cee5a60
RB		 2296 static char *texts[] = { "Single", "Double" };
2297
2298 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
763f356c 2299 uinfo->count = 1;
3cee5a60
RB		 2300 uinfo->value.enumerated.items = 2;
2301
2302 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2303 uinfo->value.enumerated.item =
2304 uinfo->value.enumerated.items - 1;
2305 strcpy(uinfo->value.enumerated.name,
2306 texts[uinfo->value.enumerated.item]);
2307
763f356c
TI		 2308 return 0;
2309}
2310
3cee5a60
RB		 2311static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
2312 struct snd_ctl_elem_value *ucontrol)
763f356c 2313{
98274f07 2314 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c
TI		 2315
2316 spin_lock_irq(&hdspm->lock);
3cee5a60 2317 ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
763f356c
TI		 2318 spin_unlock_irq(&hdspm->lock);
2319 return 0;
2320}
2321
3cee5a60
RB		 2322static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
2323 struct snd_ctl_elem_value *ucontrol)
763f356c 2324{
98274f07 2325 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c
TI		 2326 int change;
2327 unsigned int val;
2328
2329 if (!snd_hdspm_use_is_exclusive(hdspm))
2330 return -EBUSY;
2331 val = ucontrol->value.integer.value[0] & 1;
2332 spin_lock_irq(&hdspm->lock);
3cee5a60
RB		 2333 change = (int) val != hdspm_ds_wire(hdspm);
2334 hdspm_set_ds_wire(hdspm, val);
763f356c
TI		 2335 spin_unlock_irq(&hdspm->lock);
2336 return change;
2337}
2338
3cee5a60 2339#define HDSPM_QS_WIRE(xname, xindex) \
67ed4161 2340{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
763f356c
TI		 2341 .name = xname, \
2342 .index = xindex, \
3cee5a60
RB		 2343 .info = snd_hdspm_info_qs_wire, \
2344 .get = snd_hdspm_get_qs_wire, \
2345 .put = snd_hdspm_put_qs_wire \
763f356c
TI		 2346}
2347
3cee5a60 2348static int hdspm_qs_wire(struct hdspm * hdspm)
763f356c 2349{
3cee5a60
RB		 2350 if (hdspm->control_register & HDSPM_QS_DoubleWire)
2351 return 1;
2352 if (hdspm->control_register & HDSPM_QS_QuadWire)
2353 return 2;
2354 return 0;
763f356c
TI		 2355}
2356
3cee5a60 2357static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
763f356c 2358{
3cee5a60
RB		 2359 hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
2360 switch (mode) {
2361 case 0:
2362 break;
2363 case 1:
2364 hdspm->control_register |= HDSPM_QS_DoubleWire;
2365 break;
2366 case 2:
2367 hdspm->control_register |= HDSPM_QS_QuadWire;
2368 break;
2369 }
763f356c
TI		 2370 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2371
2372 return 0;
2373}
2374
3cee5a60 2375static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
98274f07 2376 struct snd_ctl_elem_info *uinfo)
763f356c 2377{
3cee5a60 2378 static char *texts[] = { "Single", "Double", "Quad" };
763f356c
TI		 2379
2380 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2381 uinfo->count = 1;
3cee5a60 2382 uinfo->value.enumerated.items = 3;
763f356c
TI		 2383
2384 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2385 uinfo->value.enumerated.item =
2386 uinfo->value.enumerated.items - 1;
2387 strcpy(uinfo->value.enumerated.name,
2388 texts[uinfo->value.enumerated.item]);
2389
2390 return 0;
2391}
2392
3cee5a60 2393static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
98274f07 2394 struct snd_ctl_elem_value *ucontrol)
763f356c 2395{
98274f07 2396 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c
TI		 2397
2398 spin_lock_irq(&hdspm->lock);
3cee5a60 2399 ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
763f356c
TI		 2400 spin_unlock_irq(&hdspm->lock);
2401 return 0;
2402}
2403
3cee5a60 2404static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
98274f07 2405 struct snd_ctl_elem_value *ucontrol)
763f356c 2406{
98274f07 2407 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c 2408 int change;
3cee5a60 2409 int val;
763f356c
TI		 2410
2411 if (!snd_hdspm_use_is_exclusive(hdspm))
2412 return -EBUSY;
3cee5a60
RB		 2413 val = ucontrol->value.integer.value[0];
2414 if (val < 0)
2415 val = 0;
2416 if (val > 2)
2417 val = 2;
763f356c 2418 spin_lock_irq(&hdspm->lock);
3cee5a60
RB		 2419 change = (int) val != hdspm_qs_wire(hdspm);
2420 hdspm_set_qs_wire(hdspm, val);
763f356c
TI		 2421 spin_unlock_irq(&hdspm->lock);
2422 return change;
2423}
2424
2425/* Simple Mixer
2426 deprecated since to much faders ???
2427 MIXER interface says output (source, destination, value)
2428 where source > MAX_channels are playback channels
2429 on MADICARD
2430 - playback mixer matrix: [channelout+64] [output] [value]
2431 - input(thru) mixer matrix: [channelin] [output] [value]
2432 (better do 2 kontrols for seperation ?)
2433*/
2434
2435#define HDSPM_MIXER(xname, xindex) \
2436{ .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2437 .name = xname, \
2438 .index = xindex, \
67ed4161 2439 .device = 0, \
763f356c
TI		 2440 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2441 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2442 .info = snd_hdspm_info_mixer, \
2443 .get = snd_hdspm_get_mixer, \
2444 .put = snd_hdspm_put_mixer \
2445}
2446
98274f07
TI		 2447static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
2448 struct snd_ctl_elem_info *uinfo)
763f356c
TI		 2449{
2450 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2451 uinfo->count = 3;
2452 uinfo->value.integer.min = 0;
2453 uinfo->value.integer.max = 65535;
2454 uinfo->value.integer.step = 1;
2455 return 0;
2456}
2457
98274f07
TI		 2458static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
2459 struct snd_ctl_elem_value *ucontrol)
763f356c 2460{
98274f07 2461 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c
TI		 2462 int source;
2463 int destination;
2464
2465 source = ucontrol->value.integer.value[0];
2466 if (source < 0)
2467 source = 0;
2468 else if (source >= 2 * HDSPM_MAX_CHANNELS)
2469 source = 2 * HDSPM_MAX_CHANNELS - 1;
2470
2471 destination = ucontrol->value.integer.value[1];
2472 if (destination < 0)
2473 destination = 0;
2474 else if (destination >= HDSPM_MAX_CHANNELS)
2475 destination = HDSPM_MAX_CHANNELS - 1;
2476
2477 spin_lock_irq(&hdspm->lock);
2478 if (source >= HDSPM_MAX_CHANNELS)
2479 ucontrol->value.integer.value[2] =
2480 hdspm_read_pb_gain(hdspm, destination,
2481 source - HDSPM_MAX_CHANNELS);
2482 else
2483 ucontrol->value.integer.value[2] =
2484 hdspm_read_in_gain(hdspm, destination, source);
2485
2486 spin_unlock_irq(&hdspm->lock);
2487
2488 return 0;
2489}
2490
98274f07
TI		 2491static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
2492 struct snd_ctl_elem_value *ucontrol)
763f356c 2493{
98274f07 2494 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c
TI		 2495 int change;
2496 int source;
2497 int destination;
2498 int gain;
2499
2500 if (!snd_hdspm_use_is_exclusive(hdspm))
2501 return -EBUSY;
2502
2503 source = ucontrol->value.integer.value[0];
2504 destination = ucontrol->value.integer.value[1];
2505
2506 if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
2507 return -1;
2508 if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
2509 return -1;
2510
2511 gain = ucontrol->value.integer.value[2];
2512
2513 spin_lock_irq(&hdspm->lock);
2514
2515 if (source >= HDSPM_MAX_CHANNELS)
2516 change = gain != hdspm_read_pb_gain(hdspm, destination,
2517 source -
2518 HDSPM_MAX_CHANNELS);
2519 else
2520 change =
2521 gain != hdspm_read_in_gain(hdspm, destination, source);
2522
2523 if (change) {
2524 if (source >= HDSPM_MAX_CHANNELS)
2525 hdspm_write_pb_gain(hdspm, destination,
2526 source - HDSPM_MAX_CHANNELS,
2527 gain);
2528 else
2529 hdspm_write_in_gain(hdspm, destination, source,
2530 gain);
2531 }
2532 spin_unlock_irq(&hdspm->lock);
2533
2534 return change;
2535}
2536
2537/* The simple mixer control(s) provide gain control for the
2538 basic 1:1 mappings of playback streams to output
2539 streams.
2540*/
2541
2542#define HDSPM_PLAYBACK_MIXER \
2543{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2544 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
2545 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2546 .info = snd_hdspm_info_playback_mixer, \
2547 .get = snd_hdspm_get_playback_mixer, \
2548 .put = snd_hdspm_put_playback_mixer \
2549}
2550
98274f07
TI		 2551static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
2552 struct snd_ctl_elem_info *uinfo)
763f356c
TI		 2553{
2554 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2555 uinfo->count = 1;
2556 uinfo->value.integer.min = 0;
2557 uinfo->value.integer.max = 65536;
2558 uinfo->value.integer.step = 1;
2559 return 0;
2560}
2561
98274f07
TI		 2562static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
2563 struct snd_ctl_elem_value *ucontrol)
763f356c 2564{
98274f07 2565 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c
TI		 2566 int channel;
2567 int mapped_channel;
2568
2569 channel = ucontrol->id.index - 1;
2570
2571 snd_assert(channel >= 0
2572 || channel < HDSPM_MAX_CHANNELS, return -EINVAL);
2573
2574 if ((mapped_channel = hdspm->channel_map[channel]) < 0)
2575 return -EINVAL;
2576
2577 spin_lock_irq(&hdspm->lock);
2578 ucontrol->value.integer.value[0] =
2579 hdspm_read_pb_gain(hdspm, mapped_channel, mapped_channel);
2580 spin_unlock_irq(&hdspm->lock);
2581
2582 /* snd_printdd("get pb mixer index %d, channel %d, mapped_channel %d, value %d\n",
2583 ucontrol->id.index, channel, mapped_channel, ucontrol->value.integer.value[0]);
2584 */
2585
2586 return 0;
2587}
2588
98274f07
TI		 2589static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
2590 struct snd_ctl_elem_value *ucontrol)
763f356c 2591{
98274f07 2592 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c
TI		 2593 int change;
2594 int channel;
2595 int mapped_channel;
2596 int gain;
2597
2598 if (!snd_hdspm_use_is_exclusive(hdspm))
2599 return -EBUSY;
2600
2601 channel = ucontrol->id.index - 1;
2602
2603 snd_assert(channel >= 0
2604 || channel < HDSPM_MAX_CHANNELS, return -EINVAL);
2605
2606 if ((mapped_channel = hdspm->channel_map[channel]) < 0)
2607 return -EINVAL;
2608
2609 gain = ucontrol->value.integer.value[0];
2610
2611 spin_lock_irq(&hdspm->lock);
2612 change =
2613 gain != hdspm_read_pb_gain(hdspm, mapped_channel,
2614 mapped_channel);
2615 if (change)
2616 hdspm_write_pb_gain(hdspm, mapped_channel, mapped_channel,
2617 gain);
2618 spin_unlock_irq(&hdspm->lock);
2619 return change;
2620}
2621
2622#define HDSPM_WC_SYNC_CHECK(xname, xindex) \
67ed4161 2623{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
763f356c
TI		 2624 .name = xname, \
2625 .index = xindex, \
2626 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2627 .info = snd_hdspm_info_sync_check, \
2628 .get = snd_hdspm_get_wc_sync_check \
2629}
2630
98274f07
TI		 2631static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
2632 struct snd_ctl_elem_info *uinfo)
763f356c
TI		 2633{
2634 static char *texts[] = { "No Lock", "Lock", "Sync" };
2635 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2636 uinfo->count = 1;
2637 uinfo->value.enumerated.items = 3;
2638 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2639 uinfo->value.enumerated.item =
2640 uinfo->value.enumerated.items - 1;
2641 strcpy(uinfo->value.enumerated.name,
2642 texts[uinfo->value.enumerated.item]);
2643 return 0;
2644}
2645
98274f07 2646static int hdspm_wc_sync_check(struct hdspm * hdspm)
763f356c 2647{
3cee5a60
RB		 2648 if (hdspm->is_aes32) {
2649 int status = hdspm_read(hdspm, HDSPM_statusRegister);
2650 if (status & HDSPM_AES32_wcLock) {
2651 /* I don't know how to differenciate sync from lock.
2652 Doing as if sync for now */
763f356c 2653 return 2;
3cee5a60
RB		 2654 }
2655 return 0;
2656 } else {
2657 int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
2658 if (status2 & HDSPM_wcLock) {
2659 if (status2 & HDSPM_wcSync)
2660 return 2;
2661 else
2662 return 1;
2663 }
2664 return 0;
763f356c 2665 }
763f356c
TI		 2666}
2667
98274f07
TI		 2668static int snd_hdspm_get_wc_sync_check(struct snd_kcontrol *kcontrol,
2669 struct snd_ctl_elem_value *ucontrol)
763f356c 2670{
98274f07 2671 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c
TI		 2672
2673 ucontrol->value.enumerated.item[0] = hdspm_wc_sync_check(hdspm);
2674 return 0;
2675}
2676
2677
2678#define HDSPM_MADI_SYNC_CHECK(xname, xindex) \
67ed4161 2679{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
763f356c
TI		 2680 .name = xname, \
2681 .index = xindex, \
2682 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2683 .info = snd_hdspm_info_sync_check, \
2684 .get = snd_hdspm_get_madisync_sync_check \
2685}
2686
98274f07 2687static int hdspm_madisync_sync_check(struct hdspm * hdspm)
763f356c
TI		 2688{
2689 int status = hdspm_read(hdspm, HDSPM_statusRegister);
2690 if (status & HDSPM_madiLock) {
2691 if (status & HDSPM_madiSync)
2692 return 2;
2693 else
2694 return 1;
2695 }
2696 return 0;
2697}
2698
98274f07
TI		 2699static int snd_hdspm_get_madisync_sync_check(struct snd_kcontrol *kcontrol,
2700 struct snd_ctl_elem_value *
763f356c
TI		 2701 ucontrol)
2702{
98274f07 2703 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c
TI		 2704
2705 ucontrol->value.enumerated.item[0] =
2706 hdspm_madisync_sync_check(hdspm);
2707 return 0;
2708}
2709
2710
3cee5a60
RB		 2711#define HDSPM_AES_SYNC_CHECK(xname, xindex) \
2712{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2713 .name = xname, \
2714 .index = xindex, \
2715 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2716 .info = snd_hdspm_info_sync_check, \
2717 .get = snd_hdspm_get_aes_sync_check \
2718}
2719
2720static int hdspm_aes_sync_check(struct hdspm * hdspm, int idx)
2721{
2722 int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
2723 if (status2 & (HDSPM_LockAES >> idx)) {
2724 /* I don't know how to differenciate sync from lock.
2725 Doing as if sync for now */
2726 return 2;
2727 }
2728 return 0;
2729}
2730
2731static int snd_hdspm_get_aes_sync_check(struct snd_kcontrol *kcontrol,
2732 struct snd_ctl_elem_value *ucontrol)
2733{
2734 int offset;
2735 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2736
2737 offset = ucontrol->id.index - 1;
2738 if (offset < 0 || offset >= 8)
2739 return -EINVAL;
2740
2741 ucontrol->value.enumerated.item[0] =
2742 hdspm_aes_sync_check(hdspm, offset);
2743 return 0;
2744}
763f356c
TI		 2745
2746
3cee5a60 2747static struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
763f356c
TI		 2748
2749 HDSPM_MIXER("Mixer", 0),
2750/* 'Sample Clock Source' complies with the alsa control naming scheme */
2751 HDSPM_CLOCK_SOURCE("Sample Clock Source", 0),
2752
2753 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
2754 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
2755 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
2756 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
2757/* 'External Rate' complies with the alsa control naming scheme */
2758 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
2759 HDSPM_WC_SYNC_CHECK("Word Clock Lock Status", 0),
2760 HDSPM_MADI_SYNC_CHECK("MADI Sync Lock Status", 0),
2761 HDSPM_LINE_OUT("Line Out", 0),
2762 HDSPM_TX_64("TX 64 channels mode", 0),
2763 HDSPM_C_TMS("Clear Track Marker", 0),
2764 HDSPM_SAFE_MODE("Safe Mode", 0),
2765 HDSPM_INPUT_SELECT("Input Select", 0),
2766};
2767
3cee5a60
RB		 2768static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
2769
2770 HDSPM_MIXER("Mixer", 0),
2771/* 'Sample Clock Source' complies with the alsa control naming scheme */
2772 HDSPM_CLOCK_SOURCE("Sample Clock Source", 0),
2773
2774 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
2775 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
2776 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
2777 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
2778/* 'External Rate' complies with the alsa control naming scheme */
2779 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
2780 HDSPM_WC_SYNC_CHECK("Word Clock Lock Status", 0),
2781/* HDSPM_AES_SYNC_CHECK("AES Lock Status", 0),*/ /* created in snd_hdspm_create_controls() */
2782 HDSPM_LINE_OUT("Line Out", 0),
2783 HDSPM_EMPHASIS("Emphasis", 0),
2784 HDSPM_DOLBY("Non Audio", 0),
2785 HDSPM_PROFESSIONAL("Professional", 0),
2786 HDSPM_C_TMS("Clear Track Marker", 0),
2787 HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
2788 HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
2789};
2790
98274f07 2791static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
763f356c
TI		 2792
2793
98274f07 2794static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
763f356c
TI		 2795{
2796 int i;
2797
2798 for (i = hdspm->ds_channels; i < hdspm->ss_channels; ++i) {
2799 if (hdspm->system_sample_rate > 48000) {
2800 hdspm->playback_mixer_ctls[i]->vd[0].access =
2801 SNDRV_CTL_ELEM_ACCESS_INACTIVE |
2802 SNDRV_CTL_ELEM_ACCESS_READ |
2803 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
2804 } else {
2805 hdspm->playback_mixer_ctls[i]->vd[0].access =
2806 SNDRV_CTL_ELEM_ACCESS_READWRITE |
2807 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
2808 }
2809 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
2810 SNDRV_CTL_EVENT_MASK_INFO,
2811 &hdspm->playback_mixer_ctls[i]->id);
2812 }
2813
2814 return 0;
2815}
2816
2817
98274f07 2818static int snd_hdspm_create_controls(struct snd_card *card, struct hdspm * hdspm)
763f356c
TI		 2819{
2820 unsigned int idx, limit;
2821 int err;
98274f07 2822 struct snd_kcontrol *kctl;
763f356c
TI		 2823
2824 /* add control list first */
3cee5a60
RB		 2825 if (hdspm->is_aes32) {
2826 struct snd_kcontrol_new aes_sync_ctl =
2827 HDSPM_AES_SYNC_CHECK("AES Lock Status", 0);
2828
2829 for (idx = 0; idx < ARRAY_SIZE(snd_hdspm_controls_aes32);
2830 idx++) {
2831 err = snd_ctl_add(card,
2832 snd_ctl_new1(&snd_hdspm_controls_aes32[idx],
2833 hdspm));
2834 if (err < 0)
2835 return err;
2836 }
2837 for (idx = 1; idx <= 8; idx++) {
2838 aes_sync_ctl.index = idx;
2839 err = snd_ctl_add(card,
2840 snd_ctl_new1(&aes_sync_ctl, hdspm));
2841 if (err < 0)
2842 return err;
2843 }
2844 } else {
2845 for (idx = 0; idx < ARRAY_SIZE(snd_hdspm_controls_madi);
2846 idx++) {
2847 err = snd_ctl_add(card,
2848 snd_ctl_new1(&snd_hdspm_controls_madi[idx],
2849 hdspm));
2850 if (err < 0)
2851 return err;
763f356c
TI		 2852 }
2853 }
2854
2855 /* Channel playback mixer as default control
3cee5a60
RB		 2856Note: the whole matrix would be 128*HDSPM_MIXER_CHANNELS Faders, thats too big for any alsamixer
2857they are accesible via special IOCTL on hwdep
2858and the mixer 2dimensional mixer control */
763f356c
TI		 2859
2860 snd_hdspm_playback_mixer.name = "Chn";
2861 limit = HDSPM_MAX_CHANNELS;
2862
2863 /* The index values are one greater than the channel ID so that alsamixer
2864 will display them correctly. We want to use the index for fast lookup
2865 of the relevant channel, but if we use it at all, most ALSA software
2866 does the wrong thing with it ...
2867 */
2868
2869 for (idx = 0; idx < limit; ++idx) {
2870 snd_hdspm_playback_mixer.index = idx + 1;
2871 if ((err = snd_ctl_add(card,
2872 kctl =
2873 snd_ctl_new1
2874 (&snd_hdspm_playback_mixer,
2875 hdspm)))) {
2876 return err;
2877 }
2878 hdspm->playback_mixer_ctls[idx] = kctl;
2879 }
2880
2881 return 0;
2882}
2883
2884/*------------------------------------------------------------
2885 /proc interface
2886 ------------------------------------------------------------*/
2887
2888static void
3cee5a60
RB		 2889snd_hdspm_proc_read_madi(struct snd_info_entry * entry,
2890 struct snd_info_buffer *buffer)
763f356c 2891{
98274f07 2892 struct hdspm *hdspm = (struct hdspm *) entry->private_data;
763f356c
TI		 2893 unsigned int status;
2894 unsigned int status2;
2895 char *pref_sync_ref;
2896 char *autosync_ref;
2897 char *system_clock_mode;
2898 char *clock_source;
2899 char *insel;
2900 char *syncref;
2901 int x, x2;
2902
2903 status = hdspm_read(hdspm, HDSPM_statusRegister);
2904 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
2905
2906 snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
2907 hdspm->card_name, hdspm->card->number + 1,
2908 hdspm->firmware_rev,
2909 (status2 & HDSPM_version0) |
2910 (status2 & HDSPM_version1) | (status2 &
2911 HDSPM_version2));
2912
2913 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
2914 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
2915
2916 snd_iprintf(buffer, "--- System ---\n");
2917
2918 snd_iprintf(buffer,
2919 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
2920 status & HDSPM_audioIRQPending,
2921 (status & HDSPM_midi0IRQPending) ? 1 : 0,
2922 (status & HDSPM_midi1IRQPending) ? 1 : 0,
2923 hdspm->irq_count);
2924 snd_iprintf(buffer,
2925 "HW pointer: id = %d, rawptr = %d (%d->%d) estimated= %ld (bytes)\n",
2926 ((status & HDSPM_BufferID) ? 1 : 0),
2927 (status & HDSPM_BufferPositionMask),
2928 (status & HDSPM_BufferPositionMask) % (2 *
2929 (int)hdspm->
2930 period_bytes),
2931 ((status & HDSPM_BufferPositionMask) -
2932 64) % (2 * (int)hdspm->period_bytes),
2933 (long) hdspm_hw_pointer(hdspm) * 4);
2934
2935 snd_iprintf(buffer,
2936 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
2937 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
2938 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
2939 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
2940 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
2941 snd_iprintf(buffer,
2942 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, status2=0x%x\n",
2943 hdspm->control_register, hdspm->control2_register,
2944 status, status2);
2945
2946 snd_iprintf(buffer, "--- Settings ---\n");
2947
2948 x = 1 << (6 +
2949 hdspm_decode_latency(hdspm->
2950 control_register &
2951 HDSPM_LatencyMask));
2952
2953 snd_iprintf(buffer,
2954 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
2955 x, (unsigned long) hdspm->period_bytes);
2956
2957 snd_iprintf(buffer, "Line out: %s, Precise Pointer: %s\n",
2958 (hdspm->
2959 control_register & HDSPM_LineOut) ? "on " : "off",
2960 (hdspm->precise_ptr) ? "on" : "off");
2961
2962 switch (hdspm->control_register & HDSPM_InputMask) {
2963 case HDSPM_InputOptical:
2964 insel = "Optical";
2965 break;
2966 case HDSPM_InputCoaxial:
2967 insel = "Coaxial";
2968 break;
2969 default:
2970 insel = "Unkown";
2971 }
2972
2973 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2974 case HDSPM_SyncRef_Word:
2975 syncref = "WordClock";
2976 break;
2977 case HDSPM_SyncRef_MADI:
2978 syncref = "MADI";
2979 break;
2980 default:
2981 syncref = "Unkown";
2982 }
2983 snd_iprintf(buffer, "Inputsel = %s, SyncRef = %s\n", insel,
2984 syncref);
2985
2986 snd_iprintf(buffer,
2987 "ClearTrackMarker = %s, Transmit in %s Channel Mode, Auto Input %s\n",
2988 (hdspm->
2989 control_register & HDSPM_clr_tms) ? "on" : "off",
2990 (hdspm->
2991 control_register & HDSPM_TX_64ch) ? "64" : "56",
2992 (hdspm->
2993 control_register & HDSPM_AutoInp) ? "on" : "off");
2994
2995 switch (hdspm_clock_source(hdspm)) {
2996 case HDSPM_CLOCK_SOURCE_AUTOSYNC:
2997 clock_source = "AutoSync";
2998 break;
2999 case HDSPM_CLOCK_SOURCE_INTERNAL_32KHZ:
3000 clock_source = "Internal 32 kHz";
3001 break;
3002 case HDSPM_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3003 clock_source = "Internal 44.1 kHz";
3004 break;
3005 case HDSPM_CLOCK_SOURCE_INTERNAL_48KHZ:
3006 clock_source = "Internal 48 kHz";
3007 break;
3008 case HDSPM_CLOCK_SOURCE_INTERNAL_64KHZ:
3009 clock_source = "Internal 64 kHz";
3010 break;
3011 case HDSPM_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3012 clock_source = "Internal 88.2 kHz";
3013 break;
3014 case HDSPM_CLOCK_SOURCE_INTERNAL_96KHZ:
3015 clock_source = "Internal 96 kHz";
3016 break;
3017 default:
3018 clock_source = "Error";
3019 }
3020 snd_iprintf(buffer, "Sample Clock Source: %s\n", clock_source);
3cee5a60 3021 if (!(hdspm->control_register & HDSPM_ClockModeMaster))
763f356c 3022 system_clock_mode = "Slave";
3cee5a60 3023 else
763f356c 3024 system_clock_mode = "Master";
763f356c
TI		 3025 snd_iprintf(buffer, "System Clock Mode: %s\n", system_clock_mode);
3026
3027 switch (hdspm_pref_sync_ref(hdspm)) {
3028 case HDSPM_SYNC_FROM_WORD:
3029 pref_sync_ref = "Word Clock";
3030 break;
3031 case HDSPM_SYNC_FROM_MADI:
3032 pref_sync_ref = "MADI Sync";
3033 break;
3034 default:
3035 pref_sync_ref = "XXXX Clock";
3036 break;
3037 }
3038 snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
3039 pref_sync_ref);
3040
3041 snd_iprintf(buffer, "System Clock Frequency: %d\n",
3042 hdspm->system_sample_rate);
3043
3044
3045 snd_iprintf(buffer, "--- Status:\n");
3046
3047 x = status & HDSPM_madiSync;
3048 x2 = status2 & HDSPM_wcSync;
3049
3050 snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
3051 (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
3052 "NoLock",
3053 (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
3054 "NoLock");
3055
3056 switch (hdspm_autosync_ref(hdspm)) {
3057 case HDSPM_AUTOSYNC_FROM_WORD:
3058 autosync_ref = "Word Clock";
3059 break;
3060 case HDSPM_AUTOSYNC_FROM_MADI:
3061 autosync_ref = "MADI Sync";
3062 break;
3063 case HDSPM_AUTOSYNC_FROM_NONE:
3064 autosync_ref = "Input not valid";
3065 break;
3066 default:
3067 autosync_ref = "---";
3068 break;
3069 }
3070 snd_iprintf(buffer,
3071 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
3072 autosync_ref, hdspm_external_sample_rate(hdspm),
3073 (status & HDSPM_madiFreqMask) >> 22,
3074 (status2 & HDSPM_wcFreqMask) >> 5);
3075
3076 snd_iprintf(buffer, "Input: %s, Mode=%s\n",
3077 (status & HDSPM_AB_int) ? "Coax" : "Optical",
3078 (status & HDSPM_RX_64ch) ? "64 channels" :
3079 "56 channels");
3080
3081 snd_iprintf(buffer, "\n");
3082}
3083
3cee5a60
RB		 3084static void
3085snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
3086 struct snd_info_buffer *buffer)
3087{
3088 struct hdspm *hdspm = (struct hdspm *) entry->private_data;
3089 unsigned int status;
3090 unsigned int status2;
3091 unsigned int timecode;
3092 int pref_syncref;
3093 char *autosync_ref;
3094 char *system_clock_mode;
3095 char *clock_source;
3096 int x;
3097
3098 status = hdspm_read(hdspm, HDSPM_statusRegister);
3099 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3100 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
3101
3102 snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
3103 hdspm->card_name, hdspm->card->number + 1,
3104 hdspm->firmware_rev);
3105
3106 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3107 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
3108
3109 snd_iprintf(buffer, "--- System ---\n");
3110
3111 snd_iprintf(buffer,
3112 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
3113 status & HDSPM_audioIRQPending,
3114 (status & HDSPM_midi0IRQPending) ? 1 : 0,
3115 (status & HDSPM_midi1IRQPending) ? 1 : 0,
3116 hdspm->irq_count);
3117 snd_iprintf(buffer,
3118 "HW pointer: id = %d, rawptr = %d (%d->%d) estimated= %ld (bytes)\n",
3119 ((status & HDSPM_BufferID) ? 1 : 0),
3120 (status & HDSPM_BufferPositionMask),
3121 (status & HDSPM_BufferPositionMask) % (2 *
3122 (int)hdspm->
3123 period_bytes),
3124 ((status & HDSPM_BufferPositionMask) -
3125 64) % (2 * (int)hdspm->period_bytes),
3126 (long) hdspm_hw_pointer(hdspm) * 4);
3127
3128 snd_iprintf(buffer,
3129 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
3130 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
3131 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
3132 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
3133 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
3134 snd_iprintf(buffer,
ffb2c3c0
RB		 3135 "Register: ctrl1=0x%x, status1=0x%x, status2=0x%x, timecode=0x%x\n",
3136 hdspm->control_register,
3cee5a60
RB		 3137 status, status2, timecode);
3138
3139 snd_iprintf(buffer, "--- Settings ---\n");
3140
3141 x = 1 << (6 +
3142 hdspm_decode_latency(hdspm->
3143 control_register &
3144 HDSPM_LatencyMask));
3145
3146 snd_iprintf(buffer,
3147 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
3148 x, (unsigned long) hdspm->period_bytes);
3149
3150 snd_iprintf(buffer, "Line out: %s, Precise Pointer: %s\n",
3151 (hdspm->
3152 control_register & HDSPM_LineOut) ? "on " : "off",
3153 (hdspm->precise_ptr) ? "on" : "off");
3154
3155 snd_iprintf(buffer,
3156 "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
3157 (hdspm->
3158 control_register & HDSPM_clr_tms) ? "on" : "off",
3159 (hdspm->
3160 control_register & HDSPM_Emphasis) ? "on" : "off",
3161 (hdspm->
3162 control_register & HDSPM_Dolby) ? "on" : "off");
3163
3164 switch (hdspm_clock_source(hdspm)) {
3165 case HDSPM_CLOCK_SOURCE_AUTOSYNC:
3166 clock_source = "AutoSync";
3167 break;
3168 case HDSPM_CLOCK_SOURCE_INTERNAL_32KHZ:
3169 clock_source = "Internal 32 kHz";
3170 break;
3171 case HDSPM_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3172 clock_source = "Internal 44.1 kHz";
3173 break;
3174 case HDSPM_CLOCK_SOURCE_INTERNAL_48KHZ:
3175 clock_source = "Internal 48 kHz";
3176 break;
3177 case HDSPM_CLOCK_SOURCE_INTERNAL_64KHZ:
3178 clock_source = "Internal 64 kHz";
3179 break;
3180 case HDSPM_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3181 clock_source = "Internal 88.2 kHz";
3182 break;
3183 case HDSPM_CLOCK_SOURCE_INTERNAL_96KHZ:
3184 clock_source = "Internal 96 kHz";
3185 break;
3186 case HDSPM_CLOCK_SOURCE_INTERNAL_128KHZ:
3187 clock_source = "Internal 128 kHz";
3188 break;
3189 case HDSPM_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3190 clock_source = "Internal 176.4 kHz";
3191 break;
3192 case HDSPM_CLOCK_SOURCE_INTERNAL_192KHZ:
3193 clock_source = "Internal 192 kHz";
3194 break;
3195 default:
3196 clock_source = "Error";
3197 }
3198 snd_iprintf(buffer, "Sample Clock Source: %s\n", clock_source);
3199 if (!(hdspm->control_register & HDSPM_ClockModeMaster))
3200 system_clock_mode = "Slave";
3201 else
3202 system_clock_mode = "Master";
3203 snd_iprintf(buffer, "System Clock Mode: %s\n", system_clock_mode);
3204
3205 pref_syncref = hdspm_pref_sync_ref(hdspm);
3206 if (pref_syncref == 0)
3207 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
3208 else
3209 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
3210 pref_syncref);
3211
3212 snd_iprintf(buffer, "System Clock Frequency: %d\n",
3213 hdspm->system_sample_rate);
3214
3215 snd_iprintf(buffer, "Double speed: %s\n",
3216 hdspm->control_register & HDSPM_DS_DoubleWire?
3217 "Double wire" : "Single wire");
3218 snd_iprintf(buffer, "Quad speed: %s\n",
3219 hdspm->control_register & HDSPM_QS_DoubleWire?
3220 "Double wire" :
3221 hdspm->control_register & HDSPM_QS_QuadWire?
3222 "Quad wire" : "Single wire");
3223
3224 snd_iprintf(buffer, "--- Status:\n");
3225
3226 snd_iprintf(buffer, "Word: %s Frequency: %d\n",
3227 (status & HDSPM_AES32_wcLock)? "Sync " : "No Lock",
3228 HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
3229
3230 for (x = 0; x < 8; x++) {
3231 snd_iprintf(buffer, "AES%d: %s Frequency: %d\n",
3232 x+1,
3233 (status2 & (HDSPM_LockAES >> x))? "Sync ": "No Lock",
3234 HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
3235 }
3236
3237 switch (hdspm_autosync_ref(hdspm)) {
3238 case HDSPM_AES32_AUTOSYNC_FROM_NONE: autosync_ref="None"; break;
3239 case HDSPM_AES32_AUTOSYNC_FROM_WORD: autosync_ref="Word Clock"; break;
3240 case HDSPM_AES32_AUTOSYNC_FROM_AES1: autosync_ref="AES1"; break;
3241 case HDSPM_AES32_AUTOSYNC_FROM_AES2: autosync_ref="AES2"; break;
3242 case HDSPM_AES32_AUTOSYNC_FROM_AES3: autosync_ref="AES3"; break;
3243 case HDSPM_AES32_AUTOSYNC_FROM_AES4: autosync_ref="AES4"; break;
3244 case HDSPM_AES32_AUTOSYNC_FROM_AES5: autosync_ref="AES5"; break;
3245 case HDSPM_AES32_AUTOSYNC_FROM_AES6: autosync_ref="AES6"; break;
3246 case HDSPM_AES32_AUTOSYNC_FROM_AES7: autosync_ref="AES7"; break;
3247 case HDSPM_AES32_AUTOSYNC_FROM_AES8: autosync_ref="AES8"; break;
3248 default: autosync_ref = "---"; break;
3249 }
3250 snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
3251
3252 snd_iprintf(buffer, "\n");
3253}
3254
3255#ifdef CONFIG_SND_DEBUG
3256static void
3257snd_hdspm_proc_read_debug(struct snd_info_entry * entry,
3258 struct snd_info_buffer *buffer)
3259{
3260 struct hdspm *hdspm = (struct hdspm *)entry->private_data;
3261
3262 int j,i;
3263
3264 for (i = 0; i < 256 /* 1024*64 */; i += j)
3265 {
3266 snd_iprintf(buffer, "0x%08X: ", i);
3267 for (j = 0; j < 16; j += 4)
3268 snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
3269 snd_iprintf(buffer, "\n");
3270 }
3271}
3272#endif
3273
3274
3275
98274f07 3276static void __devinit snd_hdspm_proc_init(struct hdspm * hdspm)
763f356c 3277{
98274f07 3278 struct snd_info_entry *entry;
763f356c
TI		 3279
3280 if (!snd_card_proc_new(hdspm->card, "hdspm", &entry))
bf850204 3281 snd_info_set_text_ops(entry, hdspm,
3cee5a60
RB		 3282 hdspm->is_aes32 ?
3283 snd_hdspm_proc_read_aes32 :
3284 snd_hdspm_proc_read_madi);
3285#ifdef CONFIG_SND_DEBUG
3286 /* debug file to read all hdspm registers */
3287 if (!snd_card_proc_new(hdspm->card, "debug", &entry))
3288 snd_info_set_text_ops(entry, hdspm,
3289 snd_hdspm_proc_read_debug);
3290#endif
763f356c
TI		 3291}
3292
3293/*------------------------------------------------------------
3294 hdspm intitialize
3295 ------------------------------------------------------------*/
3296
98274f07 3297static int snd_hdspm_set_defaults(struct hdspm * hdspm)
763f356c
TI		 3298{
3299 unsigned int i;
3300
3301 /* ASSUMPTION: hdspm->lock is either held, or there is no need to
3302 hold it (e.g. during module initalization).
3303 */
3304
3305 /* set defaults: */
3306
3cee5a60
RB		 3307 if (hdspm->is_aes32)
3308 hdspm->control_register = HDSPM_ClockModeMaster | /* Master Cloack Mode on */
3309 hdspm_encode_latency(7) | /* latency maximum = 8192 samples */
3310 HDSPM_SyncRef0 | /* AES1 is syncclock */
3311 HDSPM_LineOut | /* Analog output in */
3312 HDSPM_Professional; /* Professional mode */
3313 else
3314 hdspm->control_register = HDSPM_ClockModeMaster | /* Master Cloack Mode on */
3315 hdspm_encode_latency(7) | /* latency maximum = 8192 samples */
3316 HDSPM_InputCoaxial | /* Input Coax not Optical */
3317 HDSPM_SyncRef_MADI | /* Madi is syncclock */
3318 HDSPM_LineOut | /* Analog output in */
3319 HDSPM_TX_64ch | /* transmit in 64ch mode */
3320 HDSPM_AutoInp; /* AutoInput chossing (takeover) */
763f356c
TI		 3321
3322 /* ! HDSPM_Frequency0|HDSPM_Frequency1 = 44.1khz */
3323 /* ! HDSPM_DoubleSpeed HDSPM_QuadSpeed = normal speed */
3324 /* ! HDSPM_clr_tms = do not clear bits in track marks */
3325
3326 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3327
ffb2c3c0
RB		 3328 if (!hdspm->is_aes32) {
3329 /* No control2 register for AES32 */
763f356c 3330#ifdef SNDRV_BIG_ENDIAN
ffb2c3c0 3331 hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
763f356c 3332#else
ffb2c3c0 3333 hdspm->control2_register = 0;
763f356c
TI		 3334#endif
3335
ffb2c3c0
RB		 3336 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
3337 }
763f356c
TI		 3338 hdspm_compute_period_size(hdspm);
3339
3340 /* silence everything */
3341
3342 all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
3343
3344 if (line_outs_monitor[hdspm->dev]) {
3345
3346 snd_printk(KERN_INFO "HDSPM: sending all playback streams to line outs.\n");
3347
3348 for (i = 0; i < HDSPM_MIXER_CHANNELS; i++) {
3349 if (hdspm_write_pb_gain(hdspm, i, i, UNITY_GAIN))
3350 return -EIO;
3351 }
3352 }
3353
3354 /* set a default rate so that the channel map is set up. */
3355 hdspm->channel_map = channel_map_madi_ss;
3356 hdspm_set_rate(hdspm, 44100, 1);
3357
3358 return 0;
3359}
3360
3361
3362/*------------------------------------------------------------
3363 interupt
3364 ------------------------------------------------------------*/
3365
7d12e780 3366static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
763f356c 3367{
98274f07 3368 struct hdspm *hdspm = (struct hdspm *) dev_id;
763f356c
TI		 3369 unsigned int status;
3370 int audio;
3371 int midi0;
3372 int midi1;
3373 unsigned int midi0status;
3374 unsigned int midi1status;
3375 int schedule = 0;
3376
3377 status = hdspm_read(hdspm, HDSPM_statusRegister);
3378
3379 audio = status & HDSPM_audioIRQPending;
3380 midi0 = status & HDSPM_midi0IRQPending;
3381 midi1 = status & HDSPM_midi1IRQPending;
3382
3383 if (!audio && !midi0 && !midi1)
3384 return IRQ_NONE;
3385
3386 hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
3387 hdspm->irq_count++;
3388
3389 midi0status = hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xff;
3390 midi1status = hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xff;
3391
3392 if (audio) {
3393
3394 if (hdspm->capture_substream)
3395 snd_pcm_period_elapsed(hdspm->pcm->
3396 streams
3397 [SNDRV_PCM_STREAM_CAPTURE].
3398 substream);
3399
3400 if (hdspm->playback_substream)
3401 snd_pcm_period_elapsed(hdspm->pcm->
3402 streams
3403 [SNDRV_PCM_STREAM_PLAYBACK].
3404 substream);
3405 }
3406
3407 if (midi0 && midi0status) {
3408 /* we disable interrupts for this input until processing is done */
3409 hdspm->control_register &= ~HDSPM_Midi0InterruptEnable;
3410 hdspm_write(hdspm, HDSPM_controlRegister,
3411 hdspm->control_register);
3412 hdspm->midi[0].pending = 1;
3413 schedule = 1;
3414 }
3415 if (midi1 && midi1status) {
3416 /* we disable interrupts for this input until processing is done */
3417 hdspm->control_register &= ~HDSPM_Midi1InterruptEnable;
3418 hdspm_write(hdspm, HDSPM_controlRegister,
3419 hdspm->control_register);
3420 hdspm->midi[1].pending = 1;
3421 schedule = 1;
3422 }
3423 if (schedule)
3424 tasklet_hi_schedule(&hdspm->midi_tasklet);
3425 return IRQ_HANDLED;
3426}
3427
3428/*------------------------------------------------------------
3429 pcm interface
3430 ------------------------------------------------------------*/
3431
3432
98274f07 3433static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream *
763f356c
TI		 3434 substream)
3435{
98274f07 3436 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
763f356c
TI		 3437 return hdspm_hw_pointer(hdspm);
3438}
3439
98274f07 3440static char *hdspm_channel_buffer_location(struct hdspm * hdspm,
763f356c
TI		 3441 int stream, int channel)
3442{
3443 int mapped_channel;
3444
3445 snd_assert(channel >= 0
3446 || channel < HDSPM_MAX_CHANNELS, return NULL);
3447
3448 if ((mapped_channel = hdspm->channel_map[channel]) < 0)
3449 return NULL;
3450
3451 if (stream == SNDRV_PCM_STREAM_CAPTURE) {
3452 return hdspm->capture_buffer +
3453 mapped_channel * HDSPM_CHANNEL_BUFFER_BYTES;
3454 } else {
3455 return hdspm->playback_buffer +
3456 mapped_channel * HDSPM_CHANNEL_BUFFER_BYTES;
3457 }
3458}
3459
3460
3461/* dont know why need it ??? */
98274f07 3462static int snd_hdspm_playback_copy(struct snd_pcm_substream *substream,
763f356c
TI		 3463 int channel, snd_pcm_uframes_t pos,
3464 void __user *src, snd_pcm_uframes_t count)
3465{
98274f07 3466 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
763f356c
TI		 3467 char *channel_buf;
3468
3469 snd_assert(pos + count <= HDSPM_CHANNEL_BUFFER_BYTES / 4,
3470 return -EINVAL);
3471
3472 channel_buf = hdspm_channel_buffer_location(hdspm,
3473 substream->pstr->
3474 stream, channel);
3475
3476 snd_assert(channel_buf != NULL, return -EIO);
3477
3478 return copy_from_user(channel_buf + pos * 4, src, count * 4);
3479}
3480
98274f07 3481static int snd_hdspm_capture_copy(struct snd_pcm_substream *substream,
763f356c
TI		 3482 int channel, snd_pcm_uframes_t pos,
3483 void __user *dst, snd_pcm_uframes_t count)
3484{
98274f07 3485 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
763f356c
TI		 3486 char *channel_buf;
3487
3488 snd_assert(pos + count <= HDSPM_CHANNEL_BUFFER_BYTES / 4,
3489 return -EINVAL);
3490
3491 channel_buf = hdspm_channel_buffer_location(hdspm,
3492 substream->pstr->
3493 stream, channel);
3494 snd_assert(channel_buf != NULL, return -EIO);
3495 return copy_to_user(dst, channel_buf + pos * 4, count * 4);
3496}
3497
98274f07 3498static int snd_hdspm_hw_silence(struct snd_pcm_substream *substream,
763f356c
TI		 3499 int channel, snd_pcm_uframes_t pos,
3500 snd_pcm_uframes_t count)
3501{
98274f07 3502 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
763f356c
TI		 3503 char *channel_buf;
3504
3505 channel_buf =
3506 hdspm_channel_buffer_location(hdspm, substream->pstr->stream,
3507 channel);
3508 snd_assert(channel_buf != NULL, return -EIO);
3509 memset(channel_buf + pos * 4, 0, count * 4);
3510 return 0;
3511}
3512
98274f07 3513static int snd_hdspm_reset(struct snd_pcm_substream *substream)
763f356c 3514{
98274f07
TI		 3515 struct snd_pcm_runtime *runtime = substream->runtime;
3516 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
3517 struct snd_pcm_substream *other;
763f356c
TI		 3518
3519 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3520 other = hdspm->capture_substream;
3521 else
3522 other = hdspm->playback_substream;
3523
3524 if (hdspm->running)
3525 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
3526 else
3527 runtime->status->hw_ptr = 0;
3528 if (other) {
98274f07
TI		 3529 struct snd_pcm_substream *s;
3530 struct snd_pcm_runtime *oruntime = other->runtime;
ef991b95 3531 snd_pcm_group_for_each_entry(s, substream) {
763f356c
TI		 3532 if (s == other) {
3533 oruntime->status->hw_ptr =
3534 runtime->status->hw_ptr;
3535 break;
3536 }
3537 }
3538 }
3539 return 0;
3540}
3541
98274f07
TI		 3542static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
3543 struct snd_pcm_hw_params *params)
763f356c 3544{
98274f07 3545 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
763f356c
TI		 3546 int err;
3547 int i;
3548 pid_t this_pid;
3549 pid_t other_pid;
3550 struct snd_sg_buf *sgbuf;
3551
3552
3553 spin_lock_irq(&hdspm->lock);
3554
3555 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3556 this_pid = hdspm->playback_pid;
3557 other_pid = hdspm->capture_pid;
3558 } else {
3559 this_pid = hdspm->capture_pid;
3560 other_pid = hdspm->playback_pid;
3561 }
3562
3563 if ((other_pid > 0) && (this_pid != other_pid)) {
3564
3565 /* The other stream is open, and not by the same
3566 task as this one. Make sure that the parameters
3567 that matter are the same.
3568 */
3569
3570 if (params_rate(params) != hdspm->system_sample_rate) {
3571 spin_unlock_irq(&hdspm->lock);
3572 _snd_pcm_hw_param_setempty(params,
3573 SNDRV_PCM_HW_PARAM_RATE);
3574 return -EBUSY;
3575 }
3576
3577 if (params_period_size(params) != hdspm->period_bytes / 4) {
3578 spin_unlock_irq(&hdspm->lock);
3579 _snd_pcm_hw_param_setempty(params,
3580 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3581 return -EBUSY;
3582 }
3583
3584 }
3585 /* We're fine. */
3586 spin_unlock_irq(&hdspm->lock);
3587
3588 /* how to make sure that the rate matches an externally-set one ? */
3589
3590 spin_lock_irq(&hdspm->lock);
3591 if ((err = hdspm_set_rate(hdspm, params_rate(params), 0)) < 0) {
3592 spin_unlock_irq(&hdspm->lock);
3593 _snd_pcm_hw_param_setempty(params,
3594 SNDRV_PCM_HW_PARAM_RATE);
3595 return err;
3596 }
3597 spin_unlock_irq(&hdspm->lock);
3598
3599 if ((err =
3600 hdspm_set_interrupt_interval(hdspm,
3601 params_period_size(params))) <
3602 0) {
3603 _snd_pcm_hw_param_setempty(params,
3604 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3605 return err;
3606 }
3607
3608 /* Memory allocation, takashi's method, dont know if we should spinlock */
3609 /* malloc all buffer even if not enabled to get sure */
ffb2c3c0
RB		 3610 /* Update for MADI rev 204: we need to allocate for all channels,
3611 * otherwise it doesn't work at 96kHz */
763f356c 3612 err =
ffb2c3c0 3613 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
763f356c
TI		 3614 if (err < 0)
3615 return err;
3616
3617 sgbuf = snd_pcm_substream_sgbuf(substream);
3618
3619 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3620
3621 hdspm_set_sgbuf(hdspm, sgbuf, HDSPM_pageAddressBufferOut,
3622 params_channels(params));
3623
3624 for (i = 0; i < params_channels(params); ++i)
3625 snd_hdspm_enable_out(hdspm, i, 1);
3626
3627 hdspm->playback_buffer =
3628 (unsigned char *) substream->runtime->dma_area;
54bf5dd9 3629 snd_printdd("Allocated sample buffer for playback at %p\n",
3cee5a60 3630 hdspm->playback_buffer);
763f356c
TI		 3631 } else {
3632 hdspm_set_sgbuf(hdspm, sgbuf, HDSPM_pageAddressBufferIn,
3633 params_channels(params));
3634
3635 for (i = 0; i < params_channels(params); ++i)
3636 snd_hdspm_enable_in(hdspm, i, 1);
3637
3638 hdspm->capture_buffer =
3639 (unsigned char *) substream->runtime->dma_area;
54bf5dd9 3640 snd_printdd("Allocated sample buffer for capture at %p\n",
3cee5a60 3641 hdspm->capture_buffer);
763f356c 3642 }
3cee5a60
RB		 3643 /*
3644 snd_printdd("Allocated sample buffer for %s at 0x%08X\n",
3645 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
3646 "playback" : "capture",
3647 snd_pcm_sgbuf_get_addr(sgbuf, 0));
3648 */
ffb2c3c0
RB		 3649 /*
3650 snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n",
3651 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
3652 "playback" : "capture",
3653 params_rate(params), params_channels(params),
3654 params_buffer_size(params));
3655 */
763f356c
TI		 3656 return 0;
3657}
3658
98274f07 3659static int snd_hdspm_hw_free(struct snd_pcm_substream *substream)
763f356c
TI		 3660{
3661 int i;
98274f07 3662 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
763f356c
TI		 3663
3664 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3665
3666 /* params_channels(params) should be enough,
3667 but to get sure in case of error */
3668 for (i = 0; i < HDSPM_MAX_CHANNELS; ++i)
3669 snd_hdspm_enable_out(hdspm, i, 0);
3670
3671 hdspm->playback_buffer = NULL;
3672 } else {
3673 for (i = 0; i < HDSPM_MAX_CHANNELS; ++i)
3674 snd_hdspm_enable_in(hdspm, i, 0);
3675
3676 hdspm->capture_buffer = NULL;
3677
3678 }
3679
3680 snd_pcm_lib_free_pages(substream);
3681
3682 return 0;
3683}
3684
98274f07
TI		 3685static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
3686 struct snd_pcm_channel_info * info)
763f356c 3687{
98274f07 3688 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
763f356c
TI		 3689 int mapped_channel;
3690
3691 snd_assert(info->channel < HDSPM_MAX_CHANNELS, return -EINVAL);
3692
3693 if ((mapped_channel = hdspm->channel_map[info->channel]) < 0)
3694 return -EINVAL;
3695
3696 info->offset = mapped_channel * HDSPM_CHANNEL_BUFFER_BYTES;
3697 info->first = 0;
3698 info->step = 32;
3699 return 0;
3700}
3701
98274f07 3702static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
763f356c
TI		 3703 unsigned int cmd, void *arg)
3704{
3705 switch (cmd) {
3706 case SNDRV_PCM_IOCTL1_RESET:
3707 {
3708 return snd_hdspm_reset(substream);
3709 }
3710
3711 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
3712 {
98274f07 3713 struct snd_pcm_channel_info *info = arg;
763f356c
TI		 3714 return snd_hdspm_channel_info(substream, info);
3715 }
3716 default:
3717 break;
3718 }
3719
3720 return snd_pcm_lib_ioctl(substream, cmd, arg);
3721}
3722
98274f07 3723static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd)
763f356c 3724{
98274f07
TI		 3725 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
3726 struct snd_pcm_substream *other;
763f356c
TI		 3727 int running;
3728
3729 spin_lock(&hdspm->lock);
3730 running = hdspm->running;
3731 switch (cmd) {
3732 case SNDRV_PCM_TRIGGER_START:
3733 running |= 1 << substream->stream;
3734 break;
3735 case SNDRV_PCM_TRIGGER_STOP:
3736 running &= ~(1 << substream->stream);
3737 break;
3738 default:
3739 snd_BUG();
3740 spin_unlock(&hdspm->lock);
3741 return -EINVAL;
3742 }
3743 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3744 other = hdspm->capture_substream;
3745 else
3746 other = hdspm->playback_substream;
3747
3748 if (other) {
98274f07 3749 struct snd_pcm_substream *s;
ef991b95 3750 snd_pcm_group_for_each_entry(s, substream) {
763f356c
TI		 3751 if (s == other) {
3752 snd_pcm_trigger_done(s, substream);
3753 if (cmd == SNDRV_PCM_TRIGGER_START)
3754 running |= 1 << s->stream;
3755 else
3756 running &= ~(1 << s->stream);
3757 goto _ok;
3758 }
3759 }
3760 if (cmd == SNDRV_PCM_TRIGGER_START) {
3761 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
3762 && substream->stream ==
3763 SNDRV_PCM_STREAM_CAPTURE)
3764 hdspm_silence_playback(hdspm);
3765 } else {
3766 if (running &&
3767 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3768 hdspm_silence_playback(hdspm);
3769 }
3770 } else {
3771 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
3772 hdspm_silence_playback(hdspm);
3773 }
3774 _ok:
3775 snd_pcm_trigger_done(substream, substream);
3776 if (!hdspm->running && running)
3777 hdspm_start_audio(hdspm);
3778 else if (hdspm->running && !running)
3779 hdspm_stop_audio(hdspm);
3780 hdspm->running = running;
3781 spin_unlock(&hdspm->lock);
3782
3783 return 0;
3784}
3785
98274f07 3786static int snd_hdspm_prepare(struct snd_pcm_substream *substream)
763f356c
TI		 3787{
3788 return 0;
3789}
3790
3791static unsigned int period_sizes[] =
3792 { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
3793
98274f07 3794static struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
763f356c
TI		 3795 .info = (SNDRV_PCM_INFO_MMAP |
3796 SNDRV_PCM_INFO_MMAP_VALID |
3797 SNDRV_PCM_INFO_NONINTERLEAVED |
3798 SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE),
3799 .formats = SNDRV_PCM_FMTBIT_S32_LE,
3800 .rates = (SNDRV_PCM_RATE_32000 |
3801 SNDRV_PCM_RATE_44100 |
3802 SNDRV_PCM_RATE_48000 |
3803 SNDRV_PCM_RATE_64000 |
3cee5a60
RB		 3804 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
3805 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ),
763f356c 3806 .rate_min = 32000,
3cee5a60 3807 .rate_max = 192000,
763f356c
TI		 3808 .channels_min = 1,
3809 .channels_max = HDSPM_MAX_CHANNELS,
3810 .buffer_bytes_max =
3811 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
3812 .period_bytes_min = (64 * 4),
3813 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
3814 .periods_min = 2,
3815 .periods_max = 2,
3816 .fifo_size = 0
3817};
3818
98274f07 3819static struct snd_pcm_hardware snd_hdspm_capture_subinfo = {
763f356c
TI		 3820 .info = (SNDRV_PCM_INFO_MMAP |
3821 SNDRV_PCM_INFO_MMAP_VALID |
3822 SNDRV_PCM_INFO_NONINTERLEAVED |
3823 SNDRV_PCM_INFO_SYNC_START),
3824 .formats = SNDRV_PCM_FMTBIT_S32_LE,
3825 .rates = (SNDRV_PCM_RATE_32000 |
3826 SNDRV_PCM_RATE_44100 |
3827 SNDRV_PCM_RATE_48000 |
3828 SNDRV_PCM_RATE_64000 |
3cee5a60
RB		 3829 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
3830 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000),
763f356c 3831 .rate_min = 32000,
3cee5a60 3832 .rate_max = 192000,
763f356c
TI		 3833 .channels_min = 1,
3834 .channels_max = HDSPM_MAX_CHANNELS,
3835 .buffer_bytes_max =
3836 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
3837 .period_bytes_min = (64 * 4),
3838 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
3839 .periods_min = 2,
3840 .periods_max = 2,
3841 .fifo_size = 0
3842};
3843
98274f07 3844static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = {
763f356c
TI		 3845 .count = ARRAY_SIZE(period_sizes),
3846 .list = period_sizes,
3847 .mask = 0
3848};
3849
3850
98274f07
TI		 3851static int snd_hdspm_hw_rule_channels_rate(struct snd_pcm_hw_params *params,
3852 struct snd_pcm_hw_rule * rule)
763f356c 3853{
98274f07
TI		 3854 struct hdspm *hdspm = rule->private;
3855 struct snd_interval *c =
763f356c 3856 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
98274f07 3857 struct snd_interval *r =
763f356c
TI		 3858 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
3859
ffb2c3c0 3860 if (r->min > 48000 && r->max <= 96000) {
98274f07 3861 struct snd_interval t = {
ffb2c3c0 3862 .min = hdspm->ds_channels,
763f356c
TI		 3863 .max = hdspm->ds_channels,
3864 .integer = 1,
3865 };
3866 return snd_interval_refine(c, &t);
3867 } else if (r->max < 64000) {
98274f07 3868 struct snd_interval t = {
ffb2c3c0 3869 .min = hdspm->ss_channels,
763f356c
TI		 3870 .max = hdspm->ss_channels,
3871 .integer = 1,
3872 };
3873 return snd_interval_refine(c, &t);
3874 }
3875 return 0;
3876}
3877
98274f07
TI		 3878static int snd_hdspm_hw_rule_rate_channels(struct snd_pcm_hw_params *params,
3879 struct snd_pcm_hw_rule * rule)
763f356c 3880{
98274f07
TI		 3881 struct hdspm *hdspm = rule->private;
3882 struct snd_interval *c =
763f356c 3883 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
98274f07 3884 struct snd_interval *r =
763f356c
TI		 3885 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
3886
ffb2c3c0 3887 if (c->min >= hdspm->ss_channels) {
98274f07 3888 struct snd_interval t = {
763f356c
TI		 3889 .min = 32000,
3890 .max = 48000,
3891 .integer = 1,
3892 };
3893 return snd_interval_refine(r, &t);
ffb2c3c0 3894 } else if (c->max <= hdspm->ds_channels) {
98274f07 3895 struct snd_interval t = {
763f356c
TI		 3896 .min = 64000,
3897 .max = 96000,
3898 .integer = 1,
3899 };
3900
3901 return snd_interval_refine(r, &t);
3902 }
3903 return 0;
3904}
3905
ffb2c3c0
RB		 3906static int snd_hdspm_hw_rule_channels(struct snd_pcm_hw_params *params,
3907 struct snd_pcm_hw_rule *rule)
3908{
3909 unsigned int list[3];
3910 struct hdspm *hdspm = rule->private;
3911 struct snd_interval *c = hw_param_interval(params,
3912 SNDRV_PCM_HW_PARAM_CHANNELS);
3913 if (hdspm->is_aes32) {
3914 list[0] = hdspm->qs_channels;
3915 list[1] = hdspm->ds_channels;
3916 list[2] = hdspm->ss_channels;
3917 return snd_interval_list(c, 3, list, 0);
3918 } else {
3919 list[0] = hdspm->ds_channels;
3920 list[1] = hdspm->ss_channels;
3921 return snd_interval_list(c, 2, list, 0);
3922 }
3923}
3924
3925
3926static unsigned int hdspm_aes32_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
3927
3928static struct snd_pcm_hw_constraint_list hdspm_hw_constraints_aes32_sample_rates = {
3929 .count = ARRAY_SIZE(hdspm_aes32_sample_rates),
3930 .list = hdspm_aes32_sample_rates,
3931 .mask = 0
3932};
3933
98274f07 3934static int snd_hdspm_playback_open(struct snd_pcm_substream *substream)
763f356c 3935{
98274f07
TI		 3936 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
3937 struct snd_pcm_runtime *runtime = substream->runtime;
763f356c 3938
763f356c
TI		 3939 spin_lock_irq(&hdspm->lock);
3940
3941 snd_pcm_set_sync(substream);
3942
3943 runtime->hw = snd_hdspm_playback_subinfo;
3944
3945 if (hdspm->capture_substream == NULL)
3946 hdspm_stop_audio(hdspm);
3947
3948 hdspm->playback_pid = current->pid;
3949 hdspm->playback_substream = substream;
3950
3951 spin_unlock_irq(&hdspm->lock);
3952
3953 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
3954
3955 snd_pcm_hw_constraint_list(runtime, 0,
3956 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
3957 &hw_constraints_period_sizes);
3958
ffb2c3c0
RB		 3959 if (hdspm->is_aes32) {
3960 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
3961 &hdspm_hw_constraints_aes32_sample_rates);
3962 } else {
3963 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
3964 snd_hdspm_hw_rule_channels, hdspm,
3965 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
3966 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
3967 snd_hdspm_hw_rule_channels_rate, hdspm,
3968 SNDRV_PCM_HW_PARAM_RATE, -1);
3969
3970 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
3971 snd_hdspm_hw_rule_rate_channels, hdspm,
3972 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
3973 }
763f356c
TI		 3974 return 0;
3975}
3976
98274f07 3977static int snd_hdspm_playback_release(struct snd_pcm_substream *substream)
763f356c 3978{
98274f07 3979 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
763f356c
TI		 3980
3981 spin_lock_irq(&hdspm->lock);
3982
3983 hdspm->playback_pid = -1;
3984 hdspm->playback_substream = NULL;
3985
3986 spin_unlock_irq(&hdspm->lock);
3987
3988 return 0;
3989}
3990
3991
98274f07 3992static int snd_hdspm_capture_open(struct snd_pcm_substream *substream)
763f356c 3993{
98274f07
TI		 3994 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
3995 struct snd_pcm_runtime *runtime = substream->runtime;
763f356c
TI		 3996
3997 spin_lock_irq(&hdspm->lock);
3998 snd_pcm_set_sync(substream);
3999 runtime->hw = snd_hdspm_capture_subinfo;
4000
4001 if (hdspm->playback_substream == NULL)
4002 hdspm_stop_audio(hdspm);
4003
4004 hdspm->capture_pid = current->pid;
4005 hdspm->capture_substream = substream;
4006
4007 spin_unlock_irq(&hdspm->lock);
4008
4009 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4010 snd_pcm_hw_constraint_list(runtime, 0,
4011 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
4012 &hw_constraints_period_sizes);
ffb2c3c0
RB		 4013 if (hdspm->is_aes32) {
4014 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4015 &hdspm_hw_constraints_aes32_sample_rates);
4016 } else {
4017 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4018 snd_hdspm_hw_rule_channels, hdspm,
4019 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4020 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4021 snd_hdspm_hw_rule_channels_rate, hdspm,
4022 SNDRV_PCM_HW_PARAM_RATE, -1);
4023
4024 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4025 snd_hdspm_hw_rule_rate_channels, hdspm,
4026 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4027 }
763f356c
TI		 4028 return 0;
4029}
4030
98274f07 4031static int snd_hdspm_capture_release(struct snd_pcm_substream *substream)
763f356c 4032{
98274f07 4033 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
763f356c
TI		 4034
4035 spin_lock_irq(&hdspm->lock);
4036
4037 hdspm->capture_pid = -1;
4038 hdspm->capture_substream = NULL;
4039
4040 spin_unlock_irq(&hdspm->lock);
4041 return 0;
4042}
4043
98274f07 4044static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep * hw, struct file *file)
763f356c
TI		 4045{
4046 /* we have nothing to initialize but the call is required */
4047 return 0;
4048}
4049
4050
98274f07 4051static int snd_hdspm_hwdep_ioctl(struct snd_hwdep * hw, struct file *file,
763f356c
TI		 4052 unsigned int cmd, unsigned long arg)
4053{
98274f07
TI		 4054 struct hdspm *hdspm = (struct hdspm *) hw->private_data;
4055 struct hdspm_mixer_ioctl mixer;
4056 struct hdspm_config_info info;
4057 struct hdspm_version hdspm_version;
4058 struct hdspm_peak_rms_ioctl rms;
763f356c
TI		 4059
4060 switch (cmd) {
4061
4062
4063 case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS:
4064 if (copy_from_user(&rms, (void __user *)arg, sizeof(rms)))
4065 return -EFAULT;
4066 /* maybe there is a chance to memorymap in future so dont touch just copy */
4067 if(copy_to_user_fromio((void __user *)rms.peak,
4068 hdspm->iobase+HDSPM_MADI_peakrmsbase,
98274f07 4069 sizeof(struct hdspm_peak_rms)) != 0 )
763f356c
TI		 4070 return -EFAULT;
4071
4072 break;
4073
4074
4075 case SNDRV_HDSPM_IOCTL_GET_CONFIG_INFO:
4076
4077 spin_lock_irq(&hdspm->lock);
4078 info.pref_sync_ref =
4079 (unsigned char) hdspm_pref_sync_ref(hdspm);
4080 info.wordclock_sync_check =
4081 (unsigned char) hdspm_wc_sync_check(hdspm);
4082
4083 info.system_sample_rate = hdspm->system_sample_rate;
4084 info.autosync_sample_rate =
4085 hdspm_external_sample_rate(hdspm);
4086 info.system_clock_mode =
4087 (unsigned char) hdspm_system_clock_mode(hdspm);
4088 info.clock_source =
4089 (unsigned char) hdspm_clock_source(hdspm);
4090 info.autosync_ref =
4091 (unsigned char) hdspm_autosync_ref(hdspm);
4092 info.line_out = (unsigned char) hdspm_line_out(hdspm);
4093 info.passthru = 0;
4094 spin_unlock_irq(&hdspm->lock);
4095 if (copy_to_user((void __user *) arg, &info, sizeof(info)))
4096 return -EFAULT;
4097 break;
4098
4099 case SNDRV_HDSPM_IOCTL_GET_VERSION:
4100 hdspm_version.firmware_rev = hdspm->firmware_rev;
4101 if (copy_to_user((void __user *) arg, &hdspm_version,
4102 sizeof(hdspm_version)))
4103 return -EFAULT;
4104 break;
4105
4106 case SNDRV_HDSPM_IOCTL_GET_MIXER:
4107 if (copy_from_user(&mixer, (void __user *)arg, sizeof(mixer)))
4108 return -EFAULT;
4109 if (copy_to_user
98274f07 4110 ((void __user *)mixer.mixer, hdspm->mixer, sizeof(struct hdspm_mixer)))
763f356c
TI		 4111 return -EFAULT;
4112 break;
4113
4114 default:
4115 return -EINVAL;
4116 }
4117 return 0;
4118}
4119
98274f07 4120static struct snd_pcm_ops snd_hdspm_playback_ops = {
763f356c
TI		 4121 .open = snd_hdspm_playback_open,
4122 .close = snd_hdspm_playback_release,
4123 .ioctl = snd_hdspm_ioctl,
4124 .hw_params = snd_hdspm_hw_params,
4125 .hw_free = snd_hdspm_hw_free,
4126 .prepare = snd_hdspm_prepare,
4127 .trigger = snd_hdspm_trigger,
4128 .pointer = snd_hdspm_hw_pointer,
4129 .copy = snd_hdspm_playback_copy,
4130 .silence = snd_hdspm_hw_silence,
4131 .page = snd_pcm_sgbuf_ops_page,
4132};
4133
98274f07 4134static struct snd_pcm_ops snd_hdspm_capture_ops = {
763f356c
TI		 4135 .open = snd_hdspm_capture_open,
4136 .close = snd_hdspm_capture_release,
4137 .ioctl = snd_hdspm_ioctl,
4138 .hw_params = snd_hdspm_hw_params,
4139 .hw_free = snd_hdspm_hw_free,
4140 .prepare = snd_hdspm_prepare,
4141 .trigger = snd_hdspm_trigger,
4142 .pointer = snd_hdspm_hw_pointer,
4143 .copy = snd_hdspm_capture_copy,
4144 .page = snd_pcm_sgbuf_ops_page,
4145};
4146
98274f07
TI		 4147static int __devinit snd_hdspm_create_hwdep(struct snd_card *card,
4148 struct hdspm * hdspm)
763f356c 4149{
98274f07 4150 struct snd_hwdep *hw;
763f356c
TI		 4151 int err;
4152
4153 if ((err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw)) < 0)
4154 return err;
4155
4156 hdspm->hwdep = hw;
4157 hw->private_data = hdspm;
4158 strcpy(hw->name, "HDSPM hwdep interface");
4159
4160 hw->ops.open = snd_hdspm_hwdep_dummy_op;
4161 hw->ops.ioctl = snd_hdspm_hwdep_ioctl;
4162 hw->ops.release = snd_hdspm_hwdep_dummy_op;
4163
4164 return 0;
4165}
4166
4167
4168/*------------------------------------------------------------
4169 memory interface
4170 ------------------------------------------------------------*/
98274f07 4171static int __devinit snd_hdspm_preallocate_memory(struct hdspm * hdspm)
763f356c
TI		 4172{
4173 int err;
98274f07 4174 struct snd_pcm *pcm;
763f356c
TI		 4175 size_t wanted;
4176
4177 pcm = hdspm->pcm;
4178
3cee5a60
RB		 4179/* wanted = HDSPM_DMA_AREA_BYTES + 4096;*/ /* dont know why, but it works */
4180 wanted = HDSPM_DMA_AREA_BYTES;
763f356c
TI		 4181
4182 if ((err =
4183 snd_pcm_lib_preallocate_pages_for_all(pcm,
4184 SNDRV_DMA_TYPE_DEV_SG,
4185 snd_dma_pci_data(hdspm->pci),
4186 wanted,
4187 wanted)) < 0) {
e2eba3e7 4188 snd_printdd("Could not preallocate %zd Bytes\n", wanted);
763f356c
TI		 4189
4190 return err;
4191 } else
e2eba3e7 4192 snd_printdd(" Preallocated %zd Bytes\n", wanted);
763f356c
TI		 4193
4194 return 0;
4195}
4196
98274f07 4197static void hdspm_set_sgbuf(struct hdspm * hdspm, struct snd_sg_buf *sgbuf,
763f356c
TI		 4198 unsigned int reg, int channels)
4199{
4200 int i;
4201 for (i = 0; i < (channels * 16); i++)
4202 hdspm_write(hdspm, reg + 4 * i,
4203 snd_pcm_sgbuf_get_addr(sgbuf,
4204 (size_t) 4096 * i));
4205}
4206
4207/* ------------- ALSA Devices ---------------------------- */
98274f07
TI		 4208static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
4209 struct hdspm * hdspm)
763f356c 4210{
98274f07 4211 struct snd_pcm *pcm;
763f356c
TI		 4212 int err;
4213
4214 if ((err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm)) < 0)
4215 return err;
4216
4217 hdspm->pcm = pcm;
4218 pcm->private_data = hdspm;
4219 strcpy(pcm->name, hdspm->card_name);
4220
4221 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
4222 &snd_hdspm_playback_ops);
4223 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
4224 &snd_hdspm_capture_ops);
4225
4226 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4227
4228 if ((err = snd_hdspm_preallocate_memory(hdspm)) < 0)
4229 return err;
4230
4231 return 0;
4232}
4233
98274f07 4234static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm)
763f356c
TI		 4235{
4236 snd_hdspm_flush_midi_input(hdspm, 0);
4237 snd_hdspm_flush_midi_input(hdspm, 1);
4238}
4239
98274f07
TI		 4240static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
4241 struct hdspm * hdspm)
763f356c
TI		 4242{
4243 int err;
4244
4245 snd_printdd("Create card...\n");
4246 if ((err = snd_hdspm_create_pcm(card, hdspm)) < 0)
4247 return err;
4248
4249 if ((err = snd_hdspm_create_midi(card, hdspm, 0)) < 0)
4250 return err;
4251
4252 if ((err = snd_hdspm_create_midi(card, hdspm, 1)) < 0)
4253 return err;
4254
4255 if ((err = snd_hdspm_create_controls(card, hdspm)) < 0)
4256 return err;
4257
4258 if ((err = snd_hdspm_create_hwdep(card, hdspm)) < 0)
4259 return err;
4260
4261 snd_printdd("proc init...\n");
4262 snd_hdspm_proc_init(hdspm);
4263
4264 hdspm->system_sample_rate = -1;
4265 hdspm->last_external_sample_rate = -1;
4266 hdspm->last_internal_sample_rate = -1;
4267 hdspm->playback_pid = -1;
4268 hdspm->capture_pid = -1;
4269 hdspm->capture_substream = NULL;
4270 hdspm->playback_substream = NULL;
4271
4272 snd_printdd("Set defaults...\n");
4273 if ((err = snd_hdspm_set_defaults(hdspm)) < 0)
4274 return err;
4275
4276 snd_printdd("Update mixer controls...\n");
4277 hdspm_update_simple_mixer_controls(hdspm);
4278
4279 snd_printdd("Initializeing complete ???\n");
4280
4281 if ((err = snd_card_register(card)) < 0) {
4282 snd_printk(KERN_ERR "HDSPM: error registering card\n");
4283 return err;
4284 }
4285
4286 snd_printdd("... yes now\n");
4287
4288 return 0;
4289}
4290
98274f07 4291static int __devinit snd_hdspm_create(struct snd_card *card, struct hdspm * hdspm,
763f356c
TI		 4292 int precise_ptr, int enable_monitor)
4293{
4294 struct pci_dev *pci = hdspm->pci;
4295 int err;
4296 int i;
4297
4298 unsigned long io_extent;
4299
4300 hdspm->irq = -1;
4301 hdspm->irq_count = 0;
4302
4303 hdspm->midi[0].rmidi = NULL;
4304 hdspm->midi[1].rmidi = NULL;
4305 hdspm->midi[0].input = NULL;
4306 hdspm->midi[1].input = NULL;
4307 hdspm->midi[0].output = NULL;
4308 hdspm->midi[1].output = NULL;
4309 spin_lock_init(&hdspm->midi[0].lock);
4310 spin_lock_init(&hdspm->midi[1].lock);
4311 hdspm->iobase = NULL;
4312 hdspm->control_register = 0;
4313 hdspm->control2_register = 0;
4314
4315 hdspm->playback_buffer = NULL;
4316 hdspm->capture_buffer = NULL;
4317
4318 for (i = 0; i < HDSPM_MAX_CHANNELS; ++i)
4319 hdspm->playback_mixer_ctls[i] = NULL;
4320 hdspm->mixer = NULL;
4321
4322 hdspm->card = card;
4323
4324 spin_lock_init(&hdspm->lock);
4325
4326 tasklet_init(&hdspm->midi_tasklet,
4327 hdspm_midi_tasklet, (unsigned long) hdspm);
4328
4329 pci_read_config_word(hdspm->pci,
4330 PCI_CLASS_REVISION, &hdspm->firmware_rev);
4331
3cee5a60
RB		 4332 hdspm->is_aes32 = (hdspm->firmware_rev >= HDSPM_AESREVISION);
4333
763f356c 4334 strcpy(card->mixername, "Xilinx FPGA");
3cee5a60
RB		 4335 if (hdspm->is_aes32) {
4336 strcpy(card->driver, "HDSPAES32");
4337 hdspm->card_name = "RME HDSPM AES32";
4338 } else {
4339 strcpy(card->driver, "HDSPM");
4340 hdspm->card_name = "RME HDSPM MADI";
4341 }
763f356c
TI		 4342
4343 if ((err = pci_enable_device(pci)) < 0)
4344 return err;
4345
4346 pci_set_master(hdspm->pci);
4347
4348 if ((err = pci_request_regions(pci, "hdspm")) < 0)
4349 return err;
4350
4351 hdspm->port = pci_resource_start(pci, 0);
4352 io_extent = pci_resource_len(pci, 0);
4353
4354 snd_printdd("grabbed memory region 0x%lx-0x%lx\n",
4355 hdspm->port, hdspm->port + io_extent - 1);
4356
4357
4358 if ((hdspm->iobase = ioremap_nocache(hdspm->port, io_extent)) == NULL) {
4359 snd_printk(KERN_ERR "HDSPM: unable to remap region 0x%lx-0x%lx\n",
4360 hdspm->port, hdspm->port + io_extent - 1);
4361 return -EBUSY;
4362 }
4363 snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n",
4364 (unsigned long)hdspm->iobase, hdspm->port,
4365 hdspm->port + io_extent - 1);
4366
4367 if (request_irq(pci->irq, snd_hdspm_interrupt,
437a5a46 4368 IRQF_SHARED, "hdspm", hdspm)) {
763f356c
TI		 4369 snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq);
4370 return -EBUSY;
4371 }
4372
4373 snd_printdd("use IRQ %d\n", pci->irq);
4374
4375 hdspm->irq = pci->irq;
4376 hdspm->precise_ptr = precise_ptr;
4377
4378 hdspm->monitor_outs = enable_monitor;
4379
e2eba3e7 4380 snd_printdd("kmalloc Mixer memory of %zd Bytes\n",
98274f07
TI		 4381 sizeof(struct hdspm_mixer));
4382 if ((hdspm->mixer = kmalloc(sizeof(struct hdspm_mixer), GFP_KERNEL))
763f356c
TI		 4383 == NULL) {
4384 snd_printk(KERN_ERR "HDSPM: unable to kmalloc Mixer memory of %d Bytes\n",
98274f07 4385 (int)sizeof(struct hdspm_mixer));
763f356c
TI		 4386 return err;
4387 }
4388
4389 hdspm->ss_channels = MADI_SS_CHANNELS;
4390 hdspm->ds_channels = MADI_DS_CHANNELS;
4391 hdspm->qs_channels = MADI_QS_CHANNELS;
4392
4393 snd_printdd("create alsa devices.\n");
4394 if ((err = snd_hdspm_create_alsa_devices(card, hdspm)) < 0)
4395 return err;
4396
4397 snd_hdspm_initialize_midi_flush(hdspm);
4398
4399 return 0;
4400}
4401
98274f07 4402static int snd_hdspm_free(struct hdspm * hdspm)
763f356c
TI		 4403{
4404
4405 if (hdspm->port) {
4406
4407 /* stop th audio, and cancel all interrupts */
4408 hdspm->control_register &=
4409 ~(HDSPM_Start | HDSPM_AudioInterruptEnable
4410 | HDSPM_Midi0InterruptEnable |
4411 HDSPM_Midi1InterruptEnable);
4412 hdspm_write(hdspm, HDSPM_controlRegister,
4413 hdspm->control_register);
4414 }
4415
4416 if (hdspm->irq >= 0)
4417 free_irq(hdspm->irq, (void *) hdspm);
4418
4419
fc58422a 4420 kfree(hdspm->mixer);
763f356c
TI		 4421
4422 if (hdspm->iobase)
4423 iounmap(hdspm->iobase);
4424
763f356c
TI		 4425 if (hdspm->port)
4426 pci_release_regions(hdspm->pci);
4427
4428 pci_disable_device(hdspm->pci);
4429 return 0;
4430}
4431
98274f07 4432static void snd_hdspm_card_free(struct snd_card *card)
763f356c 4433{
98274f07 4434 struct hdspm *hdspm = (struct hdspm *) card->private_data;
763f356c
TI		 4435
4436 if (hdspm)
4437 snd_hdspm_free(hdspm);
4438}
4439
4440static int __devinit snd_hdspm_probe(struct pci_dev *pci,
4441 const struct pci_device_id *pci_id)
4442{
4443 static int dev;
98274f07
TI		 4444 struct hdspm *hdspm;
4445 struct snd_card *card;
763f356c
TI		 4446 int err;
4447
4448 if (dev >= SNDRV_CARDS)
4449 return -ENODEV;
4450 if (!enable[dev]) {
4451 dev++;
4452 return -ENOENT;
4453 }
4454
4455 if (!(card = snd_card_new(index[dev], id[dev],
98274f07 4456 THIS_MODULE, sizeof(struct hdspm))))
763f356c
TI		 4457 return -ENOMEM;
4458
98274f07 4459 hdspm = (struct hdspm *) card->private_data;
763f356c
TI		 4460 card->private_free = snd_hdspm_card_free;
4461 hdspm->dev = dev;
4462 hdspm->pci = pci;
4463
c187c041
TI		 4464 snd_card_set_dev(card, &pci->dev);
4465
763f356c
TI		 4466 if ((err =
4467 snd_hdspm_create(card, hdspm, precise_ptr[dev],
4468 enable_monitor[dev])) < 0) {
4469 snd_card_free(card);
4470 return err;
4471 }
4472
4473 strcpy(card->shortname, "HDSPM MADI");
4474 sprintf(card->longname, "%s at 0x%lx, irq %d", hdspm->card_name,
4475 hdspm->port, hdspm->irq);
4476
4477 if ((err = snd_card_register(card)) < 0) {
4478 snd_card_free(card);
4479 return err;
4480 }
4481
4482 pci_set_drvdata(pci, card);
4483
4484 dev++;
4485 return 0;
4486}
4487
4488static void __devexit snd_hdspm_remove(struct pci_dev *pci)
4489{
4490 snd_card_free(pci_get_drvdata(pci));
4491 pci_set_drvdata(pci, NULL);
4492}
4493
4494static struct pci_driver driver = {
4495 .name = "RME Hammerfall DSP MADI",
4496 .id_table = snd_hdspm_ids,
4497 .probe = snd_hdspm_probe,
4498 .remove = __devexit_p(snd_hdspm_remove),
4499};
4500
4501
4502static int __init alsa_card_hdspm_init(void)
4503{
4504 return pci_register_driver(&driver);
4505}
4506
4507static void __exit alsa_card_hdspm_exit(void)
4508{
4509 pci_unregister_driver(&driver);
4510}
4511
4512module_init(alsa_card_hdspm_init)
4513module_exit(alsa_card_hdspm_exit)
Linux kernel - Deliverables
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