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6c742509 SG |
1 | /* |
2 | * atmel_ssc_dai.c -- ALSA SoC ATMEL SSC Audio Layer Platform driver | |
3 | * | |
4 | * Copyright (C) 2005 SAN People | |
5 | * Copyright (C) 2008 Atmel | |
6 | * | |
7 | * Author: Sedji Gaouaou <sedji.gaouaou@atmel.com> | |
8 | * ATMEL CORP. | |
9 | * | |
10 | * Based on at91-ssc.c by | |
11 | * Frank Mandarino <fmandarino@endrelia.com> | |
12 | * Based on pxa2xx Platform drivers by | |
64ca0404 | 13 | * Liam Girdwood <lrg@slimlogic.co.uk> |
6c742509 SG |
14 | * |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License as published by | |
17 | * the Free Software Foundation; either version 2 of the License, or | |
18 | * (at your option) any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License | |
26 | * along with this program; if not, write to the Free Software | |
27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
28 | */ | |
29 | ||
30 | #include <linux/init.h> | |
31 | #include <linux/module.h> | |
32 | #include <linux/interrupt.h> | |
33 | #include <linux/device.h> | |
34 | #include <linux/delay.h> | |
35 | #include <linux/clk.h> | |
36 | #include <linux/atmel_pdc.h> | |
37 | ||
38 | #include <linux/atmel-ssc.h> | |
39 | #include <sound/core.h> | |
40 | #include <sound/pcm.h> | |
41 | #include <sound/pcm_params.h> | |
42 | #include <sound/initval.h> | |
43 | #include <sound/soc.h> | |
44 | ||
6c742509 SG |
45 | #include "atmel-pcm.h" |
46 | #include "atmel_ssc_dai.h" | |
47 | ||
48 | ||
6c742509 | 49 | #define NUM_SSC_DEVICES 3 |
6c742509 SG |
50 | |
51 | /* | |
52 | * SSC PDC registers required by the PCM DMA engine. | |
53 | */ | |
54 | static struct atmel_pdc_regs pdc_tx_reg = { | |
55 | .xpr = ATMEL_PDC_TPR, | |
56 | .xcr = ATMEL_PDC_TCR, | |
57 | .xnpr = ATMEL_PDC_TNPR, | |
58 | .xncr = ATMEL_PDC_TNCR, | |
59 | }; | |
60 | ||
61 | static struct atmel_pdc_regs pdc_rx_reg = { | |
62 | .xpr = ATMEL_PDC_RPR, | |
63 | .xcr = ATMEL_PDC_RCR, | |
64 | .xnpr = ATMEL_PDC_RNPR, | |
65 | .xncr = ATMEL_PDC_RNCR, | |
66 | }; | |
67 | ||
68 | /* | |
69 | * SSC & PDC status bits for transmit and receive. | |
70 | */ | |
71 | static struct atmel_ssc_mask ssc_tx_mask = { | |
72 | .ssc_enable = SSC_BIT(CR_TXEN), | |
73 | .ssc_disable = SSC_BIT(CR_TXDIS), | |
74 | .ssc_endx = SSC_BIT(SR_ENDTX), | |
75 | .ssc_endbuf = SSC_BIT(SR_TXBUFE), | |
f1b0dd8b | 76 | .ssc_error = SSC_BIT(SR_OVRUN), |
6c742509 SG |
77 | .pdc_enable = ATMEL_PDC_TXTEN, |
78 | .pdc_disable = ATMEL_PDC_TXTDIS, | |
79 | }; | |
80 | ||
81 | static struct atmel_ssc_mask ssc_rx_mask = { | |
82 | .ssc_enable = SSC_BIT(CR_RXEN), | |
83 | .ssc_disable = SSC_BIT(CR_RXDIS), | |
84 | .ssc_endx = SSC_BIT(SR_ENDRX), | |
85 | .ssc_endbuf = SSC_BIT(SR_RXBUFF), | |
f1b0dd8b | 86 | .ssc_error = SSC_BIT(SR_OVRUN), |
6c742509 SG |
87 | .pdc_enable = ATMEL_PDC_RXTEN, |
88 | .pdc_disable = ATMEL_PDC_RXTDIS, | |
89 | }; | |
90 | ||
91 | ||
92 | /* | |
93 | * DMA parameters. | |
94 | */ | |
95 | static struct atmel_pcm_dma_params ssc_dma_params[NUM_SSC_DEVICES][2] = { | |
96 | {{ | |
97 | .name = "SSC0 PCM out", | |
98 | .pdc = &pdc_tx_reg, | |
99 | .mask = &ssc_tx_mask, | |
100 | }, | |
101 | { | |
102 | .name = "SSC0 PCM in", | |
103 | .pdc = &pdc_rx_reg, | |
104 | .mask = &ssc_rx_mask, | |
105 | } }, | |
6c742509 SG |
106 | {{ |
107 | .name = "SSC1 PCM out", | |
108 | .pdc = &pdc_tx_reg, | |
109 | .mask = &ssc_tx_mask, | |
110 | }, | |
111 | { | |
112 | .name = "SSC1 PCM in", | |
113 | .pdc = &pdc_rx_reg, | |
114 | .mask = &ssc_rx_mask, | |
115 | } }, | |
116 | {{ | |
117 | .name = "SSC2 PCM out", | |
118 | .pdc = &pdc_tx_reg, | |
119 | .mask = &ssc_tx_mask, | |
120 | }, | |
121 | { | |
122 | .name = "SSC2 PCM in", | |
123 | .pdc = &pdc_rx_reg, | |
124 | .mask = &ssc_rx_mask, | |
125 | } }, | |
6c742509 SG |
126 | }; |
127 | ||
128 | ||
129 | static struct atmel_ssc_info ssc_info[NUM_SSC_DEVICES] = { | |
130 | { | |
131 | .name = "ssc0", | |
132 | .lock = __SPIN_LOCK_UNLOCKED(ssc_info[0].lock), | |
133 | .dir_mask = SSC_DIR_MASK_UNUSED, | |
134 | .initialized = 0, | |
135 | }, | |
6c742509 SG |
136 | { |
137 | .name = "ssc1", | |
138 | .lock = __SPIN_LOCK_UNLOCKED(ssc_info[1].lock), | |
139 | .dir_mask = SSC_DIR_MASK_UNUSED, | |
140 | .initialized = 0, | |
141 | }, | |
142 | { | |
143 | .name = "ssc2", | |
144 | .lock = __SPIN_LOCK_UNLOCKED(ssc_info[2].lock), | |
145 | .dir_mask = SSC_DIR_MASK_UNUSED, | |
146 | .initialized = 0, | |
147 | }, | |
6c742509 SG |
148 | }; |
149 | ||
150 | ||
151 | /* | |
152 | * SSC interrupt handler. Passes PDC interrupts to the DMA | |
153 | * interrupt handler in the PCM driver. | |
154 | */ | |
155 | static irqreturn_t atmel_ssc_interrupt(int irq, void *dev_id) | |
156 | { | |
157 | struct atmel_ssc_info *ssc_p = dev_id; | |
158 | struct atmel_pcm_dma_params *dma_params; | |
159 | u32 ssc_sr; | |
160 | u32 ssc_substream_mask; | |
161 | int i; | |
162 | ||
163 | ssc_sr = (unsigned long)ssc_readl(ssc_p->ssc->regs, SR) | |
164 | & (unsigned long)ssc_readl(ssc_p->ssc->regs, IMR); | |
165 | ||
166 | /* | |
167 | * Loop through the substreams attached to this SSC. If | |
168 | * a DMA-related interrupt occurred on that substream, call | |
169 | * the DMA interrupt handler function, if one has been | |
170 | * registered in the dma_params structure by the PCM driver. | |
171 | */ | |
172 | for (i = 0; i < ARRAY_SIZE(ssc_p->dma_params); i++) { | |
173 | dma_params = ssc_p->dma_params[i]; | |
174 | ||
175 | if ((dma_params != NULL) && | |
176 | (dma_params->dma_intr_handler != NULL)) { | |
177 | ssc_substream_mask = (dma_params->mask->ssc_endx | | |
178 | dma_params->mask->ssc_endbuf); | |
179 | if (ssc_sr & ssc_substream_mask) { | |
180 | dma_params->dma_intr_handler(ssc_sr, | |
181 | dma_params-> | |
182 | substream); | |
183 | } | |
184 | } | |
185 | } | |
186 | ||
187 | return IRQ_HANDLED; | |
188 | } | |
189 | ||
b6d6c6e9 PR |
190 | /* |
191 | * When the bit clock is input, limit the maximum rate according to the | |
192 | * Serial Clock Ratio Considerations section from the SSC documentation: | |
193 | * | |
194 | * The Transmitter and the Receiver can be programmed to operate | |
195 | * with the clock signals provided on either the TK or RK pins. | |
196 | * This allows the SSC to support many slave-mode data transfers. | |
197 | * In this case, the maximum clock speed allowed on the RK pin is: | |
198 | * - Peripheral clock divided by 2 if Receiver Frame Synchro is input | |
199 | * - Peripheral clock divided by 3 if Receiver Frame Synchro is output | |
200 | * In addition, the maximum clock speed allowed on the TK pin is: | |
201 | * - Peripheral clock divided by 6 if Transmit Frame Synchro is input | |
202 | * - Peripheral clock divided by 2 if Transmit Frame Synchro is output | |
203 | * | |
204 | * When the bit clock is output, limit the rate according to the | |
205 | * SSC divider restrictions. | |
206 | */ | |
207 | static int atmel_ssc_hw_rule_rate(struct snd_pcm_hw_params *params, | |
208 | struct snd_pcm_hw_rule *rule) | |
209 | { | |
210 | struct atmel_ssc_info *ssc_p = rule->private; | |
211 | struct ssc_device *ssc = ssc_p->ssc; | |
212 | struct snd_interval *i = hw_param_interval(params, rule->var); | |
213 | struct snd_interval t; | |
214 | struct snd_ratnum r = { | |
215 | .den_min = 1, | |
216 | .den_max = 4095, | |
217 | .den_step = 1, | |
218 | }; | |
219 | unsigned int num = 0, den = 0; | |
220 | int frame_size; | |
221 | int mck_div = 2; | |
222 | int ret; | |
223 | ||
224 | frame_size = snd_soc_params_to_frame_size(params); | |
225 | if (frame_size < 0) | |
226 | return frame_size; | |
227 | ||
228 | switch (ssc_p->daifmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
229 | case SND_SOC_DAIFMT_CBM_CFS: | |
230 | if ((ssc_p->dir_mask & SSC_DIR_MASK_CAPTURE) | |
231 | && ssc->clk_from_rk_pin) | |
232 | /* Receiver Frame Synchro (i.e. capture) | |
233 | * is output (format is _CFS) and the RK pin | |
234 | * is used for input (format is _CBM_). | |
235 | */ | |
236 | mck_div = 3; | |
237 | break; | |
238 | ||
239 | case SND_SOC_DAIFMT_CBM_CFM: | |
240 | if ((ssc_p->dir_mask & SSC_DIR_MASK_PLAYBACK) | |
241 | && !ssc->clk_from_rk_pin) | |
242 | /* Transmit Frame Synchro (i.e. playback) | |
243 | * is input (format is _CFM) and the TK pin | |
244 | * is used for input (format _CBM_ but not | |
245 | * using the RK pin). | |
246 | */ | |
247 | mck_div = 6; | |
248 | break; | |
249 | } | |
250 | ||
251 | switch (ssc_p->daifmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
252 | case SND_SOC_DAIFMT_CBS_CFS: | |
253 | r.num = ssc_p->mck_rate / mck_div / frame_size; | |
254 | ||
255 | ret = snd_interval_ratnum(i, 1, &r, &num, &den); | |
256 | if (ret >= 0 && den && rule->var == SNDRV_PCM_HW_PARAM_RATE) { | |
257 | params->rate_num = num; | |
258 | params->rate_den = den; | |
259 | } | |
260 | break; | |
261 | ||
262 | case SND_SOC_DAIFMT_CBM_CFS: | |
263 | case SND_SOC_DAIFMT_CBM_CFM: | |
264 | t.min = 8000; | |
265 | t.max = ssc_p->mck_rate / mck_div / frame_size; | |
266 | t.openmin = t.openmax = 0; | |
267 | t.integer = 0; | |
268 | ret = snd_interval_refine(i, &t); | |
269 | break; | |
270 | ||
271 | default: | |
272 | ret = -EINVAL; | |
273 | break; | |
274 | } | |
275 | ||
276 | return ret; | |
277 | } | |
6c742509 SG |
278 | |
279 | /*-------------------------------------------------------------------------*\ | |
280 | * DAI functions | |
281 | \*-------------------------------------------------------------------------*/ | |
282 | /* | |
283 | * Startup. Only that one substream allowed in each direction. | |
284 | */ | |
dee89c4d MB |
285 | static int atmel_ssc_startup(struct snd_pcm_substream *substream, |
286 | struct snd_soc_dai *dai) | |
6c742509 | 287 | { |
f0fba2ad | 288 | struct atmel_ssc_info *ssc_p = &ssc_info[dai->id]; |
01f00d55 BS |
289 | struct atmel_pcm_dma_params *dma_params; |
290 | int dir, dir_mask; | |
b6d6c6e9 | 291 | int ret; |
6c742509 SG |
292 | |
293 | pr_debug("atmel_ssc_startup: SSC_SR=0x%u\n", | |
294 | ssc_readl(ssc_p->ssc->regs, SR)); | |
295 | ||
cbaadf0f BS |
296 | /* Enable PMC peripheral clock for this SSC */ |
297 | pr_debug("atmel_ssc_dai: Starting clock\n"); | |
298 | clk_enable(ssc_p->ssc->clk); | |
b6d6c6e9 | 299 | ssc_p->mck_rate = clk_get_rate(ssc_p->ssc->clk); |
cbaadf0f BS |
300 | |
301 | /* Reset the SSC to keep it at a clean status */ | |
302 | ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST)); | |
303 | ||
01f00d55 BS |
304 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
305 | dir = 0; | |
6c742509 | 306 | dir_mask = SSC_DIR_MASK_PLAYBACK; |
01f00d55 BS |
307 | } else { |
308 | dir = 1; | |
6c742509 | 309 | dir_mask = SSC_DIR_MASK_CAPTURE; |
01f00d55 BS |
310 | } |
311 | ||
b6d6c6e9 PR |
312 | ret = snd_pcm_hw_rule_add(substream->runtime, 0, |
313 | SNDRV_PCM_HW_PARAM_RATE, | |
314 | atmel_ssc_hw_rule_rate, | |
315 | ssc_p, | |
316 | SNDRV_PCM_HW_PARAM_FRAME_BITS, | |
317 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); | |
318 | if (ret < 0) { | |
319 | dev_err(dai->dev, "Failed to specify rate rule: %d\n", ret); | |
320 | return ret; | |
321 | } | |
322 | ||
01f00d55 BS |
323 | dma_params = &ssc_dma_params[dai->id][dir]; |
324 | dma_params->ssc = ssc_p->ssc; | |
325 | dma_params->substream = substream; | |
326 | ||
327 | ssc_p->dma_params[dir] = dma_params; | |
328 | ||
329 | snd_soc_dai_set_dma_data(dai, substream, dma_params); | |
6c742509 SG |
330 | |
331 | spin_lock_irq(&ssc_p->lock); | |
332 | if (ssc_p->dir_mask & dir_mask) { | |
333 | spin_unlock_irq(&ssc_p->lock); | |
334 | return -EBUSY; | |
335 | } | |
336 | ssc_p->dir_mask |= dir_mask; | |
337 | spin_unlock_irq(&ssc_p->lock); | |
338 | ||
339 | return 0; | |
340 | } | |
341 | ||
342 | /* | |
343 | * Shutdown. Clear DMA parameters and shutdown the SSC if there | |
344 | * are no other substreams open. | |
345 | */ | |
dee89c4d MB |
346 | static void atmel_ssc_shutdown(struct snd_pcm_substream *substream, |
347 | struct snd_soc_dai *dai) | |
6c742509 | 348 | { |
f0fba2ad | 349 | struct atmel_ssc_info *ssc_p = &ssc_info[dai->id]; |
6c742509 SG |
350 | struct atmel_pcm_dma_params *dma_params; |
351 | int dir, dir_mask; | |
352 | ||
353 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
354 | dir = 0; | |
355 | else | |
356 | dir = 1; | |
357 | ||
358 | dma_params = ssc_p->dma_params[dir]; | |
359 | ||
360 | if (dma_params != NULL) { | |
6c742509 SG |
361 | dma_params->ssc = NULL; |
362 | dma_params->substream = NULL; | |
363 | ssc_p->dma_params[dir] = NULL; | |
364 | } | |
365 | ||
366 | dir_mask = 1 << dir; | |
367 | ||
368 | spin_lock_irq(&ssc_p->lock); | |
369 | ssc_p->dir_mask &= ~dir_mask; | |
370 | if (!ssc_p->dir_mask) { | |
371 | if (ssc_p->initialized) { | |
6c742509 SG |
372 | free_irq(ssc_p->ssc->irq, ssc_p); |
373 | ssc_p->initialized = 0; | |
374 | } | |
375 | ||
376 | /* Reset the SSC */ | |
377 | ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST)); | |
378 | /* Clear the SSC dividers */ | |
379 | ssc_p->cmr_div = ssc_p->tcmr_period = ssc_p->rcmr_period = 0; | |
380 | } | |
381 | spin_unlock_irq(&ssc_p->lock); | |
cbaadf0f BS |
382 | |
383 | /* Shutdown the SSC clock. */ | |
384 | pr_debug("atmel_ssc_dai: Stopping clock\n"); | |
385 | clk_disable(ssc_p->ssc->clk); | |
6c742509 SG |
386 | } |
387 | ||
388 | ||
389 | /* | |
390 | * Record the DAI format for use in hw_params(). | |
391 | */ | |
392 | static int atmel_ssc_set_dai_fmt(struct snd_soc_dai *cpu_dai, | |
393 | unsigned int fmt) | |
394 | { | |
395 | struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id]; | |
396 | ||
397 | ssc_p->daifmt = fmt; | |
398 | return 0; | |
399 | } | |
400 | ||
401 | /* | |
402 | * Record SSC clock dividers for use in hw_params(). | |
403 | */ | |
404 | static int atmel_ssc_set_dai_clkdiv(struct snd_soc_dai *cpu_dai, | |
405 | int div_id, int div) | |
406 | { | |
407 | struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id]; | |
408 | ||
409 | switch (div_id) { | |
410 | case ATMEL_SSC_CMR_DIV: | |
411 | /* | |
412 | * The same master clock divider is used for both | |
413 | * transmit and receive, so if a value has already | |
414 | * been set, it must match this value. | |
415 | */ | |
eb58960e PR |
416 | if (ssc_p->dir_mask != |
417 | (SSC_DIR_MASK_PLAYBACK | SSC_DIR_MASK_CAPTURE)) | |
418 | ssc_p->cmr_div = div; | |
419 | else if (ssc_p->cmr_div == 0) | |
6c742509 SG |
420 | ssc_p->cmr_div = div; |
421 | else | |
422 | if (div != ssc_p->cmr_div) | |
423 | return -EBUSY; | |
424 | break; | |
425 | ||
426 | case ATMEL_SSC_TCMR_PERIOD: | |
427 | ssc_p->tcmr_period = div; | |
428 | break; | |
429 | ||
430 | case ATMEL_SSC_RCMR_PERIOD: | |
431 | ssc_p->rcmr_period = div; | |
432 | break; | |
433 | ||
434 | default: | |
435 | return -EINVAL; | |
436 | } | |
437 | ||
438 | return 0; | |
439 | } | |
440 | ||
441 | /* | |
442 | * Configure the SSC. | |
443 | */ | |
444 | static int atmel_ssc_hw_params(struct snd_pcm_substream *substream, | |
dee89c4d MB |
445 | struct snd_pcm_hw_params *params, |
446 | struct snd_soc_dai *dai) | |
6c742509 | 447 | { |
f0fba2ad | 448 | int id = dai->id; |
6c742509 | 449 | struct atmel_ssc_info *ssc_p = &ssc_info[id]; |
048d4ff8 | 450 | struct ssc_device *ssc = ssc_p->ssc; |
6c742509 SG |
451 | struct atmel_pcm_dma_params *dma_params; |
452 | int dir, channels, bits; | |
453 | u32 tfmr, rfmr, tcmr, rcmr; | |
6c742509 | 454 | int ret; |
dfaf5356 | 455 | int fslen, fslen_ext; |
6c742509 SG |
456 | |
457 | /* | |
458 | * Currently, there is only one set of dma params for | |
459 | * each direction. If more are added, this code will | |
460 | * have to be changed to select the proper set. | |
461 | */ | |
462 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
463 | dir = 0; | |
464 | else | |
465 | dir = 1; | |
466 | ||
01f00d55 | 467 | dma_params = ssc_p->dma_params[dir]; |
6c742509 SG |
468 | |
469 | channels = params_channels(params); | |
470 | ||
471 | /* | |
472 | * Determine sample size in bits and the PDC increment. | |
473 | */ | |
474 | switch (params_format(params)) { | |
475 | case SNDRV_PCM_FORMAT_S8: | |
476 | bits = 8; | |
477 | dma_params->pdc_xfer_size = 1; | |
478 | break; | |
479 | case SNDRV_PCM_FORMAT_S16_LE: | |
480 | bits = 16; | |
481 | dma_params->pdc_xfer_size = 2; | |
482 | break; | |
483 | case SNDRV_PCM_FORMAT_S24_LE: | |
484 | bits = 24; | |
485 | dma_params->pdc_xfer_size = 4; | |
486 | break; | |
487 | case SNDRV_PCM_FORMAT_S32_LE: | |
488 | bits = 32; | |
489 | dma_params->pdc_xfer_size = 4; | |
490 | break; | |
491 | default: | |
492 | printk(KERN_WARNING "atmel_ssc_dai: unsupported PCM format"); | |
493 | return -EINVAL; | |
494 | } | |
495 | ||
6c742509 SG |
496 | /* |
497 | * Compute SSC register settings. | |
498 | */ | |
499 | switch (ssc_p->daifmt | |
500 | & (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_MASTER_MASK)) { | |
501 | ||
502 | case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS: | |
503 | /* | |
504 | * I2S format, SSC provides BCLK and LRC clocks. | |
505 | * | |
506 | * The SSC transmit and receive clocks are generated | |
507 | * from the MCK divider, and the BCLK signal | |
508 | * is output on the SSC TK line. | |
509 | */ | |
dfaf5356 BS |
510 | |
511 | if (bits > 16 && !ssc->pdata->has_fslen_ext) { | |
512 | dev_err(dai->dev, | |
513 | "sample size %d is too large for SSC device\n", | |
514 | bits); | |
515 | return -EINVAL; | |
516 | } | |
517 | ||
518 | fslen_ext = (bits - 1) / 16; | |
519 | fslen = (bits - 1) % 16; | |
520 | ||
6c742509 SG |
521 | rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period) |
522 | | SSC_BF(RCMR_STTDLY, START_DELAY) | |
523 | | SSC_BF(RCMR_START, SSC_START_FALLING_RF) | |
524 | | SSC_BF(RCMR_CKI, SSC_CKI_RISING) | |
525 | | SSC_BF(RCMR_CKO, SSC_CKO_NONE) | |
526 | | SSC_BF(RCMR_CKS, SSC_CKS_DIV); | |
527 | ||
dfaf5356 BS |
528 | rfmr = SSC_BF(RFMR_FSLEN_EXT, fslen_ext) |
529 | | SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) | |
6c742509 | 530 | | SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE) |
dfaf5356 | 531 | | SSC_BF(RFMR_FSLEN, fslen) |
6c742509 SG |
532 | | SSC_BF(RFMR_DATNB, (channels - 1)) |
533 | | SSC_BIT(RFMR_MSBF) | |
534 | | SSC_BF(RFMR_LOOP, 0) | |
535 | | SSC_BF(RFMR_DATLEN, (bits - 1)); | |
536 | ||
537 | tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period) | |
538 | | SSC_BF(TCMR_STTDLY, START_DELAY) | |
539 | | SSC_BF(TCMR_START, SSC_START_FALLING_RF) | |
540 | | SSC_BF(TCMR_CKI, SSC_CKI_FALLING) | |
541 | | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS) | |
542 | | SSC_BF(TCMR_CKS, SSC_CKS_DIV); | |
543 | ||
dfaf5356 BS |
544 | tfmr = SSC_BF(TFMR_FSLEN_EXT, fslen_ext) |
545 | | SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE) | |
6c742509 SG |
546 | | SSC_BF(TFMR_FSDEN, 0) |
547 | | SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE) | |
dfaf5356 | 548 | | SSC_BF(TFMR_FSLEN, fslen) |
6c742509 SG |
549 | | SSC_BF(TFMR_DATNB, (channels - 1)) |
550 | | SSC_BIT(TFMR_MSBF) | |
551 | | SSC_BF(TFMR_DATDEF, 0) | |
552 | | SSC_BF(TFMR_DATLEN, (bits - 1)); | |
553 | break; | |
554 | ||
555 | case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM: | |
67d1aed0 | 556 | /* I2S format, CODEC supplies BCLK and LRC clocks. */ |
6c742509 SG |
557 | rcmr = SSC_BF(RCMR_PERIOD, 0) |
558 | | SSC_BF(RCMR_STTDLY, START_DELAY) | |
a43bd7e1 | 559 | | SSC_BF(RCMR_START, SSC_START_FALLING_RF) |
6c742509 SG |
560 | | SSC_BF(RCMR_CKI, SSC_CKI_RISING) |
561 | | SSC_BF(RCMR_CKO, SSC_CKO_NONE) | |
048d4ff8 BS |
562 | | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ? |
563 | SSC_CKS_PIN : SSC_CKS_CLOCK); | |
6c742509 SG |
564 | |
565 | rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) | |
566 | | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE) | |
567 | | SSC_BF(RFMR_FSLEN, 0) | |
a43bd7e1 | 568 | | SSC_BF(RFMR_DATNB, (channels - 1)) |
6c742509 SG |
569 | | SSC_BIT(RFMR_MSBF) |
570 | | SSC_BF(RFMR_LOOP, 0) | |
571 | | SSC_BF(RFMR_DATLEN, (bits - 1)); | |
572 | ||
573 | tcmr = SSC_BF(TCMR_PERIOD, 0) | |
574 | | SSC_BF(TCMR_STTDLY, START_DELAY) | |
a43bd7e1 | 575 | | SSC_BF(TCMR_START, SSC_START_FALLING_RF) |
6c742509 SG |
576 | | SSC_BF(TCMR_CKI, SSC_CKI_FALLING) |
577 | | SSC_BF(TCMR_CKO, SSC_CKO_NONE) | |
048d4ff8 BS |
578 | | SSC_BF(TCMR_CKS, ssc->clk_from_rk_pin ? |
579 | SSC_CKS_CLOCK : SSC_CKS_PIN); | |
6c742509 SG |
580 | |
581 | tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE) | |
582 | | SSC_BF(TFMR_FSDEN, 0) | |
583 | | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE) | |
584 | | SSC_BF(TFMR_FSLEN, 0) | |
a43bd7e1 | 585 | | SSC_BF(TFMR_DATNB, (channels - 1)) |
6c742509 SG |
586 | | SSC_BIT(TFMR_MSBF) |
587 | | SSC_BF(TFMR_DATDEF, 0) | |
588 | | SSC_BF(TFMR_DATLEN, (bits - 1)); | |
589 | break; | |
590 | ||
eb527149 PR |
591 | case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFS: |
592 | /* I2S format, CODEC supplies BCLK, SSC supplies LRCLK. */ | |
593 | if (bits > 16 && !ssc->pdata->has_fslen_ext) { | |
594 | dev_err(dai->dev, | |
595 | "sample size %d is too large for SSC device\n", | |
596 | bits); | |
597 | return -EINVAL; | |
598 | } | |
599 | ||
600 | fslen_ext = (bits - 1) / 16; | |
601 | fslen = (bits - 1) % 16; | |
602 | ||
603 | rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period) | |
604 | | SSC_BF(RCMR_STTDLY, START_DELAY) | |
605 | | SSC_BF(RCMR_START, SSC_START_FALLING_RF) | |
606 | | SSC_BF(RCMR_CKI, SSC_CKI_RISING) | |
607 | | SSC_BF(RCMR_CKO, SSC_CKO_NONE) | |
608 | | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ? | |
609 | SSC_CKS_PIN : SSC_CKS_CLOCK); | |
610 | ||
611 | rfmr = SSC_BF(RFMR_FSLEN_EXT, fslen_ext) | |
612 | | SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) | |
613 | | SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE) | |
614 | | SSC_BF(RFMR_FSLEN, fslen) | |
615 | | SSC_BF(RFMR_DATNB, (channels - 1)) | |
616 | | SSC_BIT(RFMR_MSBF) | |
617 | | SSC_BF(RFMR_LOOP, 0) | |
618 | | SSC_BF(RFMR_DATLEN, (bits - 1)); | |
619 | ||
620 | tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period) | |
621 | | SSC_BF(TCMR_STTDLY, START_DELAY) | |
622 | | SSC_BF(TCMR_START, SSC_START_FALLING_RF) | |
623 | | SSC_BF(TCMR_CKI, SSC_CKI_FALLING) | |
624 | | SSC_BF(TCMR_CKO, SSC_CKO_NONE) | |
625 | | SSC_BF(TCMR_CKS, ssc->clk_from_rk_pin ? | |
626 | SSC_CKS_CLOCK : SSC_CKS_PIN); | |
627 | ||
628 | tfmr = SSC_BF(TFMR_FSLEN_EXT, fslen_ext) | |
629 | | SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_NEGATIVE) | |
630 | | SSC_BF(TFMR_FSDEN, 0) | |
631 | | SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE) | |
632 | | SSC_BF(TFMR_FSLEN, fslen) | |
633 | | SSC_BF(TFMR_DATNB, (channels - 1)) | |
6c742509 SG |
634 | | SSC_BIT(TFMR_MSBF) |
635 | | SSC_BF(TFMR_DATDEF, 0) | |
636 | | SSC_BF(TFMR_DATLEN, (bits - 1)); | |
637 | break; | |
638 | ||
639 | case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS: | |
640 | /* | |
641 | * DSP/PCM Mode A format, SSC provides BCLK and LRC clocks. | |
642 | * | |
643 | * The SSC transmit and receive clocks are generated from the | |
644 | * MCK divider, and the BCLK signal is output | |
645 | * on the SSC TK line. | |
646 | */ | |
647 | rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period) | |
648 | | SSC_BF(RCMR_STTDLY, 1) | |
649 | | SSC_BF(RCMR_START, SSC_START_RISING_RF) | |
20cf2603 | 650 | | SSC_BF(RCMR_CKI, SSC_CKI_FALLING) |
6c742509 SG |
651 | | SSC_BF(RCMR_CKO, SSC_CKO_NONE) |
652 | | SSC_BF(RCMR_CKS, SSC_CKS_DIV); | |
653 | ||
654 | rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) | |
655 | | SSC_BF(RFMR_FSOS, SSC_FSOS_POSITIVE) | |
656 | | SSC_BF(RFMR_FSLEN, 0) | |
657 | | SSC_BF(RFMR_DATNB, (channels - 1)) | |
658 | | SSC_BIT(RFMR_MSBF) | |
659 | | SSC_BF(RFMR_LOOP, 0) | |
660 | | SSC_BF(RFMR_DATLEN, (bits - 1)); | |
661 | ||
662 | tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period) | |
663 | | SSC_BF(TCMR_STTDLY, 1) | |
664 | | SSC_BF(TCMR_START, SSC_START_RISING_RF) | |
20cf2603 | 665 | | SSC_BF(TCMR_CKI, SSC_CKI_FALLING) |
6c742509 SG |
666 | | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS) |
667 | | SSC_BF(TCMR_CKS, SSC_CKS_DIV); | |
668 | ||
669 | tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE) | |
670 | | SSC_BF(TFMR_FSDEN, 0) | |
671 | | SSC_BF(TFMR_FSOS, SSC_FSOS_POSITIVE) | |
672 | | SSC_BF(TFMR_FSLEN, 0) | |
673 | | SSC_BF(TFMR_DATNB, (channels - 1)) | |
674 | | SSC_BIT(TFMR_MSBF) | |
675 | | SSC_BF(TFMR_DATDEF, 0) | |
676 | | SSC_BF(TFMR_DATLEN, (bits - 1)); | |
677 | break; | |
678 | ||
679 | case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM: | |
f6a75d95 ZP |
680 | /* |
681 | * DSP/PCM Mode A format, CODEC supplies BCLK and LRC clocks. | |
682 | * | |
f6a75d95 ZP |
683 | * Data is transferred on first BCLK after LRC pulse rising |
684 | * edge.If stereo, the right channel data is contiguous with | |
685 | * the left channel data. | |
686 | */ | |
687 | rcmr = SSC_BF(RCMR_PERIOD, 0) | |
688 | | SSC_BF(RCMR_STTDLY, START_DELAY) | |
689 | | SSC_BF(RCMR_START, SSC_START_RISING_RF) | |
20cf2603 | 690 | | SSC_BF(RCMR_CKI, SSC_CKI_FALLING) |
f6a75d95 | 691 | | SSC_BF(RCMR_CKO, SSC_CKO_NONE) |
048d4ff8 BS |
692 | | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ? |
693 | SSC_CKS_PIN : SSC_CKS_CLOCK); | |
f6a75d95 ZP |
694 | |
695 | rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) | |
696 | | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE) | |
697 | | SSC_BF(RFMR_FSLEN, 0) | |
698 | | SSC_BF(RFMR_DATNB, (channels - 1)) | |
699 | | SSC_BIT(RFMR_MSBF) | |
700 | | SSC_BF(RFMR_LOOP, 0) | |
701 | | SSC_BF(RFMR_DATLEN, (bits - 1)); | |
702 | ||
703 | tcmr = SSC_BF(TCMR_PERIOD, 0) | |
704 | | SSC_BF(TCMR_STTDLY, START_DELAY) | |
705 | | SSC_BF(TCMR_START, SSC_START_RISING_RF) | |
706 | | SSC_BF(TCMR_CKI, SSC_CKI_FALLING) | |
707 | | SSC_BF(TCMR_CKO, SSC_CKO_NONE) | |
048d4ff8 BS |
708 | | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ? |
709 | SSC_CKS_CLOCK : SSC_CKS_PIN); | |
f6a75d95 ZP |
710 | |
711 | tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE) | |
712 | | SSC_BF(TFMR_FSDEN, 0) | |
713 | | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE) | |
714 | | SSC_BF(TFMR_FSLEN, 0) | |
715 | | SSC_BF(TFMR_DATNB, (channels - 1)) | |
716 | | SSC_BIT(TFMR_MSBF) | |
717 | | SSC_BF(TFMR_DATDEF, 0) | |
718 | | SSC_BF(TFMR_DATLEN, (bits - 1)); | |
719 | break; | |
720 | ||
6c742509 SG |
721 | default: |
722 | printk(KERN_WARNING "atmel_ssc_dai: unsupported DAI format 0x%x\n", | |
723 | ssc_p->daifmt); | |
724 | return -EINVAL; | |
6c742509 SG |
725 | } |
726 | pr_debug("atmel_ssc_hw_params: " | |
727 | "RCMR=%08x RFMR=%08x TCMR=%08x TFMR=%08x\n", | |
728 | rcmr, rfmr, tcmr, tfmr); | |
729 | ||
730 | if (!ssc_p->initialized) { | |
3fd5b30c BS |
731 | if (!ssc_p->ssc->pdata->use_dma) { |
732 | ssc_writel(ssc_p->ssc->regs, PDC_RPR, 0); | |
733 | ssc_writel(ssc_p->ssc->regs, PDC_RCR, 0); | |
734 | ssc_writel(ssc_p->ssc->regs, PDC_RNPR, 0); | |
735 | ssc_writel(ssc_p->ssc->regs, PDC_RNCR, 0); | |
736 | ||
737 | ssc_writel(ssc_p->ssc->regs, PDC_TPR, 0); | |
738 | ssc_writel(ssc_p->ssc->regs, PDC_TCR, 0); | |
739 | ssc_writel(ssc_p->ssc->regs, PDC_TNPR, 0); | |
740 | ssc_writel(ssc_p->ssc->regs, PDC_TNCR, 0); | |
741 | } | |
6c742509 SG |
742 | |
743 | ret = request_irq(ssc_p->ssc->irq, atmel_ssc_interrupt, 0, | |
744 | ssc_p->name, ssc_p); | |
745 | if (ret < 0) { | |
746 | printk(KERN_WARNING | |
747 | "atmel_ssc_dai: request_irq failure\n"); | |
748 | pr_debug("Atmel_ssc_dai: Stoping clock\n"); | |
749 | clk_disable(ssc_p->ssc->clk); | |
750 | return ret; | |
751 | } | |
752 | ||
753 | ssc_p->initialized = 1; | |
754 | } | |
755 | ||
756 | /* set SSC clock mode register */ | |
757 | ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->cmr_div); | |
758 | ||
759 | /* set receive clock mode and format */ | |
760 | ssc_writel(ssc_p->ssc->regs, RCMR, rcmr); | |
761 | ssc_writel(ssc_p->ssc->regs, RFMR, rfmr); | |
762 | ||
763 | /* set transmit clock mode and format */ | |
764 | ssc_writel(ssc_p->ssc->regs, TCMR, tcmr); | |
765 | ssc_writel(ssc_p->ssc->regs, TFMR, tfmr); | |
766 | ||
767 | pr_debug("atmel_ssc_dai,hw_params: SSC initialized\n"); | |
768 | return 0; | |
769 | } | |
770 | ||
771 | ||
dee89c4d MB |
772 | static int atmel_ssc_prepare(struct snd_pcm_substream *substream, |
773 | struct snd_soc_dai *dai) | |
6c742509 | 774 | { |
f0fba2ad | 775 | struct atmel_ssc_info *ssc_p = &ssc_info[dai->id]; |
6c742509 SG |
776 | struct atmel_pcm_dma_params *dma_params; |
777 | int dir; | |
778 | ||
779 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
780 | dir = 0; | |
781 | else | |
782 | dir = 1; | |
783 | ||
784 | dma_params = ssc_p->dma_params[dir]; | |
785 | ||
a8f1f100 | 786 | ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable); |
e0111434 | 787 | ssc_writel(ssc_p->ssc->regs, IDR, dma_params->mask->ssc_error); |
6c742509 SG |
788 | |
789 | pr_debug("%s enabled SSC_SR=0x%08x\n", | |
790 | dir ? "receive" : "transmit", | |
791 | ssc_readl(ssc_p->ssc->regs, SR)); | |
792 | return 0; | |
793 | } | |
794 | ||
a8f1f100 BS |
795 | static int atmel_ssc_trigger(struct snd_pcm_substream *substream, |
796 | int cmd, struct snd_soc_dai *dai) | |
797 | { | |
798 | struct atmel_ssc_info *ssc_p = &ssc_info[dai->id]; | |
799 | struct atmel_pcm_dma_params *dma_params; | |
800 | int dir; | |
801 | ||
802 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
803 | dir = 0; | |
804 | else | |
805 | dir = 1; | |
806 | ||
807 | dma_params = ssc_p->dma_params[dir]; | |
808 | ||
809 | switch (cmd) { | |
810 | case SNDRV_PCM_TRIGGER_START: | |
811 | case SNDRV_PCM_TRIGGER_RESUME: | |
812 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
813 | ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_enable); | |
814 | break; | |
815 | default: | |
816 | ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable); | |
817 | break; | |
818 | } | |
819 | ||
820 | return 0; | |
821 | } | |
6c742509 SG |
822 | |
823 | #ifdef CONFIG_PM | |
dc7d7b83 | 824 | static int atmel_ssc_suspend(struct snd_soc_dai *cpu_dai) |
6c742509 SG |
825 | { |
826 | struct atmel_ssc_info *ssc_p; | |
827 | ||
828 | if (!cpu_dai->active) | |
829 | return 0; | |
830 | ||
831 | ssc_p = &ssc_info[cpu_dai->id]; | |
832 | ||
833 | /* Save the status register before disabling transmit and receive */ | |
834 | ssc_p->ssc_state.ssc_sr = ssc_readl(ssc_p->ssc->regs, SR); | |
835 | ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_TXDIS) | SSC_BIT(CR_RXDIS)); | |
836 | ||
837 | /* Save the current interrupt mask, then disable unmasked interrupts */ | |
838 | ssc_p->ssc_state.ssc_imr = ssc_readl(ssc_p->ssc->regs, IMR); | |
839 | ssc_writel(ssc_p->ssc->regs, IDR, ssc_p->ssc_state.ssc_imr); | |
840 | ||
841 | ssc_p->ssc_state.ssc_cmr = ssc_readl(ssc_p->ssc->regs, CMR); | |
842 | ssc_p->ssc_state.ssc_rcmr = ssc_readl(ssc_p->ssc->regs, RCMR); | |
843 | ssc_p->ssc_state.ssc_rfmr = ssc_readl(ssc_p->ssc->regs, RFMR); | |
844 | ssc_p->ssc_state.ssc_tcmr = ssc_readl(ssc_p->ssc->regs, TCMR); | |
845 | ssc_p->ssc_state.ssc_tfmr = ssc_readl(ssc_p->ssc->regs, TFMR); | |
846 | ||
847 | return 0; | |
848 | } | |
849 | ||
850 | ||
851 | ||
dc7d7b83 | 852 | static int atmel_ssc_resume(struct snd_soc_dai *cpu_dai) |
6c742509 SG |
853 | { |
854 | struct atmel_ssc_info *ssc_p; | |
855 | u32 cr; | |
856 | ||
857 | if (!cpu_dai->active) | |
858 | return 0; | |
859 | ||
860 | ssc_p = &ssc_info[cpu_dai->id]; | |
861 | ||
862 | /* restore SSC register settings */ | |
863 | ssc_writel(ssc_p->ssc->regs, TFMR, ssc_p->ssc_state.ssc_tfmr); | |
864 | ssc_writel(ssc_p->ssc->regs, TCMR, ssc_p->ssc_state.ssc_tcmr); | |
865 | ssc_writel(ssc_p->ssc->regs, RFMR, ssc_p->ssc_state.ssc_rfmr); | |
866 | ssc_writel(ssc_p->ssc->regs, RCMR, ssc_p->ssc_state.ssc_rcmr); | |
867 | ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->ssc_state.ssc_cmr); | |
868 | ||
869 | /* re-enable interrupts */ | |
870 | ssc_writel(ssc_p->ssc->regs, IER, ssc_p->ssc_state.ssc_imr); | |
871 | ||
25985edc | 872 | /* Re-enable receive and transmit as appropriate */ |
6c742509 SG |
873 | cr = 0; |
874 | cr |= | |
875 | (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_RXEN)) ? SSC_BIT(CR_RXEN) : 0; | |
876 | cr |= | |
877 | (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_TXEN)) ? SSC_BIT(CR_TXEN) : 0; | |
878 | ssc_writel(ssc_p->ssc->regs, CR, cr); | |
879 | ||
880 | return 0; | |
881 | } | |
882 | #else /* CONFIG_PM */ | |
883 | # define atmel_ssc_suspend NULL | |
884 | # define atmel_ssc_resume NULL | |
885 | #endif /* CONFIG_PM */ | |
886 | ||
6c742509 SG |
887 | #define ATMEL_SSC_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\ |
888 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) | |
889 | ||
85e7652d | 890 | static const struct snd_soc_dai_ops atmel_ssc_dai_ops = { |
6335d055 EM |
891 | .startup = atmel_ssc_startup, |
892 | .shutdown = atmel_ssc_shutdown, | |
893 | .prepare = atmel_ssc_prepare, | |
a8f1f100 | 894 | .trigger = atmel_ssc_trigger, |
6335d055 EM |
895 | .hw_params = atmel_ssc_hw_params, |
896 | .set_fmt = atmel_ssc_set_dai_fmt, | |
897 | .set_clkdiv = atmel_ssc_set_dai_clkdiv, | |
898 | }; | |
899 | ||
be681a82 | 900 | static struct snd_soc_dai_driver atmel_ssc_dai = { |
6c742509 SG |
901 | .suspend = atmel_ssc_suspend, |
902 | .resume = atmel_ssc_resume, | |
903 | .playback = { | |
904 | .channels_min = 1, | |
905 | .channels_max = 2, | |
b6d6c6e9 PR |
906 | .rates = SNDRV_PCM_RATE_CONTINUOUS, |
907 | .rate_min = 8000, | |
908 | .rate_max = 384000, | |
6c742509 SG |
909 | .formats = ATMEL_SSC_FORMATS,}, |
910 | .capture = { | |
911 | .channels_min = 1, | |
912 | .channels_max = 2, | |
b6d6c6e9 PR |
913 | .rates = SNDRV_PCM_RATE_CONTINUOUS, |
914 | .rate_min = 8000, | |
915 | .rate_max = 384000, | |
6c742509 | 916 | .formats = ATMEL_SSC_FORMATS,}, |
6335d055 | 917 | .ops = &atmel_ssc_dai_ops, |
6c742509 | 918 | }; |
6c742509 | 919 | |
a2c662c0 KM |
920 | static const struct snd_soc_component_driver atmel_ssc_component = { |
921 | .name = "atmel-ssc", | |
922 | }; | |
923 | ||
be681a82 | 924 | static int asoc_ssc_init(struct device *dev) |
f0fba2ad | 925 | { |
3951e4aa BS |
926 | struct platform_device *pdev = to_platform_device(dev); |
927 | struct ssc_device *ssc = platform_get_drvdata(pdev); | |
be681a82 BS |
928 | int ret; |
929 | ||
a2c662c0 KM |
930 | ret = snd_soc_register_component(dev, &atmel_ssc_component, |
931 | &atmel_ssc_dai, 1); | |
be681a82 BS |
932 | if (ret) { |
933 | dev_err(dev, "Could not register DAI: %d\n", ret); | |
934 | goto err; | |
935 | } | |
936 | ||
3951e4aa BS |
937 | if (ssc->pdata->use_dma) |
938 | ret = atmel_pcm_dma_platform_register(dev); | |
939 | else | |
940 | ret = atmel_pcm_pdc_platform_register(dev); | |
941 | ||
be681a82 BS |
942 | if (ret) { |
943 | dev_err(dev, "Could not register PCM: %d\n", ret); | |
944 | goto err_unregister_dai; | |
1d198f26 | 945 | } |
f0fba2ad | 946 | |
f0fba2ad | 947 | return 0; |
f0fba2ad | 948 | |
be681a82 | 949 | err_unregister_dai: |
a2c662c0 | 950 | snd_soc_unregister_component(dev); |
be681a82 BS |
951 | err: |
952 | return ret; | |
953 | } | |
f0fba2ad | 954 | |
be681a82 BS |
955 | static void asoc_ssc_exit(struct device *dev) |
956 | { | |
3951e4aa BS |
957 | struct platform_device *pdev = to_platform_device(dev); |
958 | struct ssc_device *ssc = platform_get_drvdata(pdev); | |
959 | ||
960 | if (ssc->pdata->use_dma) | |
961 | atmel_pcm_dma_platform_unregister(dev); | |
962 | else | |
963 | atmel_pcm_pdc_platform_unregister(dev); | |
964 | ||
a2c662c0 | 965 | snd_soc_unregister_component(dev); |
be681a82 | 966 | } |
f0fba2ad | 967 | |
abfa4eae MB |
968 | /** |
969 | * atmel_ssc_set_audio - Allocate the specified SSC for audio use. | |
970 | */ | |
971 | int atmel_ssc_set_audio(int ssc_id) | |
972 | { | |
973 | struct ssc_device *ssc; | |
abfa4eae MB |
974 | int ret; |
975 | ||
abfa4eae MB |
976 | /* If we can grab the SSC briefly to parent the DAI device off it */ |
977 | ssc = ssc_request(ssc_id); | |
be681a82 BS |
978 | if (IS_ERR(ssc)) { |
979 | pr_err("Unable to parent ASoC SSC DAI on SSC: %ld\n", | |
abfa4eae | 980 | PTR_ERR(ssc)); |
be681a82 BS |
981 | return PTR_ERR(ssc); |
982 | } else { | |
983 | ssc_info[ssc_id].ssc = ssc; | |
840d8e5e | 984 | } |
abfa4eae | 985 | |
be681a82 | 986 | ret = asoc_ssc_init(&ssc->pdev->dev); |
abfa4eae MB |
987 | |
988 | return ret; | |
989 | } | |
990 | EXPORT_SYMBOL_GPL(atmel_ssc_set_audio); | |
991 | ||
be681a82 BS |
992 | void atmel_ssc_put_audio(int ssc_id) |
993 | { | |
994 | struct ssc_device *ssc = ssc_info[ssc_id].ssc; | |
995 | ||
be681a82 | 996 | asoc_ssc_exit(&ssc->pdev->dev); |
69706028 | 997 | ssc_free(ssc); |
be681a82 BS |
998 | } |
999 | EXPORT_SYMBOL_GPL(atmel_ssc_put_audio); | |
3f4b783c | 1000 | |
6c742509 SG |
1001 | /* Module information */ |
1002 | MODULE_AUTHOR("Sedji Gaouaou, sedji.gaouaou@atmel.com, www.atmel.com"); | |
1003 | MODULE_DESCRIPTION("ATMEL SSC ASoC Interface"); | |
1004 | MODULE_LICENSE("GPL"); |