projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
USB: xhci: don't start a halted endpoint before its new dequeue is set
[deliverable/linux.git] / sound / soc / atmel / atmel_ssc_dai.c
CommitLineData
6c742509
SG		 1/*
2 * atmel_ssc_dai.c -- ALSA SoC ATMEL SSC Audio Layer Platform driver
3 *
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2008 Atmel
6 *
7 * Author: Sedji Gaouaou <sedji.gaouaou@atmel.com>
8 * ATMEL CORP.
9 *
10 * Based on at91-ssc.c by
11 * Frank Mandarino <fmandarino@endrelia.com>
12 * Based on pxa2xx Platform drivers by
64ca0404 13 * Liam Girdwood <lrg@slimlogic.co.uk>
6c742509
SG		 14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 */
29
30#include <linux/init.h>
31#include <linux/module.h>
32#include <linux/interrupt.h>
33#include <linux/device.h>
34#include <linux/delay.h>
35#include <linux/clk.h>
36#include <linux/atmel_pdc.h>
37
38#include <linux/atmel-ssc.h>
39#include <sound/core.h>
40#include <sound/pcm.h>
41#include <sound/pcm_params.h>
42#include <sound/initval.h>
43#include <sound/soc.h>
44
6c742509
SG		 45#include "atmel-pcm.h"
46#include "atmel_ssc_dai.h"
47
48
6c742509 49#define NUM_SSC_DEVICES 3
6c742509
SG		 50
51/*
52 * SSC PDC registers required by the PCM DMA engine.
53 */
54static struct atmel_pdc_regs pdc_tx_reg = {
55 .xpr = ATMEL_PDC_TPR,
56 .xcr = ATMEL_PDC_TCR,
57 .xnpr = ATMEL_PDC_TNPR,
58 .xncr = ATMEL_PDC_TNCR,
59};
60
61static struct atmel_pdc_regs pdc_rx_reg = {
62 .xpr = ATMEL_PDC_RPR,
63 .xcr = ATMEL_PDC_RCR,
64 .xnpr = ATMEL_PDC_RNPR,
65 .xncr = ATMEL_PDC_RNCR,
66};
67
68/*
69 * SSC & PDC status bits for transmit and receive.
70 */
71static struct atmel_ssc_mask ssc_tx_mask = {
72 .ssc_enable = SSC_BIT(CR_TXEN),
73 .ssc_disable = SSC_BIT(CR_TXDIS),
74 .ssc_endx = SSC_BIT(SR_ENDTX),
75 .ssc_endbuf = SSC_BIT(SR_TXBUFE),
f1b0dd8b 76 .ssc_error = SSC_BIT(SR_OVRUN),
6c742509
SG		 77 .pdc_enable = ATMEL_PDC_TXTEN,
78 .pdc_disable = ATMEL_PDC_TXTDIS,
79};
80
81static struct atmel_ssc_mask ssc_rx_mask = {
82 .ssc_enable = SSC_BIT(CR_RXEN),
83 .ssc_disable = SSC_BIT(CR_RXDIS),
84 .ssc_endx = SSC_BIT(SR_ENDRX),
85 .ssc_endbuf = SSC_BIT(SR_RXBUFF),
f1b0dd8b 86 .ssc_error = SSC_BIT(SR_OVRUN),
6c742509
SG		 87 .pdc_enable = ATMEL_PDC_RXTEN,
88 .pdc_disable = ATMEL_PDC_RXTDIS,
89};
90
91
92/*
93 * DMA parameters.
94 */
95static struct atmel_pcm_dma_params ssc_dma_params[NUM_SSC_DEVICES][2] = {
96 {{
97 .name = "SSC0 PCM out",
98 .pdc = &pdc_tx_reg,
99 .mask = &ssc_tx_mask,
100 },
101 {
102 .name = "SSC0 PCM in",
103 .pdc = &pdc_rx_reg,
104 .mask = &ssc_rx_mask,
105 } },
6c742509
SG		 106 {{
107 .name = "SSC1 PCM out",
108 .pdc = &pdc_tx_reg,
109 .mask = &ssc_tx_mask,
110 },
111 {
112 .name = "SSC1 PCM in",
113 .pdc = &pdc_rx_reg,
114 .mask = &ssc_rx_mask,
115 } },
116 {{
117 .name = "SSC2 PCM out",
118 .pdc = &pdc_tx_reg,
119 .mask = &ssc_tx_mask,
120 },
121 {
122 .name = "SSC2 PCM in",
123 .pdc = &pdc_rx_reg,
124 .mask = &ssc_rx_mask,
125 } },
6c742509
SG		 126};
127
128
129static struct atmel_ssc_info ssc_info[NUM_SSC_DEVICES] = {
130 {
131 .name = "ssc0",
132 .lock = __SPIN_LOCK_UNLOCKED(ssc_info[0].lock),
133 .dir_mask = SSC_DIR_MASK_UNUSED,
134 .initialized = 0,
135 },
6c742509
SG		 136 {
137 .name = "ssc1",
138 .lock = __SPIN_LOCK_UNLOCKED(ssc_info[1].lock),
139 .dir_mask = SSC_DIR_MASK_UNUSED,
140 .initialized = 0,
141 },
142 {
143 .name = "ssc2",
144 .lock = __SPIN_LOCK_UNLOCKED(ssc_info[2].lock),
145 .dir_mask = SSC_DIR_MASK_UNUSED,
146 .initialized = 0,
147 },
6c742509
SG		 148};
149
150
151/*
152 * SSC interrupt handler. Passes PDC interrupts to the DMA
153 * interrupt handler in the PCM driver.
154 */
155static irqreturn_t atmel_ssc_interrupt(int irq, void *dev_id)
156{
157 struct atmel_ssc_info *ssc_p = dev_id;
158 struct atmel_pcm_dma_params *dma_params;
159 u32 ssc_sr;
160 u32 ssc_substream_mask;
161 int i;
162
163 ssc_sr = (unsigned long)ssc_readl(ssc_p->ssc->regs, SR)
164 & (unsigned long)ssc_readl(ssc_p->ssc->regs, IMR);
165
166 /*
167 * Loop through the substreams attached to this SSC. If
168 * a DMA-related interrupt occurred on that substream, call
169 * the DMA interrupt handler function, if one has been
170 * registered in the dma_params structure by the PCM driver.
171 */
172 for (i = 0; i < ARRAY_SIZE(ssc_p->dma_params); i++) {
173 dma_params = ssc_p->dma_params[i];
174
175 if ((dma_params != NULL) &&
176 (dma_params->dma_intr_handler != NULL)) {
177 ssc_substream_mask = (dma_params->mask->ssc_endx |
178 dma_params->mask->ssc_endbuf);
179 if (ssc_sr & ssc_substream_mask) {
180 dma_params->dma_intr_handler(ssc_sr,
181 dma_params->
182 substream);
183 }
184 }
185 }
186
187 return IRQ_HANDLED;
188}
189
190
191/*-------------------------------------------------------------------------*\
192 * DAI functions
193\*-------------------------------------------------------------------------*/
194/*
195 * Startup. Only that one substream allowed in each direction.
196 */
dee89c4d
MB		 197static int atmel_ssc_startup(struct snd_pcm_substream *substream,
198 struct snd_soc_dai *dai)
6c742509 199{
f0fba2ad 200 struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
01f00d55
BS		 201 struct atmel_pcm_dma_params *dma_params;
202 int dir, dir_mask;
6c742509
SG		 203
204 pr_debug("atmel_ssc_startup: SSC_SR=0x%u\n",
205 ssc_readl(ssc_p->ssc->regs, SR));
206
01f00d55
BS		 207 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
208 dir = 0;
6c742509 209 dir_mask = SSC_DIR_MASK_PLAYBACK;
01f00d55
BS		 210 } else {
211 dir = 1;
6c742509 212 dir_mask = SSC_DIR_MASK_CAPTURE;
01f00d55
BS		 213 }
214
215 dma_params = &ssc_dma_params[dai->id][dir];
216 dma_params->ssc = ssc_p->ssc;
217 dma_params->substream = substream;
218
219 ssc_p->dma_params[dir] = dma_params;
220
221 snd_soc_dai_set_dma_data(dai, substream, dma_params);
6c742509
SG		 222
223 spin_lock_irq(&ssc_p->lock);
224 if (ssc_p->dir_mask & dir_mask) {
225 spin_unlock_irq(&ssc_p->lock);
226 return -EBUSY;
227 }
228 ssc_p->dir_mask |= dir_mask;
229 spin_unlock_irq(&ssc_p->lock);
230
231 return 0;
232}
233
234/*
235 * Shutdown. Clear DMA parameters and shutdown the SSC if there
236 * are no other substreams open.
237 */
dee89c4d
MB		 238static void atmel_ssc_shutdown(struct snd_pcm_substream *substream,
239 struct snd_soc_dai *dai)
6c742509 240{
f0fba2ad 241 struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
6c742509
SG		 242 struct atmel_pcm_dma_params *dma_params;
243 int dir, dir_mask;
244
245 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
246 dir = 0;
247 else
248 dir = 1;
249
250 dma_params = ssc_p->dma_params[dir];
251
252 if (dma_params != NULL) {
253 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable);
254 pr_debug("atmel_ssc_shutdown: %s disabled SSC_SR=0x%08x\n",
255 (dir ? "receive" : "transmit"),
256 ssc_readl(ssc_p->ssc->regs, SR));
257
258 dma_params->ssc = NULL;
259 dma_params->substream = NULL;
260 ssc_p->dma_params[dir] = NULL;
261 }
262
263 dir_mask = 1 << dir;
264
265 spin_lock_irq(&ssc_p->lock);
266 ssc_p->dir_mask &= ~dir_mask;
267 if (!ssc_p->dir_mask) {
268 if (ssc_p->initialized) {
269 /* Shutdown the SSC clock. */
270 pr_debug("atmel_ssc_dau: Stopping clock\n");
271 clk_disable(ssc_p->ssc->clk);
272
273 free_irq(ssc_p->ssc->irq, ssc_p);
274 ssc_p->initialized = 0;
275 }
276
277 /* Reset the SSC */
278 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
279 /* Clear the SSC dividers */
280 ssc_p->cmr_div = ssc_p->tcmr_period = ssc_p->rcmr_period = 0;
281 }
282 spin_unlock_irq(&ssc_p->lock);
283}
284
285
286/*
287 * Record the DAI format for use in hw_params().
288 */
289static int atmel_ssc_set_dai_fmt(struct snd_soc_dai *cpu_dai,
290 unsigned int fmt)
291{
292 struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
293
294 ssc_p->daifmt = fmt;
295 return 0;
296}
297
298/*
299 * Record SSC clock dividers for use in hw_params().
300 */
301static int atmel_ssc_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
302 int div_id, int div)
303{
304 struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
305
306 switch (div_id) {
307 case ATMEL_SSC_CMR_DIV:
308 /*
309 * The same master clock divider is used for both
310 * transmit and receive, so if a value has already
311 * been set, it must match this value.
312 */
313 if (ssc_p->cmr_div == 0)
314 ssc_p->cmr_div = div;
315 else
316 if (div != ssc_p->cmr_div)
317 return -EBUSY;
318 break;
319
320 case ATMEL_SSC_TCMR_PERIOD:
321 ssc_p->tcmr_period = div;
322 break;
323
324 case ATMEL_SSC_RCMR_PERIOD:
325 ssc_p->rcmr_period = div;
326 break;
327
328 default:
329 return -EINVAL;
330 }
331
332 return 0;
333}
334
335/*
336 * Configure the SSC.
337 */
338static int atmel_ssc_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 339 struct snd_pcm_hw_params *params,
340 struct snd_soc_dai *dai)
6c742509 341{
f0fba2ad 342 int id = dai->id;
6c742509 343 struct atmel_ssc_info *ssc_p = &ssc_info[id];
048d4ff8 344 struct ssc_device *ssc = ssc_p->ssc;
6c742509
SG		 345 struct atmel_pcm_dma_params *dma_params;
346 int dir, channels, bits;
347 u32 tfmr, rfmr, tcmr, rcmr;
348 int start_event;
349 int ret;
dfaf5356 350 int fslen, fslen_ext;
6c742509
SG		 351
352 /*
353 * Currently, there is only one set of dma params for
354 * each direction. If more are added, this code will
355 * have to be changed to select the proper set.
356 */
357 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
358 dir = 0;
359 else
360 dir = 1;
361
01f00d55 362 dma_params = ssc_p->dma_params[dir];
6c742509
SG		 363
364 channels = params_channels(params);
365
366 /*
367 * Determine sample size in bits and the PDC increment.
368 */
369 switch (params_format(params)) {
370 case SNDRV_PCM_FORMAT_S8:
371 bits = 8;
372 dma_params->pdc_xfer_size = 1;
373 break;
374 case SNDRV_PCM_FORMAT_S16_LE:
375 bits = 16;
376 dma_params->pdc_xfer_size = 2;
377 break;
378 case SNDRV_PCM_FORMAT_S24_LE:
379 bits = 24;
380 dma_params->pdc_xfer_size = 4;
381 break;
382 case SNDRV_PCM_FORMAT_S32_LE:
383 bits = 32;
384 dma_params->pdc_xfer_size = 4;
385 break;
386 default:
387 printk(KERN_WARNING "atmel_ssc_dai: unsupported PCM format");
388 return -EINVAL;
389 }
390
6c742509
SG		 391 /*
392 * Compute SSC register settings.
393 */
394 switch (ssc_p->daifmt
395 & (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_MASTER_MASK)) {
396
397 case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS:
398 /*
399 * I2S format, SSC provides BCLK and LRC clocks.
400 *
401 * The SSC transmit and receive clocks are generated
402 * from the MCK divider, and the BCLK signal
403 * is output on the SSC TK line.
404 */
dfaf5356
BS		 405
406 if (bits > 16 && !ssc->pdata->has_fslen_ext) {
407 dev_err(dai->dev,
408 "sample size %d is too large for SSC device\n",
409 bits);
410 return -EINVAL;
411 }
412
413 fslen_ext = (bits - 1) / 16;
414 fslen = (bits - 1) % 16;
415
6c742509
SG		 416 rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
417 | SSC_BF(RCMR_STTDLY, START_DELAY)
418 | SSC_BF(RCMR_START, SSC_START_FALLING_RF)
419 | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
420 | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
421 | SSC_BF(RCMR_CKS, SSC_CKS_DIV);
422
dfaf5356
BS		 423 rfmr = SSC_BF(RFMR_FSLEN_EXT, fslen_ext)
424 | SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
6c742509 425 | SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE)
dfaf5356 426 | SSC_BF(RFMR_FSLEN, fslen)
6c742509
SG		 427 | SSC_BF(RFMR_DATNB, (channels - 1))
428 | SSC_BIT(RFMR_MSBF)
429 | SSC_BF(RFMR_LOOP, 0)
430 | SSC_BF(RFMR_DATLEN, (bits - 1));
431
432 tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
433 | SSC_BF(TCMR_STTDLY, START_DELAY)
434 | SSC_BF(TCMR_START, SSC_START_FALLING_RF)
435 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
436 | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS)
437 | SSC_BF(TCMR_CKS, SSC_CKS_DIV);
438
dfaf5356
BS		 439 tfmr = SSC_BF(TFMR_FSLEN_EXT, fslen_ext)
440 | SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
6c742509
SG		 441 | SSC_BF(TFMR_FSDEN, 0)
442 | SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE)
dfaf5356 443 | SSC_BF(TFMR_FSLEN, fslen)
6c742509
SG		 444 | SSC_BF(TFMR_DATNB, (channels - 1))
445 | SSC_BIT(TFMR_MSBF)
446 | SSC_BF(TFMR_DATDEF, 0)
447 | SSC_BF(TFMR_DATLEN, (bits - 1));
448 break;
449
450 case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM:
451 /*
452 * I2S format, CODEC supplies BCLK and LRC clocks.
453 *
454 * The SSC transmit clock is obtained from the BCLK signal on
455 * on the TK line, and the SSC receive clock is
456 * generated from the transmit clock.
457 *
458 * For single channel data, one sample is transferred
459 * on the falling edge of the LRC clock.
460 * For two channel data, one sample is
461 * transferred on both edges of the LRC clock.
462 */
463 start_event = ((channels == 1)
464 ? SSC_START_FALLING_RF
465 : SSC_START_EDGE_RF);
466
467 rcmr = SSC_BF(RCMR_PERIOD, 0)
468 | SSC_BF(RCMR_STTDLY, START_DELAY)
469 | SSC_BF(RCMR_START, start_event)
470 | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
471 | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
048d4ff8
BS		 472 | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
473 SSC_CKS_PIN : SSC_CKS_CLOCK);
6c742509
SG		 474
475 rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
476 | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE)
477 | SSC_BF(RFMR_FSLEN, 0)
478 | SSC_BF(RFMR_DATNB, 0)
479 | SSC_BIT(RFMR_MSBF)
480 | SSC_BF(RFMR_LOOP, 0)
481 | SSC_BF(RFMR_DATLEN, (bits - 1));
482
483 tcmr = SSC_BF(TCMR_PERIOD, 0)
484 | SSC_BF(TCMR_STTDLY, START_DELAY)
485 | SSC_BF(TCMR_START, start_event)
486 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
487 | SSC_BF(TCMR_CKO, SSC_CKO_NONE)
048d4ff8
BS		 488 | SSC_BF(TCMR_CKS, ssc->clk_from_rk_pin ?
489 SSC_CKS_CLOCK : SSC_CKS_PIN);
6c742509
SG		 490
491 tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
492 | SSC_BF(TFMR_FSDEN, 0)
493 | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE)
494 | SSC_BF(TFMR_FSLEN, 0)
495 | SSC_BF(TFMR_DATNB, 0)
496 | SSC_BIT(TFMR_MSBF)
497 | SSC_BF(TFMR_DATDEF, 0)
498 | SSC_BF(TFMR_DATLEN, (bits - 1));
499 break;
500
501 case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS:
502 /*
503 * DSP/PCM Mode A format, SSC provides BCLK and LRC clocks.
504 *
505 * The SSC transmit and receive clocks are generated from the
506 * MCK divider, and the BCLK signal is output
507 * on the SSC TK line.
508 */
509 rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
510 | SSC_BF(RCMR_STTDLY, 1)
511 | SSC_BF(RCMR_START, SSC_START_RISING_RF)
512 | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
513 | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
514 | SSC_BF(RCMR_CKS, SSC_CKS_DIV);
515
516 rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
517 | SSC_BF(RFMR_FSOS, SSC_FSOS_POSITIVE)
518 | SSC_BF(RFMR_FSLEN, 0)
519 | SSC_BF(RFMR_DATNB, (channels - 1))
520 | SSC_BIT(RFMR_MSBF)
521 | SSC_BF(RFMR_LOOP, 0)
522 | SSC_BF(RFMR_DATLEN, (bits - 1));
523
524 tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
525 | SSC_BF(TCMR_STTDLY, 1)
526 | SSC_BF(TCMR_START, SSC_START_RISING_RF)
527 | SSC_BF(TCMR_CKI, SSC_CKI_RISING)
528 | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS)
529 | SSC_BF(TCMR_CKS, SSC_CKS_DIV);
530
531 tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
532 | SSC_BF(TFMR_FSDEN, 0)
533 | SSC_BF(TFMR_FSOS, SSC_FSOS_POSITIVE)
534 | SSC_BF(TFMR_FSLEN, 0)
535 | SSC_BF(TFMR_DATNB, (channels - 1))
536 | SSC_BIT(TFMR_MSBF)
537 | SSC_BF(TFMR_DATDEF, 0)
538 | SSC_BF(TFMR_DATLEN, (bits - 1));
539 break;
540
541 case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM:
f6a75d95
ZP		 542 /*
543 * DSP/PCM Mode A format, CODEC supplies BCLK and LRC clocks.
544 *
545 * The SSC transmit clock is obtained from the BCLK signal on
546 * on the TK line, and the SSC receive clock is
547 * generated from the transmit clock.
548 *
549 * Data is transferred on first BCLK after LRC pulse rising
550 * edge.If stereo, the right channel data is contiguous with
551 * the left channel data.
552 */
553 rcmr = SSC_BF(RCMR_PERIOD, 0)
554 | SSC_BF(RCMR_STTDLY, START_DELAY)
555 | SSC_BF(RCMR_START, SSC_START_RISING_RF)
556 | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
557 | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
048d4ff8
BS		 558 | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
559 SSC_CKS_PIN : SSC_CKS_CLOCK);
f6a75d95
ZP		 560
561 rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
562 | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE)
563 | SSC_BF(RFMR_FSLEN, 0)
564 | SSC_BF(RFMR_DATNB, (channels - 1))
565 | SSC_BIT(RFMR_MSBF)
566 | SSC_BF(RFMR_LOOP, 0)
567 | SSC_BF(RFMR_DATLEN, (bits - 1));
568
569 tcmr = SSC_BF(TCMR_PERIOD, 0)
570 | SSC_BF(TCMR_STTDLY, START_DELAY)
571 | SSC_BF(TCMR_START, SSC_START_RISING_RF)
572 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
573 | SSC_BF(TCMR_CKO, SSC_CKO_NONE)
048d4ff8
BS		 574 | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
575 SSC_CKS_CLOCK : SSC_CKS_PIN);
f6a75d95
ZP		 576
577 tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
578 | SSC_BF(TFMR_FSDEN, 0)
579 | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE)
580 | SSC_BF(TFMR_FSLEN, 0)
581 | SSC_BF(TFMR_DATNB, (channels - 1))
582 | SSC_BIT(TFMR_MSBF)
583 | SSC_BF(TFMR_DATDEF, 0)
584 | SSC_BF(TFMR_DATLEN, (bits - 1));
585 break;
586
6c742509
SG		 587 default:
588 printk(KERN_WARNING "atmel_ssc_dai: unsupported DAI format 0x%x\n",
589 ssc_p->daifmt);
590 return -EINVAL;
6c742509
SG		 591 }
592 pr_debug("atmel_ssc_hw_params: "
593 "RCMR=%08x RFMR=%08x TCMR=%08x TFMR=%08x\n",
594 rcmr, rfmr, tcmr, tfmr);
595
596 if (!ssc_p->initialized) {
597
598 /* Enable PMC peripheral clock for this SSC */
599 pr_debug("atmel_ssc_dai: Starting clock\n");
600 clk_enable(ssc_p->ssc->clk);
601
602 /* Reset the SSC and its PDC registers */
603 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
604
605 ssc_writel(ssc_p->ssc->regs, PDC_RPR, 0);
606 ssc_writel(ssc_p->ssc->regs, PDC_RCR, 0);
607 ssc_writel(ssc_p->ssc->regs, PDC_RNPR, 0);
608 ssc_writel(ssc_p->ssc->regs, PDC_RNCR, 0);
609
610 ssc_writel(ssc_p->ssc->regs, PDC_TPR, 0);
611 ssc_writel(ssc_p->ssc->regs, PDC_TCR, 0);
612 ssc_writel(ssc_p->ssc->regs, PDC_TNPR, 0);
613 ssc_writel(ssc_p->ssc->regs, PDC_TNCR, 0);
614
615 ret = request_irq(ssc_p->ssc->irq, atmel_ssc_interrupt, 0,
616 ssc_p->name, ssc_p);
617 if (ret < 0) {
618 printk(KERN_WARNING
619 "atmel_ssc_dai: request_irq failure\n");
620 pr_debug("Atmel_ssc_dai: Stoping clock\n");
621 clk_disable(ssc_p->ssc->clk);
622 return ret;
623 }
624
625 ssc_p->initialized = 1;
626 }
627
628 /* set SSC clock mode register */
629 ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->cmr_div);
630
631 /* set receive clock mode and format */
632 ssc_writel(ssc_p->ssc->regs, RCMR, rcmr);
633 ssc_writel(ssc_p->ssc->regs, RFMR, rfmr);
634
635 /* set transmit clock mode and format */
636 ssc_writel(ssc_p->ssc->regs, TCMR, tcmr);
637 ssc_writel(ssc_p->ssc->regs, TFMR, tfmr);
638
639 pr_debug("atmel_ssc_dai,hw_params: SSC initialized\n");
640 return 0;
641}
642
643
dee89c4d
MB		 644static int atmel_ssc_prepare(struct snd_pcm_substream *substream,
645 struct snd_soc_dai *dai)
6c742509 646{
f0fba2ad 647 struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
6c742509
SG		 648 struct atmel_pcm_dma_params *dma_params;
649 int dir;
650
651 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
652 dir = 0;
653 else
654 dir = 1;
655
656 dma_params = ssc_p->dma_params[dir];
657
a8f1f100 658 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable);
e0111434 659 ssc_writel(ssc_p->ssc->regs, IDR, dma_params->mask->ssc_error);
6c742509
SG		 660
661 pr_debug("%s enabled SSC_SR=0x%08x\n",
662 dir ? "receive" : "transmit",
663 ssc_readl(ssc_p->ssc->regs, SR));
664 return 0;
665}
666
a8f1f100
BS		 667static int atmel_ssc_trigger(struct snd_pcm_substream *substream,
668 int cmd, struct snd_soc_dai *dai)
669{
670 struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
671 struct atmel_pcm_dma_params *dma_params;
672 int dir;
673
674 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
675 dir = 0;
676 else
677 dir = 1;
678
679 dma_params = ssc_p->dma_params[dir];
680
681 switch (cmd) {
682 case SNDRV_PCM_TRIGGER_START:
683 case SNDRV_PCM_TRIGGER_RESUME:
684 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
685 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_enable);
686 break;
687 default:
688 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable);
689 break;
690 }
691
692 return 0;
693}
6c742509
SG		 694
695#ifdef CONFIG_PM
dc7d7b83 696static int atmel_ssc_suspend(struct snd_soc_dai *cpu_dai)
6c742509
SG		 697{
698 struct atmel_ssc_info *ssc_p;
699
700 if (!cpu_dai->active)
701 return 0;
702
703 ssc_p = &ssc_info[cpu_dai->id];
704
705 /* Save the status register before disabling transmit and receive */
706 ssc_p->ssc_state.ssc_sr = ssc_readl(ssc_p->ssc->regs, SR);
707 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_TXDIS) | SSC_BIT(CR_RXDIS));
708
709 /* Save the current interrupt mask, then disable unmasked interrupts */
710 ssc_p->ssc_state.ssc_imr = ssc_readl(ssc_p->ssc->regs, IMR);
711 ssc_writel(ssc_p->ssc->regs, IDR, ssc_p->ssc_state.ssc_imr);
712
713 ssc_p->ssc_state.ssc_cmr = ssc_readl(ssc_p->ssc->regs, CMR);
714 ssc_p->ssc_state.ssc_rcmr = ssc_readl(ssc_p->ssc->regs, RCMR);
715 ssc_p->ssc_state.ssc_rfmr = ssc_readl(ssc_p->ssc->regs, RFMR);
716 ssc_p->ssc_state.ssc_tcmr = ssc_readl(ssc_p->ssc->regs, TCMR);
717 ssc_p->ssc_state.ssc_tfmr = ssc_readl(ssc_p->ssc->regs, TFMR);
718
719 return 0;
720}
721
722
723
dc7d7b83 724static int atmel_ssc_resume(struct snd_soc_dai *cpu_dai)
6c742509
SG		 725{
726 struct atmel_ssc_info *ssc_p;
727 u32 cr;
728
729 if (!cpu_dai->active)
730 return 0;
731
732 ssc_p = &ssc_info[cpu_dai->id];
733
734 /* restore SSC register settings */
735 ssc_writel(ssc_p->ssc->regs, TFMR, ssc_p->ssc_state.ssc_tfmr);
736 ssc_writel(ssc_p->ssc->regs, TCMR, ssc_p->ssc_state.ssc_tcmr);
737 ssc_writel(ssc_p->ssc->regs, RFMR, ssc_p->ssc_state.ssc_rfmr);
738 ssc_writel(ssc_p->ssc->regs, RCMR, ssc_p->ssc_state.ssc_rcmr);
739 ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->ssc_state.ssc_cmr);
740
741 /* re-enable interrupts */
742 ssc_writel(ssc_p->ssc->regs, IER, ssc_p->ssc_state.ssc_imr);
743
25985edc 744 /* Re-enable receive and transmit as appropriate */
6c742509
SG		 745 cr = 0;
746 cr |=
747 (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_RXEN)) ? SSC_BIT(CR_RXEN) : 0;
748 cr |=
749 (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_TXEN)) ? SSC_BIT(CR_TXEN) : 0;
750 ssc_writel(ssc_p->ssc->regs, CR, cr);
751
752 return 0;
753}
754#else /* CONFIG_PM */
755# define atmel_ssc_suspend NULL
756# define atmel_ssc_resume NULL
757#endif /* CONFIG_PM */
758
6c742509
SG		 759#define ATMEL_SSC_RATES (SNDRV_PCM_RATE_8000_96000)
760
761#define ATMEL_SSC_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
762 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
763
85e7652d 764static const struct snd_soc_dai_ops atmel_ssc_dai_ops = {
6335d055
EM		 765 .startup = atmel_ssc_startup,
766 .shutdown = atmel_ssc_shutdown,
767 .prepare = atmel_ssc_prepare,
a8f1f100 768 .trigger = atmel_ssc_trigger,
6335d055
EM		 769 .hw_params = atmel_ssc_hw_params,
770 .set_fmt = atmel_ssc_set_dai_fmt,
771 .set_clkdiv = atmel_ssc_set_dai_clkdiv,
772};
773
be681a82 774static struct snd_soc_dai_driver atmel_ssc_dai = {
6c742509
SG		 775 .suspend = atmel_ssc_suspend,
776 .resume = atmel_ssc_resume,
777 .playback = {
778 .channels_min = 1,
779 .channels_max = 2,
780 .rates = ATMEL_SSC_RATES,
781 .formats = ATMEL_SSC_FORMATS,},
782 .capture = {
783 .channels_min = 1,
784 .channels_max = 2,
785 .rates = ATMEL_SSC_RATES,
786 .formats = ATMEL_SSC_FORMATS,},
6335d055 787 .ops = &atmel_ssc_dai_ops,
6c742509 788};
6c742509 789
a2c662c0
KM		 790static const struct snd_soc_component_driver atmel_ssc_component = {
791 .name = "atmel-ssc",
792};
793
be681a82 794static int asoc_ssc_init(struct device *dev)
f0fba2ad 795{
3951e4aa
BS		 796 struct platform_device *pdev = to_platform_device(dev);
797 struct ssc_device *ssc = platform_get_drvdata(pdev);
be681a82
BS		 798 int ret;
799
a2c662c0
KM		 800 ret = snd_soc_register_component(dev, &atmel_ssc_component,
801 &atmel_ssc_dai, 1);
be681a82
BS		 802 if (ret) {
803 dev_err(dev, "Could not register DAI: %d\n", ret);
804 goto err;
805 }
806
3951e4aa
BS		 807 if (ssc->pdata->use_dma)
808 ret = atmel_pcm_dma_platform_register(dev);
809 else
810 ret = atmel_pcm_pdc_platform_register(dev);
811
be681a82
BS		 812 if (ret) {
813 dev_err(dev, "Could not register PCM: %d\n", ret);
814 goto err_unregister_dai;
1d198f26 815 }
f0fba2ad 816
f0fba2ad 817 return 0;
f0fba2ad 818
be681a82 819err_unregister_dai:
a2c662c0 820 snd_soc_unregister_component(dev);
be681a82
BS		 821err:
822 return ret;
823}
f0fba2ad 824
be681a82
BS		 825static void asoc_ssc_exit(struct device *dev)
826{
3951e4aa
BS		 827 struct platform_device *pdev = to_platform_device(dev);
828 struct ssc_device *ssc = platform_get_drvdata(pdev);
829
830 if (ssc->pdata->use_dma)
831 atmel_pcm_dma_platform_unregister(dev);
832 else
833 atmel_pcm_pdc_platform_unregister(dev);
834
a2c662c0 835 snd_soc_unregister_component(dev);
be681a82 836}
f0fba2ad 837
abfa4eae
MB		 838/**
839 * atmel_ssc_set_audio - Allocate the specified SSC for audio use.
840 */
841int atmel_ssc_set_audio(int ssc_id)
842{
843 struct ssc_device *ssc;
abfa4eae
MB		 844 int ret;
845
abfa4eae
MB		 846 /* If we can grab the SSC briefly to parent the DAI device off it */
847 ssc = ssc_request(ssc_id);
be681a82
BS		 848 if (IS_ERR(ssc)) {
849 pr_err("Unable to parent ASoC SSC DAI on SSC: %ld\n",
abfa4eae 850 PTR_ERR(ssc));
be681a82
BS		 851 return PTR_ERR(ssc);
852 } else {
853 ssc_info[ssc_id].ssc = ssc;
840d8e5e 854 }
abfa4eae 855
be681a82 856 ret = asoc_ssc_init(&ssc->pdev->dev);
abfa4eae
MB		 857
858 return ret;
859}
860EXPORT_SYMBOL_GPL(atmel_ssc_set_audio);
861
be681a82
BS		 862void atmel_ssc_put_audio(int ssc_id)
863{
864 struct ssc_device *ssc = ssc_info[ssc_id].ssc;
865
be681a82 866 asoc_ssc_exit(&ssc->pdev->dev);
69706028 867 ssc_free(ssc);
be681a82
BS		 868}
869EXPORT_SYMBOL_GPL(atmel_ssc_put_audio);
3f4b783c 870
6c742509
SG		 871/* Module information */
872MODULE_AUTHOR("Sedji Gaouaou, sedji.gaouaou@atmel.com, www.atmel.com");
873MODULE_DESCRIPTION("ATMEL SSC ASoC Interface");
874MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.340185 seconds and 5 git commands to generate.