[deliverable/linux.git] / sound / soc / au1x / psc-ac97.c

/*
 * Au12x0/Au1550 PSC ALSA ASoC audio support.
 *
 * (c) 2007-2009 MSC Vertriebsges.m.b.H.,
 *	Manuel Lauss <manuel.lauss@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Au1xxx-PSC AC97 glue.
 *
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/mutex.h>
#include <linux/suspend.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1xxx_psc.h>

#include "psc.h"

/* how often to retry failed codec register reads/writes */
#define AC97_RW_RETRIES	5

#define AC97_DIR	\
	(SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE)

#define AC97_RATES	\
	SNDRV_PCM_RATE_8000_48000

#define AC97_FMTS	\
	(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3BE)

#define AC97PCR_START(stype)	\
	((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_AC97PCR_TS : PSC_AC97PCR_RS)
#define AC97PCR_STOP(stype)	\
	((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_AC97PCR_TP : PSC_AC97PCR_RP)
#define AC97PCR_CLRFIFO(stype)	\
	((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_AC97PCR_TC : PSC_AC97PCR_RC)

#define AC97STAT_BUSY(stype)	\
	((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_AC97STAT_TB : PSC_AC97STAT_RB)

/* instance data. There can be only one, MacLeod!!!! */
static struct au1xpsc_audio_data *au1xpsc_ac97_workdata;

#if 0

/* this could theoretically work, but ac97->bus->card->private_data can be NULL
 * when snd_ac97_mixer() is called; I don't know if the rest further down the
 * chain are always valid either.
 */
static inline struct au1xpsc_audio_data *ac97_to_pscdata(struct snd_ac97 *x)
{
	struct snd_soc_card *c = x->bus->card->private_data;
	return snd_soc_dai_get_drvdata(c->rtd->cpu_dai);
}

#else

#define ac97_to_pscdata(x)	au1xpsc_ac97_workdata

#endif

/* AC97 controller reads codec register */
static unsigned short au1xpsc_ac97_read(struct snd_ac97 *ac97,
					unsigned short reg)
{
	struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97);
	unsigned short retry, tmo;
	unsigned long data;

	au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
	au_sync();

	retry = AC97_RW_RETRIES;
	do {
		mutex_lock(&pscdata->lock);

		au_writel(PSC_AC97CDC_RD | PSC_AC97CDC_INDX(reg),
			  AC97_CDC(pscdata));
		au_sync();

		tmo = 20;
		do {
			udelay(21);
			if (au_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)
				break;
		} while (--tmo);

		data = au_readl(AC97_CDC(pscdata));

		au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
		au_sync();

		mutex_unlock(&pscdata->lock);

		if (reg != ((data >> 16) & 0x7f))
			tmo = 1;	/* wrong register, try again */

	} while (--retry && !tmo);

	return retry ? data & 0xffff : 0xffff;
}

/* AC97 controller writes to codec register */
static void au1xpsc_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
				unsigned short val)
{
	struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97);
	unsigned int tmo, retry;

	au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
	au_sync();

	retry = AC97_RW_RETRIES;
	do {
		mutex_lock(&pscdata->lock);

		au_writel(PSC_AC97CDC_INDX(reg) | (val & 0xffff),
			  AC97_CDC(pscdata));
		au_sync();

		tmo = 20;
		do {
			udelay(21);
			if (au_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)
				break;
		} while (--tmo);

		au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
		au_sync();

		mutex_unlock(&pscdata->lock);
	} while (--retry && !tmo);
}

/* AC97 controller asserts a warm reset */
static void au1xpsc_ac97_warm_reset(struct snd_ac97 *ac97)
{
	struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97);

	au_writel(PSC_AC97RST_SNC, AC97_RST(pscdata));
	au_sync();
	msleep(10);
	au_writel(0, AC97_RST(pscdata));
	au_sync();
}

static void au1xpsc_ac97_cold_reset(struct snd_ac97 *ac97)
{
	struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97);
	int i;

	/* disable PSC during cold reset */
	au_writel(0, AC97_CFG(au1xpsc_ac97_workdata));
	au_sync();
	au_writel(PSC_CTRL_DISABLE, PSC_CTRL(pscdata));
	au_sync();

	/* issue cold reset */
	au_writel(PSC_AC97RST_RST, AC97_RST(pscdata));
	au_sync();
	msleep(500);
	au_writel(0, AC97_RST(pscdata));
	au_sync();

	/* enable PSC */
	au_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata));
	au_sync();

	/* wait for PSC to indicate it's ready */
	i = 1000;
	while (!((au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_SR)) && (--i))
		msleep(1);

	if (i == 0) {
		printk(KERN_ERR "au1xpsc-ac97: PSC not ready!\n");
		return;
	}

	/* enable the ac97 function */
	au_writel(pscdata->cfg | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
	au_sync();

	/* wait for AC97 core to become ready */
	i = 1000;
	while (!((au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && (--i))
		msleep(1);
	if (i == 0)
		printk(KERN_ERR "au1xpsc-ac97: AC97 ctrl not ready\n");
}

/* AC97 controller operations */
struct snd_ac97_bus_ops soc_ac97_ops = {
	.read		= au1xpsc_ac97_read,
	.write		= au1xpsc_ac97_write,
	.reset		= au1xpsc_ac97_cold_reset,
	.warm_reset	= au1xpsc_ac97_warm_reset,
};
EXPORT_SYMBOL_GPL(soc_ac97_ops);

static int au1xpsc_ac97_hw_params(struct snd_pcm_substream *substream,
				  struct snd_pcm_hw_params *params,
				  struct snd_soc_dai *dai)
{
	struct au1xpsc_audio_data *pscdata = snd_soc_dai_get_drvdata(dai);
	unsigned long r, ro, stat;
	int chans, t, stype = substream->stream;

	chans = params_channels(params);

	r = ro = au_readl(AC97_CFG(pscdata));
	stat = au_readl(AC97_STAT(pscdata));

	/* already active? */
	if (stat & (PSC_AC97STAT_TB | PSC_AC97STAT_RB)) {
		/* reject parameters not currently set up */
		if ((PSC_AC97CFG_GET_LEN(r) != params->msbits) ||
		    (pscdata->rate != params_rate(params)))
			return -EINVAL;
	} else {

		/* set sample bitdepth: REG[24:21]=(BITS-2)/2 */
		r &= ~PSC_AC97CFG_LEN_MASK;
		r |= PSC_AC97CFG_SET_LEN(params->msbits);

		/* channels: enable slots for front L/R channel */
		if (stype == SNDRV_PCM_STREAM_PLAYBACK) {
			r &= ~PSC_AC97CFG_TXSLOT_MASK;
			r |= PSC_AC97CFG_TXSLOT_ENA(3);
			r |= PSC_AC97CFG_TXSLOT_ENA(4);
		} else {
			r &= ~PSC_AC97CFG_RXSLOT_MASK;
			r |= PSC_AC97CFG_RXSLOT_ENA(3);
			r |= PSC_AC97CFG_RXSLOT_ENA(4);
		}

		/* do we need to poke the hardware? */
		if (!(r ^ ro))
			goto out;

		/* ac97 engine is about to be disabled */
		mutex_lock(&pscdata->lock);

		/* disable AC97 device controller first... */
		au_writel(r & ~PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
		au_sync();

		/* ...wait for it... */
		t = 100;
		while ((au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR) && --t)
			msleep(1);

		if (!t)
			printk(KERN_ERR "PSC-AC97: can't disable!\n");

		/* ...write config... */
		au_writel(r, AC97_CFG(pscdata));
		au_sync();

		/* ...enable the AC97 controller again... */
		au_writel(r | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
		au_sync();

		/* ...and wait for ready bit */
		t = 100;
		while ((!(au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && --t)
			msleep(1);

		if (!t)
			printk(KERN_ERR "PSC-AC97: can't enable!\n");

		mutex_unlock(&pscdata->lock);

		pscdata->cfg = r;
		pscdata->rate = params_rate(params);
	}

out:
	return 0;
}

static int au1xpsc_ac97_trigger(struct snd_pcm_substream *substream,
				int cmd, struct snd_soc_dai *dai)
{
	struct au1xpsc_audio_data *pscdata = snd_soc_dai_get_drvdata(dai);
	int ret, stype = substream->stream;

	ret = 0;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
		au_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata));
		au_sync();
		au_writel(AC97PCR_START(stype), AC97_PCR(pscdata));
		au_sync();
		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
		au_writel(AC97PCR_STOP(stype), AC97_PCR(pscdata));
		au_sync();

		while (au_readl(AC97_STAT(pscdata)) & AC97STAT_BUSY(stype))
			asm volatile ("nop");

		au_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata));
		au_sync();

		break;
	default:
		ret = -EINVAL;
	}
	return ret;
}

static int au1xpsc_ac97_startup(struct snd_pcm_substream *substream,
				struct snd_soc_dai *dai)
{
	struct au1xpsc_audio_data *pscdata = snd_soc_dai_get_drvdata(dai);
	snd_soc_dai_set_dma_data(dai, substream, &pscdata->dmaids[0]);
	return 0;
}

static int au1xpsc_ac97_probe(struct snd_soc_dai *dai)
{
	return au1xpsc_ac97_workdata ? 0 : -ENODEV;
}

static const struct snd_soc_dai_ops au1xpsc_ac97_dai_ops = {
	.startup	= au1xpsc_ac97_startup,
	.trigger	= au1xpsc_ac97_trigger,
	.hw_params	= au1xpsc_ac97_hw_params,
};

static const struct snd_soc_dai_driver au1xpsc_ac97_dai_template = {
	.ac97_control		= 1,
	.probe			= au1xpsc_ac97_probe,
	.playback = {
		.rates		= AC97_RATES,
		.formats	= AC97_FMTS,
		.channels_min	= 2,
		.channels_max	= 2,
	},
	.capture = {
		.rates		= AC97_RATES,
		.formats	= AC97_FMTS,
		.channels_min	= 2,
		.channels_max	= 2,
	},
	.ops = &au1xpsc_ac97_dai_ops,
};

static int au1xpsc_ac97_drvprobe(struct platform_device *pdev)
{
	int ret;
	struct resource *iores, *dmares;
	unsigned long sel;
	struct au1xpsc_audio_data *wd;

	wd = devm_kzalloc(&pdev->dev, sizeof(struct au1xpsc_audio_data),
			  GFP_KERNEL);
	if (!wd)
		return -ENOMEM;

	mutex_init(&wd->lock);

	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!iores)
		return -ENODEV;

	if (!devm_request_mem_region(&pdev->dev, iores->start,
				     resource_size(iores),
				     pdev->name))
		return -EBUSY;

	wd->mmio = devm_ioremap(&pdev->dev, iores->start,
				resource_size(iores));
	if (!wd->mmio)
		return -EBUSY;

	dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
	if (!dmares)
		return -EBUSY;
	wd->dmaids[SNDRV_PCM_STREAM_PLAYBACK] = dmares->start;

	dmares = platform_get_resource(pdev, IORESOURCE_DMA, 1);
	if (!dmares)
		return -EBUSY;
	wd->dmaids[SNDRV_PCM_STREAM_CAPTURE] = dmares->start;

	/* configuration: max dma trigger threshold, enable ac97 */
	wd->cfg = PSC_AC97CFG_RT_FIFO8 | PSC_AC97CFG_TT_FIFO8 |
		  PSC_AC97CFG_DE_ENABLE;

	/* preserve PSC clock source set up by platform	 */
	sel = au_readl(PSC_SEL(wd)) & PSC_SEL_CLK_MASK;
	au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
	au_sync();
	au_writel(0, PSC_SEL(wd));
	au_sync();
	au_writel(PSC_SEL_PS_AC97MODE | sel, PSC_SEL(wd));
	au_sync();

	/* name the DAI like this device instance ("au1xpsc-ac97.PSCINDEX") */
	memcpy(&wd->dai_drv, &au1xpsc_ac97_dai_template,
	       sizeof(struct snd_soc_dai_driver));
	wd->dai_drv.name = dev_name(&pdev->dev);

	platform_set_drvdata(pdev, wd);

	ret = snd_soc_register_dai(&pdev->dev, &wd->dai_drv);
	if (ret)
		return ret;

	au1xpsc_ac97_workdata = wd;
	return 0;
}

static int au1xpsc_ac97_drvremove(struct platform_device *pdev)
{
	struct au1xpsc_audio_data *wd = platform_get_drvdata(pdev);

	snd_soc_unregister_dai(&pdev->dev);

	/* disable PSC completely */
	au_writel(0, AC97_CFG(wd));
	au_sync();
	au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
	au_sync();

	au1xpsc_ac97_workdata = NULL;	/* MDEV */

	return 0;
}

#ifdef CONFIG_PM
static int au1xpsc_ac97_drvsuspend(struct device *dev)
{
	struct au1xpsc_audio_data *wd = dev_get_drvdata(dev);

	/* save interesting registers and disable PSC */
	wd->pm[0] = au_readl(PSC_SEL(wd));

	au_writel(0, AC97_CFG(wd));
	au_sync();
	au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
	au_sync();

	return 0;
}

static int au1xpsc_ac97_drvresume(struct device *dev)
{
	struct au1xpsc_audio_data *wd = dev_get_drvdata(dev);

	/* restore PSC clock config */
	au_writel(wd->pm[0] | PSC_SEL_PS_AC97MODE, PSC_SEL(wd));
	au_sync();

	/* after this point the ac97 core will cold-reset the codec.
	 * During cold-reset the PSC is reinitialized and the last
	 * configuration set up in hw_params() is restored.
	 */
	return 0;
}

static struct dev_pm_ops au1xpscac97_pmops = {
	.suspend	= au1xpsc_ac97_drvsuspend,
	.resume		= au1xpsc_ac97_drvresume,
};

#define AU1XPSCAC97_PMOPS &au1xpscac97_pmops

#else

#define AU1XPSCAC97_PMOPS NULL

#endif

static struct platform_driver au1xpsc_ac97_driver = {
	.driver	= {
		.name	= "au1xpsc_ac97",
		.owner	= THIS_MODULE,
		.pm	= AU1XPSCAC97_PMOPS,
	},
	.probe		= au1xpsc_ac97_drvprobe,
	.remove		= au1xpsc_ac97_drvremove,
};

static int __init au1xpsc_ac97_load(void)
{
	au1xpsc_ac97_workdata = NULL;
	return platform_driver_register(&au1xpsc_ac97_driver);
}

static void __exit au1xpsc_ac97_unload(void)
{
	platform_driver_unregister(&au1xpsc_ac97_driver);
}

module_init(au1xpsc_ac97_load);
module_exit(au1xpsc_ac97_unload);

MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Au12x0/Au1550 PSC AC97 ALSA ASoC audio driver");
MODULE_AUTHOR("Manuel Lauss");
Commit	Line	Data
4a161d23 ML	1	/*
	2	* Au12x0/Au1550 PSC ALSA ASoC audio support.
	3	*
cdc65fbe ML	4	* (c) 2007-2009 MSC Vertriebsges.m.b.H.,
cdc65fbe ML	5	* Manuel Lauss <manuel.lauss@gmail.com>
4a161d23 ML	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* Au1xxx-PSC AC97 glue.
	12	*
4a161d23 ML	13	*/
	14
	15	#include <linux/init.h>
	16	#include <linux/module.h>
5a0e3ad6	17	#include <linux/slab.h>
4a161d23 ML	18	#include <linux/device.h>
4a161d23 ML	19	#include <linux/delay.h>
cdc65fbe	20	#include <linux/mutex.h>
4a161d23 ML	21	#include <linux/suspend.h>
	22	#include <sound/core.h>
	23	#include <sound/pcm.h>
	24	#include <sound/initval.h>
	25	#include <sound/soc.h>
	26	#include <asm/mach-au1x00/au1000.h>
	27	#include <asm/mach-au1x00/au1xxx_psc.h>
	28
	29	#include "psc.h"
	30
cdc65fbe ML	31	/* how often to retry failed codec register reads/writes */
	32	#define AC97_RW_RETRIES 5
	33
4a161d23 ML	34	#define AC97_DIR \
	35	(SND_SOC_DAIDIR_PLAYBACK \| SND_SOC_DAIDIR_CAPTURE)
	36
	37	#define AC97_RATES \
	38	SNDRV_PCM_RATE_8000_48000
	39
	40	#define AC97_FMTS \
	41	(SNDRV_PCM_FMTBIT_S16_LE \| SNDRV_PCM_FMTBIT_S20_3BE)
	42
	43	#define AC97PCR_START(stype) \
25942fdc	44	((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_AC97PCR_TS : PSC_AC97PCR_RS)
4a161d23	45	#define AC97PCR_STOP(stype) \
25942fdc	46	((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_AC97PCR_TP : PSC_AC97PCR_RP)
4a161d23	47	#define AC97PCR_CLRFIFO(stype) \
25942fdc	48	((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_AC97PCR_TC : PSC_AC97PCR_RC)
4a161d23	49
cdc65fbe	50	#define AC97STAT_BUSY(stype) \
25942fdc	51	((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_AC97STAT_TB : PSC_AC97STAT_RB)
cdc65fbe	52
4a161d23 ML	53	/* instance data. There can be only one, MacLeod!!!! */
	54	static struct au1xpsc_audio_data *au1xpsc_ac97_workdata;
	55
ffc4fdbb ML	56	#if 0
	57
	58	/* this could theoretically work, but ac97->bus->card->private_data can be NULL
	59	* when snd_ac97_mixer() is called; I don't know if the rest further down the
	60	* chain are always valid either.
	61	*/
	62	static inline struct au1xpsc_audio_data ac97_to_pscdata(struct snd_ac97 x)
	63	{
	64	struct snd_soc_card *c = x->bus->card->private_data;
	65	return snd_soc_dai_get_drvdata(c->rtd->cpu_dai);
	66	}
	67
	68	#else
	69
	70	#define ac97_to_pscdata(x) au1xpsc_ac97_workdata
	71
	72	#endif
	73
4a161d23 ML	74	/* AC97 controller reads codec register */
	75	static unsigned short au1xpsc_ac97_read(struct snd_ac97 *ac97,
	76	unsigned short reg)
	77	{
ffc4fdbb	78	struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97);
e697cd41 ML	79	unsigned short retry, tmo;
e697cd41 ML	80	unsigned long data;
4a161d23	81
cdc65fbe	82	au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
4a161d23 ML	83	au_sync();
4a161d23 ML	84
cdc65fbe ML	85	retry = AC97_RW_RETRIES;
	86	do {
	87	mutex_lock(&pscdata->lock);
	88
	89	au_writel(PSC_AC97CDC_RD \| PSC_AC97CDC_INDX(reg),
	90	AC97_CDC(pscdata));
	91	au_sync();
	92
8d567b6b ML	93	tmo = 20;
	94	do {
	95	udelay(21);
	96	if (au_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)
	97	break;
	98	} while (--tmo);
4a161d23	99
e697cd41	100	data = au_readl(AC97_CDC(pscdata));
4a161d23	101
cdc65fbe ML	102	au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
	103	au_sync();
	104
	105	mutex_unlock(&pscdata->lock);
e697cd41 ML	106
	107	if (reg != ((data >> 16) & 0x7f))
	108	tmo = 1; /* wrong register, try again */
	109
cdc65fbe	110	} while (--retry && !tmo);
4a161d23	111
e697cd41	112	return retry ? data & 0xffff : 0xffff;
4a161d23 ML	113	}
	114
	115	/* AC97 controller writes to codec register */
	116	static void au1xpsc_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
	117	unsigned short val)
	118	{
ffc4fdbb	119	struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97);
cdc65fbe	120	unsigned int tmo, retry;
4a161d23	121
cdc65fbe	122	au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
4a161d23	123	au_sync();
cdc65fbe ML	124
	125	retry = AC97_RW_RETRIES;
	126	do {
	127	mutex_lock(&pscdata->lock);
	128
	129	au_writel(PSC_AC97CDC_INDX(reg) \| (val & 0xffff),
	130	AC97_CDC(pscdata));
4a161d23 ML	131	au_sync();
4a161d23 ML	132
8d567b6b ML	133	tmo = 20;
	134	do {
	135	udelay(21);
	136	if (au_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)
	137	break;
	138	} while (--tmo);
cdc65fbe ML	139
	140	au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
	141	au_sync();
	142
	143	mutex_unlock(&pscdata->lock);
	144	} while (--retry && !tmo);
4a161d23 ML	145	}
	146
	147	/* AC97 controller asserts a warm reset */
	148	static void au1xpsc_ac97_warm_reset(struct snd_ac97 *ac97)
	149	{
ffc4fdbb	150	struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97);
4a161d23 ML	151
	152	au_writel(PSC_AC97RST_SNC, AC97_RST(pscdata));
	153	au_sync();
	154	msleep(10);
	155	au_writel(0, AC97_RST(pscdata));
	156	au_sync();
	157	}
	158
	159	static void au1xpsc_ac97_cold_reset(struct snd_ac97 *ac97)
	160	{
ffc4fdbb	161	struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97);
4a161d23 ML	162	int i;
	163
	164	/* disable PSC during cold reset */
	165	au_writel(0, AC97_CFG(au1xpsc_ac97_workdata));
	166	au_sync();
	167	au_writel(PSC_CTRL_DISABLE, PSC_CTRL(pscdata));
	168	au_sync();
	169
	170	/* issue cold reset */
	171	au_writel(PSC_AC97RST_RST, AC97_RST(pscdata));
	172	au_sync();
	173	msleep(500);
	174	au_writel(0, AC97_RST(pscdata));
	175	au_sync();
	176
	177	/* enable PSC */
	178	au_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata));
	179	au_sync();
	180
	181	/* wait for PSC to indicate it's ready */
cdc65fbe	182	i = 1000;
4a161d23	183	while (!((au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_SR)) && (--i))
cdc65fbe	184	msleep(1);
4a161d23 ML	185
	186	if (i == 0) {
	187	printk(KERN_ERR "au1xpsc-ac97: PSC not ready!\n");
	188	return;
	189	}
	190
	191	/* enable the ac97 function */
	192	au_writel(pscdata->cfg \| PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
	193	au_sync();
	194
	195	/* wait for AC97 core to become ready */
cdc65fbe	196	i = 1000;
4a161d23	197	while (!((au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && (--i))
cdc65fbe	198	msleep(1);
4a161d23 ML	199	if (i == 0)
	200	printk(KERN_ERR "au1xpsc-ac97: AC97 ctrl not ready\n");
	201	}
	202
	203	/* AC97 controller operations */
	204	struct snd_ac97_bus_ops soc_ac97_ops = {
	205	.read = au1xpsc_ac97_read,
	206	.write = au1xpsc_ac97_write,
	207	.reset = au1xpsc_ac97_cold_reset,
	208	.warm_reset = au1xpsc_ac97_warm_reset,
	209	};
	210	EXPORT_SYMBOL_GPL(soc_ac97_ops);
	211
	212	static int au1xpsc_ac97_hw_params(struct snd_pcm_substream *substream,
dee89c4d MB	213	struct snd_pcm_hw_params *params,
dee89c4d MB	214	struct snd_soc_dai *dai)
4a161d23	215	{
ffc4fdbb	216	struct au1xpsc_audio_data *pscdata = snd_soc_dai_get_drvdata(dai);
cdc65fbe	217	unsigned long r, ro, stat;
25942fdc	218	int chans, t, stype = substream->stream;
4a161d23 ML	219
	220	chans = params_channels(params);
	221
cdc65fbe	222	r = ro = au_readl(AC97_CFG(pscdata));
4a161d23 ML	223	stat = au_readl(AC97_STAT(pscdata));
	224
	225	/* already active? */
	226	if (stat & (PSC_AC97STAT_TB \| PSC_AC97STAT_RB)) {
	227	/* reject parameters not currently set up */
	228	if ((PSC_AC97CFG_GET_LEN(r) != params->msbits) \|\|
	229	(pscdata->rate != params_rate(params)))
	230	return -EINVAL;
	231	} else {
4a161d23 ML	232
	233	/* set sample bitdepth: REG[24:21]=(BITS-2)/2 */
	234	r &= ~PSC_AC97CFG_LEN_MASK;
	235	r \|= PSC_AC97CFG_SET_LEN(params->msbits);
	236
	237	/* channels: enable slots for front L/R channel */
25942fdc	238	if (stype == SNDRV_PCM_STREAM_PLAYBACK) {
4a161d23 ML	239	r &= ~PSC_AC97CFG_TXSLOT_MASK;
	240	r \|= PSC_AC97CFG_TXSLOT_ENA(3);
	241	r \|= PSC_AC97CFG_TXSLOT_ENA(4);
	242	} else {
	243	r &= ~PSC_AC97CFG_RXSLOT_MASK;
	244	r \|= PSC_AC97CFG_RXSLOT_ENA(3);
	245	r \|= PSC_AC97CFG_RXSLOT_ENA(4);
	246	}
	247
cdc65fbe ML	248	/* do we need to poke the hardware? */
	249	if (!(r ^ ro))
	250	goto out;
	251
	252	/* ac97 engine is about to be disabled */
	253	mutex_lock(&pscdata->lock);
	254
	255	/* disable AC97 device controller first... */
	256	au_writel(r & ~PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
	257	au_sync();
	258
	259	/* ...wait for it... */
8d567b6b ML	260	t = 100;
	261	while ((au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR) && --t)
	262	msleep(1);
	263
	264	if (!t)
	265	printk(KERN_ERR "PSC-AC97: can't disable!\n");
cdc65fbe ML	266
	267	/* ...write config... */
	268	au_writel(r, AC97_CFG(pscdata));
	269	au_sync();
	270
	271	/* ...enable the AC97 controller again... */
4a161d23 ML	272	au_writel(r \| PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
	273	au_sync();
	274
cdc65fbe	275	/* ...and wait for ready bit */
8d567b6b ML	276	t = 100;
	277	while ((!(au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && --t)
	278	msleep(1);
	279
	280	if (!t)
	281	printk(KERN_ERR "PSC-AC97: can't enable!\n");
cdc65fbe ML	282
	283	mutex_unlock(&pscdata->lock);
	284
4a161d23 ML	285	pscdata->cfg = r;
	286	pscdata->rate = params_rate(params);
	287	}
	288
cdc65fbe	289	out:
4a161d23 ML	290	return 0;
	291	}
	292
	293	static int au1xpsc_ac97_trigger(struct snd_pcm_substream *substream,
dee89c4d	294	int cmd, struct snd_soc_dai *dai)
4a161d23	295	{
ffc4fdbb	296	struct au1xpsc_audio_data *pscdata = snd_soc_dai_get_drvdata(dai);
25942fdc	297	int ret, stype = substream->stream;
4a161d23 ML	298
	299	ret = 0;
	300
	301	switch (cmd) {
	302	case SNDRV_PCM_TRIGGER_START:
	303	case SNDRV_PCM_TRIGGER_RESUME:
cdc65fbe ML	304	au_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata));
cdc65fbe ML	305	au_sync();
4a161d23 ML	306	au_writel(AC97PCR_START(stype), AC97_PCR(pscdata));
	307	au_sync();
	308	break;
	309	case SNDRV_PCM_TRIGGER_STOP:
	310	case SNDRV_PCM_TRIGGER_SUSPEND:
	311	au_writel(AC97PCR_STOP(stype), AC97_PCR(pscdata));
	312	au_sync();
cdc65fbe ML	313
	314	while (au_readl(AC97_STAT(pscdata)) & AC97STAT_BUSY(stype))
	315	asm volatile ("nop");
	316
	317	au_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata));
	318	au_sync();
	319
4a161d23 ML	320	break;
	321	default:
	322	ret = -EINVAL;
	323	}
	324	return ret;
	325	}
	326
5b0912be ML	327	static int au1xpsc_ac97_startup(struct snd_pcm_substream *substream,
	328	struct snd_soc_dai *dai)
	329	{
	330	struct au1xpsc_audio_data *pscdata = snd_soc_dai_get_drvdata(dai);
	331	snd_soc_dai_set_dma_data(dai, substream, &pscdata->dmaids[0]);
	332	return 0;
	333	}
	334
f0fba2ad	335	static int au1xpsc_ac97_probe(struct snd_soc_dai *dai)
0f83d639 ML	336	{
	337	return au1xpsc_ac97_workdata ? 0 : -ENODEV;
	338	}
	339
85e7652d	340	static const struct snd_soc_dai_ops au1xpsc_ac97_dai_ops = {
5b0912be	341	.startup = au1xpsc_ac97_startup,
0f83d639 ML	342	.trigger = au1xpsc_ac97_trigger,
	343	.hw_params = au1xpsc_ac97_hw_params,
	344	};
	345
ffc4fdbb	346	static const struct snd_soc_dai_driver au1xpsc_ac97_dai_template = {
0f83d639 ML	347	.ac97_control = 1,
0f83d639 ML	348	.probe = au1xpsc_ac97_probe,
0f83d639 ML	349	.playback = {
	350	.rates = AC97_RATES,
	351	.formats = AC97_FMTS,
	352	.channels_min = 2,
	353	.channels_max = 2,
	354	},
	355	.capture = {
	356	.rates = AC97_RATES,
	357	.formats = AC97_FMTS,
	358	.channels_min = 2,
	359	.channels_max = 2,
	360	},
	361	.ops = &au1xpsc_ac97_dai_ops,
	362	};
0f83d639	363
5c658be0	364	static int au1xpsc_ac97_drvprobe(struct platform_device *pdev)
4a161d23 ML	365	{
4a161d23 ML	366	int ret;
226d0f22	367	struct resource iores, dmares;
4a161d23	368	unsigned long sel;
0f83d639	369	struct au1xpsc_audio_data *wd;
4a161d23	370
8d9626d7 JL	371	wd = devm_kzalloc(&pdev->dev, sizeof(struct au1xpsc_audio_data),
8d9626d7 JL	372	GFP_KERNEL);
0f83d639	373	if (!wd)
4a161d23 ML	374	return -ENOMEM;
4a161d23 ML	375
0f83d639	376	mutex_init(&wd->lock);
cdc65fbe	377
226d0f22	378	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8d9626d7 JL	379	if (!iores)
8d9626d7 JL	380	return -ENODEV;
4a161d23	381
8d9626d7 JL	382	if (!devm_request_mem_region(&pdev->dev, iores->start,
	383	resource_size(iores),
	384	pdev->name))
	385	return -EBUSY;
4a161d23	386
8d9626d7 JL	387	wd->mmio = devm_ioremap(&pdev->dev, iores->start,
8d9626d7 JL	388	resource_size(iores));
0f83d639	389	if (!wd->mmio)
8d9626d7	390	return -EBUSY;
4a161d23	391
226d0f22 JL	392	dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
226d0f22 JL	393	if (!dmares)
8d9626d7	394	return -EBUSY;
226d0f22	395	wd->dmaids[SNDRV_PCM_STREAM_PLAYBACK] = dmares->start;
5b0912be	396
226d0f22 JL	397	dmares = platform_get_resource(pdev, IORESOURCE_DMA, 1);
226d0f22 JL	398	if (!dmares)
8d9626d7	399	return -EBUSY;
226d0f22	400	wd->dmaids[SNDRV_PCM_STREAM_CAPTURE] = dmares->start;
5b0912be	401
4a161d23	402	/* configuration: max dma trigger threshold, enable ac97 */
0f83d639 ML	403	wd->cfg = PSC_AC97CFG_RT_FIFO8 \| PSC_AC97CFG_TT_FIFO8 \|
0f83d639 ML	404	PSC_AC97CFG_DE_ENABLE;
4a161d23	405
0f83d639 ML	406	/* preserve PSC clock source set up by platform */
	407	sel = au_readl(PSC_SEL(wd)) & PSC_SEL_CLK_MASK;
	408	au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
4a161d23	409	au_sync();
0f83d639	410	au_writel(0, PSC_SEL(wd));
4a161d23	411	au_sync();
0f83d639	412	au_writel(PSC_SEL_PS_AC97MODE \| sel, PSC_SEL(wd));
4a161d23	413	au_sync();
4a161d23	414
ffc4fdbb ML	415	/* name the DAI like this device instance ("au1xpsc-ac97.PSCINDEX") */
	416	memcpy(&wd->dai_drv, &au1xpsc_ac97_dai_template,
	417	sizeof(struct snd_soc_dai_driver));
	418	wd->dai_drv.name = dev_name(&pdev->dev);
	419
	420	platform_set_drvdata(pdev, wd);
	421
	422	ret = snd_soc_register_dai(&pdev->dev, &wd->dai_drv);
0f83d639	423	if (ret)
8d9626d7	424	return ret;
0f83d639	425
5b0912be ML	426	au1xpsc_ac97_workdata = wd;
5b0912be ML	427	return 0;
4a161d23 ML	428	}
4a161d23 ML	429
5c658be0	430	static int au1xpsc_ac97_drvremove(struct platform_device *pdev)
4a161d23	431	{
0f83d639 ML	432	struct au1xpsc_audio_data *wd = platform_get_drvdata(pdev);
0f83d639 ML	433
f0fba2ad	434	snd_soc_unregister_dai(&pdev->dev);
0f83d639	435
4a161d23	436	/* disable PSC completely */
0f83d639	437	au_writel(0, AC97_CFG(wd));
4a161d23	438	au_sync();
0f83d639	439	au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
4a161d23 ML	440	au_sync();
4a161d23 ML	441
0f83d639 ML	442	au1xpsc_ac97_workdata = NULL; /* MDEV */
	443
	444	return 0;
4a161d23 ML	445	}
4a161d23 ML	446
0f83d639 ML	447	#ifdef CONFIG_PM
0f83d639 ML	448	static int au1xpsc_ac97_drvsuspend(struct device *dev)
4a161d23	449	{
0f83d639 ML	450	struct au1xpsc_audio_data *wd = dev_get_drvdata(dev);
0f83d639 ML	451
4a161d23	452	/* save interesting registers and disable PSC */
0f83d639	453	wd->pm[0] = au_readl(PSC_SEL(wd));
4a161d23	454
0f83d639	455	au_writel(0, AC97_CFG(wd));
4a161d23	456	au_sync();
0f83d639	457	au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
4a161d23 ML	458	au_sync();
	459
	460	return 0;
	461	}
	462
0f83d639	463	static int au1xpsc_ac97_drvresume(struct device *dev)
4a161d23	464	{
0f83d639 ML	465	struct au1xpsc_audio_data *wd = dev_get_drvdata(dev);
0f83d639 ML	466
4a161d23	467	/* restore PSC clock config */
0f83d639	468	au_writel(wd->pm[0] \| PSC_SEL_PS_AC97MODE, PSC_SEL(wd));
4a161d23 ML	469	au_sync();
	470
	471	/* after this point the ac97 core will cold-reset the codec.
	472	* During cold-reset the PSC is reinitialized and the last
	473	* configuration set up in hw_params() is restored.
	474	*/
	475	return 0;
	476	}
	477
0f83d639 ML	478	static struct dev_pm_ops au1xpscac97_pmops = {
	479	.suspend = au1xpsc_ac97_drvsuspend,
	480	.resume = au1xpsc_ac97_drvresume,
6335d055 EM	481	};
6335d055 EM	482
0f83d639 ML	483	#define AU1XPSCAC97_PMOPS &au1xpscac97_pmops
	484
	485	#else
	486
	487	#define AU1XPSCAC97_PMOPS NULL
	488
	489	#endif
	490
	491	static struct platform_driver au1xpsc_ac97_driver = {
	492	.driver = {
ffc4fdbb	493	.name = "au1xpsc_ac97",
0f83d639 ML	494	.owner = THIS_MODULE,
0f83d639 ML	495	.pm = AU1XPSCAC97_PMOPS,
4a161d23	496	},
0f83d639	497	.probe = au1xpsc_ac97_drvprobe,
5c658be0	498	.remove = au1xpsc_ac97_drvremove,
4a161d23	499	};
4a161d23	500
0f83d639	501	static int __init au1xpsc_ac97_load(void)
4a161d23 ML	502	{
4a161d23 ML	503	au1xpsc_ac97_workdata = NULL;
0f83d639	504	return platform_driver_register(&au1xpsc_ac97_driver);
4a161d23 ML	505	}
4a161d23 ML	506
0f83d639	507	static void __exit au1xpsc_ac97_unload(void)
4a161d23	508	{
0f83d639	509	platform_driver_unregister(&au1xpsc_ac97_driver);
4a161d23 ML	510	}
4a161d23 ML	511
0f83d639 ML	512	module_init(au1xpsc_ac97_load);
0f83d639 ML	513	module_exit(au1xpsc_ac97_unload);
4a161d23 ML	514
	515	MODULE_LICENSE("GPL");
	516	MODULE_DESCRIPTION("Au12x0/Au1550 PSC AC97 ALSA ASoC audio driver");
0f83d639 ML	517	MODULE_AUTHOR("Manuel Lauss");
0f83d639 ML	518