[deliverable/linux.git] / sound / soc / au1x / psc-ac97.c

/*
 * Au12x0/Au1550 PSC ALSA ASoC audio support.
 *
 * (c) 2007-2009 MSC Vertriebsges.m.b.H.,
 *	Manuel Lauss <manuel.lauss@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Au1xxx-PSC AC97 glue.
 *
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/mutex.h>
#include <linux/suspend.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1xxx_psc.h>

#include "psc.h"

/* how often to retry failed codec register reads/writes */
#define AC97_RW_RETRIES	5

#define AC97_DIR	\
	(SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE)

#define AC97_RATES	\
	SNDRV_PCM_RATE_8000_48000

#define AC97_FMTS	\
	(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3BE)

#define AC97PCR_START(stype)	\
	((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_AC97PCR_TS : PSC_AC97PCR_RS)
#define AC97PCR_STOP(stype)	\
	((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_AC97PCR_TP : PSC_AC97PCR_RP)
#define AC97PCR_CLRFIFO(stype)	\
	((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_AC97PCR_TC : PSC_AC97PCR_RC)

#define AC97STAT_BUSY(stype)	\
	((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_AC97STAT_TB : PSC_AC97STAT_RB)

/* instance data. There can be only one, MacLeod!!!! */
static struct au1xpsc_audio_data *au1xpsc_ac97_workdata;

#if 0

/* this could theoretically work, but ac97->bus->card->private_data can be NULL
 * when snd_ac97_mixer() is called; I don't know if the rest further down the
 * chain are always valid either.
 */
static inline struct au1xpsc_audio_data *ac97_to_pscdata(struct snd_ac97 *x)
{
	struct snd_soc_card *c = x->bus->card->private_data;
	return snd_soc_dai_get_drvdata(c->rtd->cpu_dai);
}

#else

#define ac97_to_pscdata(x)	au1xpsc_ac97_workdata

#endif

/* AC97 controller reads codec register */
static unsigned short au1xpsc_ac97_read(struct snd_ac97 *ac97,
					unsigned short reg)
{
	struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97);
	unsigned short retry, tmo;
	unsigned long data;

	__raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
	wmb(); /* drain writebuffer */

	retry = AC97_RW_RETRIES;
	do {
		mutex_lock(&pscdata->lock);

		__raw_writel(PSC_AC97CDC_RD | PSC_AC97CDC_INDX(reg),
			  AC97_CDC(pscdata));
		wmb(); /* drain writebuffer */

		tmo = 20;
		do {
			udelay(21);
			if (__raw_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)
				break;
		} while (--tmo);

		data = __raw_readl(AC97_CDC(pscdata));

		__raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
		wmb(); /* drain writebuffer */

		mutex_unlock(&pscdata->lock);

		if (reg != ((data >> 16) & 0x7f))
			tmo = 1;	/* wrong register, try again */

	} while (--retry && !tmo);

	return retry ? data & 0xffff : 0xffff;
}

/* AC97 controller writes to codec register */
static void au1xpsc_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
				unsigned short val)
{
	struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97);
	unsigned int tmo, retry;

	__raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
	wmb(); /* drain writebuffer */

	retry = AC97_RW_RETRIES;
	do {
		mutex_lock(&pscdata->lock);

		__raw_writel(PSC_AC97CDC_INDX(reg) | (val & 0xffff),
			  AC97_CDC(pscdata));
		wmb(); /* drain writebuffer */

		tmo = 20;
		do {
			udelay(21);
			if (__raw_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)
				break;
		} while (--tmo);

		__raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
		wmb(); /* drain writebuffer */

		mutex_unlock(&pscdata->lock);
	} while (--retry && !tmo);
}

/* AC97 controller asserts a warm reset */
static void au1xpsc_ac97_warm_reset(struct snd_ac97 *ac97)
{
	struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97);

	__raw_writel(PSC_AC97RST_SNC, AC97_RST(pscdata));
	wmb(); /* drain writebuffer */
	msleep(10);
	__raw_writel(0, AC97_RST(pscdata));
	wmb(); /* drain writebuffer */
}

static void au1xpsc_ac97_cold_reset(struct snd_ac97 *ac97)
{
	struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97);
	int i;

	/* disable PSC during cold reset */
	__raw_writel(0, AC97_CFG(au1xpsc_ac97_workdata));
	wmb(); /* drain writebuffer */
	__raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(pscdata));
	wmb(); /* drain writebuffer */

	/* issue cold reset */
	__raw_writel(PSC_AC97RST_RST, AC97_RST(pscdata));
	wmb(); /* drain writebuffer */
	msleep(500);
	__raw_writel(0, AC97_RST(pscdata));
	wmb(); /* drain writebuffer */

	/* enable PSC */
	__raw_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata));
	wmb(); /* drain writebuffer */

	/* wait for PSC to indicate it's ready */
	i = 1000;
	while (!((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_SR)) && (--i))
		msleep(1);

	if (i == 0) {
		printk(KERN_ERR "au1xpsc-ac97: PSC not ready!\n");
		return;
	}

	/* enable the ac97 function */
	__raw_writel(pscdata->cfg | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
	wmb(); /* drain writebuffer */

	/* wait for AC97 core to become ready */
	i = 1000;
	while (!((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && (--i))
		msleep(1);
	if (i == 0)
		printk(KERN_ERR "au1xpsc-ac97: AC97 ctrl not ready\n");
}

/* AC97 controller operations */
static struct snd_ac97_bus_ops psc_ac97_ops = {
	.read		= au1xpsc_ac97_read,
	.write		= au1xpsc_ac97_write,
	.reset		= au1xpsc_ac97_cold_reset,
	.warm_reset	= au1xpsc_ac97_warm_reset,
};

static int au1xpsc_ac97_hw_params(struct snd_pcm_substream *substream,
				  struct snd_pcm_hw_params *params,
				  struct snd_soc_dai *dai)
{
	struct au1xpsc_audio_data *pscdata = snd_soc_dai_get_drvdata(dai);
	unsigned long r, ro, stat;
	int chans, t, stype = substream->stream;

	chans = params_channels(params);

	r = ro = __raw_readl(AC97_CFG(pscdata));
	stat = __raw_readl(AC97_STAT(pscdata));

	/* already active? */
	if (stat & (PSC_AC97STAT_TB | PSC_AC97STAT_RB)) {
		/* reject parameters not currently set up */
		if ((PSC_AC97CFG_GET_LEN(r) != params->msbits) ||
		    (pscdata->rate != params_rate(params)))
			return -EINVAL;
	} else {

		/* set sample bitdepth: REG[24:21]=(BITS-2)/2 */
		r &= ~PSC_AC97CFG_LEN_MASK;
		r |= PSC_AC97CFG_SET_LEN(params->msbits);

		/* channels: enable slots for front L/R channel */
		if (stype == SNDRV_PCM_STREAM_PLAYBACK) {
			r &= ~PSC_AC97CFG_TXSLOT_MASK;
			r |= PSC_AC97CFG_TXSLOT_ENA(3);
			r |= PSC_AC97CFG_TXSLOT_ENA(4);
		} else {
			r &= ~PSC_AC97CFG_RXSLOT_MASK;
			r |= PSC_AC97CFG_RXSLOT_ENA(3);
			r |= PSC_AC97CFG_RXSLOT_ENA(4);
		}

		/* do we need to poke the hardware? */
		if (!(r ^ ro))
			goto out;

		/* ac97 engine is about to be disabled */
		mutex_lock(&pscdata->lock);

		/* disable AC97 device controller first... */
		__raw_writel(r & ~PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
		wmb(); /* drain writebuffer */

		/* ...wait for it... */
		t = 100;
		while ((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR) && --t)
			msleep(1);

		if (!t)
			printk(KERN_ERR "PSC-AC97: can't disable!\n");

		/* ...write config... */
		__raw_writel(r, AC97_CFG(pscdata));
		wmb(); /* drain writebuffer */

		/* ...enable the AC97 controller again... */
		__raw_writel(r | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
		wmb(); /* drain writebuffer */

		/* ...and wait for ready bit */
		t = 100;
		while ((!(__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && --t)
			msleep(1);

		if (!t)
			printk(KERN_ERR "PSC-AC97: can't enable!\n");

		mutex_unlock(&pscdata->lock);

		pscdata->cfg = r;
		pscdata->rate = params_rate(params);
	}

out:
	return 0;
}

static int au1xpsc_ac97_trigger(struct snd_pcm_substream *substream,
				int cmd, struct snd_soc_dai *dai)
{
	struct au1xpsc_audio_data *pscdata = snd_soc_dai_get_drvdata(dai);
	int ret, stype = substream->stream;

	ret = 0;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
		__raw_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata));
		wmb(); /* drain writebuffer */
		__raw_writel(AC97PCR_START(stype), AC97_PCR(pscdata));
		wmb(); /* drain writebuffer */
		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
		__raw_writel(AC97PCR_STOP(stype), AC97_PCR(pscdata));
		wmb(); /* drain writebuffer */

		while (__raw_readl(AC97_STAT(pscdata)) & AC97STAT_BUSY(stype))
			asm volatile ("nop");

		__raw_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata));
		wmb(); /* drain writebuffer */

		break;
	default:
		ret = -EINVAL;
	}
	return ret;
}

static int au1xpsc_ac97_startup(struct snd_pcm_substream *substream,
				struct snd_soc_dai *dai)
{
	struct au1xpsc_audio_data *pscdata = snd_soc_dai_get_drvdata(dai);
	snd_soc_dai_set_dma_data(dai, substream, &pscdata->dmaids[0]);
	return 0;
}

static int au1xpsc_ac97_probe(struct snd_soc_dai *dai)
{
	return au1xpsc_ac97_workdata ? 0 : -ENODEV;
}

static const struct snd_soc_dai_ops au1xpsc_ac97_dai_ops = {
	.startup	= au1xpsc_ac97_startup,
	.trigger	= au1xpsc_ac97_trigger,
	.hw_params	= au1xpsc_ac97_hw_params,
};

static const struct snd_soc_dai_driver au1xpsc_ac97_dai_template = {
	.bus_control		= true,
	.probe			= au1xpsc_ac97_probe,
	.playback = {
		.rates		= AC97_RATES,
		.formats	= AC97_FMTS,
		.channels_min	= 2,
		.channels_max	= 2,
	},
	.capture = {
		.rates		= AC97_RATES,
		.formats	= AC97_FMTS,
		.channels_min	= 2,
		.channels_max	= 2,
	},
	.ops = &au1xpsc_ac97_dai_ops,
};

static const struct snd_soc_component_driver au1xpsc_ac97_component = {
	.name		= "au1xpsc-ac97",
};

static int au1xpsc_ac97_drvprobe(struct platform_device *pdev)
{
	int ret;
	struct resource *iores, *dmares;
	unsigned long sel;
	struct au1xpsc_audio_data *wd;

	wd = devm_kzalloc(&pdev->dev, sizeof(struct au1xpsc_audio_data),
			  GFP_KERNEL);
	if (!wd)
		return -ENOMEM;

	mutex_init(&wd->lock);

	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	wd->mmio = devm_ioremap_resource(&pdev->dev, iores);
	if (IS_ERR(wd->mmio))
		return PTR_ERR(wd->mmio);

	dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
	if (!dmares)
		return -EBUSY;
	wd->dmaids[SNDRV_PCM_STREAM_PLAYBACK] = dmares->start;

	dmares = platform_get_resource(pdev, IORESOURCE_DMA, 1);
	if (!dmares)
		return -EBUSY;
	wd->dmaids[SNDRV_PCM_STREAM_CAPTURE] = dmares->start;

	/* configuration: max dma trigger threshold, enable ac97 */
	wd->cfg = PSC_AC97CFG_RT_FIFO8 | PSC_AC97CFG_TT_FIFO8 |
		  PSC_AC97CFG_DE_ENABLE;

	/* preserve PSC clock source set up by platform	 */
	sel = __raw_readl(PSC_SEL(wd)) & PSC_SEL_CLK_MASK;
	__raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
	wmb(); /* drain writebuffer */
	__raw_writel(0, PSC_SEL(wd));
	wmb(); /* drain writebuffer */
	__raw_writel(PSC_SEL_PS_AC97MODE | sel, PSC_SEL(wd));
	wmb(); /* drain writebuffer */

	/* name the DAI like this device instance ("au1xpsc-ac97.PSCINDEX") */
	memcpy(&wd->dai_drv, &au1xpsc_ac97_dai_template,
	       sizeof(struct snd_soc_dai_driver));
	wd->dai_drv.name = dev_name(&pdev->dev);

	platform_set_drvdata(pdev, wd);

	ret = snd_soc_set_ac97_ops(&psc_ac97_ops);
	if (ret)
		return ret;

	ret = snd_soc_register_component(&pdev->dev, &au1xpsc_ac97_component,
					 &wd->dai_drv, 1);
	if (ret)
		return ret;

	au1xpsc_ac97_workdata = wd;
	return 0;
}

static int au1xpsc_ac97_drvremove(struct platform_device *pdev)
{
	struct au1xpsc_audio_data *wd = platform_get_drvdata(pdev);

	snd_soc_unregister_component(&pdev->dev);

	/* disable PSC completely */
	__raw_writel(0, AC97_CFG(wd));
	wmb(); /* drain writebuffer */
	__raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
	wmb(); /* drain writebuffer */

	au1xpsc_ac97_workdata = NULL;	/* MDEV */

	return 0;
}

#ifdef CONFIG_PM
static int au1xpsc_ac97_drvsuspend(struct device *dev)
{
	struct au1xpsc_audio_data *wd = dev_get_drvdata(dev);

	/* save interesting registers and disable PSC */
	wd->pm[0] = __raw_readl(PSC_SEL(wd));

	__raw_writel(0, AC97_CFG(wd));
	wmb(); /* drain writebuffer */
	__raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
	wmb(); /* drain writebuffer */

	return 0;
}

static int au1xpsc_ac97_drvresume(struct device *dev)
{
	struct au1xpsc_audio_data *wd = dev_get_drvdata(dev);

	/* restore PSC clock config */
	__raw_writel(wd->pm[0] | PSC_SEL_PS_AC97MODE, PSC_SEL(wd));
	wmb(); /* drain writebuffer */

	/* after this point the ac97 core will cold-reset the codec.
	 * During cold-reset the PSC is reinitialized and the last
	 * configuration set up in hw_params() is restored.
	 */
	return 0;
}

static struct dev_pm_ops au1xpscac97_pmops = {
	.suspend	= au1xpsc_ac97_drvsuspend,
	.resume		= au1xpsc_ac97_drvresume,
};

#define AU1XPSCAC97_PMOPS &au1xpscac97_pmops

#else

#define AU1XPSCAC97_PMOPS NULL

#endif

static struct platform_driver au1xpsc_ac97_driver = {
	.driver	= {
		.name	= "au1xpsc_ac97",
		.pm	= AU1XPSCAC97_PMOPS,
	},
	.probe		= au1xpsc_ac97_drvprobe,
	.remove		= au1xpsc_ac97_drvremove,
};

module_platform_driver(au1xpsc_ac97_driver);

MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Au12x0/Au1550 PSC AC97 ALSA ASoC audio driver");
MODULE_AUTHOR("Manuel Lauss");
Commit	Line	Data
4a161d23 ML	1	/*
	2	* Au12x0/Au1550 PSC ALSA ASoC audio support.
	3	*
cdc65fbe ML	4	* (c) 2007-2009 MSC Vertriebsges.m.b.H.,
cdc65fbe ML	5	* Manuel Lauss <manuel.lauss@gmail.com>
4a161d23 ML	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* Au1xxx-PSC AC97 glue.
	12	*
4a161d23 ML	13	*/
	14
	15	#include <linux/init.h>
	16	#include <linux/module.h>
5a0e3ad6	17	#include <linux/slab.h>
4a161d23 ML	18	#include <linux/device.h>
4a161d23 ML	19	#include <linux/delay.h>
cdc65fbe	20	#include <linux/mutex.h>
4a161d23 ML	21	#include <linux/suspend.h>
	22	#include <sound/core.h>
	23	#include <sound/pcm.h>
	24	#include <sound/initval.h>
	25	#include <sound/soc.h>
	26	#include <asm/mach-au1x00/au1000.h>
	27	#include <asm/mach-au1x00/au1xxx_psc.h>
	28
	29	#include "psc.h"
	30
cdc65fbe ML	31	/* how often to retry failed codec register reads/writes */
	32	#define AC97_RW_RETRIES 5
	33
4a161d23 ML	34	#define AC97_DIR \
	35	(SND_SOC_DAIDIR_PLAYBACK \| SND_SOC_DAIDIR_CAPTURE)
	36
	37	#define AC97_RATES \
	38	SNDRV_PCM_RATE_8000_48000
	39
	40	#define AC97_FMTS \
	41	(SNDRV_PCM_FMTBIT_S16_LE \| SNDRV_PCM_FMTBIT_S20_3BE)
	42
	43	#define AC97PCR_START(stype) \
25942fdc	44	((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_AC97PCR_TS : PSC_AC97PCR_RS)
4a161d23	45	#define AC97PCR_STOP(stype) \
25942fdc	46	((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_AC97PCR_TP : PSC_AC97PCR_RP)
4a161d23	47	#define AC97PCR_CLRFIFO(stype) \
25942fdc	48	((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_AC97PCR_TC : PSC_AC97PCR_RC)
4a161d23	49
cdc65fbe	50	#define AC97STAT_BUSY(stype) \
25942fdc	51	((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_AC97STAT_TB : PSC_AC97STAT_RB)
cdc65fbe	52
4a161d23 ML	53	/* instance data. There can be only one, MacLeod!!!! */
	54	static struct au1xpsc_audio_data *au1xpsc_ac97_workdata;
	55
ffc4fdbb ML	56	#if 0
	57
	58	/* this could theoretically work, but ac97->bus->card->private_data can be NULL
	59	* when snd_ac97_mixer() is called; I don't know if the rest further down the
	60	* chain are always valid either.
	61	*/
	62	static inline struct au1xpsc_audio_data ac97_to_pscdata(struct snd_ac97 x)
	63	{
	64	struct snd_soc_card *c = x->bus->card->private_data;
	65	return snd_soc_dai_get_drvdata(c->rtd->cpu_dai);
	66	}
	67
	68	#else
	69
	70	#define ac97_to_pscdata(x) au1xpsc_ac97_workdata
	71
	72	#endif
	73
4a161d23 ML	74	/* AC97 controller reads codec register */
	75	static unsigned short au1xpsc_ac97_read(struct snd_ac97 *ac97,
	76	unsigned short reg)
	77	{
ffc4fdbb	78	struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97);
e697cd41 ML	79	unsigned short retry, tmo;
e697cd41 ML	80	unsigned long data;
4a161d23	81
2f73bfbe ML	82	__raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
2f73bfbe ML	83	wmb(); /* drain writebuffer */
4a161d23	84
cdc65fbe ML	85	retry = AC97_RW_RETRIES;
	86	do {
	87	mutex_lock(&pscdata->lock);
	88
2f73bfbe	89	__raw_writel(PSC_AC97CDC_RD \| PSC_AC97CDC_INDX(reg),
cdc65fbe	90	AC97_CDC(pscdata));
2f73bfbe	91	wmb(); /* drain writebuffer */
cdc65fbe	92
8d567b6b ML	93	tmo = 20;
	94	do {
	95	udelay(21);
2f73bfbe	96	if (__raw_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)
8d567b6b ML	97	break;
8d567b6b ML	98	} while (--tmo);
4a161d23	99
2f73bfbe	100	data = __raw_readl(AC97_CDC(pscdata));
4a161d23	101
2f73bfbe ML	102	__raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
2f73bfbe ML	103	wmb(); /* drain writebuffer */
cdc65fbe ML	104
cdc65fbe ML	105	mutex_unlock(&pscdata->lock);
e697cd41 ML	106
	107	if (reg != ((data >> 16) & 0x7f))
	108	tmo = 1; /* wrong register, try again */
	109
cdc65fbe	110	} while (--retry && !tmo);
4a161d23	111
e697cd41	112	return retry ? data & 0xffff : 0xffff;
4a161d23 ML	113	}
	114
	115	/* AC97 controller writes to codec register */
	116	static void au1xpsc_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
	117	unsigned short val)
	118	{
ffc4fdbb	119	struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97);
cdc65fbe	120	unsigned int tmo, retry;
4a161d23	121
2f73bfbe ML	122	__raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
2f73bfbe ML	123	wmb(); /* drain writebuffer */
cdc65fbe ML	124
	125	retry = AC97_RW_RETRIES;
	126	do {
	127	mutex_lock(&pscdata->lock);
	128
2f73bfbe	129	__raw_writel(PSC_AC97CDC_INDX(reg) \| (val & 0xffff),
cdc65fbe	130	AC97_CDC(pscdata));
2f73bfbe	131	wmb(); /* drain writebuffer */
4a161d23	132
8d567b6b ML	133	tmo = 20;
	134	do {
	135	udelay(21);
2f73bfbe	136	if (__raw_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)
8d567b6b ML	137	break;
8d567b6b ML	138	} while (--tmo);
cdc65fbe	139
2f73bfbe ML	140	__raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
2f73bfbe ML	141	wmb(); /* drain writebuffer */
cdc65fbe ML	142
	143	mutex_unlock(&pscdata->lock);
	144	} while (--retry && !tmo);
4a161d23 ML	145	}
	146
	147	/* AC97 controller asserts a warm reset */
	148	static void au1xpsc_ac97_warm_reset(struct snd_ac97 *ac97)
	149	{
ffc4fdbb	150	struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97);
4a161d23	151
2f73bfbe ML	152	__raw_writel(PSC_AC97RST_SNC, AC97_RST(pscdata));
2f73bfbe ML	153	wmb(); /* drain writebuffer */
4a161d23	154	msleep(10);
2f73bfbe ML	155	__raw_writel(0, AC97_RST(pscdata));
2f73bfbe ML	156	wmb(); /* drain writebuffer */
4a161d23 ML	157	}
	158
	159	static void au1xpsc_ac97_cold_reset(struct snd_ac97 *ac97)
	160	{
ffc4fdbb	161	struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97);
4a161d23 ML	162	int i;
	163
	164	/* disable PSC during cold reset */
2f73bfbe ML	165	__raw_writel(0, AC97_CFG(au1xpsc_ac97_workdata));
	166	wmb(); /* drain writebuffer */
	167	__raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(pscdata));
	168	wmb(); /* drain writebuffer */
4a161d23 ML	169
4a161d23 ML	170	/* issue cold reset */
2f73bfbe ML	171	__raw_writel(PSC_AC97RST_RST, AC97_RST(pscdata));
2f73bfbe ML	172	wmb(); /* drain writebuffer */
4a161d23	173	msleep(500);
2f73bfbe ML	174	__raw_writel(0, AC97_RST(pscdata));
2f73bfbe ML	175	wmb(); /* drain writebuffer */
4a161d23 ML	176
4a161d23 ML	177	/* enable PSC */
2f73bfbe ML	178	__raw_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata));
2f73bfbe ML	179	wmb(); /* drain writebuffer */
4a161d23 ML	180
4a161d23 ML	181	/* wait for PSC to indicate it's ready */
cdc65fbe	182	i = 1000;
2f73bfbe	183	while (!((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_SR)) && (--i))
cdc65fbe	184	msleep(1);
4a161d23 ML	185
	186	if (i == 0) {
	187	printk(KERN_ERR "au1xpsc-ac97: PSC not ready!\n");
	188	return;
	189	}
	190
	191	/* enable the ac97 function */
2f73bfbe ML	192	__raw_writel(pscdata->cfg \| PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
2f73bfbe ML	193	wmb(); /* drain writebuffer */
4a161d23 ML	194
4a161d23 ML	195	/* wait for AC97 core to become ready */
cdc65fbe	196	i = 1000;
2f73bfbe	197	while (!((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && (--i))
cdc65fbe	198	msleep(1);
4a161d23 ML	199	if (i == 0)
	200	printk(KERN_ERR "au1xpsc-ac97: AC97 ctrl not ready\n");
	201	}
	202
	203	/* AC97 controller operations */
b047e1cc	204	static struct snd_ac97_bus_ops psc_ac97_ops = {
4a161d23 ML	205	.read = au1xpsc_ac97_read,
	206	.write = au1xpsc_ac97_write,
	207	.reset = au1xpsc_ac97_cold_reset,
	208	.warm_reset = au1xpsc_ac97_warm_reset,
	209	};
4a161d23 ML	210
4a161d23 ML	211	static int au1xpsc_ac97_hw_params(struct snd_pcm_substream *substream,
dee89c4d MB	212	struct snd_pcm_hw_params *params,
dee89c4d MB	213	struct snd_soc_dai *dai)
4a161d23	214	{
ffc4fdbb	215	struct au1xpsc_audio_data *pscdata = snd_soc_dai_get_drvdata(dai);
cdc65fbe	216	unsigned long r, ro, stat;
25942fdc	217	int chans, t, stype = substream->stream;
4a161d23 ML	218
	219	chans = params_channels(params);
	220
2f73bfbe ML	221	r = ro = __raw_readl(AC97_CFG(pscdata));
2f73bfbe ML	222	stat = __raw_readl(AC97_STAT(pscdata));
4a161d23 ML	223
	224	/* already active? */
	225	if (stat & (PSC_AC97STAT_TB \| PSC_AC97STAT_RB)) {
	226	/* reject parameters not currently set up */
	227	if ((PSC_AC97CFG_GET_LEN(r) != params->msbits) \|\|
	228	(pscdata->rate != params_rate(params)))
	229	return -EINVAL;
	230	} else {
4a161d23 ML	231
	232	/* set sample bitdepth: REG[24:21]=(BITS-2)/2 */
	233	r &= ~PSC_AC97CFG_LEN_MASK;
	234	r \|= PSC_AC97CFG_SET_LEN(params->msbits);
	235
	236	/* channels: enable slots for front L/R channel */
25942fdc	237	if (stype == SNDRV_PCM_STREAM_PLAYBACK) {
4a161d23 ML	238	r &= ~PSC_AC97CFG_TXSLOT_MASK;
	239	r \|= PSC_AC97CFG_TXSLOT_ENA(3);
	240	r \|= PSC_AC97CFG_TXSLOT_ENA(4);
	241	} else {
	242	r &= ~PSC_AC97CFG_RXSLOT_MASK;
	243	r \|= PSC_AC97CFG_RXSLOT_ENA(3);
	244	r \|= PSC_AC97CFG_RXSLOT_ENA(4);
	245	}
	246
cdc65fbe ML	247	/* do we need to poke the hardware? */
	248	if (!(r ^ ro))
	249	goto out;
	250
	251	/* ac97 engine is about to be disabled */
	252	mutex_lock(&pscdata->lock);
	253
	254	/* disable AC97 device controller first... */
2f73bfbe ML	255	__raw_writel(r & ~PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
2f73bfbe ML	256	wmb(); /* drain writebuffer */
cdc65fbe ML	257
cdc65fbe ML	258	/* ...wait for it... */
8d567b6b	259	t = 100;
2f73bfbe	260	while ((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR) && --t)
8d567b6b ML	261	msleep(1);
	262
	263	if (!t)
	264	printk(KERN_ERR "PSC-AC97: can't disable!\n");
cdc65fbe ML	265
cdc65fbe ML	266	/* ...write config... */
2f73bfbe ML	267	__raw_writel(r, AC97_CFG(pscdata));
2f73bfbe ML	268	wmb(); /* drain writebuffer */
cdc65fbe ML	269
cdc65fbe ML	270	/* ...enable the AC97 controller again... */
2f73bfbe ML	271	__raw_writel(r \| PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
2f73bfbe ML	272	wmb(); /* drain writebuffer */
4a161d23	273
cdc65fbe	274	/* ...and wait for ready bit */
8d567b6b	275	t = 100;
2f73bfbe	276	while ((!(__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && --t)
8d567b6b ML	277	msleep(1);
	278
	279	if (!t)
	280	printk(KERN_ERR "PSC-AC97: can't enable!\n");
cdc65fbe ML	281
	282	mutex_unlock(&pscdata->lock);
	283
4a161d23 ML	284	pscdata->cfg = r;
	285	pscdata->rate = params_rate(params);
	286	}
	287
cdc65fbe	288	out:
4a161d23 ML	289	return 0;
	290	}
	291
	292	static int au1xpsc_ac97_trigger(struct snd_pcm_substream *substream,
dee89c4d	293	int cmd, struct snd_soc_dai *dai)
4a161d23	294	{
ffc4fdbb	295	struct au1xpsc_audio_data *pscdata = snd_soc_dai_get_drvdata(dai);
25942fdc	296	int ret, stype = substream->stream;
4a161d23 ML	297
	298	ret = 0;
	299
	300	switch (cmd) {
	301	case SNDRV_PCM_TRIGGER_START:
	302	case SNDRV_PCM_TRIGGER_RESUME:
2f73bfbe ML	303	__raw_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata));
	304	wmb(); /* drain writebuffer */
	305	__raw_writel(AC97PCR_START(stype), AC97_PCR(pscdata));
	306	wmb(); /* drain writebuffer */
4a161d23 ML	307	break;
	308	case SNDRV_PCM_TRIGGER_STOP:
	309	case SNDRV_PCM_TRIGGER_SUSPEND:
2f73bfbe ML	310	__raw_writel(AC97PCR_STOP(stype), AC97_PCR(pscdata));
2f73bfbe ML	311	wmb(); /* drain writebuffer */
cdc65fbe	312
2f73bfbe	313	while (__raw_readl(AC97_STAT(pscdata)) & AC97STAT_BUSY(stype))
cdc65fbe ML	314	asm volatile ("nop");
cdc65fbe ML	315
2f73bfbe ML	316	__raw_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata));
2f73bfbe ML	317	wmb(); /* drain writebuffer */
cdc65fbe	318
4a161d23 ML	319	break;
	320	default:
	321	ret = -EINVAL;
	322	}
	323	return ret;
	324	}
	325
5b0912be ML	326	static int au1xpsc_ac97_startup(struct snd_pcm_substream *substream,
	327	struct snd_soc_dai *dai)
	328	{
	329	struct au1xpsc_audio_data *pscdata = snd_soc_dai_get_drvdata(dai);
	330	snd_soc_dai_set_dma_data(dai, substream, &pscdata->dmaids[0]);
	331	return 0;
	332	}
	333
f0fba2ad	334	static int au1xpsc_ac97_probe(struct snd_soc_dai *dai)
0f83d639 ML	335	{
	336	return au1xpsc_ac97_workdata ? 0 : -ENODEV;
	337	}
	338
85e7652d	339	static const struct snd_soc_dai_ops au1xpsc_ac97_dai_ops = {
5b0912be	340	.startup = au1xpsc_ac97_startup,
0f83d639 ML	341	.trigger = au1xpsc_ac97_trigger,
	342	.hw_params = au1xpsc_ac97_hw_params,
	343	};
	344
ffc4fdbb	345	static const struct snd_soc_dai_driver au1xpsc_ac97_dai_template = {
bc263214	346	.bus_control = true,
0f83d639	347	.probe = au1xpsc_ac97_probe,
0f83d639 ML	348	.playback = {
	349	.rates = AC97_RATES,
	350	.formats = AC97_FMTS,
	351	.channels_min = 2,
	352	.channels_max = 2,
	353	},
	354	.capture = {
	355	.rates = AC97_RATES,
	356	.formats = AC97_FMTS,
	357	.channels_min = 2,
	358	.channels_max = 2,
	359	},
	360	.ops = &au1xpsc_ac97_dai_ops,
	361	};
0f83d639	362
a4ff200c KM	363	static const struct snd_soc_component_driver au1xpsc_ac97_component = {
	364	.name = "au1xpsc-ac97",
	365	};
	366
5c658be0	367	static int au1xpsc_ac97_drvprobe(struct platform_device *pdev)
4a161d23 ML	368	{
4a161d23 ML	369	int ret;
226d0f22	370	struct resource iores, dmares;
4a161d23	371	unsigned long sel;
0f83d639	372	struct au1xpsc_audio_data *wd;
4a161d23	373
8d9626d7 JL	374	wd = devm_kzalloc(&pdev->dev, sizeof(struct au1xpsc_audio_data),
8d9626d7 JL	375	GFP_KERNEL);
0f83d639	376	if (!wd)
4a161d23 ML	377	return -ENOMEM;
4a161d23 ML	378
0f83d639	379	mutex_init(&wd->lock);
cdc65fbe	380
226d0f22	381	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
a16a6c68 MB	382	wd->mmio = devm_ioremap_resource(&pdev->dev, iores);
	383	if (IS_ERR(wd->mmio))
	384	return PTR_ERR(wd->mmio);
4a161d23	385
226d0f22 JL	386	dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
226d0f22 JL	387	if (!dmares)
8d9626d7	388	return -EBUSY;
226d0f22	389	wd->dmaids[SNDRV_PCM_STREAM_PLAYBACK] = dmares->start;
5b0912be	390
226d0f22 JL	391	dmares = platform_get_resource(pdev, IORESOURCE_DMA, 1);
226d0f22 JL	392	if (!dmares)
8d9626d7	393	return -EBUSY;
226d0f22	394	wd->dmaids[SNDRV_PCM_STREAM_CAPTURE] = dmares->start;
5b0912be	395
4a161d23	396	/* configuration: max dma trigger threshold, enable ac97 */
0f83d639 ML	397	wd->cfg = PSC_AC97CFG_RT_FIFO8 \| PSC_AC97CFG_TT_FIFO8 \|
0f83d639 ML	398	PSC_AC97CFG_DE_ENABLE;
4a161d23	399
0f83d639	400	/* preserve PSC clock source set up by platform */
2f73bfbe ML	401	sel = __raw_readl(PSC_SEL(wd)) & PSC_SEL_CLK_MASK;
	402	__raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
	403	wmb(); /* drain writebuffer */
	404	__raw_writel(0, PSC_SEL(wd));
	405	wmb(); /* drain writebuffer */
	406	__raw_writel(PSC_SEL_PS_AC97MODE \| sel, PSC_SEL(wd));
	407	wmb(); /* drain writebuffer */
4a161d23	408
ffc4fdbb ML	409	/* name the DAI like this device instance ("au1xpsc-ac97.PSCINDEX") */
	410	memcpy(&wd->dai_drv, &au1xpsc_ac97_dai_template,
	411	sizeof(struct snd_soc_dai_driver));
	412	wd->dai_drv.name = dev_name(&pdev->dev);
	413
	414	platform_set_drvdata(pdev, wd);
	415
b047e1cc MB	416	ret = snd_soc_set_ac97_ops(&psc_ac97_ops);
	417	if (ret)
	418	return ret;
	419
a4ff200c KM	420	ret = snd_soc_register_component(&pdev->dev, &au1xpsc_ac97_component,
a4ff200c KM	421	&wd->dai_drv, 1);
0f83d639	422	if (ret)
8d9626d7	423	return ret;
0f83d639	424
5b0912be ML	425	au1xpsc_ac97_workdata = wd;
5b0912be ML	426	return 0;
4a161d23 ML	427	}
4a161d23 ML	428
5c658be0	429	static int au1xpsc_ac97_drvremove(struct platform_device *pdev)
4a161d23	430	{
0f83d639 ML	431	struct au1xpsc_audio_data *wd = platform_get_drvdata(pdev);
0f83d639 ML	432
a4ff200c	433	snd_soc_unregister_component(&pdev->dev);
0f83d639	434
4a161d23	435	/* disable PSC completely */
2f73bfbe ML	436	__raw_writel(0, AC97_CFG(wd));
	437	wmb(); /* drain writebuffer */
	438	__raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
	439	wmb(); /* drain writebuffer */
4a161d23	440
0f83d639 ML	441	au1xpsc_ac97_workdata = NULL; /* MDEV */
	442
	443	return 0;
4a161d23 ML	444	}
4a161d23 ML	445
0f83d639 ML	446	#ifdef CONFIG_PM
0f83d639 ML	447	static int au1xpsc_ac97_drvsuspend(struct device *dev)
4a161d23	448	{
0f83d639 ML	449	struct au1xpsc_audio_data *wd = dev_get_drvdata(dev);
0f83d639 ML	450
4a161d23	451	/* save interesting registers and disable PSC */
2f73bfbe	452	wd->pm[0] = __raw_readl(PSC_SEL(wd));
4a161d23	453
2f73bfbe ML	454	__raw_writel(0, AC97_CFG(wd));
	455	wmb(); /* drain writebuffer */
	456	__raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
	457	wmb(); /* drain writebuffer */
4a161d23 ML	458
	459	return 0;
	460	}
	461
0f83d639	462	static int au1xpsc_ac97_drvresume(struct device *dev)
4a161d23	463	{
0f83d639 ML	464	struct au1xpsc_audio_data *wd = dev_get_drvdata(dev);
0f83d639 ML	465
4a161d23	466	/* restore PSC clock config */
2f73bfbe ML	467	__raw_writel(wd->pm[0] \| PSC_SEL_PS_AC97MODE, PSC_SEL(wd));
2f73bfbe ML	468	wmb(); /* drain writebuffer */
4a161d23 ML	469
	470	/* after this point the ac97 core will cold-reset the codec.
	471	* During cold-reset the PSC is reinitialized and the last
	472	* configuration set up in hw_params() is restored.
	473	*/
	474	return 0;
	475	}
	476
0f83d639 ML	477	static struct dev_pm_ops au1xpscac97_pmops = {
	478	.suspend = au1xpsc_ac97_drvsuspend,
	479	.resume = au1xpsc_ac97_drvresume,
6335d055 EM	480	};
6335d055 EM	481
0f83d639 ML	482	#define AU1XPSCAC97_PMOPS &au1xpscac97_pmops
	483
	484	#else
	485
	486	#define AU1XPSCAC97_PMOPS NULL
	487
	488	#endif
	489
	490	static struct platform_driver au1xpsc_ac97_driver = {
	491	.driver = {
ffc4fdbb	492	.name = "au1xpsc_ac97",
0f83d639	493	.pm = AU1XPSCAC97_PMOPS,
4a161d23	494	},
0f83d639	495	.probe = au1xpsc_ac97_drvprobe,
5c658be0	496	.remove = au1xpsc_ac97_drvremove,
4a161d23	497	};
4a161d23	498
2105d63e	499	module_platform_driver(au1xpsc_ac97_driver);
4a161d23 ML	500
	501	MODULE_LICENSE("GPL");
	502	MODULE_DESCRIPTION("Au12x0/Au1550 PSC AC97 ALSA ASoC audio driver");
0f83d639 ML	503	MODULE_AUTHOR("Manuel Lauss");
0f83d639 ML	504