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c6aeb7de FM |
1 | /* |
2 | * ALSA SoC I2S Audio Layer for Broadcom BCM2835 SoC | |
3 | * | |
4 | * Author: Florian Meier <florian.meier@koalo.de> | |
5 | * Copyright 2013 | |
6 | * | |
7 | * Based on | |
8 | * Raspberry Pi PCM I2S ALSA Driver | |
9 | * Copyright (c) by Phil Poole 2013 | |
10 | * | |
11 | * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor | |
12 | * Vladimir Barinov, <vbarinov@embeddedalley.com> | |
13 | * Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com> | |
14 | * | |
15 | * OMAP ALSA SoC DAI driver using McBSP port | |
16 | * Copyright (C) 2008 Nokia Corporation | |
17 | * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com> | |
18 | * Peter Ujfalusi <peter.ujfalusi@ti.com> | |
19 | * | |
20 | * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver | |
21 | * Author: Timur Tabi <timur@freescale.com> | |
22 | * Copyright 2007-2010 Freescale Semiconductor, Inc. | |
23 | * | |
24 | * This program is free software; you can redistribute it and/or | |
25 | * modify it under the terms of the GNU General Public License | |
26 | * version 2 as published by the Free Software Foundation. | |
27 | * | |
28 | * This program is distributed in the hope that it will be useful, but | |
29 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
30 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
31 | * General Public License for more details. | |
32 | */ | |
33 | ||
7905f082 MS |
34 | #include <linux/clk.h> |
35 | #include <linux/delay.h> | |
36 | #include <linux/device.h> | |
c6aeb7de | 37 | #include <linux/init.h> |
7905f082 | 38 | #include <linux/io.h> |
c6aeb7de | 39 | #include <linux/module.h> |
517e7a15 | 40 | #include <linux/of_address.h> |
c6aeb7de | 41 | #include <linux/slab.h> |
c6aeb7de FM |
42 | |
43 | #include <sound/core.h> | |
7905f082 MS |
44 | #include <sound/dmaengine_pcm.h> |
45 | #include <sound/initval.h> | |
c6aeb7de FM |
46 | #include <sound/pcm.h> |
47 | #include <sound/pcm_params.h> | |
c6aeb7de | 48 | #include <sound/soc.h> |
c6aeb7de | 49 | |
c6aeb7de FM |
50 | /* I2S registers */ |
51 | #define BCM2835_I2S_CS_A_REG 0x00 | |
52 | #define BCM2835_I2S_FIFO_A_REG 0x04 | |
53 | #define BCM2835_I2S_MODE_A_REG 0x08 | |
54 | #define BCM2835_I2S_RXC_A_REG 0x0c | |
55 | #define BCM2835_I2S_TXC_A_REG 0x10 | |
56 | #define BCM2835_I2S_DREQ_A_REG 0x14 | |
57 | #define BCM2835_I2S_INTEN_A_REG 0x18 | |
58 | #define BCM2835_I2S_INTSTC_A_REG 0x1c | |
59 | #define BCM2835_I2S_GRAY_REG 0x20 | |
60 | ||
61 | /* I2S register settings */ | |
62 | #define BCM2835_I2S_STBY BIT(25) | |
63 | #define BCM2835_I2S_SYNC BIT(24) | |
64 | #define BCM2835_I2S_RXSEX BIT(23) | |
65 | #define BCM2835_I2S_RXF BIT(22) | |
66 | #define BCM2835_I2S_TXE BIT(21) | |
67 | #define BCM2835_I2S_RXD BIT(20) | |
68 | #define BCM2835_I2S_TXD BIT(19) | |
69 | #define BCM2835_I2S_RXR BIT(18) | |
70 | #define BCM2835_I2S_TXW BIT(17) | |
71 | #define BCM2835_I2S_CS_RXERR BIT(16) | |
72 | #define BCM2835_I2S_CS_TXERR BIT(15) | |
73 | #define BCM2835_I2S_RXSYNC BIT(14) | |
74 | #define BCM2835_I2S_TXSYNC BIT(13) | |
75 | #define BCM2835_I2S_DMAEN BIT(9) | |
76 | #define BCM2835_I2S_RXTHR(v) ((v) << 7) | |
77 | #define BCM2835_I2S_TXTHR(v) ((v) << 5) | |
78 | #define BCM2835_I2S_RXCLR BIT(4) | |
79 | #define BCM2835_I2S_TXCLR BIT(3) | |
80 | #define BCM2835_I2S_TXON BIT(2) | |
81 | #define BCM2835_I2S_RXON BIT(1) | |
82 | #define BCM2835_I2S_EN (1) | |
83 | ||
84 | #define BCM2835_I2S_CLKDIS BIT(28) | |
85 | #define BCM2835_I2S_PDMN BIT(27) | |
86 | #define BCM2835_I2S_PDME BIT(26) | |
87 | #define BCM2835_I2S_FRXP BIT(25) | |
88 | #define BCM2835_I2S_FTXP BIT(24) | |
89 | #define BCM2835_I2S_CLKM BIT(23) | |
90 | #define BCM2835_I2S_CLKI BIT(22) | |
91 | #define BCM2835_I2S_FSM BIT(21) | |
92 | #define BCM2835_I2S_FSI BIT(20) | |
93 | #define BCM2835_I2S_FLEN(v) ((v) << 10) | |
94 | #define BCM2835_I2S_FSLEN(v) (v) | |
95 | ||
96 | #define BCM2835_I2S_CHWEX BIT(15) | |
97 | #define BCM2835_I2S_CHEN BIT(14) | |
98 | #define BCM2835_I2S_CHPOS(v) ((v) << 4) | |
99 | #define BCM2835_I2S_CHWID(v) (v) | |
100 | #define BCM2835_I2S_CH1(v) ((v) << 16) | |
101 | #define BCM2835_I2S_CH2(v) (v) | |
102 | ||
103 | #define BCM2835_I2S_TX_PANIC(v) ((v) << 24) | |
104 | #define BCM2835_I2S_RX_PANIC(v) ((v) << 16) | |
105 | #define BCM2835_I2S_TX(v) ((v) << 8) | |
106 | #define BCM2835_I2S_RX(v) (v) | |
107 | ||
108 | #define BCM2835_I2S_INT_RXERR BIT(3) | |
109 | #define BCM2835_I2S_INT_TXERR BIT(2) | |
110 | #define BCM2835_I2S_INT_RXR BIT(1) | |
111 | #define BCM2835_I2S_INT_TXW BIT(0) | |
112 | ||
c6aeb7de FM |
113 | /* General device struct */ |
114 | struct bcm2835_i2s_dev { | |
115 | struct device *dev; | |
116 | struct snd_dmaengine_dai_dma_data dma_data[2]; | |
117 | unsigned int fmt; | |
118 | unsigned int bclk_ratio; | |
119 | ||
517e7a15 MS |
120 | struct regmap *i2s_regmap; |
121 | struct clk *clk; | |
122 | bool clk_prepared; | |
c6aeb7de FM |
123 | }; |
124 | ||
125 | static void bcm2835_i2s_start_clock(struct bcm2835_i2s_dev *dev) | |
126 | { | |
c6aeb7de FM |
127 | unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK; |
128 | ||
517e7a15 MS |
129 | if (dev->clk_prepared) |
130 | return; | |
131 | ||
c6aeb7de FM |
132 | switch (master) { |
133 | case SND_SOC_DAIFMT_CBS_CFS: | |
134 | case SND_SOC_DAIFMT_CBS_CFM: | |
517e7a15 MS |
135 | clk_prepare_enable(dev->clk); |
136 | dev->clk_prepared = true; | |
c6aeb7de FM |
137 | break; |
138 | default: | |
139 | break; | |
140 | } | |
141 | } | |
142 | ||
143 | static void bcm2835_i2s_stop_clock(struct bcm2835_i2s_dev *dev) | |
144 | { | |
517e7a15 MS |
145 | if (dev->clk_prepared) |
146 | clk_disable_unprepare(dev->clk); | |
147 | dev->clk_prepared = false; | |
c6aeb7de FM |
148 | } |
149 | ||
150 | static void bcm2835_i2s_clear_fifos(struct bcm2835_i2s_dev *dev, | |
151 | bool tx, bool rx) | |
152 | { | |
153 | int timeout = 1000; | |
154 | uint32_t syncval; | |
155 | uint32_t csreg; | |
156 | uint32_t i2s_active_state; | |
517e7a15 | 157 | bool clk_was_prepared; |
c6aeb7de FM |
158 | uint32_t off; |
159 | uint32_t clr; | |
160 | ||
161 | off = tx ? BCM2835_I2S_TXON : 0; | |
162 | off |= rx ? BCM2835_I2S_RXON : 0; | |
163 | ||
164 | clr = tx ? BCM2835_I2S_TXCLR : 0; | |
165 | clr |= rx ? BCM2835_I2S_RXCLR : 0; | |
166 | ||
167 | /* Backup the current state */ | |
168 | regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &csreg); | |
169 | i2s_active_state = csreg & (BCM2835_I2S_RXON | BCM2835_I2S_TXON); | |
170 | ||
c6aeb7de | 171 | /* Start clock if not running */ |
517e7a15 MS |
172 | clk_was_prepared = dev->clk_prepared; |
173 | if (!clk_was_prepared) | |
174 | bcm2835_i2s_start_clock(dev); | |
c6aeb7de FM |
175 | |
176 | /* Stop I2S module */ | |
177 | regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, off, 0); | |
178 | ||
179 | /* | |
180 | * Clear the FIFOs | |
181 | * Requires at least 2 PCM clock cycles to take effect | |
182 | */ | |
183 | regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, clr, clr); | |
184 | ||
185 | /* Wait for 2 PCM clock cycles */ | |
186 | ||
187 | /* | |
188 | * Toggle the SYNC flag. After 2 PCM clock cycles it can be read back | |
189 | * FIXME: This does not seem to work for slave mode! | |
190 | */ | |
191 | regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &syncval); | |
192 | syncval &= BCM2835_I2S_SYNC; | |
193 | ||
194 | regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, | |
195 | BCM2835_I2S_SYNC, ~syncval); | |
196 | ||
197 | /* Wait for the SYNC flag changing it's state */ | |
198 | while (--timeout) { | |
199 | regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &csreg); | |
200 | if ((csreg & BCM2835_I2S_SYNC) != syncval) | |
201 | break; | |
202 | } | |
203 | ||
204 | if (!timeout) | |
205 | dev_err(dev->dev, "I2S SYNC error!\n"); | |
206 | ||
207 | /* Stop clock if it was not running before */ | |
517e7a15 | 208 | if (!clk_was_prepared) |
c6aeb7de FM |
209 | bcm2835_i2s_stop_clock(dev); |
210 | ||
211 | /* Restore I2S state */ | |
212 | regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, | |
213 | BCM2835_I2S_RXON | BCM2835_I2S_TXON, i2s_active_state); | |
214 | } | |
215 | ||
216 | static int bcm2835_i2s_set_dai_fmt(struct snd_soc_dai *dai, | |
217 | unsigned int fmt) | |
218 | { | |
219 | struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); | |
220 | dev->fmt = fmt; | |
221 | return 0; | |
222 | } | |
223 | ||
224 | static int bcm2835_i2s_set_dai_bclk_ratio(struct snd_soc_dai *dai, | |
225 | unsigned int ratio) | |
226 | { | |
227 | struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); | |
228 | dev->bclk_ratio = ratio; | |
229 | return 0; | |
230 | } | |
231 | ||
232 | static int bcm2835_i2s_hw_params(struct snd_pcm_substream *substream, | |
233 | struct snd_pcm_hw_params *params, | |
234 | struct snd_soc_dai *dai) | |
235 | { | |
236 | struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); | |
c6aeb7de FM |
237 | unsigned int sampling_rate = params_rate(params); |
238 | unsigned int data_length, data_delay, bclk_ratio; | |
239 | unsigned int ch1pos, ch2pos, mode, format; | |
c6aeb7de FM |
240 | uint32_t csreg; |
241 | ||
242 | /* | |
243 | * If a stream is already enabled, | |
244 | * the registers are already set properly. | |
245 | */ | |
246 | regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &csreg); | |
247 | ||
248 | if (csreg & (BCM2835_I2S_TXON | BCM2835_I2S_RXON)) | |
249 | return 0; | |
250 | ||
251 | /* | |
252 | * Adjust the data length according to the format. | |
253 | * We prefill the half frame length with an integer | |
254 | * divider of 2400 as explained at the clock settings. | |
255 | * Maybe it is overwritten there, if the Integer mode | |
256 | * does not apply. | |
257 | */ | |
258 | switch (params_format(params)) { | |
259 | case SNDRV_PCM_FORMAT_S16_LE: | |
260 | data_length = 16; | |
c6aeb7de | 261 | break; |
a34b027d MR |
262 | case SNDRV_PCM_FORMAT_S24_LE: |
263 | data_length = 24; | |
264 | break; | |
c6aeb7de FM |
265 | case SNDRV_PCM_FORMAT_S32_LE: |
266 | data_length = 32; | |
c6aeb7de FM |
267 | break; |
268 | default: | |
269 | return -EINVAL; | |
270 | } | |
271 | ||
272 | /* If bclk_ratio already set, use that one. */ | |
273 | if (dev->bclk_ratio) | |
274 | bclk_ratio = dev->bclk_ratio; | |
517e7a15 MS |
275 | else |
276 | /* otherwise calculate a fitting block ratio */ | |
277 | bclk_ratio = 2 * data_length; | |
c6aeb7de | 278 | |
60507fe1 MR |
279 | /* Clock should only be set up here if CPU is clock master */ |
280 | switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
281 | case SND_SOC_DAIFMT_CBS_CFS: | |
282 | case SND_SOC_DAIFMT_CBS_CFM: | |
283 | clk_set_rate(dev->clk, sampling_rate * bclk_ratio); | |
284 | break; | |
285 | default: | |
286 | break; | |
287 | } | |
c6aeb7de FM |
288 | |
289 | /* Setup the frame format */ | |
290 | format = BCM2835_I2S_CHEN; | |
291 | ||
a34b027d | 292 | if (data_length >= 24) |
c6aeb7de FM |
293 | format |= BCM2835_I2S_CHWEX; |
294 | ||
295 | format |= BCM2835_I2S_CHWID((data_length-8)&0xf); | |
296 | ||
297 | switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
298 | case SND_SOC_DAIFMT_I2S: | |
299 | data_delay = 1; | |
300 | break; | |
301 | default: | |
302 | /* | |
303 | * TODO | |
304 | * Others are possible but are not implemented at the moment. | |
305 | */ | |
306 | dev_err(dev->dev, "%s:bad format\n", __func__); | |
307 | return -EINVAL; | |
308 | } | |
309 | ||
310 | ch1pos = data_delay; | |
311 | ch2pos = bclk_ratio / 2 + data_delay; | |
312 | ||
313 | switch (params_channels(params)) { | |
314 | case 2: | |
315 | format = BCM2835_I2S_CH1(format) | BCM2835_I2S_CH2(format); | |
316 | format |= BCM2835_I2S_CH1(BCM2835_I2S_CHPOS(ch1pos)); | |
317 | format |= BCM2835_I2S_CH2(BCM2835_I2S_CHPOS(ch2pos)); | |
318 | break; | |
319 | default: | |
320 | return -EINVAL; | |
321 | } | |
322 | ||
323 | /* | |
324 | * Set format for both streams. | |
325 | * We cannot set another frame length | |
326 | * (and therefore word length) anyway, | |
327 | * so the format will be the same. | |
328 | */ | |
329 | regmap_write(dev->i2s_regmap, BCM2835_I2S_RXC_A_REG, format); | |
330 | regmap_write(dev->i2s_regmap, BCM2835_I2S_TXC_A_REG, format); | |
331 | ||
332 | /* Setup the I2S mode */ | |
333 | mode = 0; | |
334 | ||
335 | if (data_length <= 16) { | |
336 | /* | |
337 | * Use frame packed mode (2 channels per 32 bit word) | |
338 | * We cannot set another frame length in the second stream | |
339 | * (and therefore word length) anyway, | |
340 | * so the format will be the same. | |
341 | */ | |
342 | mode |= BCM2835_I2S_FTXP | BCM2835_I2S_FRXP; | |
343 | } | |
344 | ||
345 | mode |= BCM2835_I2S_FLEN(bclk_ratio - 1); | |
346 | mode |= BCM2835_I2S_FSLEN(bclk_ratio / 2); | |
347 | ||
348 | /* Master or slave? */ | |
349 | switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
350 | case SND_SOC_DAIFMT_CBS_CFS: | |
351 | /* CPU is master */ | |
352 | break; | |
353 | case SND_SOC_DAIFMT_CBM_CFS: | |
354 | /* | |
355 | * CODEC is bit clock master | |
356 | * CPU is frame master | |
357 | */ | |
358 | mode |= BCM2835_I2S_CLKM; | |
359 | break; | |
360 | case SND_SOC_DAIFMT_CBS_CFM: | |
361 | /* | |
362 | * CODEC is frame master | |
363 | * CPU is bit clock master | |
364 | */ | |
365 | mode |= BCM2835_I2S_FSM; | |
366 | break; | |
367 | case SND_SOC_DAIFMT_CBM_CFM: | |
368 | /* CODEC is master */ | |
369 | mode |= BCM2835_I2S_CLKM; | |
370 | mode |= BCM2835_I2S_FSM; | |
371 | break; | |
372 | default: | |
373 | dev_err(dev->dev, "%s:bad master\n", __func__); | |
374 | return -EINVAL; | |
375 | } | |
376 | ||
377 | /* | |
378 | * Invert clocks? | |
379 | * | |
380 | * The BCM approach seems to be inverted to the classical I2S approach. | |
381 | */ | |
382 | switch (dev->fmt & SND_SOC_DAIFMT_INV_MASK) { | |
383 | case SND_SOC_DAIFMT_NB_NF: | |
384 | /* None. Therefore, both for BCM */ | |
385 | mode |= BCM2835_I2S_CLKI; | |
386 | mode |= BCM2835_I2S_FSI; | |
387 | break; | |
388 | case SND_SOC_DAIFMT_IB_IF: | |
389 | /* Both. Therefore, none for BCM */ | |
390 | break; | |
391 | case SND_SOC_DAIFMT_NB_IF: | |
392 | /* | |
393 | * Invert only frame sync. Therefore, | |
394 | * invert only bit clock for BCM | |
395 | */ | |
396 | mode |= BCM2835_I2S_CLKI; | |
397 | break; | |
398 | case SND_SOC_DAIFMT_IB_NF: | |
399 | /* | |
400 | * Invert only bit clock. Therefore, | |
401 | * invert only frame sync for BCM | |
402 | */ | |
403 | mode |= BCM2835_I2S_FSI; | |
404 | break; | |
405 | default: | |
406 | return -EINVAL; | |
407 | } | |
408 | ||
409 | regmap_write(dev->i2s_regmap, BCM2835_I2S_MODE_A_REG, mode); | |
410 | ||
411 | /* Setup the DMA parameters */ | |
412 | regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, | |
413 | BCM2835_I2S_RXTHR(1) | |
414 | | BCM2835_I2S_TXTHR(1) | |
415 | | BCM2835_I2S_DMAEN, 0xffffffff); | |
416 | ||
417 | regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_DREQ_A_REG, | |
418 | BCM2835_I2S_TX_PANIC(0x10) | |
419 | | BCM2835_I2S_RX_PANIC(0x30) | |
420 | | BCM2835_I2S_TX(0x30) | |
421 | | BCM2835_I2S_RX(0x20), 0xffffffff); | |
422 | ||
423 | /* Clear FIFOs */ | |
424 | bcm2835_i2s_clear_fifos(dev, true, true); | |
425 | ||
426 | return 0; | |
427 | } | |
428 | ||
429 | static int bcm2835_i2s_prepare(struct snd_pcm_substream *substream, | |
430 | struct snd_soc_dai *dai) | |
431 | { | |
432 | struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); | |
433 | uint32_t cs_reg; | |
434 | ||
435 | bcm2835_i2s_start_clock(dev); | |
436 | ||
437 | /* | |
438 | * Clear both FIFOs if the one that should be started | |
439 | * is not empty at the moment. This should only happen | |
440 | * after overrun. Otherwise, hw_params would have cleared | |
441 | * the FIFO. | |
442 | */ | |
443 | regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &cs_reg); | |
444 | ||
445 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK | |
446 | && !(cs_reg & BCM2835_I2S_TXE)) | |
447 | bcm2835_i2s_clear_fifos(dev, true, false); | |
448 | else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE | |
449 | && (cs_reg & BCM2835_I2S_RXD)) | |
450 | bcm2835_i2s_clear_fifos(dev, false, true); | |
451 | ||
452 | return 0; | |
453 | } | |
454 | ||
455 | static void bcm2835_i2s_stop(struct bcm2835_i2s_dev *dev, | |
456 | struct snd_pcm_substream *substream, | |
457 | struct snd_soc_dai *dai) | |
458 | { | |
459 | uint32_t mask; | |
460 | ||
461 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
462 | mask = BCM2835_I2S_RXON; | |
463 | else | |
464 | mask = BCM2835_I2S_TXON; | |
465 | ||
466 | regmap_update_bits(dev->i2s_regmap, | |
467 | BCM2835_I2S_CS_A_REG, mask, 0); | |
468 | ||
469 | /* Stop also the clock when not SND_SOC_DAIFMT_CONT */ | |
470 | if (!dai->active && !(dev->fmt & SND_SOC_DAIFMT_CONT)) | |
471 | bcm2835_i2s_stop_clock(dev); | |
472 | } | |
473 | ||
474 | static int bcm2835_i2s_trigger(struct snd_pcm_substream *substream, int cmd, | |
475 | struct snd_soc_dai *dai) | |
476 | { | |
477 | struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); | |
478 | uint32_t mask; | |
479 | ||
480 | switch (cmd) { | |
481 | case SNDRV_PCM_TRIGGER_START: | |
482 | case SNDRV_PCM_TRIGGER_RESUME: | |
483 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
484 | bcm2835_i2s_start_clock(dev); | |
485 | ||
486 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
487 | mask = BCM2835_I2S_RXON; | |
488 | else | |
489 | mask = BCM2835_I2S_TXON; | |
490 | ||
491 | regmap_update_bits(dev->i2s_regmap, | |
492 | BCM2835_I2S_CS_A_REG, mask, mask); | |
493 | break; | |
494 | ||
495 | case SNDRV_PCM_TRIGGER_STOP: | |
496 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
497 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
498 | bcm2835_i2s_stop(dev, substream, dai); | |
499 | break; | |
500 | default: | |
501 | return -EINVAL; | |
502 | } | |
503 | ||
504 | return 0; | |
505 | } | |
506 | ||
507 | static int bcm2835_i2s_startup(struct snd_pcm_substream *substream, | |
508 | struct snd_soc_dai *dai) | |
509 | { | |
510 | struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); | |
511 | ||
512 | if (dai->active) | |
513 | return 0; | |
514 | ||
515 | /* Should this still be running stop it */ | |
516 | bcm2835_i2s_stop_clock(dev); | |
517 | ||
518 | /* Enable PCM block */ | |
519 | regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, | |
520 | BCM2835_I2S_EN, BCM2835_I2S_EN); | |
521 | ||
522 | /* | |
523 | * Disable STBY. | |
524 | * Requires at least 4 PCM clock cycles to take effect. | |
525 | */ | |
526 | regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, | |
527 | BCM2835_I2S_STBY, BCM2835_I2S_STBY); | |
528 | ||
529 | return 0; | |
530 | } | |
531 | ||
532 | static void bcm2835_i2s_shutdown(struct snd_pcm_substream *substream, | |
533 | struct snd_soc_dai *dai) | |
534 | { | |
535 | struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); | |
536 | ||
537 | bcm2835_i2s_stop(dev, substream, dai); | |
538 | ||
539 | /* If both streams are stopped, disable module and clock */ | |
540 | if (dai->active) | |
541 | return; | |
542 | ||
543 | /* Disable the module */ | |
544 | regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, | |
545 | BCM2835_I2S_EN, 0); | |
546 | ||
547 | /* | |
548 | * Stopping clock is necessary, because stop does | |
549 | * not stop the clock when SND_SOC_DAIFMT_CONT | |
550 | */ | |
551 | bcm2835_i2s_stop_clock(dev); | |
552 | } | |
553 | ||
554 | static const struct snd_soc_dai_ops bcm2835_i2s_dai_ops = { | |
555 | .startup = bcm2835_i2s_startup, | |
556 | .shutdown = bcm2835_i2s_shutdown, | |
557 | .prepare = bcm2835_i2s_prepare, | |
558 | .trigger = bcm2835_i2s_trigger, | |
559 | .hw_params = bcm2835_i2s_hw_params, | |
560 | .set_fmt = bcm2835_i2s_set_dai_fmt, | |
517e7a15 | 561 | .set_bclk_ratio = bcm2835_i2s_set_dai_bclk_ratio, |
c6aeb7de FM |
562 | }; |
563 | ||
564 | static int bcm2835_i2s_dai_probe(struct snd_soc_dai *dai) | |
565 | { | |
566 | struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); | |
567 | ||
568 | snd_soc_dai_init_dma_data(dai, | |
569 | &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK], | |
570 | &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE]); | |
571 | ||
572 | return 0; | |
573 | } | |
574 | ||
575 | static struct snd_soc_dai_driver bcm2835_i2s_dai = { | |
576 | .name = "bcm2835-i2s", | |
577 | .probe = bcm2835_i2s_dai_probe, | |
578 | .playback = { | |
579 | .channels_min = 2, | |
580 | .channels_max = 2, | |
581 | .rates = SNDRV_PCM_RATE_8000_192000, | |
582 | .formats = SNDRV_PCM_FMTBIT_S16_LE | |
a34b027d | 583 | | SNDRV_PCM_FMTBIT_S24_LE |
c6aeb7de FM |
584 | | SNDRV_PCM_FMTBIT_S32_LE |
585 | }, | |
586 | .capture = { | |
587 | .channels_min = 2, | |
588 | .channels_max = 2, | |
589 | .rates = SNDRV_PCM_RATE_8000_192000, | |
590 | .formats = SNDRV_PCM_FMTBIT_S16_LE | |
a34b027d | 591 | | SNDRV_PCM_FMTBIT_S24_LE |
c6aeb7de FM |
592 | | SNDRV_PCM_FMTBIT_S32_LE |
593 | }, | |
594 | .ops = &bcm2835_i2s_dai_ops, | |
595 | .symmetric_rates = 1 | |
596 | }; | |
597 | ||
598 | static bool bcm2835_i2s_volatile_reg(struct device *dev, unsigned int reg) | |
599 | { | |
600 | switch (reg) { | |
601 | case BCM2835_I2S_CS_A_REG: | |
602 | case BCM2835_I2S_FIFO_A_REG: | |
603 | case BCM2835_I2S_INTSTC_A_REG: | |
604 | case BCM2835_I2S_GRAY_REG: | |
605 | return true; | |
606 | default: | |
607 | return false; | |
608 | }; | |
609 | } | |
610 | ||
611 | static bool bcm2835_i2s_precious_reg(struct device *dev, unsigned int reg) | |
612 | { | |
613 | switch (reg) { | |
614 | case BCM2835_I2S_FIFO_A_REG: | |
615 | return true; | |
616 | default: | |
617 | return false; | |
618 | }; | |
619 | } | |
620 | ||
517e7a15 MS |
621 | static const struct regmap_config bcm2835_regmap_config = { |
622 | .reg_bits = 32, | |
623 | .reg_stride = 4, | |
624 | .val_bits = 32, | |
625 | .max_register = BCM2835_I2S_GRAY_REG, | |
626 | .precious_reg = bcm2835_i2s_precious_reg, | |
627 | .volatile_reg = bcm2835_i2s_volatile_reg, | |
628 | .cache_type = REGCACHE_RBTREE, | |
c6aeb7de FM |
629 | }; |
630 | ||
631 | static const struct snd_soc_component_driver bcm2835_i2s_component = { | |
632 | .name = "bcm2835-i2s-comp", | |
633 | }; | |
634 | ||
635 | static int bcm2835_i2s_probe(struct platform_device *pdev) | |
636 | { | |
637 | struct bcm2835_i2s_dev *dev; | |
c6aeb7de | 638 | int ret; |
517e7a15 MS |
639 | struct resource *mem; |
640 | void __iomem *base; | |
641 | const __be32 *addr; | |
642 | dma_addr_t dma_base; | |
c6aeb7de FM |
643 | |
644 | dev = devm_kzalloc(&pdev->dev, sizeof(*dev), | |
645 | GFP_KERNEL); | |
646 | if (!dev) | |
647 | return -ENOMEM; | |
648 | ||
517e7a15 MS |
649 | /* get the clock */ |
650 | dev->clk_prepared = false; | |
651 | dev->clk = devm_clk_get(&pdev->dev, NULL); | |
652 | if (IS_ERR(dev->clk)) { | |
653 | dev_err(&pdev->dev, "could not get clk: %ld\n", | |
654 | PTR_ERR(dev->clk)); | |
655 | return PTR_ERR(dev->clk); | |
656 | } | |
657 | ||
658 | /* Request ioarea */ | |
659 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
660 | base = devm_ioremap_resource(&pdev->dev, mem); | |
661 | if (IS_ERR(base)) | |
662 | return PTR_ERR(base); | |
663 | ||
664 | dev->i2s_regmap = devm_regmap_init_mmio(&pdev->dev, base, | |
665 | &bcm2835_regmap_config); | |
666 | if (IS_ERR(dev->i2s_regmap)) | |
667 | return PTR_ERR(dev->i2s_regmap); | |
668 | ||
669 | /* Set the DMA address - we have to parse DT ourselves */ | |
670 | addr = of_get_address(pdev->dev.of_node, 0, NULL, NULL); | |
671 | if (!addr) { | |
672 | dev_err(&pdev->dev, "could not get DMA-register address\n"); | |
673 | return -EINVAL; | |
674 | } | |
675 | dma_base = be32_to_cpup(addr); | |
c6aeb7de | 676 | |
c6aeb7de | 677 | dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr = |
517e7a15 | 678 | dma_base + BCM2835_I2S_FIFO_A_REG; |
c6aeb7de FM |
679 | |
680 | dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr = | |
517e7a15 | 681 | dma_base + BCM2835_I2S_FIFO_A_REG; |
c6aeb7de FM |
682 | |
683 | /* Set the bus width */ | |
684 | dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr_width = | |
685 | DMA_SLAVE_BUSWIDTH_4_BYTES; | |
686 | dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr_width = | |
687 | DMA_SLAVE_BUSWIDTH_4_BYTES; | |
688 | ||
689 | /* Set burst */ | |
690 | dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].maxburst = 2; | |
691 | dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].maxburst = 2; | |
692 | ||
beff053c MR |
693 | /* |
694 | * Set the PACK flag to enable S16_LE support (2 S16_LE values | |
695 | * packed into 32-bit transfers). | |
696 | */ | |
697 | dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].flags = | |
698 | SND_DMAENGINE_PCM_DAI_FLAG_PACK; | |
699 | dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].flags = | |
700 | SND_DMAENGINE_PCM_DAI_FLAG_PACK; | |
701 | ||
c6aeb7de FM |
702 | /* BCLK ratio - use default */ |
703 | dev->bclk_ratio = 0; | |
704 | ||
705 | /* Store the pdev */ | |
706 | dev->dev = &pdev->dev; | |
707 | dev_set_drvdata(&pdev->dev, dev); | |
708 | ||
709 | ret = devm_snd_soc_register_component(&pdev->dev, | |
710 | &bcm2835_i2s_component, &bcm2835_i2s_dai, 1); | |
711 | if (ret) { | |
712 | dev_err(&pdev->dev, "Could not register DAI: %d\n", ret); | |
713 | return ret; | |
714 | } | |
715 | ||
3990c516 | 716 | ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); |
c6aeb7de FM |
717 | if (ret) { |
718 | dev_err(&pdev->dev, "Could not register PCM: %d\n", ret); | |
719 | return ret; | |
720 | } | |
721 | ||
722 | return 0; | |
723 | } | |
724 | ||
725 | static const struct of_device_id bcm2835_i2s_of_match[] = { | |
726 | { .compatible = "brcm,bcm2835-i2s", }, | |
727 | {}, | |
728 | }; | |
729 | ||
054bc835 LB |
730 | MODULE_DEVICE_TABLE(of, bcm2835_i2s_of_match); |
731 | ||
c6aeb7de FM |
732 | static struct platform_driver bcm2835_i2s_driver = { |
733 | .probe = bcm2835_i2s_probe, | |
c6aeb7de FM |
734 | .driver = { |
735 | .name = "bcm2835-i2s", | |
c6aeb7de FM |
736 | .of_match_table = bcm2835_i2s_of_match, |
737 | }, | |
738 | }; | |
739 | ||
740 | module_platform_driver(bcm2835_i2s_driver); | |
741 | ||
742 | MODULE_ALIAS("platform:bcm2835-i2s"); | |
743 | MODULE_DESCRIPTION("BCM2835 I2S interface"); | |
744 | MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>"); | |
745 | MODULE_LICENSE("GPL v2"); |