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8c9c1983 CC |
1 | /* |
2 | * File: bf5xx_sport.c | |
3 | * Based on: | |
4 | * Author: Roy Huang <roy.huang@analog.com> | |
5 | * | |
6 | * Created: Tue Sep 21 10:52:42 CEST 2004 | |
7 | * Description: | |
8 | * Blackfin SPORT Driver | |
9 | * | |
10 | * Copyright 2004-2007 Analog Devices Inc. | |
11 | * | |
12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or | |
17 | * (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, see the file COPYING, or write | |
26 | * to the Free Software Foundation, Inc., | |
27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
28 | */ | |
29 | ||
30 | #include <linux/kernel.h> | |
31 | #include <linux/slab.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/dma-mapping.h> | |
34 | #include <linux/gpio.h> | |
35 | #include <linux/bug.h> | |
36 | #include <asm/portmux.h> | |
37 | #include <asm/dma.h> | |
38 | #include <asm/blackfin.h> | |
39 | #include <asm/cacheflush.h> | |
40 | ||
41 | #include "bf5xx-sport.h" | |
42 | /* delay between frame sync pulse and first data bit in multichannel mode */ | |
43 | #define FRAME_DELAY (1<<12) | |
44 | ||
45 | struct sport_device *sport_handle; | |
46 | EXPORT_SYMBOL(sport_handle); | |
47 | /* note: multichannel is in units of 8 channels, | |
48 | * tdm_count is # channels NOT / 8 ! */ | |
49 | int sport_set_multichannel(struct sport_device *sport, | |
50 | int tdm_count, u32 mask, int packed) | |
51 | { | |
52 | pr_debug("%s tdm_count=%d mask:0x%08x packed=%d\n", __func__, | |
53 | tdm_count, mask, packed); | |
54 | ||
55 | if ((sport->regs->tcr1 & TSPEN) || (sport->regs->rcr1 & RSPEN)) | |
56 | return -EBUSY; | |
57 | ||
58 | if (tdm_count & 0x7) | |
59 | return -EINVAL; | |
60 | ||
61 | if (tdm_count > 32) | |
62 | return -EINVAL; /* Only support less than 32 channels now */ | |
63 | ||
64 | if (tdm_count) { | |
65 | sport->regs->mcmc1 = ((tdm_count>>3)-1) << 12; | |
66 | sport->regs->mcmc2 = FRAME_DELAY | MCMEN | \ | |
67 | (packed ? (MCDTXPE|MCDRXPE) : 0); | |
68 | ||
69 | sport->regs->mtcs0 = mask; | |
70 | sport->regs->mrcs0 = mask; | |
71 | sport->regs->mtcs1 = 0; | |
72 | sport->regs->mrcs1 = 0; | |
73 | sport->regs->mtcs2 = 0; | |
74 | sport->regs->mrcs2 = 0; | |
75 | sport->regs->mtcs3 = 0; | |
76 | sport->regs->mrcs3 = 0; | |
77 | } else { | |
78 | sport->regs->mcmc1 = 0; | |
79 | sport->regs->mcmc2 = 0; | |
80 | ||
81 | sport->regs->mtcs0 = 0; | |
82 | sport->regs->mrcs0 = 0; | |
83 | } | |
84 | ||
85 | sport->regs->mtcs1 = 0; sport->regs->mtcs2 = 0; sport->regs->mtcs3 = 0; | |
86 | sport->regs->mrcs1 = 0; sport->regs->mrcs2 = 0; sport->regs->mrcs3 = 0; | |
87 | ||
88 | SSYNC(); | |
89 | ||
90 | return 0; | |
91 | } | |
92 | EXPORT_SYMBOL(sport_set_multichannel); | |
93 | ||
94 | int sport_config_rx(struct sport_device *sport, unsigned int rcr1, | |
95 | unsigned int rcr2, unsigned int clkdiv, unsigned int fsdiv) | |
96 | { | |
97 | if ((sport->regs->tcr1 & TSPEN) || (sport->regs->rcr1 & RSPEN)) | |
98 | return -EBUSY; | |
99 | ||
100 | sport->regs->rcr1 = rcr1; | |
101 | sport->regs->rcr2 = rcr2; | |
102 | sport->regs->rclkdiv = clkdiv; | |
103 | sport->regs->rfsdiv = fsdiv; | |
104 | ||
105 | SSYNC(); | |
106 | ||
107 | return 0; | |
108 | } | |
109 | EXPORT_SYMBOL(sport_config_rx); | |
110 | ||
111 | int sport_config_tx(struct sport_device *sport, unsigned int tcr1, | |
112 | unsigned int tcr2, unsigned int clkdiv, unsigned int fsdiv) | |
113 | { | |
114 | if ((sport->regs->tcr1 & TSPEN) || (sport->regs->rcr1 & RSPEN)) | |
115 | return -EBUSY; | |
116 | ||
117 | sport->regs->tcr1 = tcr1; | |
118 | sport->regs->tcr2 = tcr2; | |
119 | sport->regs->tclkdiv = clkdiv; | |
120 | sport->regs->tfsdiv = fsdiv; | |
121 | ||
122 | SSYNC(); | |
123 | ||
124 | return 0; | |
125 | } | |
126 | EXPORT_SYMBOL(sport_config_tx); | |
127 | ||
128 | static void setup_desc(struct dmasg *desc, void *buf, int fragcount, | |
129 | size_t fragsize, unsigned int cfg, | |
130 | unsigned int x_count, unsigned int ycount, size_t wdsize) | |
131 | { | |
132 | ||
133 | int i; | |
134 | ||
135 | for (i = 0; i < fragcount; ++i) { | |
136 | desc[i].next_desc_addr = (unsigned long)&(desc[i + 1]); | |
137 | desc[i].start_addr = (unsigned long)buf + i*fragsize; | |
138 | desc[i].cfg = cfg; | |
139 | desc[i].x_count = x_count; | |
140 | desc[i].x_modify = wdsize; | |
141 | desc[i].y_count = ycount; | |
142 | desc[i].y_modify = wdsize; | |
143 | } | |
144 | ||
145 | /* make circular */ | |
146 | desc[fragcount-1].next_desc_addr = (unsigned long)desc; | |
147 | ||
148 | pr_debug("setup desc: desc0=%p, next0=%lx, desc1=%p," | |
149 | "next1=%lx\nx_count=%x,y_count=%x,addr=0x%lx,cfs=0x%x\n", | |
150 | &(desc[0]), desc[0].next_desc_addr, | |
151 | &(desc[1]), desc[1].next_desc_addr, | |
152 | desc[0].x_count, desc[0].y_count, | |
153 | desc[0].start_addr, desc[0].cfg); | |
154 | } | |
155 | ||
156 | static int sport_start(struct sport_device *sport) | |
157 | { | |
158 | enable_dma(sport->dma_rx_chan); | |
159 | enable_dma(sport->dma_tx_chan); | |
160 | sport->regs->rcr1 |= RSPEN; | |
161 | sport->regs->tcr1 |= TSPEN; | |
162 | SSYNC(); | |
163 | ||
164 | return 0; | |
165 | } | |
166 | ||
167 | static int sport_stop(struct sport_device *sport) | |
168 | { | |
169 | sport->regs->tcr1 &= ~TSPEN; | |
170 | sport->regs->rcr1 &= ~RSPEN; | |
171 | SSYNC(); | |
172 | ||
173 | disable_dma(sport->dma_rx_chan); | |
174 | disable_dma(sport->dma_tx_chan); | |
175 | return 0; | |
176 | } | |
177 | ||
178 | static inline int sport_hook_rx_dummy(struct sport_device *sport) | |
179 | { | |
180 | struct dmasg *desc, temp_desc; | |
181 | unsigned long flags; | |
182 | ||
183 | BUG_ON(sport->dummy_rx_desc == NULL); | |
184 | BUG_ON(sport->curr_rx_desc == sport->dummy_rx_desc); | |
185 | ||
186 | /* Maybe the dummy buffer descriptor ring is damaged */ | |
187 | sport->dummy_rx_desc->next_desc_addr = \ | |
188 | (unsigned long)(sport->dummy_rx_desc+1); | |
189 | ||
190 | local_irq_save(flags); | |
191 | desc = (struct dmasg *)get_dma_next_desc_ptr(sport->dma_rx_chan); | |
192 | /* Copy the descriptor which will be damaged to backup */ | |
193 | temp_desc = *desc; | |
194 | desc->x_count = 0xa; | |
195 | desc->y_count = 0; | |
196 | desc->next_desc_addr = (unsigned long)(sport->dummy_rx_desc); | |
197 | local_irq_restore(flags); | |
198 | /* Waiting for dummy buffer descriptor is already hooked*/ | |
199 | while ((get_dma_curr_desc_ptr(sport->dma_rx_chan) - | |
200 | sizeof(struct dmasg)) != | |
201 | (unsigned long)sport->dummy_rx_desc) | |
202 | ; | |
203 | sport->curr_rx_desc = sport->dummy_rx_desc; | |
204 | /* Restore the damaged descriptor */ | |
205 | *desc = temp_desc; | |
206 | ||
207 | return 0; | |
208 | } | |
209 | ||
210 | static inline int sport_rx_dma_start(struct sport_device *sport, int dummy) | |
211 | { | |
212 | if (dummy) { | |
213 | sport->dummy_rx_desc->next_desc_addr = \ | |
214 | (unsigned long) sport->dummy_rx_desc; | |
215 | sport->curr_rx_desc = sport->dummy_rx_desc; | |
216 | } else | |
217 | sport->curr_rx_desc = sport->dma_rx_desc; | |
218 | ||
219 | set_dma_next_desc_addr(sport->dma_rx_chan, \ | |
220 | (unsigned long)(sport->curr_rx_desc)); | |
221 | set_dma_x_count(sport->dma_rx_chan, 0); | |
222 | set_dma_x_modify(sport->dma_rx_chan, 0); | |
223 | set_dma_config(sport->dma_rx_chan, (DMAFLOW_LARGE | NDSIZE_9 | \ | |
224 | WDSIZE_32 | WNR)); | |
225 | set_dma_curr_addr(sport->dma_rx_chan, sport->curr_rx_desc->start_addr); | |
226 | SSYNC(); | |
227 | ||
228 | return 0; | |
229 | } | |
230 | ||
231 | static inline int sport_tx_dma_start(struct sport_device *sport, int dummy) | |
232 | { | |
233 | if (dummy) { | |
234 | sport->dummy_tx_desc->next_desc_addr = \ | |
235 | (unsigned long) sport->dummy_tx_desc; | |
236 | sport->curr_tx_desc = sport->dummy_tx_desc; | |
237 | } else | |
238 | sport->curr_tx_desc = sport->dma_tx_desc; | |
239 | ||
240 | set_dma_next_desc_addr(sport->dma_tx_chan, \ | |
241 | (unsigned long)(sport->curr_tx_desc)); | |
242 | set_dma_x_count(sport->dma_tx_chan, 0); | |
243 | set_dma_x_modify(sport->dma_tx_chan, 0); | |
244 | set_dma_config(sport->dma_tx_chan, | |
245 | (DMAFLOW_LARGE | NDSIZE_9 | WDSIZE_32)); | |
246 | set_dma_curr_addr(sport->dma_tx_chan, sport->curr_tx_desc->start_addr); | |
247 | SSYNC(); | |
248 | ||
249 | return 0; | |
250 | } | |
251 | ||
252 | int sport_rx_start(struct sport_device *sport) | |
253 | { | |
254 | unsigned long flags; | |
255 | pr_debug("%s enter\n", __func__); | |
256 | if (sport->rx_run) | |
257 | return -EBUSY; | |
258 | if (sport->tx_run) { | |
259 | /* tx is running, rx is not running */ | |
260 | BUG_ON(sport->dma_rx_desc == NULL); | |
261 | BUG_ON(sport->curr_rx_desc != sport->dummy_rx_desc); | |
262 | local_irq_save(flags); | |
263 | while ((get_dma_curr_desc_ptr(sport->dma_rx_chan) - | |
264 | sizeof(struct dmasg)) != | |
265 | (unsigned long)sport->dummy_rx_desc) | |
266 | ; | |
267 | sport->dummy_rx_desc->next_desc_addr = | |
268 | (unsigned long)(sport->dma_rx_desc); | |
269 | local_irq_restore(flags); | |
270 | sport->curr_rx_desc = sport->dma_rx_desc; | |
271 | } else { | |
272 | sport_tx_dma_start(sport, 1); | |
273 | sport_rx_dma_start(sport, 0); | |
274 | sport_start(sport); | |
275 | } | |
276 | ||
277 | sport->rx_run = 1; | |
278 | ||
279 | return 0; | |
280 | } | |
281 | EXPORT_SYMBOL(sport_rx_start); | |
282 | ||
283 | int sport_rx_stop(struct sport_device *sport) | |
284 | { | |
285 | pr_debug("%s enter\n", __func__); | |
286 | ||
287 | if (!sport->rx_run) | |
288 | return 0; | |
289 | if (sport->tx_run) { | |
290 | /* TX dma is still running, hook the dummy buffer */ | |
291 | sport_hook_rx_dummy(sport); | |
292 | } else { | |
293 | /* Both rx and tx dma will be stopped */ | |
294 | sport_stop(sport); | |
295 | sport->curr_rx_desc = NULL; | |
296 | sport->curr_tx_desc = NULL; | |
297 | } | |
298 | ||
299 | sport->rx_run = 0; | |
300 | ||
301 | return 0; | |
302 | } | |
303 | EXPORT_SYMBOL(sport_rx_stop); | |
304 | ||
305 | static inline int sport_hook_tx_dummy(struct sport_device *sport) | |
306 | { | |
307 | struct dmasg *desc, temp_desc; | |
308 | unsigned long flags; | |
309 | ||
310 | BUG_ON(sport->dummy_tx_desc == NULL); | |
311 | BUG_ON(sport->curr_tx_desc == sport->dummy_tx_desc); | |
312 | ||
313 | sport->dummy_tx_desc->next_desc_addr = \ | |
314 | (unsigned long)(sport->dummy_tx_desc+1); | |
315 | ||
316 | /* Shorten the time on last normal descriptor */ | |
317 | local_irq_save(flags); | |
318 | desc = (struct dmasg *)get_dma_next_desc_ptr(sport->dma_tx_chan); | |
319 | /* Store the descriptor which will be damaged */ | |
320 | temp_desc = *desc; | |
321 | desc->x_count = 0xa; | |
322 | desc->y_count = 0; | |
323 | desc->next_desc_addr = (unsigned long)(sport->dummy_tx_desc); | |
324 | local_irq_restore(flags); | |
325 | /* Waiting for dummy buffer descriptor is already hooked*/ | |
326 | while ((get_dma_curr_desc_ptr(sport->dma_tx_chan) - \ | |
327 | sizeof(struct dmasg)) != \ | |
328 | (unsigned long)sport->dummy_tx_desc) | |
329 | ; | |
330 | sport->curr_tx_desc = sport->dummy_tx_desc; | |
331 | /* Restore the damaged descriptor */ | |
332 | *desc = temp_desc; | |
333 | ||
334 | return 0; | |
335 | } | |
336 | ||
337 | int sport_tx_start(struct sport_device *sport) | |
338 | { | |
339 | unsigned flags; | |
340 | pr_debug("%s: tx_run:%d, rx_run:%d\n", __func__, | |
341 | sport->tx_run, sport->rx_run); | |
342 | if (sport->tx_run) | |
343 | return -EBUSY; | |
344 | if (sport->rx_run) { | |
345 | BUG_ON(sport->dma_tx_desc == NULL); | |
346 | BUG_ON(sport->curr_tx_desc != sport->dummy_tx_desc); | |
347 | /* Hook the normal buffer descriptor */ | |
348 | local_irq_save(flags); | |
349 | while ((get_dma_curr_desc_ptr(sport->dma_tx_chan) - | |
350 | sizeof(struct dmasg)) != | |
351 | (unsigned long)sport->dummy_tx_desc) | |
352 | ; | |
353 | sport->dummy_tx_desc->next_desc_addr = | |
354 | (unsigned long)(sport->dma_tx_desc); | |
355 | local_irq_restore(flags); | |
356 | sport->curr_tx_desc = sport->dma_tx_desc; | |
357 | } else { | |
358 | ||
359 | sport_tx_dma_start(sport, 0); | |
360 | /* Let rx dma run the dummy buffer */ | |
361 | sport_rx_dma_start(sport, 1); | |
362 | sport_start(sport); | |
363 | } | |
364 | sport->tx_run = 1; | |
365 | return 0; | |
366 | } | |
367 | EXPORT_SYMBOL(sport_tx_start); | |
368 | ||
369 | int sport_tx_stop(struct sport_device *sport) | |
370 | { | |
371 | if (!sport->tx_run) | |
372 | return 0; | |
373 | if (sport->rx_run) { | |
374 | /* RX is still running, hook the dummy buffer */ | |
375 | sport_hook_tx_dummy(sport); | |
376 | } else { | |
377 | /* Both rx and tx dma stopped */ | |
378 | sport_stop(sport); | |
379 | sport->curr_rx_desc = NULL; | |
380 | sport->curr_tx_desc = NULL; | |
381 | } | |
382 | ||
383 | sport->tx_run = 0; | |
384 | ||
385 | return 0; | |
386 | } | |
387 | EXPORT_SYMBOL(sport_tx_stop); | |
388 | ||
389 | static inline int compute_wdsize(size_t wdsize) | |
390 | { | |
391 | switch (wdsize) { | |
392 | case 1: | |
393 | return WDSIZE_8; | |
394 | case 2: | |
395 | return WDSIZE_16; | |
396 | case 4: | |
397 | default: | |
398 | return WDSIZE_32; | |
399 | } | |
400 | } | |
401 | ||
402 | int sport_config_rx_dma(struct sport_device *sport, void *buf, | |
403 | int fragcount, size_t fragsize) | |
404 | { | |
405 | unsigned int x_count; | |
406 | unsigned int y_count; | |
407 | unsigned int cfg; | |
408 | dma_addr_t addr; | |
409 | ||
410 | pr_debug("%s buf:%p, frag:%d, fragsize:0x%lx\n", __func__, \ | |
411 | buf, fragcount, fragsize); | |
412 | ||
413 | x_count = fragsize / sport->wdsize; | |
414 | y_count = 0; | |
415 | ||
416 | /* for fragments larger than 64k words we use 2d dma, | |
417 | * denote fragecount as two numbers' mutliply and both of them | |
418 | * are less than 64k.*/ | |
419 | if (x_count >= 0x10000) { | |
420 | int i, count = x_count; | |
421 | ||
422 | for (i = 16; i > 0; i--) { | |
423 | x_count = 1 << i; | |
424 | if ((count & (x_count - 1)) == 0) { | |
425 | y_count = count >> i; | |
426 | if (y_count < 0x10000) | |
427 | break; | |
428 | } | |
429 | } | |
430 | if (i == 0) | |
431 | return -EINVAL; | |
432 | } | |
433 | pr_debug("%s(x_count:0x%x, y_count:0x%x)\n", __func__, | |
434 | x_count, y_count); | |
435 | ||
436 | if (sport->dma_rx_desc) | |
437 | dma_free_coherent(NULL, sport->rx_desc_bytes, | |
438 | sport->dma_rx_desc, 0); | |
439 | ||
440 | /* Allocate a new descritor ring as current one. */ | |
441 | sport->dma_rx_desc = dma_alloc_coherent(NULL, \ | |
442 | fragcount * sizeof(struct dmasg), &addr, 0); | |
443 | sport->rx_desc_bytes = fragcount * sizeof(struct dmasg); | |
444 | ||
445 | if (!sport->dma_rx_desc) { | |
446 | pr_err("Failed to allocate memory for rx desc\n"); | |
447 | return -ENOMEM; | |
448 | } | |
449 | ||
450 | sport->rx_buf = buf; | |
451 | sport->rx_fragsize = fragsize; | |
452 | sport->rx_frags = fragcount; | |
453 | ||
454 | cfg = 0x7000 | DI_EN | compute_wdsize(sport->wdsize) | WNR | \ | |
455 | (DESC_ELEMENT_COUNT << 8); /* large descriptor mode */ | |
456 | ||
457 | if (y_count != 0) | |
458 | cfg |= DMA2D; | |
459 | ||
460 | setup_desc(sport->dma_rx_desc, buf, fragcount, fragsize, | |
461 | cfg|DMAEN, x_count, y_count, sport->wdsize); | |
462 | ||
463 | return 0; | |
464 | } | |
465 | EXPORT_SYMBOL(sport_config_rx_dma); | |
466 | ||
467 | int sport_config_tx_dma(struct sport_device *sport, void *buf, \ | |
468 | int fragcount, size_t fragsize) | |
469 | { | |
470 | unsigned int x_count; | |
471 | unsigned int y_count; | |
472 | unsigned int cfg; | |
473 | dma_addr_t addr; | |
474 | ||
475 | pr_debug("%s buf:%p, fragcount:%d, fragsize:0x%lx\n", | |
476 | __func__, buf, fragcount, fragsize); | |
477 | ||
478 | x_count = fragsize/sport->wdsize; | |
479 | y_count = 0; | |
480 | ||
481 | /* for fragments larger than 64k words we use 2d dma, | |
482 | * denote fragecount as two numbers' mutliply and both of them | |
483 | * are less than 64k.*/ | |
484 | if (x_count >= 0x10000) { | |
485 | int i, count = x_count; | |
486 | ||
487 | for (i = 16; i > 0; i--) { | |
488 | x_count = 1 << i; | |
489 | if ((count & (x_count - 1)) == 0) { | |
490 | y_count = count >> i; | |
491 | if (y_count < 0x10000) | |
492 | break; | |
493 | } | |
494 | } | |
495 | if (i == 0) | |
496 | return -EINVAL; | |
497 | } | |
498 | pr_debug("%s x_count:0x%x, y_count:0x%x\n", __func__, | |
499 | x_count, y_count); | |
500 | ||
501 | ||
502 | if (sport->dma_tx_desc) { | |
503 | dma_free_coherent(NULL, sport->tx_desc_bytes, \ | |
504 | sport->dma_tx_desc, 0); | |
505 | } | |
506 | ||
507 | sport->dma_tx_desc = dma_alloc_coherent(NULL, \ | |
508 | fragcount * sizeof(struct dmasg), &addr, 0); | |
509 | sport->tx_desc_bytes = fragcount * sizeof(struct dmasg); | |
510 | if (!sport->dma_tx_desc) { | |
511 | pr_err("Failed to allocate memory for tx desc\n"); | |
512 | return -ENOMEM; | |
513 | } | |
514 | ||
515 | sport->tx_buf = buf; | |
516 | sport->tx_fragsize = fragsize; | |
517 | sport->tx_frags = fragcount; | |
518 | cfg = 0x7000 | DI_EN | compute_wdsize(sport->wdsize) | \ | |
519 | (DESC_ELEMENT_COUNT << 8); /* large descriptor mode */ | |
520 | ||
521 | if (y_count != 0) | |
522 | cfg |= DMA2D; | |
523 | ||
524 | setup_desc(sport->dma_tx_desc, buf, fragcount, fragsize, | |
525 | cfg|DMAEN, x_count, y_count, sport->wdsize); | |
526 | ||
527 | return 0; | |
528 | } | |
529 | EXPORT_SYMBOL(sport_config_tx_dma); | |
530 | ||
531 | /* setup dummy dma descriptor ring, which don't generate interrupts, | |
532 | * the x_modify is set to 0 */ | |
533 | static int sport_config_rx_dummy(struct sport_device *sport) | |
534 | { | |
535 | struct dmasg *desc; | |
536 | unsigned config; | |
537 | ||
538 | pr_debug("%s entered\n", __func__); | |
539 | #if L1_DATA_A_LENGTH != 0 | |
540 | desc = (struct dmasg *) l1_data_sram_alloc(2 * sizeof(*desc)); | |
541 | #else | |
542 | { | |
543 | dma_addr_t addr; | |
544 | desc = dma_alloc_coherent(NULL, 2 * sizeof(*desc), &addr, 0); | |
545 | } | |
546 | #endif | |
547 | if (desc == NULL) { | |
548 | pr_err("Failed to allocate memory for dummy rx desc\n"); | |
549 | return -ENOMEM; | |
550 | } | |
551 | memset(desc, 0, 2 * sizeof(*desc)); | |
552 | sport->dummy_rx_desc = desc; | |
553 | desc->start_addr = (unsigned long)sport->dummy_buf; | |
554 | config = DMAFLOW_LARGE | NDSIZE_9 | compute_wdsize(sport->wdsize) | |
555 | | WNR | DMAEN; | |
556 | desc->cfg = config; | |
557 | desc->x_count = sport->dummy_count/sport->wdsize; | |
558 | desc->x_modify = sport->wdsize; | |
559 | desc->y_count = 0; | |
560 | desc->y_modify = 0; | |
561 | memcpy(desc+1, desc, sizeof(*desc)); | |
562 | desc->next_desc_addr = (unsigned long)(desc+1); | |
563 | desc[1].next_desc_addr = (unsigned long)desc; | |
564 | return 0; | |
565 | } | |
566 | ||
567 | static int sport_config_tx_dummy(struct sport_device *sport) | |
568 | { | |
569 | struct dmasg *desc; | |
570 | unsigned int config; | |
571 | ||
572 | pr_debug("%s entered\n", __func__); | |
573 | ||
574 | #if L1_DATA_A_LENGTH != 0 | |
575 | desc = (struct dmasg *) l1_data_sram_alloc(2 * sizeof(*desc)); | |
576 | #else | |
577 | { | |
578 | dma_addr_t addr; | |
579 | desc = dma_alloc_coherent(NULL, 2 * sizeof(*desc), &addr, 0); | |
580 | } | |
581 | #endif | |
582 | if (!desc) { | |
583 | pr_err("Failed to allocate memory for dummy tx desc\n"); | |
584 | return -ENOMEM; | |
585 | } | |
586 | memset(desc, 0, 2 * sizeof(*desc)); | |
587 | sport->dummy_tx_desc = desc; | |
588 | desc->start_addr = (unsigned long)sport->dummy_buf + \ | |
589 | sport->dummy_count; | |
590 | config = DMAFLOW_LARGE | NDSIZE_9 | | |
591 | compute_wdsize(sport->wdsize) | DMAEN; | |
592 | desc->cfg = config; | |
593 | desc->x_count = sport->dummy_count/sport->wdsize; | |
594 | desc->x_modify = sport->wdsize; | |
595 | desc->y_count = 0; | |
596 | desc->y_modify = 0; | |
597 | memcpy(desc+1, desc, sizeof(*desc)); | |
598 | desc->next_desc_addr = (unsigned long)(desc+1); | |
599 | desc[1].next_desc_addr = (unsigned long)desc; | |
600 | return 0; | |
601 | } | |
602 | ||
603 | unsigned long sport_curr_offset_rx(struct sport_device *sport) | |
604 | { | |
605 | unsigned long curr = get_dma_curr_addr(sport->dma_rx_chan); | |
606 | ||
607 | return (unsigned char *)curr - sport->rx_buf; | |
608 | } | |
609 | EXPORT_SYMBOL(sport_curr_offset_rx); | |
610 | ||
611 | unsigned long sport_curr_offset_tx(struct sport_device *sport) | |
612 | { | |
613 | unsigned long curr = get_dma_curr_addr(sport->dma_tx_chan); | |
614 | ||
615 | return (unsigned char *)curr - sport->tx_buf; | |
616 | } | |
617 | EXPORT_SYMBOL(sport_curr_offset_tx); | |
618 | ||
619 | void sport_incfrag(struct sport_device *sport, int *frag, int tx) | |
620 | { | |
621 | ++(*frag); | |
622 | if (tx == 1 && *frag == sport->tx_frags) | |
623 | *frag = 0; | |
624 | ||
625 | if (tx == 0 && *frag == sport->rx_frags) | |
626 | *frag = 0; | |
627 | } | |
628 | EXPORT_SYMBOL(sport_incfrag); | |
629 | ||
630 | void sport_decfrag(struct sport_device *sport, int *frag, int tx) | |
631 | { | |
632 | --(*frag); | |
633 | if (tx == 1 && *frag == 0) | |
634 | *frag = sport->tx_frags; | |
635 | ||
636 | if (tx == 0 && *frag == 0) | |
637 | *frag = sport->rx_frags; | |
638 | } | |
639 | EXPORT_SYMBOL(sport_decfrag); | |
640 | ||
641 | static int sport_check_status(struct sport_device *sport, | |
642 | unsigned int *sport_stat, | |
643 | unsigned int *rx_stat, | |
644 | unsigned int *tx_stat) | |
645 | { | |
646 | int status = 0; | |
647 | ||
648 | if (sport_stat) { | |
649 | SSYNC(); | |
650 | status = sport->regs->stat; | |
651 | if (status & (TOVF|TUVF|ROVF|RUVF)) | |
652 | sport->regs->stat = (status & (TOVF|TUVF|ROVF|RUVF)); | |
653 | SSYNC(); | |
654 | *sport_stat = status; | |
655 | } | |
656 | ||
657 | if (rx_stat) { | |
658 | SSYNC(); | |
659 | status = get_dma_curr_irqstat(sport->dma_rx_chan); | |
660 | if (status & (DMA_DONE|DMA_ERR)) | |
661 | clear_dma_irqstat(sport->dma_rx_chan); | |
662 | SSYNC(); | |
663 | *rx_stat = status; | |
664 | } | |
665 | ||
666 | if (tx_stat) { | |
667 | SSYNC(); | |
668 | status = get_dma_curr_irqstat(sport->dma_tx_chan); | |
669 | if (status & (DMA_DONE|DMA_ERR)) | |
670 | clear_dma_irqstat(sport->dma_tx_chan); | |
671 | SSYNC(); | |
672 | *tx_stat = status; | |
673 | } | |
674 | ||
675 | return 0; | |
676 | } | |
677 | ||
678 | int sport_dump_stat(struct sport_device *sport, char *buf, size_t len) | |
679 | { | |
680 | int ret; | |
681 | ||
682 | ret = snprintf(buf, len, | |
683 | "sts: 0x%04x\n" | |
684 | "rx dma %d sts: 0x%04x tx dma %d sts: 0x%04x\n", | |
685 | sport->regs->stat, | |
686 | sport->dma_rx_chan, | |
687 | get_dma_curr_irqstat(sport->dma_rx_chan), | |
688 | sport->dma_tx_chan, | |
689 | get_dma_curr_irqstat(sport->dma_tx_chan)); | |
690 | buf += ret; | |
691 | len -= ret; | |
692 | ||
693 | ret += snprintf(buf, len, | |
694 | "curr_rx_desc:0x%p, curr_tx_desc:0x%p\n" | |
695 | "dma_rx_desc:0x%p, dma_tx_desc:0x%p\n" | |
696 | "dummy_rx_desc:0x%p, dummy_tx_desc:0x%p\n", | |
697 | sport->curr_rx_desc, sport->curr_tx_desc, | |
698 | sport->dma_rx_desc, sport->dma_tx_desc, | |
699 | sport->dummy_rx_desc, sport->dummy_tx_desc); | |
700 | ||
701 | return ret; | |
702 | } | |
703 | ||
704 | static irqreturn_t rx_handler(int irq, void *dev_id) | |
705 | { | |
706 | unsigned int rx_stat; | |
707 | struct sport_device *sport = dev_id; | |
708 | ||
709 | pr_debug("%s enter\n", __func__); | |
710 | sport_check_status(sport, NULL, &rx_stat, NULL); | |
711 | if (!(rx_stat & DMA_DONE)) | |
712 | pr_err("rx dma is already stopped\n"); | |
713 | ||
714 | if (sport->rx_callback) { | |
715 | sport->rx_callback(sport->rx_data); | |
716 | return IRQ_HANDLED; | |
717 | } | |
718 | ||
719 | return IRQ_NONE; | |
720 | } | |
721 | ||
722 | static irqreturn_t tx_handler(int irq, void *dev_id) | |
723 | { | |
724 | unsigned int tx_stat; | |
725 | struct sport_device *sport = dev_id; | |
726 | pr_debug("%s enter\n", __func__); | |
727 | sport_check_status(sport, NULL, NULL, &tx_stat); | |
728 | if (!(tx_stat & DMA_DONE)) { | |
729 | pr_err("tx dma is already stopped\n"); | |
730 | return IRQ_HANDLED; | |
731 | } | |
732 | if (sport->tx_callback) { | |
733 | sport->tx_callback(sport->tx_data); | |
734 | return IRQ_HANDLED; | |
735 | } | |
736 | ||
737 | return IRQ_NONE; | |
738 | } | |
739 | ||
740 | static irqreturn_t err_handler(int irq, void *dev_id) | |
741 | { | |
742 | unsigned int status = 0; | |
743 | struct sport_device *sport = dev_id; | |
744 | ||
745 | pr_debug("%s\n", __func__); | |
746 | if (sport_check_status(sport, &status, NULL, NULL)) { | |
747 | pr_err("error checking status ??"); | |
748 | return IRQ_NONE; | |
749 | } | |
750 | ||
751 | if (status & (TOVF|TUVF|ROVF|RUVF)) { | |
752 | pr_info("sport status error:%s%s%s%s\n", | |
753 | status & TOVF ? " TOVF" : "", | |
754 | status & TUVF ? " TUVF" : "", | |
755 | status & ROVF ? " ROVF" : "", | |
756 | status & RUVF ? " RUVF" : ""); | |
757 | if (status & TOVF || status & TUVF) { | |
758 | disable_dma(sport->dma_tx_chan); | |
759 | if (sport->tx_run) | |
760 | sport_tx_dma_start(sport, 0); | |
761 | else | |
762 | sport_tx_dma_start(sport, 1); | |
763 | enable_dma(sport->dma_tx_chan); | |
764 | } else { | |
765 | disable_dma(sport->dma_rx_chan); | |
766 | if (sport->rx_run) | |
767 | sport_rx_dma_start(sport, 0); | |
768 | else | |
769 | sport_rx_dma_start(sport, 1); | |
770 | enable_dma(sport->dma_rx_chan); | |
771 | } | |
772 | } | |
773 | status = sport->regs->stat; | |
774 | if (status & (TOVF|TUVF|ROVF|RUVF)) | |
775 | sport->regs->stat = (status & (TOVF|TUVF|ROVF|RUVF)); | |
776 | SSYNC(); | |
777 | ||
778 | if (sport->err_callback) | |
779 | sport->err_callback(sport->err_data); | |
780 | ||
781 | return IRQ_HANDLED; | |
782 | } | |
783 | ||
784 | int sport_set_rx_callback(struct sport_device *sport, | |
785 | void (*rx_callback)(void *), void *rx_data) | |
786 | { | |
787 | BUG_ON(rx_callback == NULL); | |
788 | sport->rx_callback = rx_callback; | |
789 | sport->rx_data = rx_data; | |
790 | ||
791 | return 0; | |
792 | } | |
793 | EXPORT_SYMBOL(sport_set_rx_callback); | |
794 | ||
795 | int sport_set_tx_callback(struct sport_device *sport, | |
796 | void (*tx_callback)(void *), void *tx_data) | |
797 | { | |
798 | BUG_ON(tx_callback == NULL); | |
799 | sport->tx_callback = tx_callback; | |
800 | sport->tx_data = tx_data; | |
801 | ||
802 | return 0; | |
803 | } | |
804 | EXPORT_SYMBOL(sport_set_tx_callback); | |
805 | ||
806 | int sport_set_err_callback(struct sport_device *sport, | |
807 | void (*err_callback)(void *), void *err_data) | |
808 | { | |
809 | BUG_ON(err_callback == NULL); | |
810 | sport->err_callback = err_callback; | |
811 | sport->err_data = err_data; | |
812 | ||
813 | return 0; | |
814 | } | |
815 | EXPORT_SYMBOL(sport_set_err_callback); | |
816 | ||
817 | struct sport_device *sport_init(struct sport_param *param, unsigned wdsize, | |
818 | unsigned dummy_count, void *private_data) | |
819 | { | |
820 | int ret; | |
821 | struct sport_device *sport; | |
822 | pr_debug("%s enter\n", __func__); | |
823 | BUG_ON(param == NULL); | |
824 | BUG_ON(wdsize == 0 || dummy_count == 0); | |
825 | sport = kmalloc(sizeof(struct sport_device), GFP_KERNEL); | |
826 | if (!sport) { | |
827 | pr_err("Failed to allocate for sport device\n"); | |
828 | return NULL; | |
829 | } | |
830 | ||
831 | memset(sport, 0, sizeof(struct sport_device)); | |
832 | sport->dma_rx_chan = param->dma_rx_chan; | |
833 | sport->dma_tx_chan = param->dma_tx_chan; | |
834 | sport->err_irq = param->err_irq; | |
835 | sport->regs = param->regs; | |
836 | sport->private_data = private_data; | |
837 | ||
838 | if (request_dma(sport->dma_rx_chan, "SPORT RX Data") == -EBUSY) { | |
839 | pr_err("Failed to request RX dma %d\n", \ | |
840 | sport->dma_rx_chan); | |
841 | goto __init_err1; | |
842 | } | |
843 | if (set_dma_callback(sport->dma_rx_chan, rx_handler, sport) != 0) { | |
844 | pr_err("Failed to request RX irq %d\n", \ | |
845 | sport->dma_rx_chan); | |
846 | goto __init_err2; | |
847 | } | |
848 | ||
849 | if (request_dma(sport->dma_tx_chan, "SPORT TX Data") == -EBUSY) { | |
850 | pr_err("Failed to request TX dma %d\n", \ | |
851 | sport->dma_tx_chan); | |
852 | goto __init_err2; | |
853 | } | |
854 | ||
855 | if (set_dma_callback(sport->dma_tx_chan, tx_handler, sport) != 0) { | |
856 | pr_err("Failed to request TX irq %d\n", \ | |
857 | sport->dma_tx_chan); | |
858 | goto __init_err3; | |
859 | } | |
860 | ||
861 | if (request_irq(sport->err_irq, err_handler, IRQF_SHARED, "SPORT err", | |
862 | sport) < 0) { | |
863 | pr_err("Failed to request err irq:%d\n", \ | |
864 | sport->err_irq); | |
865 | goto __init_err3; | |
866 | } | |
867 | ||
868 | pr_err("dma rx:%d tx:%d, err irq:%d, regs:%p\n", | |
869 | sport->dma_rx_chan, sport->dma_tx_chan, | |
870 | sport->err_irq, sport->regs); | |
871 | ||
872 | sport->wdsize = wdsize; | |
873 | sport->dummy_count = dummy_count; | |
874 | ||
875 | #if L1_DATA_A_LENGTH != 0 | |
876 | sport->dummy_buf = l1_data_sram_alloc(dummy_count * 2); | |
877 | #else | |
878 | sport->dummy_buf = kmalloc(dummy_count * 2, GFP_KERNEL); | |
879 | #endif | |
880 | if (sport->dummy_buf == NULL) { | |
881 | pr_err("Failed to allocate dummy buffer\n"); | |
882 | goto __error; | |
883 | } | |
884 | ||
885 | memset(sport->dummy_buf, 0, dummy_count * 2); | |
886 | ret = sport_config_rx_dummy(sport); | |
887 | if (ret) { | |
888 | pr_err("Failed to config rx dummy ring\n"); | |
889 | goto __error; | |
890 | } | |
891 | ret = sport_config_tx_dummy(sport); | |
892 | if (ret) { | |
893 | pr_err("Failed to config tx dummy ring\n"); | |
894 | goto __error; | |
895 | } | |
896 | ||
897 | return sport; | |
898 | __error: | |
899 | free_irq(sport->err_irq, sport); | |
900 | __init_err3: | |
901 | free_dma(sport->dma_tx_chan); | |
902 | __init_err2: | |
903 | free_dma(sport->dma_rx_chan); | |
904 | __init_err1: | |
905 | kfree(sport); | |
906 | return NULL; | |
907 | } | |
908 | EXPORT_SYMBOL(sport_init); | |
909 | ||
910 | void sport_done(struct sport_device *sport) | |
911 | { | |
912 | if (sport == NULL) | |
913 | return; | |
914 | ||
915 | sport_stop(sport); | |
916 | if (sport->dma_rx_desc) | |
917 | dma_free_coherent(NULL, sport->rx_desc_bytes, | |
918 | sport->dma_rx_desc, 0); | |
919 | if (sport->dma_tx_desc) | |
920 | dma_free_coherent(NULL, sport->tx_desc_bytes, | |
921 | sport->dma_tx_desc, 0); | |
922 | ||
923 | #if L1_DATA_A_LENGTH != 0 | |
924 | l1_data_sram_free(sport->dummy_rx_desc); | |
925 | l1_data_sram_free(sport->dummy_tx_desc); | |
926 | l1_data_sram_free(sport->dummy_buf); | |
927 | #else | |
928 | dma_free_coherent(NULL, 2*sizeof(struct dmasg), | |
929 | sport->dummy_rx_desc, 0); | |
930 | dma_free_coherent(NULL, 2*sizeof(struct dmasg), | |
931 | sport->dummy_tx_desc, 0); | |
932 | kfree(sport->dummy_buf); | |
933 | #endif | |
934 | free_dma(sport->dma_rx_chan); | |
935 | free_dma(sport->dma_tx_chan); | |
936 | free_irq(sport->err_irq, sport); | |
937 | ||
938 | kfree(sport); | |
939 | sport = NULL; | |
940 | } | |
941 | EXPORT_SYMBOL(sport_done); | |
942 | /* | |
943 | * It is only used to send several bytes when dma is not enabled | |
944 | * sport controller is configured but not enabled. | |
945 | * Multichannel cannot works with pio mode */ | |
946 | /* Used by ac97 to write and read codec register */ | |
947 | int sport_send_and_recv(struct sport_device *sport, u8 *out_data, \ | |
948 | u8 *in_data, int len) | |
949 | { | |
950 | unsigned short dma_config; | |
951 | unsigned short status; | |
952 | unsigned long flags; | |
953 | unsigned long wait = 0; | |
954 | ||
955 | pr_debug("%s enter, out_data:%p, in_data:%p len:%d\n", \ | |
956 | __func__, out_data, in_data, len); | |
957 | pr_debug("tcr1:0x%04x, tcr2:0x%04x, tclkdiv:0x%04x, tfsdiv:0x%04x\n" | |
958 | "mcmc1:0x%04x, mcmc2:0x%04x\n", | |
959 | sport->regs->tcr1, sport->regs->tcr2, | |
960 | sport->regs->tclkdiv, sport->regs->tfsdiv, | |
961 | sport->regs->mcmc1, sport->regs->mcmc2); | |
962 | flush_dcache_range((unsigned)out_data, (unsigned)(out_data + len)); | |
963 | ||
964 | /* Enable tx dma */ | |
965 | dma_config = (RESTART | WDSIZE_16 | DI_EN); | |
966 | set_dma_start_addr(sport->dma_tx_chan, (unsigned long)out_data); | |
967 | set_dma_x_count(sport->dma_tx_chan, len/2); | |
968 | set_dma_x_modify(sport->dma_tx_chan, 2); | |
969 | set_dma_config(sport->dma_tx_chan, dma_config); | |
970 | enable_dma(sport->dma_tx_chan); | |
971 | ||
972 | if (in_data != NULL) { | |
973 | invalidate_dcache_range((unsigned)in_data, \ | |
974 | (unsigned)(in_data + len)); | |
975 | /* Enable rx dma */ | |
976 | dma_config = (RESTART | WDSIZE_16 | WNR | DI_EN); | |
977 | set_dma_start_addr(sport->dma_rx_chan, (unsigned long)in_data); | |
978 | set_dma_x_count(sport->dma_rx_chan, len/2); | |
979 | set_dma_x_modify(sport->dma_rx_chan, 2); | |
980 | set_dma_config(sport->dma_rx_chan, dma_config); | |
981 | enable_dma(sport->dma_rx_chan); | |
982 | } | |
983 | ||
984 | local_irq_save(flags); | |
985 | sport->regs->tcr1 |= TSPEN; | |
986 | sport->regs->rcr1 |= RSPEN; | |
987 | SSYNC(); | |
988 | ||
989 | status = get_dma_curr_irqstat(sport->dma_tx_chan); | |
990 | while (status & DMA_RUN) { | |
991 | udelay(1); | |
992 | status = get_dma_curr_irqstat(sport->dma_tx_chan); | |
993 | pr_debug("DMA status:0x%04x\n", status); | |
994 | if (wait++ > 100) | |
995 | goto __over; | |
996 | } | |
997 | status = sport->regs->stat; | |
998 | wait = 0; | |
999 | ||
1000 | while (!(status & TXHRE)) { | |
1001 | pr_debug("sport status:0x%04x\n", status); | |
1002 | udelay(1); | |
1003 | status = *(unsigned short *)&sport->regs->stat; | |
1004 | if (wait++ > 1000) | |
1005 | goto __over; | |
1006 | } | |
1007 | /* Wait for the last byte sent out */ | |
1008 | udelay(20); | |
1009 | pr_debug("sport status:0x%04x\n", status); | |
1010 | ||
1011 | __over: | |
1012 | sport->regs->tcr1 &= ~TSPEN; | |
1013 | sport->regs->rcr1 &= ~RSPEN; | |
1014 | SSYNC(); | |
1015 | disable_dma(sport->dma_tx_chan); | |
1016 | /* Clear the status */ | |
1017 | clear_dma_irqstat(sport->dma_tx_chan); | |
1018 | if (in_data != NULL) { | |
1019 | disable_dma(sport->dma_rx_chan); | |
1020 | clear_dma_irqstat(sport->dma_rx_chan); | |
1021 | } | |
1022 | SSYNC(); | |
1023 | local_irq_restore(flags); | |
1024 | ||
1025 | return 0; | |
1026 | } | |
1027 | EXPORT_SYMBOL(sport_send_and_recv); | |
1028 | ||
1029 | MODULE_AUTHOR("Roy Huang"); | |
1030 | MODULE_DESCRIPTION("SPORT driver for ADI Blackfin"); | |
1031 | MODULE_LICENSE("GPL"); | |
1032 |