[deliverable/linux.git] / sound / soc / cirrus / ep93xx-ac97.c

/*
 * ASoC driver for Cirrus Logic EP93xx AC97 controller.
 *
 * Copyright (c) 2010 Mika Westerberg
 *
 * Based on s3c-ac97 ASoC driver by Jaswinder Singh.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include <sound/core.h>
#include <sound/dmaengine_pcm.h>
#include <sound/ac97_codec.h>
#include <sound/soc.h>

#include <linux/platform_data/dma-ep93xx.h>

#include "ep93xx-pcm.h"

/*
 * Per channel (1-4) registers.
 */
#define AC97CH(n)		(((n) - 1) * 0x20)

#define AC97DR(n)		(AC97CH(n) + 0x0000)

#define AC97RXCR(n)		(AC97CH(n) + 0x0004)
#define AC97RXCR_REN		BIT(0)
#define AC97RXCR_RX3		BIT(3)
#define AC97RXCR_RX4		BIT(4)
#define AC97RXCR_CM		BIT(15)

#define AC97TXCR(n)		(AC97CH(n) + 0x0008)
#define AC97TXCR_TEN		BIT(0)
#define AC97TXCR_TX3		BIT(3)
#define AC97TXCR_TX4		BIT(4)
#define AC97TXCR_CM		BIT(15)

#define AC97SR(n)		(AC97CH(n) + 0x000c)
#define AC97SR_TXFE		BIT(1)
#define AC97SR_TXUE		BIT(6)

#define AC97RISR(n)		(AC97CH(n) + 0x0010)
#define AC97ISR(n)		(AC97CH(n) + 0x0014)
#define AC97IE(n)		(AC97CH(n) + 0x0018)

/*
 * Global AC97 controller registers.
 */
#define AC97S1DATA		0x0080
#define AC97S2DATA		0x0084
#define AC97S12DATA		0x0088

#define AC97RGIS		0x008c
#define AC97GIS			0x0090
#define AC97IM			0x0094
/*
 * Common bits for RGIS, GIS and IM registers.
 */
#define AC97_SLOT2RXVALID	BIT(1)
#define AC97_CODECREADY		BIT(5)
#define AC97_SLOT2TXCOMPLETE	BIT(6)

#define AC97EOI			0x0098
#define AC97EOI_WINT		BIT(0)
#define AC97EOI_CODECREADY	BIT(1)

#define AC97GCR			0x009c
#define AC97GCR_AC97IFE		BIT(0)

#define AC97RESET		0x00a0
#define AC97RESET_TIMEDRESET	BIT(0)

#define AC97SYNC		0x00a4
#define AC97SYNC_TIMEDSYNC	BIT(0)

#define AC97_TIMEOUT		msecs_to_jiffies(5)

/**
 * struct ep93xx_ac97_info - EP93xx AC97 controller info structure
 * @lock: mutex serializing access to the bus (slot 1 & 2 ops)
 * @dev: pointer to the platform device dev structure
 * @regs: mapped AC97 controller registers
 * @done: bus ops wait here for an interrupt
 */
struct ep93xx_ac97_info {
	struct mutex		lock;
	struct device		*dev;
	void __iomem		*regs;
	struct completion	done;
	struct snd_dmaengine_dai_dma_data dma_params_rx;
	struct snd_dmaengine_dai_dma_data dma_params_tx;
};

/* currently ALSA only supports a single AC97 device */
static struct ep93xx_ac97_info *ep93xx_ac97_info;

static struct ep93xx_dma_data ep93xx_ac97_pcm_out = {
	.name		= "ac97-pcm-out",
	.port		= EP93XX_DMA_AAC1,
	.direction	= DMA_MEM_TO_DEV,
};

static struct ep93xx_dma_data ep93xx_ac97_pcm_in = {
	.name		= "ac97-pcm-in",
	.port		= EP93XX_DMA_AAC1,
	.direction	= DMA_DEV_TO_MEM,
};

static inline unsigned ep93xx_ac97_read_reg(struct ep93xx_ac97_info *info,
					    unsigned reg)
{
	return __raw_readl(info->regs + reg);
}

static inline void ep93xx_ac97_write_reg(struct ep93xx_ac97_info *info,
					 unsigned reg, unsigned val)
{
	__raw_writel(val, info->regs + reg);
}

static unsigned short ep93xx_ac97_read(struct snd_ac97 *ac97,
				       unsigned short reg)
{
	struct ep93xx_ac97_info *info = ep93xx_ac97_info;
	unsigned short val;

	mutex_lock(&info->lock);

	ep93xx_ac97_write_reg(info, AC97S1DATA, reg);
	ep93xx_ac97_write_reg(info, AC97IM, AC97_SLOT2RXVALID);
	if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT)) {
		dev_warn(info->dev, "timeout reading register %x\n", reg);
		mutex_unlock(&info->lock);
		return -ETIMEDOUT;
	}
	val = (unsigned short)ep93xx_ac97_read_reg(info, AC97S2DATA);

	mutex_unlock(&info->lock);
	return val;
}

static void ep93xx_ac97_write(struct snd_ac97 *ac97,
			      unsigned short reg,
			      unsigned short val)
{
	struct ep93xx_ac97_info *info = ep93xx_ac97_info;

	mutex_lock(&info->lock);

	/*
	 * Writes to the codec need to be done so that slot 2 is filled in
	 * before slot 1.
	 */
	ep93xx_ac97_write_reg(info, AC97S2DATA, val);
	ep93xx_ac97_write_reg(info, AC97S1DATA, reg);

	ep93xx_ac97_write_reg(info, AC97IM, AC97_SLOT2TXCOMPLETE);
	if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
		dev_warn(info->dev, "timeout writing register %x\n", reg);

	mutex_unlock(&info->lock);
}

static void ep93xx_ac97_warm_reset(struct snd_ac97 *ac97)
{
	struct ep93xx_ac97_info *info = ep93xx_ac97_info;

	mutex_lock(&info->lock);

	/*
	 * We are assuming that before this functions gets called, the codec
	 * BIT_CLK is stopped by forcing the codec into powerdown mode. We can
	 * control the SYNC signal directly via AC97SYNC register. Using
	 * TIMEDSYNC the controller will keep the SYNC high > 1us.
	 */
	ep93xx_ac97_write_reg(info, AC97SYNC, AC97SYNC_TIMEDSYNC);
	ep93xx_ac97_write_reg(info, AC97IM, AC97_CODECREADY);
	if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
		dev_warn(info->dev, "codec warm reset timeout\n");

	mutex_unlock(&info->lock);
}

static void ep93xx_ac97_cold_reset(struct snd_ac97 *ac97)
{
	struct ep93xx_ac97_info *info = ep93xx_ac97_info;

	mutex_lock(&info->lock);

	/*
	 * For doing cold reset, we disable the AC97 controller interface, clear
	 * WINT and CODECREADY bits, and finally enable the interface again.
	 */
	ep93xx_ac97_write_reg(info, AC97GCR, 0);
	ep93xx_ac97_write_reg(info, AC97EOI, AC97EOI_CODECREADY | AC97EOI_WINT);
	ep93xx_ac97_write_reg(info, AC97GCR, AC97GCR_AC97IFE);

	/*
	 * Now, assert the reset and wait for the codec to become ready.
	 */
	ep93xx_ac97_write_reg(info, AC97RESET, AC97RESET_TIMEDRESET);
	ep93xx_ac97_write_reg(info, AC97IM, AC97_CODECREADY);
	if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
		dev_warn(info->dev, "codec cold reset timeout\n");

	/*
	 * Give the codec some time to come fully out from the reset. This way
	 * we ensure that the subsequent reads/writes will work.
	 */
	usleep_range(15000, 20000);

	mutex_unlock(&info->lock);
}

static irqreturn_t ep93xx_ac97_interrupt(int irq, void *dev_id)
{
	struct ep93xx_ac97_info *info = dev_id;
	unsigned status, mask;

	/*
	 * Just mask out the interrupt and wake up the waiting thread.
	 * Interrupts are cleared via reading/writing to slot 1 & 2 registers by
	 * the waiting thread.
	 */
	status = ep93xx_ac97_read_reg(info, AC97GIS);
	mask = ep93xx_ac97_read_reg(info, AC97IM);
	mask &= ~status;
	ep93xx_ac97_write_reg(info, AC97IM, mask);

	complete(&info->done);
	return IRQ_HANDLED;
}

static struct snd_ac97_bus_ops ep93xx_ac97_ops = {
	.read		= ep93xx_ac97_read,
	.write		= ep93xx_ac97_write,
	.reset		= ep93xx_ac97_cold_reset,
	.warm_reset	= ep93xx_ac97_warm_reset,
};

static int ep93xx_ac97_trigger(struct snd_pcm_substream *substream,
			       int cmd, struct snd_soc_dai *dai)
{
	struct ep93xx_ac97_info *info = snd_soc_dai_get_drvdata(dai);
	unsigned v = 0;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
			/*
			 * Enable compact mode, TX slots 3 & 4, and the TX FIFO
			 * itself.
			 */
			v |= AC97TXCR_CM;
			v |= AC97TXCR_TX3 | AC97TXCR_TX4;
			v |= AC97TXCR_TEN;
			ep93xx_ac97_write_reg(info, AC97TXCR(1), v);
		} else {
			/*
			 * Enable compact mode, RX slots 3 & 4, and the RX FIFO
			 * itself.
			 */
			v |= AC97RXCR_CM;
			v |= AC97RXCR_RX3 | AC97RXCR_RX4;
			v |= AC97RXCR_REN;
			ep93xx_ac97_write_reg(info, AC97RXCR(1), v);
		}
		break;

	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
			/*
			 * As per Cirrus EP93xx errata described below:
			 *
			 * http://www.cirrus.com/en/pubs/errata/ER667E2B.pdf
			 *
			 * we will wait for the TX FIFO to be empty before
			 * clearing the TEN bit.
			 */
			unsigned long timeout = jiffies + AC97_TIMEOUT;

			do {
				v = ep93xx_ac97_read_reg(info, AC97SR(1));
				if (time_after(jiffies, timeout)) {
					dev_warn(info->dev, "TX timeout\n");
					break;
				}
			} while (!(v & (AC97SR_TXFE | AC97SR_TXUE)));

			/* disable the TX FIFO */
			ep93xx_ac97_write_reg(info, AC97TXCR(1), 0);
		} else {
			/* disable the RX FIFO */
			ep93xx_ac97_write_reg(info, AC97RXCR(1), 0);
		}
		break;

	default:
		dev_warn(info->dev, "unknown command %d\n", cmd);
		return -EINVAL;
	}

	return 0;
}

static int ep93xx_ac97_dai_probe(struct snd_soc_dai *dai)
{
	struct ep93xx_ac97_info *info = snd_soc_dai_get_drvdata(dai);

	info->dma_params_tx.filter_data = &ep93xx_ac97_pcm_out;
	info->dma_params_rx.filter_data = &ep93xx_ac97_pcm_in;

	dai->playback_dma_data = &info->dma_params_tx;
	dai->capture_dma_data = &info->dma_params_rx;

	return 0;
}

static const struct snd_soc_dai_ops ep93xx_ac97_dai_ops = {
	.trigger	= ep93xx_ac97_trigger,
};

static struct snd_soc_dai_driver ep93xx_ac97_dai = {
	.name		= "ep93xx-ac97",
	.id		= 0,
	.bus_control	= true,
	.probe		= ep93xx_ac97_dai_probe,
	.playback	= {
		.stream_name	= "AC97 Playback",
		.channels_min	= 2,
		.channels_max	= 2,
		.rates		= SNDRV_PCM_RATE_8000_48000,
		.formats	= SNDRV_PCM_FMTBIT_S16_LE,
	},
	.capture	= {
		.stream_name	= "AC97 Capture",
		.channels_min	= 2,
		.channels_max	= 2,
		.rates		= SNDRV_PCM_RATE_8000_48000,
		.formats	= SNDRV_PCM_FMTBIT_S16_LE,
	},
	.ops			= &ep93xx_ac97_dai_ops,
};

static const struct snd_soc_component_driver ep93xx_ac97_component = {
	.name		= "ep93xx-ac97",
};

static int ep93xx_ac97_probe(struct platform_device *pdev)
{
	struct ep93xx_ac97_info *info;
	struct resource *res;
	unsigned int irq;
	int ret;

	info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
	if (!info)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	info->regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(info->regs))
		return PTR_ERR(info->regs);

	irq = platform_get_irq(pdev, 0);
	if (!irq)
		return -ENODEV;

	ret = devm_request_irq(&pdev->dev, irq, ep93xx_ac97_interrupt,
			       IRQF_TRIGGER_HIGH, pdev->name, info);
	if (ret)
		goto fail;

	dev_set_drvdata(&pdev->dev, info);

	mutex_init(&info->lock);
	init_completion(&info->done);
	info->dev = &pdev->dev;

	ep93xx_ac97_info = info;
	platform_set_drvdata(pdev, info);

	ret = snd_soc_set_ac97_ops(&ep93xx_ac97_ops);
	if (ret)
		goto fail;

	ret = snd_soc_register_component(&pdev->dev, &ep93xx_ac97_component,
					 &ep93xx_ac97_dai, 1);
	if (ret)
		goto fail;

	ret = devm_ep93xx_pcm_platform_register(&pdev->dev);
	if (ret)
		goto fail_unregister;

	return 0;

fail_unregister:
	snd_soc_unregister_component(&pdev->dev);
fail:
	ep93xx_ac97_info = NULL;
	snd_soc_set_ac97_ops(NULL);
	return ret;
}

static int ep93xx_ac97_remove(struct platform_device *pdev)
{
	struct ep93xx_ac97_info	*info = platform_get_drvdata(pdev);

	snd_soc_unregister_component(&pdev->dev);

	/* disable the AC97 controller */
	ep93xx_ac97_write_reg(info, AC97GCR, 0);

	ep93xx_ac97_info = NULL;

	snd_soc_set_ac97_ops(NULL);

	return 0;
}

static struct platform_driver ep93xx_ac97_driver = {
	.probe	= ep93xx_ac97_probe,
	.remove	= ep93xx_ac97_remove,
	.driver = {
		.name = "ep93xx-ac97",
	},
};

module_platform_driver(ep93xx_ac97_driver);

MODULE_DESCRIPTION("EP93xx AC97 ASoC Driver");
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:ep93xx-ac97");
Commit	Line	Data
aa7e1b84 MW	1	/*
	2	* ASoC driver for Cirrus Logic EP93xx AC97 controller.
	3	*
	4	* Copyright (c) 2010 Mika Westerberg
	5	*
	6	* Based on s3c-ac97 ASoC driver by Jaswinder Singh.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/delay.h>
b25b5aa0	14	#include <linux/err.h>
aa7e1b84 MW	15	#include <linux/io.h>
	16	#include <linux/init.h>
	17	#include <linux/module.h>
	18	#include <linux/platform_device.h>
	19	#include <linux/slab.h>
	20
	21	#include <sound/core.h>
a8983d4b	22	#include <sound/dmaengine_pcm.h>
aa7e1b84 MW	23	#include <sound/ac97_codec.h>
	24	#include <sound/soc.h>
	25
a3b29245	26	#include <linux/platform_data/dma-ep93xx.h>
aa7e1b84	27
6f2032a1 SW	28	#include "ep93xx-pcm.h"
6f2032a1 SW	29
aa7e1b84 MW	30	/*
	31	* Per channel (1-4) registers.
	32	*/
	33	#define AC97CH(n) (((n) - 1) * 0x20)
	34
	35	#define AC97DR(n) (AC97CH(n) + 0x0000)
	36
	37	#define AC97RXCR(n) (AC97CH(n) + 0x0004)
	38	#define AC97RXCR_REN BIT(0)
	39	#define AC97RXCR_RX3 BIT(3)
	40	#define AC97RXCR_RX4 BIT(4)
	41	#define AC97RXCR_CM BIT(15)
	42
	43	#define AC97TXCR(n) (AC97CH(n) + 0x0008)
	44	#define AC97TXCR_TEN BIT(0)
	45	#define AC97TXCR_TX3 BIT(3)
	46	#define AC97TXCR_TX4 BIT(4)
	47	#define AC97TXCR_CM BIT(15)
	48
	49	#define AC97SR(n) (AC97CH(n) + 0x000c)
	50	#define AC97SR_TXFE BIT(1)
	51	#define AC97SR_TXUE BIT(6)
	52
	53	#define AC97RISR(n) (AC97CH(n) + 0x0010)
	54	#define AC97ISR(n) (AC97CH(n) + 0x0014)
	55	#define AC97IE(n) (AC97CH(n) + 0x0018)
	56
	57	/*
	58	* Global AC97 controller registers.
	59	*/
	60	#define AC97S1DATA 0x0080
	61	#define AC97S2DATA 0x0084
	62	#define AC97S12DATA 0x0088
	63
	64	#define AC97RGIS 0x008c
	65	#define AC97GIS 0x0090
	66	#define AC97IM 0x0094
	67	/*
	68	* Common bits for RGIS, GIS and IM registers.
	69	*/
	70	#define AC97_SLOT2RXVALID BIT(1)
	71	#define AC97_CODECREADY BIT(5)
	72	#define AC97_SLOT2TXCOMPLETE BIT(6)
	73
	74	#define AC97EOI 0x0098
	75	#define AC97EOI_WINT BIT(0)
	76	#define AC97EOI_CODECREADY BIT(1)
	77
	78	#define AC97GCR 0x009c
	79	#define AC97GCR_AC97IFE BIT(0)
	80
	81	#define AC97RESET 0x00a0
	82	#define AC97RESET_TIMEDRESET BIT(0)
	83
	84	#define AC97SYNC 0x00a4
	85	#define AC97SYNC_TIMEDSYNC BIT(0)
	86
	87	#define AC97_TIMEOUT msecs_to_jiffies(5)
	88
	89	/**
	90	* struct ep93xx_ac97_info - EP93xx AC97 controller info structure
	91	* @lock: mutex serializing access to the bus (slot 1 & 2 ops)
	92	* @dev: pointer to the platform device dev structure
aa7e1b84	93	* @regs: mapped AC97 controller registers
aa7e1b84 MW	94	* @done: bus ops wait here for an interrupt
	95	*/
	96	struct ep93xx_ac97_info {
	97	struct mutex lock;
	98	struct device *dev;
aa7e1b84	99	void __iomem *regs;
aa7e1b84	100	struct completion done;
a8983d4b SW	101	struct snd_dmaengine_dai_dma_data dma_params_rx;
a8983d4b SW	102	struct snd_dmaengine_dai_dma_data dma_params_tx;
aa7e1b84 MW	103	};
	104
	105	/* currently ALSA only supports a single AC97 device */
	106	static struct ep93xx_ac97_info *ep93xx_ac97_info;
	107
453807f3	108	static struct ep93xx_dma_data ep93xx_ac97_pcm_out = {
aa7e1b84	109	.name = "ac97-pcm-out",
83e2e4ee	110	.port = EP93XX_DMA_AAC1,
453807f3	111	.direction = DMA_MEM_TO_DEV,
aa7e1b84 MW	112	};
aa7e1b84 MW	113
453807f3	114	static struct ep93xx_dma_data ep93xx_ac97_pcm_in = {
aa7e1b84	115	.name = "ac97-pcm-in",
83e2e4ee	116	.port = EP93XX_DMA_AAC1,
453807f3	117	.direction = DMA_DEV_TO_MEM,
aa7e1b84 MW	118	};
	119
	120	static inline unsigned ep93xx_ac97_read_reg(struct ep93xx_ac97_info *info,
	121	unsigned reg)
	122	{
	123	return __raw_readl(info->regs + reg);
	124	}
	125
	126	static inline void ep93xx_ac97_write_reg(struct ep93xx_ac97_info *info,
	127	unsigned reg, unsigned val)
	128	{
	129	__raw_writel(val, info->regs + reg);
	130	}
	131
	132	static unsigned short ep93xx_ac97_read(struct snd_ac97 *ac97,
	133	unsigned short reg)
	134	{
	135	struct ep93xx_ac97_info *info = ep93xx_ac97_info;
	136	unsigned short val;
	137
	138	mutex_lock(&info->lock);
	139
	140	ep93xx_ac97_write_reg(info, AC97S1DATA, reg);
	141	ep93xx_ac97_write_reg(info, AC97IM, AC97_SLOT2RXVALID);
	142	if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT)) {
	143	dev_warn(info->dev, "timeout reading register %x\n", reg);
	144	mutex_unlock(&info->lock);
	145	return -ETIMEDOUT;
	146	}
	147	val = (unsigned short)ep93xx_ac97_read_reg(info, AC97S2DATA);
	148
	149	mutex_unlock(&info->lock);
	150	return val;
	151	}
	152
	153	static void ep93xx_ac97_write(struct snd_ac97 *ac97,
	154	unsigned short reg,
	155	unsigned short val)
	156	{
	157	struct ep93xx_ac97_info *info = ep93xx_ac97_info;
	158
	159	mutex_lock(&info->lock);
	160
	161	/*
	162	* Writes to the codec need to be done so that slot 2 is filled in
	163	* before slot 1.
	164	*/
	165	ep93xx_ac97_write_reg(info, AC97S2DATA, val);
	166	ep93xx_ac97_write_reg(info, AC97S1DATA, reg);
	167
	168	ep93xx_ac97_write_reg(info, AC97IM, AC97_SLOT2TXCOMPLETE);
	169	if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
	170	dev_warn(info->dev, "timeout writing register %x\n", reg);
	171
	172	mutex_unlock(&info->lock);
	173	}
	174
	175	static void ep93xx_ac97_warm_reset(struct snd_ac97 *ac97)
	176	{
	177	struct ep93xx_ac97_info *info = ep93xx_ac97_info;
	178
	179	mutex_lock(&info->lock);
	180
	181	/*
182	* We are assuming that before this functions gets called, the codec
183	* BIT_CLK is stopped by forcing the codec into powerdown mode. We can
184	* control the SYNC signal directly via AC97SYNC register. Using
185	* TIMEDSYNC the controller will keep the SYNC high > 1us.
186	*/
187	ep93xx_ac97_write_reg(info, AC97SYNC, AC97SYNC_TIMEDSYNC);
188	ep93xx_ac97_write_reg(info, AC97IM, AC97_CODECREADY);
189	if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
190	dev_warn(info->dev, "codec warm reset timeout\n");
191
192	mutex_unlock(&info->lock);
193	}
194
195	static void ep93xx_ac97_cold_reset(struct snd_ac97 *ac97)
196	{
197	struct ep93xx_ac97_info *info = ep93xx_ac97_info;
198
199	mutex_lock(&info->lock);
200
201	/*
202	* For doing cold reset, we disable the AC97 controller interface, clear
203	* WINT and CODECREADY bits, and finally enable the interface again.
204	*/
205	ep93xx_ac97_write_reg(info, AC97GCR, 0);
206	ep93xx_ac97_write_reg(info, AC97EOI, AC97EOI_CODECREADY \| AC97EOI_WINT);
207	ep93xx_ac97_write_reg(info, AC97GCR, AC97GCR_AC97IFE);
208
209	/*
210	* Now, assert the reset and wait for the codec to become ready.
211	*/
212	ep93xx_ac97_write_reg(info, AC97RESET, AC97RESET_TIMEDRESET);
213	ep93xx_ac97_write_reg(info, AC97IM, AC97_CODECREADY);
214	if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
215	dev_warn(info->dev, "codec cold reset timeout\n");
216
217	/*
218	* Give the codec some time to come fully out from the reset. This way
219	* we ensure that the subsequent reads/writes will work.
220	*/
221	usleep_range(15000, 20000);
222
223	mutex_unlock(&info->lock);
224	}
225
226	static irqreturn_t ep93xx_ac97_interrupt(int irq, void *dev_id)
227	{
228	struct ep93xx_ac97_info *info = dev_id;
229	unsigned status, mask;
230
231	/*
232	* Just mask out the interrupt and wake up the waiting thread.
233	* Interrupts are cleared via reading/writing to slot 1 & 2 registers by
234	* the waiting thread.
235	*/
236	status = ep93xx_ac97_read_reg(info, AC97GIS);
237	mask = ep93xx_ac97_read_reg(info, AC97IM);
238	mask &= ~status;
239	ep93xx_ac97_write_reg(info, AC97IM, mask);
240
241	complete(&info->done);
242	return IRQ_HANDLED;
243	}
244
b047e1cc	245	static struct snd_ac97_bus_ops ep93xx_ac97_ops = {
aa7e1b84 MW	246	.read = ep93xx_ac97_read,
	247	.write = ep93xx_ac97_write,
	248	.reset = ep93xx_ac97_cold_reset,
	249	.warm_reset = ep93xx_ac97_warm_reset,
	250	};
aa7e1b84 MW	251
	252	static int ep93xx_ac97_trigger(struct snd_pcm_substream *substream,
	253	int cmd, struct snd_soc_dai *dai)
	254	{
	255	struct ep93xx_ac97_info *info = snd_soc_dai_get_drvdata(dai);
	256	unsigned v = 0;
	257
aa7e1b84 MW	258	switch (cmd) {
	259	case SNDRV_PCM_TRIGGER_START:
	260	case SNDRV_PCM_TRIGGER_RESUME:
	261	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	262	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	263	/*
	264	* Enable compact mode, TX slots 3 & 4, and the TX FIFO
	265	* itself.
	266	*/
	267	v \|= AC97TXCR_CM;
	268	v \|= AC97TXCR_TX3 \| AC97TXCR_TX4;
	269	v \|= AC97TXCR_TEN;
	270	ep93xx_ac97_write_reg(info, AC97TXCR(1), v);
	271	} else {
	272	/*
	273	* Enable compact mode, RX slots 3 & 4, and the RX FIFO
	274	* itself.
	275	*/
	276	v \|= AC97RXCR_CM;
	277	v \|= AC97RXCR_RX3 \| AC97RXCR_RX4;
	278	v \|= AC97RXCR_REN;
	279	ep93xx_ac97_write_reg(info, AC97RXCR(1), v);
	280	}
	281	break;
	282
	283	case SNDRV_PCM_TRIGGER_STOP:
	284	case SNDRV_PCM_TRIGGER_SUSPEND:
	285	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	286	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	287	/*
	288	* As per Cirrus EP93xx errata described below:
	289	*
	290	* http://www.cirrus.com/en/pubs/errata/ER667E2B.pdf
	291	*
	292	* we will wait for the TX FIFO to be empty before
	293	* clearing the TEN bit.
	294	*/
	295	unsigned long timeout = jiffies + AC97_TIMEOUT;
	296
	297	do {
	298	v = ep93xx_ac97_read_reg(info, AC97SR(1));
	299	if (time_after(jiffies, timeout)) {
	300	dev_warn(info->dev, "TX timeout\n");
	301	break;
	302	}
	303	} while (!(v & (AC97SR_TXFE \| AC97SR_TXUE)));
	304
	305	/* disable the TX FIFO */
	306	ep93xx_ac97_write_reg(info, AC97TXCR(1), 0);
	307	} else {
	308	/* disable the RX FIFO */
	309	ep93xx_ac97_write_reg(info, AC97RXCR(1), 0);
	310	}
	311	break;
	312
	313	default:
	314	dev_warn(info->dev, "unknown command %d\n", cmd);
	315	return -EINVAL;
	316	}
	317
	318	return 0;
	319	}
	320
785d81e2	321	static int ep93xx_ac97_dai_probe(struct snd_soc_dai *dai)
aa7e1b84	322	{
a8983d4b SW	323	struct ep93xx_ac97_info *info = snd_soc_dai_get_drvdata(dai);
	324
	325	info->dma_params_tx.filter_data = &ep93xx_ac97_pcm_out;
	326	info->dma_params_rx.filter_data = &ep93xx_ac97_pcm_in;
	327
	328	dai->playback_dma_data = &info->dma_params_tx;
	329	dai->capture_dma_data = &info->dma_params_rx;
aa7e1b84	330
aa7e1b84 MW	331	return 0;
	332	}
	333
85e7652d	334	static const struct snd_soc_dai_ops ep93xx_ac97_dai_ops = {
aa7e1b84 MW	335	.trigger = ep93xx_ac97_trigger,
	336	};
	337
1c6927f8	338	static struct snd_soc_dai_driver ep93xx_ac97_dai = {
aa7e1b84 MW	339	.name = "ep93xx-ac97",
aa7e1b84 MW	340	.id = 0,
bc263214	341	.bus_control = true,
785d81e2	342	.probe = ep93xx_ac97_dai_probe,
aa7e1b84 MW	343	.playback = {
	344	.stream_name = "AC97 Playback",
	345	.channels_min = 2,
	346	.channels_max = 2,
	347	.rates = SNDRV_PCM_RATE_8000_48000,
	348	.formats = SNDRV_PCM_FMTBIT_S16_LE,
	349	},
	350	.capture = {
	351	.stream_name = "AC97 Capture",
	352	.channels_min = 2,
	353	.channels_max = 2,
	354	.rates = SNDRV_PCM_RATE_8000_48000,
	355	.formats = SNDRV_PCM_FMTBIT_S16_LE,
	356	},
	357	.ops = &ep93xx_ac97_dai_ops,
	358	};
	359
426c3408 KM	360	static const struct snd_soc_component_driver ep93xx_ac97_component = {
	361	.name = "ep93xx-ac97",
	362	};
	363
145e2879	364	static int ep93xx_ac97_probe(struct platform_device *pdev)
aa7e1b84 MW	365	{
aa7e1b84 MW	366	struct ep93xx_ac97_info *info;
e7cff0ab HS	367	struct resource *res;
e7cff0ab HS	368	unsigned int irq;
aa7e1b84 MW	369	int ret;
aa7e1b84 MW	370
e7cff0ab	371	info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
aa7e1b84 MW	372	if (!info)
	373	return -ENOMEM;
	374
e7cff0ab	375	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b25b5aa0 TR	376	info->regs = devm_ioremap_resource(&pdev->dev, res);
	377	if (IS_ERR(info->regs))
	378	return PTR_ERR(info->regs);
aa7e1b84	379
e7cff0ab HS	380	irq = platform_get_irq(pdev, 0);
	381	if (!irq)
	382	return -ENODEV;
aa7e1b84	383
e7cff0ab HS	384	ret = devm_request_irq(&pdev->dev, irq, ep93xx_ac97_interrupt,
	385	IRQF_TRIGGER_HIGH, pdev->name, info);
	386	if (ret)
	387	goto fail;
aa7e1b84	388
e7cff0ab	389	dev_set_drvdata(&pdev->dev, info);
aa7e1b84	390
e7cff0ab HS	391	mutex_init(&info->lock);
	392	init_completion(&info->done);
	393	info->dev = &pdev->dev;
aa7e1b84 MW	394
	395	ep93xx_ac97_info = info;
	396	platform_set_drvdata(pdev, info);
	397
b047e1cc MB	398	ret = snd_soc_set_ac97_ops(&ep93xx_ac97_ops);
	399	if (ret)
	400	goto fail;
	401
426c3408 KM	402	ret = snd_soc_register_component(&pdev->dev, &ep93xx_ac97_component,
426c3408 KM	403	&ep93xx_ac97_dai, 1);
aa7e1b84	404	if (ret)
e7cff0ab	405	goto fail;
aa7e1b84	406
6f2032a1 SW	407	ret = devm_ep93xx_pcm_platform_register(&pdev->dev);
	408	if (ret)
	409	goto fail_unregister;
	410
aa7e1b84 MW	411	return 0;
aa7e1b84 MW	412
6f2032a1 SW	413	fail_unregister:
6f2032a1 SW	414	snd_soc_unregister_component(&pdev->dev);
e7cff0ab	415	fail:
e7cff0ab	416	ep93xx_ac97_info = NULL;
b047e1cc	417	snd_soc_set_ac97_ops(NULL);
aa7e1b84 MW	418	return ret;
	419	}
	420
145e2879	421	static int ep93xx_ac97_remove(struct platform_device *pdev)
aa7e1b84 MW	422	{
	423	struct ep93xx_ac97_info *info = platform_get_drvdata(pdev);
	424
426c3408	425	snd_soc_unregister_component(&pdev->dev);
aa7e1b84 MW	426
	427	/* disable the AC97 controller */
	428	ep93xx_ac97_write_reg(info, AC97GCR, 0);
	429
e7cff0ab	430	ep93xx_ac97_info = NULL;
aa7e1b84	431
b047e1cc	432	snd_soc_set_ac97_ops(NULL);
aa7e1b84 MW	433
	434	return 0;
	435	}
	436
	437	static struct platform_driver ep93xx_ac97_driver = {
	438	.probe = ep93xx_ac97_probe,
145e2879	439	.remove = ep93xx_ac97_remove,
aa7e1b84 MW	440	.driver = {
aa7e1b84 MW	441	.name = "ep93xx-ac97",
aa7e1b84 MW	442	},
	443	};
	444
ee18f631	445	module_platform_driver(ep93xx_ac97_driver);
aa7e1b84 MW	446
	447	MODULE_DESCRIPTION("EP93xx AC97 ASoC Driver");
	448	MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");
	449	MODULE_LICENSE("GPL");
	450	MODULE_ALIAS("platform:ep93xx-ac97");