[deliverable/linux.git] / sound / soc / cirrus / ep93xx-i2s.c

/*
 * linux/sound/soc/ep93xx-i2s.c
 * EP93xx I2S driver
 *
 * Copyright (C) 2010 Ryan Mallon
 *
 * Based on the original driver by:
 *   Copyright (C) 2007 Chase Douglas <chasedouglas@gmail>
 *   Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/io.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>

#include <mach/hardware.h>
#include <mach/ep93xx-regs.h>
#include <linux/platform_data/dma-ep93xx.h>

#include "ep93xx-pcm.h"

#define EP93XX_I2S_TXCLKCFG		0x00
#define EP93XX_I2S_RXCLKCFG		0x04
#define EP93XX_I2S_GLCTRL		0x0C

#define EP93XX_I2S_TXLINCTRLDATA	0x28
#define EP93XX_I2S_TXCTRL		0x2C
#define EP93XX_I2S_TXWRDLEN		0x30
#define EP93XX_I2S_TX0EN		0x34

#define EP93XX_I2S_RXLINCTRLDATA	0x58
#define EP93XX_I2S_RXCTRL		0x5C
#define EP93XX_I2S_RXWRDLEN		0x60
#define EP93XX_I2S_RX0EN		0x64

#define EP93XX_I2S_WRDLEN_16		(0 << 0)
#define EP93XX_I2S_WRDLEN_24		(1 << 0)
#define EP93XX_I2S_WRDLEN_32		(2 << 0)

#define EP93XX_I2S_LINCTRLDATA_R_JUST	(1 << 2) /* Right justify */

#define EP93XX_I2S_CLKCFG_LRS		(1 << 0) /* lrclk polarity */
#define EP93XX_I2S_CLKCFG_CKP		(1 << 1) /* Bit clock polarity */
#define EP93XX_I2S_CLKCFG_REL		(1 << 2) /* First bit transition */
#define EP93XX_I2S_CLKCFG_MASTER	(1 << 3) /* Master mode */
#define EP93XX_I2S_CLKCFG_NBCG		(1 << 4) /* Not bit clock gating */

struct ep93xx_i2s_info {
	struct clk			*mclk;
	struct clk			*sclk;
	struct clk			*lrclk;
	void __iomem			*regs;
};

static struct ep93xx_dma_data ep93xx_i2s_dma_data[] = {
	[SNDRV_PCM_STREAM_PLAYBACK] = {
		.name		= "i2s-pcm-out",
		.port		= EP93XX_DMA_I2S1,
		.direction	= DMA_MEM_TO_DEV,
	},
	[SNDRV_PCM_STREAM_CAPTURE] = {
		.name		= "i2s-pcm-in",
		.port		= EP93XX_DMA_I2S1,
		.direction	= DMA_DEV_TO_MEM,
	},
};

static inline void ep93xx_i2s_write_reg(struct ep93xx_i2s_info *info,
					unsigned reg, unsigned val)
{
	__raw_writel(val, info->regs + reg);
}

static inline unsigned ep93xx_i2s_read_reg(struct ep93xx_i2s_info *info,
					   unsigned reg)
{
	return __raw_readl(info->regs + reg);
}

static void ep93xx_i2s_enable(struct ep93xx_i2s_info *info, int stream)
{
	unsigned base_reg;
	int i;

	if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
	    (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
		/* Enable clocks */
		clk_enable(info->mclk);
		clk_enable(info->sclk);
		clk_enable(info->lrclk);

		/* Enable i2s */
		ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 1);
	}

	/* Enable fifos */
	if (stream == SNDRV_PCM_STREAM_PLAYBACK)
		base_reg = EP93XX_I2S_TX0EN;
	else
		base_reg = EP93XX_I2S_RX0EN;
	for (i = 0; i < 3; i++)
		ep93xx_i2s_write_reg(info, base_reg + (i * 4), 1);
}

static void ep93xx_i2s_disable(struct ep93xx_i2s_info *info, int stream)
{
	unsigned base_reg;
	int i;

	/* Disable fifos */
	if (stream == SNDRV_PCM_STREAM_PLAYBACK)
		base_reg = EP93XX_I2S_TX0EN;
	else
		base_reg = EP93XX_I2S_RX0EN;
	for (i = 0; i < 3; i++)
		ep93xx_i2s_write_reg(info, base_reg + (i * 4), 0);

	if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
	    (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
		/* Disable i2s */
		ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 0);

		/* Disable clocks */
		clk_disable(info->lrclk);
		clk_disable(info->sclk);
		clk_disable(info->mclk);
	}
}

static int ep93xx_i2s_dai_probe(struct snd_soc_dai *dai)
{
	dai->playback_dma_data = &ep93xx_i2s_dma_data[SNDRV_PCM_STREAM_PLAYBACK];
	dai->capture_dma_data = &ep93xx_i2s_dma_data[SNDRV_PCM_STREAM_CAPTURE];

	return 0;
}

static void ep93xx_i2s_shutdown(struct snd_pcm_substream *substream,
				struct snd_soc_dai *dai)
{
	struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);

	ep93xx_i2s_disable(info, substream->stream);
}

static int ep93xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
				  unsigned int fmt)
{
	struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai);
	unsigned int clk_cfg, lin_ctrl;

	clk_cfg  = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXCLKCFG);
	lin_ctrl = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXLINCTRLDATA);

	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_I2S:
		clk_cfg |= EP93XX_I2S_CLKCFG_REL;
		lin_ctrl &= ~EP93XX_I2S_LINCTRLDATA_R_JUST;
		break;

	case SND_SOC_DAIFMT_LEFT_J:
		clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
		lin_ctrl &= ~EP93XX_I2S_LINCTRLDATA_R_JUST;
		break;

	case SND_SOC_DAIFMT_RIGHT_J:
		clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
		lin_ctrl |= EP93XX_I2S_LINCTRLDATA_R_JUST;
		break;

	default:
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		/* CPU is master */
		clk_cfg |= EP93XX_I2S_CLKCFG_MASTER;
		break;

	case SND_SOC_DAIFMT_CBM_CFM:
		/* Codec is master */
		clk_cfg &= ~EP93XX_I2S_CLKCFG_MASTER;
		break;

	default:
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_NB_NF:
		/* Negative bit clock, lrclk low on left word */
		clk_cfg &= ~(EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_REL);
		break;

	case SND_SOC_DAIFMT_NB_IF:
		/* Negative bit clock, lrclk low on right word */
		clk_cfg &= ~EP93XX_I2S_CLKCFG_CKP;
		clk_cfg |= EP93XX_I2S_CLKCFG_REL;
		break;

	case SND_SOC_DAIFMT_IB_NF:
		/* Positive bit clock, lrclk low on left word */
		clk_cfg |= EP93XX_I2S_CLKCFG_CKP;
		clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
		break;

	case SND_SOC_DAIFMT_IB_IF:
		/* Positive bit clock, lrclk low on right word */
		clk_cfg |= EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_REL;
		break;
	}

	/* Write new register values */
	ep93xx_i2s_write_reg(info, EP93XX_I2S_RXCLKCFG, clk_cfg);
	ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCLKCFG, clk_cfg);
	ep93xx_i2s_write_reg(info, EP93XX_I2S_RXLINCTRLDATA, lin_ctrl);
	ep93xx_i2s_write_reg(info, EP93XX_I2S_TXLINCTRLDATA, lin_ctrl);
	return 0;
}

static int ep93xx_i2s_hw_params(struct snd_pcm_substream *substream,
				struct snd_pcm_hw_params *params,
				struct snd_soc_dai *dai)
{
	struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
	unsigned word_len, div, sdiv, lrdiv;
	int err;

	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S16_LE:
		word_len = EP93XX_I2S_WRDLEN_16;
		break;

	case SNDRV_PCM_FORMAT_S24_LE:
		word_len = EP93XX_I2S_WRDLEN_24;
		break;

	case SNDRV_PCM_FORMAT_S32_LE:
		word_len = EP93XX_I2S_WRDLEN_32;
		break;

	default:
		return -EINVAL;
	}

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		ep93xx_i2s_write_reg(info, EP93XX_I2S_TXWRDLEN, word_len);
	else
		ep93xx_i2s_write_reg(info, EP93XX_I2S_RXWRDLEN, word_len);

	/*
	 * EP93xx I2S module can be setup so SCLK / LRCLK value can be
	 * 32, 64, 128. MCLK / SCLK value can be 2 and 4.
	 * We set LRCLK equal to `rate' and minimum SCLK / LRCLK 
	 * value is 64, because our sample size is 32 bit * 2 channels.
	 * I2S standard permits us to transmit more bits than
	 * the codec uses.
	 */
	div = clk_get_rate(info->mclk) / params_rate(params);
	sdiv = 4;
	if (div > (256 + 512) / 2) {
		lrdiv = 128;
	} else {
		lrdiv = 64;
		if (div < (128 + 256) / 2)
			sdiv = 2;
	}

	err = clk_set_rate(info->sclk, clk_get_rate(info->mclk) / sdiv);
	if (err)
		return err;

	err = clk_set_rate(info->lrclk, clk_get_rate(info->sclk) / lrdiv);
	if (err)
		return err;

	ep93xx_i2s_enable(info, substream->stream);
	return 0;
}

static int ep93xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
				 unsigned int freq, int dir)
{
	struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai);

	if (dir == SND_SOC_CLOCK_IN || clk_id != 0)
		return -EINVAL;

	return clk_set_rate(info->mclk, freq);
}

#ifdef CONFIG_PM
static int ep93xx_i2s_suspend(struct snd_soc_dai *dai)
{
	struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);

	if (!dai->active)
		return 0;

	ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_PLAYBACK);
	ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_CAPTURE);

	return 0;
}

static int ep93xx_i2s_resume(struct snd_soc_dai *dai)
{
	struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);

	if (!dai->active)
		return 0;

	ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_PLAYBACK);
	ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_CAPTURE);

	return 0;
}
#else
#define ep93xx_i2s_suspend	NULL
#define ep93xx_i2s_resume	NULL
#endif

static const struct snd_soc_dai_ops ep93xx_i2s_dai_ops = {
	.shutdown	= ep93xx_i2s_shutdown,
	.hw_params	= ep93xx_i2s_hw_params,
	.set_sysclk	= ep93xx_i2s_set_sysclk,
	.set_fmt	= ep93xx_i2s_set_dai_fmt,
};

#define EP93XX_I2S_FORMATS (SNDRV_PCM_FMTBIT_S32_LE)

static struct snd_soc_dai_driver ep93xx_i2s_dai = {
	.symmetric_rates= 1,
	.probe		= ep93xx_i2s_dai_probe,
	.suspend	= ep93xx_i2s_suspend,
	.resume		= ep93xx_i2s_resume,
	.playback	= {
		.channels_min	= 2,
		.channels_max	= 2,
		.rates		= SNDRV_PCM_RATE_8000_192000,
		.formats	= EP93XX_I2S_FORMATS,
	},
	.capture	= {
		 .channels_min	= 2,
		 .channels_max	= 2,
		 .rates		= SNDRV_PCM_RATE_8000_192000,
		 .formats	= EP93XX_I2S_FORMATS,
	},
	.ops		= &ep93xx_i2s_dai_ops,
};

static const struct snd_soc_component_driver ep93xx_i2s_component = {
	.name		= "ep93xx-i2s",
};

static int ep93xx_i2s_probe(struct platform_device *pdev)
{
	struct ep93xx_i2s_info *info;
	struct resource *res;
	int err;

	info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
	if (!info)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	info->regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(info->regs))
		return PTR_ERR(info->regs);

	info->mclk = clk_get(&pdev->dev, "mclk");
	if (IS_ERR(info->mclk)) {
		err = PTR_ERR(info->mclk);
		goto fail;
	}

	info->sclk = clk_get(&pdev->dev, "sclk");
	if (IS_ERR(info->sclk)) {
		err = PTR_ERR(info->sclk);
		goto fail_put_mclk;
	}

	info->lrclk = clk_get(&pdev->dev, "lrclk");
	if (IS_ERR(info->lrclk)) {
		err = PTR_ERR(info->lrclk);
		goto fail_put_sclk;
	}

	dev_set_drvdata(&pdev->dev, info);

	err = snd_soc_register_component(&pdev->dev, &ep93xx_i2s_component,
					 &ep93xx_i2s_dai, 1);
	if (err)
		goto fail_put_lrclk;

	err = devm_ep93xx_pcm_platform_register(&pdev->dev);
	if (err)
		goto fail_unregister;

	return 0;

fail_unregister:
	snd_soc_unregister_component(&pdev->dev);
fail_put_lrclk:
	clk_put(info->lrclk);
fail_put_sclk:
	clk_put(info->sclk);
fail_put_mclk:
	clk_put(info->mclk);
fail:
	return err;
}

static int ep93xx_i2s_remove(struct platform_device *pdev)
{
	struct ep93xx_i2s_info *info = dev_get_drvdata(&pdev->dev);

	snd_soc_unregister_component(&pdev->dev);
	clk_put(info->lrclk);
	clk_put(info->sclk);
	clk_put(info->mclk);
	return 0;
}

static struct platform_driver ep93xx_i2s_driver = {
	.probe	= ep93xx_i2s_probe,
	.remove	= ep93xx_i2s_remove,
	.driver	= {
		.name	= "ep93xx-i2s",
		.owner	= THIS_MODULE,
	},
};

module_platform_driver(ep93xx_i2s_driver);

MODULE_ALIAS("platform:ep93xx-i2s");
MODULE_AUTHOR("Ryan Mallon");
MODULE_DESCRIPTION("EP93XX I2S driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
db5bf412 RM	1	/*
	2	* linux/sound/soc/ep93xx-i2s.c
	3	* EP93xx I2S driver
	4	*
1c5454ee	5	* Copyright (C) 2010 Ryan Mallon
db5bf412 RM	6	*
	7	* Based on the original driver by:
	8	* Copyright (C) 2007 Chase Douglas <chasedouglas@gmail>
	9	* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*
	15	*/
	16
	17	#include <linux/module.h>
	18	#include <linux/init.h>
	19	#include <linux/slab.h>
	20	#include <linux/clk.h>
	21	#include <linux/io.h>
	22
	23	#include <sound/core.h>
	24	#include <sound/pcm.h>
	25	#include <sound/pcm_params.h>
	26	#include <sound/initval.h>
	27	#include <sound/soc.h>
	28
	29	#include <mach/hardware.h>
	30	#include <mach/ep93xx-regs.h>
a3b29245	31	#include <linux/platform_data/dma-ep93xx.h>
db5bf412	32
6f2032a1 SW	33	#include "ep93xx-pcm.h"
6f2032a1 SW	34
db5bf412 RM	35	#define EP93XX_I2S_TXCLKCFG 0x00
	36	#define EP93XX_I2S_RXCLKCFG 0x04
	37	#define EP93XX_I2S_GLCTRL 0x0C
	38
	39	#define EP93XX_I2S_TXLINCTRLDATA 0x28
	40	#define EP93XX_I2S_TXCTRL 0x2C
	41	#define EP93XX_I2S_TXWRDLEN 0x30
	42	#define EP93XX_I2S_TX0EN 0x34
	43
	44	#define EP93XX_I2S_RXLINCTRLDATA 0x58
	45	#define EP93XX_I2S_RXCTRL 0x5C
	46	#define EP93XX_I2S_RXWRDLEN 0x60
	47	#define EP93XX_I2S_RX0EN 0x64
	48
	49	#define EP93XX_I2S_WRDLEN_16 (0 << 0)
	50	#define EP93XX_I2S_WRDLEN_24 (1 << 0)
	51	#define EP93XX_I2S_WRDLEN_32 (2 << 0)
	52
	53	#define EP93XX_I2S_LINCTRLDATA_R_JUST (1 << 2) /* Right justify */
	54
	55	#define EP93XX_I2S_CLKCFG_LRS (1 << 0) /* lrclk polarity */
	56	#define EP93XX_I2S_CLKCFG_CKP (1 << 1) /* Bit clock polarity */
	57	#define EP93XX_I2S_CLKCFG_REL (1 << 2) /* First bit transition */
	58	#define EP93XX_I2S_CLKCFG_MASTER (1 << 3) /* Master mode */
	59	#define EP93XX_I2S_CLKCFG_NBCG (1 << 4) /* Not bit clock gating */
	60
	61	struct ep93xx_i2s_info {
	62	struct clk *mclk;
	63	struct clk *sclk;
	64	struct clk *lrclk;
db5bf412 RM	65	void __iomem *regs;
	66	};
	67
be87f75e	68	static struct ep93xx_dma_data ep93xx_i2s_dma_data[] = {
db5bf412 RM	69	[SNDRV_PCM_STREAM_PLAYBACK] = {
db5bf412 RM	70	.name = "i2s-pcm-out",
e6451c3f	71	.port = EP93XX_DMA_I2S1,
453807f3	72	.direction = DMA_MEM_TO_DEV,
db5bf412 RM	73	},
	74	[SNDRV_PCM_STREAM_CAPTURE] = {
	75	.name = "i2s-pcm-in",
e6451c3f	76	.port = EP93XX_DMA_I2S1,
453807f3	77	.direction = DMA_DEV_TO_MEM,
db5bf412 RM	78	},
	79	};
	80
	81	static inline void ep93xx_i2s_write_reg(struct ep93xx_i2s_info *info,
	82	unsigned reg, unsigned val)
	83	{
	84	__raw_writel(val, info->regs + reg);
	85	}
	86
	87	static inline unsigned ep93xx_i2s_read_reg(struct ep93xx_i2s_info *info,
	88	unsigned reg)
	89	{
	90	return __raw_readl(info->regs + reg);
	91	}
	92
	93	static void ep93xx_i2s_enable(struct ep93xx_i2s_info *info, int stream)
	94	{
	95	unsigned base_reg;
	96	int i;
	97
	98	if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
	99	(ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
	100	/* Enable clocks */
	101	clk_enable(info->mclk);
	102	clk_enable(info->sclk);
	103	clk_enable(info->lrclk);
	104
	105	/* Enable i2s */
	106	ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 1);
	107	}
	108
	109	/* Enable fifos */
	110	if (stream == SNDRV_PCM_STREAM_PLAYBACK)
	111	base_reg = EP93XX_I2S_TX0EN;
	112	else
	113	base_reg = EP93XX_I2S_RX0EN;
	114	for (i = 0; i < 3; i++)
	115	ep93xx_i2s_write_reg(info, base_reg + (i * 4), 1);
	116	}
	117
	118	static void ep93xx_i2s_disable(struct ep93xx_i2s_info *info, int stream)
	119	{
	120	unsigned base_reg;
	121	int i;
	122
	123	/* Disable fifos */
	124	if (stream == SNDRV_PCM_STREAM_PLAYBACK)
	125	base_reg = EP93XX_I2S_TX0EN;
	126	else
	127	base_reg = EP93XX_I2S_RX0EN;
	128	for (i = 0; i < 3; i++)
	129	ep93xx_i2s_write_reg(info, base_reg + (i * 4), 0);
	130
	131	if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
	132	(ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
	133	/* Disable i2s */
	134	ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 0);
	135
	136	/* Disable clocks */
	137	clk_disable(info->lrclk);
	138	clk_disable(info->sclk);
	139	clk_disable(info->mclk);
	140	}
	141	}
142
785d81e2	143	static int ep93xx_i2s_dai_probe(struct snd_soc_dai *dai)
db5bf412	144	{
785d81e2 LPC	145	dai->playback_dma_data = &ep93xx_i2s_dma_data[SNDRV_PCM_STREAM_PLAYBACK];
785d81e2 LPC	146	dai->capture_dma_data = &ep93xx_i2s_dma_data[SNDRV_PCM_STREAM_CAPTURE];
db5bf412	147
db5bf412 RM	148	return 0;
	149	}
	150
	151	static void ep93xx_i2s_shutdown(struct snd_pcm_substream *substream,
	152	struct snd_soc_dai *dai)
	153	{
f0fba2ad	154	struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
db5bf412 RM	155
	156	ep93xx_i2s_disable(info, substream->stream);
	157	}
	158
	159	static int ep93xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
	160	unsigned int fmt)
	161	{
f0fba2ad	162	struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai);
db5bf412 RM	163	unsigned int clk_cfg, lin_ctrl;
	164
	165	clk_cfg = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXCLKCFG);
	166	lin_ctrl = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXLINCTRLDATA);
	167
	168	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	169	case SND_SOC_DAIFMT_I2S:
	170	clk_cfg \|= EP93XX_I2S_CLKCFG_REL;
	171	lin_ctrl &= ~EP93XX_I2S_LINCTRLDATA_R_JUST;
	172	break;
	173
	174	case SND_SOC_DAIFMT_LEFT_J:
	175	clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
	176	lin_ctrl &= ~EP93XX_I2S_LINCTRLDATA_R_JUST;
	177	break;
	178
	179	case SND_SOC_DAIFMT_RIGHT_J:
	180	clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
	181	lin_ctrl \|= EP93XX_I2S_LINCTRLDATA_R_JUST;
	182	break;
	183
	184	default:
	185	return -EINVAL;
	186	}
	187
	188	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	189	case SND_SOC_DAIFMT_CBS_CFS:
	190	/* CPU is master */
	191	clk_cfg \|= EP93XX_I2S_CLKCFG_MASTER;
	192	break;
	193
	194	case SND_SOC_DAIFMT_CBM_CFM:
	195	/* Codec is master */
	196	clk_cfg &= ~EP93XX_I2S_CLKCFG_MASTER;
	197	break;
	198
	199	default:
	200	return -EINVAL;
	201	}
	202
	203	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	204	case SND_SOC_DAIFMT_NB_NF:
	205	/* Negative bit clock, lrclk low on left word */
	206	clk_cfg &= ~(EP93XX_I2S_CLKCFG_CKP \| EP93XX_I2S_CLKCFG_REL);
	207	break;
	208
	209	case SND_SOC_DAIFMT_NB_IF:
	210	/* Negative bit clock, lrclk low on right word */
	211	clk_cfg &= ~EP93XX_I2S_CLKCFG_CKP;
	212	clk_cfg \|= EP93XX_I2S_CLKCFG_REL;
	213	break;
	214
	215	case SND_SOC_DAIFMT_IB_NF:
	216	/* Positive bit clock, lrclk low on left word */
	217	clk_cfg \|= EP93XX_I2S_CLKCFG_CKP;
	218	clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
	219	break;
	220
	221	case SND_SOC_DAIFMT_IB_IF:
	222	/* Positive bit clock, lrclk low on right word */
	223	clk_cfg \|= EP93XX_I2S_CLKCFG_CKP \| EP93XX_I2S_CLKCFG_REL;
	224	break;
	225	}
	226
227	/* Write new register values */
228	ep93xx_i2s_write_reg(info, EP93XX_I2S_RXCLKCFG, clk_cfg);
229	ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCLKCFG, clk_cfg);
230	ep93xx_i2s_write_reg(info, EP93XX_I2S_RXLINCTRLDATA, lin_ctrl);
231	ep93xx_i2s_write_reg(info, EP93XX_I2S_TXLINCTRLDATA, lin_ctrl);
232	return 0;
233	}
234
235	static int ep93xx_i2s_hw_params(struct snd_pcm_substream *substream,
236	struct snd_pcm_hw_params *params,
237	struct snd_soc_dai *dai)
238	{
f0fba2ad	239	struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
db5bf412	240	unsigned word_len, div, sdiv, lrdiv;
5cbf7e49	241	int err;
db5bf412 RM	242
	243	switch (params_format(params)) {
	244	case SNDRV_PCM_FORMAT_S16_LE:
	245	word_len = EP93XX_I2S_WRDLEN_16;
	246	break;
	247
	248	case SNDRV_PCM_FORMAT_S24_LE:
	249	word_len = EP93XX_I2S_WRDLEN_24;
	250	break;
	251
	252	case SNDRV_PCM_FORMAT_S32_LE:
	253	word_len = EP93XX_I2S_WRDLEN_32;
	254	break;
	255
	256	default:
	257	return -EINVAL;
	258	}
	259
	260	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	261	ep93xx_i2s_write_reg(info, EP93XX_I2S_TXWRDLEN, word_len);
	262	else
	263	ep93xx_i2s_write_reg(info, EP93XX_I2S_RXWRDLEN, word_len);
	264
	265	/*
7322ce21 AS	266	* EP93xx I2S module can be setup so SCLK / LRCLK value can be
	267	* 32, 64, 128. MCLK / SCLK value can be 2 and 4.
	268	* We set LRCLK equal to `rate' and minimum SCLK / LRCLK
	269	* value is 64, because our sample size is 32 bit * 2 channels.
	270	* I2S standard permits us to transmit more bits than
	271	* the codec uses.
db5bf412	272	*/
7322ce21	273	div = clk_get_rate(info->mclk) / params_rate(params);
5cbf7e49 AS	274	sdiv = 4;
	275	if (div > (256 + 512) / 2) {
	276	lrdiv = 128;
	277	} else {
	278	lrdiv = 64;
	279	if (div < (128 + 256) / 2)
	280	sdiv = 2;
	281	}
db5bf412 RM	282
	283	err = clk_set_rate(info->sclk, clk_get_rate(info->mclk) / sdiv);
	284	if (err)
	285	return err;
	286
	287	err = clk_set_rate(info->lrclk, clk_get_rate(info->sclk) / lrdiv);
	288	if (err)
	289	return err;
	290
	291	ep93xx_i2s_enable(info, substream->stream);
	292	return 0;
	293	}
	294
	295	static int ep93xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
	296	unsigned int freq, int dir)
	297	{
f0fba2ad	298	struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai);
db5bf412 RM	299
	300	if (dir == SND_SOC_CLOCK_IN \|\| clk_id != 0)
	301	return -EINVAL;
	302
	303	return clk_set_rate(info->mclk, freq);
	304	}
	305
	306	#ifdef CONFIG_PM
	307	static int ep93xx_i2s_suspend(struct snd_soc_dai *dai)
	308	{
f0fba2ad	309	struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
db5bf412 RM	310
db5bf412 RM	311	if (!dai->active)
f9c54045	312	return 0;
db5bf412 RM	313
	314	ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_PLAYBACK);
	315	ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_CAPTURE);
f9c54045 AS	316
f9c54045 AS	317	return 0;
db5bf412 RM	318	}
	319
	320	static int ep93xx_i2s_resume(struct snd_soc_dai *dai)
	321	{
f0fba2ad	322	struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
db5bf412 RM	323
db5bf412 RM	324	if (!dai->active)
f9c54045	325	return 0;
db5bf412 RM	326
	327	ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_PLAYBACK);
	328	ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_CAPTURE);
f9c54045 AS	329
f9c54045 AS	330	return 0;
db5bf412 RM	331	}
	332	#else
	333	#define ep93xx_i2s_suspend NULL
	334	#define ep93xx_i2s_resume NULL
	335	#endif
	336
85e7652d	337	static const struct snd_soc_dai_ops ep93xx_i2s_dai_ops = {
db5bf412 RM	338	.shutdown = ep93xx_i2s_shutdown,
	339	.hw_params = ep93xx_i2s_hw_params,
	340	.set_sysclk = ep93xx_i2s_set_sysclk,
	341	.set_fmt = ep93xx_i2s_set_dai_fmt,
	342	};
	343
7322ce21	344	#define EP93XX_I2S_FORMATS (SNDRV_PCM_FMTBIT_S32_LE)
db5bf412	345
f0fba2ad	346	static struct snd_soc_dai_driver ep93xx_i2s_dai = {
db5bf412	347	.symmetric_rates= 1,
785d81e2	348	.probe = ep93xx_i2s_dai_probe,
db5bf412 RM	349	.suspend = ep93xx_i2s_suspend,
	350	.resume = ep93xx_i2s_resume,
	351	.playback = {
	352	.channels_min = 2,
	353	.channels_max = 2,
4cfeb695	354	.rates = SNDRV_PCM_RATE_8000_192000,
db5bf412 RM	355	.formats = EP93XX_I2S_FORMATS,
	356	},
	357	.capture = {
	358	.channels_min = 2,
	359	.channels_max = 2,
4cfeb695	360	.rates = SNDRV_PCM_RATE_8000_192000,
db5bf412 RM	361	.formats = EP93XX_I2S_FORMATS,
	362	},
	363	.ops = &ep93xx_i2s_dai_ops,
	364	};
db5bf412	365
ec050851 KM	366	static const struct snd_soc_component_driver ep93xx_i2s_component = {
	367	.name = "ep93xx-i2s",
	368	};
	369
db5bf412 RM	370	static int ep93xx_i2s_probe(struct platform_device *pdev)
	371	{
	372	struct ep93xx_i2s_info *info;
	373	struct resource *res;
	374	int err;
	375
01651bab HS	376	info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
	377	if (!info)
	378	return -ENOMEM;
db5bf412 RM	379
db5bf412 RM	380	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b25b5aa0 TR	381	info->regs = devm_ioremap_resource(&pdev->dev, res);
	382	if (IS_ERR(info->regs))
	383	return PTR_ERR(info->regs);
db5bf412 RM	384
	385	info->mclk = clk_get(&pdev->dev, "mclk");
	386	if (IS_ERR(info->mclk)) {
	387	err = PTR_ERR(info->mclk);
01651bab	388	goto fail;
db5bf412 RM	389	}
	390
	391	info->sclk = clk_get(&pdev->dev, "sclk");
	392	if (IS_ERR(info->sclk)) {
	393	err = PTR_ERR(info->sclk);
	394	goto fail_put_mclk;
	395	}
	396
	397	info->lrclk = clk_get(&pdev->dev, "lrclk");
	398	if (IS_ERR(info->lrclk)) {
	399	err = PTR_ERR(info->lrclk);
	400	goto fail_put_sclk;
	401	}
	402
01651bab	403	dev_set_drvdata(&pdev->dev, info);
01651bab	404
ec050851 KM	405	err = snd_soc_register_component(&pdev->dev, &ep93xx_i2s_component,
ec050851 KM	406	&ep93xx_i2s_dai, 1);
db5bf412 RM	407	if (err)
	408	goto fail_put_lrclk;
	409
6f2032a1 SW	410	err = devm_ep93xx_pcm_platform_register(&pdev->dev);
	411	if (err)
	412	goto fail_unregister;
	413
db5bf412 RM	414	return 0;
db5bf412 RM	415
6f2032a1 SW	416	fail_unregister:
6f2032a1 SW	417	snd_soc_unregister_component(&pdev->dev);
db5bf412 RM	418	fail_put_lrclk:
	419	clk_put(info->lrclk);
	420	fail_put_sclk:
	421	clk_put(info->sclk);
	422	fail_put_mclk:
	423	clk_put(info->mclk);
db5bf412 RM	424	fail:
	425	return err;
	426	}
	427
145e2879	428	static int ep93xx_i2s_remove(struct platform_device *pdev)
db5bf412	429	{
f0fba2ad	430	struct ep93xx_i2s_info *info = dev_get_drvdata(&pdev->dev);
db5bf412	431
ec050851	432	snd_soc_unregister_component(&pdev->dev);
db5bf412 RM	433	clk_put(info->lrclk);
	434	clk_put(info->sclk);
	435	clk_put(info->mclk);
db5bf412 RM	436	return 0;
	437	}
	438
	439	static struct platform_driver ep93xx_i2s_driver = {
	440	.probe = ep93xx_i2s_probe,
145e2879	441	.remove = ep93xx_i2s_remove,
db5bf412 RM	442	.driver = {
	443	.name = "ep93xx-i2s",
	444	.owner = THIS_MODULE,
	445	},
	446	};
	447
ee18f631	448	module_platform_driver(ep93xx_i2s_driver);
db5bf412 RM	449
db5bf412 RM	450	MODULE_ALIAS("platform:ep93xx-i2s");
1c5454ee	451	MODULE_AUTHOR("Ryan Mallon");
db5bf412 RM	452	MODULE_DESCRIPTION("EP93XX I2S driver");
db5bf412 RM	453	MODULE_LICENSE("GPL");