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ASoC: ab8500-codec: Drop bank prefix from AB8500_GPIO_DIR4_REG register define
[deliverable/linux.git] / sound / soc / codecs / ab8500-codec.c
CommitLineData
679d7abd
OL		 1/*
2 * Copyright (C) ST-Ericsson SA 2012
3 *
4 * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
5 * Kristoffer Karlsson <kristoffer.karlsson@stericsson.com>,
6 * Roger Nilsson <roger.xr.nilsson@stericsson.com>,
7 * for ST-Ericsson.
8 *
9 * Based on the early work done by:
10 * Mikko J. Lehto <mikko.lehto@symbio.com>,
11 * Mikko Sarmanne <mikko.sarmanne@symbio.com>,
12 * Jarmo K. Kuronen <jarmo.kuronen@symbio.com>,
13 * for ST-Ericsson.
14 *
15 * License terms:
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License version 2 as published
19 * by the Free Software Foundation.
20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/device.h>
25#include <linux/slab.h>
26#include <linux/moduleparam.h>
27#include <linux/init.h>
28#include <linux/delay.h>
29#include <linux/pm.h>
30#include <linux/platform_device.h>
31#include <linux/mutex.h>
32#include <linux/mfd/abx500/ab8500.h>
33#include <linux/mfd/abx500.h>
34#include <linux/mfd/abx500/ab8500-sysctrl.h>
35#include <linux/mfd/abx500/ab8500-codec.h>
36#include <linux/regulator/consumer.h>
db5c811d 37#include <linux/of.h>
679d7abd
OL		 38
39#include <sound/core.h>
40#include <sound/pcm.h>
41#include <sound/pcm_params.h>
42#include <sound/initval.h>
43#include <sound/soc.h>
44#include <sound/soc-dapm.h>
45#include <sound/tlv.h>
46
47#include "ab8500-codec.h"
48
49/* Macrocell value definitions */
50#define CLK_32K_OUT2_DISABLE 0x01
51#define INACTIVE_RESET_AUDIO 0x02
52#define ENABLE_AUDIO_CLK_TO_AUDIO_BLK 0x10
53#define ENABLE_VINTCORE12_SUPPLY 0x04
54#define GPIO27_DIR_OUTPUT 0x04
55#define GPIO29_DIR_OUTPUT 0x10
56#define GPIO31_DIR_OUTPUT 0x40
57
58/* Macrocell register definitions */
6391fffb 59#define AB8500_GPIO_DIR4_REG 0x13 /* Bank AB8500_MISC */
679d7abd
OL		 60
61/* Nr of FIR/IIR-coeff banks in ANC-block */
62#define AB8500_NR_OF_ANC_COEFF_BANKS 2
63
64/* Minimum duration to keep ANC IIR Init bit high or
65low before proceeding with the configuration sequence */
66#define AB8500_ANC_SM_DELAY 2000
67
68#define AB8500_FILTER_CONTROL(xname, xcount, xmin, xmax) \
69{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
70 .info = filter_control_info, \
71 .get = filter_control_get, .put = filter_control_put, \
72 .private_value = (unsigned long)&(struct filter_control) \
73 {.count = xcount, .min = xmin, .max = xmax} }
74
75struct filter_control {
76 long min, max;
77 unsigned int count;
78 long value[128];
79};
80
81/* Sidetone states */
82static const char * const enum_sid_state[] = {
83 "Unconfigured",
84 "Apply FIR",
85 "FIR is configured",
86};
87enum sid_state {
88 SID_UNCONFIGURED = 0,
89 SID_APPLY_FIR = 1,
90 SID_FIR_CONFIGURED = 2,
91};
92
93static const char * const enum_anc_state[] = {
94 "Unconfigured",
95 "Apply FIR and IIR",
96 "FIR and IIR are configured",
97 "Apply FIR",
98 "FIR is configured",
99 "Apply IIR",
100 "IIR is configured"
101};
102enum anc_state {
103 ANC_UNCONFIGURED = 0,
104 ANC_APPLY_FIR_IIR = 1,
105 ANC_FIR_IIR_CONFIGURED = 2,
106 ANC_APPLY_FIR = 3,
107 ANC_FIR_CONFIGURED = 4,
108 ANC_APPLY_IIR = 5,
109 ANC_IIR_CONFIGURED = 6
110};
111
112/* Analog microphones */
113enum amic_idx {
114 AMIC_IDX_1A,
115 AMIC_IDX_1B,
116 AMIC_IDX_2
117};
118
119struct ab8500_codec_drvdata_dbg {
120 struct regulator *vaud;
121 struct regulator *vamic1;
122 struct regulator *vamic2;
123 struct regulator *vdmic;
124};
125
126/* Private data for AB8500 device-driver */
127struct ab8500_codec_drvdata {
128 /* Sidetone */
129 long *sid_fir_values;
130 enum sid_state sid_status;
131
132 /* ANC */
133 struct mutex anc_lock;
134 long *anc_fir_values;
135 long *anc_iir_values;
136 enum anc_state anc_status;
137};
138
139static inline const char *amic_micbias_str(enum amic_micbias micbias)
140{
141 switch (micbias) {
142 case AMIC_MICBIAS_VAMIC1:
143 return "VAMIC1";
144 case AMIC_MICBIAS_VAMIC2:
145 return "VAMIC2";
146 default:
147 return "Unknown";
148 }
149}
150
151static inline const char *amic_type_str(enum amic_type type)
152{
153 switch (type) {
154 case AMIC_TYPE_DIFFERENTIAL:
155 return "DIFFERENTIAL";
156 case AMIC_TYPE_SINGLE_ENDED:
157 return "SINGLE ENDED";
158 default:
159 return "Unknown";
160 }
161}
162
163/*
164 * Read'n'write functions
165 */
166
167/* Read a register from the audio-bank of AB8500 */
63e6d43b
LJ		 168static unsigned int ab8500_codec_read_reg(struct snd_soc_codec *codec,
169 unsigned int reg)
679d7abd
OL		 170{
171 int status;
63e6d43b 172 unsigned int value = 0;
679d7abd
OL		 173
174 u8 value8;
63e6d43b
LJ		 175 status = abx500_get_register_interruptible(codec->dev, AB8500_AUDIO,
176 reg, &value8);
177 if (status < 0) {
178 dev_err(codec->dev,
179 "%s: ERROR: Register (0x%02x:0x%02x) read failed (%d).\n",
180 __func__, (u8)AB8500_AUDIO, (u8)reg, status);
181 } else {
182 dev_dbg(codec->dev,
183 "%s: Read 0x%02x from register 0x%02x:0x%02x\n",
184 __func__, value8, (u8)AB8500_AUDIO, (u8)reg);
185 value = (unsigned int)value8;
186 }
679d7abd 187
63e6d43b 188 return value;
679d7abd
OL		 189}
190
191/* Write to a register in the audio-bank of AB8500 */
63e6d43b
LJ		 192static int ab8500_codec_write_reg(struct snd_soc_codec *codec,
193 unsigned int reg, unsigned int value)
679d7abd 194{
63e6d43b 195 int status;
679d7abd 196
63e6d43b
LJ		 197 status = abx500_set_register_interruptible(codec->dev, AB8500_AUDIO,
198 reg, value);
199 if (status < 0)
200 dev_err(codec->dev,
201 "%s: ERROR: Register (%02x:%02x) write failed (%d).\n",
202 __func__, (u8)AB8500_AUDIO, (u8)reg, status);
203 else
204 dev_dbg(codec->dev,
205 "%s: Wrote 0x%02x into register %02x:%02x\n",
206 __func__, (u8)value, (u8)AB8500_AUDIO, (u8)reg);
679d7abd 207
63e6d43b
LJ		 208 return status;
209}
ff795d61 210
679d7abd
OL		 211/*
212 * Controls - DAPM
213 */
214
215/* Earpiece */
216
217/* Earpiece source selector */
218static const char * const enum_ear_lineout_source[] = {"Headset Left",
219 "Speaker Left"};
220static SOC_ENUM_SINGLE_DECL(dapm_enum_ear_lineout_source, AB8500_DMICFILTCONF,
221 AB8500_DMICFILTCONF_DA3TOEAR, enum_ear_lineout_source);
222static const struct snd_kcontrol_new dapm_ear_lineout_source =
223 SOC_DAPM_ENUM("Earpiece or LineOut Mono Source",
224 dapm_enum_ear_lineout_source);
225
226/* LineOut */
227
228/* LineOut source selector */
229static const char * const enum_lineout_source[] = {"Mono Path", "Stereo Path"};
230static SOC_ENUM_DOUBLE_DECL(dapm_enum_lineout_source, AB8500_ANACONF5,
231 AB8500_ANACONF5_HSLDACTOLOL,
232 AB8500_ANACONF5_HSRDACTOLOR, enum_lineout_source);
233static const struct snd_kcontrol_new dapm_lineout_source[] = {
234 SOC_DAPM_ENUM("LineOut Source", dapm_enum_lineout_source),
235};
236
237/* Handsfree */
238
239/* Speaker Left - ANC selector */
240static const char * const enum_HFx_sel[] = {"Audio Path", "ANC"};
241static SOC_ENUM_SINGLE_DECL(dapm_enum_HFl_sel, AB8500_DIGMULTCONF2,
242 AB8500_DIGMULTCONF2_HFLSEL, enum_HFx_sel);
243static const struct snd_kcontrol_new dapm_HFl_select[] = {
244 SOC_DAPM_ENUM("Speaker Left Source", dapm_enum_HFl_sel),
245};
246
247/* Speaker Right - ANC selector */
248static SOC_ENUM_SINGLE_DECL(dapm_enum_HFr_sel, AB8500_DIGMULTCONF2,
249 AB8500_DIGMULTCONF2_HFRSEL, enum_HFx_sel);
250static const struct snd_kcontrol_new dapm_HFr_select[] = {
251 SOC_DAPM_ENUM("Speaker Right Source", dapm_enum_HFr_sel),
252};
253
254/* Mic 1 */
255
256/* Mic 1 - Mic 1a or 1b selector */
257static const char * const enum_mic1ab_sel[] = {"Mic 1b", "Mic 1a"};
258static SOC_ENUM_SINGLE_DECL(dapm_enum_mic1ab_sel, AB8500_ANACONF3,
259 AB8500_ANACONF3_MIC1SEL, enum_mic1ab_sel);
260static const struct snd_kcontrol_new dapm_mic1ab_mux[] = {
261 SOC_DAPM_ENUM("Mic 1a or 1b Select", dapm_enum_mic1ab_sel),
262};
263
264/* Mic 1 - AD3 - Mic 1 or DMic 3 selector */
265static const char * const enum_ad3_sel[] = {"Mic 1", "DMic 3"};
266static SOC_ENUM_SINGLE_DECL(dapm_enum_ad3_sel, AB8500_DIGMULTCONF1,
267 AB8500_DIGMULTCONF1_AD3SEL, enum_ad3_sel);
268static const struct snd_kcontrol_new dapm_ad3_select[] = {
269 SOC_DAPM_ENUM("AD3 Source Select", dapm_enum_ad3_sel),
270};
271
272/* Mic 1 - AD6 - Mic 1 or DMic 6 selector */
273static const char * const enum_ad6_sel[] = {"Mic 1", "DMic 6"};
274static SOC_ENUM_SINGLE_DECL(dapm_enum_ad6_sel, AB8500_DIGMULTCONF1,
275 AB8500_DIGMULTCONF1_AD6SEL, enum_ad6_sel);
276static const struct snd_kcontrol_new dapm_ad6_select[] = {
277 SOC_DAPM_ENUM("AD6 Source Select", dapm_enum_ad6_sel),
278};
279
280/* Mic 2 */
281
282/* Mic 2 - AD5 - Mic 2 or DMic 5 selector */
283static const char * const enum_ad5_sel[] = {"Mic 2", "DMic 5"};
284static SOC_ENUM_SINGLE_DECL(dapm_enum_ad5_sel, AB8500_DIGMULTCONF1,
285 AB8500_DIGMULTCONF1_AD5SEL, enum_ad5_sel);
286static const struct snd_kcontrol_new dapm_ad5_select[] = {
287 SOC_DAPM_ENUM("AD5 Source Select", dapm_enum_ad5_sel),
288};
289
290/* LineIn */
291
292/* LineIn left - AD1 - LineIn Left or DMic 1 selector */
293static const char * const enum_ad1_sel[] = {"LineIn Left", "DMic 1"};
294static SOC_ENUM_SINGLE_DECL(dapm_enum_ad1_sel, AB8500_DIGMULTCONF1,
295 AB8500_DIGMULTCONF1_AD1SEL, enum_ad1_sel);
296static const struct snd_kcontrol_new dapm_ad1_select[] = {
297 SOC_DAPM_ENUM("AD1 Source Select", dapm_enum_ad1_sel),
298};
299
300/* LineIn right - Mic 2 or LineIn Right selector */
301static const char * const enum_mic2lr_sel[] = {"Mic 2", "LineIn Right"};
302static SOC_ENUM_SINGLE_DECL(dapm_enum_mic2lr_sel, AB8500_ANACONF3,
303 AB8500_ANACONF3_LINRSEL, enum_mic2lr_sel);
304static const struct snd_kcontrol_new dapm_mic2lr_select[] = {
305 SOC_DAPM_ENUM("Mic 2 or LINR Select", dapm_enum_mic2lr_sel),
306};
307
308/* LineIn right - AD2 - LineIn Right or DMic2 selector */
309static const char * const enum_ad2_sel[] = {"LineIn Right", "DMic 2"};
310static SOC_ENUM_SINGLE_DECL(dapm_enum_ad2_sel, AB8500_DIGMULTCONF1,
311 AB8500_DIGMULTCONF1_AD2SEL, enum_ad2_sel);
312static const struct snd_kcontrol_new dapm_ad2_select[] = {
313 SOC_DAPM_ENUM("AD2 Source Select", dapm_enum_ad2_sel),
314};
315
316
317/* ANC */
318
319static const char * const enum_anc_in_sel[] = {"Mic 1 / DMic 6",
320 "Mic 2 / DMic 5"};
321static SOC_ENUM_SINGLE_DECL(dapm_enum_anc_in_sel, AB8500_DMICFILTCONF,
322 AB8500_DMICFILTCONF_ANCINSEL, enum_anc_in_sel);
323static const struct snd_kcontrol_new dapm_anc_in_select[] = {
324 SOC_DAPM_ENUM("ANC Source", dapm_enum_anc_in_sel),
325};
326
327/* ANC - Enable/Disable */
328static const struct snd_kcontrol_new dapm_anc_enable[] = {
329 SOC_DAPM_SINGLE("Switch", AB8500_ANCCONF1,
330 AB8500_ANCCONF1_ENANC, 0, 0),
331};
332
333/* ANC to Earpiece - Mute */
334static const struct snd_kcontrol_new dapm_anc_ear_mute[] = {
335 SOC_DAPM_SINGLE("Switch", AB8500_DIGMULTCONF1,
336 AB8500_DIGMULTCONF1_ANCSEL, 1, 0),
337};
338
339
340
341/* Sidetone left */
342
343/* Sidetone left - Input selector */
344static const char * const enum_stfir1_in_sel[] = {
345 "LineIn Left", "LineIn Right", "Mic 1", "Headset Left"
346};
347static SOC_ENUM_SINGLE_DECL(dapm_enum_stfir1_in_sel, AB8500_DIGMULTCONF2,
348 AB8500_DIGMULTCONF2_FIRSID1SEL, enum_stfir1_in_sel);
349static const struct snd_kcontrol_new dapm_stfir1_in_select[] = {
350 SOC_DAPM_ENUM("Sidetone Left Source", dapm_enum_stfir1_in_sel),
351};
352
353/* Sidetone right path */
354
355/* Sidetone right - Input selector */
356static const char * const enum_stfir2_in_sel[] = {
357 "LineIn Right", "Mic 1", "DMic 4", "Headset Right"
358};
359static SOC_ENUM_SINGLE_DECL(dapm_enum_stfir2_in_sel, AB8500_DIGMULTCONF2,
360 AB8500_DIGMULTCONF2_FIRSID2SEL, enum_stfir2_in_sel);
361static const struct snd_kcontrol_new dapm_stfir2_in_select[] = {
362 SOC_DAPM_ENUM("Sidetone Right Source", dapm_enum_stfir2_in_sel),
363};
364
365/* Vibra */
366
367static const char * const enum_pwm2vibx[] = {"Audio Path", "PWM Generator"};
368
369static SOC_ENUM_SINGLE_DECL(dapm_enum_pwm2vib1, AB8500_PWMGENCONF1,
370 AB8500_PWMGENCONF1_PWMTOVIB1, enum_pwm2vibx);
371
372static const struct snd_kcontrol_new dapm_pwm2vib1[] = {
373 SOC_DAPM_ENUM("Vibra 1 Controller", dapm_enum_pwm2vib1),
374};
375
376static SOC_ENUM_SINGLE_DECL(dapm_enum_pwm2vib2, AB8500_PWMGENCONF1,
377 AB8500_PWMGENCONF1_PWMTOVIB2, enum_pwm2vibx);
378
379static const struct snd_kcontrol_new dapm_pwm2vib2[] = {
380 SOC_DAPM_ENUM("Vibra 2 Controller", dapm_enum_pwm2vib2),
381};
382
383/*
384 * DAPM-widgets
385 */
386
387static const struct snd_soc_dapm_widget ab8500_dapm_widgets[] = {
388
389 /* Clocks */
390 SND_SOC_DAPM_CLOCK_SUPPLY("audioclk"),
391
392 /* Regulators */
822b4b8d
MB		 393 SND_SOC_DAPM_REGULATOR_SUPPLY("V-AUD", 0, 0),
394 SND_SOC_DAPM_REGULATOR_SUPPLY("V-AMIC1", 0, 0),
395 SND_SOC_DAPM_REGULATOR_SUPPLY("V-AMIC2", 0, 0),
396 SND_SOC_DAPM_REGULATOR_SUPPLY("V-DMIC", 0, 0),
679d7abd
OL		 397
398 /* Power */
399 SND_SOC_DAPM_SUPPLY("Audio Power",
400 AB8500_POWERUP, AB8500_POWERUP_POWERUP, 0,
401 NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
402 SND_SOC_DAPM_SUPPLY("Audio Analog Power",
403 AB8500_POWERUP, AB8500_POWERUP_ENANA, 0,
404 NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
405
406 /* Main supply node */
407 SND_SOC_DAPM_SUPPLY("Main Supply", SND_SOC_NOPM, 0, 0,
408 NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
409
410 /* DA/AD */
411
412 SND_SOC_DAPM_INPUT("ADC Input"),
413 SND_SOC_DAPM_ADC("ADC", "ab8500_0c", SND_SOC_NOPM, 0, 0),
414
415 SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
416 SND_SOC_DAPM_OUTPUT("DAC Output"),
417
418 SND_SOC_DAPM_AIF_IN("DA_IN1", NULL, 0, SND_SOC_NOPM, 0, 0),
419 SND_SOC_DAPM_AIF_IN("DA_IN2", NULL, 0, SND_SOC_NOPM, 0, 0),
420 SND_SOC_DAPM_AIF_IN("DA_IN3", NULL, 0, SND_SOC_NOPM, 0, 0),
421 SND_SOC_DAPM_AIF_IN("DA_IN4", NULL, 0, SND_SOC_NOPM, 0, 0),
422 SND_SOC_DAPM_AIF_IN("DA_IN5", NULL, 0, SND_SOC_NOPM, 0, 0),
423 SND_SOC_DAPM_AIF_IN("DA_IN6", NULL, 0, SND_SOC_NOPM, 0, 0),
424 SND_SOC_DAPM_AIF_OUT("AD_OUT1", NULL, 0, SND_SOC_NOPM, 0, 0),
425 SND_SOC_DAPM_AIF_OUT("AD_OUT2", NULL, 0, SND_SOC_NOPM, 0, 0),
426 SND_SOC_DAPM_AIF_OUT("AD_OUT3", NULL, 0, SND_SOC_NOPM, 0, 0),
427 SND_SOC_DAPM_AIF_OUT("AD_OUT4", NULL, 0, SND_SOC_NOPM, 0, 0),
428 SND_SOC_DAPM_AIF_OUT("AD_OUT57", NULL, 0, SND_SOC_NOPM, 0, 0),
429 SND_SOC_DAPM_AIF_OUT("AD_OUT68", NULL, 0, SND_SOC_NOPM, 0, 0),
430
431 /* Headset path */
432
433 SND_SOC_DAPM_SUPPLY("Charge Pump", AB8500_ANACONF5,
434 AB8500_ANACONF5_ENCPHS, 0, NULL, 0),
435
436 SND_SOC_DAPM_DAC("DA1 Enable", "ab8500_0p",
437 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA1, 0),
438 SND_SOC_DAPM_DAC("DA2 Enable", "ab8500_0p",
439 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA2, 0),
440
441 SND_SOC_DAPM_PGA("HSL Digital Volume", SND_SOC_NOPM, 0, 0,
442 NULL, 0),
443 SND_SOC_DAPM_PGA("HSR Digital Volume", SND_SOC_NOPM, 0, 0,
444 NULL, 0),
445
446 SND_SOC_DAPM_DAC("HSL DAC", "ab8500_0p",
447 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHSL, 0),
448 SND_SOC_DAPM_DAC("HSR DAC", "ab8500_0p",
449 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHSR, 0),
450 SND_SOC_DAPM_MIXER("HSL DAC Mute", AB8500_MUTECONF,
451 AB8500_MUTECONF_MUTDACHSL, 1,
452 NULL, 0),
453 SND_SOC_DAPM_MIXER("HSR DAC Mute", AB8500_MUTECONF,
454 AB8500_MUTECONF_MUTDACHSR, 1,
455 NULL, 0),
456 SND_SOC_DAPM_DAC("HSL DAC Driver", "ab8500_0p",
457 AB8500_ANACONF3, AB8500_ANACONF3_ENDRVHSL, 0),
458 SND_SOC_DAPM_DAC("HSR DAC Driver", "ab8500_0p",
459 AB8500_ANACONF3, AB8500_ANACONF3_ENDRVHSR, 0),
460
461 SND_SOC_DAPM_MIXER("HSL Mute",
462 AB8500_MUTECONF, AB8500_MUTECONF_MUTHSL, 1,
463 NULL, 0),
464 SND_SOC_DAPM_MIXER("HSR Mute",
465 AB8500_MUTECONF, AB8500_MUTECONF_MUTHSR, 1,
466 NULL, 0),
467 SND_SOC_DAPM_MIXER("HSL Enable",
468 AB8500_ANACONF4, AB8500_ANACONF4_ENHSL, 0,
469 NULL, 0),
470 SND_SOC_DAPM_MIXER("HSR Enable",
471 AB8500_ANACONF4, AB8500_ANACONF4_ENHSR, 0,
472 NULL, 0),
473 SND_SOC_DAPM_PGA("HSL Volume",
474 SND_SOC_NOPM, 0, 0,
475 NULL, 0),
476 SND_SOC_DAPM_PGA("HSR Volume",
477 SND_SOC_NOPM, 0, 0,
478 NULL, 0),
479
480 SND_SOC_DAPM_OUTPUT("Headset Left"),
481 SND_SOC_DAPM_OUTPUT("Headset Right"),
482
483 /* LineOut path */
484
485 SND_SOC_DAPM_MUX("LineOut Source",
486 SND_SOC_NOPM, 0, 0, dapm_lineout_source),
487
488 SND_SOC_DAPM_MIXER("LOL Disable HFL",
489 AB8500_ANACONF4, AB8500_ANACONF4_ENHFL, 1,
490 NULL, 0),
491 SND_SOC_DAPM_MIXER("LOR Disable HFR",
492 AB8500_ANACONF4, AB8500_ANACONF4_ENHFR, 1,
493 NULL, 0),
494
495 SND_SOC_DAPM_MIXER("LOL Enable",
496 AB8500_ANACONF5, AB8500_ANACONF5_ENLOL, 0,
497 NULL, 0),
498 SND_SOC_DAPM_MIXER("LOR Enable",
499 AB8500_ANACONF5, AB8500_ANACONF5_ENLOR, 0,
500 NULL, 0),
501
502 SND_SOC_DAPM_OUTPUT("LineOut Left"),
503 SND_SOC_DAPM_OUTPUT("LineOut Right"),
504
505 /* Earpiece path */
506
507 SND_SOC_DAPM_MUX("Earpiece or LineOut Mono Source",
508 SND_SOC_NOPM, 0, 0, &dapm_ear_lineout_source),
509 SND_SOC_DAPM_MIXER("EAR DAC",
510 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACEAR, 0,
511 NULL, 0),
512 SND_SOC_DAPM_MIXER("EAR Mute",
513 AB8500_MUTECONF, AB8500_MUTECONF_MUTEAR, 1,
514 NULL, 0),
515 SND_SOC_DAPM_MIXER("EAR Enable",
516 AB8500_ANACONF4, AB8500_ANACONF4_ENEAR, 0,
517 NULL, 0),
518
519 SND_SOC_DAPM_OUTPUT("Earpiece"),
520
521 /* Handsfree path */
522
523 SND_SOC_DAPM_MIXER("DA3 Channel Volume",
524 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA3, 0,
525 NULL, 0),
526 SND_SOC_DAPM_MIXER("DA4 Channel Volume",
527 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA4, 0,
528 NULL, 0),
529 SND_SOC_DAPM_MUX("Speaker Left Source",
530 SND_SOC_NOPM, 0, 0, dapm_HFl_select),
531 SND_SOC_DAPM_MUX("Speaker Right Source",
532 SND_SOC_NOPM, 0, 0, dapm_HFr_select),
533 SND_SOC_DAPM_MIXER("HFL DAC", AB8500_DAPATHCONF,
534 AB8500_DAPATHCONF_ENDACHFL, 0,
535 NULL, 0),
536 SND_SOC_DAPM_MIXER("HFR DAC",
537 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHFR, 0,
538 NULL, 0),
539 SND_SOC_DAPM_MIXER("DA4 or ANC path to HfR",
540 AB8500_DIGMULTCONF2, AB8500_DIGMULTCONF2_DATOHFREN, 0,
541 NULL, 0),
542 SND_SOC_DAPM_MIXER("DA3 or ANC path to HfL",
543 AB8500_DIGMULTCONF2, AB8500_DIGMULTCONF2_DATOHFLEN, 0,
544 NULL, 0),
545 SND_SOC_DAPM_MIXER("HFL Enable",
546 AB8500_ANACONF4, AB8500_ANACONF4_ENHFL, 0,
547 NULL, 0),
548 SND_SOC_DAPM_MIXER("HFR Enable",
549 AB8500_ANACONF4, AB8500_ANACONF4_ENHFR, 0,
550 NULL, 0),
551
552 SND_SOC_DAPM_OUTPUT("Speaker Left"),
553 SND_SOC_DAPM_OUTPUT("Speaker Right"),
554
555 /* Vibrator path */
556
557 SND_SOC_DAPM_INPUT("PWMGEN1"),
558 SND_SOC_DAPM_INPUT("PWMGEN2"),
559
560 SND_SOC_DAPM_MIXER("DA5 Channel Volume",
561 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA5, 0,
562 NULL, 0),
563 SND_SOC_DAPM_MIXER("DA6 Channel Volume",
564 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA6, 0,
565 NULL, 0),
566 SND_SOC_DAPM_MIXER("VIB1 DAC",
567 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACVIB1, 0,
568 NULL, 0),
569 SND_SOC_DAPM_MIXER("VIB2 DAC",
570 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACVIB2, 0,
571 NULL, 0),
572 SND_SOC_DAPM_MUX("Vibra 1 Controller",
573 SND_SOC_NOPM, 0, 0, dapm_pwm2vib1),
574 SND_SOC_DAPM_MUX("Vibra 2 Controller",
575 SND_SOC_NOPM, 0, 0, dapm_pwm2vib2),
576 SND_SOC_DAPM_MIXER("VIB1 Enable",
577 AB8500_ANACONF4, AB8500_ANACONF4_ENVIB1, 0,
578 NULL, 0),
579 SND_SOC_DAPM_MIXER("VIB2 Enable",
580 AB8500_ANACONF4, AB8500_ANACONF4_ENVIB2, 0,
581 NULL, 0),
582
583 SND_SOC_DAPM_OUTPUT("Vibra 1"),
584 SND_SOC_DAPM_OUTPUT("Vibra 2"),
585
586 /* Mic 1 */
587
588 SND_SOC_DAPM_INPUT("Mic 1"),
589
590 SND_SOC_DAPM_MUX("Mic 1a or 1b Select",
591 SND_SOC_NOPM, 0, 0, dapm_mic1ab_mux),
592 SND_SOC_DAPM_MIXER("MIC1 Mute",
593 AB8500_ANACONF2, AB8500_ANACONF2_MUTMIC1, 1,
594 NULL, 0),
595 SND_SOC_DAPM_MIXER("MIC1A V-AMICx Enable",
596 AB8500_ANACONF2, AB8500_ANACONF2_ENMIC1, 0,
597 NULL, 0),
598 SND_SOC_DAPM_MIXER("MIC1B V-AMICx Enable",
599 AB8500_ANACONF2, AB8500_ANACONF2_ENMIC1, 0,
600 NULL, 0),
601 SND_SOC_DAPM_MIXER("MIC1 ADC",
602 AB8500_ANACONF3, AB8500_ANACONF3_ENADCMIC, 0,
603 NULL, 0),
604 SND_SOC_DAPM_MUX("AD3 Source Select",
605 SND_SOC_NOPM, 0, 0, dapm_ad3_select),
606 SND_SOC_DAPM_MIXER("AD3 Channel Volume",
607 SND_SOC_NOPM, 0, 0,
608 NULL, 0),
609 SND_SOC_DAPM_MIXER("AD3 Enable",
610 AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD34, 0,
611 NULL, 0),
612
613 /* Mic 2 */
614
615 SND_SOC_DAPM_INPUT("Mic 2"),
616
617 SND_SOC_DAPM_MIXER("MIC2 Mute",
618 AB8500_ANACONF2, AB8500_ANACONF2_MUTMIC2, 1,
619 NULL, 0),
620 SND_SOC_DAPM_MIXER("MIC2 V-AMICx Enable", AB8500_ANACONF2,
621 AB8500_ANACONF2_ENMIC2, 0,
622 NULL, 0),
623
624 /* LineIn */
625
626 SND_SOC_DAPM_INPUT("LineIn Left"),
627 SND_SOC_DAPM_INPUT("LineIn Right"),
628
629 SND_SOC_DAPM_MIXER("LINL Mute",
630 AB8500_ANACONF2, AB8500_ANACONF2_MUTLINL, 1,
631 NULL, 0),
632 SND_SOC_DAPM_MIXER("LINR Mute",
633 AB8500_ANACONF2, AB8500_ANACONF2_MUTLINR, 1,
634 NULL, 0),
635 SND_SOC_DAPM_MIXER("LINL Enable", AB8500_ANACONF2,
636 AB8500_ANACONF2_ENLINL, 0,
637 NULL, 0),
638 SND_SOC_DAPM_MIXER("LINR Enable", AB8500_ANACONF2,
639 AB8500_ANACONF2_ENLINR, 0,
640 NULL, 0),
641
642 /* LineIn Bypass path */
643 SND_SOC_DAPM_MIXER("LINL to HSL Volume",
644 SND_SOC_NOPM, 0, 0,
645 NULL, 0),
646 SND_SOC_DAPM_MIXER("LINR to HSR Volume",
647 SND_SOC_NOPM, 0, 0,
648 NULL, 0),
649
650 /* LineIn, Mic 2 */
651 SND_SOC_DAPM_MUX("Mic 2 or LINR Select",
652 SND_SOC_NOPM, 0, 0, dapm_mic2lr_select),
653 SND_SOC_DAPM_MIXER("LINL ADC", AB8500_ANACONF3,
654 AB8500_ANACONF3_ENADCLINL, 0,
655 NULL, 0),
656 SND_SOC_DAPM_MIXER("LINR ADC", AB8500_ANACONF3,
657 AB8500_ANACONF3_ENADCLINR, 0,
658 NULL, 0),
659 SND_SOC_DAPM_MUX("AD1 Source Select",
660 SND_SOC_NOPM, 0, 0, dapm_ad1_select),
661 SND_SOC_DAPM_MUX("AD2 Source Select",
662 SND_SOC_NOPM, 0, 0, dapm_ad2_select),
663 SND_SOC_DAPM_MIXER("AD1 Channel Volume",
664 SND_SOC_NOPM, 0, 0,
665 NULL, 0),
666 SND_SOC_DAPM_MIXER("AD2 Channel Volume",
667 SND_SOC_NOPM, 0, 0,
668 NULL, 0),
669
670 SND_SOC_DAPM_MIXER("AD12 Enable",
671 AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD12, 0,
672 NULL, 0),
673
674 /* HD Capture path */
675
676 SND_SOC_DAPM_MUX("AD5 Source Select",
677 SND_SOC_NOPM, 0, 0, dapm_ad5_select),
678 SND_SOC_DAPM_MUX("AD6 Source Select",
679 SND_SOC_NOPM, 0, 0, dapm_ad6_select),
680 SND_SOC_DAPM_MIXER("AD5 Channel Volume",
681 SND_SOC_NOPM, 0, 0,
682 NULL, 0),
683 SND_SOC_DAPM_MIXER("AD6 Channel Volume",
684 SND_SOC_NOPM, 0, 0,
685 NULL, 0),
686 SND_SOC_DAPM_MIXER("AD57 Enable",
687 AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD5768, 0,
688 NULL, 0),
689 SND_SOC_DAPM_MIXER("AD68 Enable",
690 AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD5768, 0,
691 NULL, 0),
692
693 /* Digital Microphone path */
694
695 SND_SOC_DAPM_INPUT("DMic 1"),
696 SND_SOC_DAPM_INPUT("DMic 2"),
697 SND_SOC_DAPM_INPUT("DMic 3"),
698 SND_SOC_DAPM_INPUT("DMic 4"),
699 SND_SOC_DAPM_INPUT("DMic 5"),
700 SND_SOC_DAPM_INPUT("DMic 6"),
701
702 SND_SOC_DAPM_MIXER("DMIC1",
703 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC1, 0,
704 NULL, 0),
705 SND_SOC_DAPM_MIXER("DMIC2",
706 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC2, 0,
707 NULL, 0),
708 SND_SOC_DAPM_MIXER("DMIC3",
709 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC3, 0,
710 NULL, 0),
711 SND_SOC_DAPM_MIXER("DMIC4",
712 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC4, 0,
713 NULL, 0),
714 SND_SOC_DAPM_MIXER("DMIC5",
715 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC5, 0,
716 NULL, 0),
717 SND_SOC_DAPM_MIXER("DMIC6",
718 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC6, 0,
719 NULL, 0),
720 SND_SOC_DAPM_MIXER("AD4 Channel Volume",
721 SND_SOC_NOPM, 0, 0,
722 NULL, 0),
723 SND_SOC_DAPM_MIXER("AD4 Enable",
724 AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD34,
725 0, NULL, 0),
726
727 /* Acoustical Noise Cancellation path */
728
729 SND_SOC_DAPM_INPUT("ANC Configure Input"),
730 SND_SOC_DAPM_OUTPUT("ANC Configure Output"),
731
732 SND_SOC_DAPM_MUX("ANC Source",
733 SND_SOC_NOPM, 0, 0,
734 dapm_anc_in_select),
735 SND_SOC_DAPM_SWITCH("ANC",
736 SND_SOC_NOPM, 0, 0,
737 dapm_anc_enable),
738 SND_SOC_DAPM_SWITCH("ANC to Earpiece",
739 SND_SOC_NOPM, 0, 0,
740 dapm_anc_ear_mute),
741
742 /* Sidetone Filter path */
743
744 SND_SOC_DAPM_MUX("Sidetone Left Source",
745 SND_SOC_NOPM, 0, 0,
746 dapm_stfir1_in_select),
747 SND_SOC_DAPM_MUX("Sidetone Right Source",
748 SND_SOC_NOPM, 0, 0,
749 dapm_stfir2_in_select),
750 SND_SOC_DAPM_MIXER("STFIR1 Control",
751 SND_SOC_NOPM, 0, 0,
752 NULL, 0),
753 SND_SOC_DAPM_MIXER("STFIR2 Control",
754 SND_SOC_NOPM, 0, 0,
755 NULL, 0),
756 SND_SOC_DAPM_MIXER("STFIR1 Volume",
757 SND_SOC_NOPM, 0, 0,
758 NULL, 0),
759 SND_SOC_DAPM_MIXER("STFIR2 Volume",
760 SND_SOC_NOPM, 0, 0,
761 NULL, 0),
762};
763
764/*
765 * DAPM-routes
766 */
767static const struct snd_soc_dapm_route ab8500_dapm_routes[] = {
768 /* Power AB8500 audio-block when AD/DA is active */
769 {"Main Supply", NULL, "V-AUD"},
770 {"Main Supply", NULL, "audioclk"},
771 {"Main Supply", NULL, "Audio Power"},
772 {"Main Supply", NULL, "Audio Analog Power"},
773
774 {"DAC", NULL, "ab8500_0p"},
775 {"DAC", NULL, "Main Supply"},
776 {"ADC", NULL, "ab8500_0c"},
777 {"ADC", NULL, "Main Supply"},
778
779 /* ANC Configure */
780 {"ANC Configure Input", NULL, "Main Supply"},
781 {"ANC Configure Output", NULL, "ANC Configure Input"},
782
783 /* AD/DA */
784 {"ADC", NULL, "ADC Input"},
785 {"DAC Output", NULL, "DAC"},
786
787 /* Powerup charge pump if DA1/2 is in use */
788
789 {"DA_IN1", NULL, "ab8500_0p"},
790 {"DA_IN1", NULL, "Charge Pump"},
791 {"DA_IN2", NULL, "ab8500_0p"},
792 {"DA_IN2", NULL, "Charge Pump"},
793
794 /* Headset path */
795
796 {"DA1 Enable", NULL, "DA_IN1"},
797 {"DA2 Enable", NULL, "DA_IN2"},
798
799 {"HSL Digital Volume", NULL, "DA1 Enable"},
800 {"HSR Digital Volume", NULL, "DA2 Enable"},
801
802 {"HSL DAC", NULL, "HSL Digital Volume"},
803 {"HSR DAC", NULL, "HSR Digital Volume"},
804
805 {"HSL DAC Mute", NULL, "HSL DAC"},
806 {"HSR DAC Mute", NULL, "HSR DAC"},
807
808 {"HSL DAC Driver", NULL, "HSL DAC Mute"},
809 {"HSR DAC Driver", NULL, "HSR DAC Mute"},
810
811 {"HSL Mute", NULL, "HSL DAC Driver"},
812 {"HSR Mute", NULL, "HSR DAC Driver"},
813
814 {"HSL Enable", NULL, "HSL Mute"},
815 {"HSR Enable", NULL, "HSR Mute"},
816
817 {"HSL Volume", NULL, "HSL Enable"},
818 {"HSR Volume", NULL, "HSR Enable"},
819
820 {"Headset Left", NULL, "HSL Volume"},
821 {"Headset Right", NULL, "HSR Volume"},
822
823 /* HF or LineOut path */
824
825 {"DA_IN3", NULL, "ab8500_0p"},
826 {"DA3 Channel Volume", NULL, "DA_IN3"},
827 {"DA_IN4", NULL, "ab8500_0p"},
828 {"DA4 Channel Volume", NULL, "DA_IN4"},
829
830 {"Speaker Left Source", "Audio Path", "DA3 Channel Volume"},
831 {"Speaker Right Source", "Audio Path", "DA4 Channel Volume"},
832
833 {"DA3 or ANC path to HfL", NULL, "Speaker Left Source"},
834 {"DA4 or ANC path to HfR", NULL, "Speaker Right Source"},
835
836 /* HF path */
837
838 {"HFL DAC", NULL, "DA3 or ANC path to HfL"},
839 {"HFR DAC", NULL, "DA4 or ANC path to HfR"},
840
841 {"HFL Enable", NULL, "HFL DAC"},
842 {"HFR Enable", NULL, "HFR DAC"},
843
844 {"Speaker Left", NULL, "HFL Enable"},
845 {"Speaker Right", NULL, "HFR Enable"},
846
847 /* Earpiece path */
848
849 {"Earpiece or LineOut Mono Source", "Headset Left",
850 "HSL Digital Volume"},
851 {"Earpiece or LineOut Mono Source", "Speaker Left",
852 "DA3 or ANC path to HfL"},
853
854 {"EAR DAC", NULL, "Earpiece or LineOut Mono Source"},
855
856 {"EAR Mute", NULL, "EAR DAC"},
857
858 {"EAR Enable", NULL, "EAR Mute"},
859
860 {"Earpiece", NULL, "EAR Enable"},
861
862 /* LineOut path stereo */
863
864 {"LineOut Source", "Stereo Path", "HSL DAC Driver"},
865 {"LineOut Source", "Stereo Path", "HSR DAC Driver"},
866
867 /* LineOut path mono */
868
869 {"LineOut Source", "Mono Path", "EAR DAC"},
870
871 /* LineOut path */
872
873 {"LOL Disable HFL", NULL, "LineOut Source"},
874 {"LOR Disable HFR", NULL, "LineOut Source"},
875
876 {"LOL Enable", NULL, "LOL Disable HFL"},
877 {"LOR Enable", NULL, "LOR Disable HFR"},
878
879 {"LineOut Left", NULL, "LOL Enable"},
880 {"LineOut Right", NULL, "LOR Enable"},
881
882 /* Vibrator path */
883
884 {"DA_IN5", NULL, "ab8500_0p"},
885 {"DA5 Channel Volume", NULL, "DA_IN5"},
886 {"DA_IN6", NULL, "ab8500_0p"},
887 {"DA6 Channel Volume", NULL, "DA_IN6"},
888
889 {"VIB1 DAC", NULL, "DA5 Channel Volume"},
890 {"VIB2 DAC", NULL, "DA6 Channel Volume"},
891
892 {"Vibra 1 Controller", "Audio Path", "VIB1 DAC"},
893 {"Vibra 2 Controller", "Audio Path", "VIB2 DAC"},
894 {"Vibra 1 Controller", "PWM Generator", "PWMGEN1"},
895 {"Vibra 2 Controller", "PWM Generator", "PWMGEN2"},
896
897 {"VIB1 Enable", NULL, "Vibra 1 Controller"},
898 {"VIB2 Enable", NULL, "Vibra 2 Controller"},
899
900 {"Vibra 1", NULL, "VIB1 Enable"},
901 {"Vibra 2", NULL, "VIB2 Enable"},
902
903
904 /* Mic 2 */
905
906 {"MIC2 V-AMICx Enable", NULL, "Mic 2"},
907
908 /* LineIn */
909 {"LINL Mute", NULL, "LineIn Left"},
910 {"LINR Mute", NULL, "LineIn Right"},
911
912 {"LINL Enable", NULL, "LINL Mute"},
913 {"LINR Enable", NULL, "LINR Mute"},
914
915 /* LineIn, Mic 2 */
916 {"Mic 2 or LINR Select", "LineIn Right", "LINR Enable"},
917 {"Mic 2 or LINR Select", "Mic 2", "MIC2 V-AMICx Enable"},
918
919 {"LINL ADC", NULL, "LINL Enable"},
920 {"LINR ADC", NULL, "Mic 2 or LINR Select"},
921
922 {"AD1 Source Select", "LineIn Left", "LINL ADC"},
923 {"AD2 Source Select", "LineIn Right", "LINR ADC"},
924
925 {"AD1 Channel Volume", NULL, "AD1 Source Select"},
926 {"AD2 Channel Volume", NULL, "AD2 Source Select"},
927
928 {"AD12 Enable", NULL, "AD1 Channel Volume"},
929 {"AD12 Enable", NULL, "AD2 Channel Volume"},
930
931 {"AD_OUT1", NULL, "ab8500_0c"},
932 {"AD_OUT1", NULL, "AD12 Enable"},
933 {"AD_OUT2", NULL, "ab8500_0c"},
934 {"AD_OUT2", NULL, "AD12 Enable"},
935
936 /* Mic 1 */
937
938 {"MIC1 Mute", NULL, "Mic 1"},
939
940 {"MIC1A V-AMICx Enable", NULL, "MIC1 Mute"},
941 {"MIC1B V-AMICx Enable", NULL, "MIC1 Mute"},
942
943 {"Mic 1a or 1b Select", "Mic 1a", "MIC1A V-AMICx Enable"},
944 {"Mic 1a or 1b Select", "Mic 1b", "MIC1B V-AMICx Enable"},
945
946 {"MIC1 ADC", NULL, "Mic 1a or 1b Select"},
947
948 {"AD3 Source Select", "Mic 1", "MIC1 ADC"},
949
950 {"AD3 Channel Volume", NULL, "AD3 Source Select"},
951
952 {"AD3 Enable", NULL, "AD3 Channel Volume"},
953
954 {"AD_OUT3", NULL, "ab8500_0c"},
955 {"AD_OUT3", NULL, "AD3 Enable"},
956
957 /* HD Capture path */
958
959 {"AD5 Source Select", "Mic 2", "LINR ADC"},
960 {"AD6 Source Select", "Mic 1", "MIC1 ADC"},
961
962 {"AD5 Channel Volume", NULL, "AD5 Source Select"},
963 {"AD6 Channel Volume", NULL, "AD6 Source Select"},
964
965 {"AD57 Enable", NULL, "AD5 Channel Volume"},
966 {"AD68 Enable", NULL, "AD6 Channel Volume"},
967
968 {"AD_OUT57", NULL, "ab8500_0c"},
969 {"AD_OUT57", NULL, "AD57 Enable"},
970 {"AD_OUT68", NULL, "ab8500_0c"},
971 {"AD_OUT68", NULL, "AD68 Enable"},
972
973 /* Digital Microphone path */
974
975 {"DMic 1", NULL, "V-DMIC"},
976 {"DMic 2", NULL, "V-DMIC"},
977 {"DMic 3", NULL, "V-DMIC"},
978 {"DMic 4", NULL, "V-DMIC"},
979 {"DMic 5", NULL, "V-DMIC"},
980 {"DMic 6", NULL, "V-DMIC"},
981
982 {"AD1 Source Select", NULL, "DMic 1"},
983 {"AD2 Source Select", NULL, "DMic 2"},
984 {"AD3 Source Select", NULL, "DMic 3"},
985 {"AD5 Source Select", NULL, "DMic 5"},
986 {"AD6 Source Select", NULL, "DMic 6"},
987
988 {"AD4 Channel Volume", NULL, "DMic 4"},
989 {"AD4 Enable", NULL, "AD4 Channel Volume"},
990
991 {"AD_OUT4", NULL, "ab8500_0c"},
992 {"AD_OUT4", NULL, "AD4 Enable"},
993
994 /* LineIn Bypass path */
995
996 {"LINL to HSL Volume", NULL, "LINL Enable"},
997 {"LINR to HSR Volume", NULL, "LINR Enable"},
998
999 {"HSL DAC Driver", NULL, "LINL to HSL Volume"},
1000 {"HSR DAC Driver", NULL, "LINR to HSR Volume"},
1001
1002 /* ANC path (Acoustic Noise Cancellation) */
1003
1004 {"ANC Source", "Mic 2 / DMic 5", "AD5 Channel Volume"},
1005 {"ANC Source", "Mic 1 / DMic 6", "AD6 Channel Volume"},
1006
1007 {"ANC", "Switch", "ANC Source"},
1008
1009 {"Speaker Left Source", "ANC", "ANC"},
1010 {"Speaker Right Source", "ANC", "ANC"},
1011 {"ANC to Earpiece", "Switch", "ANC"},
1012
1013 {"HSL Digital Volume", NULL, "ANC to Earpiece"},
1014
1015 /* Sidetone Filter path */
1016
1017 {"Sidetone Left Source", "LineIn Left", "AD12 Enable"},
1018 {"Sidetone Left Source", "LineIn Right", "AD12 Enable"},
1019 {"Sidetone Left Source", "Mic 1", "AD3 Enable"},
1020 {"Sidetone Left Source", "Headset Left", "DA_IN1"},
1021 {"Sidetone Right Source", "LineIn Right", "AD12 Enable"},
1022 {"Sidetone Right Source", "Mic 1", "AD3 Enable"},
1023 {"Sidetone Right Source", "DMic 4", "AD4 Enable"},
1024 {"Sidetone Right Source", "Headset Right", "DA_IN2"},
1025
1026 {"STFIR1 Control", NULL, "Sidetone Left Source"},
1027 {"STFIR2 Control", NULL, "Sidetone Right Source"},
1028
1029 {"STFIR1 Volume", NULL, "STFIR1 Control"},
1030 {"STFIR2 Volume", NULL, "STFIR2 Control"},
1031
1032 {"DA1 Enable", NULL, "STFIR1 Volume"},
1033 {"DA2 Enable", NULL, "STFIR2 Volume"},
1034};
1035
1036static const struct snd_soc_dapm_route ab8500_dapm_routes_mic1a_vamicx[] = {
1037 {"MIC1A V-AMICx Enable", NULL, "V-AMIC1"},
1038 {"MIC1A V-AMICx Enable", NULL, "V-AMIC2"},
1039};
1040
1041static const struct snd_soc_dapm_route ab8500_dapm_routes_mic1b_vamicx[] = {
1042 {"MIC1B V-AMICx Enable", NULL, "V-AMIC1"},
1043 {"MIC1B V-AMICx Enable", NULL, "V-AMIC2"},
1044};
1045
1046static const struct snd_soc_dapm_route ab8500_dapm_routes_mic2_vamicx[] = {
1047 {"MIC2 V-AMICx Enable", NULL, "V-AMIC1"},
1048 {"MIC2 V-AMICx Enable", NULL, "V-AMIC2"},
1049};
1050
1051/* ANC FIR-coefficients configuration sequence */
1052static void anc_fir(struct snd_soc_codec *codec,
1053 unsigned int bnk, unsigned int par, unsigned int val)
1054{
1055 if (par == 0 && bnk == 0)
1056 snd_soc_update_bits(codec, AB8500_ANCCONF1,
1057 BIT(AB8500_ANCCONF1_ANCFIRUPDATE),
1058 BIT(AB8500_ANCCONF1_ANCFIRUPDATE));
1059
1060 snd_soc_write(codec, AB8500_ANCCONF5, val >> 8 & 0xff);
1061 snd_soc_write(codec, AB8500_ANCCONF6, val & 0xff);
1062
1063 if (par == AB8500_ANC_FIR_COEFFS - 1 && bnk == 1)
1064 snd_soc_update_bits(codec, AB8500_ANCCONF1,
1065 BIT(AB8500_ANCCONF1_ANCFIRUPDATE), 0);
1066}
1067
1068/* ANC IIR-coefficients configuration sequence */
1069static void anc_iir(struct snd_soc_codec *codec, unsigned int bnk,
1070 unsigned int par, unsigned int val)
1071{
1072 if (par == 0) {
1073 if (bnk == 0) {
1074 snd_soc_update_bits(codec, AB8500_ANCCONF1,
1075 BIT(AB8500_ANCCONF1_ANCIIRINIT),
1076 BIT(AB8500_ANCCONF1_ANCIIRINIT));
1077 usleep_range(AB8500_ANC_SM_DELAY, AB8500_ANC_SM_DELAY);
1078 snd_soc_update_bits(codec, AB8500_ANCCONF1,
1079 BIT(AB8500_ANCCONF1_ANCIIRINIT), 0);
1080 usleep_range(AB8500_ANC_SM_DELAY, AB8500_ANC_SM_DELAY);
1081 } else {
1082 snd_soc_update_bits(codec, AB8500_ANCCONF1,
1083 BIT(AB8500_ANCCONF1_ANCIIRUPDATE),
1084 BIT(AB8500_ANCCONF1_ANCIIRUPDATE));
1085 }
1086 } else if (par > 3) {
1087 snd_soc_write(codec, AB8500_ANCCONF7, 0);
1088 snd_soc_write(codec, AB8500_ANCCONF8, val >> 16 & 0xff);
1089 }
1090
1091 snd_soc_write(codec, AB8500_ANCCONF7, val >> 8 & 0xff);
1092 snd_soc_write(codec, AB8500_ANCCONF8, val & 0xff);
1093
1094 if (par == AB8500_ANC_IIR_COEFFS - 1 && bnk == 1)
1095 snd_soc_update_bits(codec, AB8500_ANCCONF1,
1096 BIT(AB8500_ANCCONF1_ANCIIRUPDATE), 0);
1097}
1098
1099/* ANC IIR-/FIR-coefficients configuration sequence */
1100static void anc_configure(struct snd_soc_codec *codec,
1101 bool apply_fir, bool apply_iir)
1102{
1103 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(codec->dev);
1104 unsigned int bnk, par, val;
1105
1106 dev_dbg(codec->dev, "%s: Enter.\n", __func__);
1107
1108 if (apply_fir)
1109 snd_soc_update_bits(codec, AB8500_ANCCONF1,
1110 BIT(AB8500_ANCCONF1_ENANC), 0);
1111
1112 snd_soc_update_bits(codec, AB8500_ANCCONF1,
1113 BIT(AB8500_ANCCONF1_ENANC), BIT(AB8500_ANCCONF1_ENANC));
1114
1115 if (apply_fir)
1116 for (bnk = 0; bnk < AB8500_NR_OF_ANC_COEFF_BANKS; bnk++)
1117 for (par = 0; par < AB8500_ANC_FIR_COEFFS; par++) {
1118 val = snd_soc_read(codec,
1119 drvdata->anc_fir_values[par]);
1120 anc_fir(codec, bnk, par, val);
1121 }
1122
1123 if (apply_iir)
1124 for (bnk = 0; bnk < AB8500_NR_OF_ANC_COEFF_BANKS; bnk++)
1125 for (par = 0; par < AB8500_ANC_IIR_COEFFS; par++) {
1126 val = snd_soc_read(codec,
1127 drvdata->anc_iir_values[par]);
1128 anc_iir(codec, bnk, par, val);
1129 }
1130
1131 dev_dbg(codec->dev, "%s: Exit.\n", __func__);
1132}
1133
1134/*
1135 * Control-events
1136 */
1137
1138static int sid_status_control_get(struct snd_kcontrol *kcontrol,
1139 struct snd_ctl_elem_value *ucontrol)
1140{
ea53bf77 1141 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
679d7abd
OL		 1142 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(codec->dev);
1143
1144 mutex_lock(&codec->mutex);
1145 ucontrol->value.integer.value[0] = drvdata->sid_status;
1146 mutex_unlock(&codec->mutex);
1147
1148 return 0;
1149}
1150
1151/* Write sidetone FIR-coefficients configuration sequence */
1152static int sid_status_control_put(struct snd_kcontrol *kcontrol,
1153 struct snd_ctl_elem_value *ucontrol)
1154{
ea53bf77 1155 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
679d7abd
OL		 1156 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(codec->dev);
1157 unsigned int param, sidconf, val;
1158 int status = 1;
1159
1160 dev_dbg(codec->dev, "%s: Enter\n", __func__);
1161
1162 if (ucontrol->value.integer.value[0] != SID_APPLY_FIR) {
1163 dev_err(codec->dev,
1164 "%s: ERROR: This control supports '%s' only!\n",
1165 __func__, enum_sid_state[SID_APPLY_FIR]);
1166 return -EIO;
1167 }
1168
1169 mutex_lock(&codec->mutex);
1170
1171 sidconf = snd_soc_read(codec, AB8500_SIDFIRCONF);
1172 if (((sidconf & BIT(AB8500_SIDFIRCONF_FIRSIDBUSY)) != 0)) {
1173 if ((sidconf & BIT(AB8500_SIDFIRCONF_ENFIRSIDS)) == 0) {
1174 dev_err(codec->dev, "%s: Sidetone busy while off!\n",
1175 __func__);
1176 status = -EPERM;
1177 } else {
1178 status = -EBUSY;
1179 }
1180 goto out;
1181 }
1182
1183 snd_soc_write(codec, AB8500_SIDFIRADR, 0);
1184
1185 for (param = 0; param < AB8500_SID_FIR_COEFFS; param++) {
1186 val = snd_soc_read(codec, drvdata->sid_fir_values[param]);
1187 snd_soc_write(codec, AB8500_SIDFIRCOEF1, val >> 8 & 0xff);
1188 snd_soc_write(codec, AB8500_SIDFIRCOEF2, val & 0xff);
1189 }
1190
1191 snd_soc_update_bits(codec, AB8500_SIDFIRADR,
1192 BIT(AB8500_SIDFIRADR_FIRSIDSET),
1193 BIT(AB8500_SIDFIRADR_FIRSIDSET));
1194 snd_soc_update_bits(codec, AB8500_SIDFIRADR,
1195 BIT(AB8500_SIDFIRADR_FIRSIDSET), 0);
1196
1197 drvdata->sid_status = SID_FIR_CONFIGURED;
1198
1199out:
1200 mutex_unlock(&codec->mutex);
1201
1202 dev_dbg(codec->dev, "%s: Exit\n", __func__);
1203
1204 return status;
1205}
1206
1207static int anc_status_control_get(struct snd_kcontrol *kcontrol,
1208 struct snd_ctl_elem_value *ucontrol)
1209{
ea53bf77 1210 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
679d7abd
OL		 1211 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(codec->dev);
1212
1213 mutex_lock(&codec->mutex);
1214 ucontrol->value.integer.value[0] = drvdata->anc_status;
1215 mutex_unlock(&codec->mutex);
1216
1217 return 0;
1218}
1219
1220static int anc_status_control_put(struct snd_kcontrol *kcontrol,
1221 struct snd_ctl_elem_value *ucontrol)
1222{
ea53bf77 1223 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
679d7abd
OL		 1224 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(codec->dev);
1225 struct device *dev = codec->dev;
1226 bool apply_fir, apply_iir;
d63733ae
DC		 1227 unsigned int req;
1228 int status;
679d7abd
OL		 1229
1230 dev_dbg(dev, "%s: Enter.\n", __func__);
1231
1232 mutex_lock(&drvdata->anc_lock);
1233
1234 req = ucontrol->value.integer.value[0];
d63733ae
DC		 1235 if (req >= ARRAY_SIZE(enum_anc_state)) {
1236 status = -EINVAL;
1237 goto cleanup;
1238 }
679d7abd
OL		 1239 if (req != ANC_APPLY_FIR_IIR && req != ANC_APPLY_FIR &&
1240 req != ANC_APPLY_IIR) {
1241 dev_err(dev, "%s: ERROR: Unsupported status to set '%s'!\n",
1242 __func__, enum_anc_state[req]);
9f0ed7a7
DC		 1243 status = -EINVAL;
1244 goto cleanup;
679d7abd
OL		 1245 }
1246 apply_fir = req == ANC_APPLY_FIR || req == ANC_APPLY_FIR_IIR;
1247 apply_iir = req == ANC_APPLY_IIR || req == ANC_APPLY_FIR_IIR;
1248
1249 status = snd_soc_dapm_force_enable_pin(&codec->dapm,
1250 "ANC Configure Input");
1251 if (status < 0) {
1252 dev_err(dev,
1253 "%s: ERROR: Failed to enable power (status = %d)!\n",
1254 __func__, status);
1255 goto cleanup;
1256 }
1257 snd_soc_dapm_sync(&codec->dapm);
1258
1259 mutex_lock(&codec->mutex);
1260 anc_configure(codec, apply_fir, apply_iir);
1261 mutex_unlock(&codec->mutex);
1262
1263 if (apply_fir) {
1264 if (drvdata->anc_status == ANC_IIR_CONFIGURED)
1265 drvdata->anc_status = ANC_FIR_IIR_CONFIGURED;
1266 else if (drvdata->anc_status != ANC_FIR_IIR_CONFIGURED)
1267 drvdata->anc_status = ANC_FIR_CONFIGURED;
1268 }
1269 if (apply_iir) {
1270 if (drvdata->anc_status == ANC_FIR_CONFIGURED)
1271 drvdata->anc_status = ANC_FIR_IIR_CONFIGURED;
1272 else if (drvdata->anc_status != ANC_FIR_IIR_CONFIGURED)
1273 drvdata->anc_status = ANC_IIR_CONFIGURED;
1274 }
1275
1276 status = snd_soc_dapm_disable_pin(&codec->dapm, "ANC Configure Input");
1277 snd_soc_dapm_sync(&codec->dapm);
1278
1279cleanup:
1280 mutex_unlock(&drvdata->anc_lock);
1281
1282 if (status < 0)
1283 dev_err(dev, "%s: Unable to configure ANC! (status = %d)\n",
1284 __func__, status);
1285
1286 dev_dbg(dev, "%s: Exit.\n", __func__);
1287
1288 return (status < 0) ? status : 1;
1289}
1290
1291static int filter_control_info(struct snd_kcontrol *kcontrol,
1292 struct snd_ctl_elem_info *uinfo)
1293{
1294 struct filter_control *fc =
1295 (struct filter_control *)kcontrol->private_value;
1296
1297 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1298 uinfo->count = fc->count;
1299 uinfo->value.integer.min = fc->min;
1300 uinfo->value.integer.max = fc->max;
1301
1302 return 0;
1303}
1304
1305static int filter_control_get(struct snd_kcontrol *kcontrol,
1306 struct snd_ctl_elem_value *ucontrol)
1307{
ea53bf77 1308 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
679d7abd
OL		 1309 struct filter_control *fc =
1310 (struct filter_control *)kcontrol->private_value;
1311 unsigned int i;
1312
1313 mutex_lock(&codec->mutex);
1314 for (i = 0; i < fc->count; i++)
1315 ucontrol->value.integer.value[i] = fc->value[i];
1316 mutex_unlock(&codec->mutex);
1317
1318 return 0;
1319}
1320
1321static int filter_control_put(struct snd_kcontrol *kcontrol,
1322 struct snd_ctl_elem_value *ucontrol)
1323{
ea53bf77 1324 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
679d7abd
OL		 1325 struct filter_control *fc =
1326 (struct filter_control *)kcontrol->private_value;
1327 unsigned int i;
1328
1329 mutex_lock(&codec->mutex);
1330 for (i = 0; i < fc->count; i++)
1331 fc->value[i] = ucontrol->value.integer.value[i];
1332 mutex_unlock(&codec->mutex);
1333
1334 return 0;
1335}
1336
1337/*
1338 * Controls - Non-DAPM ASoC
1339 */
1340
1341static DECLARE_TLV_DB_SCALE(adx_dig_gain_tlv, -3200, 100, 1);
1342/* -32dB = Mute */
1343
1344static DECLARE_TLV_DB_SCALE(dax_dig_gain_tlv, -6300, 100, 1);
1345/* -63dB = Mute */
1346
1347static DECLARE_TLV_DB_SCALE(hs_ear_dig_gain_tlv, -100, 100, 1);
1348/* -1dB = Mute */
1349
1350static const unsigned int hs_gain_tlv[] = {
1351 TLV_DB_RANGE_HEAD(2),
1352 0, 3, TLV_DB_SCALE_ITEM(-3200, 400, 0),
1353 4, 15, TLV_DB_SCALE_ITEM(-1800, 200, 0),
1354};
1355
1356static DECLARE_TLV_DB_SCALE(mic_gain_tlv, 0, 100, 0);
1357
1358static DECLARE_TLV_DB_SCALE(lin_gain_tlv, -1000, 200, 0);
1359
1360static DECLARE_TLV_DB_SCALE(lin2hs_gain_tlv, -3800, 200, 1);
1361/* -38dB = Mute */
1362
1363static const char * const enum_hsfadspeed[] = {"2ms", "0.5ms", "10.6ms",
1364 "5ms"};
1365static SOC_ENUM_SINGLE_DECL(soc_enum_hsfadspeed,
1366 AB8500_DIGMICCONF, AB8500_DIGMICCONF_HSFADSPEED, enum_hsfadspeed);
1367
1368static const char * const enum_envdetthre[] = {
1369 "250mV", "300mV", "350mV", "400mV",
1370 "450mV", "500mV", "550mV", "600mV",
1371 "650mV", "700mV", "750mV", "800mV",
1372 "850mV", "900mV", "950mV", "1.00V" };
1373static SOC_ENUM_SINGLE_DECL(soc_enum_envdeththre,
1374 AB8500_ENVCPCONF, AB8500_ENVCPCONF_ENVDETHTHRE, enum_envdetthre);
1375static SOC_ENUM_SINGLE_DECL(soc_enum_envdetlthre,
1376 AB8500_ENVCPCONF, AB8500_ENVCPCONF_ENVDETLTHRE, enum_envdetthre);
1377static const char * const enum_envdettime[] = {
1378 "26.6us", "53.2us", "106us", "213us",
1379 "426us", "851us", "1.70ms", "3.40ms",
1380 "6.81ms", "13.6ms", "27.2ms", "54.5ms",
1381 "109ms", "218ms", "436ms", "872ms" };
1382static SOC_ENUM_SINGLE_DECL(soc_enum_envdettime,
1383 AB8500_SIGENVCONF, AB8500_SIGENVCONF_ENVDETTIME, enum_envdettime);
1384
1385static const char * const enum_sinc31[] = {"Sinc 3", "Sinc 1"};
1386static SOC_ENUM_SINGLE_DECL(soc_enum_hsesinc, AB8500_HSLEARDIGGAIN,
1387 AB8500_HSLEARDIGGAIN_HSSINC1, enum_sinc31);
1388
1389static const char * const enum_fadespeed[] = {"1ms", "4ms", "8ms", "16ms"};
1390static SOC_ENUM_SINGLE_DECL(soc_enum_fadespeed, AB8500_HSRDIGGAIN,
1391 AB8500_HSRDIGGAIN_FADESPEED, enum_fadespeed);
1392
1393/* Earpiece */
1394
1395static const char * const enum_lowpow[] = {"Normal", "Low Power"};
1396static SOC_ENUM_SINGLE_DECL(soc_enum_eardaclowpow, AB8500_ANACONF1,
1397 AB8500_ANACONF1_EARDACLOWPOW, enum_lowpow);
1398static SOC_ENUM_SINGLE_DECL(soc_enum_eardrvlowpow, AB8500_ANACONF1,
1399 AB8500_ANACONF1_EARDRVLOWPOW, enum_lowpow);
1400
1401static const char * const enum_av_mode[] = {"Audio", "Voice"};
1402static SOC_ENUM_DOUBLE_DECL(soc_enum_ad12voice, AB8500_ADFILTCONF,
1403 AB8500_ADFILTCONF_AD1VOICE, AB8500_ADFILTCONF_AD2VOICE, enum_av_mode);
1404static SOC_ENUM_DOUBLE_DECL(soc_enum_ad34voice, AB8500_ADFILTCONF,
1405 AB8500_ADFILTCONF_AD3VOICE, AB8500_ADFILTCONF_AD4VOICE, enum_av_mode);
1406
1407/* DA */
1408
1409static SOC_ENUM_SINGLE_DECL(soc_enum_da12voice,
1410 AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_DA12VOICE,
1411 enum_av_mode);
1412static SOC_ENUM_SINGLE_DECL(soc_enum_da34voice,
1413 AB8500_DASLOTCONF3, AB8500_DASLOTCONF3_DA34VOICE,
1414 enum_av_mode);
1415static SOC_ENUM_SINGLE_DECL(soc_enum_da56voice,
1416 AB8500_DASLOTCONF5, AB8500_DASLOTCONF5_DA56VOICE,
1417 enum_av_mode);
1418
1419static const char * const enum_da2hslr[] = {"Sidetone", "Audio Path"};
1420static SOC_ENUM_DOUBLE_DECL(soc_enum_da2hslr, AB8500_DIGMULTCONF1,
1421 AB8500_DIGMULTCONF1_DATOHSLEN,
1422 AB8500_DIGMULTCONF1_DATOHSREN, enum_da2hslr);
1423
1424static const char * const enum_sinc53[] = {"Sinc 5", "Sinc 3"};
1425static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic12sinc, AB8500_DMICFILTCONF,
1426 AB8500_DMICFILTCONF_DMIC1SINC3,
1427 AB8500_DMICFILTCONF_DMIC2SINC3, enum_sinc53);
1428static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic34sinc, AB8500_DMICFILTCONF,
1429 AB8500_DMICFILTCONF_DMIC3SINC3,
1430 AB8500_DMICFILTCONF_DMIC4SINC3, enum_sinc53);
1431static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic56sinc, AB8500_DMICFILTCONF,
1432 AB8500_DMICFILTCONF_DMIC5SINC3,
1433 AB8500_DMICFILTCONF_DMIC6SINC3, enum_sinc53);
1434
1435/* Digital interface - DA from slot mapping */
1436static const char * const enum_da_from_slot_map[] = {"SLOT0",
1437 "SLOT1",
1438 "SLOT2",
1439 "SLOT3",
1440 "SLOT4",
1441 "SLOT5",
1442 "SLOT6",
1443 "SLOT7",
1444 "SLOT8",
1445 "SLOT9",
1446 "SLOT10",
1447 "SLOT11",
1448 "SLOT12",
1449 "SLOT13",
1450 "SLOT14",
1451 "SLOT15",
1452 "SLOT16",
1453 "SLOT17",
1454 "SLOT18",
1455 "SLOT19",
1456 "SLOT20",
1457 "SLOT21",
1458 "SLOT22",
1459 "SLOT23",
1460 "SLOT24",
1461 "SLOT25",
1462 "SLOT26",
1463 "SLOT27",
1464 "SLOT28",
1465 "SLOT29",
1466 "SLOT30",
1467 "SLOT31"};
1468static SOC_ENUM_SINGLE_DECL(soc_enum_da1slotmap,
1469 AB8500_DASLOTCONF1, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1470 enum_da_from_slot_map);
1471static SOC_ENUM_SINGLE_DECL(soc_enum_da2slotmap,
1472 AB8500_DASLOTCONF2, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1473 enum_da_from_slot_map);
1474static SOC_ENUM_SINGLE_DECL(soc_enum_da3slotmap,
1475 AB8500_DASLOTCONF3, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1476 enum_da_from_slot_map);
1477static SOC_ENUM_SINGLE_DECL(soc_enum_da4slotmap,
1478 AB8500_DASLOTCONF4, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1479 enum_da_from_slot_map);
1480static SOC_ENUM_SINGLE_DECL(soc_enum_da5slotmap,
1481 AB8500_DASLOTCONF5, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1482 enum_da_from_slot_map);
1483static SOC_ENUM_SINGLE_DECL(soc_enum_da6slotmap,
1484 AB8500_DASLOTCONF6, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1485 enum_da_from_slot_map);
1486static SOC_ENUM_SINGLE_DECL(soc_enum_da7slotmap,
1487 AB8500_DASLOTCONF7, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1488 enum_da_from_slot_map);
1489static SOC_ENUM_SINGLE_DECL(soc_enum_da8slotmap,
1490 AB8500_DASLOTCONF8, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1491 enum_da_from_slot_map);
1492
1493/* Digital interface - AD to slot mapping */
1494static const char * const enum_ad_to_slot_map[] = {"AD_OUT1",
1495 "AD_OUT2",
1496 "AD_OUT3",
1497 "AD_OUT4",
1498 "AD_OUT5",
1499 "AD_OUT6",
1500 "AD_OUT7",
1501 "AD_OUT8",
1502 "zeroes",
b9600b4b
FB		 1503 "zeroes",
1504 "zeroes",
1505 "zeroes",
1506 "tristate",
1507 "tristate",
1508 "tristate",
679d7abd
OL		 1509 "tristate"};
1510static SOC_ENUM_SINGLE_DECL(soc_enum_adslot0map,
1511 AB8500_ADSLOTSEL1, AB8500_ADSLOTSELX_EVEN_SHIFT,
1512 enum_ad_to_slot_map);
1513static SOC_ENUM_SINGLE_DECL(soc_enum_adslot1map,
1514 AB8500_ADSLOTSEL1, AB8500_ADSLOTSELX_ODD_SHIFT,
1515 enum_ad_to_slot_map);
1516static SOC_ENUM_SINGLE_DECL(soc_enum_adslot2map,
1517 AB8500_ADSLOTSEL2, AB8500_ADSLOTSELX_EVEN_SHIFT,
1518 enum_ad_to_slot_map);
1519static SOC_ENUM_SINGLE_DECL(soc_enum_adslot3map,
1520 AB8500_ADSLOTSEL2, AB8500_ADSLOTSELX_ODD_SHIFT,
1521 enum_ad_to_slot_map);
1522static SOC_ENUM_SINGLE_DECL(soc_enum_adslot4map,
1523 AB8500_ADSLOTSEL3, AB8500_ADSLOTSELX_EVEN_SHIFT,
1524 enum_ad_to_slot_map);
1525static SOC_ENUM_SINGLE_DECL(soc_enum_adslot5map,
1526 AB8500_ADSLOTSEL3, AB8500_ADSLOTSELX_ODD_SHIFT,
1527 enum_ad_to_slot_map);
1528static SOC_ENUM_SINGLE_DECL(soc_enum_adslot6map,
1529 AB8500_ADSLOTSEL4, AB8500_ADSLOTSELX_EVEN_SHIFT,
1530 enum_ad_to_slot_map);
1531static SOC_ENUM_SINGLE_DECL(soc_enum_adslot7map,
1532 AB8500_ADSLOTSEL4, AB8500_ADSLOTSELX_ODD_SHIFT,
1533 enum_ad_to_slot_map);
1534static SOC_ENUM_SINGLE_DECL(soc_enum_adslot8map,
1535 AB8500_ADSLOTSEL5, AB8500_ADSLOTSELX_EVEN_SHIFT,
1536 enum_ad_to_slot_map);
1537static SOC_ENUM_SINGLE_DECL(soc_enum_adslot9map,
1538 AB8500_ADSLOTSEL5, AB8500_ADSLOTSELX_ODD_SHIFT,
1539 enum_ad_to_slot_map);
1540static SOC_ENUM_SINGLE_DECL(soc_enum_adslot10map,
1541 AB8500_ADSLOTSEL6, AB8500_ADSLOTSELX_EVEN_SHIFT,
1542 enum_ad_to_slot_map);
1543static SOC_ENUM_SINGLE_DECL(soc_enum_adslot11map,
1544 AB8500_ADSLOTSEL6, AB8500_ADSLOTSELX_ODD_SHIFT,
1545 enum_ad_to_slot_map);
1546static SOC_ENUM_SINGLE_DECL(soc_enum_adslot12map,
1547 AB8500_ADSLOTSEL7, AB8500_ADSLOTSELX_EVEN_SHIFT,
1548 enum_ad_to_slot_map);
1549static SOC_ENUM_SINGLE_DECL(soc_enum_adslot13map,
1550 AB8500_ADSLOTSEL7, AB8500_ADSLOTSELX_ODD_SHIFT,
1551 enum_ad_to_slot_map);
1552static SOC_ENUM_SINGLE_DECL(soc_enum_adslot14map,
1553 AB8500_ADSLOTSEL8, AB8500_ADSLOTSELX_EVEN_SHIFT,
1554 enum_ad_to_slot_map);
1555static SOC_ENUM_SINGLE_DECL(soc_enum_adslot15map,
1556 AB8500_ADSLOTSEL8, AB8500_ADSLOTSELX_ODD_SHIFT,
1557 enum_ad_to_slot_map);
1558static SOC_ENUM_SINGLE_DECL(soc_enum_adslot16map,
1559 AB8500_ADSLOTSEL9, AB8500_ADSLOTSELX_EVEN_SHIFT,
1560 enum_ad_to_slot_map);
1561static SOC_ENUM_SINGLE_DECL(soc_enum_adslot17map,
1562 AB8500_ADSLOTSEL9, AB8500_ADSLOTSELX_ODD_SHIFT,
1563 enum_ad_to_slot_map);
1564static SOC_ENUM_SINGLE_DECL(soc_enum_adslot18map,
1565 AB8500_ADSLOTSEL10, AB8500_ADSLOTSELX_EVEN_SHIFT,
1566 enum_ad_to_slot_map);
1567static SOC_ENUM_SINGLE_DECL(soc_enum_adslot19map,
1568 AB8500_ADSLOTSEL10, AB8500_ADSLOTSELX_ODD_SHIFT,
1569 enum_ad_to_slot_map);
1570static SOC_ENUM_SINGLE_DECL(soc_enum_adslot20map,
1571 AB8500_ADSLOTSEL11, AB8500_ADSLOTSELX_EVEN_SHIFT,
1572 enum_ad_to_slot_map);
1573static SOC_ENUM_SINGLE_DECL(soc_enum_adslot21map,
1574 AB8500_ADSLOTSEL11, AB8500_ADSLOTSELX_ODD_SHIFT,
1575 enum_ad_to_slot_map);
1576static SOC_ENUM_SINGLE_DECL(soc_enum_adslot22map,
1577 AB8500_ADSLOTSEL12, AB8500_ADSLOTSELX_EVEN_SHIFT,
1578 enum_ad_to_slot_map);
1579static SOC_ENUM_SINGLE_DECL(soc_enum_adslot23map,
1580 AB8500_ADSLOTSEL12, AB8500_ADSLOTSELX_ODD_SHIFT,
1581 enum_ad_to_slot_map);
1582static SOC_ENUM_SINGLE_DECL(soc_enum_adslot24map,
1583 AB8500_ADSLOTSEL13, AB8500_ADSLOTSELX_EVEN_SHIFT,
1584 enum_ad_to_slot_map);
1585static SOC_ENUM_SINGLE_DECL(soc_enum_adslot25map,
1586 AB8500_ADSLOTSEL13, AB8500_ADSLOTSELX_ODD_SHIFT,
1587 enum_ad_to_slot_map);
1588static SOC_ENUM_SINGLE_DECL(soc_enum_adslot26map,
1589 AB8500_ADSLOTSEL14, AB8500_ADSLOTSELX_EVEN_SHIFT,
1590 enum_ad_to_slot_map);
1591static SOC_ENUM_SINGLE_DECL(soc_enum_adslot27map,
1592 AB8500_ADSLOTSEL14, AB8500_ADSLOTSELX_ODD_SHIFT,
1593 enum_ad_to_slot_map);
1594static SOC_ENUM_SINGLE_DECL(soc_enum_adslot28map,
1595 AB8500_ADSLOTSEL15, AB8500_ADSLOTSELX_EVEN_SHIFT,
1596 enum_ad_to_slot_map);
1597static SOC_ENUM_SINGLE_DECL(soc_enum_adslot29map,
1598 AB8500_ADSLOTSEL15, AB8500_ADSLOTSELX_ODD_SHIFT,
1599 enum_ad_to_slot_map);
1600static SOC_ENUM_SINGLE_DECL(soc_enum_adslot30map,
1601 AB8500_ADSLOTSEL16, AB8500_ADSLOTSELX_EVEN_SHIFT,
1602 enum_ad_to_slot_map);
1603static SOC_ENUM_SINGLE_DECL(soc_enum_adslot31map,
1604 AB8500_ADSLOTSEL16, AB8500_ADSLOTSELX_ODD_SHIFT,
1605 enum_ad_to_slot_map);
1606
1607/* Digital interface - Burst mode */
1608static const char * const enum_mask[] = {"Unmasked", "Masked"};
1609static SOC_ENUM_SINGLE_DECL(soc_enum_bfifomask,
1610 AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFOMASK,
1611 enum_mask);
1612static const char * const enum_bitclk0[] = {"19_2_MHz", "38_4_MHz"};
1613static SOC_ENUM_SINGLE_DECL(soc_enum_bfifo19m2,
1614 AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFO19M2,
1615 enum_bitclk0);
1616static const char * const enum_slavemaster[] = {"Slave", "Master"};
1617static SOC_ENUM_SINGLE_DECL(soc_enum_bfifomast,
1618 AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFOMAST_SHIFT,
1619 enum_slavemaster);
1620
1621/* Sidetone */
1622static SOC_ENUM_SINGLE_EXT_DECL(soc_enum_sidstate, enum_sid_state);
1623
1624/* ANC */
1625static SOC_ENUM_SINGLE_EXT_DECL(soc_enum_ancstate, enum_anc_state);
1626
1627static struct snd_kcontrol_new ab8500_ctrls[] = {
1628 /* Charge pump */
1629 SOC_ENUM("Charge Pump High Threshold For Low Voltage",
1630 soc_enum_envdeththre),
1631 SOC_ENUM("Charge Pump Low Threshold For Low Voltage",
1632 soc_enum_envdetlthre),
1633 SOC_SINGLE("Charge Pump Envelope Detection Switch",
1634 AB8500_SIGENVCONF, AB8500_SIGENVCONF_ENVDETCPEN,
1635 1, 0),
1636 SOC_ENUM("Charge Pump Envelope Detection Decay Time",
1637 soc_enum_envdettime),
1638
1639 /* Headset */
1640 SOC_ENUM("Headset Mode", soc_enum_da12voice),
1641 SOC_SINGLE("Headset High Pass Switch",
1642 AB8500_ANACONF1, AB8500_ANACONF1_HSHPEN,
1643 1, 0),
1644 SOC_SINGLE("Headset Low Power Switch",
1645 AB8500_ANACONF1, AB8500_ANACONF1_HSLOWPOW,
1646 1, 0),
1647 SOC_SINGLE("Headset DAC Low Power Switch",
1648 AB8500_ANACONF1, AB8500_ANACONF1_DACLOWPOW1,
1649 1, 0),
1650 SOC_SINGLE("Headset DAC Drv Low Power Switch",
1651 AB8500_ANACONF1, AB8500_ANACONF1_DACLOWPOW0,
1652 1, 0),
1653 SOC_ENUM("Headset Fade Speed", soc_enum_hsfadspeed),
1654 SOC_ENUM("Headset Source", soc_enum_da2hslr),
1655 SOC_ENUM("Headset Filter", soc_enum_hsesinc),
1656 SOC_DOUBLE_R_TLV("Headset Master Volume",
1657 AB8500_DADIGGAIN1, AB8500_DADIGGAIN2,
1658 0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv),
1659 SOC_DOUBLE_R_TLV("Headset Digital Volume",
1660 AB8500_HSLEARDIGGAIN, AB8500_HSRDIGGAIN,
1661 0, AB8500_HSLEARDIGGAIN_HSLDGAIN_MAX, 1, hs_ear_dig_gain_tlv),
1662 SOC_DOUBLE_TLV("Headset Volume",
1663 AB8500_ANAGAIN3,
1664 AB8500_ANAGAIN3_HSLGAIN, AB8500_ANAGAIN3_HSRGAIN,
1665 AB8500_ANAGAIN3_HSXGAIN_MAX, 1, hs_gain_tlv),
1666
1667 /* Earpiece */
1668 SOC_ENUM("Earpiece DAC Mode",
1669 soc_enum_eardaclowpow),
1670 SOC_ENUM("Earpiece DAC Drv Mode",
1671 soc_enum_eardrvlowpow),
1672
1673 /* HandsFree */
1674 SOC_ENUM("HF Mode", soc_enum_da34voice),
1675 SOC_SINGLE("HF and Headset Swap Switch",
1676 AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_SWAPDA12_34,
1677 1, 0),
1678 SOC_DOUBLE("HF Low EMI Mode Switch",
1679 AB8500_CLASSDCONF1,
1680 AB8500_CLASSDCONF1_HFLSWAPEN, AB8500_CLASSDCONF1_HFRSWAPEN,
1681 1, 0),
1682 SOC_DOUBLE("HF FIR Bypass Switch",
1683 AB8500_CLASSDCONF2,
1684 AB8500_CLASSDCONF2_FIRBYP0, AB8500_CLASSDCONF2_FIRBYP1,
1685 1, 0),
1686 SOC_DOUBLE("HF High Volume Switch",
1687 AB8500_CLASSDCONF2,
1688 AB8500_CLASSDCONF2_HIGHVOLEN0, AB8500_CLASSDCONF2_HIGHVOLEN1,
1689 1, 0),
1690 SOC_SINGLE("HF L and R Bridge Switch",
1691 AB8500_CLASSDCONF1, AB8500_CLASSDCONF1_PARLHF,
1692 1, 0),
1693 SOC_DOUBLE_R_TLV("HF Master Volume",
1694 AB8500_DADIGGAIN3, AB8500_DADIGGAIN4,
1695 0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv),
1696
1697 /* Vibra */
1698 SOC_DOUBLE("Vibra High Volume Switch",
1699 AB8500_CLASSDCONF2,
1700 AB8500_CLASSDCONF2_HIGHVOLEN2, AB8500_CLASSDCONF2_HIGHVOLEN3,
1701 1, 0),
1702 SOC_DOUBLE("Vibra Low EMI Mode Switch",
1703 AB8500_CLASSDCONF1,
1704 AB8500_CLASSDCONF1_VIB1SWAPEN, AB8500_CLASSDCONF1_VIB2SWAPEN,
1705 1, 0),
1706 SOC_DOUBLE("Vibra FIR Bypass Switch",
1707 AB8500_CLASSDCONF2,
1708 AB8500_CLASSDCONF2_FIRBYP2, AB8500_CLASSDCONF2_FIRBYP3,
1709 1, 0),
1710 SOC_ENUM("Vibra Mode", soc_enum_da56voice),
1711 SOC_DOUBLE_R("Vibra PWM Duty Cycle N",
1712 AB8500_PWMGENCONF3, AB8500_PWMGENCONF5,
1713 AB8500_PWMGENCONFX_PWMVIBXDUTCYC,
1714 AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX, 0),
1715 SOC_DOUBLE_R("Vibra PWM Duty Cycle P",
1716 AB8500_PWMGENCONF2, AB8500_PWMGENCONF4,
1717 AB8500_PWMGENCONFX_PWMVIBXDUTCYC,
1718 AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX, 0),
1719 SOC_SINGLE("Vibra 1 and 2 Bridge Switch",
1720 AB8500_CLASSDCONF1, AB8500_CLASSDCONF1_PARLVIB,
1721 1, 0),
1722 SOC_DOUBLE_R_TLV("Vibra Master Volume",
1723 AB8500_DADIGGAIN5, AB8500_DADIGGAIN6,
1724 0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv),
1725
1726 /* HandsFree, Vibra */
1727 SOC_SINGLE("ClassD High Pass Volume",
1728 AB8500_CLASSDCONF3, AB8500_CLASSDCONF3_DITHHPGAIN,
1729 AB8500_CLASSDCONF3_DITHHPGAIN_MAX, 0),
1730 SOC_SINGLE("ClassD White Volume",
1731 AB8500_CLASSDCONF3, AB8500_CLASSDCONF3_DITHWGAIN,
1732 AB8500_CLASSDCONF3_DITHWGAIN_MAX, 0),
1733
1734 /* Mic 1, Mic 2, LineIn */
1735 SOC_DOUBLE_R_TLV("Mic Master Volume",
1736 AB8500_ADDIGGAIN3, AB8500_ADDIGGAIN4,
1737 0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv),
1738
1739 /* Mic 1 */
1740 SOC_SINGLE_TLV("Mic 1",
1741 AB8500_ANAGAIN1,
1742 AB8500_ANAGAINX_MICXGAIN,
1743 AB8500_ANAGAINX_MICXGAIN_MAX, 0, mic_gain_tlv),
1744 SOC_SINGLE("Mic 1 Low Power Switch",
1745 AB8500_ANAGAIN1, AB8500_ANAGAINX_LOWPOWMICX,
1746 1, 0),
1747
1748 /* Mic 2 */
1749 SOC_DOUBLE("Mic High Pass Switch",
1750 AB8500_ADFILTCONF,
1751 AB8500_ADFILTCONF_AD3NH, AB8500_ADFILTCONF_AD4NH,
1752 1, 1),
1753 SOC_ENUM("Mic Mode", soc_enum_ad34voice),
1754 SOC_ENUM("Mic Filter", soc_enum_dmic34sinc),
1755 SOC_SINGLE_TLV("Mic 2",
1756 AB8500_ANAGAIN2,
1757 AB8500_ANAGAINX_MICXGAIN,
1758 AB8500_ANAGAINX_MICXGAIN_MAX, 0, mic_gain_tlv),
1759 SOC_SINGLE("Mic 2 Low Power Switch",
1760 AB8500_ANAGAIN2, AB8500_ANAGAINX_LOWPOWMICX,
1761 1, 0),
1762
1763 /* LineIn */
1764 SOC_DOUBLE("LineIn High Pass Switch",
1765 AB8500_ADFILTCONF,
1766 AB8500_ADFILTCONF_AD1NH, AB8500_ADFILTCONF_AD2NH,
1767 1, 1),
1768 SOC_ENUM("LineIn Filter", soc_enum_dmic12sinc),
1769 SOC_ENUM("LineIn Mode", soc_enum_ad12voice),
1770 SOC_DOUBLE_R_TLV("LineIn Master Volume",
1771 AB8500_ADDIGGAIN1, AB8500_ADDIGGAIN2,
1772 0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv),
1773 SOC_DOUBLE_TLV("LineIn",
1774 AB8500_ANAGAIN4,
1775 AB8500_ANAGAIN4_LINLGAIN, AB8500_ANAGAIN4_LINRGAIN,
1776 AB8500_ANAGAIN4_LINXGAIN_MAX, 0, lin_gain_tlv),
1777 SOC_DOUBLE_R_TLV("LineIn to Headset Volume",
1778 AB8500_DIGLINHSLGAIN, AB8500_DIGLINHSRGAIN,
1779 AB8500_DIGLINHSXGAIN_LINTOHSXGAIN,
1780 AB8500_DIGLINHSXGAIN_LINTOHSXGAIN_MAX,
1781 1, lin2hs_gain_tlv),
1782
1783 /* DMic */
1784 SOC_ENUM("DMic Filter", soc_enum_dmic56sinc),
1785 SOC_DOUBLE_R_TLV("DMic Master Volume",
1786 AB8500_ADDIGGAIN5, AB8500_ADDIGGAIN6,
1787 0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv),
1788
1789 /* Digital gains */
1790 SOC_ENUM("Digital Gain Fade Speed", soc_enum_fadespeed),
1791
1792 /* Analog loopback */
1793 SOC_DOUBLE_R_TLV("Analog Loopback Volume",
1794 AB8500_ADDIGLOOPGAIN1, AB8500_ADDIGLOOPGAIN2,
1795 0, AB8500_ADDIGLOOPGAINX_ADXLBGAIN_MAX, 1, dax_dig_gain_tlv),
1796
1797 /* Digital interface - DA from slot mapping */
1798 SOC_ENUM("Digital Interface DA 1 From Slot Map", soc_enum_da1slotmap),
1799 SOC_ENUM("Digital Interface DA 2 From Slot Map", soc_enum_da2slotmap),
1800 SOC_ENUM("Digital Interface DA 3 From Slot Map", soc_enum_da3slotmap),
1801 SOC_ENUM("Digital Interface DA 4 From Slot Map", soc_enum_da4slotmap),
1802 SOC_ENUM("Digital Interface DA 5 From Slot Map", soc_enum_da5slotmap),
1803 SOC_ENUM("Digital Interface DA 6 From Slot Map", soc_enum_da6slotmap),
1804 SOC_ENUM("Digital Interface DA 7 From Slot Map", soc_enum_da7slotmap),
1805 SOC_ENUM("Digital Interface DA 8 From Slot Map", soc_enum_da8slotmap),
1806
1807 /* Digital interface - AD to slot mapping */
1808 SOC_ENUM("Digital Interface AD To Slot 0 Map", soc_enum_adslot0map),
1809 SOC_ENUM("Digital Interface AD To Slot 1 Map", soc_enum_adslot1map),
1810 SOC_ENUM("Digital Interface AD To Slot 2 Map", soc_enum_adslot2map),
1811 SOC_ENUM("Digital Interface AD To Slot 3 Map", soc_enum_adslot3map),
1812 SOC_ENUM("Digital Interface AD To Slot 4 Map", soc_enum_adslot4map),
1813 SOC_ENUM("Digital Interface AD To Slot 5 Map", soc_enum_adslot5map),
1814 SOC_ENUM("Digital Interface AD To Slot 6 Map", soc_enum_adslot6map),
1815 SOC_ENUM("Digital Interface AD To Slot 7 Map", soc_enum_adslot7map),
1816 SOC_ENUM("Digital Interface AD To Slot 8 Map", soc_enum_adslot8map),
1817 SOC_ENUM("Digital Interface AD To Slot 9 Map", soc_enum_adslot9map),
1818 SOC_ENUM("Digital Interface AD To Slot 10 Map", soc_enum_adslot10map),
1819 SOC_ENUM("Digital Interface AD To Slot 11 Map", soc_enum_adslot11map),
1820 SOC_ENUM("Digital Interface AD To Slot 12 Map", soc_enum_adslot12map),
1821 SOC_ENUM("Digital Interface AD To Slot 13 Map", soc_enum_adslot13map),
1822 SOC_ENUM("Digital Interface AD To Slot 14 Map", soc_enum_adslot14map),
1823 SOC_ENUM("Digital Interface AD To Slot 15 Map", soc_enum_adslot15map),
1824 SOC_ENUM("Digital Interface AD To Slot 16 Map", soc_enum_adslot16map),
1825 SOC_ENUM("Digital Interface AD To Slot 17 Map", soc_enum_adslot17map),
1826 SOC_ENUM("Digital Interface AD To Slot 18 Map", soc_enum_adslot18map),
1827 SOC_ENUM("Digital Interface AD To Slot 19 Map", soc_enum_adslot19map),
1828 SOC_ENUM("Digital Interface AD To Slot 20 Map", soc_enum_adslot20map),
1829 SOC_ENUM("Digital Interface AD To Slot 21 Map", soc_enum_adslot21map),
1830 SOC_ENUM("Digital Interface AD To Slot 22 Map", soc_enum_adslot22map),
1831 SOC_ENUM("Digital Interface AD To Slot 23 Map", soc_enum_adslot23map),
1832 SOC_ENUM("Digital Interface AD To Slot 24 Map", soc_enum_adslot24map),
1833 SOC_ENUM("Digital Interface AD To Slot 25 Map", soc_enum_adslot25map),
1834 SOC_ENUM("Digital Interface AD To Slot 26 Map", soc_enum_adslot26map),
1835 SOC_ENUM("Digital Interface AD To Slot 27 Map", soc_enum_adslot27map),
1836 SOC_ENUM("Digital Interface AD To Slot 28 Map", soc_enum_adslot28map),
1837 SOC_ENUM("Digital Interface AD To Slot 29 Map", soc_enum_adslot29map),
1838 SOC_ENUM("Digital Interface AD To Slot 30 Map", soc_enum_adslot30map),
1839 SOC_ENUM("Digital Interface AD To Slot 31 Map", soc_enum_adslot31map),
1840
1841 /* Digital interface - Loopback */
1842 SOC_SINGLE("Digital Interface AD 1 Loopback Switch",
1843 AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_DAI7TOADO1,
1844 1, 0),
1845 SOC_SINGLE("Digital Interface AD 2 Loopback Switch",
1846 AB8500_DASLOTCONF2, AB8500_DASLOTCONF2_DAI8TOADO2,
1847 1, 0),
1848 SOC_SINGLE("Digital Interface AD 3 Loopback Switch",
1849 AB8500_DASLOTCONF3, AB8500_DASLOTCONF3_DAI7TOADO3,
1850 1, 0),
1851 SOC_SINGLE("Digital Interface AD 4 Loopback Switch",
1852 AB8500_DASLOTCONF4, AB8500_DASLOTCONF4_DAI8TOADO4,
1853 1, 0),
1854 SOC_SINGLE("Digital Interface AD 5 Loopback Switch",
1855 AB8500_DASLOTCONF5, AB8500_DASLOTCONF5_DAI7TOADO5,
1856 1, 0),
1857 SOC_SINGLE("Digital Interface AD 6 Loopback Switch",
1858 AB8500_DASLOTCONF6, AB8500_DASLOTCONF6_DAI8TOADO6,
1859 1, 0),
1860 SOC_SINGLE("Digital Interface AD 7 Loopback Switch",
1861 AB8500_DASLOTCONF7, AB8500_DASLOTCONF7_DAI8TOADO7,
1862 1, 0),
1863 SOC_SINGLE("Digital Interface AD 8 Loopback Switch",
1864 AB8500_DASLOTCONF8, AB8500_DASLOTCONF8_DAI7TOADO8,
1865 1, 0),
1866
1867 /* Digital interface - Burst FIFO */
1868 SOC_SINGLE("Digital Interface 0 FIFO Enable Switch",
1869 AB8500_DIGIFCONF3, AB8500_DIGIFCONF3_IF0BFIFOEN,
1870 1, 0),
1871 SOC_ENUM("Burst FIFO Mask", soc_enum_bfifomask),
1872 SOC_ENUM("Burst FIFO Bit-clock Frequency", soc_enum_bfifo19m2),
1873 SOC_SINGLE("Burst FIFO Threshold",
1874 AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFOINT_SHIFT,
1875 AB8500_FIFOCONF1_BFIFOINT_MAX, 0),
1876 SOC_SINGLE("Burst FIFO Length",
1877 AB8500_FIFOCONF2, AB8500_FIFOCONF2_BFIFOTX_SHIFT,
1878 AB8500_FIFOCONF2_BFIFOTX_MAX, 0),
1879 SOC_SINGLE("Burst FIFO EOS Extra Slots",
1880 AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFOEXSL_SHIFT,
1881 AB8500_FIFOCONF3_BFIFOEXSL_MAX, 0),
1882 SOC_SINGLE("Burst FIFO FS Extra Bit-clocks",
1883 AB8500_FIFOCONF3, AB8500_FIFOCONF3_PREBITCLK0_SHIFT,
1884 AB8500_FIFOCONF3_PREBITCLK0_MAX, 0),
1885 SOC_ENUM("Burst FIFO Interface Mode", soc_enum_bfifomast),
1886
1887 SOC_SINGLE("Burst FIFO Interface Switch",
1888 AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFORUN_SHIFT,
1889 1, 0),
1890 SOC_SINGLE("Burst FIFO Switch Frame Number",
1891 AB8500_FIFOCONF4, AB8500_FIFOCONF4_BFIFOFRAMSW_SHIFT,
1892 AB8500_FIFOCONF4_BFIFOFRAMSW_MAX, 0),
1893 SOC_SINGLE("Burst FIFO Wake Up Delay",
1894 AB8500_FIFOCONF5, AB8500_FIFOCONF5_BFIFOWAKEUP_SHIFT,
1895 AB8500_FIFOCONF5_BFIFOWAKEUP_MAX, 0),
1896 SOC_SINGLE("Burst FIFO Samples In FIFO",
1897 AB8500_FIFOCONF6, AB8500_FIFOCONF6_BFIFOSAMPLE_SHIFT,
1898 AB8500_FIFOCONF6_BFIFOSAMPLE_MAX, 0),
1899
1900 /* ANC */
1901 SOC_ENUM_EXT("ANC Status", soc_enum_ancstate,
1902 anc_status_control_get, anc_status_control_put),
1903 SOC_SINGLE_XR_SX("ANC Warp Delay Shift",
1904 AB8500_ANCCONF2, 1, AB8500_ANCCONF2_SHIFT,
1905 AB8500_ANCCONF2_MIN, AB8500_ANCCONF2_MAX, 0),
1906 SOC_SINGLE_XR_SX("ANC FIR Output Shift",
1907 AB8500_ANCCONF3, 1, AB8500_ANCCONF3_SHIFT,
1908 AB8500_ANCCONF3_MIN, AB8500_ANCCONF3_MAX, 0),
1909 SOC_SINGLE_XR_SX("ANC IIR Output Shift",
1910 AB8500_ANCCONF4, 1, AB8500_ANCCONF4_SHIFT,
1911 AB8500_ANCCONF4_MIN, AB8500_ANCCONF4_MAX, 0),
1912 SOC_SINGLE_XR_SX("ANC Warp Delay",
1913 AB8500_ANCCONF9, 2, AB8500_ANC_WARP_DELAY_SHIFT,
1914 AB8500_ANC_WARP_DELAY_MIN, AB8500_ANC_WARP_DELAY_MAX, 0),
1915
1916 /* Sidetone */
1917 SOC_ENUM_EXT("Sidetone Status", soc_enum_sidstate,
1918 sid_status_control_get, sid_status_control_put),
1919 SOC_SINGLE_STROBE("Sidetone Reset",
1920 AB8500_SIDFIRADR, AB8500_SIDFIRADR_FIRSIDSET, 0),
1921};
1922
1923static struct snd_kcontrol_new ab8500_filter_controls[] = {
1924 AB8500_FILTER_CONTROL("ANC FIR Coefficients", AB8500_ANC_FIR_COEFFS,
1925 AB8500_ANC_FIR_COEFF_MIN, AB8500_ANC_FIR_COEFF_MAX),
1926 AB8500_FILTER_CONTROL("ANC IIR Coefficients", AB8500_ANC_IIR_COEFFS,
1927 AB8500_ANC_IIR_COEFF_MIN, AB8500_ANC_IIR_COEFF_MAX),
1928 AB8500_FILTER_CONTROL("Sidetone FIR Coefficients",
1929 AB8500_SID_FIR_COEFFS, AB8500_SID_FIR_COEFF_MIN,
1930 AB8500_SID_FIR_COEFF_MAX)
1931};
1932enum ab8500_filter {
1933 AB8500_FILTER_ANC_FIR = 0,
1934 AB8500_FILTER_ANC_IIR = 1,
1935 AB8500_FILTER_SID_FIR = 2,
1936};
1937
1938/*
1939 * Extended interface for codec-driver
1940 */
1941
1942static int ab8500_audio_init_audioblock(struct snd_soc_codec *codec)
1943{
1944 int status;
1945
1946 dev_dbg(codec->dev, "%s: Enter.\n", __func__);
1947
1948 /* Reset audio-registers and disable 32kHz-clock output 2 */
1949 status = ab8500_sysctrl_write(AB8500_STW4500CTRL3,
1950 AB8500_STW4500CTRL3_CLK32KOUT2DIS |
1951 AB8500_STW4500CTRL3_RESETAUDN,
1952 AB8500_STW4500CTRL3_RESETAUDN);
1953 if (status < 0)
1954 return status;
1955
1956 return 0;
1957}
1958
1959static int ab8500_audio_setup_mics(struct snd_soc_codec *codec,
1960 struct amic_settings *amics)
1961{
1962 u8 value8;
1963 unsigned int value;
1964 int status;
1965 const struct snd_soc_dapm_route *route;
1966
1967 dev_dbg(codec->dev, "%s: Enter.\n", __func__);
1968
1969 /* Set DMic-clocks to outputs */
6391fffb
LPC		 1970 status = abx500_get_register_interruptible(codec->dev, AB8500_MISC,
1971 AB8500_GPIO_DIR4_REG,
679d7abd
OL		 1972 &value8);
1973 if (status < 0)
1974 return status;
1975 value = value8 | GPIO27_DIR_OUTPUT | GPIO29_DIR_OUTPUT |
1976 GPIO31_DIR_OUTPUT;
1977 status = abx500_set_register_interruptible(codec->dev,
6391fffb
LPC		 1978 AB8500_MISC,
1979 AB8500_GPIO_DIR4_REG,
679d7abd
OL		 1980 value);
1981 if (status < 0)
1982 return status;
1983
1984 /* Attach regulators to AMic DAPM-paths */
1985 dev_dbg(codec->dev, "%s: Mic 1a regulator: %s\n", __func__,
1986 amic_micbias_str(amics->mic1a_micbias));
1987 route = &ab8500_dapm_routes_mic1a_vamicx[amics->mic1a_micbias];
1988 status = snd_soc_dapm_add_routes(&codec->dapm, route, 1);
1989 dev_dbg(codec->dev, "%s: Mic 1b regulator: %s\n", __func__,
1990 amic_micbias_str(amics->mic1b_micbias));
1991 route = &ab8500_dapm_routes_mic1b_vamicx[amics->mic1b_micbias];
1992 status |= snd_soc_dapm_add_routes(&codec->dapm, route, 1);
1993 dev_dbg(codec->dev, "%s: Mic 2 regulator: %s\n", __func__,
1994 amic_micbias_str(amics->mic2_micbias));
1995 route = &ab8500_dapm_routes_mic2_vamicx[amics->mic2_micbias];
1996 status |= snd_soc_dapm_add_routes(&codec->dapm, route, 1);
1997 if (status < 0) {
1998 dev_err(codec->dev,
1999 "%s: Failed to add AMic-regulator DAPM-routes (%d).\n",
2000 __func__, status);
2001 return status;
2002 }
2003
2004 /* Set AMic-configuration */
2005 dev_dbg(codec->dev, "%s: Mic 1 mic-type: %s\n", __func__,
2006 amic_type_str(amics->mic1_type));
2007 snd_soc_update_bits(codec, AB8500_ANAGAIN1, AB8500_ANAGAINX_ENSEMICX,
2008 amics->mic1_type == AMIC_TYPE_DIFFERENTIAL ?
2009 0 : AB8500_ANAGAINX_ENSEMICX);
2010 dev_dbg(codec->dev, "%s: Mic 2 mic-type: %s\n", __func__,
2011 amic_type_str(amics->mic2_type));
2012 snd_soc_update_bits(codec, AB8500_ANAGAIN2, AB8500_ANAGAINX_ENSEMICX,
2013 amics->mic2_type == AMIC_TYPE_DIFFERENTIAL ?
2014 0 : AB8500_ANAGAINX_ENSEMICX);
2015
2016 return 0;
2017}
2018EXPORT_SYMBOL_GPL(ab8500_audio_setup_mics);
2019
2020static int ab8500_audio_set_ear_cmv(struct snd_soc_codec *codec,
2021 enum ear_cm_voltage ear_cmv)
2022{
2023 char *cmv_str;
2024
2025 switch (ear_cmv) {
2026 case EAR_CMV_0_95V:
2027 cmv_str = "0.95V";
2028 break;
2029 case EAR_CMV_1_10V:
2030 cmv_str = "1.10V";
2031 break;
2032 case EAR_CMV_1_27V:
2033 cmv_str = "1.27V";
2034 break;
2035 case EAR_CMV_1_58V:
2036 cmv_str = "1.58V";
2037 break;
2038 default:
2039 dev_err(codec->dev,
2040 "%s: Unknown earpiece CM-voltage (%d)!\n",
2041 __func__, (int)ear_cmv);
2042 return -EINVAL;
2043 }
2044 dev_dbg(codec->dev, "%s: Earpiece CM-voltage: %s\n", __func__,
2045 cmv_str);
2046 snd_soc_update_bits(codec, AB8500_ANACONF1, AB8500_ANACONF1_EARSELCM,
2047 ear_cmv);
2048
2049 return 0;
2050}
2051EXPORT_SYMBOL_GPL(ab8500_audio_set_ear_cmv);
2052
2053static int ab8500_audio_set_bit_delay(struct snd_soc_dai *dai,
2054 unsigned int delay)
2055{
2056 unsigned int mask, val;
2057 struct snd_soc_codec *codec = dai->codec;
2058
2059 mask = BIT(AB8500_DIGIFCONF2_IF0DEL);
2060 val = 0;
2061
2062 switch (delay) {
2063 case 0:
2064 break;
2065 case 1:
2066 val |= BIT(AB8500_DIGIFCONF2_IF0DEL);
2067 break;
2068 default:
2069 dev_err(dai->codec->dev,
2070 "%s: ERROR: Unsupported bit-delay (0x%x)!\n",
2071 __func__, delay);
2072 return -EINVAL;
2073 }
2074
2075 dev_dbg(dai->codec->dev, "%s: IF0 Bit-delay: %d bits.\n",
2076 __func__, delay);
2077 snd_soc_update_bits(codec, AB8500_DIGIFCONF2, mask, val);
2078
2079 return 0;
2080}
2081
2082/* Gates clocking according format mask */
2083static int ab8500_codec_set_dai_clock_gate(struct snd_soc_codec *codec,
2084 unsigned int fmt)
2085{
2086 unsigned int mask;
2087 unsigned int val;
2088
2089 mask = BIT(AB8500_DIGIFCONF1_ENMASTGEN) |
2090 BIT(AB8500_DIGIFCONF1_ENFSBITCLK0);
2091
2092 val = BIT(AB8500_DIGIFCONF1_ENMASTGEN);
2093
2094 switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
2095 case SND_SOC_DAIFMT_CONT: /* continuous clock */
2096 dev_dbg(codec->dev, "%s: IF0 Clock is continuous.\n",
2097 __func__);
2098 val |= BIT(AB8500_DIGIFCONF1_ENFSBITCLK0);
2099 break;
2100 case SND_SOC_DAIFMT_GATED: /* clock is gated */
2101 dev_dbg(codec->dev, "%s: IF0 Clock is gated.\n",
2102 __func__);
2103 break;
2104 default:
2105 dev_err(codec->dev,
2106 "%s: ERROR: Unsupported clock mask (0x%x)!\n",
2107 __func__, fmt & SND_SOC_DAIFMT_CLOCK_MASK);
2108 return -EINVAL;
2109 }
2110
2111 snd_soc_update_bits(codec, AB8500_DIGIFCONF1, mask, val);
2112
2113 return 0;
2114}
2115
2116static int ab8500_codec_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2117{
2118 unsigned int mask;
2119 unsigned int val;
2120 struct snd_soc_codec *codec = dai->codec;
2121 int status;
2122
2123 dev_dbg(codec->dev, "%s: Enter (fmt = 0x%x)\n", __func__, fmt);
2124
2125 mask = BIT(AB8500_DIGIFCONF3_IF1DATOIF0AD) |
2126 BIT(AB8500_DIGIFCONF3_IF1CLKTOIF0CLK) |
2127 BIT(AB8500_DIGIFCONF3_IF0BFIFOEN) |
2128 BIT(AB8500_DIGIFCONF3_IF0MASTER);
2129 val = 0;
2130
2131 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2132 case SND_SOC_DAIFMT_CBM_CFM: /* codec clk & FRM master */
2133 dev_dbg(dai->codec->dev,
2134 "%s: IF0 Master-mode: AB8500 master.\n", __func__);
2135 val |= BIT(AB8500_DIGIFCONF3_IF0MASTER);
2136 break;
2137 case SND_SOC_DAIFMT_CBS_CFS: /* codec clk & FRM slave */
2138 dev_dbg(dai->codec->dev,
2139 "%s: IF0 Master-mode: AB8500 slave.\n", __func__);
2140 break;
2141 case SND_SOC_DAIFMT_CBS_CFM: /* codec clk slave & FRM master */
2142 case SND_SOC_DAIFMT_CBM_CFS: /* codec clk master & frame slave */
2143 dev_err(dai->codec->dev,
2144 "%s: ERROR: The device is either a master or a slave.\n",
2145 __func__);
2146 default:
2147 dev_err(dai->codec->dev,
2148 "%s: ERROR: Unsupporter master mask 0x%x\n",
2149 __func__, fmt & SND_SOC_DAIFMT_MASTER_MASK);
2150 return -EINVAL;
2151 break;
2152 }
2153
2154 snd_soc_update_bits(codec, AB8500_DIGIFCONF3, mask, val);
2155
2156 /* Set clock gating */
2157 status = ab8500_codec_set_dai_clock_gate(codec, fmt);
2158 if (status) {
2159 dev_err(dai->codec->dev,
c46d5c04 2160 "%s: ERROR: Failed to set clock gate (%d).\n",
679d7abd
OL		 2161 __func__, status);
2162 return status;
2163 }
2164
2165 /* Setting data transfer format */
2166
2167 mask = BIT(AB8500_DIGIFCONF2_IF0FORMAT0) |
2168 BIT(AB8500_DIGIFCONF2_IF0FORMAT1) |
2169 BIT(AB8500_DIGIFCONF2_FSYNC0P) |
2170 BIT(AB8500_DIGIFCONF2_BITCLK0P);
2171 val = 0;
2172
2173 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2174 case SND_SOC_DAIFMT_I2S: /* I2S mode */
2175 dev_dbg(dai->codec->dev, "%s: IF0 Protocol: I2S\n", __func__);
2176 val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT1);
2177 ab8500_audio_set_bit_delay(dai, 0);
2178 break;
2179
2180 case SND_SOC_DAIFMT_DSP_A: /* L data MSB after FRM LRC */
2181 dev_dbg(dai->codec->dev,
2182 "%s: IF0 Protocol: DSP A (TDM)\n", __func__);
2183 val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0);
2184 ab8500_audio_set_bit_delay(dai, 1);
2185 break;
2186
2187 case SND_SOC_DAIFMT_DSP_B: /* L data MSB during FRM LRC */
2188 dev_dbg(dai->codec->dev,
2189 "%s: IF0 Protocol: DSP B (TDM)\n", __func__);
2190 val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0);
2191 ab8500_audio_set_bit_delay(dai, 0);
2192 break;
2193
2194 default:
2195 dev_err(dai->codec->dev,
2196 "%s: ERROR: Unsupported format (0x%x)!\n",
2197 __func__, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
2198 return -EINVAL;
2199 }
2200
2201 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2202 case SND_SOC_DAIFMT_NB_NF: /* normal bit clock + frame */
2203 dev_dbg(dai->codec->dev,
2204 "%s: IF0: Normal bit clock, normal frame\n",
2205 __func__);
2206 break;
2207 case SND_SOC_DAIFMT_NB_IF: /* normal BCLK + inv FRM */
2208 dev_dbg(dai->codec->dev,
2209 "%s: IF0: Normal bit clock, inverted frame\n",
2210 __func__);
2211 val |= BIT(AB8500_DIGIFCONF2_FSYNC0P);
2212 break;
2213 case SND_SOC_DAIFMT_IB_NF: /* invert BCLK + nor FRM */
2214 dev_dbg(dai->codec->dev,
2215 "%s: IF0: Inverted bit clock, normal frame\n",
2216 __func__);
2217 val |= BIT(AB8500_DIGIFCONF2_BITCLK0P);
2218 break;
2219 case SND_SOC_DAIFMT_IB_IF: /* invert BCLK + FRM */
2220 dev_dbg(dai->codec->dev,
2221 "%s: IF0: Inverted bit clock, inverted frame\n",
2222 __func__);
2223 val |= BIT(AB8500_DIGIFCONF2_FSYNC0P);
2224 val |= BIT(AB8500_DIGIFCONF2_BITCLK0P);
2225 break;
2226 default:
2227 dev_err(dai->codec->dev,
2228 "%s: ERROR: Unsupported INV mask 0x%x\n",
2229 __func__, fmt & SND_SOC_DAIFMT_INV_MASK);
2230 return -EINVAL;
2231 }
2232
2233 snd_soc_update_bits(codec, AB8500_DIGIFCONF2, mask, val);
2234
2235 return 0;
2236}
2237
2238static int ab8500_codec_set_dai_tdm_slot(struct snd_soc_dai *dai,
2239 unsigned int tx_mask, unsigned int rx_mask,
2240 int slots, int slot_width)
2241{
2242 struct snd_soc_codec *codec = dai->codec;
b2962633 2243 unsigned int val, mask, slot, slots_active;
679d7abd
OL		 2244
2245 mask = BIT(AB8500_DIGIFCONF2_IF0WL0) |
2246 BIT(AB8500_DIGIFCONF2_IF0WL1);
2247 val = 0;
2248
2249 switch (slot_width) {
2250 case 16:
2251 break;
2252 case 20:
2253 val |= BIT(AB8500_DIGIFCONF2_IF0WL0);
2254 break;
2255 case 24:
2256 val |= BIT(AB8500_DIGIFCONF2_IF0WL1);
2257 break;
2258 case 32:
2259 val |= BIT(AB8500_DIGIFCONF2_IF0WL1) |
2260 BIT(AB8500_DIGIFCONF2_IF0WL0);
2261 break;
2262 default:
2263 dev_err(dai->codec->dev, "%s: Unsupported slot-width 0x%x\n",
2264 __func__, slot_width);
2265 return -EINVAL;
2266 }
2267
2268 dev_dbg(dai->codec->dev, "%s: IF0 slot-width: %d bits.\n",
2269 __func__, slot_width);
2270 snd_soc_update_bits(codec, AB8500_DIGIFCONF2, mask, val);
2271
2272 /* Setup TDM clocking according to slot count */
2273 dev_dbg(dai->codec->dev, "%s: Slots, total: %d\n", __func__, slots);
2274 mask = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0) |
2275 BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1);
2276 switch (slots) {
2277 case 2:
2278 val = AB8500_MASK_NONE;
2279 break;
2280 case 4:
2281 val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0);
2282 break;
2283 case 8:
2284 val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1);
2285 break;
2286 case 16:
2287 val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0) |
2288 BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1);
2289 break;
2290 default:
2291 dev_err(dai->codec->dev,
2292 "%s: ERROR: Unsupported number of slots (%d)!\n",
2293 __func__, slots);
2294 return -EINVAL;
2295 }
2296 snd_soc_update_bits(codec, AB8500_DIGIFCONF1, mask, val);
2297
2298 /* Setup TDM DA according to active tx slots */
b2962633
FB		 2299
2300 if (tx_mask & ~0xff)
2301 return -EINVAL;
2302
679d7abd 2303 mask = AB8500_DASLOTCONFX_SLTODAX_MASK;
b2962633 2304 tx_mask = tx_mask << AB8500_DA_DATA0_OFFSET;
679d7abd 2305 slots_active = hweight32(tx_mask);
b2962633 2306
679d7abd
OL		 2307 dev_dbg(dai->codec->dev, "%s: Slots, active, TX: %d\n", __func__,
2308 slots_active);
b2962633 2309
679d7abd
OL		 2310 switch (slots_active) {
2311 case 0:
2312 break;
2313 case 1:
166a34d2 2314 slot = ffs(tx_mask);
b2962633
FB		 2315 snd_soc_update_bits(codec, AB8500_DASLOTCONF1, mask, slot);
2316 snd_soc_update_bits(codec, AB8500_DASLOTCONF3, mask, slot);
2317 snd_soc_update_bits(codec, AB8500_DASLOTCONF2, mask, slot);
2318 snd_soc_update_bits(codec, AB8500_DASLOTCONF4, mask, slot);
679d7abd
OL		 2319 break;
2320 case 2:
166a34d2 2321 slot = ffs(tx_mask);
b2962633
FB		 2322 snd_soc_update_bits(codec, AB8500_DASLOTCONF1, mask, slot);
2323 snd_soc_update_bits(codec, AB8500_DASLOTCONF3, mask, slot);
166a34d2 2324 slot = fls(tx_mask);
b2962633
FB		 2325 snd_soc_update_bits(codec, AB8500_DASLOTCONF2, mask, slot);
2326 snd_soc_update_bits(codec, AB8500_DASLOTCONF4, mask, slot);
679d7abd
OL		 2327 break;
2328 case 8:
2329 dev_dbg(dai->codec->dev,
2330 "%s: In 8-channel mode DA-from-slot mapping is set manually.",
2331 __func__);
2332 break;
2333 default:
2334 dev_err(dai->codec->dev,
2335 "%s: Unsupported number of active TX-slots (%d)!\n",
2336 __func__, slots_active);
2337 return -EINVAL;
2338 }
2339
2340 /* Setup TDM AD according to active RX-slots */
da33d723
FB		 2341
2342 if (rx_mask & ~0xff)
2343 return -EINVAL;
2344
2345 rx_mask = rx_mask << AB8500_AD_DATA0_OFFSET;
679d7abd 2346 slots_active = hweight32(rx_mask);
da33d723 2347
679d7abd
OL		 2348 dev_dbg(dai->codec->dev, "%s: Slots, active, RX: %d\n", __func__,
2349 slots_active);
da33d723 2350
679d7abd
OL		 2351 switch (slots_active) {
2352 case 0:
2353 break;
2354 case 1:
166a34d2 2355 slot = ffs(rx_mask);
da33d723
FB		 2356 snd_soc_update_bits(codec, AB8500_ADSLOTSEL(slot),
2357 AB8500_MASK_SLOT(slot),
2358 AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT3, slot));
679d7abd
OL		 2359 break;
2360 case 2:
166a34d2 2361 slot = ffs(rx_mask);
da33d723
FB		 2362 snd_soc_update_bits(codec,
2363 AB8500_ADSLOTSEL(slot),
2364 AB8500_MASK_SLOT(slot),
2365 AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT3, slot));
166a34d2 2366 slot = fls(rx_mask);
679d7abd 2367 snd_soc_update_bits(codec,
da33d723
FB		 2368 AB8500_ADSLOTSEL(slot),
2369 AB8500_MASK_SLOT(slot),
2370 AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT2, slot));
679d7abd
OL		 2371 break;
2372 case 8:
2373 dev_dbg(dai->codec->dev,
2374 "%s: In 8-channel mode AD-to-slot mapping is set manually.",
2375 __func__);
2376 break;
2377 default:
2378 dev_err(dai->codec->dev,
2379 "%s: Unsupported number of active RX-slots (%d)!\n",
2380 __func__, slots_active);
2381 return -EINVAL;
2382 }
2383
2384 return 0;
2385}
2386
7f92581b
FB		 2387static const struct snd_soc_dai_ops ab8500_codec_ops = {
2388 .set_fmt = ab8500_codec_set_dai_fmt,
2389 .set_tdm_slot = ab8500_codec_set_dai_tdm_slot,
2390};
2391
c3f68171 2392static struct snd_soc_dai_driver ab8500_codec_dai[] = {
679d7abd
OL		 2393 {
2394 .name = "ab8500-codec-dai.0",
2395 .id = 0,
2396 .playback = {
2397 .stream_name = "ab8500_0p",
2398 .channels_min = 1,
2399 .channels_max = 8,
2400 .rates = AB8500_SUPPORTED_RATE,
2401 .formats = AB8500_SUPPORTED_FMT,
2402 },
7f92581b 2403 .ops = &ab8500_codec_ops,
679d7abd
OL		 2404 .symmetric_rates = 1
2405 },
2406 {
2407 .name = "ab8500-codec-dai.1",
2408 .id = 1,
2409 .capture = {
2410 .stream_name = "ab8500_0c",
2411 .channels_min = 1,
2412 .channels_max = 8,
2413 .rates = AB8500_SUPPORTED_RATE,
2414 .formats = AB8500_SUPPORTED_FMT,
2415 },
7f92581b 2416 .ops = &ab8500_codec_ops,
679d7abd
OL		 2417 .symmetric_rates = 1
2418 }
2419};
2420
db5c811d
LJ		 2421static void ab8500_codec_of_probe(struct device *dev, struct device_node *np,
2422 struct ab8500_codec_platform_data *codec)
2423{
2424 u32 value;
2425
2426 if (of_get_property(np, "stericsson,amic1-type-single-ended", NULL))
2427 codec->amics.mic1_type = AMIC_TYPE_SINGLE_ENDED;
2428 else
2429 codec->amics.mic1_type = AMIC_TYPE_DIFFERENTIAL;
2430
2431 if (of_get_property(np, "stericsson,amic2-type-single-ended", NULL))
2432 codec->amics.mic2_type = AMIC_TYPE_SINGLE_ENDED;
2433 else
2434 codec->amics.mic2_type = AMIC_TYPE_DIFFERENTIAL;
2435
2436 /* Has a non-standard Vamic been requested? */
2437 if (of_get_property(np, "stericsson,amic1a-bias-vamic2", NULL))
2438 codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC2;
2439 else
2440 codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC1;
2441
2442 if (of_get_property(np, "stericsson,amic1b-bias-vamic2", NULL))
2443 codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC2;
2444 else
2445 codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC1;
2446
2447 if (of_get_property(np, "stericsson,amic2-bias-vamic1", NULL))
2448 codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC1;
2449 else
2450 codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC2;
2451
2452 if (!of_property_read_u32(np, "stericsson,earpeice-cmv", &value)) {
2453 switch (value) {
2454 case 950 :
2455 codec->ear_cmv = EAR_CMV_0_95V;
2456 break;
2457 case 1100 :
2458 codec->ear_cmv = EAR_CMV_1_10V;
2459 break;
2460 case 1270 :
2461 codec->ear_cmv = EAR_CMV_1_27V;
2462 break;
2463 case 1580 :
2464 codec->ear_cmv = EAR_CMV_1_58V;
2465 break;
2466 default :
2467 codec->ear_cmv = EAR_CMV_UNKNOWN;
2468 dev_err(dev, "Unsuitable earpiece voltage found in DT\n");
2469 }
2470 } else {
2471 dev_warn(dev, "No earpiece voltage found in DT - using default\n");
2472 codec->ear_cmv = EAR_CMV_0_95V;
2473 }
2474}
2475
679d7abd
OL		 2476static int ab8500_codec_probe(struct snd_soc_codec *codec)
2477{
2478 struct device *dev = codec->dev;
db5c811d 2479 struct device_node *np = dev->of_node;
679d7abd
OL		 2480 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(dev);
2481 struct ab8500_platform_data *pdata;
2482 struct filter_control *fc;
2483 int status;
2484
2485 dev_dbg(dev, "%s: Enter.\n", __func__);
2486
d95e9337
MB		 2487 /* Setup AB8500 according to board-settings */
2488 pdata = dev_get_platdata(dev->parent);
2489
db5c811d
LJ		 2490 if (np) {
2491 if (!pdata)
2492 pdata = devm_kzalloc(dev,
2493 sizeof(struct ab8500_platform_data),
2494 GFP_KERNEL);
2495
2496 if (pdata && !pdata->codec)
2497 pdata->codec
2498 = devm_kzalloc(dev,
2499 sizeof(struct ab8500_codec_platform_data),
2500 GFP_KERNEL);
2501
2502 if (!(pdata && pdata->codec))
2503 return -ENOMEM;
2504
2505 ab8500_codec_of_probe(dev, np, pdata->codec);
2506
2507 } else {
2508 if (!(pdata && pdata->codec)) {
2509 dev_err(dev, "No codec platform data or DT found\n");
2510 return -EINVAL;
2511 }
2512 }
2513
679d7abd
OL		 2514 status = ab8500_audio_setup_mics(codec, &pdata->codec->amics);
2515 if (status < 0) {
2516 pr_err("%s: Failed to setup mics (%d)!\n", __func__, status);
2517 return status;
2518 }
2519 status = ab8500_audio_set_ear_cmv(codec, pdata->codec->ear_cmv);
2520 if (status < 0) {
2521 pr_err("%s: Failed to set earpiece CM-voltage (%d)!\n",
2522 __func__, status);
2523 return status;
2524 }
2525
2526 status = ab8500_audio_init_audioblock(codec);
2527 if (status < 0) {
2528 dev_err(dev, "%s: failed to init audio-block (%d)!\n",
2529 __func__, status);
2530 return status;
2531 }
2532
2533 /* Override HW-defaults */
51f20e4c
MB		 2534 snd_soc_write(codec, AB8500_ANACONF5,
2535 BIT(AB8500_ANACONF5_HSAUTOEN));
2536 snd_soc_write(codec, AB8500_SHORTCIRCONF,
2537 BIT(AB8500_SHORTCIRCONF_HSZCDDIS));
679d7abd
OL		 2538
2539 /* Add filter controls */
2540 status = snd_soc_add_codec_controls(codec, ab8500_filter_controls,
2541 ARRAY_SIZE(ab8500_filter_controls));
2542 if (status < 0) {
2543 dev_err(dev,
2544 "%s: failed to add ab8500 filter controls (%d).\n",
2545 __func__, status);
2546 return status;
2547 }
2548 fc = (struct filter_control *)
2549 &ab8500_filter_controls[AB8500_FILTER_ANC_FIR].private_value;
2550 drvdata->anc_fir_values = (long *)fc->value;
2551 fc = (struct filter_control *)
2552 &ab8500_filter_controls[AB8500_FILTER_ANC_IIR].private_value;
2553 drvdata->anc_iir_values = (long *)fc->value;
2554 fc = (struct filter_control *)
2555 &ab8500_filter_controls[AB8500_FILTER_SID_FIR].private_value;
2556 drvdata->sid_fir_values = (long *)fc->value;
2557
2558 (void)snd_soc_dapm_disable_pin(&codec->dapm, "ANC Configure Input");
2559
2560 mutex_init(&drvdata->anc_lock);
2561
2562 return status;
2563}
2564
2565static struct snd_soc_codec_driver ab8500_codec_driver = {
2566 .probe = ab8500_codec_probe,
63e6d43b
LJ		 2567 .read = ab8500_codec_read_reg,
2568 .write = ab8500_codec_write_reg,
2569 .reg_word_size = sizeof(u8),
679d7abd
OL		 2570 .controls = ab8500_ctrls,
2571 .num_controls = ARRAY_SIZE(ab8500_ctrls),
2572 .dapm_widgets = ab8500_dapm_widgets,
2573 .num_dapm_widgets = ARRAY_SIZE(ab8500_dapm_widgets),
2574 .dapm_routes = ab8500_dapm_routes,
2575 .num_dapm_routes = ARRAY_SIZE(ab8500_dapm_routes),
2576};
2577
7a79e94e 2578static int ab8500_codec_driver_probe(struct platform_device *pdev)
679d7abd
OL		 2579{
2580 int status;
2581 struct ab8500_codec_drvdata *drvdata;
2582
2583 dev_dbg(&pdev->dev, "%s: Enter.\n", __func__);
2584
2585 /* Create driver private-data struct */
2586 drvdata = devm_kzalloc(&pdev->dev, sizeof(struct ab8500_codec_drvdata),
2587 GFP_KERNEL);
00ecdd93
TI		 2588 if (!drvdata)
2589 return -ENOMEM;
679d7abd
OL		 2590 drvdata->sid_status = SID_UNCONFIGURED;
2591 drvdata->anc_status = ANC_UNCONFIGURED;
2592 dev_set_drvdata(&pdev->dev, drvdata);
2593
2594 dev_dbg(&pdev->dev, "%s: Register codec.\n", __func__);
2595 status = snd_soc_register_codec(&pdev->dev, &ab8500_codec_driver,
2596 ab8500_codec_dai,
2597 ARRAY_SIZE(ab8500_codec_dai));
2598 if (status < 0)
2599 dev_err(&pdev->dev,
2600 "%s: Error: Failed to register codec (%d).\n",
2601 __func__, status);
2602
2603 return status;
2604}
2605
7a79e94e 2606static int ab8500_codec_driver_remove(struct platform_device *pdev)
679d7abd 2607{
38bfd48b 2608 dev_dbg(&pdev->dev, "%s Enter.\n", __func__);
679d7abd
OL		 2609
2610 snd_soc_unregister_codec(&pdev->dev);
2611
2612 return 0;
2613}
2614
2615static struct platform_driver ab8500_codec_platform_driver = {
2616 .driver = {
2617 .name = "ab8500-codec",
2618 .owner = THIS_MODULE,
2619 },
2620 .probe = ab8500_codec_driver_probe,
7a79e94e 2621 .remove = ab8500_codec_driver_remove,
679d7abd
OL		 2622 .suspend = NULL,
2623 .resume = NULL,
2624};
2625module_platform_driver(ab8500_codec_platform_driver);
2626
85f24391 2627MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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