Commit | Line | Data |
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631ed8a2 LPC |
1 | /* |
2 | * Driver for ADAU1701 SigmaDSP processor | |
3 | * | |
4 | * Copyright 2011 Analog Devices Inc. | |
5 | * Author: Lars-Peter Clausen <lars@metafoo.de> | |
6 | * based on an inital version by Cliff Cai <cliff.cai@analog.com> | |
7 | * | |
8 | * Licensed under the GPL-2 or later. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/i2c.h> | |
14 | #include <linux/delay.h> | |
631ed8a2 | 15 | #include <linux/slab.h> |
04561eac DM |
16 | #include <linux/of.h> |
17 | #include <linux/of_gpio.h> | |
18 | #include <linux/of_device.h> | |
45405d58 | 19 | #include <linux/regmap.h> |
631ed8a2 LPC |
20 | #include <sound/core.h> |
21 | #include <sound/pcm.h> | |
22 | #include <sound/pcm_params.h> | |
23 | #include <sound/soc.h> | |
24 | ||
a3a1ec66 LPC |
25 | #include <asm/unaligned.h> |
26 | ||
40216ce7 | 27 | #include "sigmadsp.h" |
631ed8a2 LPC |
28 | #include "adau1701.h" |
29 | ||
a3a1ec66 LPC |
30 | #define ADAU1701_SAFELOAD_DATA(i) (0x0810 + (i)) |
31 | #define ADAU1701_SAFELOAD_ADDR(i) (0x0815 + (i)) | |
32 | ||
45405d58 DM |
33 | #define ADAU1701_DSPCTRL 0x081c |
34 | #define ADAU1701_SEROCTL 0x081e | |
35 | #define ADAU1701_SERICTL 0x081f | |
631ed8a2 | 36 | |
97d0a868 DM |
37 | #define ADAU1701_AUXNPOW 0x0822 |
38 | #define ADAU1701_PINCONF_0 0x0820 | |
39 | #define ADAU1701_PINCONF_1 0x0821 | |
45405d58 | 40 | #define ADAU1701_AUXNPOW 0x0822 |
631ed8a2 | 41 | |
45405d58 DM |
42 | #define ADAU1701_OSCIPOW 0x0826 |
43 | #define ADAU1701_DACSET 0x0827 | |
631ed8a2 | 44 | |
45405d58 | 45 | #define ADAU1701_MAX_REGISTER 0x0828 |
631ed8a2 LPC |
46 | |
47 | #define ADAU1701_DSPCTRL_CR (1 << 2) | |
48 | #define ADAU1701_DSPCTRL_DAM (1 << 3) | |
49 | #define ADAU1701_DSPCTRL_ADM (1 << 4) | |
a3a1ec66 | 50 | #define ADAU1701_DSPCTRL_IST (1 << 5) |
631ed8a2 LPC |
51 | #define ADAU1701_DSPCTRL_SR_48 0x00 |
52 | #define ADAU1701_DSPCTRL_SR_96 0x01 | |
53 | #define ADAU1701_DSPCTRL_SR_192 0x02 | |
54 | #define ADAU1701_DSPCTRL_SR_MASK 0x03 | |
55 | ||
56 | #define ADAU1701_SEROCTL_INV_LRCLK 0x2000 | |
57 | #define ADAU1701_SEROCTL_INV_BCLK 0x1000 | |
58 | #define ADAU1701_SEROCTL_MASTER 0x0800 | |
59 | ||
60 | #define ADAU1701_SEROCTL_OBF16 0x0000 | |
61 | #define ADAU1701_SEROCTL_OBF8 0x0200 | |
62 | #define ADAU1701_SEROCTL_OBF4 0x0400 | |
63 | #define ADAU1701_SEROCTL_OBF2 0x0600 | |
64 | #define ADAU1701_SEROCTL_OBF_MASK 0x0600 | |
65 | ||
66 | #define ADAU1701_SEROCTL_OLF1024 0x0000 | |
67 | #define ADAU1701_SEROCTL_OLF512 0x0080 | |
68 | #define ADAU1701_SEROCTL_OLF256 0x0100 | |
69 | #define ADAU1701_SEROCTL_OLF_MASK 0x0180 | |
70 | ||
71 | #define ADAU1701_SEROCTL_MSB_DEALY1 0x0000 | |
72 | #define ADAU1701_SEROCTL_MSB_DEALY0 0x0004 | |
73 | #define ADAU1701_SEROCTL_MSB_DEALY8 0x0008 | |
74 | #define ADAU1701_SEROCTL_MSB_DEALY12 0x000c | |
75 | #define ADAU1701_SEROCTL_MSB_DEALY16 0x0010 | |
76 | #define ADAU1701_SEROCTL_MSB_DEALY_MASK 0x001c | |
77 | ||
78 | #define ADAU1701_SEROCTL_WORD_LEN_24 0x0000 | |
79 | #define ADAU1701_SEROCTL_WORD_LEN_20 0x0001 | |
e20970ad | 80 | #define ADAU1701_SEROCTL_WORD_LEN_16 0x0002 |
631ed8a2 LPC |
81 | #define ADAU1701_SEROCTL_WORD_LEN_MASK 0x0003 |
82 | ||
83 | #define ADAU1701_AUXNPOW_VBPD 0x40 | |
84 | #define ADAU1701_AUXNPOW_VRPD 0x20 | |
85 | ||
86 | #define ADAU1701_SERICTL_I2S 0 | |
87 | #define ADAU1701_SERICTL_LEFTJ 1 | |
88 | #define ADAU1701_SERICTL_TDM 2 | |
89 | #define ADAU1701_SERICTL_RIGHTJ_24 3 | |
90 | #define ADAU1701_SERICTL_RIGHTJ_20 4 | |
91 | #define ADAU1701_SERICTL_RIGHTJ_18 5 | |
92 | #define ADAU1701_SERICTL_RIGHTJ_16 6 | |
93 | #define ADAU1701_SERICTL_MODE_MASK 7 | |
94 | #define ADAU1701_SERICTL_INV_BCLK BIT(3) | |
95 | #define ADAU1701_SERICTL_INV_LRCLK BIT(4) | |
96 | ||
97 | #define ADAU1701_OSCIPOW_OPD 0x04 | |
98 | #define ADAU1701_DACSET_DACINIT 1 | |
99 | ||
ba51cbb8 | 100 | #define ADAU1707_CLKDIV_UNSET (-1U) |
2352d4bf | 101 | |
631ed8a2 LPC |
102 | #define ADAU1701_FIRMWARE "adau1701.bin" |
103 | ||
104 | struct adau1701 { | |
f724ba3b | 105 | int gpio_nreset; |
2352d4bf | 106 | int gpio_pll_mode[2]; |
631ed8a2 | 107 | unsigned int dai_fmt; |
2352d4bf DM |
108 | unsigned int pll_clkdiv; |
109 | unsigned int sysclk; | |
45405d58 | 110 | struct regmap *regmap; |
a3a1ec66 | 111 | struct i2c_client *client; |
97d0a868 | 112 | u8 pin_config[12]; |
d48b088e LPC |
113 | |
114 | struct sigmadsp *sigmadsp; | |
631ed8a2 LPC |
115 | }; |
116 | ||
117 | static const struct snd_kcontrol_new adau1701_controls[] = { | |
118 | SOC_SINGLE("Master Capture Switch", ADAU1701_DSPCTRL, 4, 1, 0), | |
119 | }; | |
120 | ||
121 | static const struct snd_soc_dapm_widget adau1701_dapm_widgets[] = { | |
122 | SND_SOC_DAPM_DAC("DAC0", "Playback", ADAU1701_AUXNPOW, 3, 1), | |
123 | SND_SOC_DAPM_DAC("DAC1", "Playback", ADAU1701_AUXNPOW, 2, 1), | |
124 | SND_SOC_DAPM_DAC("DAC2", "Playback", ADAU1701_AUXNPOW, 1, 1), | |
125 | SND_SOC_DAPM_DAC("DAC3", "Playback", ADAU1701_AUXNPOW, 0, 1), | |
126 | SND_SOC_DAPM_ADC("ADC", "Capture", ADAU1701_AUXNPOW, 7, 1), | |
127 | ||
128 | SND_SOC_DAPM_OUTPUT("OUT0"), | |
129 | SND_SOC_DAPM_OUTPUT("OUT1"), | |
130 | SND_SOC_DAPM_OUTPUT("OUT2"), | |
131 | SND_SOC_DAPM_OUTPUT("OUT3"), | |
132 | SND_SOC_DAPM_INPUT("IN0"), | |
133 | SND_SOC_DAPM_INPUT("IN1"), | |
134 | }; | |
135 | ||
136 | static const struct snd_soc_dapm_route adau1701_dapm_routes[] = { | |
137 | { "OUT0", NULL, "DAC0" }, | |
138 | { "OUT1", NULL, "DAC1" }, | |
139 | { "OUT2", NULL, "DAC2" }, | |
140 | { "OUT3", NULL, "DAC3" }, | |
141 | ||
142 | { "ADC", NULL, "IN0" }, | |
143 | { "ADC", NULL, "IN1" }, | |
144 | }; | |
145 | ||
45405d58 | 146 | static unsigned int adau1701_register_size(struct device *dev, |
631ed8a2 LPC |
147 | unsigned int reg) |
148 | { | |
149 | switch (reg) { | |
97d0a868 DM |
150 | case ADAU1701_PINCONF_0: |
151 | case ADAU1701_PINCONF_1: | |
152 | return 3; | |
631ed8a2 LPC |
153 | case ADAU1701_DSPCTRL: |
154 | case ADAU1701_SEROCTL: | |
155 | case ADAU1701_AUXNPOW: | |
156 | case ADAU1701_OSCIPOW: | |
157 | case ADAU1701_DACSET: | |
158 | return 2; | |
159 | case ADAU1701_SERICTL: | |
160 | return 1; | |
161 | } | |
162 | ||
45405d58 | 163 | dev_err(dev, "Unsupported register address: %d\n", reg); |
631ed8a2 LPC |
164 | return 0; |
165 | } | |
166 | ||
45405d58 | 167 | static bool adau1701_volatile_reg(struct device *dev, unsigned int reg) |
631ed8a2 | 168 | { |
45405d58 DM |
169 | switch (reg) { |
170 | case ADAU1701_DACSET: | |
a3a1ec66 | 171 | case ADAU1701_DSPCTRL: |
45405d58 DM |
172 | return true; |
173 | default: | |
174 | return false; | |
175 | } | |
176 | } | |
177 | ||
178 | static int adau1701_reg_write(void *context, unsigned int reg, | |
179 | unsigned int value) | |
180 | { | |
181 | struct i2c_client *client = context; | |
c2097409 | 182 | unsigned int i; |
631ed8a2 | 183 | unsigned int size; |
97d0a868 | 184 | uint8_t buf[5]; |
c2097409 | 185 | int ret; |
631ed8a2 | 186 | |
45405d58 | 187 | size = adau1701_register_size(&client->dev, reg); |
631ed8a2 LPC |
188 | if (size == 0) |
189 | return -EINVAL; | |
190 | ||
45405d58 DM |
191 | buf[0] = reg >> 8; |
192 | buf[1] = reg & 0xff; | |
631ed8a2 LPC |
193 | |
194 | for (i = size + 1; i >= 2; --i) { | |
195 | buf[i] = value; | |
196 | value >>= 8; | |
197 | } | |
198 | ||
45405d58 | 199 | ret = i2c_master_send(client, buf, size + 2); |
631ed8a2 LPC |
200 | if (ret == size + 2) |
201 | return 0; | |
202 | else if (ret < 0) | |
203 | return ret; | |
204 | else | |
205 | return -EIO; | |
206 | } | |
207 | ||
45405d58 DM |
208 | static int adau1701_reg_read(void *context, unsigned int reg, |
209 | unsigned int *value) | |
631ed8a2 | 210 | { |
45405d58 DM |
211 | int ret; |
212 | unsigned int i; | |
213 | unsigned int size; | |
214 | uint8_t send_buf[2], recv_buf[3]; | |
215 | struct i2c_client *client = context; | |
216 | struct i2c_msg msgs[2]; | |
217 | ||
218 | size = adau1701_register_size(&client->dev, reg); | |
219 | if (size == 0) | |
220 | return -EINVAL; | |
631ed8a2 | 221 | |
45405d58 DM |
222 | send_buf[0] = reg >> 8; |
223 | send_buf[1] = reg & 0xff; | |
224 | ||
225 | msgs[0].addr = client->addr; | |
226 | msgs[0].len = sizeof(send_buf); | |
227 | msgs[0].buf = send_buf; | |
228 | msgs[0].flags = 0; | |
229 | ||
230 | msgs[1].addr = client->addr; | |
231 | msgs[1].len = size; | |
232 | msgs[1].buf = recv_buf; | |
233 | msgs[1].flags = I2C_M_RD; | |
234 | ||
235 | ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); | |
236 | if (ret < 0) | |
631ed8a2 | 237 | return ret; |
45405d58 DM |
238 | else if (ret != ARRAY_SIZE(msgs)) |
239 | return -EIO; | |
240 | ||
241 | *value = 0; | |
242 | ||
3ad80b82 DM |
243 | for (i = 0; i < size; i++) { |
244 | *value <<= 8; | |
245 | *value |= recv_buf[i]; | |
246 | } | |
631ed8a2 | 247 | |
45405d58 | 248 | return 0; |
631ed8a2 LPC |
249 | } |
250 | ||
a3a1ec66 LPC |
251 | static int adau1701_safeload(struct sigmadsp *sigmadsp, unsigned int addr, |
252 | const uint8_t bytes[], size_t len) | |
253 | { | |
254 | struct i2c_client *client = to_i2c_client(sigmadsp->dev); | |
255 | struct adau1701 *adau1701 = i2c_get_clientdata(client); | |
256 | unsigned int val; | |
257 | unsigned int i; | |
258 | uint8_t buf[10]; | |
259 | int ret; | |
260 | ||
261 | ret = regmap_read(adau1701->regmap, ADAU1701_DSPCTRL, &val); | |
262 | if (ret) | |
263 | return ret; | |
264 | ||
265 | if (val & ADAU1701_DSPCTRL_IST) | |
266 | msleep(50); | |
267 | ||
268 | for (i = 0; i < len / 4; i++) { | |
269 | put_unaligned_le16(ADAU1701_SAFELOAD_DATA(i), buf); | |
270 | buf[2] = 0x00; | |
271 | memcpy(buf + 3, bytes + i * 4, 4); | |
272 | ret = i2c_master_send(client, buf, 7); | |
273 | if (ret < 0) | |
274 | return ret; | |
275 | else if (ret != 7) | |
276 | return -EIO; | |
277 | ||
278 | put_unaligned_le16(ADAU1701_SAFELOAD_ADDR(i), buf); | |
279 | put_unaligned_le16(addr + i, buf + 2); | |
280 | ret = i2c_master_send(client, buf, 4); | |
281 | if (ret < 0) | |
282 | return ret; | |
283 | else if (ret != 4) | |
284 | return -EIO; | |
285 | } | |
286 | ||
287 | return regmap_update_bits(adau1701->regmap, ADAU1701_DSPCTRL, | |
288 | ADAU1701_DSPCTRL_IST, ADAU1701_DSPCTRL_IST); | |
289 | } | |
290 | ||
291 | static const struct sigmadsp_ops adau1701_sigmadsp_ops = { | |
292 | .safeload = adau1701_safeload, | |
293 | }; | |
294 | ||
d48b088e LPC |
295 | static int adau1701_reset(struct snd_soc_codec *codec, unsigned int clkdiv, |
296 | unsigned int rate) | |
631ed8a2 | 297 | { |
f724ba3b | 298 | struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec); |
de9fc724 | 299 | int ret; |
f724ba3b | 300 | |
d48b088e LPC |
301 | sigmadsp_reset(adau1701->sigmadsp); |
302 | ||
2352d4bf DM |
303 | if (clkdiv != ADAU1707_CLKDIV_UNSET && |
304 | gpio_is_valid(adau1701->gpio_pll_mode[0]) && | |
305 | gpio_is_valid(adau1701->gpio_pll_mode[1])) { | |
306 | switch (clkdiv) { | |
307 | case 64: | |
9190aeb4 MB |
308 | gpio_set_value_cansleep(adau1701->gpio_pll_mode[0], 0); |
309 | gpio_set_value_cansleep(adau1701->gpio_pll_mode[1], 0); | |
2352d4bf DM |
310 | break; |
311 | case 256: | |
9190aeb4 MB |
312 | gpio_set_value_cansleep(adau1701->gpio_pll_mode[0], 0); |
313 | gpio_set_value_cansleep(adau1701->gpio_pll_mode[1], 1); | |
2352d4bf DM |
314 | break; |
315 | case 384: | |
9190aeb4 MB |
316 | gpio_set_value_cansleep(adau1701->gpio_pll_mode[0], 1); |
317 | gpio_set_value_cansleep(adau1701->gpio_pll_mode[1], 0); | |
2352d4bf DM |
318 | break; |
319 | case 0: /* fallback */ | |
320 | case 512: | |
9190aeb4 MB |
321 | gpio_set_value_cansleep(adau1701->gpio_pll_mode[0], 1); |
322 | gpio_set_value_cansleep(adau1701->gpio_pll_mode[1], 1); | |
2352d4bf DM |
323 | break; |
324 | } | |
325 | } | |
326 | ||
327 | adau1701->pll_clkdiv = clkdiv; | |
328 | ||
de9fc724 | 329 | if (gpio_is_valid(adau1701->gpio_nreset)) { |
9190aeb4 | 330 | gpio_set_value_cansleep(adau1701->gpio_nreset, 0); |
de9fc724 DM |
331 | /* minimum reset time is 20ns */ |
332 | udelay(1); | |
9190aeb4 | 333 | gpio_set_value_cansleep(adau1701->gpio_nreset, 1); |
de9fc724 DM |
334 | /* power-up time may be as long as 85ms */ |
335 | mdelay(85); | |
336 | } | |
f724ba3b | 337 | |
2352d4bf DM |
338 | /* |
339 | * Postpone the firmware download to a point in time when we | |
340 | * know the correct PLL setup | |
341 | */ | |
342 | if (clkdiv != ADAU1707_CLKDIV_UNSET) { | |
d48b088e | 343 | ret = sigmadsp_setup(adau1701->sigmadsp, rate); |
2352d4bf DM |
344 | if (ret) { |
345 | dev_warn(codec->dev, "Failed to load firmware\n"); | |
346 | return ret; | |
347 | } | |
f724ba3b DM |
348 | } |
349 | ||
45405d58 DM |
350 | regmap_write(adau1701->regmap, ADAU1701_DACSET, ADAU1701_DACSET_DACINIT); |
351 | regmap_write(adau1701->regmap, ADAU1701_DSPCTRL, ADAU1701_DSPCTRL_CR); | |
352 | ||
353 | regcache_mark_dirty(adau1701->regmap); | |
354 | regcache_sync(adau1701->regmap); | |
f724ba3b DM |
355 | |
356 | return 0; | |
631ed8a2 LPC |
357 | } |
358 | ||
359 | static int adau1701_set_capture_pcm_format(struct snd_soc_codec *codec, | |
9b58e716 | 360 | struct snd_pcm_hw_params *params) |
631ed8a2 LPC |
361 | { |
362 | struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec); | |
363 | unsigned int mask = ADAU1701_SEROCTL_WORD_LEN_MASK; | |
364 | unsigned int val; | |
365 | ||
9b58e716 MB |
366 | switch (params_width(params)) { |
367 | case 16: | |
631ed8a2 LPC |
368 | val = ADAU1701_SEROCTL_WORD_LEN_16; |
369 | break; | |
9b58e716 | 370 | case 20: |
631ed8a2 LPC |
371 | val = ADAU1701_SEROCTL_WORD_LEN_20; |
372 | break; | |
9b58e716 | 373 | case 24: |
631ed8a2 LPC |
374 | val = ADAU1701_SEROCTL_WORD_LEN_24; |
375 | break; | |
376 | default: | |
377 | return -EINVAL; | |
378 | } | |
379 | ||
380 | if (adau1701->dai_fmt == SND_SOC_DAIFMT_RIGHT_J) { | |
9b58e716 MB |
381 | switch (params_width(params)) { |
382 | case 16: | |
631ed8a2 LPC |
383 | val |= ADAU1701_SEROCTL_MSB_DEALY16; |
384 | break; | |
9b58e716 | 385 | case 20: |
631ed8a2 LPC |
386 | val |= ADAU1701_SEROCTL_MSB_DEALY12; |
387 | break; | |
9b58e716 | 388 | case 24: |
631ed8a2 LPC |
389 | val |= ADAU1701_SEROCTL_MSB_DEALY8; |
390 | break; | |
391 | } | |
392 | mask |= ADAU1701_SEROCTL_MSB_DEALY_MASK; | |
393 | } | |
394 | ||
ee441140 | 395 | regmap_update_bits(adau1701->regmap, ADAU1701_SEROCTL, mask, val); |
631ed8a2 LPC |
396 | |
397 | return 0; | |
398 | } | |
399 | ||
400 | static int adau1701_set_playback_pcm_format(struct snd_soc_codec *codec, | |
9b58e716 | 401 | struct snd_pcm_hw_params *params) |
631ed8a2 LPC |
402 | { |
403 | struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec); | |
404 | unsigned int val; | |
405 | ||
406 | if (adau1701->dai_fmt != SND_SOC_DAIFMT_RIGHT_J) | |
407 | return 0; | |
408 | ||
9b58e716 MB |
409 | switch (params_width(params)) { |
410 | case 16: | |
631ed8a2 LPC |
411 | val = ADAU1701_SERICTL_RIGHTJ_16; |
412 | break; | |
9b58e716 | 413 | case 20: |
631ed8a2 LPC |
414 | val = ADAU1701_SERICTL_RIGHTJ_20; |
415 | break; | |
9b58e716 | 416 | case 24: |
631ed8a2 LPC |
417 | val = ADAU1701_SERICTL_RIGHTJ_24; |
418 | break; | |
419 | default: | |
420 | return -EINVAL; | |
421 | } | |
422 | ||
ee441140 | 423 | regmap_update_bits(adau1701->regmap, ADAU1701_SERICTL, |
631ed8a2 LPC |
424 | ADAU1701_SERICTL_MODE_MASK, val); |
425 | ||
426 | return 0; | |
427 | } | |
428 | ||
429 | static int adau1701_hw_params(struct snd_pcm_substream *substream, | |
430 | struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) | |
431 | { | |
e6968a17 | 432 | struct snd_soc_codec *codec = dai->codec; |
2352d4bf DM |
433 | struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec); |
434 | unsigned int clkdiv = adau1701->sysclk / params_rate(params); | |
631ed8a2 | 435 | unsigned int val; |
2352d4bf DM |
436 | int ret; |
437 | ||
438 | /* | |
439 | * If the mclk/lrclk ratio changes, the chip needs updated PLL | |
440 | * mode GPIO settings, and a full reset cycle, including a new | |
441 | * firmware upload. | |
442 | */ | |
443 | if (clkdiv != adau1701->pll_clkdiv) { | |
d48b088e | 444 | ret = adau1701_reset(codec, clkdiv, params_rate(params)); |
2352d4bf DM |
445 | if (ret < 0) |
446 | return ret; | |
447 | } | |
631ed8a2 LPC |
448 | |
449 | switch (params_rate(params)) { | |
450 | case 192000: | |
451 | val = ADAU1701_DSPCTRL_SR_192; | |
452 | break; | |
453 | case 96000: | |
454 | val = ADAU1701_DSPCTRL_SR_96; | |
455 | break; | |
456 | case 48000: | |
457 | val = ADAU1701_DSPCTRL_SR_48; | |
458 | break; | |
459 | default: | |
460 | return -EINVAL; | |
461 | } | |
462 | ||
ee441140 | 463 | regmap_update_bits(adau1701->regmap, ADAU1701_DSPCTRL, |
631ed8a2 LPC |
464 | ADAU1701_DSPCTRL_SR_MASK, val); |
465 | ||
631ed8a2 | 466 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
9b58e716 | 467 | return adau1701_set_playback_pcm_format(codec, params); |
631ed8a2 | 468 | else |
9b58e716 | 469 | return adau1701_set_capture_pcm_format(codec, params); |
631ed8a2 LPC |
470 | } |
471 | ||
472 | static int adau1701_set_dai_fmt(struct snd_soc_dai *codec_dai, | |
473 | unsigned int fmt) | |
474 | { | |
475 | struct snd_soc_codec *codec = codec_dai->codec; | |
476 | struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec); | |
477 | unsigned int serictl = 0x00, seroctl = 0x00; | |
478 | bool invert_lrclk; | |
479 | ||
480 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
481 | case SND_SOC_DAIFMT_CBM_CFM: | |
482 | /* master, 64-bits per sample, 1 frame per sample */ | |
483 | seroctl |= ADAU1701_SEROCTL_MASTER | ADAU1701_SEROCTL_OBF16 | |
484 | | ADAU1701_SEROCTL_OLF1024; | |
485 | break; | |
486 | case SND_SOC_DAIFMT_CBS_CFS: | |
487 | break; | |
488 | default: | |
489 | return -EINVAL; | |
490 | } | |
491 | ||
492 | /* clock inversion */ | |
493 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
494 | case SND_SOC_DAIFMT_NB_NF: | |
495 | invert_lrclk = false; | |
496 | break; | |
497 | case SND_SOC_DAIFMT_NB_IF: | |
498 | invert_lrclk = true; | |
499 | break; | |
500 | case SND_SOC_DAIFMT_IB_NF: | |
501 | invert_lrclk = false; | |
502 | serictl |= ADAU1701_SERICTL_INV_BCLK; | |
503 | seroctl |= ADAU1701_SEROCTL_INV_BCLK; | |
504 | break; | |
505 | case SND_SOC_DAIFMT_IB_IF: | |
506 | invert_lrclk = true; | |
507 | serictl |= ADAU1701_SERICTL_INV_BCLK; | |
508 | seroctl |= ADAU1701_SEROCTL_INV_BCLK; | |
509 | break; | |
510 | default: | |
511 | return -EINVAL; | |
512 | } | |
513 | ||
514 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
515 | case SND_SOC_DAIFMT_I2S: | |
516 | break; | |
517 | case SND_SOC_DAIFMT_LEFT_J: | |
518 | serictl |= ADAU1701_SERICTL_LEFTJ; | |
519 | seroctl |= ADAU1701_SEROCTL_MSB_DEALY0; | |
520 | invert_lrclk = !invert_lrclk; | |
521 | break; | |
522 | case SND_SOC_DAIFMT_RIGHT_J: | |
523 | serictl |= ADAU1701_SERICTL_RIGHTJ_24; | |
524 | seroctl |= ADAU1701_SEROCTL_MSB_DEALY8; | |
525 | invert_lrclk = !invert_lrclk; | |
526 | break; | |
527 | default: | |
528 | return -EINVAL; | |
529 | } | |
530 | ||
531 | if (invert_lrclk) { | |
532 | seroctl |= ADAU1701_SEROCTL_INV_LRCLK; | |
533 | serictl |= ADAU1701_SERICTL_INV_LRCLK; | |
534 | } | |
535 | ||
536 | adau1701->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; | |
537 | ||
45405d58 DM |
538 | regmap_write(adau1701->regmap, ADAU1701_SERICTL, serictl); |
539 | regmap_update_bits(adau1701->regmap, ADAU1701_SEROCTL, | |
631ed8a2 LPC |
540 | ~ADAU1701_SEROCTL_WORD_LEN_MASK, seroctl); |
541 | ||
542 | return 0; | |
543 | } | |
544 | ||
545 | static int adau1701_set_bias_level(struct snd_soc_codec *codec, | |
546 | enum snd_soc_bias_level level) | |
547 | { | |
548 | unsigned int mask = ADAU1701_AUXNPOW_VBPD | ADAU1701_AUXNPOW_VRPD; | |
ee441140 | 549 | struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec); |
631ed8a2 LPC |
550 | |
551 | switch (level) { | |
552 | case SND_SOC_BIAS_ON: | |
553 | break; | |
554 | case SND_SOC_BIAS_PREPARE: | |
555 | break; | |
556 | case SND_SOC_BIAS_STANDBY: | |
557 | /* Enable VREF and VREF buffer */ | |
ee441140 DM |
558 | regmap_update_bits(adau1701->regmap, |
559 | ADAU1701_AUXNPOW, mask, 0x00); | |
631ed8a2 LPC |
560 | break; |
561 | case SND_SOC_BIAS_OFF: | |
562 | /* Disable VREF and VREF buffer */ | |
ee441140 DM |
563 | regmap_update_bits(adau1701->regmap, |
564 | ADAU1701_AUXNPOW, mask, mask); | |
631ed8a2 LPC |
565 | break; |
566 | } | |
567 | ||
631ed8a2 LPC |
568 | return 0; |
569 | } | |
570 | ||
571 | static int adau1701_digital_mute(struct snd_soc_dai *dai, int mute) | |
572 | { | |
573 | struct snd_soc_codec *codec = dai->codec; | |
574 | unsigned int mask = ADAU1701_DSPCTRL_DAM; | |
ee441140 | 575 | struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec); |
631ed8a2 LPC |
576 | unsigned int val; |
577 | ||
578 | if (mute) | |
579 | val = 0; | |
580 | else | |
581 | val = mask; | |
582 | ||
ee441140 | 583 | regmap_update_bits(adau1701->regmap, ADAU1701_DSPCTRL, mask, val); |
631ed8a2 LPC |
584 | |
585 | return 0; | |
586 | } | |
587 | ||
588 | static int adau1701_set_sysclk(struct snd_soc_codec *codec, int clk_id, | |
21326db1 | 589 | int source, unsigned int freq, int dir) |
631ed8a2 LPC |
590 | { |
591 | unsigned int val; | |
2352d4bf | 592 | struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec); |
631ed8a2 LPC |
593 | |
594 | switch (clk_id) { | |
595 | case ADAU1701_CLK_SRC_OSC: | |
596 | val = 0x0; | |
597 | break; | |
598 | case ADAU1701_CLK_SRC_MCLK: | |
599 | val = ADAU1701_OSCIPOW_OPD; | |
600 | break; | |
601 | default: | |
602 | return -EINVAL; | |
603 | } | |
604 | ||
ee441140 DM |
605 | regmap_update_bits(adau1701->regmap, ADAU1701_OSCIPOW, |
606 | ADAU1701_OSCIPOW_OPD, val); | |
2352d4bf | 607 | adau1701->sysclk = freq; |
631ed8a2 LPC |
608 | |
609 | return 0; | |
610 | } | |
611 | ||
d48b088e LPC |
612 | static int adau1701_startup(struct snd_pcm_substream *substream, |
613 | struct snd_soc_dai *dai) | |
614 | { | |
615 | struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(dai->codec); | |
616 | ||
617 | return sigmadsp_restrict_params(adau1701->sigmadsp, substream); | |
618 | } | |
619 | ||
631ed8a2 LPC |
620 | #define ADAU1701_RATES (SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | \ |
621 | SNDRV_PCM_RATE_192000) | |
622 | ||
623 | #define ADAU1701_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ | |
624 | SNDRV_PCM_FMTBIT_S24_LE) | |
625 | ||
890754a8 | 626 | static const struct snd_soc_dai_ops adau1701_dai_ops = { |
631ed8a2 LPC |
627 | .set_fmt = adau1701_set_dai_fmt, |
628 | .hw_params = adau1701_hw_params, | |
629 | .digital_mute = adau1701_digital_mute, | |
d48b088e | 630 | .startup = adau1701_startup, |
631ed8a2 LPC |
631 | }; |
632 | ||
633 | static struct snd_soc_dai_driver adau1701_dai = { | |
634 | .name = "adau1701", | |
635 | .playback = { | |
636 | .stream_name = "Playback", | |
637 | .channels_min = 2, | |
638 | .channels_max = 8, | |
639 | .rates = ADAU1701_RATES, | |
640 | .formats = ADAU1701_FORMATS, | |
641 | }, | |
642 | .capture = { | |
643 | .stream_name = "Capture", | |
644 | .channels_min = 2, | |
645 | .channels_max = 8, | |
646 | .rates = ADAU1701_RATES, | |
647 | .formats = ADAU1701_FORMATS, | |
648 | }, | |
649 | .ops = &adau1701_dai_ops, | |
650 | .symmetric_rates = 1, | |
651 | }; | |
652 | ||
04561eac DM |
653 | #ifdef CONFIG_OF |
654 | static const struct of_device_id adau1701_dt_ids[] = { | |
655 | { .compatible = "adi,adau1701", }, | |
656 | { } | |
657 | }; | |
658 | MODULE_DEVICE_TABLE(of, adau1701_dt_ids); | |
659 | #endif | |
660 | ||
631ed8a2 LPC |
661 | static int adau1701_probe(struct snd_soc_codec *codec) |
662 | { | |
97d0a868 DM |
663 | int i, ret; |
664 | unsigned int val; | |
2352d4bf | 665 | struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec); |
631ed8a2 | 666 | |
d48b088e LPC |
667 | ret = sigmadsp_attach(adau1701->sigmadsp, &codec->component); |
668 | if (ret) | |
669 | return ret; | |
670 | ||
2352d4bf DM |
671 | /* |
672 | * Let the pll_clkdiv variable default to something that won't happen | |
673 | * at runtime. That way, we can postpone the firmware download from | |
674 | * adau1701_reset() to a point in time when we know the correct PLL | |
675 | * mode parameters. | |
676 | */ | |
677 | adau1701->pll_clkdiv = ADAU1707_CLKDIV_UNSET; | |
678 | ||
679 | /* initalize with pre-configured pll mode settings */ | |
d48b088e | 680 | ret = adau1701_reset(codec, adau1701->pll_clkdiv, 0); |
2352d4bf | 681 | if (ret < 0) |
f724ba3b | 682 | return ret; |
631ed8a2 | 683 | |
97d0a868 DM |
684 | /* set up pin config */ |
685 | val = 0; | |
686 | for (i = 0; i < 6; i++) | |
687 | val |= adau1701->pin_config[i] << (i * 4); | |
688 | ||
689 | regmap_write(adau1701->regmap, ADAU1701_PINCONF_0, val); | |
690 | ||
691 | val = 0; | |
692 | for (i = 0; i < 6; i++) | |
693 | val |= adau1701->pin_config[i + 6] << (i * 4); | |
694 | ||
695 | regmap_write(adau1701->regmap, ADAU1701_PINCONF_1, val); | |
696 | ||
631ed8a2 LPC |
697 | return 0; |
698 | } | |
699 | ||
700 | static struct snd_soc_codec_driver adau1701_codec_drv = { | |
701 | .probe = adau1701_probe, | |
702 | .set_bias_level = adau1701_set_bias_level, | |
eb3032f8 | 703 | .idle_bias_off = true, |
631ed8a2 | 704 | |
631ed8a2 LPC |
705 | .controls = adau1701_controls, |
706 | .num_controls = ARRAY_SIZE(adau1701_controls), | |
707 | .dapm_widgets = adau1701_dapm_widgets, | |
708 | .num_dapm_widgets = ARRAY_SIZE(adau1701_dapm_widgets), | |
709 | .dapm_routes = adau1701_dapm_routes, | |
710 | .num_dapm_routes = ARRAY_SIZE(adau1701_dapm_routes), | |
711 | ||
631ed8a2 LPC |
712 | .set_sysclk = adau1701_set_sysclk, |
713 | }; | |
714 | ||
45405d58 DM |
715 | static const struct regmap_config adau1701_regmap = { |
716 | .reg_bits = 16, | |
717 | .val_bits = 32, | |
718 | .max_register = ADAU1701_MAX_REGISTER, | |
719 | .cache_type = REGCACHE_RBTREE, | |
720 | .volatile_reg = adau1701_volatile_reg, | |
721 | .reg_write = adau1701_reg_write, | |
722 | .reg_read = adau1701_reg_read, | |
723 | }; | |
724 | ||
7a79e94e BP |
725 | static int adau1701_i2c_probe(struct i2c_client *client, |
726 | const struct i2c_device_id *id) | |
631ed8a2 LPC |
727 | { |
728 | struct adau1701 *adau1701; | |
04561eac DM |
729 | struct device *dev = &client->dev; |
730 | int gpio_nreset = -EINVAL; | |
2352d4bf | 731 | int gpio_pll_mode[2] = { -EINVAL, -EINVAL }; |
631ed8a2 LPC |
732 | int ret; |
733 | ||
04561eac | 734 | adau1701 = devm_kzalloc(dev, sizeof(*adau1701), GFP_KERNEL); |
631ed8a2 LPC |
735 | if (!adau1701) |
736 | return -ENOMEM; | |
737 | ||
a3a1ec66 | 738 | adau1701->client = client; |
45405d58 DM |
739 | adau1701->regmap = devm_regmap_init(dev, NULL, client, |
740 | &adau1701_regmap); | |
741 | if (IS_ERR(adau1701->regmap)) | |
742 | return PTR_ERR(adau1701->regmap); | |
743 | ||
04561eac DM |
744 | if (dev->of_node) { |
745 | gpio_nreset = of_get_named_gpio(dev->of_node, "reset-gpio", 0); | |
746 | if (gpio_nreset < 0 && gpio_nreset != -ENOENT) | |
747 | return gpio_nreset; | |
2352d4bf DM |
748 | |
749 | gpio_pll_mode[0] = of_get_named_gpio(dev->of_node, | |
750 | "adi,pll-mode-gpios", 0); | |
751 | if (gpio_pll_mode[0] < 0 && gpio_pll_mode[0] != -ENOENT) | |
752 | return gpio_pll_mode[0]; | |
753 | ||
754 | gpio_pll_mode[1] = of_get_named_gpio(dev->of_node, | |
755 | "adi,pll-mode-gpios", 1); | |
756 | if (gpio_pll_mode[1] < 0 && gpio_pll_mode[1] != -ENOENT) | |
757 | return gpio_pll_mode[1]; | |
97d0a868 DM |
758 | |
759 | of_property_read_u32(dev->of_node, "adi,pll-clkdiv", | |
760 | &adau1701->pll_clkdiv); | |
761 | ||
762 | of_property_read_u8_array(dev->of_node, "adi,pin-config", | |
763 | adau1701->pin_config, | |
764 | ARRAY_SIZE(adau1701->pin_config)); | |
04561eac DM |
765 | } |
766 | ||
767 | if (gpio_is_valid(gpio_nreset)) { | |
768 | ret = devm_gpio_request_one(dev, gpio_nreset, GPIOF_OUT_INIT_LOW, | |
769 | "ADAU1701 Reset"); | |
770 | if (ret < 0) | |
771 | return ret; | |
04561eac DM |
772 | } |
773 | ||
2352d4bf DM |
774 | if (gpio_is_valid(gpio_pll_mode[0]) && |
775 | gpio_is_valid(gpio_pll_mode[1])) { | |
776 | ret = devm_gpio_request_one(dev, gpio_pll_mode[0], | |
777 | GPIOF_OUT_INIT_LOW, | |
778 | "ADAU1701 PLL mode 0"); | |
779 | if (ret < 0) | |
780 | return ret; | |
781 | ||
782 | ret = devm_gpio_request_one(dev, gpio_pll_mode[1], | |
783 | GPIOF_OUT_INIT_LOW, | |
784 | "ADAU1701 PLL mode 1"); | |
785 | if (ret < 0) | |
786 | return ret; | |
787 | } | |
788 | ||
f724ba3b | 789 | adau1701->gpio_nreset = gpio_nreset; |
2352d4bf DM |
790 | adau1701->gpio_pll_mode[0] = gpio_pll_mode[0]; |
791 | adau1701->gpio_pll_mode[1] = gpio_pll_mode[1]; | |
f724ba3b | 792 | |
631ed8a2 | 793 | i2c_set_clientdata(client, adau1701); |
d48b088e | 794 | |
a3a1ec66 LPC |
795 | adau1701->sigmadsp = devm_sigmadsp_init_i2c(client, |
796 | &adau1701_sigmadsp_ops, ADAU1701_FIRMWARE); | |
d48b088e LPC |
797 | if (IS_ERR(adau1701->sigmadsp)) |
798 | return PTR_ERR(adau1701->sigmadsp); | |
799 | ||
631ed8a2 LPC |
800 | ret = snd_soc_register_codec(&client->dev, &adau1701_codec_drv, |
801 | &adau1701_dai, 1); | |
631ed8a2 LPC |
802 | return ret; |
803 | } | |
804 | ||
7a79e94e | 805 | static int adau1701_i2c_remove(struct i2c_client *client) |
631ed8a2 LPC |
806 | { |
807 | snd_soc_unregister_codec(&client->dev); | |
631ed8a2 LPC |
808 | return 0; |
809 | } | |
810 | ||
811 | static const struct i2c_device_id adau1701_i2c_id[] = { | |
96b9bc61 LPC |
812 | { "adau1401", 0 }, |
813 | { "adau1401a", 0 }, | |
631ed8a2 | 814 | { "adau1701", 0 }, |
96b9bc61 | 815 | { "adau1702", 0 }, |
631ed8a2 LPC |
816 | { } |
817 | }; | |
818 | MODULE_DEVICE_TABLE(i2c, adau1701_i2c_id); | |
819 | ||
820 | static struct i2c_driver adau1701_i2c_driver = { | |
821 | .driver = { | |
822 | .name = "adau1701", | |
823 | .owner = THIS_MODULE, | |
04561eac | 824 | .of_match_table = of_match_ptr(adau1701_dt_ids), |
631ed8a2 LPC |
825 | }, |
826 | .probe = adau1701_i2c_probe, | |
7a79e94e | 827 | .remove = adau1701_i2c_remove, |
631ed8a2 LPC |
828 | .id_table = adau1701_i2c_id, |
829 | }; | |
830 | ||
beb22de0 | 831 | module_i2c_driver(adau1701_i2c_driver); |
631ed8a2 LPC |
832 | |
833 | MODULE_DESCRIPTION("ASoC ADAU1701 SigmaDSP driver"); | |
834 | MODULE_AUTHOR("Cliff Cai <cliff.cai@analog.com>"); | |
835 | MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); | |
836 | MODULE_LICENSE("GPL"); |