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Merge tag 'trace-3.15-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt...
[deliverable/linux.git] / sound / soc / codecs / adau1701.c
CommitLineData
631ed8a2
LPC		 1/*
2 * Driver for ADAU1701 SigmaDSP processor
3 *
4 * Copyright 2011 Analog Devices Inc.
5 * Author: Lars-Peter Clausen <lars@metafoo.de>
6 * based on an inital version by Cliff Cai <cliff.cai@analog.com>
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11#include <linux/module.h>
12#include <linux/init.h>
13#include <linux/i2c.h>
14#include <linux/delay.h>
631ed8a2 15#include <linux/slab.h>
04561eac
DM		 16#include <linux/of.h>
17#include <linux/of_gpio.h>
18#include <linux/of_device.h>
45405d58 19#include <linux/regmap.h>
631ed8a2
LPC		 20#include <sound/core.h>
21#include <sound/pcm.h>
22#include <sound/pcm_params.h>
23#include <sound/soc.h>
24
40216ce7 25#include "sigmadsp.h"
631ed8a2
LPC		 26#include "adau1701.h"
27
45405d58
DM		 28#define ADAU1701_DSPCTRL 0x081c
29#define ADAU1701_SEROCTL 0x081e
30#define ADAU1701_SERICTL 0x081f
631ed8a2 31
97d0a868
DM		 32#define ADAU1701_AUXNPOW 0x0822
33#define ADAU1701_PINCONF_0 0x0820
34#define ADAU1701_PINCONF_1 0x0821
45405d58 35#define ADAU1701_AUXNPOW 0x0822
631ed8a2 36
45405d58
DM		 37#define ADAU1701_OSCIPOW 0x0826
38#define ADAU1701_DACSET 0x0827
631ed8a2 39
45405d58 40#define ADAU1701_MAX_REGISTER 0x0828
631ed8a2
LPC		 41
42#define ADAU1701_DSPCTRL_CR (1 << 2)
43#define ADAU1701_DSPCTRL_DAM (1 << 3)
44#define ADAU1701_DSPCTRL_ADM (1 << 4)
45#define ADAU1701_DSPCTRL_SR_48 0x00
46#define ADAU1701_DSPCTRL_SR_96 0x01
47#define ADAU1701_DSPCTRL_SR_192 0x02
48#define ADAU1701_DSPCTRL_SR_MASK 0x03
49
50#define ADAU1701_SEROCTL_INV_LRCLK 0x2000
51#define ADAU1701_SEROCTL_INV_BCLK 0x1000
52#define ADAU1701_SEROCTL_MASTER 0x0800
53
54#define ADAU1701_SEROCTL_OBF16 0x0000
55#define ADAU1701_SEROCTL_OBF8 0x0200
56#define ADAU1701_SEROCTL_OBF4 0x0400
57#define ADAU1701_SEROCTL_OBF2 0x0600
58#define ADAU1701_SEROCTL_OBF_MASK 0x0600
59
60#define ADAU1701_SEROCTL_OLF1024 0x0000
61#define ADAU1701_SEROCTL_OLF512 0x0080
62#define ADAU1701_SEROCTL_OLF256 0x0100
63#define ADAU1701_SEROCTL_OLF_MASK 0x0180
64
65#define ADAU1701_SEROCTL_MSB_DEALY1 0x0000
66#define ADAU1701_SEROCTL_MSB_DEALY0 0x0004
67#define ADAU1701_SEROCTL_MSB_DEALY8 0x0008
68#define ADAU1701_SEROCTL_MSB_DEALY12 0x000c
69#define ADAU1701_SEROCTL_MSB_DEALY16 0x0010
70#define ADAU1701_SEROCTL_MSB_DEALY_MASK 0x001c
71
72#define ADAU1701_SEROCTL_WORD_LEN_24 0x0000
73#define ADAU1701_SEROCTL_WORD_LEN_20 0x0001
e20970ad 74#define ADAU1701_SEROCTL_WORD_LEN_16 0x0002
631ed8a2
LPC		 75#define ADAU1701_SEROCTL_WORD_LEN_MASK 0x0003
76
77#define ADAU1701_AUXNPOW_VBPD 0x40
78#define ADAU1701_AUXNPOW_VRPD 0x20
79
80#define ADAU1701_SERICTL_I2S 0
81#define ADAU1701_SERICTL_LEFTJ 1
82#define ADAU1701_SERICTL_TDM 2
83#define ADAU1701_SERICTL_RIGHTJ_24 3
84#define ADAU1701_SERICTL_RIGHTJ_20 4
85#define ADAU1701_SERICTL_RIGHTJ_18 5
86#define ADAU1701_SERICTL_RIGHTJ_16 6
87#define ADAU1701_SERICTL_MODE_MASK 7
88#define ADAU1701_SERICTL_INV_BCLK BIT(3)
89#define ADAU1701_SERICTL_INV_LRCLK BIT(4)
90
91#define ADAU1701_OSCIPOW_OPD 0x04
92#define ADAU1701_DACSET_DACINIT 1
93
ba51cbb8 94#define ADAU1707_CLKDIV_UNSET (-1U)
2352d4bf 95
631ed8a2
LPC		 96#define ADAU1701_FIRMWARE "adau1701.bin"
97
98struct adau1701 {
f724ba3b 99 int gpio_nreset;
2352d4bf 100 int gpio_pll_mode[2];
631ed8a2 101 unsigned int dai_fmt;
2352d4bf
DM		 102 unsigned int pll_clkdiv;
103 unsigned int sysclk;
45405d58 104 struct regmap *regmap;
97d0a868 105 u8 pin_config[12];
631ed8a2
LPC		 106};
107
108static const struct snd_kcontrol_new adau1701_controls[] = {
109 SOC_SINGLE("Master Capture Switch", ADAU1701_DSPCTRL, 4, 1, 0),
110};
111
112static const struct snd_soc_dapm_widget adau1701_dapm_widgets[] = {
113 SND_SOC_DAPM_DAC("DAC0", "Playback", ADAU1701_AUXNPOW, 3, 1),
114 SND_SOC_DAPM_DAC("DAC1", "Playback", ADAU1701_AUXNPOW, 2, 1),
115 SND_SOC_DAPM_DAC("DAC2", "Playback", ADAU1701_AUXNPOW, 1, 1),
116 SND_SOC_DAPM_DAC("DAC3", "Playback", ADAU1701_AUXNPOW, 0, 1),
117 SND_SOC_DAPM_ADC("ADC", "Capture", ADAU1701_AUXNPOW, 7, 1),
118
119 SND_SOC_DAPM_OUTPUT("OUT0"),
120 SND_SOC_DAPM_OUTPUT("OUT1"),
121 SND_SOC_DAPM_OUTPUT("OUT2"),
122 SND_SOC_DAPM_OUTPUT("OUT3"),
123 SND_SOC_DAPM_INPUT("IN0"),
124 SND_SOC_DAPM_INPUT("IN1"),
125};
126
127static const struct snd_soc_dapm_route adau1701_dapm_routes[] = {
128 { "OUT0", NULL, "DAC0" },
129 { "OUT1", NULL, "DAC1" },
130 { "OUT2", NULL, "DAC2" },
131 { "OUT3", NULL, "DAC3" },
132
133 { "ADC", NULL, "IN0" },
134 { "ADC", NULL, "IN1" },
135};
136
45405d58 137static unsigned int adau1701_register_size(struct device *dev,
631ed8a2
LPC		 138 unsigned int reg)
139{
140 switch (reg) {
97d0a868
DM		 141 case ADAU1701_PINCONF_0:
142 case ADAU1701_PINCONF_1:
143 return 3;
631ed8a2
LPC		 144 case ADAU1701_DSPCTRL:
145 case ADAU1701_SEROCTL:
146 case ADAU1701_AUXNPOW:
147 case ADAU1701_OSCIPOW:
148 case ADAU1701_DACSET:
149 return 2;
150 case ADAU1701_SERICTL:
151 return 1;
152 }
153
45405d58 154 dev_err(dev, "Unsupported register address: %d\n", reg);
631ed8a2
LPC		 155 return 0;
156}
157
45405d58 158static bool adau1701_volatile_reg(struct device *dev, unsigned int reg)
631ed8a2 159{
45405d58
DM		 160 switch (reg) {
161 case ADAU1701_DACSET:
162 return true;
163 default:
164 return false;
165 }
166}
167
168static int adau1701_reg_write(void *context, unsigned int reg,
169 unsigned int value)
170{
171 struct i2c_client *client = context;
c2097409 172 unsigned int i;
631ed8a2 173 unsigned int size;
97d0a868 174 uint8_t buf[5];
c2097409 175 int ret;
631ed8a2 176
45405d58 177 size = adau1701_register_size(&client->dev, reg);
631ed8a2
LPC		 178 if (size == 0)
179 return -EINVAL;
180
45405d58
DM		 181 buf[0] = reg >> 8;
182 buf[1] = reg & 0xff;
631ed8a2
LPC		 183
184 for (i = size + 1; i >= 2; --i) {
185 buf[i] = value;
186 value >>= 8;
187 }
188
45405d58 189 ret = i2c_master_send(client, buf, size + 2);
631ed8a2
LPC		 190 if (ret == size + 2)
191 return 0;
192 else if (ret < 0)
193 return ret;
194 else
195 return -EIO;
196}
197
45405d58
DM		 198static int adau1701_reg_read(void *context, unsigned int reg,
199 unsigned int *value)
631ed8a2 200{
45405d58
DM		 201 int ret;
202 unsigned int i;
203 unsigned int size;
204 uint8_t send_buf[2], recv_buf[3];
205 struct i2c_client *client = context;
206 struct i2c_msg msgs[2];
207
208 size = adau1701_register_size(&client->dev, reg);
209 if (size == 0)
210 return -EINVAL;
631ed8a2 211
45405d58
DM		 212 send_buf[0] = reg >> 8;
213 send_buf[1] = reg & 0xff;
214
215 msgs[0].addr = client->addr;
216 msgs[0].len = sizeof(send_buf);
217 msgs[0].buf = send_buf;
218 msgs[0].flags = 0;
219
220 msgs[1].addr = client->addr;
221 msgs[1].len = size;
222 msgs[1].buf = recv_buf;
223 msgs[1].flags = I2C_M_RD;
224
225 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
226 if (ret < 0)
631ed8a2 227 return ret;
45405d58
DM		 228 else if (ret != ARRAY_SIZE(msgs))
229 return -EIO;
230
231 *value = 0;
232
233 for (i = 0; i < size; i++)
234 *value |= recv_buf[i] << (i * 8);
631ed8a2 235
45405d58 236 return 0;
631ed8a2
LPC		 237}
238
2352d4bf 239static int adau1701_reset(struct snd_soc_codec *codec, unsigned int clkdiv)
631ed8a2 240{
f724ba3b 241 struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec);
f724ba3b 242 struct i2c_client *client = to_i2c_client(codec->dev);
de9fc724 243 int ret;
f724ba3b 244
2352d4bf
DM		 245 if (clkdiv != ADAU1707_CLKDIV_UNSET &&
246 gpio_is_valid(adau1701->gpio_pll_mode[0]) &&
247 gpio_is_valid(adau1701->gpio_pll_mode[1])) {
248 switch (clkdiv) {
249 case 64:
9190aeb4
MB		 250 gpio_set_value_cansleep(adau1701->gpio_pll_mode[0], 0);
251 gpio_set_value_cansleep(adau1701->gpio_pll_mode[1], 0);
2352d4bf
DM		 252 break;
253 case 256:
9190aeb4
MB		 254 gpio_set_value_cansleep(adau1701->gpio_pll_mode[0], 0);
255 gpio_set_value_cansleep(adau1701->gpio_pll_mode[1], 1);
2352d4bf
DM		 256 break;
257 case 384:
9190aeb4
MB		 258 gpio_set_value_cansleep(adau1701->gpio_pll_mode[0], 1);
259 gpio_set_value_cansleep(adau1701->gpio_pll_mode[1], 0);
2352d4bf
DM		 260 break;
261 case 0: /* fallback */
262 case 512:
9190aeb4
MB		 263 gpio_set_value_cansleep(adau1701->gpio_pll_mode[0], 1);
264 gpio_set_value_cansleep(adau1701->gpio_pll_mode[1], 1);
2352d4bf
DM		 265 break;
266 }
267 }
268
269 adau1701->pll_clkdiv = clkdiv;
270
de9fc724 271 if (gpio_is_valid(adau1701->gpio_nreset)) {
9190aeb4 272 gpio_set_value_cansleep(adau1701->gpio_nreset, 0);
de9fc724
DM		 273 /* minimum reset time is 20ns */
274 udelay(1);
9190aeb4 275 gpio_set_value_cansleep(adau1701->gpio_nreset, 1);
de9fc724
DM		 276 /* power-up time may be as long as 85ms */
277 mdelay(85);
278 }
f724ba3b 279
2352d4bf
DM		 280 /*
281 * Postpone the firmware download to a point in time when we
282 * know the correct PLL setup
283 */
284 if (clkdiv != ADAU1707_CLKDIV_UNSET) {
285 ret = process_sigma_firmware(client, ADAU1701_FIRMWARE);
286 if (ret) {
287 dev_warn(codec->dev, "Failed to load firmware\n");
288 return ret;
289 }
f724ba3b
DM		 290 }
291
45405d58
DM		 292 regmap_write(adau1701->regmap, ADAU1701_DACSET, ADAU1701_DACSET_DACINIT);
293 regmap_write(adau1701->regmap, ADAU1701_DSPCTRL, ADAU1701_DSPCTRL_CR);
294
295 regcache_mark_dirty(adau1701->regmap);
296 regcache_sync(adau1701->regmap);
f724ba3b
DM		 297
298 return 0;
631ed8a2
LPC		 299}
300
301static int adau1701_set_capture_pcm_format(struct snd_soc_codec *codec,
9b58e716 302 struct snd_pcm_hw_params *params)
631ed8a2
LPC		 303{
304 struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec);
305 unsigned int mask = ADAU1701_SEROCTL_WORD_LEN_MASK;
306 unsigned int val;
307
9b58e716
MB		 308 switch (params_width(params)) {
309 case 16:
631ed8a2
LPC		 310 val = ADAU1701_SEROCTL_WORD_LEN_16;
311 break;
9b58e716 312 case 20:
631ed8a2
LPC		 313 val = ADAU1701_SEROCTL_WORD_LEN_20;
314 break;
9b58e716 315 case 24:
631ed8a2
LPC		 316 val = ADAU1701_SEROCTL_WORD_LEN_24;
317 break;
318 default:
319 return -EINVAL;
320 }
321
322 if (adau1701->dai_fmt == SND_SOC_DAIFMT_RIGHT_J) {
9b58e716
MB		 323 switch (params_width(params)) {
324 case 16:
631ed8a2
LPC		 325 val |= ADAU1701_SEROCTL_MSB_DEALY16;
326 break;
9b58e716 327 case 20:
631ed8a2
LPC		 328 val |= ADAU1701_SEROCTL_MSB_DEALY12;
329 break;
9b58e716 330 case 24:
631ed8a2
LPC		 331 val |= ADAU1701_SEROCTL_MSB_DEALY8;
332 break;
333 }
334 mask |= ADAU1701_SEROCTL_MSB_DEALY_MASK;
335 }
336
ee441140 337 regmap_update_bits(adau1701->regmap, ADAU1701_SEROCTL, mask, val);
631ed8a2
LPC		 338
339 return 0;
340}
341
342static int adau1701_set_playback_pcm_format(struct snd_soc_codec *codec,
9b58e716 343 struct snd_pcm_hw_params *params)
631ed8a2
LPC		 344{
345 struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec);
346 unsigned int val;
347
348 if (adau1701->dai_fmt != SND_SOC_DAIFMT_RIGHT_J)
349 return 0;
350
9b58e716
MB		 351 switch (params_width(params)) {
352 case 16:
631ed8a2
LPC		 353 val = ADAU1701_SERICTL_RIGHTJ_16;
354 break;
9b58e716 355 case 20:
631ed8a2
LPC		 356 val = ADAU1701_SERICTL_RIGHTJ_20;
357 break;
9b58e716 358 case 24:
631ed8a2
LPC		 359 val = ADAU1701_SERICTL_RIGHTJ_24;
360 break;
361 default:
362 return -EINVAL;
363 }
364
ee441140 365 regmap_update_bits(adau1701->regmap, ADAU1701_SERICTL,
631ed8a2
LPC		 366 ADAU1701_SERICTL_MODE_MASK, val);
367
368 return 0;
369}
370
371static int adau1701_hw_params(struct snd_pcm_substream *substream,
372 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
373{
e6968a17 374 struct snd_soc_codec *codec = dai->codec;
2352d4bf
DM		 375 struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec);
376 unsigned int clkdiv = adau1701->sysclk / params_rate(params);
631ed8a2 377 unsigned int val;
2352d4bf
DM		 378 int ret;
379
380 /*
381 * If the mclk/lrclk ratio changes, the chip needs updated PLL
382 * mode GPIO settings, and a full reset cycle, including a new
383 * firmware upload.
384 */
385 if (clkdiv != adau1701->pll_clkdiv) {
386 ret = adau1701_reset(codec, clkdiv);
387 if (ret < 0)
388 return ret;
389 }
631ed8a2
LPC		 390
391 switch (params_rate(params)) {
392 case 192000:
393 val = ADAU1701_DSPCTRL_SR_192;
394 break;
395 case 96000:
396 val = ADAU1701_DSPCTRL_SR_96;
397 break;
398 case 48000:
399 val = ADAU1701_DSPCTRL_SR_48;
400 break;
401 default:
402 return -EINVAL;
403 }
404
ee441140 405 regmap_update_bits(adau1701->regmap, ADAU1701_DSPCTRL,
631ed8a2
LPC		 406 ADAU1701_DSPCTRL_SR_MASK, val);
407
631ed8a2 408 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
9b58e716 409 return adau1701_set_playback_pcm_format(codec, params);
631ed8a2 410 else
9b58e716 411 return adau1701_set_capture_pcm_format(codec, params);
631ed8a2
LPC		 412}
413
414static int adau1701_set_dai_fmt(struct snd_soc_dai *codec_dai,
415 unsigned int fmt)
416{
417 struct snd_soc_codec *codec = codec_dai->codec;
418 struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec);
419 unsigned int serictl = 0x00, seroctl = 0x00;
420 bool invert_lrclk;
421
422 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
423 case SND_SOC_DAIFMT_CBM_CFM:
424 /* master, 64-bits per sample, 1 frame per sample */
425 seroctl |= ADAU1701_SEROCTL_MASTER | ADAU1701_SEROCTL_OBF16
426 | ADAU1701_SEROCTL_OLF1024;
427 break;
428 case SND_SOC_DAIFMT_CBS_CFS:
429 break;
430 default:
431 return -EINVAL;
432 }
433
434 /* clock inversion */
435 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
436 case SND_SOC_DAIFMT_NB_NF:
437 invert_lrclk = false;
438 break;
439 case SND_SOC_DAIFMT_NB_IF:
440 invert_lrclk = true;
441 break;
442 case SND_SOC_DAIFMT_IB_NF:
443 invert_lrclk = false;
444 serictl |= ADAU1701_SERICTL_INV_BCLK;
445 seroctl |= ADAU1701_SEROCTL_INV_BCLK;
446 break;
447 case SND_SOC_DAIFMT_IB_IF:
448 invert_lrclk = true;
449 serictl |= ADAU1701_SERICTL_INV_BCLK;
450 seroctl |= ADAU1701_SEROCTL_INV_BCLK;
451 break;
452 default:
453 return -EINVAL;
454 }
455
456 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
457 case SND_SOC_DAIFMT_I2S:
458 break;
459 case SND_SOC_DAIFMT_LEFT_J:
460 serictl |= ADAU1701_SERICTL_LEFTJ;
461 seroctl |= ADAU1701_SEROCTL_MSB_DEALY0;
462 invert_lrclk = !invert_lrclk;
463 break;
464 case SND_SOC_DAIFMT_RIGHT_J:
465 serictl |= ADAU1701_SERICTL_RIGHTJ_24;
466 seroctl |= ADAU1701_SEROCTL_MSB_DEALY8;
467 invert_lrclk = !invert_lrclk;
468 break;
469 default:
470 return -EINVAL;
471 }
472
473 if (invert_lrclk) {
474 seroctl |= ADAU1701_SEROCTL_INV_LRCLK;
475 serictl |= ADAU1701_SERICTL_INV_LRCLK;
476 }
477
478 adau1701->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
479
45405d58
DM		 480 regmap_write(adau1701->regmap, ADAU1701_SERICTL, serictl);
481 regmap_update_bits(adau1701->regmap, ADAU1701_SEROCTL,
631ed8a2
LPC		 482 ~ADAU1701_SEROCTL_WORD_LEN_MASK, seroctl);
483
484 return 0;
485}
486
487static int adau1701_set_bias_level(struct snd_soc_codec *codec,
488 enum snd_soc_bias_level level)
489{
490 unsigned int mask = ADAU1701_AUXNPOW_VBPD | ADAU1701_AUXNPOW_VRPD;
ee441140 491 struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec);
631ed8a2
LPC		 492
493 switch (level) {
494 case SND_SOC_BIAS_ON:
495 break;
496 case SND_SOC_BIAS_PREPARE:
497 break;
498 case SND_SOC_BIAS_STANDBY:
499 /* Enable VREF and VREF buffer */
ee441140
DM		 500 regmap_update_bits(adau1701->regmap,
501 ADAU1701_AUXNPOW, mask, 0x00);
631ed8a2
LPC		 502 break;
503 case SND_SOC_BIAS_OFF:
504 /* Disable VREF and VREF buffer */
ee441140
DM		 505 regmap_update_bits(adau1701->regmap,
506 ADAU1701_AUXNPOW, mask, mask);
631ed8a2
LPC		 507 break;
508 }
509
510 codec->dapm.bias_level = level;
511 return 0;
512}
513
514static int adau1701_digital_mute(struct snd_soc_dai *dai, int mute)
515{
516 struct snd_soc_codec *codec = dai->codec;
517 unsigned int mask = ADAU1701_DSPCTRL_DAM;
ee441140 518 struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec);
631ed8a2
LPC		 519 unsigned int val;
520
521 if (mute)
522 val = 0;
523 else
524 val = mask;
525
ee441140 526 regmap_update_bits(adau1701->regmap, ADAU1701_DSPCTRL, mask, val);
631ed8a2
LPC		 527
528 return 0;
529}
530
531static int adau1701_set_sysclk(struct snd_soc_codec *codec, int clk_id,
21326db1 532 int source, unsigned int freq, int dir)
631ed8a2
LPC		 533{
534 unsigned int val;
2352d4bf 535 struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec);
631ed8a2
LPC		 536
537 switch (clk_id) {
538 case ADAU1701_CLK_SRC_OSC:
539 val = 0x0;
540 break;
541 case ADAU1701_CLK_SRC_MCLK:
542 val = ADAU1701_OSCIPOW_OPD;
543 break;
544 default:
545 return -EINVAL;
546 }
547
ee441140
DM		 548 regmap_update_bits(adau1701->regmap, ADAU1701_OSCIPOW,
549 ADAU1701_OSCIPOW_OPD, val);
2352d4bf 550 adau1701->sysclk = freq;
631ed8a2
LPC		 551
552 return 0;
553}
554
555#define ADAU1701_RATES (SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | \
556 SNDRV_PCM_RATE_192000)
557
558#define ADAU1701_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
559 SNDRV_PCM_FMTBIT_S24_LE)
560
890754a8 561static const struct snd_soc_dai_ops adau1701_dai_ops = {
631ed8a2
LPC		 562 .set_fmt = adau1701_set_dai_fmt,
563 .hw_params = adau1701_hw_params,
564 .digital_mute = adau1701_digital_mute,
565};
566
567static struct snd_soc_dai_driver adau1701_dai = {
568 .name = "adau1701",
569 .playback = {
570 .stream_name = "Playback",
571 .channels_min = 2,
572 .channels_max = 8,
573 .rates = ADAU1701_RATES,
574 .formats = ADAU1701_FORMATS,
575 },
576 .capture = {
577 .stream_name = "Capture",
578 .channels_min = 2,
579 .channels_max = 8,
580 .rates = ADAU1701_RATES,
581 .formats = ADAU1701_FORMATS,
582 },
583 .ops = &adau1701_dai_ops,
584 .symmetric_rates = 1,
585};
586
04561eac
DM		 587#ifdef CONFIG_OF
588static const struct of_device_id adau1701_dt_ids[] = {
589 { .compatible = "adi,adau1701", },
590 { }
591};
592MODULE_DEVICE_TABLE(of, adau1701_dt_ids);
593#endif
594
631ed8a2
LPC		 595static int adau1701_probe(struct snd_soc_codec *codec)
596{
97d0a868
DM		 597 int i, ret;
598 unsigned int val;
2352d4bf 599 struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec);
631ed8a2 600
2352d4bf
DM		 601 /*
602 * Let the pll_clkdiv variable default to something that won't happen
603 * at runtime. That way, we can postpone the firmware download from
604 * adau1701_reset() to a point in time when we know the correct PLL
605 * mode parameters.
606 */
607 adau1701->pll_clkdiv = ADAU1707_CLKDIV_UNSET;
608
609 /* initalize with pre-configured pll mode settings */
610 ret = adau1701_reset(codec, adau1701->pll_clkdiv);
611 if (ret < 0)
f724ba3b 612 return ret;
631ed8a2 613
97d0a868
DM		 614 /* set up pin config */
615 val = 0;
616 for (i = 0; i < 6; i++)
617 val |= adau1701->pin_config[i] << (i * 4);
618
619 regmap_write(adau1701->regmap, ADAU1701_PINCONF_0, val);
620
621 val = 0;
622 for (i = 0; i < 6; i++)
623 val |= adau1701->pin_config[i + 6] << (i * 4);
624
625 regmap_write(adau1701->regmap, ADAU1701_PINCONF_1, val);
626
631ed8a2
LPC		 627 return 0;
628}
629
630static struct snd_soc_codec_driver adau1701_codec_drv = {
631 .probe = adau1701_probe,
632 .set_bias_level = adau1701_set_bias_level,
eb3032f8 633 .idle_bias_off = true,
631ed8a2 634
631ed8a2
LPC		 635 .controls = adau1701_controls,
636 .num_controls = ARRAY_SIZE(adau1701_controls),
637 .dapm_widgets = adau1701_dapm_widgets,
638 .num_dapm_widgets = ARRAY_SIZE(adau1701_dapm_widgets),
639 .dapm_routes = adau1701_dapm_routes,
640 .num_dapm_routes = ARRAY_SIZE(adau1701_dapm_routes),
641
631ed8a2
LPC		 642 .set_sysclk = adau1701_set_sysclk,
643};
644
45405d58
DM		 645static const struct regmap_config adau1701_regmap = {
646 .reg_bits = 16,
647 .val_bits = 32,
648 .max_register = ADAU1701_MAX_REGISTER,
649 .cache_type = REGCACHE_RBTREE,
650 .volatile_reg = adau1701_volatile_reg,
651 .reg_write = adau1701_reg_write,
652 .reg_read = adau1701_reg_read,
653};
654
7a79e94e
BP		 655static int adau1701_i2c_probe(struct i2c_client *client,
656 const struct i2c_device_id *id)
631ed8a2
LPC		 657{
658 struct adau1701 *adau1701;
04561eac
DM		 659 struct device *dev = &client->dev;
660 int gpio_nreset = -EINVAL;
2352d4bf 661 int gpio_pll_mode[2] = { -EINVAL, -EINVAL };
631ed8a2
LPC		 662 int ret;
663
04561eac 664 adau1701 = devm_kzalloc(dev, sizeof(*adau1701), GFP_KERNEL);
631ed8a2
LPC		 665 if (!adau1701)
666 return -ENOMEM;
667
45405d58
DM		 668 adau1701->regmap = devm_regmap_init(dev, NULL, client,
669 &adau1701_regmap);
670 if (IS_ERR(adau1701->regmap))
671 return PTR_ERR(adau1701->regmap);
672
04561eac
DM		 673 if (dev->of_node) {
674 gpio_nreset = of_get_named_gpio(dev->of_node, "reset-gpio", 0);
675 if (gpio_nreset < 0 && gpio_nreset != -ENOENT)
676 return gpio_nreset;
2352d4bf
DM		 677
678 gpio_pll_mode[0] = of_get_named_gpio(dev->of_node,
679 "adi,pll-mode-gpios", 0);
680 if (gpio_pll_mode[0] < 0 && gpio_pll_mode[0] != -ENOENT)
681 return gpio_pll_mode[0];
682
683 gpio_pll_mode[1] = of_get_named_gpio(dev->of_node,
684 "adi,pll-mode-gpios", 1);
685 if (gpio_pll_mode[1] < 0 && gpio_pll_mode[1] != -ENOENT)
686 return gpio_pll_mode[1];
97d0a868
DM		 687
688 of_property_read_u32(dev->of_node, "adi,pll-clkdiv",
689 &adau1701->pll_clkdiv);
690
691 of_property_read_u8_array(dev->of_node, "adi,pin-config",
692 adau1701->pin_config,
693 ARRAY_SIZE(adau1701->pin_config));
04561eac
DM		 694 }
695
696 if (gpio_is_valid(gpio_nreset)) {
697 ret = devm_gpio_request_one(dev, gpio_nreset, GPIOF_OUT_INIT_LOW,
698 "ADAU1701 Reset");
699 if (ret < 0)
700 return ret;
04561eac
DM		 701 }
702
2352d4bf
DM		 703 if (gpio_is_valid(gpio_pll_mode[0]) &&
704 gpio_is_valid(gpio_pll_mode[1])) {
705 ret = devm_gpio_request_one(dev, gpio_pll_mode[0],
706 GPIOF_OUT_INIT_LOW,
707 "ADAU1701 PLL mode 0");
708 if (ret < 0)
709 return ret;
710
711 ret = devm_gpio_request_one(dev, gpio_pll_mode[1],
712 GPIOF_OUT_INIT_LOW,
713 "ADAU1701 PLL mode 1");
714 if (ret < 0)
715 return ret;
716 }
717
f724ba3b 718 adau1701->gpio_nreset = gpio_nreset;
2352d4bf
DM		 719 adau1701->gpio_pll_mode[0] = gpio_pll_mode[0];
720 adau1701->gpio_pll_mode[1] = gpio_pll_mode[1];
f724ba3b 721
631ed8a2
LPC		 722 i2c_set_clientdata(client, adau1701);
723 ret = snd_soc_register_codec(&client->dev, &adau1701_codec_drv,
724 &adau1701_dai, 1);
631ed8a2
LPC		 725 return ret;
726}
727
7a79e94e 728static int adau1701_i2c_remove(struct i2c_client *client)
631ed8a2
LPC		 729{
730 snd_soc_unregister_codec(&client->dev);
631ed8a2
LPC		 731 return 0;
732}
733
734static const struct i2c_device_id adau1701_i2c_id[] = {
96b9bc61
LPC		 735 { "adau1401", 0 },
736 { "adau1401a", 0 },
631ed8a2 737 { "adau1701", 0 },
96b9bc61 738 { "adau1702", 0 },
631ed8a2
LPC		 739 { }
740};
741MODULE_DEVICE_TABLE(i2c, adau1701_i2c_id);
742
743static struct i2c_driver adau1701_i2c_driver = {
744 .driver = {
745 .name = "adau1701",
746 .owner = THIS_MODULE,
04561eac 747 .of_match_table = of_match_ptr(adau1701_dt_ids),
631ed8a2
LPC		 748 },
749 .probe = adau1701_i2c_probe,
7a79e94e 750 .remove = adau1701_i2c_remove,
631ed8a2
LPC		 751 .id_table = adau1701_i2c_id,
752};
753
beb22de0 754module_i2c_driver(adau1701_i2c_driver);
631ed8a2
LPC		 755
756MODULE_DESCRIPTION("ASoC ADAU1701 SigmaDSP driver");
757MODULE_AUTHOR("Cliff Cai <cliff.cai@analog.com>");
758MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
759MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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