Commit | Line | Data |
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4101866c LPC |
1 | /* |
2 | * Common code for ADAU1X61 and ADAU1X81 codecs | |
3 | * | |
4 | * Copyright 2011-2014 Analog Devices Inc. | |
5 | * Author: Lars-Peter Clausen <lars@metafoo.de> | |
6 | * | |
7 | * Licensed under the GPL-2 or later. | |
8 | */ | |
9 | ||
10 | #include <linux/module.h> | |
11 | #include <linux/init.h> | |
5d76de61 | 12 | #include <linux/clk.h> |
4101866c LPC |
13 | #include <linux/delay.h> |
14 | #include <linux/slab.h> | |
15 | #include <sound/core.h> | |
16 | #include <sound/pcm.h> | |
17 | #include <sound/pcm_params.h> | |
18 | #include <sound/soc.h> | |
19 | #include <sound/tlv.h> | |
20 | #include <linux/gcd.h> | |
21 | #include <linux/i2c.h> | |
22 | #include <linux/spi/spi.h> | |
23 | #include <linux/regmap.h> | |
24 | ||
25 | #include "sigmadsp.h" | |
26 | #include "adau17x1.h" | |
0eadaa9c | 27 | #include "adau-utils.h" |
4101866c LPC |
28 | |
29 | static const char * const adau17x1_capture_mixer_boost_text[] = { | |
30 | "Normal operation", "Boost Level 1", "Boost Level 2", "Boost Level 3", | |
31 | }; | |
32 | ||
33 | static SOC_ENUM_SINGLE_DECL(adau17x1_capture_boost_enum, | |
34 | ADAU17X1_REC_POWER_MGMT, 5, adau17x1_capture_mixer_boost_text); | |
35 | ||
36 | static const char * const adau17x1_mic_bias_mode_text[] = { | |
37 | "Normal operation", "High performance", | |
38 | }; | |
39 | ||
40 | static SOC_ENUM_SINGLE_DECL(adau17x1_mic_bias_mode_enum, | |
41 | ADAU17X1_MICBIAS, 3, adau17x1_mic_bias_mode_text); | |
42 | ||
43 | static const DECLARE_TLV_DB_MINMAX(adau17x1_digital_tlv, -9563, 0); | |
44 | ||
45 | static const struct snd_kcontrol_new adau17x1_controls[] = { | |
46 | SOC_DOUBLE_R_TLV("Digital Capture Volume", | |
47 | ADAU17X1_LEFT_INPUT_DIGITAL_VOL, | |
48 | ADAU17X1_RIGHT_INPUT_DIGITAL_VOL, | |
49 | 0, 0xff, 1, adau17x1_digital_tlv), | |
50 | SOC_DOUBLE_R_TLV("Digital Playback Volume", ADAU17X1_DAC_CONTROL1, | |
51 | ADAU17X1_DAC_CONTROL2, 0, 0xff, 1, adau17x1_digital_tlv), | |
52 | ||
53 | SOC_SINGLE("ADC High Pass Filter Switch", ADAU17X1_ADC_CONTROL, | |
54 | 5, 1, 0), | |
55 | SOC_SINGLE("Playback De-emphasis Switch", ADAU17X1_DAC_CONTROL0, | |
56 | 2, 1, 0), | |
57 | ||
58 | SOC_ENUM("Capture Boost", adau17x1_capture_boost_enum), | |
59 | ||
60 | SOC_ENUM("Mic Bias Mode", adau17x1_mic_bias_mode_enum), | |
61 | }; | |
62 | ||
63 | static int adau17x1_pll_event(struct snd_soc_dapm_widget *w, | |
64 | struct snd_kcontrol *kcontrol, int event) | |
65 | { | |
d69db7f7 LPC |
66 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
67 | struct adau *adau = snd_soc_codec_get_drvdata(codec); | |
4101866c LPC |
68 | int ret; |
69 | ||
70 | if (SND_SOC_DAPM_EVENT_ON(event)) { | |
71 | adau->pll_regs[5] = 1; | |
72 | } else { | |
73 | adau->pll_regs[5] = 0; | |
74 | /* Bypass the PLL when disabled, otherwise registers will become | |
75 | * inaccessible. */ | |
76 | regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL, | |
77 | ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL, 0); | |
78 | } | |
79 | ||
80 | /* The PLL register is 6 bytes long and can only be written at once. */ | |
81 | ret = regmap_raw_write(adau->regmap, ADAU17X1_PLL_CONTROL, | |
82 | adau->pll_regs, ARRAY_SIZE(adau->pll_regs)); | |
83 | ||
84 | if (SND_SOC_DAPM_EVENT_ON(event)) { | |
85 | mdelay(5); | |
86 | regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL, | |
87 | ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL, | |
88 | ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL); | |
89 | } | |
90 | ||
91 | return 0; | |
92 | } | |
93 | ||
94 | static const char * const adau17x1_mono_stereo_text[] = { | |
95 | "Stereo", | |
96 | "Mono Left Channel (L+R)", | |
97 | "Mono Right Channel (L+R)", | |
98 | "Mono (L+R)", | |
99 | }; | |
100 | ||
101 | static SOC_ENUM_SINGLE_DECL(adau17x1_dac_mode_enum, | |
102 | ADAU17X1_DAC_CONTROL0, 6, adau17x1_mono_stereo_text); | |
103 | ||
104 | static const struct snd_kcontrol_new adau17x1_dac_mode_mux = | |
105 | SOC_DAPM_ENUM("DAC Mono-Stereo-Mode", adau17x1_dac_mode_enum); | |
106 | ||
107 | static const struct snd_soc_dapm_widget adau17x1_dapm_widgets[] = { | |
108 | SND_SOC_DAPM_SUPPLY_S("PLL", 3, SND_SOC_NOPM, 0, 0, adau17x1_pll_event, | |
109 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), | |
110 | ||
111 | SND_SOC_DAPM_SUPPLY("AIFCLK", SND_SOC_NOPM, 0, 0, NULL, 0), | |
112 | ||
113 | SND_SOC_DAPM_SUPPLY("MICBIAS", ADAU17X1_MICBIAS, 0, 0, NULL, 0), | |
114 | ||
115 | SND_SOC_DAPM_SUPPLY("Left Playback Enable", ADAU17X1_PLAY_POWER_MGMT, | |
116 | 0, 0, NULL, 0), | |
117 | SND_SOC_DAPM_SUPPLY("Right Playback Enable", ADAU17X1_PLAY_POWER_MGMT, | |
118 | 1, 0, NULL, 0), | |
119 | ||
120 | SND_SOC_DAPM_MUX("Left DAC Mode Mux", SND_SOC_NOPM, 0, 0, | |
121 | &adau17x1_dac_mode_mux), | |
122 | SND_SOC_DAPM_MUX("Right DAC Mode Mux", SND_SOC_NOPM, 0, 0, | |
123 | &adau17x1_dac_mode_mux), | |
124 | ||
125 | SND_SOC_DAPM_ADC("Left Decimator", NULL, ADAU17X1_ADC_CONTROL, 0, 0), | |
126 | SND_SOC_DAPM_ADC("Right Decimator", NULL, ADAU17X1_ADC_CONTROL, 1, 0), | |
127 | SND_SOC_DAPM_DAC("Left DAC", NULL, ADAU17X1_DAC_CONTROL0, 0, 0), | |
128 | SND_SOC_DAPM_DAC("Right DAC", NULL, ADAU17X1_DAC_CONTROL0, 1, 0), | |
129 | }; | |
130 | ||
131 | static const struct snd_soc_dapm_route adau17x1_dapm_routes[] = { | |
132 | { "Left Decimator", NULL, "SYSCLK" }, | |
133 | { "Right Decimator", NULL, "SYSCLK" }, | |
134 | { "Left DAC", NULL, "SYSCLK" }, | |
135 | { "Right DAC", NULL, "SYSCLK" }, | |
136 | { "Capture", NULL, "SYSCLK" }, | |
137 | { "Playback", NULL, "SYSCLK" }, | |
138 | ||
139 | { "Left DAC", NULL, "Left DAC Mode Mux" }, | |
140 | { "Right DAC", NULL, "Right DAC Mode Mux" }, | |
141 | ||
142 | { "Capture", NULL, "AIFCLK" }, | |
143 | { "Playback", NULL, "AIFCLK" }, | |
144 | }; | |
145 | ||
146 | static const struct snd_soc_dapm_route adau17x1_dapm_pll_route = { | |
147 | "SYSCLK", NULL, "PLL", | |
148 | }; | |
149 | ||
150 | /* | |
151 | * The MUX register for the Capture and Playback MUXs selects either DSP as | |
152 | * source/destination or one of the TDM slots. The TDM slot is selected via | |
153 | * snd_soc_dai_set_tdm_slot(), so we only expose whether to go to the DSP or | |
154 | * directly to the DAI interface with this control. | |
155 | */ | |
156 | static int adau17x1_dsp_mux_enum_put(struct snd_kcontrol *kcontrol, | |
157 | struct snd_ctl_elem_value *ucontrol) | |
158 | { | |
159 | struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol); | |
33c7b140 | 160 | struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); |
4101866c LPC |
161 | struct adau *adau = snd_soc_codec_get_drvdata(codec); |
162 | struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; | |
163 | struct snd_soc_dapm_update update; | |
164 | unsigned int stream = e->shift_l; | |
165 | unsigned int val, change; | |
166 | int reg; | |
167 | ||
168 | if (ucontrol->value.enumerated.item[0] >= e->items) | |
169 | return -EINVAL; | |
170 | ||
171 | switch (ucontrol->value.enumerated.item[0]) { | |
172 | case 0: | |
173 | val = 0; | |
174 | adau->dsp_bypass[stream] = false; | |
175 | break; | |
176 | default: | |
177 | val = (adau->tdm_slot[stream] * 2) + 1; | |
178 | adau->dsp_bypass[stream] = true; | |
179 | break; | |
180 | } | |
181 | ||
182 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) | |
183 | reg = ADAU17X1_SERIAL_INPUT_ROUTE; | |
184 | else | |
185 | reg = ADAU17X1_SERIAL_OUTPUT_ROUTE; | |
186 | ||
187 | change = snd_soc_test_bits(codec, reg, 0xff, val); | |
188 | if (change) { | |
189 | update.kcontrol = kcontrol; | |
190 | update.mask = 0xff; | |
191 | update.reg = reg; | |
192 | update.val = val; | |
193 | ||
33c7b140 | 194 | snd_soc_dapm_mux_update_power(dapm, kcontrol, |
4101866c LPC |
195 | ucontrol->value.enumerated.item[0], e, &update); |
196 | } | |
197 | ||
198 | return change; | |
199 | } | |
200 | ||
201 | static int adau17x1_dsp_mux_enum_get(struct snd_kcontrol *kcontrol, | |
202 | struct snd_ctl_elem_value *ucontrol) | |
203 | { | |
204 | struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol); | |
205 | struct adau *adau = snd_soc_codec_get_drvdata(codec); | |
206 | struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; | |
207 | unsigned int stream = e->shift_l; | |
208 | unsigned int reg, val; | |
209 | int ret; | |
210 | ||
211 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) | |
212 | reg = ADAU17X1_SERIAL_INPUT_ROUTE; | |
213 | else | |
214 | reg = ADAU17X1_SERIAL_OUTPUT_ROUTE; | |
215 | ||
216 | ret = regmap_read(adau->regmap, reg, &val); | |
217 | if (ret) | |
218 | return ret; | |
219 | ||
220 | if (val != 0) | |
221 | val = 1; | |
222 | ucontrol->value.enumerated.item[0] = val; | |
223 | ||
224 | return 0; | |
225 | } | |
226 | ||
227 | #define DECLARE_ADAU17X1_DSP_MUX_CTRL(_name, _label, _stream, _text) \ | |
228 | const struct snd_kcontrol_new _name = \ | |
229 | SOC_DAPM_ENUM_EXT(_label, (const struct soc_enum)\ | |
230 | SOC_ENUM_SINGLE(SND_SOC_NOPM, _stream, \ | |
231 | ARRAY_SIZE(_text), _text), \ | |
232 | adau17x1_dsp_mux_enum_get, adau17x1_dsp_mux_enum_put) | |
233 | ||
234 | static const char * const adau17x1_dac_mux_text[] = { | |
235 | "DSP", | |
236 | "AIFIN", | |
237 | }; | |
238 | ||
239 | static const char * const adau17x1_capture_mux_text[] = { | |
240 | "DSP", | |
241 | "Decimator", | |
242 | }; | |
243 | ||
244 | static DECLARE_ADAU17X1_DSP_MUX_CTRL(adau17x1_dac_mux, "DAC Playback Mux", | |
245 | SNDRV_PCM_STREAM_PLAYBACK, adau17x1_dac_mux_text); | |
246 | ||
247 | static DECLARE_ADAU17X1_DSP_MUX_CTRL(adau17x1_capture_mux, "Capture Mux", | |
248 | SNDRV_PCM_STREAM_CAPTURE, adau17x1_capture_mux_text); | |
249 | ||
250 | static const struct snd_soc_dapm_widget adau17x1_dsp_dapm_widgets[] = { | |
251 | SND_SOC_DAPM_PGA("DSP", ADAU17X1_DSP_RUN, 0, 0, NULL, 0), | |
252 | SND_SOC_DAPM_SIGGEN("DSP Siggen"), | |
253 | ||
254 | SND_SOC_DAPM_MUX("DAC Playback Mux", SND_SOC_NOPM, 0, 0, | |
255 | &adau17x1_dac_mux), | |
256 | SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, | |
257 | &adau17x1_capture_mux), | |
258 | }; | |
259 | ||
260 | static const struct snd_soc_dapm_route adau17x1_dsp_dapm_routes[] = { | |
261 | { "DAC Playback Mux", "DSP", "DSP" }, | |
262 | { "DAC Playback Mux", "AIFIN", "Playback" }, | |
263 | ||
264 | { "Left DAC Mode Mux", "Stereo", "DAC Playback Mux" }, | |
265 | { "Left DAC Mode Mux", "Mono (L+R)", "DAC Playback Mux" }, | |
266 | { "Left DAC Mode Mux", "Mono Left Channel (L+R)", "DAC Playback Mux" }, | |
267 | { "Right DAC Mode Mux", "Stereo", "DAC Playback Mux" }, | |
268 | { "Right DAC Mode Mux", "Mono (L+R)", "DAC Playback Mux" }, | |
269 | { "Right DAC Mode Mux", "Mono Right Channel (L+R)", "DAC Playback Mux" }, | |
270 | ||
271 | { "Capture Mux", "DSP", "DSP" }, | |
272 | { "Capture Mux", "Decimator", "Left Decimator" }, | |
273 | { "Capture Mux", "Decimator", "Right Decimator" }, | |
274 | ||
275 | { "Capture", NULL, "Capture Mux" }, | |
276 | ||
277 | { "DSP", NULL, "DSP Siggen" }, | |
278 | ||
279 | { "DSP", NULL, "Left Decimator" }, | |
280 | { "DSP", NULL, "Right Decimator" }, | |
281 | }; | |
282 | ||
283 | static const struct snd_soc_dapm_route adau17x1_no_dsp_dapm_routes[] = { | |
284 | { "Left DAC Mode Mux", "Stereo", "Playback" }, | |
285 | { "Left DAC Mode Mux", "Mono (L+R)", "Playback" }, | |
286 | { "Left DAC Mode Mux", "Mono Left Channel (L+R)", "Playback" }, | |
287 | { "Right DAC Mode Mux", "Stereo", "Playback" }, | |
288 | { "Right DAC Mode Mux", "Mono (L+R)", "Playback" }, | |
289 | { "Right DAC Mode Mux", "Mono Right Channel (L+R)", "Playback" }, | |
290 | { "Capture", NULL, "Left Decimator" }, | |
291 | { "Capture", NULL, "Right Decimator" }, | |
292 | }; | |
293 | ||
294 | bool adau17x1_has_dsp(struct adau *adau) | |
295 | { | |
296 | switch (adau->type) { | |
297 | case ADAU1761: | |
298 | case ADAU1381: | |
299 | case ADAU1781: | |
300 | return true; | |
301 | default: | |
302 | return false; | |
303 | } | |
304 | } | |
305 | EXPORT_SYMBOL_GPL(adau17x1_has_dsp); | |
306 | ||
5d76de61 LPC |
307 | static int adau17x1_set_dai_pll(struct snd_soc_dai *dai, int pll_id, |
308 | int source, unsigned int freq_in, unsigned int freq_out) | |
309 | { | |
310 | struct snd_soc_codec *codec = dai->codec; | |
311 | struct adau *adau = snd_soc_codec_get_drvdata(codec); | |
312 | int ret; | |
313 | ||
314 | if (freq_in < 8000000 || freq_in > 27000000) | |
315 | return -EINVAL; | |
316 | ||
317 | ret = adau_calc_pll_cfg(freq_in, freq_out, adau->pll_regs); | |
318 | if (ret < 0) | |
319 | return ret; | |
320 | ||
321 | /* The PLL register is 6 bytes long and can only be written at once. */ | |
322 | ret = regmap_raw_write(adau->regmap, ADAU17X1_PLL_CONTROL, | |
323 | adau->pll_regs, ARRAY_SIZE(adau->pll_regs)); | |
324 | if (ret) | |
325 | return ret; | |
326 | ||
327 | adau->pll_freq = freq_out; | |
328 | ||
329 | return 0; | |
330 | } | |
331 | ||
332 | static int adau17x1_set_dai_sysclk(struct snd_soc_dai *dai, | |
333 | int clk_id, unsigned int freq, int dir) | |
334 | { | |
335 | struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(dai->codec); | |
336 | struct adau *adau = snd_soc_codec_get_drvdata(dai->codec); | |
337 | bool is_pll; | |
338 | bool was_pll; | |
339 | ||
340 | switch (clk_id) { | |
341 | case ADAU17X1_CLK_SRC_MCLK: | |
342 | is_pll = false; | |
343 | break; | |
344 | case ADAU17X1_CLK_SRC_PLL_AUTO: | |
345 | if (!adau->mclk) | |
346 | return -EINVAL; | |
347 | /* Fall-through */ | |
348 | case ADAU17X1_CLK_SRC_PLL: | |
349 | is_pll = true; | |
350 | break; | |
351 | default: | |
352 | return -EINVAL; | |
353 | } | |
354 | ||
355 | switch (adau->clk_src) { | |
356 | case ADAU17X1_CLK_SRC_MCLK: | |
357 | was_pll = false; | |
358 | break; | |
359 | case ADAU17X1_CLK_SRC_PLL: | |
360 | case ADAU17X1_CLK_SRC_PLL_AUTO: | |
361 | was_pll = true; | |
362 | break; | |
363 | default: | |
364 | return -EINVAL; | |
365 | } | |
366 | ||
367 | adau->sysclk = freq; | |
368 | ||
369 | if (is_pll != was_pll) { | |
370 | if (is_pll) { | |
371 | snd_soc_dapm_add_routes(dapm, | |
372 | &adau17x1_dapm_pll_route, 1); | |
373 | } else { | |
374 | snd_soc_dapm_del_routes(dapm, | |
375 | &adau17x1_dapm_pll_route, 1); | |
376 | } | |
377 | } | |
378 | ||
379 | adau->clk_src = clk_id; | |
380 | ||
381 | return 0; | |
382 | } | |
383 | ||
384 | static int adau17x1_auto_pll(struct snd_soc_dai *dai, | |
385 | struct snd_pcm_hw_params *params) | |
386 | { | |
387 | struct adau *adau = snd_soc_dai_get_drvdata(dai); | |
388 | unsigned int pll_rate; | |
389 | ||
390 | switch (params_rate(params)) { | |
391 | case 48000: | |
392 | case 8000: | |
393 | case 12000: | |
394 | case 16000: | |
395 | case 24000: | |
396 | case 32000: | |
397 | case 96000: | |
398 | pll_rate = 48000 * 1024; | |
399 | break; | |
400 | case 44100: | |
401 | case 7350: | |
402 | case 11025: | |
403 | case 14700: | |
404 | case 22050: | |
405 | case 29400: | |
406 | case 88200: | |
407 | pll_rate = 44100 * 1024; | |
408 | break; | |
409 | default: | |
410 | return -EINVAL; | |
411 | } | |
412 | ||
413 | return adau17x1_set_dai_pll(dai, ADAU17X1_PLL, ADAU17X1_PLL_SRC_MCLK, | |
414 | clk_get_rate(adau->mclk), pll_rate); | |
415 | } | |
416 | ||
4101866c LPC |
417 | static int adau17x1_hw_params(struct snd_pcm_substream *substream, |
418 | struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) | |
419 | { | |
420 | struct snd_soc_codec *codec = dai->codec; | |
421 | struct adau *adau = snd_soc_codec_get_drvdata(codec); | |
422 | unsigned int val, div, dsp_div; | |
423 | unsigned int freq; | |
d48b088e | 424 | int ret; |
4101866c | 425 | |
5d76de61 LPC |
426 | switch (adau->clk_src) { |
427 | case ADAU17X1_CLK_SRC_PLL_AUTO: | |
428 | ret = adau17x1_auto_pll(dai, params); | |
429 | if (ret) | |
430 | return ret; | |
431 | /* Fall-through */ | |
432 | case ADAU17X1_CLK_SRC_PLL: | |
4101866c | 433 | freq = adau->pll_freq; |
5d76de61 LPC |
434 | break; |
435 | default: | |
4101866c | 436 | freq = adau->sysclk; |
5d76de61 LPC |
437 | break; |
438 | } | |
4101866c LPC |
439 | |
440 | if (freq % params_rate(params) != 0) | |
441 | return -EINVAL; | |
442 | ||
443 | switch (freq / params_rate(params)) { | |
444 | case 1024: /* fs */ | |
445 | div = 0; | |
446 | dsp_div = 1; | |
447 | break; | |
448 | case 6144: /* fs / 6 */ | |
449 | div = 1; | |
450 | dsp_div = 6; | |
451 | break; | |
452 | case 4096: /* fs / 4 */ | |
453 | div = 2; | |
454 | dsp_div = 5; | |
455 | break; | |
456 | case 3072: /* fs / 3 */ | |
457 | div = 3; | |
458 | dsp_div = 4; | |
459 | break; | |
460 | case 2048: /* fs / 2 */ | |
461 | div = 4; | |
462 | dsp_div = 3; | |
463 | break; | |
464 | case 1536: /* fs / 1.5 */ | |
465 | div = 5; | |
466 | dsp_div = 2; | |
467 | break; | |
468 | case 512: /* fs / 0.5 */ | |
469 | div = 6; | |
470 | dsp_div = 0; | |
471 | break; | |
472 | default: | |
473 | return -EINVAL; | |
474 | } | |
475 | ||
476 | regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0, | |
477 | ADAU17X1_CONVERTER0_CONVSR_MASK, div); | |
478 | if (adau17x1_has_dsp(adau)) { | |
479 | regmap_write(adau->regmap, ADAU17X1_SERIAL_SAMPLING_RATE, div); | |
480 | regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, dsp_div); | |
481 | } | |
482 | ||
d48b088e LPC |
483 | if (adau->sigmadsp) { |
484 | ret = adau17x1_setup_firmware(adau, params_rate(params)); | |
485 | if (ret < 0) | |
486 | return ret; | |
487 | } | |
488 | ||
4101866c LPC |
489 | if (adau->dai_fmt != SND_SOC_DAIFMT_RIGHT_J) |
490 | return 0; | |
491 | ||
d2a9b1c1 MB |
492 | switch (params_width(params)) { |
493 | case 16: | |
4101866c LPC |
494 | val = ADAU17X1_SERIAL_PORT1_DELAY16; |
495 | break; | |
d2a9b1c1 | 496 | case 24: |
4101866c LPC |
497 | val = ADAU17X1_SERIAL_PORT1_DELAY8; |
498 | break; | |
d2a9b1c1 | 499 | case 32: |
4101866c LPC |
500 | val = ADAU17X1_SERIAL_PORT1_DELAY0; |
501 | break; | |
502 | default: | |
503 | return -EINVAL; | |
504 | } | |
505 | ||
506 | return regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT1, | |
507 | ADAU17X1_SERIAL_PORT1_DELAY_MASK, val); | |
508 | } | |
509 | ||
4101866c LPC |
510 | static int adau17x1_set_dai_fmt(struct snd_soc_dai *dai, |
511 | unsigned int fmt) | |
512 | { | |
513 | struct adau *adau = snd_soc_codec_get_drvdata(dai->codec); | |
514 | unsigned int ctrl0, ctrl1; | |
515 | int lrclk_pol; | |
516 | ||
517 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
518 | case SND_SOC_DAIFMT_CBM_CFM: | |
519 | ctrl0 = ADAU17X1_SERIAL_PORT0_MASTER; | |
520 | adau->master = true; | |
521 | break; | |
522 | case SND_SOC_DAIFMT_CBS_CFS: | |
523 | ctrl0 = 0; | |
524 | adau->master = false; | |
525 | break; | |
526 | default: | |
527 | return -EINVAL; | |
528 | } | |
529 | ||
530 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
531 | case SND_SOC_DAIFMT_I2S: | |
532 | lrclk_pol = 0; | |
533 | ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY1; | |
534 | break; | |
535 | case SND_SOC_DAIFMT_LEFT_J: | |
536 | case SND_SOC_DAIFMT_RIGHT_J: | |
537 | lrclk_pol = 1; | |
538 | ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY0; | |
539 | break; | |
540 | case SND_SOC_DAIFMT_DSP_A: | |
541 | lrclk_pol = 1; | |
542 | ctrl0 |= ADAU17X1_SERIAL_PORT0_PULSE_MODE; | |
543 | ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY1; | |
544 | break; | |
545 | case SND_SOC_DAIFMT_DSP_B: | |
546 | lrclk_pol = 1; | |
547 | ctrl0 |= ADAU17X1_SERIAL_PORT0_PULSE_MODE; | |
548 | ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY0; | |
549 | break; | |
550 | default: | |
551 | return -EINVAL; | |
552 | } | |
553 | ||
554 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
555 | case SND_SOC_DAIFMT_NB_NF: | |
556 | break; | |
557 | case SND_SOC_DAIFMT_IB_NF: | |
558 | ctrl0 |= ADAU17X1_SERIAL_PORT0_BCLK_POL; | |
559 | break; | |
560 | case SND_SOC_DAIFMT_NB_IF: | |
561 | lrclk_pol = !lrclk_pol; | |
562 | break; | |
563 | case SND_SOC_DAIFMT_IB_IF: | |
564 | ctrl0 |= ADAU17X1_SERIAL_PORT0_BCLK_POL; | |
565 | lrclk_pol = !lrclk_pol; | |
566 | break; | |
567 | default: | |
568 | return -EINVAL; | |
569 | } | |
570 | ||
571 | if (lrclk_pol) | |
572 | ctrl0 |= ADAU17X1_SERIAL_PORT0_LRCLK_POL; | |
573 | ||
574 | regmap_write(adau->regmap, ADAU17X1_SERIAL_PORT0, ctrl0); | |
575 | regmap_write(adau->regmap, ADAU17X1_SERIAL_PORT1, ctrl1); | |
576 | ||
577 | adau->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; | |
578 | ||
579 | return 0; | |
580 | } | |
581 | ||
582 | static int adau17x1_set_dai_tdm_slot(struct snd_soc_dai *dai, | |
583 | unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) | |
584 | { | |
585 | struct adau *adau = snd_soc_codec_get_drvdata(dai->codec); | |
586 | unsigned int ser_ctrl0, ser_ctrl1; | |
587 | unsigned int conv_ctrl0, conv_ctrl1; | |
588 | ||
589 | /* I2S mode */ | |
590 | if (slots == 0) { | |
591 | slots = 2; | |
592 | rx_mask = 3; | |
593 | tx_mask = 3; | |
594 | slot_width = 32; | |
595 | } | |
596 | ||
597 | switch (slots) { | |
598 | case 2: | |
599 | ser_ctrl0 = ADAU17X1_SERIAL_PORT0_STEREO; | |
600 | break; | |
601 | case 4: | |
602 | ser_ctrl0 = ADAU17X1_SERIAL_PORT0_TDM4; | |
603 | break; | |
604 | case 8: | |
605 | if (adau->type == ADAU1361) | |
606 | return -EINVAL; | |
607 | ||
608 | ser_ctrl0 = ADAU17X1_SERIAL_PORT0_TDM8; | |
609 | break; | |
610 | default: | |
611 | return -EINVAL; | |
612 | } | |
613 | ||
614 | switch (slot_width * slots) { | |
615 | case 32: | |
616 | if (adau->type == ADAU1761) | |
617 | return -EINVAL; | |
618 | ||
619 | ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK32; | |
620 | break; | |
621 | case 64: | |
622 | ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK64; | |
623 | break; | |
624 | case 48: | |
625 | ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK48; | |
626 | break; | |
627 | case 128: | |
628 | ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK128; | |
629 | break; | |
630 | case 256: | |
631 | if (adau->type == ADAU1361) | |
632 | return -EINVAL; | |
633 | ||
634 | ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK256; | |
635 | break; | |
636 | default: | |
637 | return -EINVAL; | |
638 | } | |
639 | ||
640 | switch (rx_mask) { | |
641 | case 0x03: | |
642 | conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(1); | |
643 | adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 0; | |
644 | break; | |
645 | case 0x0c: | |
646 | conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(2); | |
647 | adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 1; | |
648 | break; | |
649 | case 0x30: | |
650 | conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(3); | |
651 | adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 2; | |
652 | break; | |
653 | case 0xc0: | |
654 | conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(4); | |
655 | adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 3; | |
656 | break; | |
657 | default: | |
658 | return -EINVAL; | |
659 | } | |
660 | ||
661 | switch (tx_mask) { | |
662 | case 0x03: | |
663 | conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(1); | |
664 | adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 0; | |
665 | break; | |
666 | case 0x0c: | |
667 | conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(2); | |
668 | adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 1; | |
669 | break; | |
670 | case 0x30: | |
671 | conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(3); | |
672 | adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 2; | |
673 | break; | |
674 | case 0xc0: | |
675 | conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(4); | |
676 | adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 3; | |
677 | break; | |
678 | default: | |
679 | return -EINVAL; | |
680 | } | |
681 | ||
682 | regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0, | |
683 | ADAU17X1_CONVERTER0_DAC_PAIR_MASK, conv_ctrl0); | |
684 | regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER1, | |
685 | ADAU17X1_CONVERTER1_ADC_PAIR_MASK, conv_ctrl1); | |
686 | regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT0, | |
687 | ADAU17X1_SERIAL_PORT0_TDM_MASK, ser_ctrl0); | |
688 | regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT1, | |
689 | ADAU17X1_SERIAL_PORT1_BCLK_MASK, ser_ctrl1); | |
690 | ||
691 | if (!adau17x1_has_dsp(adau)) | |
692 | return 0; | |
693 | ||
694 | if (adau->dsp_bypass[SNDRV_PCM_STREAM_PLAYBACK]) { | |
695 | regmap_write(adau->regmap, ADAU17X1_SERIAL_INPUT_ROUTE, | |
696 | (adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] * 2) + 1); | |
697 | } | |
698 | ||
699 | if (adau->dsp_bypass[SNDRV_PCM_STREAM_CAPTURE]) { | |
700 | regmap_write(adau->regmap, ADAU17X1_SERIAL_OUTPUT_ROUTE, | |
701 | (adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] * 2) + 1); | |
702 | } | |
703 | ||
704 | return 0; | |
705 | } | |
706 | ||
d48b088e LPC |
707 | static int adau17x1_startup(struct snd_pcm_substream *substream, |
708 | struct snd_soc_dai *dai) | |
709 | { | |
710 | struct adau *adau = snd_soc_codec_get_drvdata(dai->codec); | |
711 | ||
712 | if (adau->sigmadsp) | |
713 | return sigmadsp_restrict_params(adau->sigmadsp, substream); | |
714 | ||
715 | return 0; | |
716 | } | |
717 | ||
4101866c LPC |
718 | const struct snd_soc_dai_ops adau17x1_dai_ops = { |
719 | .hw_params = adau17x1_hw_params, | |
720 | .set_sysclk = adau17x1_set_dai_sysclk, | |
721 | .set_fmt = adau17x1_set_dai_fmt, | |
722 | .set_pll = adau17x1_set_dai_pll, | |
723 | .set_tdm_slot = adau17x1_set_dai_tdm_slot, | |
d48b088e | 724 | .startup = adau17x1_startup, |
4101866c LPC |
725 | }; |
726 | EXPORT_SYMBOL_GPL(adau17x1_dai_ops); | |
727 | ||
728 | int adau17x1_set_micbias_voltage(struct snd_soc_codec *codec, | |
729 | enum adau17x1_micbias_voltage micbias) | |
730 | { | |
731 | struct adau *adau = snd_soc_codec_get_drvdata(codec); | |
732 | ||
733 | switch (micbias) { | |
734 | case ADAU17X1_MICBIAS_0_90_AVDD: | |
735 | case ADAU17X1_MICBIAS_0_65_AVDD: | |
736 | break; | |
737 | default: | |
738 | return -EINVAL; | |
739 | } | |
740 | ||
741 | return regmap_write(adau->regmap, ADAU17X1_MICBIAS, micbias << 2); | |
742 | } | |
743 | EXPORT_SYMBOL_GPL(adau17x1_set_micbias_voltage); | |
744 | ||
dee9cec4 LPC |
745 | bool adau17x1_precious_register(struct device *dev, unsigned int reg) |
746 | { | |
747 | /* SigmaDSP parameter memory */ | |
748 | if (reg < 0x400) | |
749 | return true; | |
750 | ||
751 | return false; | |
752 | } | |
753 | EXPORT_SYMBOL_GPL(adau17x1_precious_register); | |
754 | ||
4101866c LPC |
755 | bool adau17x1_readable_register(struct device *dev, unsigned int reg) |
756 | { | |
dee9cec4 LPC |
757 | /* SigmaDSP parameter memory */ |
758 | if (reg < 0x400) | |
759 | return true; | |
760 | ||
4101866c LPC |
761 | switch (reg) { |
762 | case ADAU17X1_CLOCK_CONTROL: | |
763 | case ADAU17X1_PLL_CONTROL: | |
764 | case ADAU17X1_REC_POWER_MGMT: | |
765 | case ADAU17X1_MICBIAS: | |
766 | case ADAU17X1_SERIAL_PORT0: | |
767 | case ADAU17X1_SERIAL_PORT1: | |
768 | case ADAU17X1_CONVERTER0: | |
769 | case ADAU17X1_CONVERTER1: | |
770 | case ADAU17X1_LEFT_INPUT_DIGITAL_VOL: | |
771 | case ADAU17X1_RIGHT_INPUT_DIGITAL_VOL: | |
772 | case ADAU17X1_ADC_CONTROL: | |
773 | case ADAU17X1_PLAY_POWER_MGMT: | |
774 | case ADAU17X1_DAC_CONTROL0: | |
775 | case ADAU17X1_DAC_CONTROL1: | |
776 | case ADAU17X1_DAC_CONTROL2: | |
777 | case ADAU17X1_SERIAL_PORT_PAD: | |
778 | case ADAU17X1_CONTROL_PORT_PAD0: | |
779 | case ADAU17X1_CONTROL_PORT_PAD1: | |
780 | case ADAU17X1_DSP_SAMPLING_RATE: | |
781 | case ADAU17X1_SERIAL_INPUT_ROUTE: | |
782 | case ADAU17X1_SERIAL_OUTPUT_ROUTE: | |
783 | case ADAU17X1_DSP_ENABLE: | |
784 | case ADAU17X1_DSP_RUN: | |
785 | case ADAU17X1_SERIAL_SAMPLING_RATE: | |
786 | return true; | |
787 | default: | |
788 | break; | |
789 | } | |
790 | return false; | |
791 | } | |
792 | EXPORT_SYMBOL_GPL(adau17x1_readable_register); | |
793 | ||
794 | bool adau17x1_volatile_register(struct device *dev, unsigned int reg) | |
795 | { | |
796 | /* SigmaDSP parameter and program memory */ | |
797 | if (reg < 0x4000) | |
798 | return true; | |
799 | ||
800 | switch (reg) { | |
801 | /* The PLL register is 6 bytes long */ | |
802 | case ADAU17X1_PLL_CONTROL: | |
803 | case ADAU17X1_PLL_CONTROL + 1: | |
804 | case ADAU17X1_PLL_CONTROL + 2: | |
805 | case ADAU17X1_PLL_CONTROL + 3: | |
806 | case ADAU17X1_PLL_CONTROL + 4: | |
807 | case ADAU17X1_PLL_CONTROL + 5: | |
808 | return true; | |
809 | default: | |
810 | break; | |
811 | } | |
812 | ||
813 | return false; | |
814 | } | |
815 | EXPORT_SYMBOL_GPL(adau17x1_volatile_register); | |
816 | ||
d48b088e | 817 | int adau17x1_setup_firmware(struct adau *adau, unsigned int rate) |
4101866c LPC |
818 | { |
819 | int ret; | |
820 | int dspsr; | |
821 | ||
822 | ret = regmap_read(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, &dspsr); | |
823 | if (ret) | |
824 | return ret; | |
825 | ||
826 | regmap_write(adau->regmap, ADAU17X1_DSP_ENABLE, 1); | |
827 | regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, 0xf); | |
828 | ||
d48b088e | 829 | ret = sigmadsp_setup(adau->sigmadsp, rate); |
4101866c LPC |
830 | if (ret) { |
831 | regmap_write(adau->regmap, ADAU17X1_DSP_ENABLE, 0); | |
832 | return ret; | |
833 | } | |
834 | regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, dspsr); | |
835 | ||
836 | return 0; | |
837 | } | |
d48b088e | 838 | EXPORT_SYMBOL_GPL(adau17x1_setup_firmware); |
4101866c LPC |
839 | |
840 | int adau17x1_add_widgets(struct snd_soc_codec *codec) | |
841 | { | |
33c7b140 | 842 | struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); |
4101866c LPC |
843 | struct adau *adau = snd_soc_codec_get_drvdata(codec); |
844 | int ret; | |
845 | ||
846 | ret = snd_soc_add_codec_controls(codec, adau17x1_controls, | |
847 | ARRAY_SIZE(adau17x1_controls)); | |
848 | if (ret) | |
849 | return ret; | |
33c7b140 | 850 | ret = snd_soc_dapm_new_controls(dapm, adau17x1_dapm_widgets, |
4101866c LPC |
851 | ARRAY_SIZE(adau17x1_dapm_widgets)); |
852 | if (ret) | |
853 | return ret; | |
854 | ||
855 | if (adau17x1_has_dsp(adau)) { | |
33c7b140 | 856 | ret = snd_soc_dapm_new_controls(dapm, adau17x1_dsp_dapm_widgets, |
4101866c | 857 | ARRAY_SIZE(adau17x1_dsp_dapm_widgets)); |
d48b088e LPC |
858 | if (ret) |
859 | return ret; | |
860 | ||
861 | if (!adau->sigmadsp) | |
862 | return 0; | |
863 | ||
864 | ret = sigmadsp_attach(adau->sigmadsp, &codec->component); | |
865 | if (ret) { | |
866 | dev_err(codec->dev, "Failed to attach firmware: %d\n", | |
867 | ret); | |
868 | return ret; | |
869 | } | |
4101866c | 870 | } |
d48b088e LPC |
871 | |
872 | return 0; | |
4101866c LPC |
873 | } |
874 | EXPORT_SYMBOL_GPL(adau17x1_add_widgets); | |
875 | ||
876 | int adau17x1_add_routes(struct snd_soc_codec *codec) | |
877 | { | |
33c7b140 | 878 | struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); |
4101866c LPC |
879 | struct adau *adau = snd_soc_codec_get_drvdata(codec); |
880 | int ret; | |
881 | ||
33c7b140 | 882 | ret = snd_soc_dapm_add_routes(dapm, adau17x1_dapm_routes, |
4101866c LPC |
883 | ARRAY_SIZE(adau17x1_dapm_routes)); |
884 | if (ret) | |
885 | return ret; | |
886 | ||
887 | if (adau17x1_has_dsp(adau)) { | |
33c7b140 | 888 | ret = snd_soc_dapm_add_routes(dapm, adau17x1_dsp_dapm_routes, |
4101866c LPC |
889 | ARRAY_SIZE(adau17x1_dsp_dapm_routes)); |
890 | } else { | |
33c7b140 | 891 | ret = snd_soc_dapm_add_routes(dapm, adau17x1_no_dsp_dapm_routes, |
4101866c LPC |
892 | ARRAY_SIZE(adau17x1_no_dsp_dapm_routes)); |
893 | } | |
5d76de61 LPC |
894 | |
895 | if (adau->clk_src != ADAU17X1_CLK_SRC_MCLK) | |
896 | snd_soc_dapm_add_routes(dapm, &adau17x1_dapm_pll_route, 1); | |
897 | ||
4101866c LPC |
898 | return ret; |
899 | } | |
900 | EXPORT_SYMBOL_GPL(adau17x1_add_routes); | |
901 | ||
4101866c LPC |
902 | int adau17x1_resume(struct snd_soc_codec *codec) |
903 | { | |
904 | struct adau *adau = snd_soc_codec_get_drvdata(codec); | |
905 | ||
906 | if (adau->switch_mode) | |
907 | adau->switch_mode(codec->dev); | |
908 | ||
4101866c LPC |
909 | regcache_sync(adau->regmap); |
910 | ||
911 | return 0; | |
912 | } | |
913 | EXPORT_SYMBOL_GPL(adau17x1_resume); | |
914 | ||
915 | int adau17x1_probe(struct device *dev, struct regmap *regmap, | |
d48b088e LPC |
916 | enum adau17x1_type type, void (*switch_mode)(struct device *dev), |
917 | const char *firmware_name) | |
4101866c LPC |
918 | { |
919 | struct adau *adau; | |
5d76de61 | 920 | int ret; |
4101866c LPC |
921 | |
922 | if (IS_ERR(regmap)) | |
923 | return PTR_ERR(regmap); | |
924 | ||
925 | adau = devm_kzalloc(dev, sizeof(*adau), GFP_KERNEL); | |
926 | if (!adau) | |
927 | return -ENOMEM; | |
928 | ||
5d76de61 LPC |
929 | adau->mclk = devm_clk_get(dev, "mclk"); |
930 | if (IS_ERR(adau->mclk)) { | |
931 | if (PTR_ERR(adau->mclk) != -ENOENT) | |
932 | return PTR_ERR(adau->mclk); | |
933 | /* Clock is optional (for the driver) */ | |
934 | adau->mclk = NULL; | |
935 | } else if (adau->mclk) { | |
936 | adau->clk_src = ADAU17X1_CLK_SRC_PLL_AUTO; | |
937 | ||
938 | /* | |
939 | * Any valid PLL output rate will work at this point, use one | |
940 | * that is likely to be chosen later as well. The register will | |
941 | * be written when the PLL is powered up for the first time. | |
942 | */ | |
943 | ret = adau_calc_pll_cfg(clk_get_rate(adau->mclk), 48000 * 1024, | |
944 | adau->pll_regs); | |
945 | if (ret < 0) | |
946 | return ret; | |
947 | ||
948 | ret = clk_prepare_enable(adau->mclk); | |
949 | if (ret) | |
950 | return ret; | |
951 | } | |
952 | ||
4101866c LPC |
953 | adau->regmap = regmap; |
954 | adau->switch_mode = switch_mode; | |
955 | adau->type = type; | |
956 | ||
957 | dev_set_drvdata(dev, adau); | |
958 | ||
d48b088e LPC |
959 | if (firmware_name) { |
960 | adau->sigmadsp = devm_sigmadsp_init_regmap(dev, regmap, NULL, | |
961 | firmware_name); | |
962 | if (IS_ERR(adau->sigmadsp)) { | |
963 | dev_warn(dev, "Could not find firmware file: %ld\n", | |
964 | PTR_ERR(adau->sigmadsp)); | |
965 | adau->sigmadsp = NULL; | |
966 | } | |
967 | } | |
968 | ||
4101866c LPC |
969 | if (switch_mode) |
970 | switch_mode(dev); | |
971 | ||
972 | return 0; | |
973 | } | |
974 | EXPORT_SYMBOL_GPL(adau17x1_probe); | |
975 | ||
5d76de61 LPC |
976 | void adau17x1_remove(struct device *dev) |
977 | { | |
978 | struct adau *adau = dev_get_drvdata(dev); | |
979 | ||
980 | snd_soc_unregister_codec(dev); | |
981 | if (adau->mclk) | |
982 | clk_disable_unprepare(adau->mclk); | |
983 | } | |
984 | EXPORT_SYMBOL_GPL(adau17x1_remove); | |
985 | ||
4101866c LPC |
986 | MODULE_DESCRIPTION("ASoC ADAU1X61/ADAU1X81 common code"); |
987 | MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); | |
988 | MODULE_LICENSE("GPL"); |