[deliverable/linux.git] / sound / soc / codecs / adau17x1.h

#ifndef __ADAU17X1_H__
#define __ADAU17X1_H__

#include <linux/regmap.h>
#include <linux/platform_data/adau17x1.h>

enum adau17x1_type {
	ADAU1361,
	ADAU1761,
	ADAU1381,
	ADAU1781,
};

enum adau17x1_pll {
	ADAU17X1_PLL,
};

enum adau17x1_pll_src {
	ADAU17X1_PLL_SRC_MCLK,
};

enum adau17x1_clk_src {
	ADAU17X1_CLK_SRC_MCLK,
	ADAU17X1_CLK_SRC_PLL,
};

struct adau {
	unsigned int sysclk;
	unsigned int pll_freq;

	enum adau17x1_clk_src clk_src;
	enum adau17x1_type type;
	void (*switch_mode)(struct device *dev);

	unsigned int dai_fmt;

	uint8_t pll_regs[6];

	bool master;

	unsigned int tdm_slot[2];
	bool dsp_bypass[2];

	struct regmap *regmap;
};

int adau17x1_add_widgets(struct snd_soc_codec *codec);
int adau17x1_add_routes(struct snd_soc_codec *codec);
int adau17x1_probe(struct device *dev, struct regmap *regmap,
	enum adau17x1_type type, void (*switch_mode)(struct device *dev));
int adau17x1_set_micbias_voltage(struct snd_soc_codec *codec,
	enum adau17x1_micbias_voltage micbias);
bool adau17x1_readable_register(struct device *dev, unsigned int reg);
bool adau17x1_volatile_register(struct device *dev, unsigned int reg);
int adau17x1_resume(struct snd_soc_codec *codec);

extern const struct snd_soc_dai_ops adau17x1_dai_ops;

int adau17x1_load_firmware(struct adau *adau, struct device *dev,
	const char *firmware);
bool adau17x1_has_dsp(struct adau *adau);

#define ADAU17X1_CLOCK_CONTROL			0x4000
#define ADAU17X1_PLL_CONTROL			0x4002
#define ADAU17X1_REC_POWER_MGMT			0x4009
#define ADAU17X1_MICBIAS			0x4010
#define ADAU17X1_SERIAL_PORT0			0x4015
#define ADAU17X1_SERIAL_PORT1			0x4016
#define ADAU17X1_CONVERTER0			0x4017
#define ADAU17X1_CONVERTER1			0x4018
#define ADAU17X1_LEFT_INPUT_DIGITAL_VOL		0x401a
#define ADAU17X1_RIGHT_INPUT_DIGITAL_VOL	0x401b
#define ADAU17X1_ADC_CONTROL			0x4019
#define ADAU17X1_PLAY_POWER_MGMT		0x4029
#define ADAU17X1_DAC_CONTROL0			0x402a
#define ADAU17X1_DAC_CONTROL1			0x402b
#define ADAU17X1_DAC_CONTROL2			0x402c
#define ADAU17X1_SERIAL_PORT_PAD		0x402d
#define ADAU17X1_CONTROL_PORT_PAD0		0x402f
#define ADAU17X1_CONTROL_PORT_PAD1		0x4030
#define ADAU17X1_DSP_SAMPLING_RATE		0x40eb
#define ADAU17X1_SERIAL_INPUT_ROUTE		0x40f2
#define ADAU17X1_SERIAL_OUTPUT_ROUTE		0x40f3
#define ADAU17X1_DSP_ENABLE			0x40f5
#define ADAU17X1_DSP_RUN			0x40f6
#define ADAU17X1_SERIAL_SAMPLING_RATE		0x40f8

#define ADAU17X1_SERIAL_PORT0_BCLK_POL		BIT(4)
#define ADAU17X1_SERIAL_PORT0_LRCLK_POL		BIT(3)
#define ADAU17X1_SERIAL_PORT0_MASTER		BIT(0)

#define ADAU17X1_SERIAL_PORT1_DELAY1		0x00
#define ADAU17X1_SERIAL_PORT1_DELAY0		0x01
#define ADAU17X1_SERIAL_PORT1_DELAY8		0x02
#define ADAU17X1_SERIAL_PORT1_DELAY16		0x03
#define ADAU17X1_SERIAL_PORT1_DELAY_MASK	0x03

#define ADAU17X1_CLOCK_CONTROL_INFREQ_MASK	0x6
#define ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL	BIT(3)
#define ADAU17X1_CLOCK_CONTROL_SYSCLK_EN	BIT(0)

#define ADAU17X1_SERIAL_PORT1_BCLK32		(0x0 << 5)
#define ADAU17X1_SERIAL_PORT1_BCLK48		(0x1 << 5)
#define ADAU17X1_SERIAL_PORT1_BCLK64		(0x2 << 5)
#define ADAU17X1_SERIAL_PORT1_BCLK128		(0x3 << 5)
#define ADAU17X1_SERIAL_PORT1_BCLK256		(0x4 << 5)
#define ADAU17X1_SERIAL_PORT1_BCLK_MASK		(0x7 << 5)

#define ADAU17X1_SERIAL_PORT0_STEREO		(0x0 << 1)
#define ADAU17X1_SERIAL_PORT0_TDM4		(0x1 << 1)
#define ADAU17X1_SERIAL_PORT0_TDM8		(0x2 << 1)
#define ADAU17X1_SERIAL_PORT0_TDM_MASK		(0x3 << 1)
#define ADAU17X1_SERIAL_PORT0_PULSE_MODE	BIT(5)

#define ADAU17X1_CONVERTER0_DAC_PAIR(x)		(((x) - 1) << 5)
#define ADAU17X1_CONVERTER0_DAC_PAIR_MASK	(0x3 << 5)
#define ADAU17X1_CONVERTER1_ADC_PAIR(x)		((x) - 1)
#define ADAU17X1_CONVERTER1_ADC_PAIR_MASK	0x3

#define ADAU17X1_CONVERTER0_CONVSR_MASK		0x7


#endif
Commit	Line	Data
4101866c LPC	1	#ifndef __ADAU17X1_H__
	2	#define __ADAU17X1_H__
	3
	4	#include <linux/regmap.h>
	5	#include <linux/platform_data/adau17x1.h>
	6
	7	enum adau17x1_type {
	8	ADAU1361,
	9	ADAU1761,
	10	ADAU1381,
	11	ADAU1781,
	12	};
	13
	14	enum adau17x1_pll {
	15	ADAU17X1_PLL,
	16	};
	17
	18	enum adau17x1_pll_src {
	19	ADAU17X1_PLL_SRC_MCLK,
	20	};
	21
	22	enum adau17x1_clk_src {
	23	ADAU17X1_CLK_SRC_MCLK,
	24	ADAU17X1_CLK_SRC_PLL,
	25	};
	26
	27	struct adau {
	28	unsigned int sysclk;
	29	unsigned int pll_freq;
	30
	31	enum adau17x1_clk_src clk_src;
	32	enum adau17x1_type type;
	33	void (switch_mode)(struct device dev);
	34
	35	unsigned int dai_fmt;
	36
	37	uint8_t pll_regs[6];
	38
	39	bool master;
	40
	41	unsigned int tdm_slot[2];
	42	bool dsp_bypass[2];
	43
	44	struct regmap *regmap;
	45	};
	46
	47	int adau17x1_add_widgets(struct snd_soc_codec *codec);
	48	int adau17x1_add_routes(struct snd_soc_codec *codec);
	49	int adau17x1_probe(struct device dev, struct regmap regmap,
	50	enum adau17x1_type type, void (switch_mode)(struct device dev));
	51	int adau17x1_set_micbias_voltage(struct snd_soc_codec *codec,
	52	enum adau17x1_micbias_voltage micbias);
	53	bool adau17x1_readable_register(struct device *dev, unsigned int reg);
	54	bool adau17x1_volatile_register(struct device *dev, unsigned int reg);
4101866c LPC	55	int adau17x1_resume(struct snd_soc_codec *codec);
	56
	57	extern const struct snd_soc_dai_ops adau17x1_dai_ops;
	58
	59	int adau17x1_load_firmware(struct adau adau, struct device dev,
	60	const char *firmware);
	61	bool adau17x1_has_dsp(struct adau *adau);
	62
	63	#define ADAU17X1_CLOCK_CONTROL 0x4000
	64	#define ADAU17X1_PLL_CONTROL 0x4002
	65	#define ADAU17X1_REC_POWER_MGMT 0x4009
	66	#define ADAU17X1_MICBIAS 0x4010
	67	#define ADAU17X1_SERIAL_PORT0 0x4015
	68	#define ADAU17X1_SERIAL_PORT1 0x4016
	69	#define ADAU17X1_CONVERTER0 0x4017
	70	#define ADAU17X1_CONVERTER1 0x4018
	71	#define ADAU17X1_LEFT_INPUT_DIGITAL_VOL 0x401a
	72	#define ADAU17X1_RIGHT_INPUT_DIGITAL_VOL 0x401b
	73	#define ADAU17X1_ADC_CONTROL 0x4019
	74	#define ADAU17X1_PLAY_POWER_MGMT 0x4029
	75	#define ADAU17X1_DAC_CONTROL0 0x402a
	76	#define ADAU17X1_DAC_CONTROL1 0x402b
	77	#define ADAU17X1_DAC_CONTROL2 0x402c
	78	#define ADAU17X1_SERIAL_PORT_PAD 0x402d
	79	#define ADAU17X1_CONTROL_PORT_PAD0 0x402f
	80	#define ADAU17X1_CONTROL_PORT_PAD1 0x4030
	81	#define ADAU17X1_DSP_SAMPLING_RATE 0x40eb
	82	#define ADAU17X1_SERIAL_INPUT_ROUTE 0x40f2
	83	#define ADAU17X1_SERIAL_OUTPUT_ROUTE 0x40f3
	84	#define ADAU17X1_DSP_ENABLE 0x40f5
	85	#define ADAU17X1_DSP_RUN 0x40f6
	86	#define ADAU17X1_SERIAL_SAMPLING_RATE 0x40f8
	87
	88	#define ADAU17X1_SERIAL_PORT0_BCLK_POL BIT(4)
	89	#define ADAU17X1_SERIAL_PORT0_LRCLK_POL BIT(3)
	90	#define ADAU17X1_SERIAL_PORT0_MASTER BIT(0)
	91
	92	#define ADAU17X1_SERIAL_PORT1_DELAY1 0x00
	93	#define ADAU17X1_SERIAL_PORT1_DELAY0 0x01
	94	#define ADAU17X1_SERIAL_PORT1_DELAY8 0x02
	95	#define ADAU17X1_SERIAL_PORT1_DELAY16 0x03
	96	#define ADAU17X1_SERIAL_PORT1_DELAY_MASK 0x03
	97
	98	#define ADAU17X1_CLOCK_CONTROL_INFREQ_MASK 0x6
	99	#define ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL BIT(3)
	100	#define ADAU17X1_CLOCK_CONTROL_SYSCLK_EN BIT(0)
	101
	102	#define ADAU17X1_SERIAL_PORT1_BCLK32 (0x0 << 5)
	103	#define ADAU17X1_SERIAL_PORT1_BCLK48 (0x1 << 5)
	104	#define ADAU17X1_SERIAL_PORT1_BCLK64 (0x2 << 5)
	105	#define ADAU17X1_SERIAL_PORT1_BCLK128 (0x3 << 5)
	106	#define ADAU17X1_SERIAL_PORT1_BCLK256 (0x4 << 5)
	107	#define ADAU17X1_SERIAL_PORT1_BCLK_MASK (0x7 << 5)
	108
	109	#define ADAU17X1_SERIAL_PORT0_STEREO (0x0 << 1)
	110	#define ADAU17X1_SERIAL_PORT0_TDM4 (0x1 << 1)
	111	#define ADAU17X1_SERIAL_PORT0_TDM8 (0x2 << 1)
	112	#define ADAU17X1_SERIAL_PORT0_TDM_MASK (0x3 << 1)
	113	#define ADAU17X1_SERIAL_PORT0_PULSE_MODE BIT(5)
	114
	115	#define ADAU17X1_CONVERTER0_DAC_PAIR(x) (((x) - 1) << 5)
	116	#define ADAU17X1_CONVERTER0_DAC_PAIR_MASK (0x3 << 5)
	117	#define ADAU17X1_CONVERTER1_ADC_PAIR(x) ((x) - 1)
	118	#define ADAU17X1_CONVERTER1_ADC_PAIR_MASK 0x3
119
120	#define ADAU17X1_CONVERTER0_CONVSR_MASK 0x7
121
122
123	#endif