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ASoC: Move bias level update to the core
[deliverable/linux.git] / sound / soc / codecs / adau1977.c
CommitLineData
603597c9
LPC		 1/*
2 * ADAU1977/ADAU1978/ADAU1979 driver
3 *
4 * Copyright 2014 Analog Devices Inc.
5 * Author: Lars-Peter Clausen <lars@metafoo.de>
6 *
7 * Licensed under the GPL-2.
8 */
9
10#include <linux/delay.h>
11#include <linux/device.h>
12#include <linux/gpio/consumer.h>
13#include <linux/i2c.h>
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/platform_data/adau1977.h>
17#include <linux/regmap.h>
18#include <linux/regulator/consumer.h>
19#include <linux/slab.h>
20
21#include <sound/core.h>
22#include <sound/initval.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include <sound/tlv.h>
27
28#include "adau1977.h"
29
30#define ADAU1977_REG_POWER 0x00
31#define ADAU1977_REG_PLL 0x01
32#define ADAU1977_REG_BOOST 0x02
33#define ADAU1977_REG_MICBIAS 0x03
34#define ADAU1977_REG_BLOCK_POWER_SAI 0x04
35#define ADAU1977_REG_SAI_CTRL0 0x05
36#define ADAU1977_REG_SAI_CTRL1 0x06
37#define ADAU1977_REG_CMAP12 0x07
38#define ADAU1977_REG_CMAP34 0x08
39#define ADAU1977_REG_SAI_OVERTEMP 0x09
40#define ADAU1977_REG_POST_ADC_GAIN(x) (0x0a + (x))
41#define ADAU1977_REG_MISC_CONTROL 0x0e
42#define ADAU1977_REG_DIAG_CONTROL 0x10
43#define ADAU1977_REG_STATUS(x) (0x11 + (x))
44#define ADAU1977_REG_DIAG_IRQ1 0x15
45#define ADAU1977_REG_DIAG_IRQ2 0x16
46#define ADAU1977_REG_ADJUST1 0x17
47#define ADAU1977_REG_ADJUST2 0x18
48#define ADAU1977_REG_ADC_CLIP 0x19
49#define ADAU1977_REG_DC_HPF_CAL 0x1a
50
51#define ADAU1977_POWER_RESET BIT(7)
52#define ADAU1977_POWER_PWUP BIT(0)
53
54#define ADAU1977_PLL_CLK_S BIT(4)
55#define ADAU1977_PLL_MCS_MASK 0x7
56
57#define ADAU1977_MICBIAS_MB_VOLTS_MASK 0xf0
58#define ADAU1977_MICBIAS_MB_VOLTS_OFFSET 4
59
60#define ADAU1977_BLOCK_POWER_SAI_LR_POL BIT(7)
61#define ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE BIT(6)
62#define ADAU1977_BLOCK_POWER_SAI_LDO_EN BIT(5)
63
64#define ADAU1977_SAI_CTRL0_FMT_MASK (0x3 << 6)
65#define ADAU1977_SAI_CTRL0_FMT_I2S (0x0 << 6)
66#define ADAU1977_SAI_CTRL0_FMT_LJ (0x1 << 6)
67#define ADAU1977_SAI_CTRL0_FMT_RJ_24BIT (0x2 << 6)
68#define ADAU1977_SAI_CTRL0_FMT_RJ_16BIT (0x3 << 6)
69
70#define ADAU1977_SAI_CTRL0_SAI_MASK (0x7 << 3)
71#define ADAU1977_SAI_CTRL0_SAI_I2S (0x0 << 3)
72#define ADAU1977_SAI_CTRL0_SAI_TDM_2 (0x1 << 3)
73#define ADAU1977_SAI_CTRL0_SAI_TDM_4 (0x2 << 3)
74#define ADAU1977_SAI_CTRL0_SAI_TDM_8 (0x3 << 3)
75#define ADAU1977_SAI_CTRL0_SAI_TDM_16 (0x4 << 3)
76
77#define ADAU1977_SAI_CTRL0_FS_MASK (0x7)
78#define ADAU1977_SAI_CTRL0_FS_8000_12000 (0x0)
79#define ADAU1977_SAI_CTRL0_FS_16000_24000 (0x1)
80#define ADAU1977_SAI_CTRL0_FS_32000_48000 (0x2)
81#define ADAU1977_SAI_CTRL0_FS_64000_96000 (0x3)
82#define ADAU1977_SAI_CTRL0_FS_128000_192000 (0x4)
83
84#define ADAU1977_SAI_CTRL1_SLOT_WIDTH_MASK (0x3 << 5)
85#define ADAU1977_SAI_CTRL1_SLOT_WIDTH_32 (0x0 << 5)
86#define ADAU1977_SAI_CTRL1_SLOT_WIDTH_24 (0x1 << 5)
87#define ADAU1977_SAI_CTRL1_SLOT_WIDTH_16 (0x2 << 5)
88#define ADAU1977_SAI_CTRL1_DATA_WIDTH_MASK (0x1 << 4)
89#define ADAU1977_SAI_CTRL1_DATA_WIDTH_16BIT (0x1 << 4)
90#define ADAU1977_SAI_CTRL1_DATA_WIDTH_24BIT (0x0 << 4)
91#define ADAU1977_SAI_CTRL1_LRCLK_PULSE BIT(3)
92#define ADAU1977_SAI_CTRL1_MSB BIT(2)
93#define ADAU1977_SAI_CTRL1_BCLKRATE_16 (0x1 << 1)
94#define ADAU1977_SAI_CTRL1_BCLKRATE_32 (0x0 << 1)
95#define ADAU1977_SAI_CTRL1_BCLKRATE_MASK (0x1 << 1)
96#define ADAU1977_SAI_CTRL1_MASTER BIT(0)
97
98#define ADAU1977_SAI_OVERTEMP_DRV_C(x) BIT(4 + (x))
99#define ADAU1977_SAI_OVERTEMP_DRV_HIZ BIT(3)
100
101#define ADAU1977_MISC_CONTROL_SUM_MODE_MASK (0x3 << 6)
102#define ADAU1977_MISC_CONTROL_SUM_MODE_1CH (0x2 << 6)
103#define ADAU1977_MISC_CONTROL_SUM_MODE_2CH (0x1 << 6)
104#define ADAU1977_MISC_CONTROL_SUM_MODE_4CH (0x0 << 6)
105#define ADAU1977_MISC_CONTROL_MMUTE BIT(4)
106#define ADAU1977_MISC_CONTROL_DC_CAL BIT(0)
107
108#define ADAU1977_CHAN_MAP_SECOND_SLOT_OFFSET 4
109#define ADAU1977_CHAN_MAP_FIRST_SLOT_OFFSET 0
110
111struct adau1977 {
112 struct regmap *regmap;
113 bool right_j;
114 unsigned int sysclk;
115 enum adau1977_sysclk_src sysclk_src;
116 struct gpio_desc *reset_gpio;
117 enum adau1977_type type;
118
119 struct regulator *avdd_reg;
120 struct regulator *dvdd_reg;
121
122 struct snd_pcm_hw_constraint_list constraints;
123
124 struct device *dev;
125 void (*switch_mode)(struct device *dev);
126
127 unsigned int max_master_fs;
128 unsigned int slot_width;
129 bool enabled;
130 bool master;
131};
132
133static const struct reg_default adau1977_reg_defaults[] = {
134 { 0x00, 0x00 },
135 { 0x01, 0x41 },
136 { 0x02, 0x4a },
137 { 0x03, 0x7d },
138 { 0x04, 0x3d },
139 { 0x05, 0x02 },
140 { 0x06, 0x00 },
141 { 0x07, 0x10 },
142 { 0x08, 0x32 },
143 { 0x09, 0xf0 },
144 { 0x0a, 0xa0 },
145 { 0x0b, 0xa0 },
146 { 0x0c, 0xa0 },
147 { 0x0d, 0xa0 },
148 { 0x0e, 0x02 },
149 { 0x10, 0x0f },
150 { 0x15, 0x20 },
151 { 0x16, 0x00 },
152 { 0x17, 0x00 },
153 { 0x18, 0x00 },
154 { 0x1a, 0x00 },
155};
156
157static const DECLARE_TLV_DB_MINMAX_MUTE(adau1977_adc_gain, -3562, 6000);
158
159static const struct snd_soc_dapm_widget adau1977_micbias_dapm_widgets[] = {
160 SND_SOC_DAPM_SUPPLY("MICBIAS", ADAU1977_REG_MICBIAS,
161 3, 0, NULL, 0)
162};
163
164static const struct snd_soc_dapm_widget adau1977_dapm_widgets[] = {
165 SND_SOC_DAPM_SUPPLY("Vref", ADAU1977_REG_BLOCK_POWER_SAI,
166 4, 0, NULL, 0),
167
168 SND_SOC_DAPM_ADC("ADC1", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 0, 0),
169 SND_SOC_DAPM_ADC("ADC2", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 1, 0),
170 SND_SOC_DAPM_ADC("ADC3", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 2, 0),
171 SND_SOC_DAPM_ADC("ADC4", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 3, 0),
172
173 SND_SOC_DAPM_INPUT("AIN1"),
174 SND_SOC_DAPM_INPUT("AIN2"),
175 SND_SOC_DAPM_INPUT("AIN3"),
176 SND_SOC_DAPM_INPUT("AIN4"),
177
178 SND_SOC_DAPM_OUTPUT("VREF"),
179};
180
181static const struct snd_soc_dapm_route adau1977_dapm_routes[] = {
182 { "ADC1", NULL, "AIN1" },
183 { "ADC2", NULL, "AIN2" },
184 { "ADC3", NULL, "AIN3" },
185 { "ADC4", NULL, "AIN4" },
186
187 { "ADC1", NULL, "Vref" },
188 { "ADC2", NULL, "Vref" },
189 { "ADC3", NULL, "Vref" },
190 { "ADC4", NULL, "Vref" },
191
192 { "VREF", NULL, "Vref" },
193};
194
195#define ADAU1977_VOLUME(x) \
196 SOC_SINGLE_TLV("ADC" #x " Capture Volume", \
197 ADAU1977_REG_POST_ADC_GAIN((x) - 1), \
198 0, 255, 1, adau1977_adc_gain)
199
200#define ADAU1977_HPF_SWITCH(x) \
201 SOC_SINGLE("ADC" #x " Highpass-Filter Capture Switch", \
202 ADAU1977_REG_DC_HPF_CAL, (x) - 1, 1, 0)
203
204#define ADAU1977_DC_SUB_SWITCH(x) \
205 SOC_SINGLE("ADC" #x " DC Substraction Capture Switch", \
206 ADAU1977_REG_DC_HPF_CAL, (x) + 3, 1, 0)
207
208static const struct snd_kcontrol_new adau1977_snd_controls[] = {
209 ADAU1977_VOLUME(1),
210 ADAU1977_VOLUME(2),
211 ADAU1977_VOLUME(3),
212 ADAU1977_VOLUME(4),
213
214 ADAU1977_HPF_SWITCH(1),
215 ADAU1977_HPF_SWITCH(2),
216 ADAU1977_HPF_SWITCH(3),
217 ADAU1977_HPF_SWITCH(4),
218
219 ADAU1977_DC_SUB_SWITCH(1),
220 ADAU1977_DC_SUB_SWITCH(2),
221 ADAU1977_DC_SUB_SWITCH(3),
222 ADAU1977_DC_SUB_SWITCH(4),
223};
224
225static int adau1977_reset(struct adau1977 *adau1977)
226{
227 int ret;
228
229 /*
230 * The reset bit is obviously volatile, but we need to be able to cache
231 * the other bits in the register, so we can't just mark the whole
232 * register as volatile. Since this is the only place where we'll ever
233 * touch the reset bit just bypass the cache for this operation.
234 */
235 regcache_cache_bypass(adau1977->regmap, true);
236 ret = regmap_write(adau1977->regmap, ADAU1977_REG_POWER,
237 ADAU1977_POWER_RESET);
238 regcache_cache_bypass(adau1977->regmap, false);
239 if (ret)
240 return ret;
241
242 return ret;
243}
244
245/*
246 * Returns the appropriate setting for ths FS field in the CTRL0 register
247 * depending on the rate.
248 */
249static int adau1977_lookup_fs(unsigned int rate)
250{
251 if (rate >= 8000 && rate <= 12000)
252 return ADAU1977_SAI_CTRL0_FS_8000_12000;
253 else if (rate >= 16000 && rate <= 24000)
254 return ADAU1977_SAI_CTRL0_FS_16000_24000;
255 else if (rate >= 32000 && rate <= 48000)
256 return ADAU1977_SAI_CTRL0_FS_32000_48000;
257 else if (rate >= 64000 && rate <= 96000)
258 return ADAU1977_SAI_CTRL0_FS_64000_96000;
259 else if (rate >= 128000 && rate <= 192000)
260 return ADAU1977_SAI_CTRL0_FS_128000_192000;
261 else
262 return -EINVAL;
263}
264
265static int adau1977_lookup_mcs(struct adau1977 *adau1977, unsigned int rate,
266 unsigned int fs)
267{
268 unsigned int mcs;
269
270 /*
271 * rate = sysclk / (512 * mcs_lut[mcs]) * 2**fs
272 * => mcs_lut[mcs] = sysclk / (512 * rate) * 2**fs
273 * => mcs_lut[mcs] = sysclk / ((512 / 2**fs) * rate)
274 */
275
276 rate *= 512 >> fs;
277
278 if (adau1977->sysclk % rate != 0)
279 return -EINVAL;
280
281 mcs = adau1977->sysclk / rate;
282
283 /* The factors configured by MCS are 1, 2, 3, 4, 6 */
284 if (mcs < 1 || mcs > 6 || mcs == 5)
285 return -EINVAL;
286
287 mcs = mcs - 1;
288 if (mcs == 5)
289 mcs = 4;
290
291 return mcs;
292}
293
294static int adau1977_hw_params(struct snd_pcm_substream *substream,
295 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
296{
297 struct snd_soc_codec *codec = dai->codec;
298 struct adau1977 *adau1977 = snd_soc_codec_get_drvdata(codec);
299 unsigned int rate = params_rate(params);
300 unsigned int slot_width;
301 unsigned int ctrl0, ctrl0_mask;
302 unsigned int ctrl1;
303 int mcs, fs;
304 int ret;
305
306 fs = adau1977_lookup_fs(rate);
307 if (fs < 0)
308 return fs;
309
310 if (adau1977->sysclk_src == ADAU1977_SYSCLK_SRC_MCLK) {
311 mcs = adau1977_lookup_mcs(adau1977, rate, fs);
312 if (mcs < 0)
313 return mcs;
314 } else {
315 mcs = 0;
316 }
317
318 ctrl0_mask = ADAU1977_SAI_CTRL0_FS_MASK;
319 ctrl0 = fs;
320
321 if (adau1977->right_j) {
322 switch (params_width(params)) {
323 case 16:
324 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_RJ_16BIT;
325 break;
326 case 24:
327 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_RJ_24BIT;
328 break;
329 default:
330 return -EINVAL;
331 }
332 ctrl0_mask |= ADAU1977_SAI_CTRL0_FMT_MASK;
333 }
334
335 if (adau1977->master) {
336 switch (params_width(params)) {
337 case 16:
338 ctrl1 = ADAU1977_SAI_CTRL1_DATA_WIDTH_16BIT;
339 slot_width = 16;
340 break;
341 case 24:
342 case 32:
343 ctrl1 = ADAU1977_SAI_CTRL1_DATA_WIDTH_24BIT;
344 slot_width = 32;
345 break;
346 default:
347 return -EINVAL;
348 }
349
350 /* In TDM mode there is a fixed slot width */
351 if (adau1977->slot_width)
352 slot_width = adau1977->slot_width;
353
354 if (slot_width == 16)
355 ctrl1 |= ADAU1977_SAI_CTRL1_BCLKRATE_16;
356 else
357 ctrl1 |= ADAU1977_SAI_CTRL1_BCLKRATE_32;
358
359 ret = regmap_update_bits(adau1977->regmap,
360 ADAU1977_REG_SAI_CTRL1,
361 ADAU1977_SAI_CTRL1_DATA_WIDTH_MASK |
362 ADAU1977_SAI_CTRL1_BCLKRATE_MASK,
363 ctrl1);
364 if (ret < 0)
365 return ret;
366 }
367
368 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL0,
369 ctrl0_mask, ctrl0);
370 if (ret < 0)
371 return ret;
372
373 return regmap_update_bits(adau1977->regmap, ADAU1977_REG_PLL,
374 ADAU1977_PLL_MCS_MASK, mcs);
375}
376
377static int adau1977_power_disable(struct adau1977 *adau1977)
378{
379 int ret = 0;
380
381 if (!adau1977->enabled)
382 return 0;
383
384 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_POWER,
385 ADAU1977_POWER_PWUP, 0);
386 if (ret)
387 return ret;
388
389 regcache_mark_dirty(adau1977->regmap);
390
391 if (adau1977->reset_gpio)
392 gpiod_set_value_cansleep(adau1977->reset_gpio, 0);
393
394 regcache_cache_only(adau1977->regmap, true);
395
396 regulator_disable(adau1977->avdd_reg);
397 if (adau1977->dvdd_reg)
398 regulator_disable(adau1977->dvdd_reg);
399
400 adau1977->enabled = false;
401
402 return 0;
403}
404
405static int adau1977_power_enable(struct adau1977 *adau1977)
406{
407 unsigned int val;
408 int ret = 0;
409
410 if (adau1977->enabled)
411 return 0;
412
413 ret = regulator_enable(adau1977->avdd_reg);
414 if (ret)
415 return ret;
416
417 if (adau1977->dvdd_reg) {
418 ret = regulator_enable(adau1977->dvdd_reg);
419 if (ret)
420 goto err_disable_avdd;
421 }
422
423 if (adau1977->reset_gpio)
424 gpiod_set_value_cansleep(adau1977->reset_gpio, 1);
425
426 regcache_cache_only(adau1977->regmap, false);
427
428 if (adau1977->switch_mode)
429 adau1977->switch_mode(adau1977->dev);
430
431 ret = adau1977_reset(adau1977);
432 if (ret)
433 goto err_disable_dvdd;
434
435 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_POWER,
436 ADAU1977_POWER_PWUP, ADAU1977_POWER_PWUP);
437 if (ret)
438 goto err_disable_dvdd;
439
440 ret = regcache_sync(adau1977->regmap);
441 if (ret)
442 goto err_disable_dvdd;
443
444 /*
445 * The PLL register is not affected by the software reset. It is
446 * possible that the value of the register was changed to the
447 * default value while we were in cache only mode. In this case
448 * regcache_sync will skip over it and we have to manually sync
449 * it.
450 */
451 ret = regmap_read(adau1977->regmap, ADAU1977_REG_PLL, &val);
452 if (ret)
453 goto err_disable_dvdd;
454
455 if (val == 0x41) {
456 regcache_cache_bypass(adau1977->regmap, true);
457 ret = regmap_write(adau1977->regmap, ADAU1977_REG_PLL,
458 0x41);
459 if (ret)
460 goto err_disable_dvdd;
461 regcache_cache_bypass(adau1977->regmap, false);
462 }
463
464 adau1977->enabled = true;
465
466 return ret;
467
468err_disable_dvdd:
469 if (adau1977->dvdd_reg)
470 regulator_disable(adau1977->dvdd_reg);
471err_disable_avdd:
472 regulator_disable(adau1977->avdd_reg);
473 return ret;
474}
475
476static int adau1977_set_bias_level(struct snd_soc_codec *codec,
477 enum snd_soc_bias_level level)
478{
479 struct adau1977 *adau1977 = snd_soc_codec_get_drvdata(codec);
480 int ret = 0;
481
482 switch (level) {
483 case SND_SOC_BIAS_ON:
484 break;
485 case SND_SOC_BIAS_PREPARE:
486 break;
487 case SND_SOC_BIAS_STANDBY:
488 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
489 ret = adau1977_power_enable(adau1977);
490 break;
491 case SND_SOC_BIAS_OFF:
492 ret = adau1977_power_disable(adau1977);
493 break;
494 }
495
496 if (ret)
497 return ret;
498
603597c9
LPC		 499 return 0;
500}
501
502static int adau1977_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
503 unsigned int rx_mask, int slots, int width)
504{
505 struct adau1977 *adau1977 = snd_soc_codec_get_drvdata(dai->codec);
506 unsigned int ctrl0, ctrl1, drv;
507 unsigned int slot[4];
508 unsigned int i;
509 int ret;
510
511 if (slots == 0) {
512 /* 0 = No fixed slot width */
513 adau1977->slot_width = 0;
514 adau1977->max_master_fs = 192000;
515 return regmap_update_bits(adau1977->regmap,
516 ADAU1977_REG_SAI_CTRL0, ADAU1977_SAI_CTRL0_SAI_MASK,
517 ADAU1977_SAI_CTRL0_SAI_I2S);
518 }
519
520 if (rx_mask == 0 || tx_mask != 0)
521 return -EINVAL;
522
523 drv = 0;
524 for (i = 0; i < 4; i++) {
525 slot[i] = __ffs(rx_mask);
526 drv |= ADAU1977_SAI_OVERTEMP_DRV_C(i);
527 rx_mask &= ~(1 << slot[i]);
528 if (slot[i] >= slots)
529 return -EINVAL;
530 if (rx_mask == 0)
531 break;
532 }
533
534 if (rx_mask != 0)
535 return -EINVAL;
536
537 switch (width) {
538 case 16:
539 ctrl1 = ADAU1977_SAI_CTRL1_SLOT_WIDTH_16;
540 break;
541 case 24:
542 /* We can only generate 16 bit or 32 bit wide slots */
543 if (adau1977->master)
544 return -EINVAL;
545 ctrl1 = ADAU1977_SAI_CTRL1_SLOT_WIDTH_24;
546 break;
547 case 32:
548 ctrl1 = ADAU1977_SAI_CTRL1_SLOT_WIDTH_32;
549 break;
550 default:
551 return -EINVAL;
552 }
553
554 switch (slots) {
555 case 2:
556 ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_2;
557 break;
558 case 4:
559 ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_4;
560 break;
561 case 8:
562 ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_8;
563 break;
564 case 16:
565 ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_16;
566 break;
567 default:
568 return -EINVAL;
569 }
570
571 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_OVERTEMP,
572 ADAU1977_SAI_OVERTEMP_DRV_C(0) |
573 ADAU1977_SAI_OVERTEMP_DRV_C(1) |
574 ADAU1977_SAI_OVERTEMP_DRV_C(2) |
575 ADAU1977_SAI_OVERTEMP_DRV_C(3), drv);
576 if (ret)
577 return ret;
578
579 ret = regmap_write(adau1977->regmap, ADAU1977_REG_CMAP12,
580 (slot[1] << ADAU1977_CHAN_MAP_SECOND_SLOT_OFFSET) |
581 (slot[0] << ADAU1977_CHAN_MAP_FIRST_SLOT_OFFSET));
582 if (ret)
583 return ret;
584
585 ret = regmap_write(adau1977->regmap, ADAU1977_REG_CMAP34,
586 (slot[3] << ADAU1977_CHAN_MAP_SECOND_SLOT_OFFSET) |
587 (slot[2] << ADAU1977_CHAN_MAP_FIRST_SLOT_OFFSET));
588 if (ret)
589 return ret;
590
591 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL0,
592 ADAU1977_SAI_CTRL0_SAI_MASK, ctrl0);
593 if (ret)
594 return ret;
595
596 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL1,
597 ADAU1977_SAI_CTRL1_SLOT_WIDTH_MASK, ctrl1);
598 if (ret)
599 return ret;
600
601 adau1977->slot_width = width;
602
603 /* In master mode the maximum bitclock is 24.576 MHz */
604 adau1977->max_master_fs = min(192000, 24576000 / width / slots);
605
606 return 0;
607}
608
609static int adau1977_mute(struct snd_soc_dai *dai, int mute, int stream)
610{
611 struct adau1977 *adau1977 = snd_soc_codec_get_drvdata(dai->codec);
612 unsigned int val;
613
614 if (mute)
615 val = ADAU1977_MISC_CONTROL_MMUTE;
616 else
617 val = 0;
618
619 return regmap_update_bits(adau1977->regmap, ADAU1977_REG_MISC_CONTROL,
620 ADAU1977_MISC_CONTROL_MMUTE, val);
621}
622
623static int adau1977_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
624{
625 struct adau1977 *adau1977 = snd_soc_codec_get_drvdata(dai->codec);
626 unsigned int ctrl0 = 0, ctrl1 = 0, block_power = 0;
627 bool invert_lrclk;
628 int ret;
629
630 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
631 case SND_SOC_DAIFMT_CBS_CFS:
632 adau1977->master = false;
633 break;
634 case SND_SOC_DAIFMT_CBM_CFM:
635 ctrl1 |= ADAU1977_SAI_CTRL1_MASTER;
636 adau1977->master = true;
637 break;
638 default:
639 return -EINVAL;
640 }
641
642 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
643 case SND_SOC_DAIFMT_NB_NF:
644 invert_lrclk = false;
645 break;
646 case SND_SOC_DAIFMT_IB_NF:
647 block_power |= ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE;
648 invert_lrclk = false;
649 break;
650 case SND_SOC_DAIFMT_NB_IF:
651 invert_lrclk = true;
652 break;
653 case SND_SOC_DAIFMT_IB_IF:
654 block_power |= ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE;
655 invert_lrclk = true;
656 break;
657 default:
658 return -EINVAL;
659 }
660
661 adau1977->right_j = false;
662 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
663 case SND_SOC_DAIFMT_I2S:
664 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_I2S;
665 break;
666 case SND_SOC_DAIFMT_LEFT_J:
667 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_LJ;
668 invert_lrclk = !invert_lrclk;
669 break;
670 case SND_SOC_DAIFMT_RIGHT_J:
671 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_RJ_24BIT;
672 adau1977->right_j = true;
673 invert_lrclk = !invert_lrclk;
674 break;
675 case SND_SOC_DAIFMT_DSP_A:
676 ctrl1 |= ADAU1977_SAI_CTRL1_LRCLK_PULSE;
677 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_I2S;
678 invert_lrclk = false;
679 break;
680 case SND_SOC_DAIFMT_DSP_B:
681 ctrl1 |= ADAU1977_SAI_CTRL1_LRCLK_PULSE;
682 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_LJ;
683 invert_lrclk = false;
684 break;
685 default:
686 return -EINVAL;
687 }
688
689 if (invert_lrclk)
690 block_power |= ADAU1977_BLOCK_POWER_SAI_LR_POL;
691
692 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_BLOCK_POWER_SAI,
693 ADAU1977_BLOCK_POWER_SAI_LR_POL |
694 ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE, block_power);
695 if (ret)
696 return ret;
697
698 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL0,
699 ADAU1977_SAI_CTRL0_FMT_MASK,
700 ctrl0);
701 if (ret)
702 return ret;
703
704 return regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL1,
705 ADAU1977_SAI_CTRL1_MASTER | ADAU1977_SAI_CTRL1_LRCLK_PULSE,
706 ctrl1);
707}
708
709static int adau1977_startup(struct snd_pcm_substream *substream,
710 struct snd_soc_dai *dai)
711{
712 struct adau1977 *adau1977 = snd_soc_codec_get_drvdata(dai->codec);
713 u64 formats = 0;
714
715 if (adau1977->slot_width == 16)
716 formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE;
717 else if (adau1977->right_j || adau1977->slot_width == 24)
718 formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
719 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE;
720
721 snd_pcm_hw_constraint_list(substream->runtime, 0,
722 SNDRV_PCM_HW_PARAM_RATE, &adau1977->constraints);
723
724 if (adau1977->master)
725 snd_pcm_hw_constraint_minmax(substream->runtime,
726 SNDRV_PCM_HW_PARAM_RATE, 8000, adau1977->max_master_fs);
727
728 if (formats != 0)
729 snd_pcm_hw_constraint_mask64(substream->runtime,
730 SNDRV_PCM_HW_PARAM_FORMAT, formats);
731
732 return 0;
733}
734
735static int adau1977_set_tristate(struct snd_soc_dai *dai, int tristate)
736{
737 struct adau1977 *adau1977 = snd_soc_codec_get_drvdata(dai->codec);
738 unsigned int val;
739
740 if (tristate)
741 val = ADAU1977_SAI_OVERTEMP_DRV_HIZ;
742 else
743 val = 0;
744
745 return regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_OVERTEMP,
746 ADAU1977_SAI_OVERTEMP_DRV_HIZ, val);
747}
748
749static const struct snd_soc_dai_ops adau1977_dai_ops = {
750 .startup = adau1977_startup,
751 .hw_params = adau1977_hw_params,
752 .mute_stream = adau1977_mute,
753 .set_fmt = adau1977_set_dai_fmt,
754 .set_tdm_slot = adau1977_set_tdm_slot,
755 .set_tristate = adau1977_set_tristate,
756};
757
758static struct snd_soc_dai_driver adau1977_dai = {
759 .name = "adau1977-hifi",
760 .capture = {
761 .stream_name = "Capture",
762 .channels_min = 1,
763 .channels_max = 4,
764 .rates = SNDRV_PCM_RATE_KNOT,
765 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
766 SNDRV_PCM_FMTBIT_S32_LE,
767 .sig_bits = 24,
768 },
769 .ops = &adau1977_dai_ops,
770};
771
772static const unsigned int adau1977_rates[] = {
773 8000, 16000, 32000, 64000, 128000,
774 11025, 22050, 44100, 88200, 172400,
775 12000, 24000, 48000, 96000, 192000,
776};
777
778#define ADAU1977_RATE_CONSTRAINT_MASK_32000 0x001f
779#define ADAU1977_RATE_CONSTRAINT_MASK_44100 0x03e0
780#define ADAU1977_RATE_CONSTRAINT_MASK_48000 0x7c00
781/* All rates >= 32000 */
782#define ADAU1977_RATE_CONSTRAINT_MASK_LRCLK 0x739c
783
784static bool adau1977_check_sysclk(unsigned int mclk, unsigned int base_freq)
785{
786 unsigned int mcs;
787
788 if (mclk % (base_freq * 128) != 0)
789 return false;
790
791 mcs = mclk / (128 * base_freq);
792 if (mcs < 1 || mcs > 6 || mcs == 5)
793 return false;
794
795 return true;
796}
797
798static int adau1977_set_sysclk(struct snd_soc_codec *codec,
799 int clk_id, int source, unsigned int freq, int dir)
800{
801 struct adau1977 *adau1977 = snd_soc_codec_get_drvdata(codec);
802 unsigned int mask = 0;
803 unsigned int clk_src;
804 unsigned int ret;
805
806 if (dir != SND_SOC_CLOCK_IN)
807 return -EINVAL;
808
809 if (clk_id != ADAU1977_SYSCLK)
810 return -EINVAL;
811
812 switch (source) {
813 case ADAU1977_SYSCLK_SRC_MCLK:
814 clk_src = 0;
815 break;
816 case ADAU1977_SYSCLK_SRC_LRCLK:
817 clk_src = ADAU1977_PLL_CLK_S;
818 break;
819 default:
820 return -EINVAL;
821 }
822
823 if (freq != 0 && source == ADAU1977_SYSCLK_SRC_MCLK) {
824 if (freq < 4000000 || freq > 36864000)
825 return -EINVAL;
826
827 if (adau1977_check_sysclk(freq, 32000))
828 mask |= ADAU1977_RATE_CONSTRAINT_MASK_32000;
829 if (adau1977_check_sysclk(freq, 44100))
830 mask |= ADAU1977_RATE_CONSTRAINT_MASK_44100;
831 if (adau1977_check_sysclk(freq, 48000))
832 mask |= ADAU1977_RATE_CONSTRAINT_MASK_48000;
833
834 if (mask == 0)
835 return -EINVAL;
836 } else if (source == ADAU1977_SYSCLK_SRC_LRCLK) {
837 mask = ADAU1977_RATE_CONSTRAINT_MASK_LRCLK;
838 }
839
840 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_PLL,
841 ADAU1977_PLL_CLK_S, clk_src);
842 if (ret)
843 return ret;
844
845 adau1977->constraints.mask = mask;
846 adau1977->sysclk_src = source;
847 adau1977->sysclk = freq;
848
849 return 0;
850}
851
852static int adau1977_codec_probe(struct snd_soc_codec *codec)
853{
854 struct adau1977 *adau1977 = snd_soc_codec_get_drvdata(codec);
855 int ret;
856
857 switch (adau1977->type) {
858 case ADAU1977:
859 ret = snd_soc_dapm_new_controls(&codec->dapm,
860 adau1977_micbias_dapm_widgets,
861 ARRAY_SIZE(adau1977_micbias_dapm_widgets));
862 if (ret < 0)
863 return ret;
864 break;
865 default:
866 break;
867 }
868
869 return 0;
870}
871
872static struct snd_soc_codec_driver adau1977_codec_driver = {
873 .probe = adau1977_codec_probe,
874 .set_bias_level = adau1977_set_bias_level,
875 .set_sysclk = adau1977_set_sysclk,
876 .idle_bias_off = true,
877
878 .controls = adau1977_snd_controls,
879 .num_controls = ARRAY_SIZE(adau1977_snd_controls),
880 .dapm_widgets = adau1977_dapm_widgets,
881 .num_dapm_widgets = ARRAY_SIZE(adau1977_dapm_widgets),
882 .dapm_routes = adau1977_dapm_routes,
883 .num_dapm_routes = ARRAY_SIZE(adau1977_dapm_routes),
884};
885
886static int adau1977_setup_micbias(struct adau1977 *adau1977)
887{
888 struct adau1977_platform_data *pdata = adau1977->dev->platform_data;
889 unsigned int micbias;
890
891 if (pdata) {
892 micbias = pdata->micbias;
893 if (micbias > ADAU1977_MICBIAS_9V0)
894 return -EINVAL;
895
896 } else {
897 micbias = ADAU1977_MICBIAS_8V5;
898 }
899
900 return regmap_update_bits(adau1977->regmap, ADAU1977_REG_MICBIAS,
901 ADAU1977_MICBIAS_MB_VOLTS_MASK,
902 micbias << ADAU1977_MICBIAS_MB_VOLTS_OFFSET);
903}
904
905int adau1977_probe(struct device *dev, struct regmap *regmap,
906 enum adau1977_type type, void (*switch_mode)(struct device *dev))
907{
908 unsigned int power_off_mask;
909 struct adau1977 *adau1977;
910 int ret;
911
912 if (IS_ERR(regmap))
913 return PTR_ERR(regmap);
914
915 adau1977 = devm_kzalloc(dev, sizeof(*adau1977), GFP_KERNEL);
916 if (adau1977 == NULL)
917 return -ENOMEM;
918
919 adau1977->dev = dev;
920 adau1977->type = type;
921 adau1977->regmap = regmap;
922 adau1977->switch_mode = switch_mode;
923 adau1977->max_master_fs = 192000;
924
925 adau1977->constraints.list = adau1977_rates;
926 adau1977->constraints.count = ARRAY_SIZE(adau1977_rates);
927
928 adau1977->avdd_reg = devm_regulator_get(dev, "AVDD");
929 if (IS_ERR(adau1977->avdd_reg))
930 return PTR_ERR(adau1977->avdd_reg);
931
932 adau1977->dvdd_reg = devm_regulator_get_optional(dev, "DVDD");
933 if (IS_ERR(adau1977->dvdd_reg)) {
934 if (PTR_ERR(adau1977->dvdd_reg) != -ENODEV)
935 return PTR_ERR(adau1977->dvdd_reg);
936 adau1977->dvdd_reg = NULL;
937 }
938
34d7c390
UKK		 939 adau1977->reset_gpio = devm_gpiod_get_optional(dev, "reset",
940 GPIOD_OUT_LOW);
941 if (IS_ERR(adau1977->reset_gpio))
942 return PTR_ERR(adau1977->reset_gpio);
603597c9
LPC		 943
944 dev_set_drvdata(dev, adau1977);
945
34d7c390 946 if (adau1977->reset_gpio)
603597c9 947 ndelay(100);
603597c9
LPC		 948
949 ret = adau1977_power_enable(adau1977);
950 if (ret)
951 return ret;
952
953 if (type == ADAU1977) {
954 ret = adau1977_setup_micbias(adau1977);
955 if (ret)
956 goto err_poweroff;
957 }
958
959 if (adau1977->dvdd_reg)
960 power_off_mask = ~0;
961 else
d8df26bb 962 power_off_mask = (unsigned int)~ADAU1977_BLOCK_POWER_SAI_LDO_EN;
603597c9
LPC		 963
964 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_BLOCK_POWER_SAI,
965 power_off_mask, 0x00);
966 if (ret)
967 goto err_poweroff;
968
969 ret = adau1977_power_disable(adau1977);
970 if (ret)
971 return ret;
972
973 return snd_soc_register_codec(dev, &adau1977_codec_driver,
974 &adau1977_dai, 1);
975
976err_poweroff:
977 adau1977_power_disable(adau1977);
978 return ret;
979
980}
981EXPORT_SYMBOL_GPL(adau1977_probe);
982
983static bool adau1977_register_volatile(struct device *dev, unsigned int reg)
984{
985 switch (reg) {
986 case ADAU1977_REG_STATUS(0):
987 case ADAU1977_REG_STATUS(1):
988 case ADAU1977_REG_STATUS(2):
989 case ADAU1977_REG_STATUS(3):
990 case ADAU1977_REG_ADC_CLIP:
991 return true;
992 }
993
994 return false;
995}
996
997const struct regmap_config adau1977_regmap_config = {
998 .max_register = ADAU1977_REG_DC_HPF_CAL,
999 .volatile_reg = adau1977_register_volatile,
1000
1001 .cache_type = REGCACHE_RBTREE,
1002 .reg_defaults = adau1977_reg_defaults,
1003 .num_reg_defaults = ARRAY_SIZE(adau1977_reg_defaults),
1004};
1005EXPORT_SYMBOL_GPL(adau1977_regmap_config);
1006
1007MODULE_DESCRIPTION("ASoC ADAU1977/ADAU1978/ADAU1979 driver");
1008MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1009MODULE_LICENSE("GPL");
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