[deliverable/linux.git] / sound / soc / codecs / ak4642.c

/*
 * ak4642.c  --  AK4642/AK4643 ALSA Soc Audio driver
 *
 * Copyright (C) 2009 Renesas Solutions Corp.
 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
 *
 * Based on wm8731.c by Richard Purdie
 * Based on ak4535.c by Richard Purdie
 * Based on wm8753.c by Liam Girdwood
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/* ** CAUTION **
 *
 * This is very simple driver.
 * It can use headphone output / stereo input only
 *
 * AK4642 is tested.
 * AK4643 is tested.
 * AK4648 is tested.
 */

#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>

#define PW_MGMT1	0x00
#define PW_MGMT2	0x01
#define SG_SL1		0x02
#define SG_SL2		0x03
#define MD_CTL1		0x04
#define MD_CTL2		0x05
#define TIMER		0x06
#define ALC_CTL1	0x07
#define ALC_CTL2	0x08
#define L_IVC		0x09
#define L_DVC		0x0a
#define ALC_CTL3	0x0b
#define R_IVC		0x0c
#define R_DVC		0x0d
#define MD_CTL3		0x0e
#define MD_CTL4		0x0f
#define PW_MGMT3	0x10
#define DF_S		0x11
#define FIL3_0		0x12
#define FIL3_1		0x13
#define FIL3_2		0x14
#define FIL3_3		0x15
#define EQ_0		0x16
#define EQ_1		0x17
#define EQ_2		0x18
#define EQ_3		0x19
#define EQ_4		0x1a
#define EQ_5		0x1b
#define FIL1_0		0x1c
#define FIL1_1		0x1d
#define FIL1_2		0x1e
#define FIL1_3		0x1f
#define PW_MGMT4	0x20
#define MD_CTL5		0x21
#define LO_MS		0x22
#define HP_MS		0x23
#define SPK_MS		0x24

/* PW_MGMT1*/
#define PMVCM		(1 << 6) /* VCOM Power Management */
#define PMMIN		(1 << 5) /* MIN Input Power Management */
#define PMDAC		(1 << 2) /* DAC Power Management */
#define PMADL		(1 << 0) /* MIC Amp Lch and ADC Lch Power Management */

/* PW_MGMT2 */
#define HPMTN		(1 << 6)
#define PMHPL		(1 << 5)
#define PMHPR		(1 << 4)
#define MS		(1 << 3) /* master/slave select */
#define MCKO		(1 << 1)
#define PMPLL		(1 << 0)

#define PMHP_MASK	(PMHPL | PMHPR)
#define PMHP		PMHP_MASK

/* PW_MGMT3 */
#define PMADR		(1 << 0) /* MIC L / ADC R Power Management */

/* SG_SL1 */
#define MINS		(1 << 6) /* Switch from MIN to Speaker */
#define DACL		(1 << 4) /* Switch from DAC to Stereo or Receiver */
#define PMMP		(1 << 2) /* MPWR pin Power Management */
#define MGAIN0		(1 << 0) /* MIC amp gain*/

/* TIMER */
#define ZTM(param)	((param & 0x3) << 4) /* ALC Zoro Crossing TimeOut */
#define WTM(param)	(((param & 0x4) << 4) | ((param & 0x3) << 2))

/* ALC_CTL1 */
#define ALC		(1 << 5) /* ALC Enable */
#define LMTH0		(1 << 0) /* ALC Limiter / Recovery Level */

/* MD_CTL1 */
#define PLL3		(1 << 7)
#define PLL2		(1 << 6)
#define PLL1		(1 << 5)
#define PLL0		(1 << 4)
#define PLL_MASK	(PLL3 | PLL2 | PLL1 | PLL0)

#define BCKO_MASK	(1 << 3)
#define BCKO_64		BCKO_MASK

#define DIF_MASK	(3 << 0)
#define DSP		(0 << 0)
#define RIGHT_J		(1 << 0)
#define LEFT_J		(2 << 0)
#define I2S		(3 << 0)

/* MD_CTL2 */
#define FS0		(1 << 0)
#define FS1		(1 << 1)
#define FS2		(1 << 2)
#define FS3		(1 << 5)
#define FS_MASK		(FS0 | FS1 | FS2 | FS3)

/* MD_CTL3 */
#define BST1		(1 << 3)

/* MD_CTL4 */
#define DACH		(1 << 0)

/*
 * Playback Volume (table 39)
 *
 * max : 0x00 : +12.0 dB
 *       ( 0.5 dB step )
 * min : 0xFE : -115.0 dB
 * mute: 0xFF
 */
static const DECLARE_TLV_DB_SCALE(out_tlv, -11550, 50, 1);

static const struct snd_kcontrol_new ak4642_snd_controls[] = {

	SOC_DOUBLE_R_TLV("Digital Playback Volume", L_DVC, R_DVC,
			 0, 0xFF, 1, out_tlv),
};

static const struct snd_kcontrol_new ak4642_headphone_control =
	SOC_DAPM_SINGLE("Switch", PW_MGMT2, 6, 1, 0);

static const struct snd_kcontrol_new ak4642_lout_mixer_controls[] = {
	SOC_DAPM_SINGLE("DACL", SG_SL1, 4, 1, 0),
};

static const struct snd_soc_dapm_widget ak4642_dapm_widgets[] = {

	/* Outputs */
	SND_SOC_DAPM_OUTPUT("HPOUTL"),
	SND_SOC_DAPM_OUTPUT("HPOUTR"),
	SND_SOC_DAPM_OUTPUT("LINEOUT"),

	SND_SOC_DAPM_PGA("HPL Out", PW_MGMT2, 5, 0, NULL, 0),
	SND_SOC_DAPM_PGA("HPR Out", PW_MGMT2, 4, 0, NULL, 0),
	SND_SOC_DAPM_SWITCH("Headphone Enable", SND_SOC_NOPM, 0, 0,
			    &ak4642_headphone_control),

	SND_SOC_DAPM_PGA("DACH", MD_CTL4, 0, 0, NULL, 0),

	SND_SOC_DAPM_MIXER("LINEOUT Mixer", PW_MGMT1, 3, 0,
			   &ak4642_lout_mixer_controls[0],
			   ARRAY_SIZE(ak4642_lout_mixer_controls)),

	/* DAC */
	SND_SOC_DAPM_DAC("DAC", "HiFi Playback", PW_MGMT1, 2, 0),
};

static const struct snd_soc_dapm_route ak4642_intercon[] = {

	/* Outputs */
	{"HPOUTL", NULL, "HPL Out"},
	{"HPOUTR", NULL, "HPR Out"},
	{"LINEOUT", NULL, "LINEOUT Mixer"},

	{"HPL Out", NULL, "Headphone Enable"},
	{"HPR Out", NULL, "Headphone Enable"},

	{"Headphone Enable", "Switch", "DACH"},

	{"DACH", NULL, "DAC"},

	{"LINEOUT Mixer", "DACL", "DAC"},
};

/*
 * ak4642 register cache
 */
static const u8 ak4642_reg[] = {
	0x00, 0x00, 0x01, 0x00,
	0x02, 0x00, 0x00, 0x00,
	0xe1, 0xe1, 0x18, 0x00,
	0xe1, 0x18, 0x11, 0x08,
	0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00,
	0x00,
};

static const u8 ak4648_reg[] = {
	0x00, 0x00, 0x01, 0x00,
	0x02, 0x00, 0x00, 0x00,
	0xe1, 0xe1, 0x18, 0x00,
	0xe1, 0x18, 0x11, 0xb8,
	0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00,
	0x00, 0x88, 0x88, 0x08,
};

static int ak4642_dai_startup(struct snd_pcm_substream *substream,
			      struct snd_soc_dai *dai)
{
	int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
	struct snd_soc_codec *codec = dai->codec;

	if (is_play) {
		/*
		 * start headphone output
		 *
		 * PLL, Master Mode
		 * Audio I/F Format :MSB justified (ADC & DAC)
		 * Bass Boost Level : Middle
		 *
		 * This operation came from example code of
		 * "ASAHI KASEI AK4642" (japanese) manual p97.
		 */
		snd_soc_write(codec, L_IVC, 0x91); /* volume */
		snd_soc_write(codec, R_IVC, 0x91); /* volume */
	} else {
		/*
		 * start stereo input
		 *
		 * PLL Master Mode
		 * Audio I/F Format:MSB justified (ADC & DAC)
		 * Pre MIC AMP:+20dB
		 * MIC Power On
		 * ALC setting:Refer to Table 35
		 * ALC bit=“1”
		 *
		 * This operation came from example code of
		 * "ASAHI KASEI AK4642" (japanese) manual p94.
		 */
		snd_soc_write(codec, SG_SL1, PMMP | MGAIN0);
		snd_soc_write(codec, TIMER, ZTM(0x3) | WTM(0x3));
		snd_soc_write(codec, ALC_CTL1, ALC | LMTH0);
		snd_soc_update_bits(codec, PW_MGMT1, PMADL, PMADL);
		snd_soc_update_bits(codec, PW_MGMT3, PMADR, PMADR);
	}

	return 0;
}

static void ak4642_dai_shutdown(struct snd_pcm_substream *substream,
			       struct snd_soc_dai *dai)
{
	int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
	struct snd_soc_codec *codec = dai->codec;

	if (is_play) {
	} else {
		/* stop stereo input */
		snd_soc_update_bits(codec, PW_MGMT1, PMADL, 0);
		snd_soc_update_bits(codec, PW_MGMT3, PMADR, 0);
		snd_soc_update_bits(codec, ALC_CTL1, ALC, 0);
	}
}

static int ak4642_dai_set_sysclk(struct snd_soc_dai *codec_dai,
	int clk_id, unsigned int freq, int dir)
{
	struct snd_soc_codec *codec = codec_dai->codec;
	u8 pll;

	switch (freq) {
	case 11289600:
		pll = PLL2;
		break;
	case 12288000:
		pll = PLL2 | PLL0;
		break;
	case 12000000:
		pll = PLL2 | PLL1;
		break;
	case 24000000:
		pll = PLL2 | PLL1 | PLL0;
		break;
	case 13500000:
		pll = PLL3 | PLL2;
		break;
	case 27000000:
		pll = PLL3 | PLL2 | PLL0;
		break;
	default:
		return -EINVAL;
	}
	snd_soc_update_bits(codec, MD_CTL1, PLL_MASK, pll);

	return 0;
}

static int ak4642_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
	struct snd_soc_codec *codec = dai->codec;
	u8 data;
	u8 bcko;

	data = MCKO | PMPLL; /* use MCKO */
	bcko = 0;

	/* set master/slave audio interface */
	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBM_CFM:
		data |= MS;
		bcko = BCKO_64;
		break;
	case SND_SOC_DAIFMT_CBS_CFS:
		break;
	default:
		return -EINVAL;
	}
	snd_soc_update_bits(codec, PW_MGMT2, MS | MCKO | PMPLL, data);
	snd_soc_update_bits(codec, MD_CTL1, BCKO_MASK, bcko);

	/* format type */
	data = 0;
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_LEFT_J:
		data = LEFT_J;
		break;
	case SND_SOC_DAIFMT_I2S:
		data = I2S;
		break;
	/* FIXME
	 * Please add RIGHT_J / DSP support here
	 */
	default:
		return -EINVAL;
		break;
	}
	snd_soc_update_bits(codec, MD_CTL1, DIF_MASK, data);

	return 0;
}

static int ak4642_dai_hw_params(struct snd_pcm_substream *substream,
				struct snd_pcm_hw_params *params,
				struct snd_soc_dai *dai)
{
	struct snd_soc_codec *codec = dai->codec;
	u8 rate;

	switch (params_rate(params)) {
	case 7350:
		rate = FS2;
		break;
	case 8000:
		rate = 0;
		break;
	case 11025:
		rate = FS2 | FS0;
		break;
	case 12000:
		rate = FS0;
		break;
	case 14700:
		rate = FS2 | FS1;
		break;
	case 16000:
		rate = FS1;
		break;
	case 22050:
		rate = FS2 | FS1 | FS0;
		break;
	case 24000:
		rate = FS1 | FS0;
		break;
	case 29400:
		rate = FS3 | FS2 | FS1;
		break;
	case 32000:
		rate = FS3 | FS1;
		break;
	case 44100:
		rate = FS3 | FS2 | FS1 | FS0;
		break;
	case 48000:
		rate = FS3 | FS1 | FS0;
		break;
	default:
		return -EINVAL;
		break;
	}
	snd_soc_update_bits(codec, MD_CTL2, FS_MASK, rate);

	return 0;
}

static int ak4642_set_bias_level(struct snd_soc_codec *codec,
				 enum snd_soc_bias_level level)
{
	switch (level) {
	case SND_SOC_BIAS_OFF:
		snd_soc_write(codec, PW_MGMT1, 0x00);
		break;
	default:
		snd_soc_update_bits(codec, PW_MGMT1, PMVCM, PMVCM);
		break;
	}
	codec->dapm.bias_level = level;

	return 0;
}

static const struct snd_soc_dai_ops ak4642_dai_ops = {
	.startup	= ak4642_dai_startup,
	.shutdown	= ak4642_dai_shutdown,
	.set_sysclk	= ak4642_dai_set_sysclk,
	.set_fmt	= ak4642_dai_set_fmt,
	.hw_params	= ak4642_dai_hw_params,
};

static struct snd_soc_dai_driver ak4642_dai = {
	.name = "ak4642-hifi",
	.playback = {
		.stream_name = "Playback",
		.channels_min = 1,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_48000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE },
	.capture = {
		.stream_name = "Capture",
		.channels_min = 1,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_48000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE },
	.ops = &ak4642_dai_ops,
	.symmetric_rates = 1,
};

static int ak4642_resume(struct snd_soc_codec *codec)
{
	snd_soc_cache_sync(codec);
	return 0;
}


static int ak4642_probe(struct snd_soc_codec *codec)
{
	int ret;

	ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C);
	if (ret < 0) {
		dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
		return ret;
	}

	snd_soc_add_codec_controls(codec, ak4642_snd_controls,
			     ARRAY_SIZE(ak4642_snd_controls));

	ak4642_set_bias_level(codec, SND_SOC_BIAS_STANDBY);

	return 0;
}

static int ak4642_remove(struct snd_soc_codec *codec)
{
	ak4642_set_bias_level(codec, SND_SOC_BIAS_OFF);
	return 0;
}

static struct snd_soc_codec_driver soc_codec_dev_ak4642 = {
	.probe			= ak4642_probe,
	.remove			= ak4642_remove,
	.resume			= ak4642_resume,
	.set_bias_level		= ak4642_set_bias_level,
	.reg_cache_default	= ak4642_reg,			/* ak4642 reg */
	.reg_cache_size		= ARRAY_SIZE(ak4642_reg),	/* ak4642 reg */
	.reg_word_size		= sizeof(u8),
	.dapm_widgets		= ak4642_dapm_widgets,
	.num_dapm_widgets	= ARRAY_SIZE(ak4642_dapm_widgets),
	.dapm_routes		= ak4642_intercon,
	.num_dapm_routes	= ARRAY_SIZE(ak4642_intercon),
};

static struct snd_soc_codec_driver soc_codec_dev_ak4648 = {
	.probe			= ak4642_probe,
	.remove			= ak4642_remove,
	.resume			= ak4642_resume,
	.set_bias_level		= ak4642_set_bias_level,
	.reg_cache_default	= ak4648_reg,			/* ak4648 reg */
	.reg_cache_size		= ARRAY_SIZE(ak4648_reg),	/* ak4648 reg */
	.reg_word_size		= sizeof(u8),
	.dapm_widgets		= ak4642_dapm_widgets,
	.num_dapm_widgets	= ARRAY_SIZE(ak4642_dapm_widgets),
	.dapm_routes		= ak4642_intercon,
	.num_dapm_routes	= ARRAY_SIZE(ak4642_intercon),
};

#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
static int ak4642_i2c_probe(struct i2c_client *i2c,
			    const struct i2c_device_id *id)
{
	return snd_soc_register_codec(&i2c->dev,
				(struct snd_soc_codec_driver *)id->driver_data,
				&ak4642_dai, 1);
}

static int ak4642_i2c_remove(struct i2c_client *client)
{
	snd_soc_unregister_codec(&client->dev);
	return 0;
}

static const struct i2c_device_id ak4642_i2c_id[] = {
	{ "ak4642", (kernel_ulong_t)&soc_codec_dev_ak4642 },
	{ "ak4643", (kernel_ulong_t)&soc_codec_dev_ak4642 },
	{ "ak4648", (kernel_ulong_t)&soc_codec_dev_ak4648 },
	{ }
};
MODULE_DEVICE_TABLE(i2c, ak4642_i2c_id);

static struct i2c_driver ak4642_i2c_driver = {
	.driver = {
		.name = "ak4642-codec",
		.owner = THIS_MODULE,
	},
	.probe		= ak4642_i2c_probe,
	.remove		= ak4642_i2c_remove,
	.id_table	= ak4642_i2c_id,
};
#endif

static int __init ak4642_modinit(void)
{
	int ret = 0;
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
	ret = i2c_add_driver(&ak4642_i2c_driver);
#endif
	return ret;

}
module_init(ak4642_modinit);

static void __exit ak4642_exit(void)
{
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
	i2c_del_driver(&ak4642_i2c_driver);
#endif

}
module_exit(ak4642_exit);

MODULE_DESCRIPTION("Soc AK4642 driver");
MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
a3a83d9a KM	1	/*
	2	* ak4642.c -- AK4642/AK4643 ALSA Soc Audio driver
	3	*
	4	* Copyright (C) 2009 Renesas Solutions Corp.
	5	* Kuninori Morimoto <morimoto.kuninori@renesas.com>
	6	*
	7	* Based on wm8731.c by Richard Purdie
	8	* Based on ak4535.c by Richard Purdie
	9	* Based on wm8753.c by Liam Girdwood
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	/* CAUTION
	17	*
	18	* This is very simple driver.
	19	* It can use headphone output / stereo input only
	20	*
20211391	21	* AK4642 is tested.
a3a83d9a	22	* AK4643 is tested.
a9317e8b	23	* AK4648 is tested.
a3a83d9a KM	24	*/
a3a83d9a KM	25
a3a83d9a	26	#include <linux/delay.h>
a3a83d9a	27	#include <linux/i2c.h>
5a0e3ad6	28	#include <linux/slab.h>
da155d5b	29	#include <linux/module.h>
ce6120cc	30	#include <sound/soc.h>
a3a83d9a	31	#include <sound/initval.h>
a300de3c	32	#include <sound/tlv.h>
a3a83d9a	33
a3a83d9a KM	34	#define PW_MGMT1 0x00
	35	#define PW_MGMT2 0x01
	36	#define SG_SL1 0x02
	37	#define SG_SL2 0x03
	38	#define MD_CTL1 0x04
	39	#define MD_CTL2 0x05
	40	#define TIMER 0x06
	41	#define ALC_CTL1 0x07
	42	#define ALC_CTL2 0x08
	43	#define L_IVC 0x09
	44	#define L_DVC 0x0a
	45	#define ALC_CTL3 0x0b
	46	#define R_IVC 0x0c
	47	#define R_DVC 0x0d
	48	#define MD_CTL3 0x0e
	49	#define MD_CTL4 0x0f
	50	#define PW_MGMT3 0x10
	51	#define DF_S 0x11
	52	#define FIL3_0 0x12
	53	#define FIL3_1 0x13
	54	#define FIL3_2 0x14
	55	#define FIL3_3 0x15
	56	#define EQ_0 0x16
	57	#define EQ_1 0x17
	58	#define EQ_2 0x18
	59	#define EQ_3 0x19
	60	#define EQ_4 0x1a
	61	#define EQ_5 0x1b
	62	#define FIL1_0 0x1c
	63	#define FIL1_1 0x1d
	64	#define FIL1_2 0x1e
	65	#define FIL1_3 0x1f
	66	#define PW_MGMT4 0x20
	67	#define MD_CTL5 0x21
	68	#define LO_MS 0x22
	69	#define HP_MS 0x23
	70	#define SPK_MS 0x24
	71
a3471239 KM	72	/* PW_MGMT1*/
	73	#define PMVCM (1 << 6) /* VCOM Power Management */
	74	#define PMMIN (1 << 5) /* MIN Input Power Management */
	75	#define PMDAC (1 << 2) /* DAC Power Management */
	76	#define PMADL (1 << 0) /* MIC Amp Lch and ADC Lch Power Management */
	77
0643ce8f KM	78	/* PW_MGMT2 */
	79	#define HPMTN (1 << 6)
	80	#define PMHPL (1 << 5)
	81	#define PMHPR (1 << 4)
	82	#define MS (1 << 3) /* master/slave select */
	83	#define MCKO (1 << 1)
	84	#define PMPLL (1 << 0)
	85
	86	#define PMHP_MASK (PMHPL \| PMHPR)
	87	#define PMHP PMHP_MASK
	88
a3471239 KM	89	/* PW_MGMT3 */
	90	#define PMADR (1 << 0) /* MIC L / ADC R Power Management */
	91
	92	/* SG_SL1 */
	93	#define MINS (1 << 6) /* Switch from MIN to Speaker */
	94	#define DACL (1 << 4) /* Switch from DAC to Stereo or Receiver */
	95	#define PMMP (1 << 2) /* MPWR pin Power Management */
	96	#define MGAIN0 (1 << 0) /* MIC amp gain*/
	97
	98	/* TIMER */
	99	#define ZTM(param) ((param & 0x3) << 4) /* ALC Zoro Crossing TimeOut */
	100	#define WTM(param) (((param & 0x4) << 4) \| ((param & 0x3) << 2))
	101
	102	/* ALC_CTL1 */
	103	#define ALC (1 << 5) /* ALC Enable */
	104	#define LMTH0 (1 << 0) /* ALC Limiter / Recovery Level */
	105
4b6316b4 KM	106	/* MD_CTL1 */
	107	#define PLL3 (1 << 7)
	108	#define PLL2 (1 << 6)
	109	#define PLL1 (1 << 5)
	110	#define PLL0 (1 << 4)
	111	#define PLL_MASK (PLL3 \| PLL2 \| PLL1 \| PLL0)
	112
0643ce8f KM	113	#define BCKO_MASK (1 << 3)
	114	#define BCKO_64 BCKO_MASK
	115
cb9c130a KM	116	#define DIF_MASK (3 << 0)
	117	#define DSP (0 << 0)
	118	#define RIGHT_J (1 << 0)
	119	#define LEFT_J (2 << 0)
	120	#define I2S (3 << 0)
	121
1ad747ca KM	122	/* MD_CTL2 */
	123	#define FS0 (1 << 0)
	124	#define FS1 (1 << 1)
	125	#define FS2 (1 << 2)
	126	#define FS3 (1 << 5)
	127	#define FS_MASK (FS0 \| FS1 \| FS2 \| FS3)
	128
a3471239 KM	129	/* MD_CTL3 */
	130	#define BST1 (1 << 3)
	131
	132	/* MD_CTL4 */
	133	#define DACH (1 << 0)
a3a83d9a	134
a300de3c KM	135	/*
	136	* Playback Volume (table 39)
	137	*
	138	* max : 0x00 : +12.0 dB
	139	* ( 0.5 dB step )
	140	* min : 0xFE : -115.0 dB
	141	* mute: 0xFF
	142	*/
1f99e44c	143	static const DECLARE_TLV_DB_SCALE(out_tlv, -11550, 50, 1);
a300de3c KM	144
	145	static const struct snd_kcontrol_new ak4642_snd_controls[] = {
	146
	147	SOC_DOUBLE_R_TLV("Digital Playback Volume", L_DVC, R_DVC,
	148	0, 0xFF, 1, out_tlv),
	149	};
	150
e555cf36 KM	151	static const struct snd_kcontrol_new ak4642_headphone_control =
e555cf36 KM	152	SOC_DAPM_SINGLE("Switch", PW_MGMT2, 6, 1, 0);
24747dae	153
e8c83dbf KM	154	static const struct snd_kcontrol_new ak4642_lout_mixer_controls[] = {
	155	SOC_DAPM_SINGLE("DACL", SG_SL1, 4, 1, 0),
	156	};
	157
24747dae KM	158	static const struct snd_soc_dapm_widget ak4642_dapm_widgets[] = {
	159
	160	/* Outputs */
	161	SND_SOC_DAPM_OUTPUT("HPOUTL"),
	162	SND_SOC_DAPM_OUTPUT("HPOUTR"),
e8c83dbf	163	SND_SOC_DAPM_OUTPUT("LINEOUT"),
24747dae	164
e555cf36 KM	165	SND_SOC_DAPM_PGA("HPL Out", PW_MGMT2, 5, 0, NULL, 0),
	166	SND_SOC_DAPM_PGA("HPR Out", PW_MGMT2, 4, 0, NULL, 0),
	167	SND_SOC_DAPM_SWITCH("Headphone Enable", SND_SOC_NOPM, 0, 0,
	168	&ak4642_headphone_control),
24747dae	169
e555cf36	170	SND_SOC_DAPM_PGA("DACH", MD_CTL4, 0, 0, NULL, 0),
24747dae	171
e8c83dbf KM	172	SND_SOC_DAPM_MIXER("LINEOUT Mixer", PW_MGMT1, 3, 0,
	173	&ak4642_lout_mixer_controls[0],
	174	ARRAY_SIZE(ak4642_lout_mixer_controls)),
	175
24747dae KM	176	/* DAC */
	177	SND_SOC_DAPM_DAC("DAC", "HiFi Playback", PW_MGMT1, 2, 0),
	178	};
	179
	180	static const struct snd_soc_dapm_route ak4642_intercon[] = {
	181
	182	/* Outputs */
e555cf36 KM	183	{"HPOUTL", NULL, "HPL Out"},
e555cf36 KM	184	{"HPOUTR", NULL, "HPR Out"},
e8c83dbf	185	{"LINEOUT", NULL, "LINEOUT Mixer"},
24747dae	186
e555cf36 KM	187	{"HPL Out", NULL, "Headphone Enable"},
	188	{"HPR Out", NULL, "Headphone Enable"},
	189
	190	{"Headphone Enable", "Switch", "DACH"},
	191
	192	{"DACH", NULL, "DAC"},
	193
e8c83dbf	194	{"LINEOUT Mixer", "DACL", "DAC"},
24747dae	195	};
a300de3c	196
a3a83d9a KM	197	/*
	198	* ak4642 register cache
	199	*/
a9317e8b	200	static const u8 ak4642_reg[] = {
19b115e5 KM	201	0x00, 0x00, 0x01, 0x00,
	202	0x02, 0x00, 0x00, 0x00,
	203	0xe1, 0xe1, 0x18, 0x00,
	204	0xe1, 0x18, 0x11, 0x08,
	205	0x00, 0x00, 0x00, 0x00,
	206	0x00, 0x00, 0x00, 0x00,
	207	0x00, 0x00, 0x00, 0x00,
	208	0x00, 0x00, 0x00, 0x00,
	209	0x00, 0x00, 0x00, 0x00,
	210	0x00,
a3a83d9a KM	211	};
a3a83d9a KM	212
a9317e8b KM	213	static const u8 ak4648_reg[] = {
	214	0x00, 0x00, 0x01, 0x00,
	215	0x02, 0x00, 0x00, 0x00,
	216	0xe1, 0xe1, 0x18, 0x00,
	217	0xe1, 0x18, 0x11, 0xb8,
	218	0x00, 0x00, 0x00, 0x00,
	219	0x00, 0x00, 0x00, 0x00,
	220	0x00, 0x00, 0x00, 0x00,
	221	0x00, 0x00, 0x00, 0x00,
	222	0x00, 0x00, 0x00, 0x00,
	223	0x00, 0x88, 0x88, 0x08,
	224	};
	225
a3a83d9a KM	226	static int ak4642_dai_startup(struct snd_pcm_substream *substream,
	227	struct snd_soc_dai *dai)
	228	{
	229	int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
	230	struct snd_soc_codec *codec = dai->codec;
	231
	232	if (is_play) {
	233	/*
	234	* start headphone output
	235	*
	236	* PLL, Master Mode
	237	* Audio I/F Format :MSB justified (ADC & DAC)
a3a83d9a KM	238	* Bass Boost Level : Middle
	239	*
	240	* This operation came from example code of
	241	* "ASAHI KASEI AK4642" (japanese) manual p97.
a3a83d9a	242	*/
b91470bb AL	243	snd_soc_write(codec, L_IVC, 0x91); /* volume */
b91470bb AL	244	snd_soc_write(codec, R_IVC, 0x91); /* volume */
a3a83d9a KM	245	} else {
	246	/*
	247	* start stereo input
	248	*
	249	* PLL Master Mode
	250	* Audio I/F Format:MSB justified (ADC & DAC)
a3a83d9a KM	251	* Pre MIC AMP:+20dB
	252	* MIC Power On
	253	* ALC setting:Refer to Table 35
	254	* ALC bit=“1”
	255	*
	256	* This operation came from example code of
	257	* "ASAHI KASEI AK4642" (japanese) manual p94.
	258	*/
b91470bb AL	259	snd_soc_write(codec, SG_SL1, PMMP \| MGAIN0);
	260	snd_soc_write(codec, TIMER, ZTM(0x3) \| WTM(0x3));
	261	snd_soc_write(codec, ALC_CTL1, ALC \| LMTH0);
ed2dd7da	262	snd_soc_update_bits(codec, PW_MGMT1, PMADL, PMADL);
a3471239	263	snd_soc_update_bits(codec, PW_MGMT3, PMADR, PMADR);
a3a83d9a KM	264	}
	265
	266	return 0;
	267	}
	268
	269	static void ak4642_dai_shutdown(struct snd_pcm_substream *substream,
	270	struct snd_soc_dai *dai)
	271	{
	272	int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
	273	struct snd_soc_codec *codec = dai->codec;
	274
	275	if (is_play) {
a3a83d9a KM	276	} else {
a3a83d9a KM	277	/* stop stereo input */
a3471239 KM	278	snd_soc_update_bits(codec, PW_MGMT1, PMADL, 0);
	279	snd_soc_update_bits(codec, PW_MGMT3, PMADR, 0);
	280	snd_soc_update_bits(codec, ALC_CTL1, ALC, 0);
a3a83d9a KM	281	}
	282	}
	283
	284	static int ak4642_dai_set_sysclk(struct snd_soc_dai *codec_dai,
	285	int clk_id, unsigned int freq, int dir)
	286	{
	287	struct snd_soc_codec *codec = codec_dai->codec;
4b6316b4 KM	288	u8 pll;
	289
	290	switch (freq) {
	291	case 11289600:
	292	pll = PLL2;
	293	break;
	294	case 12288000:
	295	pll = PLL2 \| PLL0;
	296	break;
	297	case 12000000:
	298	pll = PLL2 \| PLL1;
	299	break;
	300	case 24000000:
	301	pll = PLL2 \| PLL1 \| PLL0;
	302	break;
	303	case 13500000:
	304	pll = PLL3 \| PLL2;
	305	break;
	306	case 27000000:
	307	pll = PLL3 \| PLL2 \| PLL0;
	308	break;
	309	default:
	310	return -EINVAL;
	311	}
	312	snd_soc_update_bits(codec, MD_CTL1, PLL_MASK, pll);
a3a83d9a	313
a3a83d9a KM	314	return 0;
	315	}
	316
0643ce8f KM	317	static int ak4642_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
	318	{
	319	struct snd_soc_codec *codec = dai->codec;
	320	u8 data;
	321	u8 bcko;
	322
	323	data = MCKO \| PMPLL; /* use MCKO */
	324	bcko = 0;
	325
	326	/* set master/slave audio interface */
	327	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	328	case SND_SOC_DAIFMT_CBM_CFM:
	329	data \|= MS;
	330	bcko = BCKO_64;
	331	break;
	332	case SND_SOC_DAIFMT_CBS_CFS:
	333	break;
	334	default:
	335	return -EINVAL;
	336	}
bd7fdbca	337	snd_soc_update_bits(codec, PW_MGMT2, MS \| MCKO \| PMPLL, data);
0643ce8f KM	338	snd_soc_update_bits(codec, MD_CTL1, BCKO_MASK, bcko);
0643ce8f KM	339
cb9c130a KM	340	/* format type */
	341	data = 0;
	342	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	343	case SND_SOC_DAIFMT_LEFT_J:
	344	data = LEFT_J;
	345	break;
	346	case SND_SOC_DAIFMT_I2S:
	347	data = I2S;
	348	break;
	349	/* FIXME
	350	* Please add RIGHT_J / DSP support here
	351	*/
	352	default:
	353	return -EINVAL;
	354	break;
	355	}
	356	snd_soc_update_bits(codec, MD_CTL1, DIF_MASK, data);
	357
0643ce8f KM	358	return 0;
	359	}
	360
1ad747ca KM	361	static int ak4642_dai_hw_params(struct snd_pcm_substream *substream,
	362	struct snd_pcm_hw_params *params,
	363	struct snd_soc_dai *dai)
	364	{
	365	struct snd_soc_codec *codec = dai->codec;
	366	u8 rate;
	367
	368	switch (params_rate(params)) {
	369	case 7350:
	370	rate = FS2;
	371	break;
	372	case 8000:
	373	rate = 0;
	374	break;
	375	case 11025:
	376	rate = FS2 \| FS0;
	377	break;
	378	case 12000:
	379	rate = FS0;
	380	break;
	381	case 14700:
	382	rate = FS2 \| FS1;
	383	break;
	384	case 16000:
	385	rate = FS1;
	386	break;
	387	case 22050:
	388	rate = FS2 \| FS1 \| FS0;
	389	break;
	390	case 24000:
	391	rate = FS1 \| FS0;
	392	break;
	393	case 29400:
	394	rate = FS3 \| FS2 \| FS1;
	395	break;
	396	case 32000:
	397	rate = FS3 \| FS1;
	398	break;
	399	case 44100:
	400	rate = FS3 \| FS2 \| FS1 \| FS0;
	401	break;
	402	case 48000:
	403	rate = FS3 \| FS1 \| FS0;
	404	break;
	405	default:
	406	return -EINVAL;
	407	break;
	408	}
	409	snd_soc_update_bits(codec, MD_CTL2, FS_MASK, rate);
a3a83d9a	410
a3a83d9a KM	411	return 0;
	412	}
	413
ed2dd7da KM	414	static int ak4642_set_bias_level(struct snd_soc_codec *codec,
	415	enum snd_soc_bias_level level)
	416	{
	417	switch (level) {
	418	case SND_SOC_BIAS_OFF:
	419	snd_soc_write(codec, PW_MGMT1, 0x00);
	420	break;
	421	default:
	422	snd_soc_update_bits(codec, PW_MGMT1, PMVCM, PMVCM);
	423	break;
	424	}
	425	codec->dapm.bias_level = level;
	426
	427	return 0;
	428	}
	429
85e7652d	430	static const struct snd_soc_dai_ops ak4642_dai_ops = {
a3a83d9a KM	431	.startup = ak4642_dai_startup,
	432	.shutdown = ak4642_dai_shutdown,
	433	.set_sysclk = ak4642_dai_set_sysclk,
0643ce8f	434	.set_fmt = ak4642_dai_set_fmt,
1ad747ca	435	.hw_params = ak4642_dai_hw_params,
a3a83d9a KM	436	};
a3a83d9a KM	437
f0fba2ad LG	438	static struct snd_soc_dai_driver ak4642_dai = {
f0fba2ad LG	439	.name = "ak4642-hifi",
a3a83d9a KM	440	.playback = {
	441	.stream_name = "Playback",
	442	.channels_min = 1,
	443	.channels_max = 2,
	444	.rates = SNDRV_PCM_RATE_8000_48000,
	445	.formats = SNDRV_PCM_FMTBIT_S16_LE },
	446	.capture = {
	447	.stream_name = "Capture",
	448	.channels_min = 1,
	449	.channels_max = 2,
	450	.rates = SNDRV_PCM_RATE_8000_48000,
	451	.formats = SNDRV_PCM_FMTBIT_S16_LE },
	452	.ops = &ak4642_dai_ops,
1ad747ca	453	.symmetric_rates = 1,
a3a83d9a	454	};
a3a83d9a	455
f0fba2ad	456	static int ak4642_resume(struct snd_soc_codec *codec)
a3a83d9a	457	{
b91470bb	458	snd_soc_cache_sync(codec);
a3a83d9a KM	459	return 0;
	460	}
	461
f0fba2ad LG	462
f0fba2ad LG	463	static int ak4642_probe(struct snd_soc_codec *codec)
a3a83d9a	464	{
b91470bb	465	int ret;
a3a83d9a	466
2f391251	467	ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C);
b91470bb AL	468	if (ret < 0) {
	469	dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
	470	return ret;
	471	}
a3a83d9a	472
022658be	473	snd_soc_add_codec_controls(codec, ak4642_snd_controls,
73bb379f	474	ARRAY_SIZE(ak4642_snd_controls));
a3a83d9a	475
ed2dd7da KM	476	ak4642_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
	477
	478	return 0;
	479	}
	480
	481	static int ak4642_remove(struct snd_soc_codec *codec)
	482	{
	483	ak4642_set_bias_level(codec, SND_SOC_BIAS_OFF);
f0fba2ad	484	return 0;
a3a83d9a KM	485	}
a3a83d9a KM	486
f0fba2ad	487	static struct snd_soc_codec_driver soc_codec_dev_ak4642 = {
0ce75aa4	488	.probe = ak4642_probe,
ed2dd7da	489	.remove = ak4642_remove,
0ce75aa4	490	.resume = ak4642_resume,
ed2dd7da	491	.set_bias_level = ak4642_set_bias_level,
a9317e8b KM	492	.reg_cache_default = ak4642_reg, /* ak4642 reg */
	493	.reg_cache_size = ARRAY_SIZE(ak4642_reg), /* ak4642 reg */
	494	.reg_word_size = sizeof(u8),
	495	.dapm_widgets = ak4642_dapm_widgets,
	496	.num_dapm_widgets = ARRAY_SIZE(ak4642_dapm_widgets),
	497	.dapm_routes = ak4642_intercon,
	498	.num_dapm_routes = ARRAY_SIZE(ak4642_intercon),
	499	};
	500
	501	static struct snd_soc_codec_driver soc_codec_dev_ak4648 = {
	502	.probe = ak4642_probe,
	503	.remove = ak4642_remove,
	504	.resume = ak4642_resume,
	505	.set_bias_level = ak4642_set_bias_level,
	506	.reg_cache_default = ak4648_reg, /* ak4648 reg */
	507	.reg_cache_size = ARRAY_SIZE(ak4648_reg), /* ak4648 reg */
0ce75aa4	508	.reg_word_size = sizeof(u8),
24747dae KM	509	.dapm_widgets = ak4642_dapm_widgets,
	510	.num_dapm_widgets = ARRAY_SIZE(ak4642_dapm_widgets),
	511	.dapm_routes = ak4642_intercon,
	512	.num_dapm_routes = ARRAY_SIZE(ak4642_intercon),
f0fba2ad LG	513	};
f0fba2ad LG	514
a3a83d9a	515	#if defined(CONFIG_I2C) \|\| defined(CONFIG_I2C_MODULE)
7a79e94e BP	516	static int ak4642_i2c_probe(struct i2c_client *i2c,
7a79e94e BP	517	const struct i2c_device_id *id)
a3a83d9a	518	{
2f391251	519	return snd_soc_register_codec(&i2c->dev,
a9317e8b KM	520	(struct snd_soc_codec_driver *)id->driver_data,
a9317e8b KM	521	&ak4642_dai, 1);
a3a83d9a KM	522	}
a3a83d9a KM	523
7a79e94e	524	static int ak4642_i2c_remove(struct i2c_client *client)
a3a83d9a	525	{
f0fba2ad	526	snd_soc_unregister_codec(&client->dev);
a3a83d9a KM	527	return 0;
	528	}
	529
	530	static const struct i2c_device_id ak4642_i2c_id[] = {
a9317e8b KM	531	{ "ak4642", (kernel_ulong_t)&soc_codec_dev_ak4642 },
	532	{ "ak4643", (kernel_ulong_t)&soc_codec_dev_ak4642 },
	533	{ "ak4648", (kernel_ulong_t)&soc_codec_dev_ak4648 },
a3a83d9a KM	534	{ }
	535	};
	536	MODULE_DEVICE_TABLE(i2c, ak4642_i2c_id);
	537
	538	static struct i2c_driver ak4642_i2c_driver = {
	539	.driver = {
f0fba2ad	540	.name = "ak4642-codec",
a3a83d9a KM	541	.owner = THIS_MODULE,
a3a83d9a KM	542	},
0ce75aa4	543	.probe = ak4642_i2c_probe,
7a79e94e	544	.remove = ak4642_i2c_remove,
0ce75aa4	545	.id_table = ak4642_i2c_id,
a3a83d9a	546	};
a3a83d9a KM	547	#endif
a3a83d9a KM	548
a3a83d9a KM	549	static int __init ak4642_modinit(void)
a3a83d9a KM	550	{
1cf86f6f	551	int ret = 0;
a3a83d9a KM	552	#if defined(CONFIG_I2C) \|\| defined(CONFIG_I2C_MODULE)
	553	ret = i2c_add_driver(&ak4642_i2c_driver);
	554	#endif
	555	return ret;
	556
	557	}
	558	module_init(ak4642_modinit);
	559
	560	static void __exit ak4642_exit(void)
	561	{
	562	#if defined(CONFIG_I2C) \|\| defined(CONFIG_I2C_MODULE)
	563	i2c_del_driver(&ak4642_i2c_driver);
	564	#endif
	565
	566	}
	567	module_exit(ak4642_exit);
	568
	569	MODULE_DESCRIPTION("Soc AK4642 driver");
	570	MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
	571	MODULE_LICENSE("GPL");