Commit | Line | Data |
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a3a83d9a KM |
1 | /* |
2 | * ak4642.c -- AK4642/AK4643 ALSA Soc Audio driver | |
3 | * | |
4 | * Copyright (C) 2009 Renesas Solutions Corp. | |
5 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
6 | * | |
7 | * Based on wm8731.c by Richard Purdie | |
8 | * Based on ak4535.c by Richard Purdie | |
9 | * Based on wm8753.c by Liam Girdwood | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | /* ** CAUTION ** | |
17 | * | |
18 | * This is very simple driver. | |
19 | * It can use headphone output / stereo input only | |
20 | * | |
20211391 | 21 | * AK4642 is tested. |
a3a83d9a | 22 | * AK4643 is tested. |
a9317e8b | 23 | * AK4648 is tested. |
a3a83d9a KM |
24 | */ |
25 | ||
171a0138 KM |
26 | #include <linux/clk.h> |
27 | #include <linux/clk-provider.h> | |
a3a83d9a | 28 | #include <linux/delay.h> |
a3a83d9a | 29 | #include <linux/i2c.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
bbf1453e | 31 | #include <linux/of_device.h> |
da155d5b | 32 | #include <linux/module.h> |
4574cd94 | 33 | #include <linux/regmap.h> |
ce6120cc | 34 | #include <sound/soc.h> |
a3a83d9a | 35 | #include <sound/initval.h> |
a300de3c | 36 | #include <sound/tlv.h> |
a3a83d9a | 37 | |
a3a83d9a KM |
38 | #define PW_MGMT1 0x00 |
39 | #define PW_MGMT2 0x01 | |
40 | #define SG_SL1 0x02 | |
41 | #define SG_SL2 0x03 | |
42 | #define MD_CTL1 0x04 | |
43 | #define MD_CTL2 0x05 | |
44 | #define TIMER 0x06 | |
45 | #define ALC_CTL1 0x07 | |
46 | #define ALC_CTL2 0x08 | |
47 | #define L_IVC 0x09 | |
48 | #define L_DVC 0x0a | |
49 | #define ALC_CTL3 0x0b | |
50 | #define R_IVC 0x0c | |
51 | #define R_DVC 0x0d | |
52 | #define MD_CTL3 0x0e | |
53 | #define MD_CTL4 0x0f | |
54 | #define PW_MGMT3 0x10 | |
55 | #define DF_S 0x11 | |
56 | #define FIL3_0 0x12 | |
57 | #define FIL3_1 0x13 | |
58 | #define FIL3_2 0x14 | |
59 | #define FIL3_3 0x15 | |
60 | #define EQ_0 0x16 | |
61 | #define EQ_1 0x17 | |
62 | #define EQ_2 0x18 | |
63 | #define EQ_3 0x19 | |
64 | #define EQ_4 0x1a | |
65 | #define EQ_5 0x1b | |
66 | #define FIL1_0 0x1c | |
67 | #define FIL1_1 0x1d | |
68 | #define FIL1_2 0x1e | |
f8ea6ceb | 69 | #define FIL1_3 0x1f /* The maximum valid register for ak4642 */ |
a3a83d9a KM |
70 | #define PW_MGMT4 0x20 |
71 | #define MD_CTL5 0x21 | |
72 | #define LO_MS 0x22 | |
73 | #define HP_MS 0x23 | |
f8ea6ceb AL |
74 | #define SPK_MS 0x24 /* The maximum valid register for ak4643 */ |
75 | #define EQ_FBEQAB 0x25 | |
76 | #define EQ_FBEQCD 0x26 | |
77 | #define EQ_FBEQE 0x27 /* The maximum valid register for ak4648 */ | |
a3a83d9a | 78 | |
a3471239 KM |
79 | /* PW_MGMT1*/ |
80 | #define PMVCM (1 << 6) /* VCOM Power Management */ | |
81 | #define PMMIN (1 << 5) /* MIN Input Power Management */ | |
82 | #define PMDAC (1 << 2) /* DAC Power Management */ | |
83 | #define PMADL (1 << 0) /* MIC Amp Lch and ADC Lch Power Management */ | |
84 | ||
0643ce8f KM |
85 | /* PW_MGMT2 */ |
86 | #define HPMTN (1 << 6) | |
87 | #define PMHPL (1 << 5) | |
88 | #define PMHPR (1 << 4) | |
89 | #define MS (1 << 3) /* master/slave select */ | |
90 | #define MCKO (1 << 1) | |
91 | #define PMPLL (1 << 0) | |
92 | ||
93 | #define PMHP_MASK (PMHPL | PMHPR) | |
94 | #define PMHP PMHP_MASK | |
95 | ||
a3471239 KM |
96 | /* PW_MGMT3 */ |
97 | #define PMADR (1 << 0) /* MIC L / ADC R Power Management */ | |
98 | ||
99 | /* SG_SL1 */ | |
100 | #define MINS (1 << 6) /* Switch from MIN to Speaker */ | |
101 | #define DACL (1 << 4) /* Switch from DAC to Stereo or Receiver */ | |
102 | #define PMMP (1 << 2) /* MPWR pin Power Management */ | |
103 | #define MGAIN0 (1 << 0) /* MIC amp gain*/ | |
104 | ||
39c26180 TK |
105 | /* SG_SL2 */ |
106 | #define LOPS (1 << 6) /* Stero Line-out Power Save Mode */ | |
107 | ||
a3471239 | 108 | /* TIMER */ |
da731845 | 109 | #define ZTM(param) ((param & 0x3) << 4) /* ALC Zero Crossing TimeOut */ |
a3471239 KM |
110 | #define WTM(param) (((param & 0x4) << 4) | ((param & 0x3) << 2)) |
111 | ||
112 | /* ALC_CTL1 */ | |
113 | #define ALC (1 << 5) /* ALC Enable */ | |
114 | #define LMTH0 (1 << 0) /* ALC Limiter / Recovery Level */ | |
115 | ||
4b6316b4 KM |
116 | /* MD_CTL1 */ |
117 | #define PLL3 (1 << 7) | |
118 | #define PLL2 (1 << 6) | |
119 | #define PLL1 (1 << 5) | |
120 | #define PLL0 (1 << 4) | |
121 | #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0) | |
122 | ||
0643ce8f KM |
123 | #define BCKO_MASK (1 << 3) |
124 | #define BCKO_64 BCKO_MASK | |
125 | ||
cb9c130a KM |
126 | #define DIF_MASK (3 << 0) |
127 | #define DSP (0 << 0) | |
128 | #define RIGHT_J (1 << 0) | |
129 | #define LEFT_J (2 << 0) | |
130 | #define I2S (3 << 0) | |
131 | ||
1ad747ca | 132 | /* MD_CTL2 */ |
544637bf KM |
133 | #define FSs(val) (((val & 0x7) << 0) | ((val & 0x8) << 2)) |
134 | #define PSs(val) ((val & 0x3) << 6) | |
1ad747ca | 135 | |
a3471239 KM |
136 | /* MD_CTL3 */ |
137 | #define BST1 (1 << 3) | |
138 | ||
139 | /* MD_CTL4 */ | |
140 | #define DACH (1 << 0) | |
a3a83d9a | 141 | |
d815c703 SH |
142 | struct ak4642_drvdata { |
143 | const struct regmap_config *regmap_config; | |
5cd15e29 | 144 | int extended_frequencies; |
d815c703 SH |
145 | }; |
146 | ||
147 | struct ak4642_priv { | |
148 | const struct ak4642_drvdata *drvdata; | |
171a0138 | 149 | struct clk *mcko; |
d815c703 SH |
150 | }; |
151 | ||
a300de3c KM |
152 | /* |
153 | * Playback Volume (table 39) | |
154 | * | |
155 | * max : 0x00 : +12.0 dB | |
156 | * ( 0.5 dB step ) | |
157 | * min : 0xFE : -115.0 dB | |
158 | * mute: 0xFF | |
159 | */ | |
1f99e44c | 160 | static const DECLARE_TLV_DB_SCALE(out_tlv, -11550, 50, 1); |
a300de3c KM |
161 | |
162 | static const struct snd_kcontrol_new ak4642_snd_controls[] = { | |
163 | ||
164 | SOC_DOUBLE_R_TLV("Digital Playback Volume", L_DVC, R_DVC, | |
165 | 0, 0xFF, 1, out_tlv), | |
370f83a1 SH |
166 | SOC_SINGLE("ALC Capture Switch", ALC_CTL1, 5, 1, 0), |
167 | SOC_SINGLE("ALC Capture ZC Switch", ALC_CTL1, 4, 1, 1), | |
a300de3c KM |
168 | }; |
169 | ||
e555cf36 KM |
170 | static const struct snd_kcontrol_new ak4642_headphone_control = |
171 | SOC_DAPM_SINGLE("Switch", PW_MGMT2, 6, 1, 0); | |
24747dae | 172 | |
e8c83dbf KM |
173 | static const struct snd_kcontrol_new ak4642_lout_mixer_controls[] = { |
174 | SOC_DAPM_SINGLE("DACL", SG_SL1, 4, 1, 0), | |
175 | }; | |
176 | ||
39c26180 TK |
177 | /* event handlers */ |
178 | static int ak4642_lout_event(struct snd_soc_dapm_widget *w, | |
179 | struct snd_kcontrol *kcontrol, int event) | |
180 | { | |
181 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); | |
182 | ||
183 | switch (event) { | |
184 | case SND_SOC_DAPM_PRE_PMD: | |
185 | case SND_SOC_DAPM_PRE_PMU: | |
186 | /* Power save mode ON */ | |
187 | snd_soc_update_bits(codec, SG_SL2, LOPS, LOPS); | |
188 | break; | |
189 | case SND_SOC_DAPM_POST_PMU: | |
190 | case SND_SOC_DAPM_POST_PMD: | |
191 | /* Power save mode OFF */ | |
192 | mdelay(300); | |
193 | snd_soc_update_bits(codec, SG_SL2, LOPS, 0); | |
194 | break; | |
195 | } | |
196 | ||
197 | return 0; | |
198 | } | |
199 | ||
24747dae KM |
200 | static const struct snd_soc_dapm_widget ak4642_dapm_widgets[] = { |
201 | ||
202 | /* Outputs */ | |
203 | SND_SOC_DAPM_OUTPUT("HPOUTL"), | |
204 | SND_SOC_DAPM_OUTPUT("HPOUTR"), | |
e8c83dbf | 205 | SND_SOC_DAPM_OUTPUT("LINEOUT"), |
24747dae | 206 | |
e555cf36 KM |
207 | SND_SOC_DAPM_PGA("HPL Out", PW_MGMT2, 5, 0, NULL, 0), |
208 | SND_SOC_DAPM_PGA("HPR Out", PW_MGMT2, 4, 0, NULL, 0), | |
209 | SND_SOC_DAPM_SWITCH("Headphone Enable", SND_SOC_NOPM, 0, 0, | |
210 | &ak4642_headphone_control), | |
24747dae | 211 | |
e555cf36 | 212 | SND_SOC_DAPM_PGA("DACH", MD_CTL4, 0, 0, NULL, 0), |
24747dae | 213 | |
39c26180 | 214 | SND_SOC_DAPM_MIXER_E("LINEOUT Mixer", PW_MGMT1, 3, 0, |
e8c83dbf | 215 | &ak4642_lout_mixer_controls[0], |
39c26180 TK |
216 | ARRAY_SIZE(ak4642_lout_mixer_controls), |
217 | ak4642_lout_event, | |
218 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | | |
219 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), | |
e8c83dbf | 220 | |
24747dae | 221 | /* DAC */ |
379c4b05 | 222 | SND_SOC_DAPM_DAC("DAC", NULL, PW_MGMT1, 2, 0), |
24747dae KM |
223 | }; |
224 | ||
225 | static const struct snd_soc_dapm_route ak4642_intercon[] = { | |
226 | ||
227 | /* Outputs */ | |
e555cf36 KM |
228 | {"HPOUTL", NULL, "HPL Out"}, |
229 | {"HPOUTR", NULL, "HPR Out"}, | |
e8c83dbf | 230 | {"LINEOUT", NULL, "LINEOUT Mixer"}, |
24747dae | 231 | |
e555cf36 KM |
232 | {"HPL Out", NULL, "Headphone Enable"}, |
233 | {"HPR Out", NULL, "Headphone Enable"}, | |
234 | ||
235 | {"Headphone Enable", "Switch", "DACH"}, | |
236 | ||
237 | {"DACH", NULL, "DAC"}, | |
238 | ||
e8c83dbf | 239 | {"LINEOUT Mixer", "DACL", "DAC"}, |
379c4b05 KM |
240 | |
241 | { "DAC", NULL, "Playback" }, | |
24747dae | 242 | }; |
a300de3c | 243 | |
a3a83d9a KM |
244 | /* |
245 | * ak4642 register cache | |
246 | */ | |
f8ea6ceb | 247 | static const struct reg_default ak4643_reg[] = { |
4574cd94 MB |
248 | { 0, 0x00 }, { 1, 0x00 }, { 2, 0x01 }, { 3, 0x00 }, |
249 | { 4, 0x02 }, { 5, 0x00 }, { 6, 0x00 }, { 7, 0x00 }, | |
250 | { 8, 0xe1 }, { 9, 0xe1 }, { 10, 0x18 }, { 11, 0x00 }, | |
251 | { 12, 0xe1 }, { 13, 0x18 }, { 14, 0x11 }, { 15, 0x08 }, | |
252 | { 16, 0x00 }, { 17, 0x00 }, { 18, 0x00 }, { 19, 0x00 }, | |
253 | { 20, 0x00 }, { 21, 0x00 }, { 22, 0x00 }, { 23, 0x00 }, | |
254 | { 24, 0x00 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0x00 }, | |
255 | { 28, 0x00 }, { 29, 0x00 }, { 30, 0x00 }, { 31, 0x00 }, | |
256 | { 32, 0x00 }, { 33, 0x00 }, { 34, 0x00 }, { 35, 0x00 }, | |
257 | { 36, 0x00 }, | |
a3a83d9a KM |
258 | }; |
259 | ||
f8ea6ceb AL |
260 | /* The default settings for 0x0 ~ 0x1f registers are the same for ak4642 |
261 | and ak4643. So we reuse the ak4643 reg_default for ak4642. | |
262 | The valid registers for ak4642 are 0x0 ~ 0x1f which is a subset of ak4643, | |
263 | so define NUM_AK4642_REG_DEFAULTS for ak4642. | |
264 | */ | |
265 | #define ak4642_reg ak4643_reg | |
266 | #define NUM_AK4642_REG_DEFAULTS (FIL1_3 + 1) | |
267 | ||
4574cd94 MB |
268 | static const struct reg_default ak4648_reg[] = { |
269 | { 0, 0x00 }, { 1, 0x00 }, { 2, 0x01 }, { 3, 0x00 }, | |
270 | { 4, 0x02 }, { 5, 0x00 }, { 6, 0x00 }, { 7, 0x00 }, | |
271 | { 8, 0xe1 }, { 9, 0xe1 }, { 10, 0x18 }, { 11, 0x00 }, | |
272 | { 12, 0xe1 }, { 13, 0x18 }, { 14, 0x11 }, { 15, 0xb8 }, | |
273 | { 16, 0x00 }, { 17, 0x00 }, { 18, 0x00 }, { 19, 0x00 }, | |
274 | { 20, 0x00 }, { 21, 0x00 }, { 22, 0x00 }, { 23, 0x00 }, | |
275 | { 24, 0x00 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0x00 }, | |
276 | { 28, 0x00 }, { 29, 0x00 }, { 30, 0x00 }, { 31, 0x00 }, | |
277 | { 32, 0x00 }, { 33, 0x00 }, { 34, 0x00 }, { 35, 0x00 }, | |
278 | { 36, 0x00 }, { 37, 0x88 }, { 38, 0x88 }, { 39, 0x08 }, | |
a9317e8b KM |
279 | }; |
280 | ||
a3a83d9a KM |
281 | static int ak4642_dai_startup(struct snd_pcm_substream *substream, |
282 | struct snd_soc_dai *dai) | |
283 | { | |
284 | int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; | |
285 | struct snd_soc_codec *codec = dai->codec; | |
286 | ||
287 | if (is_play) { | |
288 | /* | |
289 | * start headphone output | |
290 | * | |
291 | * PLL, Master Mode | |
292 | * Audio I/F Format :MSB justified (ADC & DAC) | |
a3a83d9a KM |
293 | * Bass Boost Level : Middle |
294 | * | |
295 | * This operation came from example code of | |
296 | * "ASAHI KASEI AK4642" (japanese) manual p97. | |
a3a83d9a | 297 | */ |
b91470bb AL |
298 | snd_soc_write(codec, L_IVC, 0x91); /* volume */ |
299 | snd_soc_write(codec, R_IVC, 0x91); /* volume */ | |
a3a83d9a KM |
300 | } else { |
301 | /* | |
302 | * start stereo input | |
303 | * | |
304 | * PLL Master Mode | |
305 | * Audio I/F Format:MSB justified (ADC & DAC) | |
a3a83d9a KM |
306 | * Pre MIC AMP:+20dB |
307 | * MIC Power On | |
308 | * ALC setting:Refer to Table 35 | |
309 | * ALC bit=“1” | |
310 | * | |
311 | * This operation came from example code of | |
312 | * "ASAHI KASEI AK4642" (japanese) manual p94. | |
313 | */ | |
7b5bfb82 | 314 | snd_soc_update_bits(codec, SG_SL1, PMMP | MGAIN0, PMMP | MGAIN0); |
b91470bb AL |
315 | snd_soc_write(codec, TIMER, ZTM(0x3) | WTM(0x3)); |
316 | snd_soc_write(codec, ALC_CTL1, ALC | LMTH0); | |
ed2dd7da | 317 | snd_soc_update_bits(codec, PW_MGMT1, PMADL, PMADL); |
a3471239 | 318 | snd_soc_update_bits(codec, PW_MGMT3, PMADR, PMADR); |
a3a83d9a KM |
319 | } |
320 | ||
321 | return 0; | |
322 | } | |
323 | ||
324 | static void ak4642_dai_shutdown(struct snd_pcm_substream *substream, | |
325 | struct snd_soc_dai *dai) | |
326 | { | |
327 | int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; | |
328 | struct snd_soc_codec *codec = dai->codec; | |
329 | ||
330 | if (is_play) { | |
a3a83d9a KM |
331 | } else { |
332 | /* stop stereo input */ | |
a3471239 KM |
333 | snd_soc_update_bits(codec, PW_MGMT1, PMADL, 0); |
334 | snd_soc_update_bits(codec, PW_MGMT3, PMADR, 0); | |
335 | snd_soc_update_bits(codec, ALC_CTL1, ALC, 0); | |
a3a83d9a KM |
336 | } |
337 | } | |
338 | ||
339 | static int ak4642_dai_set_sysclk(struct snd_soc_dai *codec_dai, | |
340 | int clk_id, unsigned int freq, int dir) | |
341 | { | |
342 | struct snd_soc_codec *codec = codec_dai->codec; | |
5cd15e29 | 343 | struct ak4642_priv *priv = snd_soc_codec_get_drvdata(codec); |
4b6316b4 | 344 | u8 pll; |
5cd15e29 | 345 | int extended_freq = 0; |
4b6316b4 KM |
346 | |
347 | switch (freq) { | |
348 | case 11289600: | |
349 | pll = PLL2; | |
350 | break; | |
351 | case 12288000: | |
352 | pll = PLL2 | PLL0; | |
353 | break; | |
354 | case 12000000: | |
355 | pll = PLL2 | PLL1; | |
356 | break; | |
357 | case 24000000: | |
358 | pll = PLL2 | PLL1 | PLL0; | |
359 | break; | |
360 | case 13500000: | |
361 | pll = PLL3 | PLL2; | |
362 | break; | |
363 | case 27000000: | |
364 | pll = PLL3 | PLL2 | PLL0; | |
365 | break; | |
5cd15e29 SH |
366 | case 19200000: |
367 | pll = PLL3; | |
368 | extended_freq = 1; | |
369 | break; | |
370 | case 13000000: | |
371 | pll = PLL3 | PLL2 | PLL1; | |
372 | extended_freq = 1; | |
373 | break; | |
374 | case 26000000: | |
375 | pll = PLL3 | PLL2 | PLL1 | PLL0; | |
376 | extended_freq = 1; | |
377 | break; | |
4b6316b4 KM |
378 | default: |
379 | return -EINVAL; | |
380 | } | |
5cd15e29 SH |
381 | |
382 | if (extended_freq && !priv->drvdata->extended_frequencies) | |
383 | return -EINVAL; | |
384 | ||
4b6316b4 | 385 | snd_soc_update_bits(codec, MD_CTL1, PLL_MASK, pll); |
a3a83d9a | 386 | |
a3a83d9a KM |
387 | return 0; |
388 | } | |
389 | ||
0643ce8f KM |
390 | static int ak4642_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
391 | { | |
392 | struct snd_soc_codec *codec = dai->codec; | |
393 | u8 data; | |
394 | u8 bcko; | |
395 | ||
396 | data = MCKO | PMPLL; /* use MCKO */ | |
397 | bcko = 0; | |
398 | ||
399 | /* set master/slave audio interface */ | |
400 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
401 | case SND_SOC_DAIFMT_CBM_CFM: | |
402 | data |= MS; | |
403 | bcko = BCKO_64; | |
404 | break; | |
405 | case SND_SOC_DAIFMT_CBS_CFS: | |
406 | break; | |
407 | default: | |
408 | return -EINVAL; | |
409 | } | |
bd7fdbca | 410 | snd_soc_update_bits(codec, PW_MGMT2, MS | MCKO | PMPLL, data); |
0643ce8f KM |
411 | snd_soc_update_bits(codec, MD_CTL1, BCKO_MASK, bcko); |
412 | ||
cb9c130a KM |
413 | /* format type */ |
414 | data = 0; | |
415 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
416 | case SND_SOC_DAIFMT_LEFT_J: | |
417 | data = LEFT_J; | |
418 | break; | |
419 | case SND_SOC_DAIFMT_I2S: | |
420 | data = I2S; | |
421 | break; | |
422 | /* FIXME | |
423 | * Please add RIGHT_J / DSP support here | |
424 | */ | |
425 | default: | |
426 | return -EINVAL; | |
cb9c130a KM |
427 | } |
428 | snd_soc_update_bits(codec, MD_CTL1, DIF_MASK, data); | |
429 | ||
0643ce8f KM |
430 | return 0; |
431 | } | |
432 | ||
171a0138 KM |
433 | static int ak4642_set_mcko(struct snd_soc_codec *codec, |
434 | u32 frequency) | |
435 | { | |
436 | u32 fs_list[] = { | |
437 | [0] = 8000, | |
438 | [1] = 12000, | |
439 | [2] = 16000, | |
440 | [3] = 24000, | |
441 | [4] = 7350, | |
442 | [5] = 11025, | |
443 | [6] = 14700, | |
444 | [7] = 22050, | |
445 | [10] = 32000, | |
446 | [11] = 48000, | |
447 | [14] = 29400, | |
448 | [15] = 44100, | |
449 | }; | |
450 | u32 ps_list[] = { | |
451 | [0] = 256, | |
452 | [1] = 128, | |
453 | [2] = 64, | |
454 | [3] = 32 | |
455 | }; | |
456 | int ps, fs; | |
457 | ||
458 | for (ps = 0; ps < ARRAY_SIZE(ps_list); ps++) { | |
459 | for (fs = 0; fs < ARRAY_SIZE(fs_list); fs++) { | |
460 | if (frequency == ps_list[ps] * fs_list[fs]) { | |
544637bf KM |
461 | snd_soc_write(codec, MD_CTL2, |
462 | PSs(ps) | FSs(fs)); | |
171a0138 KM |
463 | return 0; |
464 | } | |
465 | } | |
466 | } | |
467 | ||
468 | return 0; | |
469 | } | |
470 | ||
1ad747ca KM |
471 | static int ak4642_dai_hw_params(struct snd_pcm_substream *substream, |
472 | struct snd_pcm_hw_params *params, | |
473 | struct snd_soc_dai *dai) | |
474 | { | |
475 | struct snd_soc_codec *codec = dai->codec; | |
171a0138 KM |
476 | struct ak4642_priv *priv = snd_soc_codec_get_drvdata(codec); |
477 | u32 rate = clk_get_rate(priv->mcko); | |
1ad747ca | 478 | |
171a0138 KM |
479 | if (!rate) |
480 | rate = params_rate(params) * 256; | |
a3a83d9a | 481 | |
171a0138 | 482 | return ak4642_set_mcko(codec, rate); |
a3a83d9a KM |
483 | } |
484 | ||
ed2dd7da KM |
485 | static int ak4642_set_bias_level(struct snd_soc_codec *codec, |
486 | enum snd_soc_bias_level level) | |
487 | { | |
488 | switch (level) { | |
489 | case SND_SOC_BIAS_OFF: | |
490 | snd_soc_write(codec, PW_MGMT1, 0x00); | |
491 | break; | |
492 | default: | |
493 | snd_soc_update_bits(codec, PW_MGMT1, PMVCM, PMVCM); | |
494 | break; | |
495 | } | |
ed2dd7da KM |
496 | |
497 | return 0; | |
498 | } | |
499 | ||
85e7652d | 500 | static const struct snd_soc_dai_ops ak4642_dai_ops = { |
a3a83d9a KM |
501 | .startup = ak4642_dai_startup, |
502 | .shutdown = ak4642_dai_shutdown, | |
503 | .set_sysclk = ak4642_dai_set_sysclk, | |
0643ce8f | 504 | .set_fmt = ak4642_dai_set_fmt, |
1ad747ca | 505 | .hw_params = ak4642_dai_hw_params, |
a3a83d9a KM |
506 | }; |
507 | ||
f0fba2ad LG |
508 | static struct snd_soc_dai_driver ak4642_dai = { |
509 | .name = "ak4642-hifi", | |
a3a83d9a KM |
510 | .playback = { |
511 | .stream_name = "Playback", | |
c01673e0 | 512 | .channels_min = 2, |
a3a83d9a KM |
513 | .channels_max = 2, |
514 | .rates = SNDRV_PCM_RATE_8000_48000, | |
515 | .formats = SNDRV_PCM_FMTBIT_S16_LE }, | |
516 | .capture = { | |
517 | .stream_name = "Capture", | |
c01673e0 | 518 | .channels_min = 2, |
a3a83d9a KM |
519 | .channels_max = 2, |
520 | .rates = SNDRV_PCM_RATE_8000_48000, | |
521 | .formats = SNDRV_PCM_FMTBIT_S16_LE }, | |
522 | .ops = &ak4642_dai_ops, | |
1ad747ca | 523 | .symmetric_rates = 1, |
a3a83d9a | 524 | }; |
a3a83d9a | 525 | |
f0fba2ad | 526 | static int ak4642_resume(struct snd_soc_codec *codec) |
a3a83d9a | 527 | { |
4574cd94 MB |
528 | struct regmap *regmap = dev_get_regmap(codec->dev, NULL); |
529 | ||
530 | regcache_mark_dirty(regmap); | |
531 | regcache_sync(regmap); | |
a3a83d9a KM |
532 | return 0; |
533 | } | |
534 | ||
171a0138 KM |
535 | static int ak4642_probe(struct snd_soc_codec *codec) |
536 | { | |
537 | struct ak4642_priv *priv = snd_soc_codec_get_drvdata(codec); | |
538 | ||
539 | if (priv->mcko) | |
540 | ak4642_set_mcko(codec, clk_get_rate(priv->mcko)); | |
541 | ||
542 | return 0; | |
543 | } | |
544 | ||
f0fba2ad | 545 | static struct snd_soc_codec_driver soc_codec_dev_ak4642 = { |
171a0138 | 546 | .probe = ak4642_probe, |
0ce75aa4 | 547 | .resume = ak4642_resume, |
ed2dd7da | 548 | .set_bias_level = ak4642_set_bias_level, |
a8ca52b7 MB |
549 | .controls = ak4642_snd_controls, |
550 | .num_controls = ARRAY_SIZE(ak4642_snd_controls), | |
a9317e8b KM |
551 | .dapm_widgets = ak4642_dapm_widgets, |
552 | .num_dapm_widgets = ARRAY_SIZE(ak4642_dapm_widgets), | |
553 | .dapm_routes = ak4642_intercon, | |
554 | .num_dapm_routes = ARRAY_SIZE(ak4642_intercon), | |
555 | }; | |
556 | ||
4574cd94 MB |
557 | static const struct regmap_config ak4642_regmap = { |
558 | .reg_bits = 8, | |
559 | .val_bits = 8, | |
f8ea6ceb | 560 | .max_register = FIL1_3, |
4574cd94 | 561 | .reg_defaults = ak4642_reg, |
f8ea6ceb | 562 | .num_reg_defaults = NUM_AK4642_REG_DEFAULTS, |
d3030d11 | 563 | .cache_type = REGCACHE_RBTREE, |
f8ea6ceb AL |
564 | }; |
565 | ||
566 | static const struct regmap_config ak4643_regmap = { | |
567 | .reg_bits = 8, | |
568 | .val_bits = 8, | |
569 | .max_register = SPK_MS, | |
570 | .reg_defaults = ak4643_reg, | |
571 | .num_reg_defaults = ARRAY_SIZE(ak4643_reg), | |
d3030d11 | 572 | .cache_type = REGCACHE_RBTREE, |
4574cd94 MB |
573 | }; |
574 | ||
575 | static const struct regmap_config ak4648_regmap = { | |
576 | .reg_bits = 8, | |
577 | .val_bits = 8, | |
f8ea6ceb | 578 | .max_register = EQ_FBEQE, |
4574cd94 MB |
579 | .reg_defaults = ak4648_reg, |
580 | .num_reg_defaults = ARRAY_SIZE(ak4648_reg), | |
d3030d11 | 581 | .cache_type = REGCACHE_RBTREE, |
f0fba2ad LG |
582 | }; |
583 | ||
d815c703 SH |
584 | static const struct ak4642_drvdata ak4642_drvdata = { |
585 | .regmap_config = &ak4642_regmap, | |
586 | }; | |
587 | ||
588 | static const struct ak4642_drvdata ak4643_drvdata = { | |
f8ea6ceb | 589 | .regmap_config = &ak4643_regmap, |
d815c703 SH |
590 | }; |
591 | ||
592 | static const struct ak4642_drvdata ak4648_drvdata = { | |
593 | .regmap_config = &ak4648_regmap, | |
5cd15e29 | 594 | .extended_frequencies = 1, |
d815c703 SH |
595 | }; |
596 | ||
171a0138 KM |
597 | #ifdef CONFIG_COMMON_CLK |
598 | static struct clk *ak4642_of_parse_mcko(struct device *dev) | |
599 | { | |
600 | struct device_node *np = dev->of_node; | |
601 | struct clk *clk; | |
602 | const char *clk_name = np->name; | |
603 | const char *parent_clk_name = NULL; | |
604 | u32 rate; | |
605 | ||
606 | if (of_property_read_u32(np, "clock-frequency", &rate)) | |
607 | return NULL; | |
608 | ||
609 | if (of_property_read_bool(np, "clocks")) | |
610 | parent_clk_name = of_clk_get_parent_name(np, 0); | |
611 | ||
612 | of_property_read_string(np, "clock-output-names", &clk_name); | |
613 | ||
b6bf3289 | 614 | clk = clk_register_fixed_rate(dev, clk_name, parent_clk_name, 0, rate); |
171a0138 KM |
615 | if (!IS_ERR(clk)) |
616 | of_clk_add_provider(np, of_clk_src_simple_get, clk); | |
617 | ||
618 | return clk; | |
619 | } | |
620 | #else | |
621 | #define ak4642_of_parse_mcko(d) 0 | |
622 | #endif | |
623 | ||
27204ca8 | 624 | static const struct of_device_id ak4642_of_match[]; |
7a79e94e BP |
625 | static int ak4642_i2c_probe(struct i2c_client *i2c, |
626 | const struct i2c_device_id *id) | |
a3a83d9a | 627 | { |
2719a752 KM |
628 | struct device *dev = &i2c->dev; |
629 | struct device_node *np = dev->of_node; | |
d815c703 | 630 | const struct ak4642_drvdata *drvdata = NULL; |
4574cd94 | 631 | struct regmap *regmap; |
d815c703 | 632 | struct ak4642_priv *priv; |
171a0138 | 633 | struct clk *mcko = NULL; |
bbf1453e | 634 | |
bbf1453e KM |
635 | if (np) { |
636 | const struct of_device_id *of_id; | |
637 | ||
171a0138 KM |
638 | mcko = ak4642_of_parse_mcko(dev); |
639 | if (IS_ERR(mcko)) | |
640 | mcko = NULL; | |
641 | ||
2719a752 | 642 | of_id = of_match_device(ak4642_of_match, dev); |
bbf1453e | 643 | if (of_id) |
d815c703 | 644 | drvdata = of_id->data; |
bbf1453e | 645 | } else { |
d815c703 | 646 | drvdata = (const struct ak4642_drvdata *)id->driver_data; |
bbf1453e KM |
647 | } |
648 | ||
d815c703 | 649 | if (!drvdata) { |
2719a752 | 650 | dev_err(dev, "Unknown device type\n"); |
bbf1453e KM |
651 | return -EINVAL; |
652 | } | |
653 | ||
2719a752 | 654 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
d815c703 SH |
655 | if (!priv) |
656 | return -ENOMEM; | |
657 | ||
658 | priv->drvdata = drvdata; | |
171a0138 | 659 | priv->mcko = mcko; |
d815c703 SH |
660 | |
661 | i2c_set_clientdata(i2c, priv); | |
662 | ||
663 | regmap = devm_regmap_init_i2c(i2c, drvdata->regmap_config); | |
4574cd94 MB |
664 | if (IS_ERR(regmap)) |
665 | return PTR_ERR(regmap); | |
666 | ||
2719a752 | 667 | return snd_soc_register_codec(dev, |
4574cd94 | 668 | &soc_codec_dev_ak4642, &ak4642_dai, 1); |
a3a83d9a KM |
669 | } |
670 | ||
7a79e94e | 671 | static int ak4642_i2c_remove(struct i2c_client *client) |
a3a83d9a | 672 | { |
f0fba2ad | 673 | snd_soc_unregister_codec(&client->dev); |
a3a83d9a KM |
674 | return 0; |
675 | } | |
676 | ||
27204ca8 | 677 | static const struct of_device_id ak4642_of_match[] = { |
d815c703 SH |
678 | { .compatible = "asahi-kasei,ak4642", .data = &ak4642_drvdata}, |
679 | { .compatible = "asahi-kasei,ak4643", .data = &ak4643_drvdata}, | |
680 | { .compatible = "asahi-kasei,ak4648", .data = &ak4648_drvdata}, | |
bbf1453e KM |
681 | {}, |
682 | }; | |
683 | MODULE_DEVICE_TABLE(of, ak4642_of_match); | |
684 | ||
a3a83d9a | 685 | static const struct i2c_device_id ak4642_i2c_id[] = { |
d815c703 SH |
686 | { "ak4642", (kernel_ulong_t)&ak4642_drvdata }, |
687 | { "ak4643", (kernel_ulong_t)&ak4643_drvdata }, | |
688 | { "ak4648", (kernel_ulong_t)&ak4648_drvdata }, | |
a3a83d9a KM |
689 | { } |
690 | }; | |
691 | MODULE_DEVICE_TABLE(i2c, ak4642_i2c_id); | |
692 | ||
693 | static struct i2c_driver ak4642_i2c_driver = { | |
694 | .driver = { | |
f0fba2ad | 695 | .name = "ak4642-codec", |
bbf1453e | 696 | .of_match_table = ak4642_of_match, |
a3a83d9a | 697 | }, |
0ce75aa4 | 698 | .probe = ak4642_i2c_probe, |
7a79e94e | 699 | .remove = ak4642_i2c_remove, |
0ce75aa4 | 700 | .id_table = ak4642_i2c_id, |
a3a83d9a | 701 | }; |
a3a83d9a | 702 | |
2f54d2a1 | 703 | module_i2c_driver(ak4642_i2c_driver); |
a3a83d9a KM |
704 | |
705 | MODULE_DESCRIPTION("Soc AK4642 driver"); | |
706 | MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); | |
707 | MODULE_LICENSE("GPL"); |