[deliverable/linux.git] / sound / soc / codecs / ak4642.c

/*
 * ak4642.c  --  AK4642/AK4643 ALSA Soc Audio driver
 *
 * Copyright (C) 2009 Renesas Solutions Corp.
 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
 *
 * Based on wm8731.c by Richard Purdie
 * Based on ak4535.c by Richard Purdie
 * Based on wm8753.c by Liam Girdwood
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/* ** CAUTION **
 *
 * This is very simple driver.
 * It can use headphone output / stereo input only
 *
 * AK4642 is tested.
 * AK4643 is tested.
 * AK4648 is tested.
 */

#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/of_device.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>

#define PW_MGMT1	0x00
#define PW_MGMT2	0x01
#define SG_SL1		0x02
#define SG_SL2		0x03
#define MD_CTL1		0x04
#define MD_CTL2		0x05
#define TIMER		0x06
#define ALC_CTL1	0x07
#define ALC_CTL2	0x08
#define L_IVC		0x09
#define L_DVC		0x0a
#define ALC_CTL3	0x0b
#define R_IVC		0x0c
#define R_DVC		0x0d
#define MD_CTL3		0x0e
#define MD_CTL4		0x0f
#define PW_MGMT3	0x10
#define DF_S		0x11
#define FIL3_0		0x12
#define FIL3_1		0x13
#define FIL3_2		0x14
#define FIL3_3		0x15
#define EQ_0		0x16
#define EQ_1		0x17
#define EQ_2		0x18
#define EQ_3		0x19
#define EQ_4		0x1a
#define EQ_5		0x1b
#define FIL1_0		0x1c
#define FIL1_1		0x1d
#define FIL1_2		0x1e
#define FIL1_3		0x1f
#define PW_MGMT4	0x20
#define MD_CTL5		0x21
#define LO_MS		0x22
#define HP_MS		0x23
#define SPK_MS		0x24

/* PW_MGMT1*/
#define PMVCM		(1 << 6) /* VCOM Power Management */
#define PMMIN		(1 << 5) /* MIN Input Power Management */
#define PMDAC		(1 << 2) /* DAC Power Management */
#define PMADL		(1 << 0) /* MIC Amp Lch and ADC Lch Power Management */

/* PW_MGMT2 */
#define HPMTN		(1 << 6)
#define PMHPL		(1 << 5)
#define PMHPR		(1 << 4)
#define MS		(1 << 3) /* master/slave select */
#define MCKO		(1 << 1)
#define PMPLL		(1 << 0)

#define PMHP_MASK	(PMHPL | PMHPR)
#define PMHP		PMHP_MASK

/* PW_MGMT3 */
#define PMADR		(1 << 0) /* MIC L / ADC R Power Management */

/* SG_SL1 */
#define MINS		(1 << 6) /* Switch from MIN to Speaker */
#define DACL		(1 << 4) /* Switch from DAC to Stereo or Receiver */
#define PMMP		(1 << 2) /* MPWR pin Power Management */
#define MGAIN0		(1 << 0) /* MIC amp gain*/

/* TIMER */
#define ZTM(param)	((param & 0x3) << 4) /* ALC Zero Crossing TimeOut */
#define WTM(param)	(((param & 0x4) << 4) | ((param & 0x3) << 2))

/* ALC_CTL1 */
#define ALC		(1 << 5) /* ALC Enable */
#define LMTH0		(1 << 0) /* ALC Limiter / Recovery Level */

/* MD_CTL1 */
#define PLL3		(1 << 7)
#define PLL2		(1 << 6)
#define PLL1		(1 << 5)
#define PLL0		(1 << 4)
#define PLL_MASK	(PLL3 | PLL2 | PLL1 | PLL0)

#define BCKO_MASK	(1 << 3)
#define BCKO_64		BCKO_MASK

#define DIF_MASK	(3 << 0)
#define DSP		(0 << 0)
#define RIGHT_J		(1 << 0)
#define LEFT_J		(2 << 0)
#define I2S		(3 << 0)

/* MD_CTL2 */
#define FS0		(1 << 0)
#define FS1		(1 << 1)
#define FS2		(1 << 2)
#define FS3		(1 << 5)
#define FS_MASK		(FS0 | FS1 | FS2 | FS3)

/* MD_CTL3 */
#define BST1		(1 << 3)

/* MD_CTL4 */
#define DACH		(1 << 0)

struct ak4642_drvdata {
	const struct regmap_config *regmap_config;
	int extended_frequencies;
};

struct ak4642_priv {
	const struct ak4642_drvdata *drvdata;
};

/*
 * Playback Volume (table 39)
 *
 * max : 0x00 : +12.0 dB
 *       ( 0.5 dB step )
 * min : 0xFE : -115.0 dB
 * mute: 0xFF
 */
static const DECLARE_TLV_DB_SCALE(out_tlv, -11550, 50, 1);

static const struct snd_kcontrol_new ak4642_snd_controls[] = {

	SOC_DOUBLE_R_TLV("Digital Playback Volume", L_DVC, R_DVC,
			 0, 0xFF, 1, out_tlv),
	SOC_SINGLE("ALC Capture Switch", ALC_CTL1, 5, 1, 0),
	SOC_SINGLE("ALC Capture ZC Switch", ALC_CTL1, 4, 1, 1),
};

static const struct snd_kcontrol_new ak4642_headphone_control =
	SOC_DAPM_SINGLE("Switch", PW_MGMT2, 6, 1, 0);

static const struct snd_kcontrol_new ak4642_lout_mixer_controls[] = {
	SOC_DAPM_SINGLE("DACL", SG_SL1, 4, 1, 0),
};

static const struct snd_soc_dapm_widget ak4642_dapm_widgets[] = {

	/* Outputs */
	SND_SOC_DAPM_OUTPUT("HPOUTL"),
	SND_SOC_DAPM_OUTPUT("HPOUTR"),
	SND_SOC_DAPM_OUTPUT("LINEOUT"),

	SND_SOC_DAPM_PGA("HPL Out", PW_MGMT2, 5, 0, NULL, 0),
	SND_SOC_DAPM_PGA("HPR Out", PW_MGMT2, 4, 0, NULL, 0),
	SND_SOC_DAPM_SWITCH("Headphone Enable", SND_SOC_NOPM, 0, 0,
			    &ak4642_headphone_control),

	SND_SOC_DAPM_PGA("DACH", MD_CTL4, 0, 0, NULL, 0),

	SND_SOC_DAPM_MIXER("LINEOUT Mixer", PW_MGMT1, 3, 0,
			   &ak4642_lout_mixer_controls[0],
			   ARRAY_SIZE(ak4642_lout_mixer_controls)),

	/* DAC */
	SND_SOC_DAPM_DAC("DAC", "HiFi Playback", PW_MGMT1, 2, 0),
};

static const struct snd_soc_dapm_route ak4642_intercon[] = {

	/* Outputs */
	{"HPOUTL", NULL, "HPL Out"},
	{"HPOUTR", NULL, "HPR Out"},
	{"LINEOUT", NULL, "LINEOUT Mixer"},

	{"HPL Out", NULL, "Headphone Enable"},
	{"HPR Out", NULL, "Headphone Enable"},

	{"Headphone Enable", "Switch", "DACH"},

	{"DACH", NULL, "DAC"},

	{"LINEOUT Mixer", "DACL", "DAC"},
};

/*
 * ak4642 register cache
 */
static const struct reg_default ak4642_reg[] = {
	{  0, 0x00 }, {  1, 0x00 }, {  2, 0x01 }, {  3, 0x00 },
	{  4, 0x02 }, {  5, 0x00 }, {  6, 0x00 }, {  7, 0x00 },
	{  8, 0xe1 }, {  9, 0xe1 }, { 10, 0x18 }, { 11, 0x00 },
	{ 12, 0xe1 }, { 13, 0x18 }, { 14, 0x11 }, { 15, 0x08 },
	{ 16, 0x00 }, { 17, 0x00 }, { 18, 0x00 }, { 19, 0x00 },
	{ 20, 0x00 }, { 21, 0x00 }, { 22, 0x00 }, { 23, 0x00 },
	{ 24, 0x00 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0x00 },
	{ 28, 0x00 }, { 29, 0x00 }, { 30, 0x00 }, { 31, 0x00 },
	{ 32, 0x00 }, { 33, 0x00 }, { 34, 0x00 }, { 35, 0x00 },
	{ 36, 0x00 },
};

static const struct reg_default ak4648_reg[] = {
	{  0, 0x00 }, {  1, 0x00 }, {  2, 0x01 }, {  3, 0x00 },
	{  4, 0x02 }, {  5, 0x00 }, {  6, 0x00 }, {  7, 0x00 },
	{  8, 0xe1 }, {  9, 0xe1 }, { 10, 0x18 }, { 11, 0x00 },
	{ 12, 0xe1 }, { 13, 0x18 }, { 14, 0x11 }, { 15, 0xb8 },
	{ 16, 0x00 }, { 17, 0x00 }, { 18, 0x00 }, { 19, 0x00 },
	{ 20, 0x00 }, { 21, 0x00 }, { 22, 0x00 }, { 23, 0x00 },
	{ 24, 0x00 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0x00 },
	{ 28, 0x00 }, { 29, 0x00 }, { 30, 0x00 }, { 31, 0x00 },
	{ 32, 0x00 }, { 33, 0x00 }, { 34, 0x00 }, { 35, 0x00 },
	{ 36, 0x00 }, { 37, 0x88 }, { 38, 0x88 }, { 39, 0x08 },
};

static int ak4642_dai_startup(struct snd_pcm_substream *substream,
			      struct snd_soc_dai *dai)
{
	int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
	struct snd_soc_codec *codec = dai->codec;

	if (is_play) {
		/*
		 * start headphone output
		 *
		 * PLL, Master Mode
		 * Audio I/F Format :MSB justified (ADC & DAC)
		 * Bass Boost Level : Middle
		 *
		 * This operation came from example code of
		 * "ASAHI KASEI AK4642" (japanese) manual p97.
		 */
		snd_soc_write(codec, L_IVC, 0x91); /* volume */
		snd_soc_write(codec, R_IVC, 0x91); /* volume */
	} else {
		/*
		 * start stereo input
		 *
		 * PLL Master Mode
		 * Audio I/F Format:MSB justified (ADC & DAC)
		 * Pre MIC AMP:+20dB
		 * MIC Power On
		 * ALC setting:Refer to Table 35
		 * ALC bit=“1”
		 *
		 * This operation came from example code of
		 * "ASAHI KASEI AK4642" (japanese) manual p94.
		 */
		snd_soc_update_bits(codec, SG_SL1, PMMP | MGAIN0, PMMP | MGAIN0);
		snd_soc_write(codec, TIMER, ZTM(0x3) | WTM(0x3));
		snd_soc_write(codec, ALC_CTL1, ALC | LMTH0);
		snd_soc_update_bits(codec, PW_MGMT1, PMADL, PMADL);
		snd_soc_update_bits(codec, PW_MGMT3, PMADR, PMADR);
	}

	return 0;
}

static void ak4642_dai_shutdown(struct snd_pcm_substream *substream,
			       struct snd_soc_dai *dai)
{
	int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
	struct snd_soc_codec *codec = dai->codec;

	if (is_play) {
	} else {
		/* stop stereo input */
		snd_soc_update_bits(codec, PW_MGMT1, PMADL, 0);
		snd_soc_update_bits(codec, PW_MGMT3, PMADR, 0);
		snd_soc_update_bits(codec, ALC_CTL1, ALC, 0);
	}
}

static int ak4642_dai_set_sysclk(struct snd_soc_dai *codec_dai,
	int clk_id, unsigned int freq, int dir)
{
	struct snd_soc_codec *codec = codec_dai->codec;
	struct ak4642_priv *priv = snd_soc_codec_get_drvdata(codec);
	u8 pll;
	int extended_freq = 0;

	switch (freq) {
	case 11289600:
		pll = PLL2;
		break;
	case 12288000:
		pll = PLL2 | PLL0;
		break;
	case 12000000:
		pll = PLL2 | PLL1;
		break;
	case 24000000:
		pll = PLL2 | PLL1 | PLL0;
		break;
	case 13500000:
		pll = PLL3 | PLL2;
		break;
	case 27000000:
		pll = PLL3 | PLL2 | PLL0;
		break;
	case 19200000:
		pll = PLL3;
		extended_freq = 1;
		break;
	case 13000000:
		pll = PLL3 | PLL2 | PLL1;
		extended_freq = 1;
		break;
	case 26000000:
		pll = PLL3 | PLL2 | PLL1 | PLL0;
		extended_freq = 1;
		break;
	default:
		return -EINVAL;
	}

	if (extended_freq && !priv->drvdata->extended_frequencies)
		return -EINVAL;

	snd_soc_update_bits(codec, MD_CTL1, PLL_MASK, pll);

	return 0;
}

static int ak4642_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
	struct snd_soc_codec *codec = dai->codec;
	u8 data;
	u8 bcko;

	data = MCKO | PMPLL; /* use MCKO */
	bcko = 0;

	/* set master/slave audio interface */
	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBM_CFM:
		data |= MS;
		bcko = BCKO_64;
		break;
	case SND_SOC_DAIFMT_CBS_CFS:
		break;
	default:
		return -EINVAL;
	}
	snd_soc_update_bits(codec, PW_MGMT2, MS | MCKO | PMPLL, data);
	snd_soc_update_bits(codec, MD_CTL1, BCKO_MASK, bcko);

	/* format type */
	data = 0;
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_LEFT_J:
		data = LEFT_J;
		break;
	case SND_SOC_DAIFMT_I2S:
		data = I2S;
		break;
	/* FIXME
	 * Please add RIGHT_J / DSP support here
	 */
	default:
		return -EINVAL;
	}
	snd_soc_update_bits(codec, MD_CTL1, DIF_MASK, data);

	return 0;
}

static int ak4642_dai_hw_params(struct snd_pcm_substream *substream,
				struct snd_pcm_hw_params *params,
				struct snd_soc_dai *dai)
{
	struct snd_soc_codec *codec = dai->codec;
	u8 rate;

	switch (params_rate(params)) {
	case 7350:
		rate = FS2;
		break;
	case 8000:
		rate = 0;
		break;
	case 11025:
		rate = FS2 | FS0;
		break;
	case 12000:
		rate = FS0;
		break;
	case 14700:
		rate = FS2 | FS1;
		break;
	case 16000:
		rate = FS1;
		break;
	case 22050:
		rate = FS2 | FS1 | FS0;
		break;
	case 24000:
		rate = FS1 | FS0;
		break;
	case 29400:
		rate = FS3 | FS2 | FS1;
		break;
	case 32000:
		rate = FS3 | FS1;
		break;
	case 44100:
		rate = FS3 | FS2 | FS1 | FS0;
		break;
	case 48000:
		rate = FS3 | FS1 | FS0;
		break;
	default:
		return -EINVAL;
	}
	snd_soc_update_bits(codec, MD_CTL2, FS_MASK, rate);

	return 0;
}

static int ak4642_set_bias_level(struct snd_soc_codec *codec,
				 enum snd_soc_bias_level level)
{
	switch (level) {
	case SND_SOC_BIAS_OFF:
		snd_soc_write(codec, PW_MGMT1, 0x00);
		break;
	default:
		snd_soc_update_bits(codec, PW_MGMT1, PMVCM, PMVCM);
		break;
	}
	codec->dapm.bias_level = level;

	return 0;
}

static const struct snd_soc_dai_ops ak4642_dai_ops = {
	.startup	= ak4642_dai_startup,
	.shutdown	= ak4642_dai_shutdown,
	.set_sysclk	= ak4642_dai_set_sysclk,
	.set_fmt	= ak4642_dai_set_fmt,
	.hw_params	= ak4642_dai_hw_params,
};

static struct snd_soc_dai_driver ak4642_dai = {
	.name = "ak4642-hifi",
	.playback = {
		.stream_name = "Playback",
		.channels_min = 1,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_48000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE },
	.capture = {
		.stream_name = "Capture",
		.channels_min = 1,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_48000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE },
	.ops = &ak4642_dai_ops,
	.symmetric_rates = 1,
};

static int ak4642_resume(struct snd_soc_codec *codec)
{
	struct regmap *regmap = dev_get_regmap(codec->dev, NULL);

	regcache_mark_dirty(regmap);
	regcache_sync(regmap);
	return 0;
}

static struct snd_soc_codec_driver soc_codec_dev_ak4642 = {
	.resume			= ak4642_resume,
	.set_bias_level		= ak4642_set_bias_level,
	.controls		= ak4642_snd_controls,
	.num_controls		= ARRAY_SIZE(ak4642_snd_controls),
	.dapm_widgets		= ak4642_dapm_widgets,
	.num_dapm_widgets	= ARRAY_SIZE(ak4642_dapm_widgets),
	.dapm_routes		= ak4642_intercon,
	.num_dapm_routes	= ARRAY_SIZE(ak4642_intercon),
};

static const struct regmap_config ak4642_regmap = {
	.reg_bits		= 8,
	.val_bits		= 8,
	.max_register		= ARRAY_SIZE(ak4642_reg) + 1,
	.reg_defaults		= ak4642_reg,
	.num_reg_defaults	= ARRAY_SIZE(ak4642_reg),
};

static const struct regmap_config ak4648_regmap = {
	.reg_bits		= 8,
	.val_bits		= 8,
	.max_register		= ARRAY_SIZE(ak4648_reg) + 1,
	.reg_defaults		= ak4648_reg,
	.num_reg_defaults	= ARRAY_SIZE(ak4648_reg),
};

static const struct ak4642_drvdata ak4642_drvdata = {
	.regmap_config = &ak4642_regmap,
};

static const struct ak4642_drvdata ak4643_drvdata = {
	.regmap_config = &ak4642_regmap,
};

static const struct ak4642_drvdata ak4648_drvdata = {
	.regmap_config = &ak4648_regmap,
	.extended_frequencies = 1,
};

static const struct of_device_id ak4642_of_match[];
static int ak4642_i2c_probe(struct i2c_client *i2c,
			    const struct i2c_device_id *id)
{
	struct device_node *np = i2c->dev.of_node;
	const struct ak4642_drvdata *drvdata = NULL;
	struct regmap *regmap;
	struct ak4642_priv *priv;

	if (np) {
		const struct of_device_id *of_id;

		of_id = of_match_device(ak4642_of_match, &i2c->dev);
		if (of_id)
			drvdata = of_id->data;
	} else {
		drvdata = (const struct ak4642_drvdata *)id->driver_data;
	}

	if (!drvdata) {
		dev_err(&i2c->dev, "Unknown device type\n");
		return -EINVAL;
	}

	priv = devm_kzalloc(&i2c->dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->drvdata = drvdata;

	i2c_set_clientdata(i2c, priv);

	regmap = devm_regmap_init_i2c(i2c, drvdata->regmap_config);
	if (IS_ERR(regmap))
		return PTR_ERR(regmap);

	return snd_soc_register_codec(&i2c->dev,
				      &soc_codec_dev_ak4642, &ak4642_dai, 1);
}

static int ak4642_i2c_remove(struct i2c_client *client)
{
	snd_soc_unregister_codec(&client->dev);
	return 0;
}

static const struct of_device_id ak4642_of_match[] = {
	{ .compatible = "asahi-kasei,ak4642",	.data = &ak4642_drvdata},
	{ .compatible = "asahi-kasei,ak4643",	.data = &ak4643_drvdata},
	{ .compatible = "asahi-kasei,ak4648",	.data = &ak4648_drvdata},
	{},
};
MODULE_DEVICE_TABLE(of, ak4642_of_match);

static const struct i2c_device_id ak4642_i2c_id[] = {
	{ "ak4642", (kernel_ulong_t)&ak4642_drvdata },
	{ "ak4643", (kernel_ulong_t)&ak4643_drvdata },
	{ "ak4648", (kernel_ulong_t)&ak4648_drvdata },
	{ }
};
MODULE_DEVICE_TABLE(i2c, ak4642_i2c_id);

static struct i2c_driver ak4642_i2c_driver = {
	.driver = {
		.name = "ak4642-codec",
		.owner = THIS_MODULE,
		.of_match_table = ak4642_of_match,
	},
	.probe		= ak4642_i2c_probe,
	.remove		= ak4642_i2c_remove,
	.id_table	= ak4642_i2c_id,
};

module_i2c_driver(ak4642_i2c_driver);

MODULE_DESCRIPTION("Soc AK4642 driver");
MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
a3a83d9a KM	1	/*
	2	* ak4642.c -- AK4642/AK4643 ALSA Soc Audio driver
	3	*
	4	* Copyright (C) 2009 Renesas Solutions Corp.
	5	* Kuninori Morimoto <morimoto.kuninori@renesas.com>
	6	*
	7	* Based on wm8731.c by Richard Purdie
	8	* Based on ak4535.c by Richard Purdie
	9	* Based on wm8753.c by Liam Girdwood
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	/* CAUTION
	17	*
	18	* This is very simple driver.
	19	* It can use headphone output / stereo input only
	20	*
20211391	21	* AK4642 is tested.
a3a83d9a	22	* AK4643 is tested.
a9317e8b	23	* AK4648 is tested.
a3a83d9a KM	24	*/
a3a83d9a KM	25
a3a83d9a	26	#include <linux/delay.h>
a3a83d9a	27	#include <linux/i2c.h>
5a0e3ad6	28	#include <linux/slab.h>
bbf1453e	29	#include <linux/of_device.h>
da155d5b	30	#include <linux/module.h>
4574cd94	31	#include <linux/regmap.h>
ce6120cc	32	#include <sound/soc.h>
a3a83d9a	33	#include <sound/initval.h>
a300de3c	34	#include <sound/tlv.h>
a3a83d9a	35
a3a83d9a KM	36	#define PW_MGMT1 0x00
	37	#define PW_MGMT2 0x01
	38	#define SG_SL1 0x02
	39	#define SG_SL2 0x03
	40	#define MD_CTL1 0x04
	41	#define MD_CTL2 0x05
	42	#define TIMER 0x06
	43	#define ALC_CTL1 0x07
	44	#define ALC_CTL2 0x08
	45	#define L_IVC 0x09
	46	#define L_DVC 0x0a
	47	#define ALC_CTL3 0x0b
	48	#define R_IVC 0x0c
	49	#define R_DVC 0x0d
	50	#define MD_CTL3 0x0e
	51	#define MD_CTL4 0x0f
	52	#define PW_MGMT3 0x10
	53	#define DF_S 0x11
	54	#define FIL3_0 0x12
	55	#define FIL3_1 0x13
	56	#define FIL3_2 0x14
	57	#define FIL3_3 0x15
	58	#define EQ_0 0x16
	59	#define EQ_1 0x17
	60	#define EQ_2 0x18
	61	#define EQ_3 0x19
	62	#define EQ_4 0x1a
	63	#define EQ_5 0x1b
	64	#define FIL1_0 0x1c
	65	#define FIL1_1 0x1d
	66	#define FIL1_2 0x1e
	67	#define FIL1_3 0x1f
	68	#define PW_MGMT4 0x20
	69	#define MD_CTL5 0x21
	70	#define LO_MS 0x22
	71	#define HP_MS 0x23
	72	#define SPK_MS 0x24
	73
a3471239 KM	74	/* PW_MGMT1*/
	75	#define PMVCM (1 << 6) /* VCOM Power Management */
	76	#define PMMIN (1 << 5) /* MIN Input Power Management */
	77	#define PMDAC (1 << 2) /* DAC Power Management */
	78	#define PMADL (1 << 0) /* MIC Amp Lch and ADC Lch Power Management */
	79
0643ce8f KM	80	/* PW_MGMT2 */
	81	#define HPMTN (1 << 6)
	82	#define PMHPL (1 << 5)
	83	#define PMHPR (1 << 4)
	84	#define MS (1 << 3) /* master/slave select */
	85	#define MCKO (1 << 1)
	86	#define PMPLL (1 << 0)
	87
	88	#define PMHP_MASK (PMHPL \| PMHPR)
	89	#define PMHP PMHP_MASK
	90
a3471239 KM	91	/* PW_MGMT3 */
	92	#define PMADR (1 << 0) /* MIC L / ADC R Power Management */
	93
	94	/* SG_SL1 */
	95	#define MINS (1 << 6) /* Switch from MIN to Speaker */
	96	#define DACL (1 << 4) /* Switch from DAC to Stereo or Receiver */
	97	#define PMMP (1 << 2) /* MPWR pin Power Management */
	98	#define MGAIN0 (1 << 0) /* MIC amp gain*/
	99
	100	/* TIMER */
da731845	101	#define ZTM(param) ((param & 0x3) << 4) /* ALC Zero Crossing TimeOut */
a3471239 KM	102	#define WTM(param) (((param & 0x4) << 4) \| ((param & 0x3) << 2))
	103
	104	/* ALC_CTL1 */
	105	#define ALC (1 << 5) /* ALC Enable */
	106	#define LMTH0 (1 << 0) /* ALC Limiter / Recovery Level */
	107
4b6316b4 KM	108	/* MD_CTL1 */
	109	#define PLL3 (1 << 7)
	110	#define PLL2 (1 << 6)
	111	#define PLL1 (1 << 5)
	112	#define PLL0 (1 << 4)
	113	#define PLL_MASK (PLL3 \| PLL2 \| PLL1 \| PLL0)
	114
0643ce8f KM	115	#define BCKO_MASK (1 << 3)
	116	#define BCKO_64 BCKO_MASK
	117
cb9c130a KM	118	#define DIF_MASK (3 << 0)
	119	#define DSP (0 << 0)
	120	#define RIGHT_J (1 << 0)
	121	#define LEFT_J (2 << 0)
	122	#define I2S (3 << 0)
	123
1ad747ca KM	124	/* MD_CTL2 */
	125	#define FS0 (1 << 0)
	126	#define FS1 (1 << 1)
	127	#define FS2 (1 << 2)
	128	#define FS3 (1 << 5)
	129	#define FS_MASK (FS0 \| FS1 \| FS2 \| FS3)
	130
a3471239 KM	131	/* MD_CTL3 */
	132	#define BST1 (1 << 3)
	133
	134	/* MD_CTL4 */
	135	#define DACH (1 << 0)
a3a83d9a	136
d815c703 SH	137	struct ak4642_drvdata {
d815c703 SH	138	const struct regmap_config *regmap_config;
5cd15e29	139	int extended_frequencies;
d815c703 SH	140	};
	141
	142	struct ak4642_priv {
	143	const struct ak4642_drvdata *drvdata;
	144	};
	145
a300de3c KM	146	/*
	147	* Playback Volume (table 39)
	148	*
	149	* max : 0x00 : +12.0 dB
	150	* ( 0.5 dB step )
	151	* min : 0xFE : -115.0 dB
	152	* mute: 0xFF
	153	*/
1f99e44c	154	static const DECLARE_TLV_DB_SCALE(out_tlv, -11550, 50, 1);
a300de3c KM	155
	156	static const struct snd_kcontrol_new ak4642_snd_controls[] = {
	157
	158	SOC_DOUBLE_R_TLV("Digital Playback Volume", L_DVC, R_DVC,
	159	0, 0xFF, 1, out_tlv),
370f83a1 SH	160	SOC_SINGLE("ALC Capture Switch", ALC_CTL1, 5, 1, 0),
370f83a1 SH	161	SOC_SINGLE("ALC Capture ZC Switch", ALC_CTL1, 4, 1, 1),
a300de3c KM	162	};
a300de3c KM	163
e555cf36 KM	164	static const struct snd_kcontrol_new ak4642_headphone_control =
e555cf36 KM	165	SOC_DAPM_SINGLE("Switch", PW_MGMT2, 6, 1, 0);
24747dae	166
e8c83dbf KM	167	static const struct snd_kcontrol_new ak4642_lout_mixer_controls[] = {
	168	SOC_DAPM_SINGLE("DACL", SG_SL1, 4, 1, 0),
	169	};
	170
24747dae KM	171	static const struct snd_soc_dapm_widget ak4642_dapm_widgets[] = {
	172
	173	/* Outputs */
	174	SND_SOC_DAPM_OUTPUT("HPOUTL"),
	175	SND_SOC_DAPM_OUTPUT("HPOUTR"),
e8c83dbf	176	SND_SOC_DAPM_OUTPUT("LINEOUT"),
24747dae	177
e555cf36 KM	178	SND_SOC_DAPM_PGA("HPL Out", PW_MGMT2, 5, 0, NULL, 0),
	179	SND_SOC_DAPM_PGA("HPR Out", PW_MGMT2, 4, 0, NULL, 0),
	180	SND_SOC_DAPM_SWITCH("Headphone Enable", SND_SOC_NOPM, 0, 0,
	181	&ak4642_headphone_control),
24747dae	182
e555cf36	183	SND_SOC_DAPM_PGA("DACH", MD_CTL4, 0, 0, NULL, 0),
24747dae	184
e8c83dbf KM	185	SND_SOC_DAPM_MIXER("LINEOUT Mixer", PW_MGMT1, 3, 0,
	186	&ak4642_lout_mixer_controls[0],
	187	ARRAY_SIZE(ak4642_lout_mixer_controls)),
	188
24747dae KM	189	/* DAC */
	190	SND_SOC_DAPM_DAC("DAC", "HiFi Playback", PW_MGMT1, 2, 0),
	191	};
	192
	193	static const struct snd_soc_dapm_route ak4642_intercon[] = {
	194
	195	/* Outputs */
e555cf36 KM	196	{"HPOUTL", NULL, "HPL Out"},
e555cf36 KM	197	{"HPOUTR", NULL, "HPR Out"},
e8c83dbf	198	{"LINEOUT", NULL, "LINEOUT Mixer"},
24747dae	199
e555cf36 KM	200	{"HPL Out", NULL, "Headphone Enable"},
	201	{"HPR Out", NULL, "Headphone Enable"},
	202
	203	{"Headphone Enable", "Switch", "DACH"},
	204
	205	{"DACH", NULL, "DAC"},
	206
e8c83dbf	207	{"LINEOUT Mixer", "DACL", "DAC"},
24747dae	208	};
a300de3c	209
a3a83d9a KM	210	/*
	211	* ak4642 register cache
	212	*/
4574cd94 MB	213	static const struct reg_default ak4642_reg[] = {
	214	{ 0, 0x00 }, { 1, 0x00 }, { 2, 0x01 }, { 3, 0x00 },
	215	{ 4, 0x02 }, { 5, 0x00 }, { 6, 0x00 }, { 7, 0x00 },
	216	{ 8, 0xe1 }, { 9, 0xe1 }, { 10, 0x18 }, { 11, 0x00 },
	217	{ 12, 0xe1 }, { 13, 0x18 }, { 14, 0x11 }, { 15, 0x08 },
	218	{ 16, 0x00 }, { 17, 0x00 }, { 18, 0x00 }, { 19, 0x00 },
	219	{ 20, 0x00 }, { 21, 0x00 }, { 22, 0x00 }, { 23, 0x00 },
	220	{ 24, 0x00 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0x00 },
	221	{ 28, 0x00 }, { 29, 0x00 }, { 30, 0x00 }, { 31, 0x00 },
	222	{ 32, 0x00 }, { 33, 0x00 }, { 34, 0x00 }, { 35, 0x00 },
	223	{ 36, 0x00 },
a3a83d9a KM	224	};
a3a83d9a KM	225
4574cd94 MB	226	static const struct reg_default ak4648_reg[] = {
	227	{ 0, 0x00 }, { 1, 0x00 }, { 2, 0x01 }, { 3, 0x00 },
	228	{ 4, 0x02 }, { 5, 0x00 }, { 6, 0x00 }, { 7, 0x00 },
	229	{ 8, 0xe1 }, { 9, 0xe1 }, { 10, 0x18 }, { 11, 0x00 },
	230	{ 12, 0xe1 }, { 13, 0x18 }, { 14, 0x11 }, { 15, 0xb8 },
	231	{ 16, 0x00 }, { 17, 0x00 }, { 18, 0x00 }, { 19, 0x00 },
	232	{ 20, 0x00 }, { 21, 0x00 }, { 22, 0x00 }, { 23, 0x00 },
	233	{ 24, 0x00 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0x00 },
	234	{ 28, 0x00 }, { 29, 0x00 }, { 30, 0x00 }, { 31, 0x00 },
	235	{ 32, 0x00 }, { 33, 0x00 }, { 34, 0x00 }, { 35, 0x00 },
	236	{ 36, 0x00 }, { 37, 0x88 }, { 38, 0x88 }, { 39, 0x08 },
a9317e8b KM	237	};
a9317e8b KM	238
a3a83d9a KM	239	static int ak4642_dai_startup(struct snd_pcm_substream *substream,
	240	struct snd_soc_dai *dai)
	241	{
	242	int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
	243	struct snd_soc_codec *codec = dai->codec;
	244
	245	if (is_play) {
	246	/*
	247	* start headphone output
	248	*
	249	* PLL, Master Mode
	250	* Audio I/F Format :MSB justified (ADC & DAC)
a3a83d9a KM	251	* Bass Boost Level : Middle
	252	*
	253	* This operation came from example code of
	254	* "ASAHI KASEI AK4642" (japanese) manual p97.
a3a83d9a	255	*/
b91470bb AL	256	snd_soc_write(codec, L_IVC, 0x91); /* volume */
b91470bb AL	257	snd_soc_write(codec, R_IVC, 0x91); /* volume */
a3a83d9a KM	258	} else {
	259	/*
	260	* start stereo input
	261	*
	262	* PLL Master Mode
	263	* Audio I/F Format:MSB justified (ADC & DAC)
a3a83d9a KM	264	* Pre MIC AMP:+20dB
	265	* MIC Power On
	266	* ALC setting:Refer to Table 35
	267	* ALC bit=“1”
	268	*
	269	* This operation came from example code of
	270	* "ASAHI KASEI AK4642" (japanese) manual p94.
	271	*/
7b5bfb82	272	snd_soc_update_bits(codec, SG_SL1, PMMP \| MGAIN0, PMMP \| MGAIN0);
b91470bb AL	273	snd_soc_write(codec, TIMER, ZTM(0x3) \| WTM(0x3));
b91470bb AL	274	snd_soc_write(codec, ALC_CTL1, ALC \| LMTH0);
ed2dd7da	275	snd_soc_update_bits(codec, PW_MGMT1, PMADL, PMADL);
a3471239	276	snd_soc_update_bits(codec, PW_MGMT3, PMADR, PMADR);
a3a83d9a KM	277	}
	278
	279	return 0;
	280	}
	281
	282	static void ak4642_dai_shutdown(struct snd_pcm_substream *substream,
	283	struct snd_soc_dai *dai)
	284	{
	285	int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
	286	struct snd_soc_codec *codec = dai->codec;
	287
	288	if (is_play) {
a3a83d9a KM	289	} else {
a3a83d9a KM	290	/* stop stereo input */
a3471239 KM	291	snd_soc_update_bits(codec, PW_MGMT1, PMADL, 0);
	292	snd_soc_update_bits(codec, PW_MGMT3, PMADR, 0);
	293	snd_soc_update_bits(codec, ALC_CTL1, ALC, 0);
a3a83d9a KM	294	}
	295	}
	296
	297	static int ak4642_dai_set_sysclk(struct snd_soc_dai *codec_dai,
	298	int clk_id, unsigned int freq, int dir)
	299	{
	300	struct snd_soc_codec *codec = codec_dai->codec;
5cd15e29	301	struct ak4642_priv *priv = snd_soc_codec_get_drvdata(codec);
4b6316b4	302	u8 pll;
5cd15e29	303	int extended_freq = 0;
4b6316b4 KM	304
	305	switch (freq) {
	306	case 11289600:
	307	pll = PLL2;
	308	break;
	309	case 12288000:
	310	pll = PLL2 \| PLL0;
	311	break;
	312	case 12000000:
	313	pll = PLL2 \| PLL1;
	314	break;
	315	case 24000000:
	316	pll = PLL2 \| PLL1 \| PLL0;
	317	break;
	318	case 13500000:
	319	pll = PLL3 \| PLL2;
	320	break;
	321	case 27000000:
	322	pll = PLL3 \| PLL2 \| PLL0;
	323	break;
5cd15e29 SH	324	case 19200000:
	325	pll = PLL3;
	326	extended_freq = 1;
	327	break;
	328	case 13000000:
	329	pll = PLL3 \| PLL2 \| PLL1;
	330	extended_freq = 1;
	331	break;
	332	case 26000000:
	333	pll = PLL3 \| PLL2 \| PLL1 \| PLL0;
	334	extended_freq = 1;
	335	break;
4b6316b4 KM	336	default:
	337	return -EINVAL;
	338	}
5cd15e29 SH	339
	340	if (extended_freq && !priv->drvdata->extended_frequencies)
	341	return -EINVAL;
	342
4b6316b4	343	snd_soc_update_bits(codec, MD_CTL1, PLL_MASK, pll);
a3a83d9a	344
a3a83d9a KM	345	return 0;
	346	}
	347
0643ce8f KM	348	static int ak4642_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
	349	{
	350	struct snd_soc_codec *codec = dai->codec;
	351	u8 data;
	352	u8 bcko;
	353
	354	data = MCKO \| PMPLL; /* use MCKO */
	355	bcko = 0;
	356
	357	/* set master/slave audio interface */
	358	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	359	case SND_SOC_DAIFMT_CBM_CFM:
	360	data \|= MS;
	361	bcko = BCKO_64;
	362	break;
	363	case SND_SOC_DAIFMT_CBS_CFS:
	364	break;
	365	default:
	366	return -EINVAL;
	367	}
bd7fdbca	368	snd_soc_update_bits(codec, PW_MGMT2, MS \| MCKO \| PMPLL, data);
0643ce8f KM	369	snd_soc_update_bits(codec, MD_CTL1, BCKO_MASK, bcko);
0643ce8f KM	370
cb9c130a KM	371	/* format type */
	372	data = 0;
	373	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	374	case SND_SOC_DAIFMT_LEFT_J:
	375	data = LEFT_J;
	376	break;
	377	case SND_SOC_DAIFMT_I2S:
	378	data = I2S;
	379	break;
	380	/* FIXME
	381	* Please add RIGHT_J / DSP support here
	382	*/
	383	default:
	384	return -EINVAL;
cb9c130a KM	385	}
	386	snd_soc_update_bits(codec, MD_CTL1, DIF_MASK, data);
	387
0643ce8f KM	388	return 0;
	389	}
	390
1ad747ca KM	391	static int ak4642_dai_hw_params(struct snd_pcm_substream *substream,
	392	struct snd_pcm_hw_params *params,
	393	struct snd_soc_dai *dai)
	394	{
	395	struct snd_soc_codec *codec = dai->codec;
	396	u8 rate;
	397
	398	switch (params_rate(params)) {
	399	case 7350:
	400	rate = FS2;
	401	break;
	402	case 8000:
	403	rate = 0;
	404	break;
	405	case 11025:
	406	rate = FS2 \| FS0;
	407	break;
	408	case 12000:
	409	rate = FS0;
	410	break;
	411	case 14700:
	412	rate = FS2 \| FS1;
	413	break;
	414	case 16000:
	415	rate = FS1;
	416	break;
	417	case 22050:
	418	rate = FS2 \| FS1 \| FS0;
	419	break;
	420	case 24000:
	421	rate = FS1 \| FS0;
	422	break;
	423	case 29400:
	424	rate = FS3 \| FS2 \| FS1;
	425	break;
	426	case 32000:
	427	rate = FS3 \| FS1;
	428	break;
	429	case 44100:
	430	rate = FS3 \| FS2 \| FS1 \| FS0;
	431	break;
	432	case 48000:
	433	rate = FS3 \| FS1 \| FS0;
	434	break;
	435	default:
	436	return -EINVAL;
1ad747ca KM	437	}
1ad747ca KM	438	snd_soc_update_bits(codec, MD_CTL2, FS_MASK, rate);
a3a83d9a	439
a3a83d9a KM	440	return 0;
	441	}
	442
ed2dd7da KM	443	static int ak4642_set_bias_level(struct snd_soc_codec *codec,
	444	enum snd_soc_bias_level level)
	445	{
	446	switch (level) {
	447	case SND_SOC_BIAS_OFF:
	448	snd_soc_write(codec, PW_MGMT1, 0x00);
	449	break;
	450	default:
	451	snd_soc_update_bits(codec, PW_MGMT1, PMVCM, PMVCM);
	452	break;
	453	}
	454	codec->dapm.bias_level = level;
	455
	456	return 0;
	457	}
	458
85e7652d	459	static const struct snd_soc_dai_ops ak4642_dai_ops = {
a3a83d9a KM	460	.startup = ak4642_dai_startup,
	461	.shutdown = ak4642_dai_shutdown,
	462	.set_sysclk = ak4642_dai_set_sysclk,
0643ce8f	463	.set_fmt = ak4642_dai_set_fmt,
1ad747ca	464	.hw_params = ak4642_dai_hw_params,
a3a83d9a KM	465	};
a3a83d9a KM	466
f0fba2ad LG	467	static struct snd_soc_dai_driver ak4642_dai = {
f0fba2ad LG	468	.name = "ak4642-hifi",
a3a83d9a KM	469	.playback = {
	470	.stream_name = "Playback",
	471	.channels_min = 1,
	472	.channels_max = 2,
	473	.rates = SNDRV_PCM_RATE_8000_48000,
	474	.formats = SNDRV_PCM_FMTBIT_S16_LE },
	475	.capture = {
	476	.stream_name = "Capture",
	477	.channels_min = 1,
	478	.channels_max = 2,
	479	.rates = SNDRV_PCM_RATE_8000_48000,
	480	.formats = SNDRV_PCM_FMTBIT_S16_LE },
	481	.ops = &ak4642_dai_ops,
1ad747ca	482	.symmetric_rates = 1,
a3a83d9a	483	};
a3a83d9a	484
f0fba2ad	485	static int ak4642_resume(struct snd_soc_codec *codec)
a3a83d9a	486	{
4574cd94 MB	487	struct regmap *regmap = dev_get_regmap(codec->dev, NULL);
	488
	489	regcache_mark_dirty(regmap);
	490	regcache_sync(regmap);
a3a83d9a KM	491	return 0;
	492	}
	493
f0fba2ad	494	static struct snd_soc_codec_driver soc_codec_dev_ak4642 = {
0ce75aa4	495	.resume = ak4642_resume,
ed2dd7da	496	.set_bias_level = ak4642_set_bias_level,
a8ca52b7 MB	497	.controls = ak4642_snd_controls,
a8ca52b7 MB	498	.num_controls = ARRAY_SIZE(ak4642_snd_controls),
a9317e8b KM	499	.dapm_widgets = ak4642_dapm_widgets,
	500	.num_dapm_widgets = ARRAY_SIZE(ak4642_dapm_widgets),
	501	.dapm_routes = ak4642_intercon,
	502	.num_dapm_routes = ARRAY_SIZE(ak4642_intercon),
	503	};
	504
4574cd94 MB	505	static const struct regmap_config ak4642_regmap = {
	506	.reg_bits = 8,
	507	.val_bits = 8,
	508	.max_register = ARRAY_SIZE(ak4642_reg) + 1,
	509	.reg_defaults = ak4642_reg,
	510	.num_reg_defaults = ARRAY_SIZE(ak4642_reg),
	511	};
	512
	513	static const struct regmap_config ak4648_regmap = {
	514	.reg_bits = 8,
	515	.val_bits = 8,
	516	.max_register = ARRAY_SIZE(ak4648_reg) + 1,
	517	.reg_defaults = ak4648_reg,
	518	.num_reg_defaults = ARRAY_SIZE(ak4648_reg),
f0fba2ad LG	519	};
f0fba2ad LG	520
d815c703 SH	521	static const struct ak4642_drvdata ak4642_drvdata = {
	522	.regmap_config = &ak4642_regmap,
	523	};
	524
	525	static const struct ak4642_drvdata ak4643_drvdata = {
	526	.regmap_config = &ak4642_regmap,
	527	};
	528
	529	static const struct ak4642_drvdata ak4648_drvdata = {
	530	.regmap_config = &ak4648_regmap,
5cd15e29	531	.extended_frequencies = 1,
d815c703 SH	532	};
d815c703 SH	533
27204ca8	534	static const struct of_device_id ak4642_of_match[];
7a79e94e BP	535	static int ak4642_i2c_probe(struct i2c_client *i2c,
7a79e94e BP	536	const struct i2c_device_id *id)
a3a83d9a	537	{
bbf1453e	538	struct device_node *np = i2c->dev.of_node;
d815c703	539	const struct ak4642_drvdata *drvdata = NULL;
4574cd94	540	struct regmap *regmap;
d815c703	541	struct ak4642_priv *priv;
bbf1453e	542
bbf1453e KM	543	if (np) {
	544	const struct of_device_id *of_id;
	545
	546	of_id = of_match_device(ak4642_of_match, &i2c->dev);
	547	if (of_id)
d815c703	548	drvdata = of_id->data;
bbf1453e	549	} else {
d815c703	550	drvdata = (const struct ak4642_drvdata *)id->driver_data;
bbf1453e KM	551	}
bbf1453e KM	552
d815c703	553	if (!drvdata) {
4574cd94	554	dev_err(&i2c->dev, "Unknown device type\n");
bbf1453e KM	555	return -EINVAL;
	556	}
	557
d815c703 SH	558	priv = devm_kzalloc(&i2c->dev, sizeof(*priv), GFP_KERNEL);
	559	if (!priv)
	560	return -ENOMEM;
	561
	562	priv->drvdata = drvdata;
	563
	564	i2c_set_clientdata(i2c, priv);
	565
	566	regmap = devm_regmap_init_i2c(i2c, drvdata->regmap_config);
4574cd94 MB	567	if (IS_ERR(regmap))
	568	return PTR_ERR(regmap);
	569
2f391251	570	return snd_soc_register_codec(&i2c->dev,
4574cd94	571	&soc_codec_dev_ak4642, &ak4642_dai, 1);
a3a83d9a KM	572	}
a3a83d9a KM	573
7a79e94e	574	static int ak4642_i2c_remove(struct i2c_client *client)
a3a83d9a	575	{
f0fba2ad	576	snd_soc_unregister_codec(&client->dev);
a3a83d9a KM	577	return 0;
	578	}
	579
27204ca8	580	static const struct of_device_id ak4642_of_match[] = {
d815c703 SH	581	{ .compatible = "asahi-kasei,ak4642", .data = &ak4642_drvdata},
	582	{ .compatible = "asahi-kasei,ak4643", .data = &ak4643_drvdata},
	583	{ .compatible = "asahi-kasei,ak4648", .data = &ak4648_drvdata},
bbf1453e KM	584	{},
	585	};
	586	MODULE_DEVICE_TABLE(of, ak4642_of_match);
	587
a3a83d9a	588	static const struct i2c_device_id ak4642_i2c_id[] = {
d815c703 SH	589	{ "ak4642", (kernel_ulong_t)&ak4642_drvdata },
	590	{ "ak4643", (kernel_ulong_t)&ak4643_drvdata },
	591	{ "ak4648", (kernel_ulong_t)&ak4648_drvdata },
a3a83d9a KM	592	{ }
	593	};
	594	MODULE_DEVICE_TABLE(i2c, ak4642_i2c_id);
	595
	596	static struct i2c_driver ak4642_i2c_driver = {
	597	.driver = {
f0fba2ad	598	.name = "ak4642-codec",
a3a83d9a	599	.owner = THIS_MODULE,
bbf1453e	600	.of_match_table = ak4642_of_match,
a3a83d9a	601	},
0ce75aa4	602	.probe = ak4642_i2c_probe,
7a79e94e	603	.remove = ak4642_i2c_remove,
0ce75aa4	604	.id_table = ak4642_i2c_id,
a3a83d9a	605	};
a3a83d9a	606
2f54d2a1	607	module_i2c_driver(ak4642_i2c_driver);
a3a83d9a KM	608
	609	MODULE_DESCRIPTION("Soc AK4642 driver");
	610	MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
	611	MODULE_LICENSE("GPL");