[deliverable/linux.git] / sound / soc / codecs / ak4642.c

/*
 * ak4642.c  --  AK4642/AK4643 ALSA Soc Audio driver
 *
 * Copyright (C) 2009 Renesas Solutions Corp.
 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
 *
 * Based on wm8731.c by Richard Purdie
 * Based on ak4535.c by Richard Purdie
 * Based on wm8753.c by Liam Girdwood
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/* ** CAUTION **
 *
 * This is very simple driver.
 * It can use headphone output / stereo input only
 *
 * AK4642 is not tested.
 * AK4643 is tested.
 */

#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>

#define AK4642_VERSION "0.0.1"

#define PW_MGMT1	0x00
#define PW_MGMT2	0x01
#define SG_SL1		0x02
#define SG_SL2		0x03
#define MD_CTL1		0x04
#define MD_CTL2		0x05
#define TIMER		0x06
#define ALC_CTL1	0x07
#define ALC_CTL2	0x08
#define L_IVC		0x09
#define L_DVC		0x0a
#define ALC_CTL3	0x0b
#define R_IVC		0x0c
#define R_DVC		0x0d
#define MD_CTL3		0x0e
#define MD_CTL4		0x0f
#define PW_MGMT3	0x10
#define DF_S		0x11
#define FIL3_0		0x12
#define FIL3_1		0x13
#define FIL3_2		0x14
#define FIL3_3		0x15
#define EQ_0		0x16
#define EQ_1		0x17
#define EQ_2		0x18
#define EQ_3		0x19
#define EQ_4		0x1a
#define EQ_5		0x1b
#define FIL1_0		0x1c
#define FIL1_1		0x1d
#define FIL1_2		0x1e
#define FIL1_3		0x1f
#define PW_MGMT4	0x20
#define MD_CTL5		0x21
#define LO_MS		0x22
#define HP_MS		0x23
#define SPK_MS		0x24

#define AK4642_CACHEREGNUM 	0x25

/* PW_MGMT1*/
#define PMVCM		(1 << 6) /* VCOM Power Management */
#define PMMIN		(1 << 5) /* MIN Input Power Management */
#define PMDAC		(1 << 2) /* DAC Power Management */
#define PMADL		(1 << 0) /* MIC Amp Lch and ADC Lch Power Management */

/* PW_MGMT2 */
#define HPMTN		(1 << 6)
#define PMHPL		(1 << 5)
#define PMHPR		(1 << 4)
#define MS		(1 << 3) /* master/slave select */
#define MCKO		(1 << 1)
#define PMPLL		(1 << 0)

#define PMHP_MASK	(PMHPL | PMHPR)
#define PMHP		PMHP_MASK

/* PW_MGMT3 */
#define PMADR		(1 << 0) /* MIC L / ADC R Power Management */

/* SG_SL1 */
#define MINS		(1 << 6) /* Switch from MIN to Speaker */
#define DACL		(1 << 4) /* Switch from DAC to Stereo or Receiver */
#define PMMP		(1 << 2) /* MPWR pin Power Management */
#define MGAIN0		(1 << 0) /* MIC amp gain*/

/* TIMER */
#define ZTM(param)	((param & 0x3) << 4) /* ALC Zoro Crossing TimeOut */
#define WTM(param)	(((param & 0x4) << 4) | ((param & 0x3) << 2))

/* ALC_CTL1 */
#define ALC		(1 << 5) /* ALC Enable */
#define LMTH0		(1 << 0) /* ALC Limiter / Recovery Level */

/* MD_CTL1 */
#define PLL3		(1 << 7)
#define PLL2		(1 << 6)
#define PLL1		(1 << 5)
#define PLL0		(1 << 4)
#define PLL_MASK	(PLL3 | PLL2 | PLL1 | PLL0)

#define BCKO_MASK	(1 << 3)
#define BCKO_64		BCKO_MASK

/* MD_CTL2 */
#define FS0		(1 << 0)
#define FS1		(1 << 1)
#define FS2		(1 << 2)
#define FS3		(1 << 5)
#define FS_MASK		(FS0 | FS1 | FS2 | FS3)

/* MD_CTL3 */
#define BST1		(1 << 3)

/* MD_CTL4 */
#define DACH		(1 << 0)

/*
 * Playback Volume (table 39)
 *
 * max : 0x00 : +12.0 dB
 *       ( 0.5 dB step )
 * min : 0xFE : -115.0 dB
 * mute: 0xFF
 */
static const DECLARE_TLV_DB_SCALE(out_tlv, -11500, 50, 1);

static const struct snd_kcontrol_new ak4642_snd_controls[] = {

	SOC_DOUBLE_R_TLV("Digital Playback Volume", L_DVC, R_DVC,
			 0, 0xFF, 1, out_tlv),
};


/* codec private data */
struct ak4642_priv {
	unsigned int sysclk;
	enum snd_soc_control_type control_type;
	void *control_data;
};

/*
 * ak4642 register cache
 */
static const u16 ak4642_reg[AK4642_CACHEREGNUM] = {
	0x0000, 0x0000, 0x0001, 0x0000,
	0x0002, 0x0000, 0x0000, 0x0000,
	0x00e1, 0x00e1, 0x0018, 0x0000,
	0x00e1, 0x0018, 0x0011, 0x0008,
	0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000,
	0x0000,
};

/*
 * read ak4642 register cache
 */
static inline unsigned int ak4642_read_reg_cache(struct snd_soc_codec *codec,
	unsigned int reg)
{
	u16 *cache = codec->reg_cache;
	if (reg >= AK4642_CACHEREGNUM)
		return -1;
	return cache[reg];
}

/*
 * write ak4642 register cache
 */
static inline void ak4642_write_reg_cache(struct snd_soc_codec *codec,
	u16 reg, unsigned int value)
{
	u16 *cache = codec->reg_cache;
	if (reg >= AK4642_CACHEREGNUM)
		return;

	cache[reg] = value;
}

/*
 * write to the AK4642 register space
 */
static int ak4642_write(struct snd_soc_codec *codec, unsigned int reg,
	unsigned int value)
{
	u8 data[2];

	/* data is
	 *   D15..D8 AK4642 register offset
	 *   D7...D0 register data
	 */
	data[0] = reg & 0xff;
	data[1] = value & 0xff;

	if (codec->hw_write(codec->control_data, data, 2) == 2) {
		ak4642_write_reg_cache(codec, reg, value);
		return 0;
	} else
		return -EIO;
}

static int ak4642_sync(struct snd_soc_codec *codec)
{
	u16 *cache = codec->reg_cache;
	int i, r = 0;

	for (i = 0; i < AK4642_CACHEREGNUM; i++)
		r |= ak4642_write(codec, i, cache[i]);

	return r;
};

static int ak4642_dai_startup(struct snd_pcm_substream *substream,
			      struct snd_soc_dai *dai)
{
	int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
	struct snd_soc_codec *codec = dai->codec;

	if (is_play) {
		/*
		 * start headphone output
		 *
		 * PLL, Master Mode
		 * Audio I/F Format :MSB justified (ADC & DAC)
		 * Bass Boost Level : Middle
		 *
		 * This operation came from example code of
		 * "ASAHI KASEI AK4642" (japanese) manual p97.
		 */
		snd_soc_update_bits(codec, MD_CTL4, DACH, DACH);
		snd_soc_update_bits(codec, MD_CTL3, BST1, BST1);
		ak4642_write(codec, L_IVC, 0x91); /* volume */
		ak4642_write(codec, R_IVC, 0x91); /* volume */
		snd_soc_update_bits(codec, PW_MGMT1, PMVCM | PMMIN | PMDAC,
						     PMVCM | PMMIN | PMDAC);
		snd_soc_update_bits(codec, PW_MGMT2, PMHP_MASK,	PMHP);
		snd_soc_update_bits(codec, PW_MGMT2, HPMTN,	HPMTN);
	} else {
		/*
		 * start stereo input
		 *
		 * PLL Master Mode
		 * Audio I/F Format:MSB justified (ADC & DAC)
		 * Pre MIC AMP:+20dB
		 * MIC Power On
		 * ALC setting:Refer to Table 35
		 * ALC bit=“1”
		 *
		 * This operation came from example code of
		 * "ASAHI KASEI AK4642" (japanese) manual p94.
		 */
		ak4642_write(codec, SG_SL1, PMMP | MGAIN0);
		ak4642_write(codec, TIMER, ZTM(0x3) | WTM(0x3));
		ak4642_write(codec, ALC_CTL1, ALC | LMTH0);
		snd_soc_update_bits(codec, PW_MGMT1, PMVCM | PMADL,
						     PMVCM | PMADL);
		snd_soc_update_bits(codec, PW_MGMT3, PMADR, PMADR);
	}

	return 0;
}

static void ak4642_dai_shutdown(struct snd_pcm_substream *substream,
			       struct snd_soc_dai *dai)
{
	int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
	struct snd_soc_codec *codec = dai->codec;

	if (is_play) {
		/* stop headphone output */
		snd_soc_update_bits(codec, PW_MGMT2, HPMTN,	0);
		snd_soc_update_bits(codec, PW_MGMT2, PMHP_MASK,	0);
		snd_soc_update_bits(codec, PW_MGMT1, PMMIN | PMDAC, 0);
		snd_soc_update_bits(codec, MD_CTL3, BST1, 0);
		snd_soc_update_bits(codec, MD_CTL4, DACH, 0);
	} else {
		/* stop stereo input */
		snd_soc_update_bits(codec, PW_MGMT1, PMADL, 0);
		snd_soc_update_bits(codec, PW_MGMT3, PMADR, 0);
		snd_soc_update_bits(codec, ALC_CTL1, ALC, 0);
	}
}

static int ak4642_dai_set_sysclk(struct snd_soc_dai *codec_dai,
	int clk_id, unsigned int freq, int dir)
{
	struct snd_soc_codec *codec = codec_dai->codec;
	u8 pll;

	switch (freq) {
	case 11289600:
		pll = PLL2;
		break;
	case 12288000:
		pll = PLL2 | PLL0;
		break;
	case 12000000:
		pll = PLL2 | PLL1;
		break;
	case 24000000:
		pll = PLL2 | PLL1 | PLL0;
		break;
	case 13500000:
		pll = PLL3 | PLL2;
		break;
	case 27000000:
		pll = PLL3 | PLL2 | PLL0;
		break;
	default:
		return -EINVAL;
	}
	snd_soc_update_bits(codec, MD_CTL1, PLL_MASK, pll);

	return 0;
}

static int ak4642_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
	struct snd_soc_codec *codec = dai->codec;
	u8 data;
	u8 bcko;

	data = MCKO | PMPLL; /* use MCKO */
	bcko = 0;

	/* set master/slave audio interface */
	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBM_CFM:
		data |= MS;
		bcko = BCKO_64;
		break;
	case SND_SOC_DAIFMT_CBS_CFS:
		break;
	default:
		return -EINVAL;
	}
	snd_soc_update_bits(codec, PW_MGMT2, MS, data);
	snd_soc_update_bits(codec, MD_CTL1, BCKO_MASK, bcko);

	return 0;
}

static int ak4642_dai_hw_params(struct snd_pcm_substream *substream,
				struct snd_pcm_hw_params *params,
				struct snd_soc_dai *dai)
{
	struct snd_soc_codec *codec = dai->codec;
	u8 rate;

	switch (params_rate(params)) {
	case 7350:
		rate = FS2;
		break;
	case 8000:
		rate = 0;
		break;
	case 11025:
		rate = FS2 | FS0;
		break;
	case 12000:
		rate = FS0;
		break;
	case 14700:
		rate = FS2 | FS1;
		break;
	case 16000:
		rate = FS1;
		break;
	case 22050:
		rate = FS2 | FS1 | FS0;
		break;
	case 24000:
		rate = FS1 | FS0;
		break;
	case 29400:
		rate = FS3 | FS2 | FS1;
		break;
	case 32000:
		rate = FS3 | FS1;
		break;
	case 44100:
		rate = FS3 | FS2 | FS1 | FS0;
		break;
	case 48000:
		rate = FS3 | FS1 | FS0;
		break;
	default:
		return -EINVAL;
		break;
	}
	snd_soc_update_bits(codec, MD_CTL2, FS_MASK, rate);

	return 0;
}

static struct snd_soc_dai_ops ak4642_dai_ops = {
	.startup	= ak4642_dai_startup,
	.shutdown	= ak4642_dai_shutdown,
	.set_sysclk	= ak4642_dai_set_sysclk,
	.set_fmt	= ak4642_dai_set_fmt,
	.hw_params	= ak4642_dai_hw_params,
};

static struct snd_soc_dai_driver ak4642_dai = {
	.name = "ak4642-hifi",
	.playback = {
		.stream_name = "Playback",
		.channels_min = 1,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_48000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE },
	.capture = {
		.stream_name = "Capture",
		.channels_min = 1,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_48000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE },
	.ops = &ak4642_dai_ops,
	.symmetric_rates = 1,
};

static int ak4642_resume(struct snd_soc_codec *codec)
{
	ak4642_sync(codec);
	return 0;
}


static int ak4642_probe(struct snd_soc_codec *codec)
{
	struct ak4642_priv *ak4642 = snd_soc_codec_get_drvdata(codec);

	dev_info(codec->dev, "AK4642 Audio Codec %s", AK4642_VERSION);

	codec->hw_write		= (hw_write_t)i2c_master_send;
	codec->control_data	= ak4642->control_data;

	snd_soc_add_controls(codec, ak4642_snd_controls,
			     ARRAY_SIZE(ak4642_snd_controls));

	return 0;
}

static struct snd_soc_codec_driver soc_codec_dev_ak4642 = {
	.probe			= ak4642_probe,
	.resume			= ak4642_resume,
	.read			= ak4642_read_reg_cache,
	.write			= ak4642_write,
	.reg_cache_size		= ARRAY_SIZE(ak4642_reg),
	.reg_word_size		= sizeof(u8),
	.reg_cache_default	= ak4642_reg,
};

#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
static __devinit int ak4642_i2c_probe(struct i2c_client *i2c,
				      const struct i2c_device_id *id)
{
	struct ak4642_priv *ak4642;
	int ret;

	ak4642 = kzalloc(sizeof(struct ak4642_priv), GFP_KERNEL);
	if (!ak4642)
		return -ENOMEM;

	i2c_set_clientdata(i2c, ak4642);
	ak4642->control_data = i2c;
	ak4642->control_type = SND_SOC_I2C;

	ret =  snd_soc_register_codec(&i2c->dev,
			&soc_codec_dev_ak4642, &ak4642_dai, 1);
	if (ret < 0)
		kfree(ak4642);
	return ret;
}

static __devexit int ak4642_i2c_remove(struct i2c_client *client)
{
	snd_soc_unregister_codec(&client->dev);
	kfree(i2c_get_clientdata(client));
	return 0;
}

static const struct i2c_device_id ak4642_i2c_id[] = {
	{ "ak4642", 0 },
	{ "ak4643", 0 },
	{ }
};
MODULE_DEVICE_TABLE(i2c, ak4642_i2c_id);

static struct i2c_driver ak4642_i2c_driver = {
	.driver = {
		.name = "ak4642-codec",
		.owner = THIS_MODULE,
	},
	.probe		= ak4642_i2c_probe,
	.remove		= __devexit_p(ak4642_i2c_remove),
	.id_table	= ak4642_i2c_id,
};
#endif

static int __init ak4642_modinit(void)
{
	int ret = 0;
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
	ret = i2c_add_driver(&ak4642_i2c_driver);
#endif
	return ret;

}
module_init(ak4642_modinit);

static void __exit ak4642_exit(void)
{
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
	i2c_del_driver(&ak4642_i2c_driver);
#endif

}
module_exit(ak4642_exit);

MODULE_DESCRIPTION("Soc AK4642 driver");
MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
a3a83d9a KM	1	/*
	2	* ak4642.c -- AK4642/AK4643 ALSA Soc Audio driver
	3	*
	4	* Copyright (C) 2009 Renesas Solutions Corp.
	5	* Kuninori Morimoto <morimoto.kuninori@renesas.com>
	6	*
	7	* Based on wm8731.c by Richard Purdie
	8	* Based on ak4535.c by Richard Purdie
	9	* Based on wm8753.c by Liam Girdwood
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	/* CAUTION
	17	*
	18	* This is very simple driver.
	19	* It can use headphone output / stereo input only
	20	*
	21	* AK4642 is not tested.
	22	* AK4643 is tested.
	23	*/
	24
a3a83d9a	25	#include <linux/delay.h>
a3a83d9a KM	26	#include <linux/i2c.h>
a3a83d9a KM	27	#include <linux/platform_device.h>
5a0e3ad6	28	#include <linux/slab.h>
ce6120cc	29	#include <sound/soc.h>
a3a83d9a	30	#include <sound/initval.h>
a300de3c	31	#include <sound/tlv.h>
a3a83d9a	32
a3a83d9a KM	33	#define AK4642_VERSION "0.0.1"
	34
	35	#define PW_MGMT1 0x00
	36	#define PW_MGMT2 0x01
	37	#define SG_SL1 0x02
	38	#define SG_SL2 0x03
	39	#define MD_CTL1 0x04
	40	#define MD_CTL2 0x05
	41	#define TIMER 0x06
	42	#define ALC_CTL1 0x07
	43	#define ALC_CTL2 0x08
	44	#define L_IVC 0x09
	45	#define L_DVC 0x0a
	46	#define ALC_CTL3 0x0b
	47	#define R_IVC 0x0c
	48	#define R_DVC 0x0d
	49	#define MD_CTL3 0x0e
	50	#define MD_CTL4 0x0f
	51	#define PW_MGMT3 0x10
	52	#define DF_S 0x11
	53	#define FIL3_0 0x12
	54	#define FIL3_1 0x13
	55	#define FIL3_2 0x14
	56	#define FIL3_3 0x15
	57	#define EQ_0 0x16
	58	#define EQ_1 0x17
	59	#define EQ_2 0x18
	60	#define EQ_3 0x19
	61	#define EQ_4 0x1a
	62	#define EQ_5 0x1b
	63	#define FIL1_0 0x1c
	64	#define FIL1_1 0x1d
	65	#define FIL1_2 0x1e
	66	#define FIL1_3 0x1f
	67	#define PW_MGMT4 0x20
	68	#define MD_CTL5 0x21
	69	#define LO_MS 0x22
	70	#define HP_MS 0x23
	71	#define SPK_MS 0x24
	72
	73	#define AK4642_CACHEREGNUM 0x25
	74
a3471239 KM	75	/* PW_MGMT1*/
	76	#define PMVCM (1 << 6) /* VCOM Power Management */
	77	#define PMMIN (1 << 5) /* MIN Input Power Management */
	78	#define PMDAC (1 << 2) /* DAC Power Management */
	79	#define PMADL (1 << 0) /* MIC Amp Lch and ADC Lch Power Management */
	80
0643ce8f KM	81	/* PW_MGMT2 */
	82	#define HPMTN (1 << 6)
	83	#define PMHPL (1 << 5)
	84	#define PMHPR (1 << 4)
	85	#define MS (1 << 3) /* master/slave select */
	86	#define MCKO (1 << 1)
	87	#define PMPLL (1 << 0)
	88
	89	#define PMHP_MASK (PMHPL \| PMHPR)
	90	#define PMHP PMHP_MASK
	91
a3471239 KM	92	/* PW_MGMT3 */
	93	#define PMADR (1 << 0) /* MIC L / ADC R Power Management */
	94
	95	/* SG_SL1 */
	96	#define MINS (1 << 6) /* Switch from MIN to Speaker */
	97	#define DACL (1 << 4) /* Switch from DAC to Stereo or Receiver */
	98	#define PMMP (1 << 2) /* MPWR pin Power Management */
	99	#define MGAIN0 (1 << 0) /* MIC amp gain*/
	100
	101	/* TIMER */
	102	#define ZTM(param) ((param & 0x3) << 4) /* ALC Zoro Crossing TimeOut */
	103	#define WTM(param) (((param & 0x4) << 4) \| ((param & 0x3) << 2))
	104
	105	/* ALC_CTL1 */
	106	#define ALC (1 << 5) /* ALC Enable */
	107	#define LMTH0 (1 << 0) /* ALC Limiter / Recovery Level */
	108
4b6316b4 KM	109	/* MD_CTL1 */
	110	#define PLL3 (1 << 7)
	111	#define PLL2 (1 << 6)
	112	#define PLL1 (1 << 5)
	113	#define PLL0 (1 << 4)
	114	#define PLL_MASK (PLL3 \| PLL2 \| PLL1 \| PLL0)
	115
0643ce8f KM	116	#define BCKO_MASK (1 << 3)
	117	#define BCKO_64 BCKO_MASK
	118
1ad747ca KM	119	/* MD_CTL2 */
	120	#define FS0 (1 << 0)
	121	#define FS1 (1 << 1)
	122	#define FS2 (1 << 2)
	123	#define FS3 (1 << 5)
	124	#define FS_MASK (FS0 \| FS1 \| FS2 \| FS3)
	125
a3471239 KM	126	/* MD_CTL3 */
	127	#define BST1 (1 << 3)
	128
	129	/* MD_CTL4 */
	130	#define DACH (1 << 0)
a3a83d9a	131
a300de3c KM	132	/*
	133	* Playback Volume (table 39)
	134	*
	135	* max : 0x00 : +12.0 dB
	136	* ( 0.5 dB step )
	137	* min : 0xFE : -115.0 dB
	138	* mute: 0xFF
	139	*/
	140	static const DECLARE_TLV_DB_SCALE(out_tlv, -11500, 50, 1);
	141
	142	static const struct snd_kcontrol_new ak4642_snd_controls[] = {
	143
	144	SOC_DOUBLE_R_TLV("Digital Playback Volume", L_DVC, R_DVC,
	145	0, 0xFF, 1, out_tlv),
	146	};
	147
	148
a3a83d9a KM	149	/* codec private data */
a3a83d9a KM	150	struct ak4642_priv {
f0fba2ad LG	151	unsigned int sysclk;
	152	enum snd_soc_control_type control_type;
	153	void *control_data;
a3a83d9a KM	154	};
a3a83d9a KM	155
a3a83d9a KM	156	/*
	157	* ak4642 register cache
	158	*/
	159	static const u16 ak4642_reg[AK4642_CACHEREGNUM] = {
	160	0x0000, 0x0000, 0x0001, 0x0000,
	161	0x0002, 0x0000, 0x0000, 0x0000,
	162	0x00e1, 0x00e1, 0x0018, 0x0000,
	163	0x00e1, 0x0018, 0x0011, 0x0008,
	164	0x0000, 0x0000, 0x0000, 0x0000,
	165	0x0000, 0x0000, 0x0000, 0x0000,
	166	0x0000, 0x0000, 0x0000, 0x0000,
	167	0x0000, 0x0000, 0x0000, 0x0000,
	168	0x0000, 0x0000, 0x0000, 0x0000,
	169	0x0000,
	170	};
	171
	172	/*
	173	* read ak4642 register cache
	174	*/
	175	static inline unsigned int ak4642_read_reg_cache(struct snd_soc_codec *codec,
	176	unsigned int reg)
	177	{
	178	u16 *cache = codec->reg_cache;
	179	if (reg >= AK4642_CACHEREGNUM)
	180	return -1;
	181	return cache[reg];
	182	}
	183
	184	/*
	185	* write ak4642 register cache
	186	*/
	187	static inline void ak4642_write_reg_cache(struct snd_soc_codec *codec,
	188	u16 reg, unsigned int value)
	189	{
	190	u16 *cache = codec->reg_cache;
	191	if (reg >= AK4642_CACHEREGNUM)
	192	return;
	193
	194	cache[reg] = value;
	195	}
	196
	197	/*
	198	* write to the AK4642 register space
	199	*/
	200	static int ak4642_write(struct snd_soc_codec *codec, unsigned int reg,
	201	unsigned int value)
	202	{
	203	u8 data[2];
	204
	205	/* data is
	206	* D15..D8 AK4642 register offset
	207	* D7...D0 register data
	208	*/
	209	data[0] = reg & 0xff;
	210	data[1] = value & 0xff;
	211
	212	if (codec->hw_write(codec->control_data, data, 2) == 2) {
	213	ak4642_write_reg_cache(codec, reg, value);
	214	return 0;
	215	} else
	216	return -EIO;
	217	}
	218
	219	static int ak4642_sync(struct snd_soc_codec *codec)
220	{
221	u16 *cache = codec->reg_cache;
222	int i, r = 0;
223
224	for (i = 0; i < AK4642_CACHEREGNUM; i++)
225	r \|= ak4642_write(codec, i, cache[i]);
226
227	return r;
228	};
229
230	static int ak4642_dai_startup(struct snd_pcm_substream *substream,
231	struct snd_soc_dai *dai)
232	{
233	int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
234	struct snd_soc_codec *codec = dai->codec;
235
236	if (is_play) {
237	/*
238	* start headphone output
239	*
240	* PLL, Master Mode
241	* Audio I/F Format :MSB justified (ADC & DAC)
a3a83d9a KM	242	* Bass Boost Level : Middle
	243	*
	244	* This operation came from example code of
	245	* "ASAHI KASEI AK4642" (japanese) manual p97.
a3a83d9a	246	*/
a3471239 KM	247	snd_soc_update_bits(codec, MD_CTL4, DACH, DACH);
	248	snd_soc_update_bits(codec, MD_CTL3, BST1, BST1);
	249	ak4642_write(codec, L_IVC, 0x91); /* volume */
	250	ak4642_write(codec, R_IVC, 0x91); /* volume */
	251	snd_soc_update_bits(codec, PW_MGMT1, PMVCM \| PMMIN \| PMDAC,
	252	PMVCM \| PMMIN \| PMDAC);
0643ce8f KM	253	snd_soc_update_bits(codec, PW_MGMT2, PMHP_MASK, PMHP);
0643ce8f KM	254	snd_soc_update_bits(codec, PW_MGMT2, HPMTN, HPMTN);
a3a83d9a KM	255	} else {
	256	/*
	257	* start stereo input
	258	*
	259	* PLL Master Mode
	260	* Audio I/F Format:MSB justified (ADC & DAC)
a3a83d9a KM	261	* Pre MIC AMP:+20dB
	262	* MIC Power On
	263	* ALC setting:Refer to Table 35
	264	* ALC bit=“1”
	265	*
	266	* This operation came from example code of
	267	* "ASAHI KASEI AK4642" (japanese) manual p94.
	268	*/
a3471239 KM	269	ak4642_write(codec, SG_SL1, PMMP \| MGAIN0);
	270	ak4642_write(codec, TIMER, ZTM(0x3) \| WTM(0x3));
	271	ak4642_write(codec, ALC_CTL1, ALC \| LMTH0);
	272	snd_soc_update_bits(codec, PW_MGMT1, PMVCM \| PMADL,
	273	PMVCM \| PMADL);
	274	snd_soc_update_bits(codec, PW_MGMT3, PMADR, PMADR);
a3a83d9a KM	275	}
	276
	277	return 0;
	278	}
	279
	280	static void ak4642_dai_shutdown(struct snd_pcm_substream *substream,
	281	struct snd_soc_dai *dai)
	282	{
	283	int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
	284	struct snd_soc_codec *codec = dai->codec;
	285
	286	if (is_play) {
	287	/* stop headphone output */
0643ce8f KM	288	snd_soc_update_bits(codec, PW_MGMT2, HPMTN, 0);
0643ce8f KM	289	snd_soc_update_bits(codec, PW_MGMT2, PMHP_MASK, 0);
a3471239 KM	290	snd_soc_update_bits(codec, PW_MGMT1, PMMIN \| PMDAC, 0);
	291	snd_soc_update_bits(codec, MD_CTL3, BST1, 0);
	292	snd_soc_update_bits(codec, MD_CTL4, DACH, 0);
a3a83d9a KM	293	} else {
a3a83d9a KM	294	/* stop stereo input */
a3471239 KM	295	snd_soc_update_bits(codec, PW_MGMT1, PMADL, 0);
	296	snd_soc_update_bits(codec, PW_MGMT3, PMADR, 0);
	297	snd_soc_update_bits(codec, ALC_CTL1, ALC, 0);
a3a83d9a KM	298	}
	299	}
	300
	301	static int ak4642_dai_set_sysclk(struct snd_soc_dai *codec_dai,
	302	int clk_id, unsigned int freq, int dir)
	303	{
	304	struct snd_soc_codec *codec = codec_dai->codec;
4b6316b4 KM	305	u8 pll;
	306
	307	switch (freq) {
	308	case 11289600:
	309	pll = PLL2;
	310	break;
	311	case 12288000:
	312	pll = PLL2 \| PLL0;
	313	break;
	314	case 12000000:
	315	pll = PLL2 \| PLL1;
	316	break;
	317	case 24000000:
	318	pll = PLL2 \| PLL1 \| PLL0;
	319	break;
	320	case 13500000:
	321	pll = PLL3 \| PLL2;
	322	break;
	323	case 27000000:
	324	pll = PLL3 \| PLL2 \| PLL0;
	325	break;
	326	default:
	327	return -EINVAL;
	328	}
	329	snd_soc_update_bits(codec, MD_CTL1, PLL_MASK, pll);
a3a83d9a	330
a3a83d9a KM	331	return 0;
	332	}
	333
0643ce8f KM	334	static int ak4642_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
	335	{
	336	struct snd_soc_codec *codec = dai->codec;
	337	u8 data;
	338	u8 bcko;
	339
	340	data = MCKO \| PMPLL; /* use MCKO */
	341	bcko = 0;
	342
	343	/* set master/slave audio interface */
	344	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	345	case SND_SOC_DAIFMT_CBM_CFM:
	346	data \|= MS;
	347	bcko = BCKO_64;
	348	break;
	349	case SND_SOC_DAIFMT_CBS_CFS:
	350	break;
	351	default:
	352	return -EINVAL;
	353	}
	354	snd_soc_update_bits(codec, PW_MGMT2, MS, data);
	355	snd_soc_update_bits(codec, MD_CTL1, BCKO_MASK, bcko);
	356
	357	return 0;
	358	}
	359
1ad747ca KM	360	static int ak4642_dai_hw_params(struct snd_pcm_substream *substream,
	361	struct snd_pcm_hw_params *params,
	362	struct snd_soc_dai *dai)
	363	{
	364	struct snd_soc_codec *codec = dai->codec;
	365	u8 rate;
	366
	367	switch (params_rate(params)) {
	368	case 7350:
	369	rate = FS2;
	370	break;
	371	case 8000:
	372	rate = 0;
	373	break;
	374	case 11025:
	375	rate = FS2 \| FS0;
	376	break;
	377	case 12000:
	378	rate = FS0;
	379	break;
	380	case 14700:
	381	rate = FS2 \| FS1;
	382	break;
	383	case 16000:
	384	rate = FS1;
	385	break;
	386	case 22050:
	387	rate = FS2 \| FS1 \| FS0;
	388	break;
	389	case 24000:
	390	rate = FS1 \| FS0;
	391	break;
	392	case 29400:
	393	rate = FS3 \| FS2 \| FS1;
	394	break;
	395	case 32000:
	396	rate = FS3 \| FS1;
	397	break;
	398	case 44100:
	399	rate = FS3 \| FS2 \| FS1 \| FS0;
	400	break;
	401	case 48000:
	402	rate = FS3 \| FS1 \| FS0;
	403	break;
	404	default:
	405	return -EINVAL;
	406	break;
	407	}
	408	snd_soc_update_bits(codec, MD_CTL2, FS_MASK, rate);
a3a83d9a	409
a3a83d9a KM	410	return 0;
	411	}
	412
	413	static struct snd_soc_dai_ops ak4642_dai_ops = {
	414	.startup = ak4642_dai_startup,
	415	.shutdown = ak4642_dai_shutdown,
	416	.set_sysclk = ak4642_dai_set_sysclk,
0643ce8f	417	.set_fmt = ak4642_dai_set_fmt,
1ad747ca	418	.hw_params = ak4642_dai_hw_params,
a3a83d9a KM	419	};
a3a83d9a KM	420
f0fba2ad LG	421	static struct snd_soc_dai_driver ak4642_dai = {
f0fba2ad LG	422	.name = "ak4642-hifi",
a3a83d9a KM	423	.playback = {
	424	.stream_name = "Playback",
	425	.channels_min = 1,
	426	.channels_max = 2,
	427	.rates = SNDRV_PCM_RATE_8000_48000,
	428	.formats = SNDRV_PCM_FMTBIT_S16_LE },
	429	.capture = {
	430	.stream_name = "Capture",
	431	.channels_min = 1,
	432	.channels_max = 2,
	433	.rates = SNDRV_PCM_RATE_8000_48000,
	434	.formats = SNDRV_PCM_FMTBIT_S16_LE },
	435	.ops = &ak4642_dai_ops,
1ad747ca	436	.symmetric_rates = 1,
a3a83d9a	437	};
a3a83d9a	438
f0fba2ad	439	static int ak4642_resume(struct snd_soc_codec *codec)
a3a83d9a	440	{
a3a83d9a KM	441	ak4642_sync(codec);
	442	return 0;
	443	}
	444
f0fba2ad LG	445
f0fba2ad LG	446	static int ak4642_probe(struct snd_soc_codec *codec)
a3a83d9a	447	{
f0fba2ad	448	struct ak4642_priv *ak4642 = snd_soc_codec_get_drvdata(codec);
a3a83d9a	449
f0fba2ad	450	dev_info(codec->dev, "AK4642 Audio Codec %s", AK4642_VERSION);
a3a83d9a	451
a3a83d9a	452	codec->hw_write = (hw_write_t)i2c_master_send;
0ce75aa4	453	codec->control_data = ak4642->control_data;
a3a83d9a	454
73bb379f KM	455	snd_soc_add_controls(codec, ak4642_snd_controls,
73bb379f KM	456	ARRAY_SIZE(ak4642_snd_controls));
a3a83d9a	457
f0fba2ad	458	return 0;
a3a83d9a KM	459	}
a3a83d9a KM	460
f0fba2ad	461	static struct snd_soc_codec_driver soc_codec_dev_ak4642 = {
0ce75aa4 KM	462	.probe = ak4642_probe,
	463	.resume = ak4642_resume,
	464	.read = ak4642_read_reg_cache,
	465	.write = ak4642_write,
	466	.reg_cache_size = ARRAY_SIZE(ak4642_reg),
	467	.reg_word_size = sizeof(u8),
f0fba2ad LG	468	.reg_cache_default = ak4642_reg,
	469	};
	470
a3a83d9a	471	#if defined(CONFIG_I2C) \|\| defined(CONFIG_I2C_MODULE)
f0fba2ad LG	472	static __devinit int ak4642_i2c_probe(struct i2c_client *i2c,
f0fba2ad LG	473	const struct i2c_device_id *id)
a3a83d9a KM	474	{
a3a83d9a KM	475	struct ak4642_priv *ak4642;
a3a83d9a KM	476	int ret;
	477
	478	ak4642 = kzalloc(sizeof(struct ak4642_priv), GFP_KERNEL);
0ce75aa4	479	if (!ak4642)
a3a83d9a KM	480	return -ENOMEM;
a3a83d9a KM	481
a3a83d9a	482	i2c_set_clientdata(i2c, ak4642);
f0fba2ad LG	483	ak4642->control_data = i2c;
f0fba2ad LG	484	ak4642->control_type = SND_SOC_I2C;
a3a83d9a	485
f0fba2ad LG	486	ret = snd_soc_register_codec(&i2c->dev,
	487	&soc_codec_dev_ak4642, &ak4642_dai, 1);
	488	if (ret < 0)
7bcaad91	489	kfree(ak4642);
a3a83d9a KM	490	return ret;
	491	}
	492
f0fba2ad	493	static __devexit int ak4642_i2c_remove(struct i2c_client *client)
a3a83d9a	494	{
f0fba2ad LG	495	snd_soc_unregister_codec(&client->dev);
f0fba2ad LG	496	kfree(i2c_get_clientdata(client));
a3a83d9a KM	497	return 0;
	498	}
	499
	500	static const struct i2c_device_id ak4642_i2c_id[] = {
	501	{ "ak4642", 0 },
	502	{ "ak4643", 0 },
	503	{ }
	504	};
	505	MODULE_DEVICE_TABLE(i2c, ak4642_i2c_id);
	506
	507	static struct i2c_driver ak4642_i2c_driver = {
	508	.driver = {
f0fba2ad	509	.name = "ak4642-codec",
a3a83d9a KM	510	.owner = THIS_MODULE,
a3a83d9a KM	511	},
0ce75aa4 KM	512	.probe = ak4642_i2c_probe,
	513	.remove = __devexit_p(ak4642_i2c_remove),
	514	.id_table = ak4642_i2c_id,
a3a83d9a	515	};
a3a83d9a KM	516	#endif
a3a83d9a KM	517
a3a83d9a KM	518	static int __init ak4642_modinit(void)
a3a83d9a KM	519	{
1cf86f6f	520	int ret = 0;
a3a83d9a KM	521	#if defined(CONFIG_I2C) \|\| defined(CONFIG_I2C_MODULE)
	522	ret = i2c_add_driver(&ak4642_i2c_driver);
	523	#endif
	524	return ret;
	525
	526	}
	527	module_init(ak4642_modinit);
	528
	529	static void __exit ak4642_exit(void)
	530	{
	531	#if defined(CONFIG_I2C) \|\| defined(CONFIG_I2C_MODULE)
	532	i2c_del_driver(&ak4642_i2c_driver);
	533	#endif
	534
	535	}
	536	module_exit(ak4642_exit);
	537
	538	MODULE_DESCRIPTION("Soc AK4642 driver");
	539	MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
	540	MODULE_LICENSE("GPL");