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ASoC: cs35l33: Fix testing return value of devm_gpiod_get_optional
[deliverable/linux.git] / sound / soc / codecs / cs35l33.c
CommitLineData
3333cb71
PH		 1/*
2 * cs35l33.c -- CS35L33 ALSA SoC audio driver
3 *
4 * Copyright 2016 Cirrus Logic, Inc.
5 *
6 * Author: Paul Handrigan <paul.handrigan@cirrus.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/version.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/delay.h>
19#include <linux/i2c.h>
20#include <linux/slab.h>
21#include <linux/workqueue.h>
22#include <linux/platform_device.h>
23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
27#include <sound/soc-dapm.h>
28#include <sound/initval.h>
29#include <sound/tlv.h>
30#include <linux/gpio.h>
31#include <linux/gpio/consumer.h>
32#include <sound/cs35l33.h>
33#include <linux/pm_runtime.h>
34#include <linux/regulator/consumer.h>
35#include <linux/regulator/machine.h>
36#include <linux/of_gpio.h>
37#include <linux/of.h>
38#include <linux/of_device.h>
39#include <linux/of_irq.h>
40
41#include "cs35l33.h"
42
43#define CS35L33_BOOT_DELAY 50
44
45struct cs35l33_private {
46 struct snd_soc_codec *codec;
47 struct cs35l33_pdata pdata;
48 struct regmap *regmap;
49 struct gpio_desc *reset_gpio;
50 bool amp_cal;
51 int mclk_int;
52 struct regulator_bulk_data core_supplies[2];
53 int num_core_supplies;
54 bool is_tdm_mode;
55 bool enable_soft_ramp;
56};
57
58static const struct reg_default cs35l33_reg[] = {
59 {CS35L33_PWRCTL1, 0x85},
60 {CS35L33_PWRCTL2, 0xFE},
61 {CS35L33_CLK_CTL, 0x0C},
62 {CS35L33_BST_PEAK_CTL, 0x90},
63 {CS35L33_PROTECT_CTL, 0x55},
64 {CS35L33_BST_CTL1, 0x00},
65 {CS35L33_BST_CTL2, 0x01},
66 {CS35L33_ADSP_CTL, 0x00},
67 {CS35L33_ADC_CTL, 0xC8},
68 {CS35L33_DAC_CTL, 0x14},
69 {CS35L33_DIG_VOL_CTL, 0x00},
70 {CS35L33_CLASSD_CTL, 0x04},
71 {CS35L33_AMP_CTL, 0x90},
72 {CS35L33_INT_MASK_1, 0xFF},
73 {CS35L33_INT_MASK_2, 0xFF},
74 {CS35L33_DIAG_LOCK, 0x00},
75 {CS35L33_DIAG_CTRL_1, 0x40},
76 {CS35L33_DIAG_CTRL_2, 0x00},
77 {CS35L33_HG_MEMLDO_CTL, 0x62},
78 {CS35L33_HG_REL_RATE, 0x03},
79 {CS35L33_LDO_DEL, 0x12},
80 {CS35L33_HG_HEAD, 0x0A},
81 {CS35L33_HG_EN, 0x05},
82 {CS35L33_TX_VMON, 0x00},
83 {CS35L33_TX_IMON, 0x03},
84 {CS35L33_TX_VPMON, 0x02},
85 {CS35L33_TX_VBSTMON, 0x05},
86 {CS35L33_TX_FLAG, 0x06},
87 {CS35L33_TX_EN1, 0x00},
88 {CS35L33_TX_EN2, 0x00},
89 {CS35L33_TX_EN3, 0x00},
90 {CS35L33_TX_EN4, 0x00},
91 {CS35L33_RX_AUD, 0x40},
92 {CS35L33_RX_SPLY, 0x03},
93 {CS35L33_RX_ALIVE, 0x04},
94 {CS35L33_BST_CTL4, 0x63},
95};
96
97static const struct reg_sequence cs35l33_patch[] = {
98 { 0x00, 0x99, 0 },
99 { 0x59, 0x02, 0 },
100 { 0x52, 0x30, 0 },
101 { 0x39, 0x45, 0 },
102 { 0x57, 0x30, 0 },
103 { 0x2C, 0x68, 0 },
104 { 0x00, 0x00, 0 },
105};
106
107static bool cs35l33_volatile_register(struct device *dev, unsigned int reg)
108{
109 switch (reg) {
110 case CS35L33_DEVID_AB:
111 case CS35L33_DEVID_CD:
112 case CS35L33_DEVID_E:
113 case CS35L33_REV_ID:
114 case CS35L33_INT_STATUS_1:
115 case CS35L33_INT_STATUS_2:
116 case CS35L33_HG_STATUS:
117 return true;
118 default:
119 return false;
120 }
121}
122
123static bool cs35l33_writeable_register(struct device *dev, unsigned int reg)
124{
125 switch (reg) {
126 /* these are read only registers */
127 case CS35L33_DEVID_AB:
128 case CS35L33_DEVID_CD:
129 case CS35L33_DEVID_E:
130 case CS35L33_REV_ID:
131 case CS35L33_INT_STATUS_1:
132 case CS35L33_INT_STATUS_2:
133 case CS35L33_HG_STATUS:
134 return false;
135 default:
136 return true;
137 }
138}
139
140static bool cs35l33_readable_register(struct device *dev, unsigned int reg)
141{
142 switch (reg) {
143 case CS35L33_DEVID_AB:
144 case CS35L33_DEVID_CD:
145 case CS35L33_DEVID_E:
146 case CS35L33_REV_ID:
147 case CS35L33_PWRCTL1:
148 case CS35L33_PWRCTL2:
149 case CS35L33_CLK_CTL:
150 case CS35L33_BST_PEAK_CTL:
151 case CS35L33_PROTECT_CTL:
152 case CS35L33_BST_CTL1:
153 case CS35L33_BST_CTL2:
154 case CS35L33_ADSP_CTL:
155 case CS35L33_ADC_CTL:
156 case CS35L33_DAC_CTL:
157 case CS35L33_DIG_VOL_CTL:
158 case CS35L33_CLASSD_CTL:
159 case CS35L33_AMP_CTL:
160 case CS35L33_INT_MASK_1:
161 case CS35L33_INT_MASK_2:
162 case CS35L33_INT_STATUS_1:
163 case CS35L33_INT_STATUS_2:
164 case CS35L33_DIAG_LOCK:
165 case CS35L33_DIAG_CTRL_1:
166 case CS35L33_DIAG_CTRL_2:
167 case CS35L33_HG_MEMLDO_CTL:
168 case CS35L33_HG_REL_RATE:
169 case CS35L33_LDO_DEL:
170 case CS35L33_HG_HEAD:
171 case CS35L33_HG_EN:
172 case CS35L33_TX_VMON:
173 case CS35L33_TX_IMON:
174 case CS35L33_TX_VPMON:
175 case CS35L33_TX_VBSTMON:
176 case CS35L33_TX_FLAG:
177 case CS35L33_TX_EN1:
178 case CS35L33_TX_EN2:
179 case CS35L33_TX_EN3:
180 case CS35L33_TX_EN4:
181 case CS35L33_RX_AUD:
182 case CS35L33_RX_SPLY:
183 case CS35L33_RX_ALIVE:
184 case CS35L33_BST_CTL4:
185 return true;
186 default:
187 return false;
188 }
189}
190
191static DECLARE_TLV_DB_SCALE(classd_ctl_tlv, 900, 100, 0);
192static DECLARE_TLV_DB_SCALE(dac_tlv, -10200, 50, 0);
193
194static const struct snd_kcontrol_new cs35l33_snd_controls[] = {
195
196 SOC_SINGLE_TLV("SPK Amp Volume", CS35L33_AMP_CTL,
197 4, 0x09, 0, classd_ctl_tlv),
198 SOC_SINGLE_SX_TLV("DAC Volume", CS35L33_DIG_VOL_CTL,
199 0, 0x34, 0xE4, dac_tlv),
200};
201
202static int cs35l33_spkrdrv_event(struct snd_soc_dapm_widget *w,
203 struct snd_kcontrol *kcontrol, int event)
204{
205 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
206 struct cs35l33_private *priv = snd_soc_codec_get_drvdata(codec);
207
208 switch (event) {
209 case SND_SOC_DAPM_POST_PMU:
210 if (!priv->amp_cal) {
211 usleep_range(8000, 9000);
212 priv->amp_cal = true;
213 regmap_update_bits(priv->regmap, CS35L33_CLASSD_CTL,
214 CS35L33_AMP_CAL, 0);
215 dev_dbg(codec->dev, "Amp calibration done\n");
216 }
217 dev_dbg(codec->dev, "Amp turned on\n");
218 break;
219 case SND_SOC_DAPM_POST_PMD:
220 dev_dbg(codec->dev, "Amp turned off\n");
221 break;
222 default:
223 dev_err(codec->dev, "Invalid event = 0x%x\n", event);
224 break;
225 }
226
227 return 0;
228}
229
230static int cs35l33_sdin_event(struct snd_soc_dapm_widget *w,
231 struct snd_kcontrol *kcontrol, int event)
232{
233 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
234 struct cs35l33_private *priv = snd_soc_codec_get_drvdata(codec);
235 unsigned int val;
236
237 switch (event) {
238 case SND_SOC_DAPM_PRE_PMU:
239 regmap_update_bits(priv->regmap, CS35L33_PWRCTL1,
240 CS35L33_PDN_BST, 0);
241 val = priv->is_tdm_mode ? 0 : CS35L33_PDN_TDM;
242 regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
243 CS35L33_PDN_TDM, val);
244 dev_dbg(codec->dev, "BST turned on\n");
245 break;
246 case SND_SOC_DAPM_POST_PMU:
247 dev_dbg(codec->dev, "SDIN turned on\n");
248 if (!priv->amp_cal) {
249 regmap_update_bits(priv->regmap, CS35L33_CLASSD_CTL,
250 CS35L33_AMP_CAL, CS35L33_AMP_CAL);
251 dev_dbg(codec->dev, "Amp calibration started\n");
252 usleep_range(10000, 11000);
253 }
254 break;
255 case SND_SOC_DAPM_POST_PMD:
256 regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
257 CS35L33_PDN_TDM, CS35L33_PDN_TDM);
258 usleep_range(4000, 4100);
259 regmap_update_bits(priv->regmap, CS35L33_PWRCTL1,
260 CS35L33_PDN_BST, CS35L33_PDN_BST);
261 dev_dbg(codec->dev, "BST and SDIN turned off\n");
262 break;
263 default:
264 dev_err(codec->dev, "Invalid event = 0x%x\n", event);
265
266 }
267
268 return 0;
269}
270
271static int cs35l33_sdout_event(struct snd_soc_dapm_widget *w,
272 struct snd_kcontrol *kcontrol, int event)
273{
274 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
275 struct cs35l33_private *priv = snd_soc_codec_get_drvdata(codec);
276 unsigned int mask = CS35L33_SDOUT_3ST_I2S | CS35L33_PDN_TDM;
277 unsigned int mask2 = CS35L33_SDOUT_3ST_TDM;
278 unsigned int val, val2;
279
280 switch (event) {
281 case SND_SOC_DAPM_PRE_PMU:
282 if (priv->is_tdm_mode) {
283 /* set sdout_3st_i2s and reset pdn_tdm */
284 val = CS35L33_SDOUT_3ST_I2S;
285 /* reset sdout_3st_tdm */
286 val2 = 0;
287 } else {
288 /* reset sdout_3st_i2s and set pdn_tdm */
289 val = CS35L33_PDN_TDM;
290 /* set sdout_3st_tdm */
291 val2 = CS35L33_SDOUT_3ST_TDM;
292 }
293 dev_dbg(codec->dev, "SDOUT turned on\n");
294 break;
295 case SND_SOC_DAPM_PRE_PMD:
296 val = CS35L33_SDOUT_3ST_I2S | CS35L33_PDN_TDM;
297 val2 = CS35L33_SDOUT_3ST_TDM;
298 dev_dbg(codec->dev, "SDOUT turned off\n");
299 break;
300 default:
301 dev_err(codec->dev, "Invalid event = 0x%x\n", event);
302 return 0;
303 }
304
305 regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
306 mask, val);
307 regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
308 mask2, val2);
309
310 return 0;
311}
312
313static const struct snd_soc_dapm_widget cs35l33_dapm_widgets[] = {
314
315 SND_SOC_DAPM_OUTPUT("SPK"),
316 SND_SOC_DAPM_OUT_DRV_E("SPKDRV", CS35L33_PWRCTL1, 7, 1, NULL, 0,
317 cs35l33_spkrdrv_event,
318 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
319 SND_SOC_DAPM_AIF_IN_E("SDIN", NULL, 0, CS35L33_PWRCTL2,
320 2, 1, cs35l33_sdin_event, SND_SOC_DAPM_PRE_PMU |
321 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
322
323 SND_SOC_DAPM_INPUT("MON"),
324
325 SND_SOC_DAPM_ADC("VMON", NULL,
326 CS35L33_PWRCTL2, CS35L33_PDN_VMON_SHIFT, 1),
327 SND_SOC_DAPM_ADC("IMON", NULL,
328 CS35L33_PWRCTL2, CS35L33_PDN_IMON_SHIFT, 1),
329 SND_SOC_DAPM_ADC("VPMON", NULL,
330 CS35L33_PWRCTL2, CS35L33_PDN_VPMON_SHIFT, 1),
331 SND_SOC_DAPM_ADC("VBSTMON", NULL,
332 CS35L33_PWRCTL2, CS35L33_PDN_VBSTMON_SHIFT, 1),
333
334 SND_SOC_DAPM_AIF_OUT_E("SDOUT", NULL, 0, SND_SOC_NOPM, 0, 0,
335 cs35l33_sdout_event, SND_SOC_DAPM_PRE_PMU |
336 SND_SOC_DAPM_PRE_PMD),
337};
338
339static const struct snd_soc_dapm_route cs35l33_audio_map[] = {
340 {"SDIN", NULL, "CS35L33 Playback"},
341 {"SPKDRV", NULL, "SDIN"},
342 {"SPK", NULL, "SPKDRV"},
343
344 {"VMON", NULL, "MON"},
345 {"IMON", NULL, "MON"},
346
347 {"SDOUT", NULL, "VMON"},
348 {"SDOUT", NULL, "IMON"},
349 {"CS35L33 Capture", NULL, "SDOUT"},
350};
351
352static const struct snd_soc_dapm_route cs35l33_vphg_auto_route[] = {
353 {"SPKDRV", NULL, "VPMON"},
354 {"VPMON", NULL, "CS35L33 Playback"},
355};
356
357static const struct snd_soc_dapm_route cs35l33_vp_vbst_mon_route[] = {
358 {"SDOUT", NULL, "VPMON"},
359 {"VPMON", NULL, "MON"},
360 {"SDOUT", NULL, "VBSTMON"},
361 {"VBSTMON", NULL, "MON"},
362};
363
364static int cs35l33_set_bias_level(struct snd_soc_codec *codec,
365 enum snd_soc_bias_level level)
366{
367 unsigned int val;
3333cb71
PH		 368 struct cs35l33_private *priv = snd_soc_codec_get_drvdata(codec);
369
370 switch (level) {
371 case SND_SOC_BIAS_ON:
372 break;
373 case SND_SOC_BIAS_PREPARE:
374 regmap_update_bits(priv->regmap, CS35L33_PWRCTL1,
375 CS35L33_PDN_ALL, 0);
376 regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
377 CS35L33_MCLKDIS, 0);
378 break;
379 case SND_SOC_BIAS_STANDBY:
380 regmap_update_bits(priv->regmap, CS35L33_PWRCTL1,
381 CS35L33_PDN_ALL, CS35L33_PDN_ALL);
382 regmap_read(priv->regmap, CS35L33_INT_STATUS_2, &val);
383 usleep_range(1000, 1100);
384 if (val & CS35L33_PDN_DONE)
385 regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
386 CS35L33_MCLKDIS, CS35L33_MCLKDIS);
387 break;
388 case SND_SOC_BIAS_OFF:
389 break;
390 default:
391 return -EINVAL;
392 }
393
3333cb71
PH		 394 return 0;
395}
396
397struct cs35l33_mclk_div {
398 int mclk;
399 int srate;
400 u8 adsp_rate;
401 u8 int_fs_ratio;
402};
403
404static const struct cs35l33_mclk_div cs35l33_mclk_coeffs[] = {
405 /* MCLK, Sample Rate, adsp_rate, int_fs_ratio */
406 {5644800, 11025, 0x4, CS35L33_INT_FS_RATE},
407 {5644800, 22050, 0x8, CS35L33_INT_FS_RATE},
408 {5644800, 44100, 0xC, CS35L33_INT_FS_RATE},
409
410 {6000000, 8000, 0x1, 0},
411 {6000000, 11025, 0x2, 0},
412 {6000000, 11029, 0x3, 0},
413 {6000000, 12000, 0x4, 0},
414 {6000000, 16000, 0x5, 0},
415 {6000000, 22050, 0x6, 0},
416 {6000000, 22059, 0x7, 0},
417 {6000000, 24000, 0x8, 0},
418 {6000000, 32000, 0x9, 0},
419 {6000000, 44100, 0xA, 0},
420 {6000000, 44118, 0xB, 0},
421 {6000000, 48000, 0xC, 0},
422
423 {6144000, 8000, 0x1, CS35L33_INT_FS_RATE},
424 {6144000, 12000, 0x4, CS35L33_INT_FS_RATE},
425 {6144000, 16000, 0x5, CS35L33_INT_FS_RATE},
426 {6144000, 24000, 0x8, CS35L33_INT_FS_RATE},
427 {6144000, 32000, 0x9, CS35L33_INT_FS_RATE},
428 {6144000, 48000, 0xC, CS35L33_INT_FS_RATE},
429};
430
431static int cs35l33_get_mclk_coeff(int mclk, int srate)
432{
433 int i;
434
435 for (i = 0; i < ARRAY_SIZE(cs35l33_mclk_coeffs); i++) {
436 if (cs35l33_mclk_coeffs[i].mclk == mclk &&
437 cs35l33_mclk_coeffs[i].srate == srate)
438 return i;
439 }
440 return -EINVAL;
441}
442
443static int cs35l33_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
444{
445 struct snd_soc_codec *codec = codec_dai->codec;
446 struct cs35l33_private *priv = snd_soc_codec_get_drvdata(codec);
447
448 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
449 case SND_SOC_DAIFMT_CBM_CFM:
450 regmap_update_bits(priv->regmap, CS35L33_ADSP_CTL,
451 CS35L33_MS_MASK, CS35L33_MS_MASK);
452 dev_dbg(codec->dev, "Audio port in master mode\n");
453 break;
454 case SND_SOC_DAIFMT_CBS_CFS:
455 regmap_update_bits(priv->regmap, CS35L33_ADSP_CTL,
456 CS35L33_MS_MASK, 0);
457 dev_dbg(codec->dev, "Audio port in slave mode\n");
458 break;
459 default:
460 return -EINVAL;
461 }
462
463 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
464 case SND_SOC_DAIFMT_DSP_A:
465 /*
466 * tdm mode in cs35l33 resembles dsp-a mode very
467 * closely, it is dsp-a with fsync shifted left by half bclk
468 */
469 priv->is_tdm_mode = true;
470 dev_dbg(codec->dev, "Audio port in TDM mode\n");
471 break;
472 case SND_SOC_DAIFMT_I2S:
473 priv->is_tdm_mode = false;
474 dev_dbg(codec->dev, "Audio port in I2S mode\n");
475 break;
476 default:
477 return -EINVAL;
478 }
479
480 return 0;
481}
482
483static int cs35l33_pcm_hw_params(struct snd_pcm_substream *substream,
484 struct snd_pcm_hw_params *params,
485 struct snd_soc_dai *dai)
486{
487 struct snd_soc_codec *codec = dai->codec;
488 struct cs35l33_private *priv = snd_soc_codec_get_drvdata(codec);
489 int sample_size = params_width(params);
490 int coeff = cs35l33_get_mclk_coeff(priv->mclk_int, params_rate(params));
491
492 if (coeff < 0)
493 return coeff;
494
495 regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
496 CS35L33_ADSP_FS | CS35L33_INT_FS_RATE,
497 cs35l33_mclk_coeffs[coeff].int_fs_ratio
498 | cs35l33_mclk_coeffs[coeff].adsp_rate);
499
500 if (priv->is_tdm_mode) {
501 sample_size = (sample_size / 8) - 1;
502 if (sample_size > 2)
503 sample_size = 2;
504 regmap_update_bits(priv->regmap, CS35L33_RX_AUD,
505 CS35L33_AUDIN_RX_DEPTH,
506 sample_size << CS35L33_AUDIN_RX_DEPTH_SHIFT);
507 }
508
509 dev_dbg(codec->dev, "sample rate=%d, bits per sample=%d\n",
510 params_rate(params), params_width(params));
511
512 return 0;
513}
514
515static const unsigned int cs35l33_src_rates[] = {
516 8000, 11025, 11029, 12000, 16000, 22050,
517 22059, 24000, 32000, 44100, 44118, 48000
518};
519
520static const struct snd_pcm_hw_constraint_list cs35l33_constraints = {
521 .count = ARRAY_SIZE(cs35l33_src_rates),
522 .list = cs35l33_src_rates,
523};
524
525static int cs35l33_pcm_startup(struct snd_pcm_substream *substream,
526 struct snd_soc_dai *dai)
527{
528 snd_pcm_hw_constraint_list(substream->runtime, 0,
529 SNDRV_PCM_HW_PARAM_RATE,
530 &cs35l33_constraints);
531 return 0;
532}
533
534static int cs35l33_set_tristate(struct snd_soc_dai *dai, int tristate)
535{
536 struct snd_soc_codec *codec = dai->codec;
537 struct cs35l33_private *priv = snd_soc_codec_get_drvdata(codec);
538
539 if (tristate) {
540 regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
541 CS35L33_SDOUT_3ST_I2S, CS35L33_SDOUT_3ST_I2S);
542 regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
543 CS35L33_SDOUT_3ST_TDM, CS35L33_SDOUT_3ST_TDM);
544 } else {
545 regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
546 CS35L33_SDOUT_3ST_I2S, 0);
547 regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
548 CS35L33_SDOUT_3ST_TDM, 0);
549 }
550
551 return 0;
552}
553
554static int cs35l33_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
555 unsigned int rx_mask, int slots, int slot_width)
556{
557 struct snd_soc_codec *codec = dai->codec;
558 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
559 struct cs35l33_private *priv = snd_soc_codec_get_drvdata(codec);
560 unsigned int reg, bit_pos, i;
561 int slot, slot_num;
562
563 if (slot_width != 8)
564 return -EINVAL;
565
566 /* scan rx_mask for aud slot */
567 slot = ffs(rx_mask) - 1;
568 if (slot >= 0) {
569 regmap_update_bits(priv->regmap, CS35L33_RX_AUD,
570 CS35L33_X_LOC, slot);
571 dev_dbg(codec->dev, "Audio starts from slots %d", slot);
572 }
573
574 /*
575 * scan tx_mask: vmon(2 slots); imon (2 slots);
576 * vpmon (1 slot) vbstmon (1 slot)
577 */
578 slot = ffs(tx_mask) - 1;
579 slot_num = 0;
580
581 for (i = 0; i < 2 ; i++) {
582 /* disable vpmon/vbstmon: enable later if set in tx_mask */
583 regmap_update_bits(priv->regmap, CS35L33_TX_VPMON + i,
584 CS35L33_X_STATE | CS35L33_X_LOC, CS35L33_X_STATE
585 | CS35L33_X_LOC);
586 }
587
588 /* disconnect {vp,vbst}_mon routes: eanble later if set in tx_mask*/
589 snd_soc_dapm_del_routes(dapm, cs35l33_vp_vbst_mon_route,
590 ARRAY_SIZE(cs35l33_vp_vbst_mon_route));
591
592 while (slot >= 0) {
593 /* configure VMON_TX_LOC */
594 if (slot_num == 0) {
595 regmap_update_bits(priv->regmap, CS35L33_TX_VMON,
596 CS35L33_X_STATE | CS35L33_X_LOC, slot);
597 dev_dbg(codec->dev, "VMON enabled in slots %d-%d",
598 slot, slot + 1);
599 }
600
601 /* configure IMON_TX_LOC */
602 if (slot_num == 3) {
603 regmap_update_bits(priv->regmap, CS35L33_TX_IMON,
604 CS35L33_X_STATE | CS35L33_X_LOC, slot);
605 dev_dbg(codec->dev, "IMON enabled in slots %d-%d",
606 slot, slot + 1);
607 }
608
609 /* configure VPMON_TX_LOC */
610 if (slot_num == 4) {
611 regmap_update_bits(priv->regmap, CS35L33_TX_VPMON,
612 CS35L33_X_STATE | CS35L33_X_LOC, slot);
613 snd_soc_dapm_add_routes(dapm,
614 &cs35l33_vp_vbst_mon_route[0], 2);
615 dev_dbg(codec->dev, "VPMON enabled in slots %d", slot);
616 }
617
618 /* configure VBSTMON_TX_LOC */
619 if (slot_num == 5) {
620 regmap_update_bits(priv->regmap, CS35L33_TX_VBSTMON,
621 CS35L33_X_STATE | CS35L33_X_LOC, slot);
622 snd_soc_dapm_add_routes(dapm,
623 &cs35l33_vp_vbst_mon_route[2], 2);
624 dev_dbg(codec->dev,
625 "VBSTMON enabled in slots %d", slot);
626 }
627
628 /* Enable the relevant tx slot */
629 reg = CS35L33_TX_EN4 - (slot/8);
630 bit_pos = slot - ((slot / 8) * (8));
631 regmap_update_bits(priv->regmap, reg,
632 1 << bit_pos, 1 << bit_pos);
633
634 tx_mask &= ~(1 << slot);
635 slot = ffs(tx_mask) - 1;
636 slot_num++;
637 }
638
639 return 0;
640}
641
642static int cs35l33_codec_set_sysclk(struct snd_soc_codec *codec,
643 int clk_id, int source, unsigned int freq, int dir)
644{
645 struct cs35l33_private *cs35l33 = snd_soc_codec_get_drvdata(codec);
646
647 switch (freq) {
648 case CS35L33_MCLK_5644:
649 case CS35L33_MCLK_6:
650 case CS35L33_MCLK_6144:
651 regmap_update_bits(cs35l33->regmap, CS35L33_CLK_CTL,
652 CS35L33_MCLKDIV2, 0);
653 cs35l33->mclk_int = freq;
654 break;
655 case CS35L33_MCLK_11289:
656 case CS35L33_MCLK_12:
657 case CS35L33_MCLK_12288:
658 regmap_update_bits(cs35l33->regmap, CS35L33_CLK_CTL,
659 CS35L33_MCLKDIV2, CS35L33_MCLKDIV2);
660 cs35l33->mclk_int = freq/2;
661 break;
662 default:
663 cs35l33->mclk_int = 0;
664 return -EINVAL;
665 }
666
667 dev_dbg(codec->dev, "external mclk freq=%d, internal mclk freq=%d\n",
668 freq, cs35l33->mclk_int);
669
670 return 0;
671}
672
673static const struct snd_soc_dai_ops cs35l33_ops = {
674 .startup = cs35l33_pcm_startup,
675 .set_tristate = cs35l33_set_tristate,
676 .set_fmt = cs35l33_set_dai_fmt,
677 .hw_params = cs35l33_pcm_hw_params,
678 .set_tdm_slot = cs35l33_set_tdm_slot,
679};
680
681static struct snd_soc_dai_driver cs35l33_dai = {
682 .name = "cs35l33-dai",
683 .id = 0,
684 .playback = {
685 .stream_name = "CS35L33 Playback",
686 .channels_min = 1,
687 .channels_max = 1,
688 .rates = CS35L33_RATES,
689 .formats = CS35L33_FORMATS,
690 },
691 .capture = {
692 .stream_name = "CS35L33 Capture",
693 .channels_min = 2,
694 .channels_max = 2,
695 .rates = CS35L33_RATES,
696 .formats = CS35L33_FORMATS,
697 },
698 .ops = &cs35l33_ops,
699 .symmetric_rates = 1,
700};
701
702static int cs35l33_set_hg_data(struct snd_soc_codec *codec,
703 struct cs35l33_pdata *pdata)
704{
705 struct cs35l33_hg *hg_config = &pdata->hg_config;
706 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
707 struct cs35l33_private *priv = snd_soc_codec_get_drvdata(codec);
708
709 if (hg_config->enable_hg_algo) {
710 regmap_update_bits(priv->regmap, CS35L33_HG_MEMLDO_CTL,
711 CS35L33_MEM_DEPTH_MASK,
712 hg_config->mem_depth << CS35L33_MEM_DEPTH_SHIFT);
713 regmap_write(priv->regmap, CS35L33_HG_REL_RATE,
714 hg_config->release_rate);
715 regmap_update_bits(priv->regmap, CS35L33_HG_HEAD,
716 CS35L33_HD_RM_MASK,
717 hg_config->hd_rm << CS35L33_HD_RM_SHIFT);
718 regmap_update_bits(priv->regmap, CS35L33_HG_MEMLDO_CTL,
719 CS35L33_LDO_THLD_MASK,
720 hg_config->ldo_thld << CS35L33_LDO_THLD_SHIFT);
721 regmap_update_bits(priv->regmap, CS35L33_HG_MEMLDO_CTL,
722 CS35L33_LDO_DISABLE_MASK,
723 hg_config->ldo_path_disable <<
724 CS35L33_LDO_DISABLE_SHIFT);
725 regmap_update_bits(priv->regmap, CS35L33_LDO_DEL,
726 CS35L33_LDO_ENTRY_DELAY_MASK,
727 hg_config->ldo_entry_delay <<
728 CS35L33_LDO_ENTRY_DELAY_SHIFT);
729 if (hg_config->vp_hg_auto) {
730 regmap_update_bits(priv->regmap, CS35L33_HG_EN,
731 CS35L33_VP_HG_AUTO_MASK,
732 CS35L33_VP_HG_AUTO_MASK);
733 snd_soc_dapm_add_routes(dapm, cs35l33_vphg_auto_route,
734 ARRAY_SIZE(cs35l33_vphg_auto_route));
735 }
736 regmap_update_bits(priv->regmap, CS35L33_HG_EN,
737 CS35L33_VP_HG_MASK,
738 hg_config->vp_hg << CS35L33_VP_HG_SHIFT);
739 regmap_update_bits(priv->regmap, CS35L33_LDO_DEL,
740 CS35L33_VP_HG_RATE_MASK,
741 hg_config->vp_hg_rate << CS35L33_VP_HG_RATE_SHIFT);
742 regmap_update_bits(priv->regmap, CS35L33_LDO_DEL,
743 CS35L33_VP_HG_VA_MASK,
744 hg_config->vp_hg_va << CS35L33_VP_HG_VA_SHIFT);
745 regmap_update_bits(priv->regmap, CS35L33_HG_EN,
746 CS35L33_CLASS_HG_EN_MASK, CS35L33_CLASS_HG_EN_MASK);
747 }
748 return 0;
749}
750
751static int cs35l33_set_bst_ipk(struct snd_soc_codec *codec, unsigned int bst)
752{
753 struct cs35l33_private *cs35l33 = snd_soc_codec_get_drvdata(codec);
754 int ret = 0, steps = 0;
755
756 /* Boost current in uA */
757 if (bst > 3600000 || bst < 1850000) {
758 dev_err(codec->dev, "Invalid boost current %d\n", bst);
759 ret = -EINVAL;
760 goto err;
761 }
762
763 if (bst % 15625) {
764 dev_err(codec->dev, "Current not a multiple of 15625uA (%d)\n",
765 bst);
766 ret = -EINVAL;
767 goto err;
768 }
769
770 while (bst > 1850000) {
771 bst -= 15625;
772 steps++;
773 }
774
775 regmap_write(cs35l33->regmap, CS35L33_BST_PEAK_CTL,
776 steps+0x70);
777
778err:
779 return ret;
780}
781
782static int cs35l33_probe(struct snd_soc_codec *codec)
783{
784 struct cs35l33_private *cs35l33 = snd_soc_codec_get_drvdata(codec);
785
786 cs35l33->codec = codec;
787 pm_runtime_get_sync(codec->dev);
788
789 regmap_update_bits(cs35l33->regmap, CS35L33_PROTECT_CTL,
790 CS35L33_ALIVE_WD_DIS, 0x8);
791 regmap_update_bits(cs35l33->regmap, CS35L33_BST_CTL2,
792 CS35L33_ALIVE_WD_DIS2,
793 CS35L33_ALIVE_WD_DIS2);
794
795 /* Set Platform Data */
796 regmap_update_bits(cs35l33->regmap, CS35L33_BST_CTL1,
797 CS35L33_BST_CTL_MASK, cs35l33->pdata.boost_ctl);
798 regmap_update_bits(cs35l33->regmap, CS35L33_CLASSD_CTL,
799 CS35L33_AMP_DRV_SEL_MASK,
800 cs35l33->pdata.amp_drv_sel << CS35L33_AMP_DRV_SEL_SHIFT);
801
802 if (cs35l33->pdata.boost_ipk)
803 cs35l33_set_bst_ipk(codec, cs35l33->pdata.boost_ipk);
804
805 if (cs35l33->enable_soft_ramp) {
806 snd_soc_update_bits(codec, CS35L33_DAC_CTL,
807 CS35L33_DIGSFT, CS35L33_DIGSFT);
808 snd_soc_update_bits(codec, CS35L33_DAC_CTL,
809 CS35L33_DSR_RATE, cs35l33->pdata.ramp_rate);
810 } else {
811 snd_soc_update_bits(codec, CS35L33_DAC_CTL,
812 CS35L33_DIGSFT, 0);
813 }
814
815 /* update IMON scaling rate if different from default of 0x8 */
816 if (cs35l33->pdata.imon_adc_scale != 0x8)
817 snd_soc_update_bits(codec, CS35L33_ADC_CTL,
818 CS35L33_IMON_SCALE, cs35l33->pdata.imon_adc_scale);
819
820 cs35l33_set_hg_data(codec, &(cs35l33->pdata));
821
822 /*
823 * unmask important interrupts that causes the chip to enter
824 * speaker safe mode and hence deserves user attention
825 */
826 regmap_update_bits(cs35l33->regmap, CS35L33_INT_MASK_1,
827 CS35L33_M_OTE | CS35L33_M_OTW | CS35L33_M_AMP_SHORT |
828 CS35L33_M_CAL_ERR, 0);
829
830 pm_runtime_put_sync(codec->dev);
831
832 return 0;
833}
834
835static struct snd_soc_codec_driver soc_codec_dev_cs35l33 = {
836 .probe = cs35l33_probe,
837
838 .set_bias_level = cs35l33_set_bias_level,
839 .set_sysclk = cs35l33_codec_set_sysclk,
840
841 .dapm_widgets = cs35l33_dapm_widgets,
842 .num_dapm_widgets = ARRAY_SIZE(cs35l33_dapm_widgets),
843 .dapm_routes = cs35l33_audio_map,
844 .num_dapm_routes = ARRAY_SIZE(cs35l33_audio_map),
845 .controls = cs35l33_snd_controls,
846 .num_controls = ARRAY_SIZE(cs35l33_snd_controls),
847
848 .idle_bias_off = true,
849};
850
851static const struct regmap_config cs35l33_regmap = {
852 .reg_bits = 8,
853 .val_bits = 8,
854
855 .max_register = CS35L33_MAX_REGISTER,
856 .reg_defaults = cs35l33_reg,
857 .num_reg_defaults = ARRAY_SIZE(cs35l33_reg),
858 .volatile_reg = cs35l33_volatile_register,
859 .readable_reg = cs35l33_readable_register,
860 .writeable_reg = cs35l33_writeable_register,
861 .cache_type = REGCACHE_RBTREE,
862 .use_single_rw = true,
863};
864
20f12f2c 865static int __maybe_unused cs35l33_runtime_resume(struct device *dev)
3333cb71
PH		 866{
867 struct cs35l33_private *cs35l33 = dev_get_drvdata(dev);
868 int ret;
869
870 dev_dbg(dev, "%s\n", __func__);
871
872 if (cs35l33->reset_gpio)
873 gpiod_set_value_cansleep(cs35l33->reset_gpio, 0);
874
875 ret = regulator_bulk_enable(cs35l33->num_core_supplies,
876 cs35l33->core_supplies);
877 if (ret != 0) {
878 dev_err(dev, "Failed to enable core supplies: %d\n", ret);
879 return ret;
880 }
881
882 regcache_cache_only(cs35l33->regmap, false);
883
884 if (cs35l33->reset_gpio)
885 gpiod_set_value_cansleep(cs35l33->reset_gpio, 1);
886
887 msleep(CS35L33_BOOT_DELAY);
888
889 ret = regcache_sync(cs35l33->regmap);
890 if (ret != 0) {
891 dev_err(dev, "Failed to restore register cache\n");
892 goto err;
893 }
894
895 return 0;
896
897err:
898 regcache_cache_only(cs35l33->regmap, true);
899 regulator_bulk_disable(cs35l33->num_core_supplies,
900 cs35l33->core_supplies);
901
902 return ret;
903}
904
20f12f2c 905static int __maybe_unused cs35l33_runtime_suspend(struct device *dev)
3333cb71
PH		 906{
907 struct cs35l33_private *cs35l33 = dev_get_drvdata(dev);
908
909 dev_dbg(dev, "%s\n", __func__);
910
911 /* redo the calibration in next power up */
912 cs35l33->amp_cal = false;
913
914 regcache_cache_only(cs35l33->regmap, true);
915 regcache_mark_dirty(cs35l33->regmap);
916 regulator_bulk_disable(cs35l33->num_core_supplies,
917 cs35l33->core_supplies);
918
919 return 0;
920}
921
922static const struct dev_pm_ops cs35l33_pm_ops = {
923 SET_RUNTIME_PM_OPS(cs35l33_runtime_suspend,
924 cs35l33_runtime_resume,
925 NULL)
926};
927
928static int cs35l33_get_hg_data(const struct device_node *np,
929 struct cs35l33_pdata *pdata)
930{
931 struct device_node *hg;
932 struct cs35l33_hg *hg_config = &pdata->hg_config;
933 u32 val32;
934
935 hg = of_get_child_by_name(np, "cirrus,hg-algo");
936 hg_config->enable_hg_algo = hg ? true : false;
937
938 if (hg_config->enable_hg_algo) {
939 if (of_property_read_u32(hg, "cirrus,mem-depth", &val32) >= 0)
940 hg_config->mem_depth = val32;
941 if (of_property_read_u32(hg, "cirrus,release-rate",
942 &val32) >= 0)
943 hg_config->release_rate = val32;
944 if (of_property_read_u32(hg, "cirrus,ldo-thld", &val32) >= 0)
945 hg_config->ldo_thld = val32;
946 if (of_property_read_u32(hg, "cirrus,ldo-path-disable",
947 &val32) >= 0)
948 hg_config->ldo_path_disable = val32;
949 if (of_property_read_u32(hg, "cirrus,ldo-entry-delay",
950 &val32) >= 0)
951 hg_config->ldo_entry_delay = val32;
952
953 hg_config->vp_hg_auto = of_property_read_bool(hg,
954 "cirrus,vp-hg-auto");
955
956 if (of_property_read_u32(hg, "cirrus,vp-hg", &val32) >= 0)
957 hg_config->vp_hg = val32;
958 if (of_property_read_u32(hg, "cirrus,vp-hg-rate", &val32) >= 0)
959 hg_config->vp_hg_rate = val32;
960 if (of_property_read_u32(hg, "cirrus,vp-hg-va", &val32) >= 0)
961 hg_config->vp_hg_va = val32;
962 }
963
964 of_node_put(hg);
965
966 return 0;
967}
968
969static irqreturn_t cs35l33_irq_thread(int irq, void *data)
970{
971 struct cs35l33_private *cs35l33 = data;
972 struct snd_soc_codec *codec = cs35l33->codec;
973 unsigned int sticky_val1, sticky_val2, current_val, mask1, mask2;
974
975 regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_2,
976 &sticky_val2);
977 regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_1,
978 &sticky_val1);
979 regmap_read(cs35l33->regmap, CS35L33_INT_MASK_2, &mask2);
980 regmap_read(cs35l33->regmap, CS35L33_INT_MASK_1, &mask1);
981
982 /* Check to see if the unmasked bits are active,
983 * if not then exit.
984 */
985 if (!(sticky_val1 & ~mask1) && !(sticky_val2 & ~mask2))
986 return IRQ_NONE;
987
988 regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_1,
989 &current_val);
990
991 /* handle the interrupts */
992
993 if (sticky_val1 & CS35L33_AMP_SHORT) {
994 dev_crit(codec->dev, "Amp short error\n");
995 if (!(current_val & CS35L33_AMP_SHORT)) {
996 dev_dbg(codec->dev,
997 "Amp short error release\n");
998 regmap_update_bits(cs35l33->regmap,
999 CS35L33_AMP_CTL,
1000 CS35L33_AMP_SHORT_RLS, 0);
1001 regmap_update_bits(cs35l33->regmap,
1002 CS35L33_AMP_CTL,
1003 CS35L33_AMP_SHORT_RLS,
1004 CS35L33_AMP_SHORT_RLS);
1005 regmap_update_bits(cs35l33->regmap,
1006 CS35L33_AMP_CTL, CS35L33_AMP_SHORT_RLS,
1007 0);
1008 }
1009 }
1010
1011 if (sticky_val1 & CS35L33_CAL_ERR) {
1012 dev_err(codec->dev, "Cal error\n");
1013
1014 /* redo the calibration in next power up */
1015 cs35l33->amp_cal = false;
1016
1017 if (!(current_val & CS35L33_CAL_ERR)) {
1018 dev_dbg(codec->dev, "Cal error release\n");
1019 regmap_update_bits(cs35l33->regmap,
1020 CS35L33_AMP_CTL, CS35L33_CAL_ERR_RLS,
1021 0);
1022 regmap_update_bits(cs35l33->regmap,
1023 CS35L33_AMP_CTL, CS35L33_CAL_ERR_RLS,
1024 CS35L33_CAL_ERR_RLS);
1025 regmap_update_bits(cs35l33->regmap,
1026 CS35L33_AMP_CTL, CS35L33_CAL_ERR_RLS,
1027 0);
1028 }
1029 }
1030
1031 if (sticky_val1 & CS35L33_OTE) {
1032 dev_crit(codec->dev, "Over temperature error\n");
1033 if (!(current_val & CS35L33_OTE)) {
1034 dev_dbg(codec->dev,
1035 "Over temperature error release\n");
1036 regmap_update_bits(cs35l33->regmap,
1037 CS35L33_AMP_CTL, CS35L33_OTE_RLS, 0);
1038 regmap_update_bits(cs35l33->regmap,
1039 CS35L33_AMP_CTL, CS35L33_OTE_RLS,
1040 CS35L33_OTE_RLS);
1041 regmap_update_bits(cs35l33->regmap,
1042 CS35L33_AMP_CTL, CS35L33_OTE_RLS, 0);
1043 }
1044 }
1045
1046 if (sticky_val1 & CS35L33_OTW) {
1047 dev_err(codec->dev, "Over temperature warning\n");
1048 if (!(current_val & CS35L33_OTW)) {
1049 dev_dbg(codec->dev,
1050 "Over temperature warning release\n");
1051 regmap_update_bits(cs35l33->regmap,
1052 CS35L33_AMP_CTL, CS35L33_OTW_RLS, 0);
1053 regmap_update_bits(cs35l33->regmap,
1054 CS35L33_AMP_CTL, CS35L33_OTW_RLS,
1055 CS35L33_OTW_RLS);
1056 regmap_update_bits(cs35l33->regmap,
1057 CS35L33_AMP_CTL, CS35L33_OTW_RLS, 0);
1058 }
1059 }
1060 if (CS35L33_ALIVE_ERR & sticky_val1)
1061 dev_err(codec->dev, "ERROR: ADSPCLK Interrupt\n");
1062
1063 if (CS35L33_MCLK_ERR & sticky_val1)
1064 dev_err(codec->dev, "ERROR: MCLK Interrupt\n");
1065
1066 if (CS35L33_VMON_OVFL & sticky_val2)
1067 dev_err(codec->dev,
1068 "ERROR: VMON Overflow Interrupt\n");
1069
1070 if (CS35L33_IMON_OVFL & sticky_val2)
1071 dev_err(codec->dev,
1072 "ERROR: IMON Overflow Interrupt\n");
1073
1074 if (CS35L33_VPMON_OVFL & sticky_val2)
1075 dev_err(codec->dev,
1076 "ERROR: VPMON Overflow Interrupt\n");
1077
1078 return IRQ_HANDLED;
1079}
1080
1081static const char * const cs35l33_core_supplies[] = {
1082 "VA",
1083 "VP",
1084};
1085
1086static int cs35l33_of_get_pdata(struct device *dev,
1087 struct cs35l33_private *cs35l33)
1088{
1089 struct device_node *np = dev->of_node;
1090 struct cs35l33_pdata *pdata = &cs35l33->pdata;
1091 u32 val32;
1092
1093 if (!np)
1094 return 0;
1095
1096 if (of_property_read_u32(np, "cirrus,boost-ctl", &val32) >= 0) {
1097 pdata->boost_ctl = val32;
1098 pdata->amp_drv_sel = 1;
1099 }
1100
1101 if (of_property_read_u32(np, "cirrus,ramp-rate", &val32) >= 0) {
1102 pdata->ramp_rate = val32;
1103 cs35l33->enable_soft_ramp = true;
1104 }
1105
1106 if (of_property_read_u32(np, "cirrus,boost-ipk", &val32) >= 0)
1107 pdata->boost_ipk = val32;
1108
1109 if (of_property_read_u32(np, "cirrus,imon-adc-scale", &val32) >= 0) {
1110 if ((val32 == 0x0) || (val32 == 0x7) || (val32 == 0x6))
1111 pdata->imon_adc_scale = val32;
1112 else
1113 /* use default value */
1114 pdata->imon_adc_scale = 0x8;
1115 } else {
1116 /* use default value */
1117 pdata->imon_adc_scale = 0x8;
1118 }
1119
1120 cs35l33_get_hg_data(np, pdata);
1121
1122 return 0;
1123}
1124
1125static int cs35l33_i2c_probe(struct i2c_client *i2c_client,
1126 const struct i2c_device_id *id)
1127{
1128 struct cs35l33_private *cs35l33;
1129 struct cs35l33_pdata *pdata = dev_get_platdata(&i2c_client->dev);
1130 int ret, devid, i;
1131 unsigned int reg;
1132
1133 cs35l33 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs35l33_private),
1134 GFP_KERNEL);
1135 if (!cs35l33)
1136 return -ENOMEM;
1137
1138 i2c_set_clientdata(i2c_client, cs35l33);
1139 cs35l33->regmap = devm_regmap_init_i2c(i2c_client, &cs35l33_regmap);
1140 if (IS_ERR(cs35l33->regmap)) {
1141 ret = PTR_ERR(cs35l33->regmap);
1142 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1143 return ret;
1144 }
1145
1146 regcache_cache_only(cs35l33->regmap, true);
1147
1148 for (i = 0; i < ARRAY_SIZE(cs35l33_core_supplies); i++)
1149 cs35l33->core_supplies[i].supply
1150 = cs35l33_core_supplies[i];
1151 cs35l33->num_core_supplies = ARRAY_SIZE(cs35l33_core_supplies);
1152
1153 ret = devm_regulator_bulk_get(&i2c_client->dev,
1154 cs35l33->num_core_supplies,
1155 cs35l33->core_supplies);
1156 if (ret != 0) {
1157 dev_err(&i2c_client->dev,
1158 "Failed to request core supplies: %d\n",
1159 ret);
1160 return ret;
1161 }
1162
1163 if (pdata) {
1164 cs35l33->pdata = *pdata;
1165 } else {
1166 cs35l33_of_get_pdata(&i2c_client->dev, cs35l33);
1167 pdata = &cs35l33->pdata;
1168 }
1169
1170 ret = devm_request_threaded_irq(&i2c_client->dev, i2c_client->irq, NULL,
1171 cs35l33_irq_thread, IRQF_ONESHOT | IRQF_TRIGGER_LOW,
1172 "cs35l33", cs35l33);
1173 if (ret != 0)
1174 dev_warn(&i2c_client->dev, "Failed to request IRQ: %d\n", ret);
1175
1176 /* We could issue !RST or skip it based on AMP topology */
1177 cs35l33->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
1178 "reset-gpios", GPIOD_OUT_HIGH);
410fe39c 1179 if (IS_ERR(cs35l33->reset_gpio)) {
3333cb71
PH		 1180 dev_err(&i2c_client->dev, "%s ERROR: Can't get reset GPIO\n",
1181 __func__);
1182 return PTR_ERR(cs35l33->reset_gpio);
1183 }
1184
1185 ret = regulator_bulk_enable(cs35l33->num_core_supplies,
1186 cs35l33->core_supplies);
1187 if (ret != 0) {
1188 dev_err(&i2c_client->dev,
1189 "Failed to enable core supplies: %d\n",
1190 ret);
beefe4a9 1191 return ret;
3333cb71
PH		 1192 }
1193
1194 if (cs35l33->reset_gpio)
1195 gpiod_set_value_cansleep(cs35l33->reset_gpio, 1);
1196
1197 msleep(CS35L33_BOOT_DELAY);
1198 regcache_cache_only(cs35l33->regmap, false);
1199
1200 /* initialize codec */
1201 ret = regmap_read(cs35l33->regmap, CS35L33_DEVID_AB, &reg);
1202 devid = (reg & 0xFF) << 12;
1203 ret = regmap_read(cs35l33->regmap, CS35L33_DEVID_CD, &reg);
1204 devid |= (reg & 0xFF) << 4;
1205 ret = regmap_read(cs35l33->regmap, CS35L33_DEVID_E, &reg);
1206 devid |= (reg & 0xF0) >> 4;
1207
1208 if (devid != CS35L33_CHIP_ID) {
1209 dev_err(&i2c_client->dev,
1210 "CS35L33 Device ID (%X). Expected ID %X\n",
1211 devid, CS35L33_CHIP_ID);
1212 goto err_enable;
1213 }
1214
1215 ret = regmap_read(cs35l33->regmap, CS35L33_REV_ID, &reg);
1216 if (ret < 0) {
1217 dev_err(&i2c_client->dev, "Get Revision ID failed\n");
1218 goto err_enable;
1219 }
1220
1221 dev_info(&i2c_client->dev,
1222 "Cirrus Logic CS35L33, Revision: %02X\n", ret & 0xFF);
1223
1224 ret = regmap_register_patch(cs35l33->regmap,
1225 cs35l33_patch, ARRAY_SIZE(cs35l33_patch));
1226 if (ret < 0) {
1227 dev_err(&i2c_client->dev,
1228 "Error in applying regmap patch: %d\n", ret);
1229 goto err_enable;
1230 }
1231
1232 /* disable mclk and tdm */
1233 regmap_update_bits(cs35l33->regmap, CS35L33_CLK_CTL,
1234 CS35L33_MCLKDIS | CS35L33_SDOUT_3ST_TDM,
1235 CS35L33_MCLKDIS | CS35L33_SDOUT_3ST_TDM);
1236
1237 pm_runtime_set_autosuspend_delay(&i2c_client->dev, 100);
1238 pm_runtime_use_autosuspend(&i2c_client->dev);
1239 pm_runtime_set_active(&i2c_client->dev);
1240 pm_runtime_enable(&i2c_client->dev);
1241
1242 ret = snd_soc_register_codec(&i2c_client->dev,
1243 &soc_codec_dev_cs35l33, &cs35l33_dai, 1);
1244 if (ret < 0) {
1245 dev_err(&i2c_client->dev, "%s: Register codec failed\n",
1246 __func__);
beefe4a9 1247 goto err_enable;
3333cb71
PH		 1248 }
1249
1250 return 0;
1251
1252err_enable:
1253 regulator_bulk_disable(cs35l33->num_core_supplies,
1254 cs35l33->core_supplies);
3333cb71
PH		 1255
1256 return ret;
1257}
1258
1259static int cs35l33_i2c_remove(struct i2c_client *client)
1260{
1261 struct cs35l33_private *cs35l33 = i2c_get_clientdata(client);
1262
1263 snd_soc_unregister_codec(&client->dev);
1264
1265 if (cs35l33->reset_gpio)
1266 gpiod_set_value_cansleep(cs35l33->reset_gpio, 0);
1267
1268 pm_runtime_disable(&client->dev);
1269 regulator_bulk_disable(cs35l33->num_core_supplies,
1270 cs35l33->core_supplies);
3333cb71
PH		 1271
1272 return 0;
1273}
1274
1275static const struct of_device_id cs35l33_of_match[] = {
1276 { .compatible = "cirrus,cs35l33", },
1277 {},
1278};
1279MODULE_DEVICE_TABLE(of, cs35l33_of_match);
1280
1281static const struct i2c_device_id cs35l33_id[] = {
1282 {"cs35l33", 0},
1283 {}
1284};
1285
1286MODULE_DEVICE_TABLE(i2c, cs35l33_id);
1287
1288static struct i2c_driver cs35l33_i2c_driver = {
1289 .driver = {
1290 .name = "cs35l33",
3333cb71
PH		 1291 .pm = &cs35l33_pm_ops,
1292 .of_match_table = cs35l33_of_match,
1293
1294 },
1295 .id_table = cs35l33_id,
1296 .probe = cs35l33_i2c_probe,
1297 .remove = cs35l33_i2c_remove,
1298
1299};
1300module_i2c_driver(cs35l33_i2c_driver);
1301
1302MODULE_DESCRIPTION("ASoC CS35L33 driver");
1303MODULE_AUTHOR("Paul Handrigan, Cirrus Logic Inc, <paul.handrigan@cirrus.com>");
1304MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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