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67b22517 AS |
1 | /* |
2 | * CS4271 ASoC codec driver | |
3 | * | |
4 | * Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * This driver support CS4271 codec being master or slave, working | |
17 | * in control port mode, connected either via SPI or I2C. | |
18 | * The data format accepted is I2S or left-justified. | |
19 | * DAPM support not implemented. | |
20 | */ | |
21 | ||
22 | #include <linux/module.h> | |
23 | #include <linux/slab.h> | |
24 | #include <linux/delay.h> | |
67b22517 AS |
25 | #include <linux/gpio.h> |
26 | #include <linux/i2c.h> | |
27 | #include <linux/spi/spi.h> | |
a31ebc34 DM |
28 | #include <linux/of_device.h> |
29 | #include <linux/of_gpio.h> | |
30 | #include <sound/pcm.h> | |
31 | #include <sound/soc.h> | |
32 | #include <sound/tlv.h> | |
67b22517 AS |
33 | #include <sound/cs4271.h> |
34 | ||
35 | #define CS4271_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ | |
36 | SNDRV_PCM_FMTBIT_S24_LE | \ | |
37 | SNDRV_PCM_FMTBIT_S32_LE) | |
383f8465 | 38 | #define CS4271_PCM_RATES SNDRV_PCM_RATE_8000_192000 |
67b22517 AS |
39 | |
40 | /* | |
41 | * CS4271 registers | |
42 | * High byte represents SPI chip address (0x10) + write command (0) | |
43 | * Low byte - codec register address | |
44 | */ | |
45 | #define CS4271_MODE1 0x2001 /* Mode Control 1 */ | |
46 | #define CS4271_DACCTL 0x2002 /* DAC Control */ | |
47 | #define CS4271_DACVOL 0x2003 /* DAC Volume & Mixing Control */ | |
48 | #define CS4271_VOLA 0x2004 /* DAC Channel A Volume Control */ | |
49 | #define CS4271_VOLB 0x2005 /* DAC Channel B Volume Control */ | |
50 | #define CS4271_ADCCTL 0x2006 /* ADC Control */ | |
51 | #define CS4271_MODE2 0x2007 /* Mode Control 2 */ | |
52 | #define CS4271_CHIPID 0x2008 /* Chip ID */ | |
53 | ||
54 | #define CS4271_FIRSTREG CS4271_MODE1 | |
55 | #define CS4271_LASTREG CS4271_MODE2 | |
56 | #define CS4271_NR_REGS ((CS4271_LASTREG & 0xFF) + 1) | |
57 | ||
58 | /* Bit masks for the CS4271 registers */ | |
59 | #define CS4271_MODE1_MODE_MASK 0xC0 | |
60 | #define CS4271_MODE1_MODE_1X 0x00 | |
61 | #define CS4271_MODE1_MODE_2X 0x80 | |
62 | #define CS4271_MODE1_MODE_4X 0xC0 | |
63 | ||
64 | #define CS4271_MODE1_DIV_MASK 0x30 | |
65 | #define CS4271_MODE1_DIV_1 0x00 | |
66 | #define CS4271_MODE1_DIV_15 0x10 | |
67 | #define CS4271_MODE1_DIV_2 0x20 | |
68 | #define CS4271_MODE1_DIV_3 0x30 | |
69 | ||
70 | #define CS4271_MODE1_MASTER 0x08 | |
71 | ||
72 | #define CS4271_MODE1_DAC_DIF_MASK 0x07 | |
73 | #define CS4271_MODE1_DAC_DIF_LJ 0x00 | |
74 | #define CS4271_MODE1_DAC_DIF_I2S 0x01 | |
75 | #define CS4271_MODE1_DAC_DIF_RJ16 0x02 | |
76 | #define CS4271_MODE1_DAC_DIF_RJ24 0x03 | |
77 | #define CS4271_MODE1_DAC_DIF_RJ20 0x04 | |
78 | #define CS4271_MODE1_DAC_DIF_RJ18 0x05 | |
79 | ||
80 | #define CS4271_DACCTL_AMUTE 0x80 | |
81 | #define CS4271_DACCTL_IF_SLOW 0x40 | |
82 | ||
83 | #define CS4271_DACCTL_DEM_MASK 0x30 | |
84 | #define CS4271_DACCTL_DEM_DIS 0x00 | |
85 | #define CS4271_DACCTL_DEM_441 0x10 | |
86 | #define CS4271_DACCTL_DEM_48 0x20 | |
87 | #define CS4271_DACCTL_DEM_32 0x30 | |
88 | ||
89 | #define CS4271_DACCTL_SVRU 0x08 | |
90 | #define CS4271_DACCTL_SRD 0x04 | |
91 | #define CS4271_DACCTL_INVA 0x02 | |
92 | #define CS4271_DACCTL_INVB 0x01 | |
93 | ||
94 | #define CS4271_DACVOL_BEQUA 0x40 | |
95 | #define CS4271_DACVOL_SOFT 0x20 | |
96 | #define CS4271_DACVOL_ZEROC 0x10 | |
97 | ||
98 | #define CS4271_DACVOL_ATAPI_MASK 0x0F | |
99 | #define CS4271_DACVOL_ATAPI_M_M 0x00 | |
100 | #define CS4271_DACVOL_ATAPI_M_BR 0x01 | |
101 | #define CS4271_DACVOL_ATAPI_M_BL 0x02 | |
102 | #define CS4271_DACVOL_ATAPI_M_BLR2 0x03 | |
103 | #define CS4271_DACVOL_ATAPI_AR_M 0x04 | |
104 | #define CS4271_DACVOL_ATAPI_AR_BR 0x05 | |
105 | #define CS4271_DACVOL_ATAPI_AR_BL 0x06 | |
106 | #define CS4271_DACVOL_ATAPI_AR_BLR2 0x07 | |
107 | #define CS4271_DACVOL_ATAPI_AL_M 0x08 | |
108 | #define CS4271_DACVOL_ATAPI_AL_BR 0x09 | |
109 | #define CS4271_DACVOL_ATAPI_AL_BL 0x0A | |
110 | #define CS4271_DACVOL_ATAPI_AL_BLR2 0x0B | |
111 | #define CS4271_DACVOL_ATAPI_ALR2_M 0x0C | |
112 | #define CS4271_DACVOL_ATAPI_ALR2_BR 0x0D | |
113 | #define CS4271_DACVOL_ATAPI_ALR2_BL 0x0E | |
114 | #define CS4271_DACVOL_ATAPI_ALR2_BLR2 0x0F | |
115 | ||
116 | #define CS4271_VOLA_MUTE 0x80 | |
117 | #define CS4271_VOLA_VOL_MASK 0x7F | |
118 | #define CS4271_VOLB_MUTE 0x80 | |
119 | #define CS4271_VOLB_VOL_MASK 0x7F | |
120 | ||
121 | #define CS4271_ADCCTL_DITHER16 0x20 | |
122 | ||
123 | #define CS4271_ADCCTL_ADC_DIF_MASK 0x10 | |
124 | #define CS4271_ADCCTL_ADC_DIF_LJ 0x00 | |
125 | #define CS4271_ADCCTL_ADC_DIF_I2S 0x10 | |
126 | ||
127 | #define CS4271_ADCCTL_MUTEA 0x08 | |
128 | #define CS4271_ADCCTL_MUTEB 0x04 | |
129 | #define CS4271_ADCCTL_HPFDA 0x02 | |
130 | #define CS4271_ADCCTL_HPFDB 0x01 | |
131 | ||
132 | #define CS4271_MODE2_LOOP 0x10 | |
133 | #define CS4271_MODE2_MUTECAEQUB 0x08 | |
134 | #define CS4271_MODE2_FREEZE 0x04 | |
135 | #define CS4271_MODE2_CPEN 0x02 | |
136 | #define CS4271_MODE2_PDN 0x01 | |
137 | ||
138 | #define CS4271_CHIPID_PART_MASK 0xF0 | |
139 | #define CS4271_CHIPID_REV_MASK 0x0F | |
140 | ||
141 | /* | |
142 | * Default CS4271 power-up configuration | |
143 | * Array contains non-existing in hw register at address 0 | |
144 | * Array do not include Chip ID, as codec driver does not use | |
145 | * registers read operations at all | |
146 | */ | |
147 | static const u8 cs4271_dflt_reg[CS4271_NR_REGS] = { | |
148 | 0, | |
149 | 0, | |
150 | CS4271_DACCTL_AMUTE, | |
151 | CS4271_DACVOL_SOFT | CS4271_DACVOL_ATAPI_AL_BR, | |
152 | 0, | |
153 | 0, | |
154 | 0, | |
155 | 0, | |
156 | }; | |
157 | ||
158 | struct cs4271_private { | |
159 | /* SND_SOC_I2C or SND_SOC_SPI */ | |
160 | enum snd_soc_control_type bus_type; | |
67b22517 AS |
161 | unsigned int mclk; |
162 | bool master; | |
163 | bool deemph; | |
164 | /* Current sample rate for de-emphasis control */ | |
165 | int rate; | |
166 | /* GPIO driving Reset pin, if any */ | |
167 | int gpio_nreset; | |
168 | /* GPIO that disable serial bus, if any */ | |
169 | int gpio_disable; | |
fd23fb9f DM |
170 | /* enable soft reset workaround */ |
171 | bool enable_soft_reset; | |
67b22517 AS |
172 | }; |
173 | ||
67b22517 AS |
174 | /* |
175 | * @freq is the desired MCLK rate | |
176 | * MCLK rate should (c) be the sample rate, multiplied by one of the | |
177 | * ratios listed in cs4271_mclk_fs_ratios table | |
178 | */ | |
179 | static int cs4271_set_dai_sysclk(struct snd_soc_dai *codec_dai, | |
180 | int clk_id, unsigned int freq, int dir) | |
181 | { | |
182 | struct snd_soc_codec *codec = codec_dai->codec; | |
183 | struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); | |
184 | ||
185 | cs4271->mclk = freq; | |
186 | return 0; | |
187 | } | |
188 | ||
189 | static int cs4271_set_dai_fmt(struct snd_soc_dai *codec_dai, | |
190 | unsigned int format) | |
191 | { | |
192 | struct snd_soc_codec *codec = codec_dai->codec; | |
193 | struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); | |
194 | unsigned int val = 0; | |
0d42e6e7 | 195 | int ret; |
67b22517 AS |
196 | |
197 | switch (format & SND_SOC_DAIFMT_MASTER_MASK) { | |
198 | case SND_SOC_DAIFMT_CBS_CFS: | |
199 | cs4271->master = 0; | |
200 | break; | |
201 | case SND_SOC_DAIFMT_CBM_CFM: | |
202 | cs4271->master = 1; | |
203 | val |= CS4271_MODE1_MASTER; | |
204 | break; | |
205 | default: | |
206 | dev_err(codec->dev, "Invalid DAI format\n"); | |
207 | return -EINVAL; | |
208 | } | |
209 | ||
210 | switch (format & SND_SOC_DAIFMT_FORMAT_MASK) { | |
211 | case SND_SOC_DAIFMT_LEFT_J: | |
212 | val |= CS4271_MODE1_DAC_DIF_LJ; | |
0d42e6e7 | 213 | ret = snd_soc_update_bits(codec, CS4271_ADCCTL, |
67b22517 | 214 | CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_LJ); |
0d42e6e7 AS |
215 | if (ret < 0) |
216 | return ret; | |
67b22517 AS |
217 | break; |
218 | case SND_SOC_DAIFMT_I2S: | |
219 | val |= CS4271_MODE1_DAC_DIF_I2S; | |
0d42e6e7 | 220 | ret = snd_soc_update_bits(codec, CS4271_ADCCTL, |
67b22517 | 221 | CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_I2S); |
0d42e6e7 AS |
222 | if (ret < 0) |
223 | return ret; | |
67b22517 AS |
224 | break; |
225 | default: | |
226 | dev_err(codec->dev, "Invalid DAI format\n"); | |
227 | return -EINVAL; | |
228 | } | |
229 | ||
0d42e6e7 | 230 | ret = snd_soc_update_bits(codec, CS4271_MODE1, |
67b22517 | 231 | CS4271_MODE1_DAC_DIF_MASK | CS4271_MODE1_MASTER, val); |
0d42e6e7 AS |
232 | if (ret < 0) |
233 | return ret; | |
67b22517 AS |
234 | return 0; |
235 | } | |
236 | ||
237 | static int cs4271_deemph[] = {0, 44100, 48000, 32000}; | |
238 | ||
239 | static int cs4271_set_deemph(struct snd_soc_codec *codec) | |
240 | { | |
241 | struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); | |
0d42e6e7 | 242 | int i, ret; |
67b22517 AS |
243 | int val = CS4271_DACCTL_DEM_DIS; |
244 | ||
245 | if (cs4271->deemph) { | |
246 | /* Find closest de-emphasis freq */ | |
247 | val = 1; | |
248 | for (i = 2; i < ARRAY_SIZE(cs4271_deemph); i++) | |
249 | if (abs(cs4271_deemph[i] - cs4271->rate) < | |
250 | abs(cs4271_deemph[val] - cs4271->rate)) | |
251 | val = i; | |
252 | val <<= 4; | |
253 | } | |
254 | ||
0d42e6e7 | 255 | ret = snd_soc_update_bits(codec, CS4271_DACCTL, |
67b22517 | 256 | CS4271_DACCTL_DEM_MASK, val); |
0d42e6e7 AS |
257 | if (ret < 0) |
258 | return ret; | |
259 | return 0; | |
67b22517 AS |
260 | } |
261 | ||
262 | static int cs4271_get_deemph(struct snd_kcontrol *kcontrol, | |
263 | struct snd_ctl_elem_value *ucontrol) | |
264 | { | |
265 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
266 | struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); | |
267 | ||
268 | ucontrol->value.enumerated.item[0] = cs4271->deemph; | |
269 | return 0; | |
270 | } | |
271 | ||
272 | static int cs4271_put_deemph(struct snd_kcontrol *kcontrol, | |
273 | struct snd_ctl_elem_value *ucontrol) | |
274 | { | |
275 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
276 | struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); | |
277 | ||
278 | cs4271->deemph = ucontrol->value.enumerated.item[0]; | |
279 | return cs4271_set_deemph(codec); | |
280 | } | |
281 | ||
5c3a12e9 AS |
282 | struct cs4271_clk_cfg { |
283 | bool master; /* codec mode */ | |
284 | u8 speed_mode; /* codec speed mode: 1x, 2x, 4x */ | |
285 | unsigned short ratio; /* MCLK / sample rate */ | |
286 | u8 ratio_mask; /* ratio bit mask for Master mode */ | |
287 | }; | |
288 | ||
289 | static struct cs4271_clk_cfg cs4271_clk_tab[] = { | |
290 | {1, CS4271_MODE1_MODE_1X, 256, CS4271_MODE1_DIV_1}, | |
291 | {1, CS4271_MODE1_MODE_1X, 384, CS4271_MODE1_DIV_15}, | |
292 | {1, CS4271_MODE1_MODE_1X, 512, CS4271_MODE1_DIV_2}, | |
293 | {1, CS4271_MODE1_MODE_1X, 768, CS4271_MODE1_DIV_3}, | |
294 | {1, CS4271_MODE1_MODE_2X, 128, CS4271_MODE1_DIV_1}, | |
295 | {1, CS4271_MODE1_MODE_2X, 192, CS4271_MODE1_DIV_15}, | |
296 | {1, CS4271_MODE1_MODE_2X, 256, CS4271_MODE1_DIV_2}, | |
297 | {1, CS4271_MODE1_MODE_2X, 384, CS4271_MODE1_DIV_3}, | |
298 | {1, CS4271_MODE1_MODE_4X, 64, CS4271_MODE1_DIV_1}, | |
299 | {1, CS4271_MODE1_MODE_4X, 96, CS4271_MODE1_DIV_15}, | |
300 | {1, CS4271_MODE1_MODE_4X, 128, CS4271_MODE1_DIV_2}, | |
301 | {1, CS4271_MODE1_MODE_4X, 192, CS4271_MODE1_DIV_3}, | |
302 | {0, CS4271_MODE1_MODE_1X, 256, CS4271_MODE1_DIV_1}, | |
303 | {0, CS4271_MODE1_MODE_1X, 384, CS4271_MODE1_DIV_1}, | |
304 | {0, CS4271_MODE1_MODE_1X, 512, CS4271_MODE1_DIV_1}, | |
305 | {0, CS4271_MODE1_MODE_1X, 768, CS4271_MODE1_DIV_2}, | |
306 | {0, CS4271_MODE1_MODE_1X, 1024, CS4271_MODE1_DIV_2}, | |
307 | {0, CS4271_MODE1_MODE_2X, 128, CS4271_MODE1_DIV_1}, | |
308 | {0, CS4271_MODE1_MODE_2X, 192, CS4271_MODE1_DIV_1}, | |
309 | {0, CS4271_MODE1_MODE_2X, 256, CS4271_MODE1_DIV_1}, | |
310 | {0, CS4271_MODE1_MODE_2X, 384, CS4271_MODE1_DIV_2}, | |
311 | {0, CS4271_MODE1_MODE_2X, 512, CS4271_MODE1_DIV_2}, | |
312 | {0, CS4271_MODE1_MODE_4X, 64, CS4271_MODE1_DIV_1}, | |
313 | {0, CS4271_MODE1_MODE_4X, 96, CS4271_MODE1_DIV_1}, | |
314 | {0, CS4271_MODE1_MODE_4X, 128, CS4271_MODE1_DIV_1}, | |
315 | {0, CS4271_MODE1_MODE_4X, 192, CS4271_MODE1_DIV_2}, | |
316 | {0, CS4271_MODE1_MODE_4X, 256, CS4271_MODE1_DIV_2}, | |
317 | }; | |
318 | ||
319 | #define CS4171_NR_RATIOS ARRAY_SIZE(cs4271_clk_tab) | |
320 | ||
67b22517 AS |
321 | static int cs4271_hw_params(struct snd_pcm_substream *substream, |
322 | struct snd_pcm_hw_params *params, | |
323 | struct snd_soc_dai *dai) | |
324 | { | |
e6968a17 | 325 | struct snd_soc_codec *codec = dai->codec; |
67b22517 | 326 | struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); |
0d42e6e7 AS |
327 | int i, ret; |
328 | unsigned int ratio, val; | |
67b22517 | 329 | |
fd23fb9f DM |
330 | if (cs4271->enable_soft_reset) { |
331 | /* | |
332 | * Put the codec in soft reset and back again in case it's not | |
333 | * currently streaming data. This way of bringing the codec in | |
334 | * sync to the current clocks is not explicitly documented in | |
335 | * the data sheet, but it seems to work fine, and in contrast | |
336 | * to a read hardware reset, we don't have to sync back all | |
337 | * registers every time. | |
338 | */ | |
339 | ||
340 | if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK && | |
341 | !dai->capture_active) || | |
342 | (substream->stream == SNDRV_PCM_STREAM_CAPTURE && | |
343 | !dai->playback_active)) { | |
344 | ret = snd_soc_update_bits(codec, CS4271_MODE2, | |
345 | CS4271_MODE2_PDN, | |
346 | CS4271_MODE2_PDN); | |
347 | if (ret < 0) | |
348 | return ret; | |
349 | ||
350 | ret = snd_soc_update_bits(codec, CS4271_MODE2, | |
351 | CS4271_MODE2_PDN, 0); | |
352 | if (ret < 0) | |
353 | return ret; | |
354 | } | |
355 | } | |
356 | ||
67b22517 | 357 | cs4271->rate = params_rate(params); |
5c3a12e9 AS |
358 | |
359 | /* Configure DAC */ | |
360 | if (cs4271->rate < 50000) | |
361 | val = CS4271_MODE1_MODE_1X; | |
362 | else if (cs4271->rate < 100000) | |
363 | val = CS4271_MODE1_MODE_2X; | |
364 | else | |
365 | val = CS4271_MODE1_MODE_4X; | |
366 | ||
67b22517 AS |
367 | ratio = cs4271->mclk / cs4271->rate; |
368 | for (i = 0; i < CS4171_NR_RATIOS; i++) | |
5c3a12e9 AS |
369 | if ((cs4271_clk_tab[i].master == cs4271->master) && |
370 | (cs4271_clk_tab[i].speed_mode == val) && | |
371 | (cs4271_clk_tab[i].ratio == ratio)) | |
67b22517 AS |
372 | break; |
373 | ||
5c3a12e9 | 374 | if (i == CS4171_NR_RATIOS) { |
67b22517 AS |
375 | dev_err(codec->dev, "Invalid sample rate\n"); |
376 | return -EINVAL; | |
377 | } | |
378 | ||
5c3a12e9 | 379 | val |= cs4271_clk_tab[i].ratio_mask; |
67b22517 | 380 | |
0d42e6e7 | 381 | ret = snd_soc_update_bits(codec, CS4271_MODE1, |
67b22517 | 382 | CS4271_MODE1_MODE_MASK | CS4271_MODE1_DIV_MASK, val); |
0d42e6e7 AS |
383 | if (ret < 0) |
384 | return ret; | |
67b22517 AS |
385 | |
386 | return cs4271_set_deemph(codec); | |
387 | } | |
388 | ||
389 | static int cs4271_digital_mute(struct snd_soc_dai *dai, int mute) | |
390 | { | |
391 | struct snd_soc_codec *codec = dai->codec; | |
0d42e6e7 | 392 | int ret; |
67b22517 AS |
393 | int val_a = 0; |
394 | int val_b = 0; | |
395 | ||
396 | if (mute) { | |
397 | val_a = CS4271_VOLA_MUTE; | |
398 | val_b = CS4271_VOLB_MUTE; | |
399 | } | |
400 | ||
0d42e6e7 AS |
401 | ret = snd_soc_update_bits(codec, CS4271_VOLA, CS4271_VOLA_MUTE, val_a); |
402 | if (ret < 0) | |
403 | return ret; | |
404 | ret = snd_soc_update_bits(codec, CS4271_VOLB, CS4271_VOLB_MUTE, val_b); | |
405 | if (ret < 0) | |
406 | return ret; | |
67b22517 AS |
407 | |
408 | return 0; | |
409 | } | |
410 | ||
411 | /* CS4271 controls */ | |
412 | static DECLARE_TLV_DB_SCALE(cs4271_dac_tlv, -12700, 100, 0); | |
413 | ||
414 | static const struct snd_kcontrol_new cs4271_snd_controls[] = { | |
415 | SOC_DOUBLE_R_TLV("Master Playback Volume", CS4271_VOLA, CS4271_VOLB, | |
416 | 0, 0x7F, 1, cs4271_dac_tlv), | |
417 | SOC_SINGLE("Digital Loopback Switch", CS4271_MODE2, 4, 1, 0), | |
418 | SOC_SINGLE("Soft Ramp Switch", CS4271_DACVOL, 5, 1, 0), | |
419 | SOC_SINGLE("Zero Cross Switch", CS4271_DACVOL, 4, 1, 0), | |
420 | SOC_SINGLE_BOOL_EXT("De-emphasis Switch", 0, | |
421 | cs4271_get_deemph, cs4271_put_deemph), | |
422 | SOC_SINGLE("Auto-Mute Switch", CS4271_DACCTL, 7, 1, 0), | |
423 | SOC_SINGLE("Slow Roll Off Filter Switch", CS4271_DACCTL, 6, 1, 0), | |
424 | SOC_SINGLE("Soft Volume Ramp-Up Switch", CS4271_DACCTL, 3, 1, 0), | |
425 | SOC_SINGLE("Soft Ramp-Down Switch", CS4271_DACCTL, 2, 1, 0), | |
426 | SOC_SINGLE("Left Channel Inversion Switch", CS4271_DACCTL, 1, 1, 0), | |
427 | SOC_SINGLE("Right Channel Inversion Switch", CS4271_DACCTL, 0, 1, 0), | |
428 | SOC_DOUBLE("Master Capture Switch", CS4271_ADCCTL, 3, 2, 1, 1), | |
429 | SOC_SINGLE("Dither 16-Bit Data Switch", CS4271_ADCCTL, 5, 1, 0), | |
430 | SOC_DOUBLE("High Pass Filter Switch", CS4271_ADCCTL, 1, 0, 1, 1), | |
431 | SOC_DOUBLE_R("Master Playback Switch", CS4271_VOLA, CS4271_VOLB, | |
432 | 7, 1, 1), | |
433 | }; | |
434 | ||
85e7652d | 435 | static const struct snd_soc_dai_ops cs4271_dai_ops = { |
67b22517 AS |
436 | .hw_params = cs4271_hw_params, |
437 | .set_sysclk = cs4271_set_dai_sysclk, | |
438 | .set_fmt = cs4271_set_dai_fmt, | |
439 | .digital_mute = cs4271_digital_mute, | |
440 | }; | |
441 | ||
16af7d60 | 442 | static struct snd_soc_dai_driver cs4271_dai = { |
67b22517 AS |
443 | .name = "cs4271-hifi", |
444 | .playback = { | |
445 | .stream_name = "Playback", | |
446 | .channels_min = 2, | |
447 | .channels_max = 2, | |
383f8465 | 448 | .rates = CS4271_PCM_RATES, |
67b22517 AS |
449 | .formats = CS4271_PCM_FORMATS, |
450 | }, | |
451 | .capture = { | |
452 | .stream_name = "Capture", | |
453 | .channels_min = 2, | |
454 | .channels_max = 2, | |
383f8465 | 455 | .rates = CS4271_PCM_RATES, |
67b22517 AS |
456 | .formats = CS4271_PCM_FORMATS, |
457 | }, | |
458 | .ops = &cs4271_dai_ops, | |
459 | .symmetric_rates = 1, | |
460 | }; | |
461 | ||
462 | #ifdef CONFIG_PM | |
84b315ee | 463 | static int cs4271_soc_suspend(struct snd_soc_codec *codec) |
67b22517 | 464 | { |
0d42e6e7 | 465 | int ret; |
67b22517 | 466 | /* Set power-down bit */ |
ef0cd470 AL |
467 | ret = snd_soc_update_bits(codec, CS4271_MODE2, CS4271_MODE2_PDN, |
468 | CS4271_MODE2_PDN); | |
0d42e6e7 AS |
469 | if (ret < 0) |
470 | return ret; | |
67b22517 AS |
471 | return 0; |
472 | } | |
473 | ||
474 | static int cs4271_soc_resume(struct snd_soc_codec *codec) | |
475 | { | |
0d42e6e7 | 476 | int ret; |
67b22517 | 477 | /* Restore codec state */ |
0d42e6e7 AS |
478 | ret = snd_soc_cache_sync(codec); |
479 | if (ret < 0) | |
480 | return ret; | |
67b22517 | 481 | /* then disable the power-down bit */ |
0d42e6e7 AS |
482 | ret = snd_soc_update_bits(codec, CS4271_MODE2, CS4271_MODE2_PDN, 0); |
483 | if (ret < 0) | |
484 | return ret; | |
67b22517 AS |
485 | return 0; |
486 | } | |
487 | #else | |
488 | #define cs4271_soc_suspend NULL | |
489 | #define cs4271_soc_resume NULL | |
490 | #endif /* CONFIG_PM */ | |
491 | ||
a31ebc34 DM |
492 | #ifdef CONFIG_OF |
493 | static const struct of_device_id cs4271_dt_ids[] = { | |
494 | { .compatible = "cirrus,cs4271", }, | |
495 | { } | |
496 | }; | |
497 | MODULE_DEVICE_TABLE(of, cs4271_dt_ids); | |
498 | #endif | |
499 | ||
67b22517 AS |
500 | static int cs4271_probe(struct snd_soc_codec *codec) |
501 | { | |
502 | struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); | |
503 | struct cs4271_platform_data *cs4271plat = codec->dev->platform_data; | |
504 | int ret; | |
505 | int gpio_nreset = -EINVAL; | |
26047e2d | 506 | bool amutec_eq_bmutec = false; |
67b22517 | 507 | |
a31ebc34 | 508 | #ifdef CONFIG_OF |
293750f9 | 509 | if (of_match_device(cs4271_dt_ids, codec->dev)) { |
a31ebc34 DM |
510 | gpio_nreset = of_get_named_gpio(codec->dev->of_node, |
511 | "reset-gpio", 0); | |
293750f9 | 512 | |
b8455c9f | 513 | if (of_get_property(codec->dev->of_node, |
293750f9 | 514 | "cirrus,amutec-eq-bmutec", NULL)) |
26047e2d | 515 | amutec_eq_bmutec = true; |
fd23fb9f DM |
516 | |
517 | if (of_get_property(codec->dev->of_node, | |
518 | "cirrus,enable-soft-reset", NULL)) | |
519 | cs4271->enable_soft_reset = true; | |
293750f9 | 520 | } |
a31ebc34 DM |
521 | #endif |
522 | ||
293750f9 DM |
523 | if (cs4271plat) { |
524 | if (gpio_is_valid(cs4271plat->gpio_nreset)) | |
525 | gpio_nreset = cs4271plat->gpio_nreset; | |
526 | ||
527 | amutec_eq_bmutec = cs4271plat->amutec_eq_bmutec; | |
fd23fb9f | 528 | cs4271->enable_soft_reset = cs4271plat->enable_soft_reset; |
293750f9 | 529 | } |
67b22517 AS |
530 | |
531 | if (gpio_nreset >= 0) | |
5574f774 | 532 | if (devm_gpio_request(codec->dev, gpio_nreset, "CS4271 Reset")) |
67b22517 AS |
533 | gpio_nreset = -EINVAL; |
534 | if (gpio_nreset >= 0) { | |
535 | /* Reset codec */ | |
536 | gpio_direction_output(gpio_nreset, 0); | |
537 | udelay(1); | |
538 | gpio_set_value(gpio_nreset, 1); | |
539 | /* Give the codec time to wake up */ | |
540 | udelay(1); | |
541 | } | |
542 | ||
543 | cs4271->gpio_nreset = gpio_nreset; | |
67b22517 AS |
544 | |
545 | /* | |
546 | * In case of I2C, chip address specified in board data. | |
547 | * So cache IO operations use 8 bit codec register address. | |
548 | * In case of SPI, chip address and register address | |
549 | * passed together as 16 bit value. | |
550 | * Anyway, register address is masked with 0xFF inside | |
551 | * soc-cache code. | |
552 | */ | |
553 | if (cs4271->bus_type == SND_SOC_SPI) | |
554 | ret = snd_soc_codec_set_cache_io(codec, 16, 8, | |
555 | cs4271->bus_type); | |
556 | else | |
557 | ret = snd_soc_codec_set_cache_io(codec, 8, 8, | |
558 | cs4271->bus_type); | |
559 | if (ret) { | |
560 | dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); | |
561 | return ret; | |
562 | } | |
563 | ||
ef0cd470 AL |
564 | ret = snd_soc_update_bits(codec, CS4271_MODE2, |
565 | CS4271_MODE2_PDN | CS4271_MODE2_CPEN, | |
566 | CS4271_MODE2_PDN | CS4271_MODE2_CPEN); | |
0d42e6e7 AS |
567 | if (ret < 0) |
568 | return ret; | |
569 | ret = snd_soc_update_bits(codec, CS4271_MODE2, CS4271_MODE2_PDN, 0); | |
570 | if (ret < 0) | |
571 | return ret; | |
67b22517 AS |
572 | /* Power-up sequence requires 85 uS */ |
573 | udelay(85); | |
574 | ||
293750f9 DM |
575 | if (amutec_eq_bmutec) |
576 | snd_soc_update_bits(codec, CS4271_MODE2, | |
577 | CS4271_MODE2_MUTECAEQUB, | |
578 | CS4271_MODE2_MUTECAEQUB); | |
579 | ||
022658be | 580 | return snd_soc_add_codec_controls(codec, cs4271_snd_controls, |
67b22517 AS |
581 | ARRAY_SIZE(cs4271_snd_controls)); |
582 | } | |
583 | ||
584 | static int cs4271_remove(struct snd_soc_codec *codec) | |
585 | { | |
586 | struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); | |
67b22517 | 587 | |
5574f774 | 588 | if (gpio_is_valid(cs4271->gpio_nreset)) |
67b22517 | 589 | /* Set codec to the reset state */ |
5574f774 | 590 | gpio_set_value(cs4271->gpio_nreset, 0); |
67b22517 | 591 | |
67b22517 AS |
592 | return 0; |
593 | }; | |
594 | ||
16af7d60 | 595 | static struct snd_soc_codec_driver soc_codec_dev_cs4271 = { |
67b22517 AS |
596 | .probe = cs4271_probe, |
597 | .remove = cs4271_remove, | |
598 | .suspend = cs4271_soc_suspend, | |
599 | .resume = cs4271_soc_resume, | |
600 | .reg_cache_default = cs4271_dflt_reg, | |
601 | .reg_cache_size = ARRAY_SIZE(cs4271_dflt_reg), | |
602 | .reg_word_size = sizeof(cs4271_dflt_reg[0]), | |
603 | .compress_type = SND_SOC_FLAT_COMPRESSION, | |
604 | }; | |
605 | ||
606 | #if defined(CONFIG_SPI_MASTER) | |
7a79e94e | 607 | static int cs4271_spi_probe(struct spi_device *spi) |
67b22517 AS |
608 | { |
609 | struct cs4271_private *cs4271; | |
610 | ||
611 | cs4271 = devm_kzalloc(&spi->dev, sizeof(*cs4271), GFP_KERNEL); | |
612 | if (!cs4271) | |
613 | return -ENOMEM; | |
614 | ||
615 | spi_set_drvdata(spi, cs4271); | |
67b22517 AS |
616 | cs4271->bus_type = SND_SOC_SPI; |
617 | ||
618 | return snd_soc_register_codec(&spi->dev, &soc_codec_dev_cs4271, | |
619 | &cs4271_dai, 1); | |
620 | } | |
621 | ||
7a79e94e | 622 | static int cs4271_spi_remove(struct spi_device *spi) |
67b22517 AS |
623 | { |
624 | snd_soc_unregister_codec(&spi->dev); | |
625 | return 0; | |
626 | } | |
627 | ||
628 | static struct spi_driver cs4271_spi_driver = { | |
629 | .driver = { | |
630 | .name = "cs4271", | |
631 | .owner = THIS_MODULE, | |
a31ebc34 | 632 | .of_match_table = of_match_ptr(cs4271_dt_ids), |
67b22517 AS |
633 | }, |
634 | .probe = cs4271_spi_probe, | |
7a79e94e | 635 | .remove = cs4271_spi_remove, |
67b22517 AS |
636 | }; |
637 | #endif /* defined(CONFIG_SPI_MASTER) */ | |
638 | ||
639 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | |
79a54ea1 | 640 | static const struct i2c_device_id cs4271_i2c_id[] = { |
67b22517 AS |
641 | {"cs4271", 0}, |
642 | {} | |
643 | }; | |
644 | MODULE_DEVICE_TABLE(i2c, cs4271_i2c_id); | |
645 | ||
7a79e94e BP |
646 | static int cs4271_i2c_probe(struct i2c_client *client, |
647 | const struct i2c_device_id *id) | |
67b22517 AS |
648 | { |
649 | struct cs4271_private *cs4271; | |
650 | ||
651 | cs4271 = devm_kzalloc(&client->dev, sizeof(*cs4271), GFP_KERNEL); | |
652 | if (!cs4271) | |
653 | return -ENOMEM; | |
654 | ||
655 | i2c_set_clientdata(client, cs4271); | |
67b22517 AS |
656 | cs4271->bus_type = SND_SOC_I2C; |
657 | ||
658 | return snd_soc_register_codec(&client->dev, &soc_codec_dev_cs4271, | |
659 | &cs4271_dai, 1); | |
660 | } | |
661 | ||
7a79e94e | 662 | static int cs4271_i2c_remove(struct i2c_client *client) |
67b22517 AS |
663 | { |
664 | snd_soc_unregister_codec(&client->dev); | |
665 | return 0; | |
666 | } | |
667 | ||
668 | static struct i2c_driver cs4271_i2c_driver = { | |
669 | .driver = { | |
670 | .name = "cs4271", | |
671 | .owner = THIS_MODULE, | |
a31ebc34 | 672 | .of_match_table = of_match_ptr(cs4271_dt_ids), |
67b22517 AS |
673 | }, |
674 | .id_table = cs4271_i2c_id, | |
675 | .probe = cs4271_i2c_probe, | |
7a79e94e | 676 | .remove = cs4271_i2c_remove, |
67b22517 AS |
677 | }; |
678 | #endif /* defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) */ | |
679 | ||
680 | /* | |
681 | * We only register our serial bus driver here without | |
682 | * assignment to particular chip. So if any of the below | |
683 | * fails, there is some problem with I2C or SPI subsystem. | |
684 | * In most cases this module will be compiled with support | |
685 | * of only one serial bus. | |
686 | */ | |
687 | static int __init cs4271_modinit(void) | |
688 | { | |
689 | int ret; | |
690 | ||
691 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | |
692 | ret = i2c_add_driver(&cs4271_i2c_driver); | |
693 | if (ret) { | |
694 | pr_err("Failed to register CS4271 I2C driver: %d\n", ret); | |
695 | return ret; | |
696 | } | |
697 | #endif | |
698 | ||
699 | #if defined(CONFIG_SPI_MASTER) | |
700 | ret = spi_register_driver(&cs4271_spi_driver); | |
701 | if (ret) { | |
702 | pr_err("Failed to register CS4271 SPI driver: %d\n", ret); | |
703 | return ret; | |
704 | } | |
705 | #endif | |
706 | ||
707 | return 0; | |
708 | } | |
709 | module_init(cs4271_modinit); | |
710 | ||
711 | static void __exit cs4271_modexit(void) | |
712 | { | |
713 | #if defined(CONFIG_SPI_MASTER) | |
714 | spi_unregister_driver(&cs4271_spi_driver); | |
715 | #endif | |
716 | ||
717 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | |
718 | i2c_del_driver(&cs4271_i2c_driver); | |
719 | #endif | |
720 | } | |
721 | module_exit(cs4271_modexit); | |
722 | ||
723 | MODULE_AUTHOR("Alexander Sverdlin <subaparts@yandex.ru>"); | |
724 | MODULE_DESCRIPTION("Cirrus Logic CS4271 ALSA SoC Codec Driver"); | |
725 | MODULE_LICENSE("GPL"); |