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Merge branch 'topic/hdac' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie...
[deliverable/linux.git] / sound / soc / codecs / cs4271.c
CommitLineData
67b22517
AS		 1/*
2 * CS4271 ASoC codec driver
3 *
4 * Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * This driver support CS4271 codec being master or slave, working
17 * in control port mode, connected either via SPI or I2C.
18 * The data format accepted is I2S or left-justified.
19 * DAPM support not implemented.
20 */
21
22#include <linux/module.h>
23#include <linux/slab.h>
24#include <linux/delay.h>
67b22517 25#include <linux/gpio.h>
a7ea1b72 26#include <linux/of.h>
a31ebc34
DM		 27#include <linux/of_device.h>
28#include <linux/of_gpio.h>
29#include <sound/pcm.h>
30#include <sound/soc.h>
31#include <sound/tlv.h>
67b22517 32#include <sound/cs4271.h>
c973b8a7 33#include "cs4271.h"
67b22517
AS		 34
35#define CS4271_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
36 SNDRV_PCM_FMTBIT_S24_LE | \
37 SNDRV_PCM_FMTBIT_S32_LE)
383f8465 38#define CS4271_PCM_RATES SNDRV_PCM_RATE_8000_192000
67b22517
AS		 39
40/*
41 * CS4271 registers
67b22517 42 */
1b1861ea
DM		 43#define CS4271_MODE1 0x01 /* Mode Control 1 */
44#define CS4271_DACCTL 0x02 /* DAC Control */
45#define CS4271_DACVOL 0x03 /* DAC Volume & Mixing Control */
46#define CS4271_VOLA 0x04 /* DAC Channel A Volume Control */
47#define CS4271_VOLB 0x05 /* DAC Channel B Volume Control */
48#define CS4271_ADCCTL 0x06 /* ADC Control */
49#define CS4271_MODE2 0x07 /* Mode Control 2 */
50#define CS4271_CHIPID 0x08 /* Chip ID */
67b22517
AS		 51
52#define CS4271_FIRSTREG CS4271_MODE1
53#define CS4271_LASTREG CS4271_MODE2
54#define CS4271_NR_REGS ((CS4271_LASTREG & 0xFF) + 1)
55
56/* Bit masks for the CS4271 registers */
57#define CS4271_MODE1_MODE_MASK 0xC0
58#define CS4271_MODE1_MODE_1X 0x00
59#define CS4271_MODE1_MODE_2X 0x80
60#define CS4271_MODE1_MODE_4X 0xC0
61
62#define CS4271_MODE1_DIV_MASK 0x30
63#define CS4271_MODE1_DIV_1 0x00
64#define CS4271_MODE1_DIV_15 0x10
65#define CS4271_MODE1_DIV_2 0x20
66#define CS4271_MODE1_DIV_3 0x30
67
68#define CS4271_MODE1_MASTER 0x08
69
70#define CS4271_MODE1_DAC_DIF_MASK 0x07
71#define CS4271_MODE1_DAC_DIF_LJ 0x00
72#define CS4271_MODE1_DAC_DIF_I2S 0x01
73#define CS4271_MODE1_DAC_DIF_RJ16 0x02
74#define CS4271_MODE1_DAC_DIF_RJ24 0x03
75#define CS4271_MODE1_DAC_DIF_RJ20 0x04
76#define CS4271_MODE1_DAC_DIF_RJ18 0x05
77
78#define CS4271_DACCTL_AMUTE 0x80
79#define CS4271_DACCTL_IF_SLOW 0x40
80
81#define CS4271_DACCTL_DEM_MASK 0x30
82#define CS4271_DACCTL_DEM_DIS 0x00
83#define CS4271_DACCTL_DEM_441 0x10
84#define CS4271_DACCTL_DEM_48 0x20
85#define CS4271_DACCTL_DEM_32 0x30
86
87#define CS4271_DACCTL_SVRU 0x08
88#define CS4271_DACCTL_SRD 0x04
89#define CS4271_DACCTL_INVA 0x02
90#define CS4271_DACCTL_INVB 0x01
91
92#define CS4271_DACVOL_BEQUA 0x40
93#define CS4271_DACVOL_SOFT 0x20
94#define CS4271_DACVOL_ZEROC 0x10
95
96#define CS4271_DACVOL_ATAPI_MASK 0x0F
97#define CS4271_DACVOL_ATAPI_M_M 0x00
98#define CS4271_DACVOL_ATAPI_M_BR 0x01
99#define CS4271_DACVOL_ATAPI_M_BL 0x02
100#define CS4271_DACVOL_ATAPI_M_BLR2 0x03
101#define CS4271_DACVOL_ATAPI_AR_M 0x04
102#define CS4271_DACVOL_ATAPI_AR_BR 0x05
103#define CS4271_DACVOL_ATAPI_AR_BL 0x06
104#define CS4271_DACVOL_ATAPI_AR_BLR2 0x07
105#define CS4271_DACVOL_ATAPI_AL_M 0x08
106#define CS4271_DACVOL_ATAPI_AL_BR 0x09
107#define CS4271_DACVOL_ATAPI_AL_BL 0x0A
108#define CS4271_DACVOL_ATAPI_AL_BLR2 0x0B
109#define CS4271_DACVOL_ATAPI_ALR2_M 0x0C
110#define CS4271_DACVOL_ATAPI_ALR2_BR 0x0D
111#define CS4271_DACVOL_ATAPI_ALR2_BL 0x0E
112#define CS4271_DACVOL_ATAPI_ALR2_BLR2 0x0F
113
114#define CS4271_VOLA_MUTE 0x80
115#define CS4271_VOLA_VOL_MASK 0x7F
116#define CS4271_VOLB_MUTE 0x80
117#define CS4271_VOLB_VOL_MASK 0x7F
118
119#define CS4271_ADCCTL_DITHER16 0x20
120
121#define CS4271_ADCCTL_ADC_DIF_MASK 0x10
122#define CS4271_ADCCTL_ADC_DIF_LJ 0x00
123#define CS4271_ADCCTL_ADC_DIF_I2S 0x10
124
125#define CS4271_ADCCTL_MUTEA 0x08
126#define CS4271_ADCCTL_MUTEB 0x04
127#define CS4271_ADCCTL_HPFDA 0x02
128#define CS4271_ADCCTL_HPFDB 0x01
129
130#define CS4271_MODE2_LOOP 0x10
131#define CS4271_MODE2_MUTECAEQUB 0x08
132#define CS4271_MODE2_FREEZE 0x04
133#define CS4271_MODE2_CPEN 0x02
134#define CS4271_MODE2_PDN 0x01
135
136#define CS4271_CHIPID_PART_MASK 0xF0
137#define CS4271_CHIPID_REV_MASK 0x0F
138
139/*
140 * Default CS4271 power-up configuration
141 * Array contains non-existing in hw register at address 0
142 * Array do not include Chip ID, as codec driver does not use
143 * registers read operations at all
144 */
1b1861ea
DM		 145static const struct reg_default cs4271_reg_defaults[] = {
146 { CS4271_MODE1, 0, },
147 { CS4271_DACCTL, CS4271_DACCTL_AMUTE, },
148 { CS4271_DACVOL, CS4271_DACVOL_SOFT | CS4271_DACVOL_ATAPI_AL_BR, },
149 { CS4271_VOLA, 0, },
150 { CS4271_VOLB, 0, },
151 { CS4271_ADCCTL, 0, },
152 { CS4271_MODE2, 0, },
67b22517
AS		 153};
154
1b1861ea
DM		 155static bool cs4271_volatile_reg(struct device *dev, unsigned int reg)
156{
157 return reg == CS4271_CHIPID;
158}
159
67b22517 160struct cs4271_private {
67b22517
AS		 161 unsigned int mclk;
162 bool master;
163 bool deemph;
1b1861ea 164 struct regmap *regmap;
67b22517
AS		 165 /* Current sample rate for de-emphasis control */
166 int rate;
167 /* GPIO driving Reset pin, if any */
168 int gpio_nreset;
169 /* GPIO that disable serial bus, if any */
170 int gpio_disable;
fd23fb9f
DM		 171 /* enable soft reset workaround */
172 bool enable_soft_reset;
67b22517
AS		 173};
174
2e7fb942
MB		 175static const struct snd_soc_dapm_widget cs4271_dapm_widgets[] = {
176SND_SOC_DAPM_INPUT("AINA"),
177SND_SOC_DAPM_INPUT("AINB"),
178
179SND_SOC_DAPM_OUTPUT("AOUTA+"),
180SND_SOC_DAPM_OUTPUT("AOUTA-"),
181SND_SOC_DAPM_OUTPUT("AOUTB+"),
182SND_SOC_DAPM_OUTPUT("AOUTB-"),
183};
184
185static const struct snd_soc_dapm_route cs4271_dapm_routes[] = {
186 { "Capture", NULL, "AINA" },
187 { "Capture", NULL, "AINB" },
188
189 { "AOUTA+", NULL, "Playback" },
190 { "AOUTA-", NULL, "Playback" },
191 { "AOUTB+", NULL, "Playback" },
192 { "AOUTB-", NULL, "Playback" },
193};
194
67b22517
AS		 195/*
196 * @freq is the desired MCLK rate
197 * MCLK rate should (c) be the sample rate, multiplied by one of the
198 * ratios listed in cs4271_mclk_fs_ratios table
199 */
200static int cs4271_set_dai_sysclk(struct snd_soc_dai *codec_dai,
201 int clk_id, unsigned int freq, int dir)
202{
203 struct snd_soc_codec *codec = codec_dai->codec;
204 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
205
206 cs4271->mclk = freq;
207 return 0;
208}
209
210static int cs4271_set_dai_fmt(struct snd_soc_dai *codec_dai,
211 unsigned int format)
212{
213 struct snd_soc_codec *codec = codec_dai->codec;
214 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
215 unsigned int val = 0;
0d42e6e7 216 int ret;
67b22517
AS		 217
218 switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
219 case SND_SOC_DAIFMT_CBS_CFS:
220 cs4271->master = 0;
221 break;
222 case SND_SOC_DAIFMT_CBM_CFM:
223 cs4271->master = 1;
224 val |= CS4271_MODE1_MASTER;
225 break;
226 default:
227 dev_err(codec->dev, "Invalid DAI format\n");
228 return -EINVAL;
229 }
230
231 switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
232 case SND_SOC_DAIFMT_LEFT_J:
233 val |= CS4271_MODE1_DAC_DIF_LJ;
1b1861ea 234 ret = regmap_update_bits(cs4271->regmap, CS4271_ADCCTL,
67b22517 235 CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_LJ);
0d42e6e7
AS		 236 if (ret < 0)
237 return ret;
67b22517
AS		 238 break;
239 case SND_SOC_DAIFMT_I2S:
240 val |= CS4271_MODE1_DAC_DIF_I2S;
1b1861ea 241 ret = regmap_update_bits(cs4271->regmap, CS4271_ADCCTL,
67b22517 242 CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_I2S);
0d42e6e7
AS		 243 if (ret < 0)
244 return ret;
67b22517
AS		 245 break;
246 default:
247 dev_err(codec->dev, "Invalid DAI format\n");
248 return -EINVAL;
249 }
250
1b1861ea 251 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE1,
67b22517 252 CS4271_MODE1_DAC_DIF_MASK | CS4271_MODE1_MASTER, val);
0d42e6e7
AS		 253 if (ret < 0)
254 return ret;
67b22517
AS		 255 return 0;
256}
257
258static int cs4271_deemph[] = {0, 44100, 48000, 32000};
259
260static int cs4271_set_deemph(struct snd_soc_codec *codec)
261{
262 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
0d42e6e7 263 int i, ret;
67b22517
AS		 264 int val = CS4271_DACCTL_DEM_DIS;
265
266 if (cs4271->deemph) {
267 /* Find closest de-emphasis freq */
268 val = 1;
269 for (i = 2; i < ARRAY_SIZE(cs4271_deemph); i++)
270 if (abs(cs4271_deemph[i] - cs4271->rate) <
271 abs(cs4271_deemph[val] - cs4271->rate))
272 val = i;
273 val <<= 4;
274 }
275
1b1861ea 276 ret = regmap_update_bits(cs4271->regmap, CS4271_DACCTL,
67b22517 277 CS4271_DACCTL_DEM_MASK, val);
0d42e6e7
AS		 278 if (ret < 0)
279 return ret;
280 return 0;
67b22517
AS		 281}
282
283static int cs4271_get_deemph(struct snd_kcontrol *kcontrol,
284 struct snd_ctl_elem_value *ucontrol)
285{
ea53bf77 286 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
67b22517
AS		 287 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
288
e8371aa0 289 ucontrol->value.integer.value[0] = cs4271->deemph;
67b22517
AS		 290 return 0;
291}
292
293static int cs4271_put_deemph(struct snd_kcontrol *kcontrol,
294 struct snd_ctl_elem_value *ucontrol)
295{
ea53bf77 296 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
67b22517
AS		 297 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
298
e8371aa0 299 cs4271->deemph = ucontrol->value.integer.value[0];
67b22517
AS		 300 return cs4271_set_deemph(codec);
301}
302
5c3a12e9
AS		 303struct cs4271_clk_cfg {
304 bool master; /* codec mode */
305 u8 speed_mode; /* codec speed mode: 1x, 2x, 4x */
306 unsigned short ratio; /* MCLK / sample rate */
307 u8 ratio_mask; /* ratio bit mask for Master mode */
308};
309
310static struct cs4271_clk_cfg cs4271_clk_tab[] = {
311 {1, CS4271_MODE1_MODE_1X, 256, CS4271_MODE1_DIV_1},
312 {1, CS4271_MODE1_MODE_1X, 384, CS4271_MODE1_DIV_15},
313 {1, CS4271_MODE1_MODE_1X, 512, CS4271_MODE1_DIV_2},
314 {1, CS4271_MODE1_MODE_1X, 768, CS4271_MODE1_DIV_3},
315 {1, CS4271_MODE1_MODE_2X, 128, CS4271_MODE1_DIV_1},
316 {1, CS4271_MODE1_MODE_2X, 192, CS4271_MODE1_DIV_15},
317 {1, CS4271_MODE1_MODE_2X, 256, CS4271_MODE1_DIV_2},
318 {1, CS4271_MODE1_MODE_2X, 384, CS4271_MODE1_DIV_3},
319 {1, CS4271_MODE1_MODE_4X, 64, CS4271_MODE1_DIV_1},
320 {1, CS4271_MODE1_MODE_4X, 96, CS4271_MODE1_DIV_15},
321 {1, CS4271_MODE1_MODE_4X, 128, CS4271_MODE1_DIV_2},
322 {1, CS4271_MODE1_MODE_4X, 192, CS4271_MODE1_DIV_3},
323 {0, CS4271_MODE1_MODE_1X, 256, CS4271_MODE1_DIV_1},
324 {0, CS4271_MODE1_MODE_1X, 384, CS4271_MODE1_DIV_1},
325 {0, CS4271_MODE1_MODE_1X, 512, CS4271_MODE1_DIV_1},
326 {0, CS4271_MODE1_MODE_1X, 768, CS4271_MODE1_DIV_2},
327 {0, CS4271_MODE1_MODE_1X, 1024, CS4271_MODE1_DIV_2},
328 {0, CS4271_MODE1_MODE_2X, 128, CS4271_MODE1_DIV_1},
329 {0, CS4271_MODE1_MODE_2X, 192, CS4271_MODE1_DIV_1},
330 {0, CS4271_MODE1_MODE_2X, 256, CS4271_MODE1_DIV_1},
331 {0, CS4271_MODE1_MODE_2X, 384, CS4271_MODE1_DIV_2},
332 {0, CS4271_MODE1_MODE_2X, 512, CS4271_MODE1_DIV_2},
333 {0, CS4271_MODE1_MODE_4X, 64, CS4271_MODE1_DIV_1},
334 {0, CS4271_MODE1_MODE_4X, 96, CS4271_MODE1_DIV_1},
335 {0, CS4271_MODE1_MODE_4X, 128, CS4271_MODE1_DIV_1},
336 {0, CS4271_MODE1_MODE_4X, 192, CS4271_MODE1_DIV_2},
337 {0, CS4271_MODE1_MODE_4X, 256, CS4271_MODE1_DIV_2},
338};
339
340#define CS4171_NR_RATIOS ARRAY_SIZE(cs4271_clk_tab)
341
67b22517
AS		 342static int cs4271_hw_params(struct snd_pcm_substream *substream,
343 struct snd_pcm_hw_params *params,
344 struct snd_soc_dai *dai)
345{
e6968a17 346 struct snd_soc_codec *codec = dai->codec;
67b22517 347 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
0d42e6e7
AS		 348 int i, ret;
349 unsigned int ratio, val;
67b22517 350
fd23fb9f
DM		 351 if (cs4271->enable_soft_reset) {
352 /*
353 * Put the codec in soft reset and back again in case it's not
354 * currently streaming data. This way of bringing the codec in
355 * sync to the current clocks is not explicitly documented in
356 * the data sheet, but it seems to work fine, and in contrast
357 * to a read hardware reset, we don't have to sync back all
358 * registers every time.
359 */
360
361 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK &&
362 !dai->capture_active) ||
363 (substream->stream == SNDRV_PCM_STREAM_CAPTURE &&
364 !dai->playback_active)) {
1b1861ea
DM		 365 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
366 CS4271_MODE2_PDN,
367 CS4271_MODE2_PDN);
fd23fb9f
DM		 368 if (ret < 0)
369 return ret;
370
1b1861ea
DM		 371 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
372 CS4271_MODE2_PDN, 0);
fd23fb9f
DM		 373 if (ret < 0)
374 return ret;
375 }
376 }
377
67b22517 378 cs4271->rate = params_rate(params);
5c3a12e9
AS		 379
380 /* Configure DAC */
381 if (cs4271->rate < 50000)
382 val = CS4271_MODE1_MODE_1X;
383 else if (cs4271->rate < 100000)
384 val = CS4271_MODE1_MODE_2X;
385 else
386 val = CS4271_MODE1_MODE_4X;
387
67b22517
AS		 388 ratio = cs4271->mclk / cs4271->rate;
389 for (i = 0; i < CS4171_NR_RATIOS; i++)
5c3a12e9
AS		 390 if ((cs4271_clk_tab[i].master == cs4271->master) &&
391 (cs4271_clk_tab[i].speed_mode == val) &&
392 (cs4271_clk_tab[i].ratio == ratio))
67b22517
AS		 393 break;
394
5c3a12e9 395 if (i == CS4171_NR_RATIOS) {
67b22517
AS		 396 dev_err(codec->dev, "Invalid sample rate\n");
397 return -EINVAL;
398 }
399
5c3a12e9 400 val |= cs4271_clk_tab[i].ratio_mask;
67b22517 401
1b1861ea 402 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE1,
67b22517 403 CS4271_MODE1_MODE_MASK | CS4271_MODE1_DIV_MASK, val);
0d42e6e7
AS		 404 if (ret < 0)
405 return ret;
67b22517
AS		 406
407 return cs4271_set_deemph(codec);
408}
409
c24a34db 410static int cs4271_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
67b22517
AS		 411{
412 struct snd_soc_codec *codec = dai->codec;
1b1861ea 413 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
0d42e6e7 414 int ret;
67b22517
AS		 415 int val_a = 0;
416 int val_b = 0;
417
c24a34db
DM		 418 if (stream != SNDRV_PCM_STREAM_PLAYBACK)
419 return 0;
420
67b22517
AS		 421 if (mute) {
422 val_a = CS4271_VOLA_MUTE;
423 val_b = CS4271_VOLB_MUTE;
424 }
425
1b1861ea
DM		 426 ret = regmap_update_bits(cs4271->regmap, CS4271_VOLA,
427 CS4271_VOLA_MUTE, val_a);
0d42e6e7
AS		 428 if (ret < 0)
429 return ret;
1b1861ea
DM		 430
431 ret = regmap_update_bits(cs4271->regmap, CS4271_VOLB,
432 CS4271_VOLB_MUTE, val_b);
0d42e6e7
AS		 433 if (ret < 0)
434 return ret;
67b22517
AS		 435
436 return 0;
437}
438
439/* CS4271 controls */
440static DECLARE_TLV_DB_SCALE(cs4271_dac_tlv, -12700, 100, 0);
441
442static const struct snd_kcontrol_new cs4271_snd_controls[] = {
443 SOC_DOUBLE_R_TLV("Master Playback Volume", CS4271_VOLA, CS4271_VOLB,
444 0, 0x7F, 1, cs4271_dac_tlv),
445 SOC_SINGLE("Digital Loopback Switch", CS4271_MODE2, 4, 1, 0),
446 SOC_SINGLE("Soft Ramp Switch", CS4271_DACVOL, 5, 1, 0),
447 SOC_SINGLE("Zero Cross Switch", CS4271_DACVOL, 4, 1, 0),
448 SOC_SINGLE_BOOL_EXT("De-emphasis Switch", 0,
449 cs4271_get_deemph, cs4271_put_deemph),
450 SOC_SINGLE("Auto-Mute Switch", CS4271_DACCTL, 7, 1, 0),
451 SOC_SINGLE("Slow Roll Off Filter Switch", CS4271_DACCTL, 6, 1, 0),
452 SOC_SINGLE("Soft Volume Ramp-Up Switch", CS4271_DACCTL, 3, 1, 0),
453 SOC_SINGLE("Soft Ramp-Down Switch", CS4271_DACCTL, 2, 1, 0),
454 SOC_SINGLE("Left Channel Inversion Switch", CS4271_DACCTL, 1, 1, 0),
455 SOC_SINGLE("Right Channel Inversion Switch", CS4271_DACCTL, 0, 1, 0),
456 SOC_DOUBLE("Master Capture Switch", CS4271_ADCCTL, 3, 2, 1, 1),
457 SOC_SINGLE("Dither 16-Bit Data Switch", CS4271_ADCCTL, 5, 1, 0),
458 SOC_DOUBLE("High Pass Filter Switch", CS4271_ADCCTL, 1, 0, 1, 1),
459 SOC_DOUBLE_R("Master Playback Switch", CS4271_VOLA, CS4271_VOLB,
460 7, 1, 1),
461};
462
85e7652d 463static const struct snd_soc_dai_ops cs4271_dai_ops = {
67b22517
AS		 464 .hw_params = cs4271_hw_params,
465 .set_sysclk = cs4271_set_dai_sysclk,
466 .set_fmt = cs4271_set_dai_fmt,
c24a34db 467 .mute_stream = cs4271_mute_stream,
67b22517
AS		 468};
469
16af7d60 470static struct snd_soc_dai_driver cs4271_dai = {
67b22517
AS		 471 .name = "cs4271-hifi",
472 .playback = {
473 .stream_name = "Playback",
474 .channels_min = 2,
475 .channels_max = 2,
383f8465 476 .rates = CS4271_PCM_RATES,
67b22517
AS		 477 .formats = CS4271_PCM_FORMATS,
478 },
479 .capture = {
480 .stream_name = "Capture",
481 .channels_min = 2,
482 .channels_max = 2,
383f8465 483 .rates = CS4271_PCM_RATES,
67b22517
AS		 484 .formats = CS4271_PCM_FORMATS,
485 },
486 .ops = &cs4271_dai_ops,
487 .symmetric_rates = 1,
488};
489
490#ifdef CONFIG_PM
84b315ee 491static int cs4271_soc_suspend(struct snd_soc_codec *codec)
67b22517 492{
0d42e6e7 493 int ret;
1b1861ea
DM		 494 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
495
67b22517 496 /* Set power-down bit */
1b1861ea
DM		 497 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
498 CS4271_MODE2_PDN, CS4271_MODE2_PDN);
0d42e6e7
AS		 499 if (ret < 0)
500 return ret;
1b1861ea 501
67b22517
AS		 502 return 0;
503}
504
505static int cs4271_soc_resume(struct snd_soc_codec *codec)
506{
0d42e6e7 507 int ret;
1b1861ea
DM		 508 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
509
67b22517 510 /* Restore codec state */
1b1861ea 511 ret = regcache_sync(cs4271->regmap);
0d42e6e7
AS		 512 if (ret < 0)
513 return ret;
1b1861ea 514
67b22517 515 /* then disable the power-down bit */
1b1861ea
DM		 516 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
517 CS4271_MODE2_PDN, 0);
0d42e6e7
AS		 518 if (ret < 0)
519 return ret;
1b1861ea 520
67b22517
AS		 521 return 0;
522}
523#else
524#define cs4271_soc_suspend NULL
525#define cs4271_soc_resume NULL
526#endif /* CONFIG_PM */
527
a31ebc34 528#ifdef CONFIG_OF
c973b8a7 529const struct of_device_id cs4271_dt_ids[] = {
a31ebc34
DM		 530 { .compatible = "cirrus,cs4271", },
531 { }
532};
533MODULE_DEVICE_TABLE(of, cs4271_dt_ids);
c973b8a7 534EXPORT_SYMBOL_GPL(cs4271_dt_ids);
a31ebc34
DM		 535#endif
536
c973b8a7 537static int cs4271_codec_probe(struct snd_soc_codec *codec)
67b22517
AS		 538{
539 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
540 struct cs4271_platform_data *cs4271plat = codec->dev->platform_data;
541 int ret;
26047e2d 542 bool amutec_eq_bmutec = false;
67b22517 543
a31ebc34 544#ifdef CONFIG_OF
293750f9 545 if (of_match_device(cs4271_dt_ids, codec->dev)) {
b8455c9f 546 if (of_get_property(codec->dev->of_node,
293750f9 547 "cirrus,amutec-eq-bmutec", NULL))
26047e2d 548 amutec_eq_bmutec = true;
fd23fb9f
DM		 549
550 if (of_get_property(codec->dev->of_node,
551 "cirrus,enable-soft-reset", NULL))
552 cs4271->enable_soft_reset = true;
293750f9 553 }
a31ebc34
DM		 554#endif
555
293750f9 556 if (cs4271plat) {
293750f9 557 amutec_eq_bmutec = cs4271plat->amutec_eq_bmutec;
fd23fb9f 558 cs4271->enable_soft_reset = cs4271plat->enable_soft_reset;
293750f9 559 }
67b22517 560
d6cf89ee 561 if (gpio_is_valid(cs4271->gpio_nreset)) {
67b22517 562 /* Reset codec */
d6cf89ee 563 gpio_direction_output(cs4271->gpio_nreset, 0);
74ff9602 564 mdelay(1);
d6cf89ee 565 gpio_set_value(cs4271->gpio_nreset, 1);
67b22517 566 /* Give the codec time to wake up */
74ff9602 567 mdelay(1);
67b22517
AS		 568 }
569
1b1861ea
DM		 570 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
571 CS4271_MODE2_PDN | CS4271_MODE2_CPEN,
572 CS4271_MODE2_PDN | CS4271_MODE2_CPEN);
0d42e6e7
AS		 573 if (ret < 0)
574 return ret;
1b1861ea
DM		 575 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2,
576 CS4271_MODE2_PDN, 0);
0d42e6e7
AS		 577 if (ret < 0)
578 return ret;
67b22517
AS		 579 /* Power-up sequence requires 85 uS */
580 udelay(85);
581
293750f9 582 if (amutec_eq_bmutec)
1b1861ea
DM		 583 regmap_update_bits(cs4271->regmap, CS4271_MODE2,
584 CS4271_MODE2_MUTECAEQUB,
585 CS4271_MODE2_MUTECAEQUB);
293750f9 586
bad268f3 587 return 0;
67b22517
AS		 588}
589
c973b8a7 590static int cs4271_codec_remove(struct snd_soc_codec *codec)
67b22517
AS		 591{
592 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
67b22517 593
5574f774 594 if (gpio_is_valid(cs4271->gpio_nreset))
67b22517 595 /* Set codec to the reset state */
5574f774 596 gpio_set_value(cs4271->gpio_nreset, 0);
67b22517 597
67b22517
AS		 598 return 0;
599};
600
16af7d60 601static struct snd_soc_codec_driver soc_codec_dev_cs4271 = {
c973b8a7
AL		 602 .probe = cs4271_codec_probe,
603 .remove = cs4271_codec_remove,
67b22517
AS		 604 .suspend = cs4271_soc_suspend,
605 .resume = cs4271_soc_resume,
bad268f3
MB		 606
607 .controls = cs4271_snd_controls,
608 .num_controls = ARRAY_SIZE(cs4271_snd_controls),
2e7fb942
MB		 609 .dapm_widgets = cs4271_dapm_widgets,
610 .num_dapm_widgets = ARRAY_SIZE(cs4271_dapm_widgets),
611 .dapm_routes = cs4271_dapm_routes,
612 .num_dapm_routes = ARRAY_SIZE(cs4271_dapm_routes),
67b22517
AS		 613};
614
d6cf89ee
DM		 615static int cs4271_common_probe(struct device *dev,
616 struct cs4271_private **c)
67b22517 617{
d6cf89ee 618 struct cs4271_platform_data *cs4271plat = dev->platform_data;
67b22517
AS		 619 struct cs4271_private *cs4271;
620
d6cf89ee 621 cs4271 = devm_kzalloc(dev, sizeof(*cs4271), GFP_KERNEL);
67b22517
AS		 622 if (!cs4271)
623 return -ENOMEM;
624
d6cf89ee
DM		 625 if (of_match_device(cs4271_dt_ids, dev))
626 cs4271->gpio_nreset =
627 of_get_named_gpio(dev->of_node, "reset-gpio", 0);
628
629 if (cs4271plat)
630 cs4271->gpio_nreset = cs4271plat->gpio_nreset;
631
632 if (gpio_is_valid(cs4271->gpio_nreset)) {
633 int ret;
634
635 ret = devm_gpio_request(dev, cs4271->gpio_nreset,
636 "CS4271 Reset");
637 if (ret < 0)
638 return ret;
639 }
640
641 *c = cs4271;
642 return 0;
643}
644
c973b8a7 645const struct regmap_config cs4271_regmap_config = {
9c369c6e 646 .max_register = CS4271_LASTREG,
9c369c6e
TI		 647
648 .reg_defaults = cs4271_reg_defaults,
649 .num_reg_defaults = ARRAY_SIZE(cs4271_reg_defaults),
650 .cache_type = REGCACHE_RBTREE,
651
652 .volatile_reg = cs4271_volatile_reg,
653};
c973b8a7 654EXPORT_SYMBOL_GPL(cs4271_regmap_config);
9c369c6e 655
c973b8a7 656int cs4271_probe(struct device *dev, struct regmap *regmap)
d6cf89ee
DM		 657{
658 struct cs4271_private *cs4271;
659 int ret;
660
c973b8a7
AL		 661 if (IS_ERR(regmap))
662 return PTR_ERR(regmap);
67b22517 663
c973b8a7 664 ret = cs4271_common_probe(dev, &cs4271);
d6cf89ee
DM		 665 if (ret < 0)
666 return ret;
67b22517 667
c973b8a7
AL		 668 dev_set_drvdata(dev, cs4271);
669 cs4271->regmap = regmap;
67b22517 670
c973b8a7
AL		 671 return snd_soc_register_codec(dev, &soc_codec_dev_cs4271, &cs4271_dai,
672 1);
67b22517 673}
c973b8a7 674EXPORT_SYMBOL_GPL(cs4271_probe);
67b22517
AS		 675
676MODULE_AUTHOR("Alexander Sverdlin <subaparts@yandex.ru>");
677MODULE_DESCRIPTION("Cirrus Logic CS4271 ALSA SoC Codec Driver");
678MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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