[deliverable/linux.git] / sound / soc / codecs / cs4271.c

/*
 * CS4271 ASoC codec driver
 *
 * Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * This driver support CS4271 codec being master or slave, working
 * in control port mode, connected either via SPI or I2C.
 * The data format accepted is I2S or left-justified.
 * DAPM support not implemented.
 */

#include <linux/module.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/spi/spi.h>
#include <sound/cs4271.h>

#define CS4271_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
			    SNDRV_PCM_FMTBIT_S24_LE | \
			    SNDRV_PCM_FMTBIT_S32_LE)
#define CS4271_PCM_RATES SNDRV_PCM_RATE_8000_192000

/*
 * CS4271 registers
 * High byte represents SPI chip address (0x10) + write command (0)
 * Low byte - codec register address
 */
#define CS4271_MODE1	0x2001	/* Mode Control 1 */
#define CS4271_DACCTL	0x2002	/* DAC Control */
#define CS4271_DACVOL	0x2003	/* DAC Volume & Mixing Control */
#define CS4271_VOLA	0x2004	/* DAC Channel A Volume Control */
#define CS4271_VOLB	0x2005	/* DAC Channel B Volume Control */
#define CS4271_ADCCTL	0x2006	/* ADC Control */
#define CS4271_MODE2	0x2007	/* Mode Control 2 */
#define CS4271_CHIPID	0x2008	/* Chip ID */

#define CS4271_FIRSTREG	CS4271_MODE1
#define CS4271_LASTREG	CS4271_MODE2
#define CS4271_NR_REGS	((CS4271_LASTREG & 0xFF) + 1)

/* Bit masks for the CS4271 registers */
#define CS4271_MODE1_MODE_MASK	0xC0
#define CS4271_MODE1_MODE_1X	0x00
#define CS4271_MODE1_MODE_2X	0x80
#define CS4271_MODE1_MODE_4X	0xC0

#define CS4271_MODE1_DIV_MASK	0x30
#define CS4271_MODE1_DIV_1	0x00
#define CS4271_MODE1_DIV_15	0x10
#define CS4271_MODE1_DIV_2	0x20
#define CS4271_MODE1_DIV_3	0x30

#define CS4271_MODE1_MASTER	0x08

#define CS4271_MODE1_DAC_DIF_MASK	0x07
#define CS4271_MODE1_DAC_DIF_LJ		0x00
#define CS4271_MODE1_DAC_DIF_I2S	0x01
#define CS4271_MODE1_DAC_DIF_RJ16	0x02
#define CS4271_MODE1_DAC_DIF_RJ24	0x03
#define CS4271_MODE1_DAC_DIF_RJ20	0x04
#define CS4271_MODE1_DAC_DIF_RJ18	0x05

#define CS4271_DACCTL_AMUTE	0x80
#define CS4271_DACCTL_IF_SLOW	0x40

#define CS4271_DACCTL_DEM_MASK	0x30
#define CS4271_DACCTL_DEM_DIS	0x00
#define CS4271_DACCTL_DEM_441	0x10
#define CS4271_DACCTL_DEM_48	0x20
#define CS4271_DACCTL_DEM_32	0x30

#define CS4271_DACCTL_SVRU	0x08
#define CS4271_DACCTL_SRD	0x04
#define CS4271_DACCTL_INVA	0x02
#define CS4271_DACCTL_INVB	0x01

#define CS4271_DACVOL_BEQUA	0x40
#define CS4271_DACVOL_SOFT	0x20
#define CS4271_DACVOL_ZEROC	0x10

#define CS4271_DACVOL_ATAPI_MASK	0x0F
#define CS4271_DACVOL_ATAPI_M_M		0x00
#define CS4271_DACVOL_ATAPI_M_BR	0x01
#define CS4271_DACVOL_ATAPI_M_BL	0x02
#define CS4271_DACVOL_ATAPI_M_BLR2	0x03
#define CS4271_DACVOL_ATAPI_AR_M	0x04
#define CS4271_DACVOL_ATAPI_AR_BR	0x05
#define CS4271_DACVOL_ATAPI_AR_BL	0x06
#define CS4271_DACVOL_ATAPI_AR_BLR2	0x07
#define CS4271_DACVOL_ATAPI_AL_M	0x08
#define CS4271_DACVOL_ATAPI_AL_BR	0x09
#define CS4271_DACVOL_ATAPI_AL_BL	0x0A
#define CS4271_DACVOL_ATAPI_AL_BLR2	0x0B
#define CS4271_DACVOL_ATAPI_ALR2_M	0x0C
#define CS4271_DACVOL_ATAPI_ALR2_BR	0x0D
#define CS4271_DACVOL_ATAPI_ALR2_BL	0x0E
#define CS4271_DACVOL_ATAPI_ALR2_BLR2	0x0F

#define CS4271_VOLA_MUTE	0x80
#define CS4271_VOLA_VOL_MASK	0x7F
#define CS4271_VOLB_MUTE	0x80
#define CS4271_VOLB_VOL_MASK	0x7F

#define CS4271_ADCCTL_DITHER16	0x20

#define CS4271_ADCCTL_ADC_DIF_MASK	0x10
#define CS4271_ADCCTL_ADC_DIF_LJ	0x00
#define CS4271_ADCCTL_ADC_DIF_I2S	0x10

#define CS4271_ADCCTL_MUTEA	0x08
#define CS4271_ADCCTL_MUTEB	0x04
#define CS4271_ADCCTL_HPFDA	0x02
#define CS4271_ADCCTL_HPFDB	0x01

#define CS4271_MODE2_LOOP	0x10
#define CS4271_MODE2_MUTECAEQUB	0x08
#define CS4271_MODE2_FREEZE	0x04
#define CS4271_MODE2_CPEN	0x02
#define CS4271_MODE2_PDN	0x01

#define CS4271_CHIPID_PART_MASK	0xF0
#define CS4271_CHIPID_REV_MASK	0x0F

/*
 * Default CS4271 power-up configuration
 * Array contains non-existing in hw register at address 0
 * Array do not include Chip ID, as codec driver does not use
 * registers read operations at all
 */
static const u8 cs4271_dflt_reg[CS4271_NR_REGS] = {
	0,
	0,
	CS4271_DACCTL_AMUTE,
	CS4271_DACVOL_SOFT | CS4271_DACVOL_ATAPI_AL_BR,
	0,
	0,
	0,
	0,
};

struct cs4271_private {
	/* SND_SOC_I2C or SND_SOC_SPI */
	enum snd_soc_control_type	bus_type;
	void				*control_data;
	unsigned int			mclk;
	bool				master;
	bool				deemph;
	/* Current sample rate for de-emphasis control */
	int				rate;
	/* GPIO driving Reset pin, if any */
	int				gpio_nreset;
	/* GPIO that disable serial bus, if any */
	int				gpio_disable;
};

struct cs4271_clk_cfg {
	unsigned int	ratio;		/* MCLK / sample rate */
	u8		speed_mode;	/* codec speed mode: 1x, 2x, 4x */
	u8		mclk_master;	/* ratio bit mask for Master mode */
	u8		mclk_slave;	/* ratio bit mask for Slave mode */
};

static struct cs4271_clk_cfg cs4271_clk_tab[] = {
	{64,   CS4271_MODE1_MODE_4X, CS4271_MODE1_DIV_1,  CS4271_MODE1_DIV_1},
	{96,   CS4271_MODE1_MODE_4X, CS4271_MODE1_DIV_15, CS4271_MODE1_DIV_1},
	{128,  CS4271_MODE1_MODE_2X, CS4271_MODE1_DIV_1,  CS4271_MODE1_DIV_1},
	{192,  CS4271_MODE1_MODE_2X, CS4271_MODE1_DIV_15, CS4271_MODE1_DIV_1},
	{256,  CS4271_MODE1_MODE_1X, CS4271_MODE1_DIV_1,  CS4271_MODE1_DIV_1},
	{384,  CS4271_MODE1_MODE_1X, CS4271_MODE1_DIV_15, CS4271_MODE1_DIV_1},
	{512,  CS4271_MODE1_MODE_1X, CS4271_MODE1_DIV_2,  CS4271_MODE1_DIV_1},
	{768,  CS4271_MODE1_MODE_1X, CS4271_MODE1_DIV_3,  CS4271_MODE1_DIV_3},
	{1024, CS4271_MODE1_MODE_1X, CS4271_MODE1_DIV_3,  CS4271_MODE1_DIV_3}
};

#define CS4171_NR_RATIOS ARRAY_SIZE(cs4271_clk_tab)

/*
 * @freq is the desired MCLK rate
 * MCLK rate should (c) be the sample rate, multiplied by one of the
 * ratios listed in cs4271_mclk_fs_ratios table
 */
static int cs4271_set_dai_sysclk(struct snd_soc_dai *codec_dai,
				 int clk_id, unsigned int freq, int dir)
{
	struct snd_soc_codec *codec = codec_dai->codec;
	struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);

	cs4271->mclk = freq;
	return 0;
}

static int cs4271_set_dai_fmt(struct snd_soc_dai *codec_dai,
			      unsigned int format)
{
	struct snd_soc_codec *codec = codec_dai->codec;
	struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
	unsigned int val = 0;
	int ret;

	switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		cs4271->master = 0;
		break;
	case SND_SOC_DAIFMT_CBM_CFM:
		cs4271->master = 1;
		val |= CS4271_MODE1_MASTER;
		break;
	default:
		dev_err(codec->dev, "Invalid DAI format\n");
		return -EINVAL;
	}

	switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_LEFT_J:
		val |= CS4271_MODE1_DAC_DIF_LJ;
		ret = snd_soc_update_bits(codec, CS4271_ADCCTL,
			CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_LJ);
		if (ret < 0)
			return ret;
		break;
	case SND_SOC_DAIFMT_I2S:
		val |= CS4271_MODE1_DAC_DIF_I2S;
		ret = snd_soc_update_bits(codec, CS4271_ADCCTL,
			CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_I2S);
		if (ret < 0)
			return ret;
		break;
	default:
		dev_err(codec->dev, "Invalid DAI format\n");
		return -EINVAL;
	}

	ret = snd_soc_update_bits(codec, CS4271_MODE1,
		CS4271_MODE1_DAC_DIF_MASK | CS4271_MODE1_MASTER, val);
	if (ret < 0)
		return ret;
	return 0;
}

static int cs4271_deemph[] = {0, 44100, 48000, 32000};

static int cs4271_set_deemph(struct snd_soc_codec *codec)
{
	struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
	int i, ret;
	int val = CS4271_DACCTL_DEM_DIS;

	if (cs4271->deemph) {
		/* Find closest de-emphasis freq */
		val = 1;
		for (i = 2; i < ARRAY_SIZE(cs4271_deemph); i++)
			if (abs(cs4271_deemph[i] - cs4271->rate) <
			    abs(cs4271_deemph[val] - cs4271->rate))
				val = i;
		val <<= 4;
	}

	ret = snd_soc_update_bits(codec, CS4271_DACCTL,
		CS4271_DACCTL_DEM_MASK, val);
	if (ret < 0)
		return ret;
	return 0;
}

static int cs4271_get_deemph(struct snd_kcontrol *kcontrol,
			     struct snd_ctl_elem_value *ucontrol)
{
	struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
	struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);

	ucontrol->value.enumerated.item[0] = cs4271->deemph;
	return 0;
}

static int cs4271_put_deemph(struct snd_kcontrol *kcontrol,
			     struct snd_ctl_elem_value *ucontrol)
{
	struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
	struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);

	cs4271->deemph = ucontrol->value.enumerated.item[0];
	return cs4271_set_deemph(codec);
}

static int cs4271_hw_params(struct snd_pcm_substream *substream,
			    struct snd_pcm_hw_params *params,
			    struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_codec *codec = rtd->codec;
	struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
	int i, ret;
	unsigned int ratio, val;

	cs4271->rate = params_rate(params);
	ratio = cs4271->mclk / cs4271->rate;
	for (i = 0; i < CS4171_NR_RATIOS; i++)
		if (cs4271_clk_tab[i].ratio == ratio)
			break;

	if ((i == CS4171_NR_RATIOS) || ((ratio == 1024) && cs4271->master)) {
		dev_err(codec->dev, "Invalid sample rate\n");
		return -EINVAL;
	}

	/* Configure DAC */
	val = cs4271_clk_tab[i].speed_mode;

	if (cs4271->master)
		val |= cs4271_clk_tab[i].mclk_master;
	else
		val |= cs4271_clk_tab[i].mclk_slave;

	ret = snd_soc_update_bits(codec, CS4271_MODE1,
		CS4271_MODE1_MODE_MASK | CS4271_MODE1_DIV_MASK, val);
	if (ret < 0)
		return ret;

	return cs4271_set_deemph(codec);
}

static int cs4271_digital_mute(struct snd_soc_dai *dai, int mute)
{
	struct snd_soc_codec *codec = dai->codec;
	int ret;
	int val_a = 0;
	int val_b = 0;

	if (mute) {
		val_a = CS4271_VOLA_MUTE;
		val_b = CS4271_VOLB_MUTE;
	}

	ret = snd_soc_update_bits(codec, CS4271_VOLA, CS4271_VOLA_MUTE, val_a);
	if (ret < 0)
		return ret;
	ret = snd_soc_update_bits(codec, CS4271_VOLB, CS4271_VOLB_MUTE, val_b);
	if (ret < 0)
		return ret;

	return 0;
}

/* CS4271 controls */
static DECLARE_TLV_DB_SCALE(cs4271_dac_tlv, -12700, 100, 0);

static const struct snd_kcontrol_new cs4271_snd_controls[] = {
	SOC_DOUBLE_R_TLV("Master Playback Volume", CS4271_VOLA, CS4271_VOLB,
		0, 0x7F, 1, cs4271_dac_tlv),
	SOC_SINGLE("Digital Loopback Switch", CS4271_MODE2, 4, 1, 0),
	SOC_SINGLE("Soft Ramp Switch", CS4271_DACVOL, 5, 1, 0),
	SOC_SINGLE("Zero Cross Switch", CS4271_DACVOL, 4, 1, 0),
	SOC_SINGLE_BOOL_EXT("De-emphasis Switch", 0,
		cs4271_get_deemph, cs4271_put_deemph),
	SOC_SINGLE("Auto-Mute Switch", CS4271_DACCTL, 7, 1, 0),
	SOC_SINGLE("Slow Roll Off Filter Switch", CS4271_DACCTL, 6, 1, 0),
	SOC_SINGLE("Soft Volume Ramp-Up Switch", CS4271_DACCTL, 3, 1, 0),
	SOC_SINGLE("Soft Ramp-Down Switch", CS4271_DACCTL, 2, 1, 0),
	SOC_SINGLE("Left Channel Inversion Switch", CS4271_DACCTL, 1, 1, 0),
	SOC_SINGLE("Right Channel Inversion Switch", CS4271_DACCTL, 0, 1, 0),
	SOC_DOUBLE("Master Capture Switch", CS4271_ADCCTL, 3, 2, 1, 1),
	SOC_SINGLE("Dither 16-Bit Data Switch", CS4271_ADCCTL, 5, 1, 0),
	SOC_DOUBLE("High Pass Filter Switch", CS4271_ADCCTL, 1, 0, 1, 1),
	SOC_DOUBLE_R("Master Playback Switch", CS4271_VOLA, CS4271_VOLB,
		7, 1, 1),
};

static struct snd_soc_dai_ops cs4271_dai_ops = {
	.hw_params	= cs4271_hw_params,
	.set_sysclk	= cs4271_set_dai_sysclk,
	.set_fmt	= cs4271_set_dai_fmt,
	.digital_mute	= cs4271_digital_mute,
};

static struct snd_soc_dai_driver cs4271_dai = {
	.name = "cs4271-hifi",
	.playback = {
		.stream_name	= "Playback",
		.channels_min	= 2,
		.channels_max	= 2,
		.rates		= CS4271_PCM_RATES,
		.formats	= CS4271_PCM_FORMATS,
	},
	.capture = {
		.stream_name	= "Capture",
		.channels_min	= 2,
		.channels_max	= 2,
		.rates		= CS4271_PCM_RATES,
		.formats	= CS4271_PCM_FORMATS,
	},
	.ops = &cs4271_dai_ops,
	.symmetric_rates = 1,
};

#ifdef CONFIG_PM
static int cs4271_soc_suspend(struct snd_soc_codec *codec, pm_message_t mesg)
{
	int ret;
	/* Set power-down bit */
	ret = snd_soc_update_bits(codec, CS4271_MODE2, 0, CS4271_MODE2_PDN);
	if (ret < 0)
		return ret;
	return 0;
}

static int cs4271_soc_resume(struct snd_soc_codec *codec)
{
	int ret;
	/* Restore codec state */
	ret = snd_soc_cache_sync(codec);
	if (ret < 0)
		return ret;
	/* then disable the power-down bit */
	ret = snd_soc_update_bits(codec, CS4271_MODE2, CS4271_MODE2_PDN, 0);
	if (ret < 0)
		return ret;
	return 0;
}
#else
#define cs4271_soc_suspend	NULL
#define cs4271_soc_resume	NULL
#endif /* CONFIG_PM */

static int cs4271_probe(struct snd_soc_codec *codec)
{
	struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
	struct cs4271_platform_data *cs4271plat = codec->dev->platform_data;
	int ret;
	int gpio_nreset = -EINVAL;

	codec->control_data = cs4271->control_data;

	if (cs4271plat && gpio_is_valid(cs4271plat->gpio_nreset))
		gpio_nreset = cs4271plat->gpio_nreset;

	if (gpio_nreset >= 0)
		if (gpio_request(gpio_nreset, "CS4271 Reset"))
			gpio_nreset = -EINVAL;
	if (gpio_nreset >= 0) {
		/* Reset codec */
		gpio_direction_output(gpio_nreset, 0);
		udelay(1);
		gpio_set_value(gpio_nreset, 1);
		/* Give the codec time to wake up */
		udelay(1);
	}

	cs4271->gpio_nreset = gpio_nreset;

	/*
	 * In case of I2C, chip address specified in board data.
	 * So cache IO operations use 8 bit codec register address.
	 * In case of SPI, chip address and register address
	 * passed together as 16 bit value.
	 * Anyway, register address is masked with 0xFF inside
	 * soc-cache code.
	 */
	if (cs4271->bus_type == SND_SOC_SPI)
		ret = snd_soc_codec_set_cache_io(codec, 16, 8,
			cs4271->bus_type);
	else
		ret = snd_soc_codec_set_cache_io(codec, 8, 8,
			cs4271->bus_type);
	if (ret) {
		dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
		return ret;
	}

	ret = snd_soc_update_bits(codec, CS4271_MODE2, 0,
		CS4271_MODE2_PDN | CS4271_MODE2_CPEN);
	if (ret < 0)
		return ret;
	ret = snd_soc_update_bits(codec, CS4271_MODE2, CS4271_MODE2_PDN, 0);
	if (ret < 0)
		return ret;
	/* Power-up sequence requires 85 uS */
	udelay(85);

	return snd_soc_add_controls(codec, cs4271_snd_controls,
		ARRAY_SIZE(cs4271_snd_controls));
}

static int cs4271_remove(struct snd_soc_codec *codec)
{
	struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
	int gpio_nreset;

	gpio_nreset = cs4271->gpio_nreset;

	if (gpio_is_valid(gpio_nreset)) {
		/* Set codec to the reset state */
		gpio_set_value(gpio_nreset, 0);
		gpio_free(gpio_nreset);
	}

	return 0;
};

static struct snd_soc_codec_driver soc_codec_dev_cs4271 = {
	.probe			= cs4271_probe,
	.remove			= cs4271_remove,
	.suspend		= cs4271_soc_suspend,
	.resume			= cs4271_soc_resume,
	.reg_cache_default	= cs4271_dflt_reg,
	.reg_cache_size		= ARRAY_SIZE(cs4271_dflt_reg),
	.reg_word_size		= sizeof(cs4271_dflt_reg[0]),
	.compress_type		= SND_SOC_FLAT_COMPRESSION,
};

#if defined(CONFIG_SPI_MASTER)
static int __devinit cs4271_spi_probe(struct spi_device *spi)
{
	struct cs4271_private *cs4271;

	cs4271 = devm_kzalloc(&spi->dev, sizeof(*cs4271), GFP_KERNEL);
	if (!cs4271)
		return -ENOMEM;

	spi_set_drvdata(spi, cs4271);
	cs4271->control_data = spi;
	cs4271->bus_type = SND_SOC_SPI;

	return snd_soc_register_codec(&spi->dev, &soc_codec_dev_cs4271,
		&cs4271_dai, 1);
}

static int __devexit cs4271_spi_remove(struct spi_device *spi)
{
	snd_soc_unregister_codec(&spi->dev);
	return 0;
}

static struct spi_driver cs4271_spi_driver = {
	.driver = {
		.name	= "cs4271",
		.owner	= THIS_MODULE,
	},
	.probe		= cs4271_spi_probe,
	.remove		= __devexit_p(cs4271_spi_remove),
};
#endif /* defined(CONFIG_SPI_MASTER) */

#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
static const struct i2c_device_id cs4271_i2c_id[] = {
	{"cs4271", 0},
	{}
};
MODULE_DEVICE_TABLE(i2c, cs4271_i2c_id);

static int __devinit cs4271_i2c_probe(struct i2c_client *client,
				      const struct i2c_device_id *id)
{
	struct cs4271_private *cs4271;

	cs4271 = devm_kzalloc(&client->dev, sizeof(*cs4271), GFP_KERNEL);
	if (!cs4271)
		return -ENOMEM;

	i2c_set_clientdata(client, cs4271);
	cs4271->control_data = client;
	cs4271->bus_type = SND_SOC_I2C;

	return snd_soc_register_codec(&client->dev, &soc_codec_dev_cs4271,
		&cs4271_dai, 1);
}

static int __devexit cs4271_i2c_remove(struct i2c_client *client)
{
	snd_soc_unregister_codec(&client->dev);
	return 0;
}

static struct i2c_driver cs4271_i2c_driver = {
	.driver = {
		.name	= "cs4271",
		.owner	= THIS_MODULE,
	},
	.id_table	= cs4271_i2c_id,
	.probe		= cs4271_i2c_probe,
	.remove		= __devexit_p(cs4271_i2c_remove),
};
#endif /* defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) */

/*
 * We only register our serial bus driver here without
 * assignment to particular chip. So if any of the below
 * fails, there is some problem with I2C or SPI subsystem.
 * In most cases this module will be compiled with support
 * of only one serial bus.
 */
static int __init cs4271_modinit(void)
{
	int ret;

#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
	ret = i2c_add_driver(&cs4271_i2c_driver);
	if (ret) {
		pr_err("Failed to register CS4271 I2C driver: %d\n", ret);
		return ret;
	}
#endif

#if defined(CONFIG_SPI_MASTER)
	ret = spi_register_driver(&cs4271_spi_driver);
	if (ret) {
		pr_err("Failed to register CS4271 SPI driver: %d\n", ret);
		return ret;
	}
#endif

	return 0;
}
module_init(cs4271_modinit);

static void __exit cs4271_modexit(void)
{
#if defined(CONFIG_SPI_MASTER)
	spi_unregister_driver(&cs4271_spi_driver);
#endif

#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
	i2c_del_driver(&cs4271_i2c_driver);
#endif
}
module_exit(cs4271_modexit);

MODULE_AUTHOR("Alexander Sverdlin <subaparts@yandex.ru>");
MODULE_DESCRIPTION("Cirrus Logic CS4271 ALSA SoC Codec Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
67b22517 AS	1	/*
	2	* CS4271 ASoC codec driver
	3	*
	4	* Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru>
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* This driver support CS4271 codec being master or slave, working
	17	* in control port mode, connected either via SPI or I2C.
	18	* The data format accepted is I2S or left-justified.
	19	* DAPM support not implemented.
	20	*/
	21
	22	#include <linux/module.h>
	23	#include <linux/slab.h>
	24	#include <linux/delay.h>
	25	#include <sound/pcm.h>
	26	#include <sound/soc.h>
	27	#include <sound/tlv.h>
	28	#include <linux/gpio.h>
	29	#include <linux/i2c.h>
	30	#include <linux/spi/spi.h>
	31	#include <sound/cs4271.h>
	32
	33	#define CS4271_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE \| \
	34	SNDRV_PCM_FMTBIT_S24_LE \| \
	35	SNDRV_PCM_FMTBIT_S32_LE)
383f8465	36	#define CS4271_PCM_RATES SNDRV_PCM_RATE_8000_192000
67b22517 AS	37
	38	/*
	39	* CS4271 registers
	40	* High byte represents SPI chip address (0x10) + write command (0)
	41	* Low byte - codec register address
	42	*/
	43	#define CS4271_MODE1 0x2001 /* Mode Control 1 */
	44	#define CS4271_DACCTL 0x2002 /* DAC Control */
	45	#define CS4271_DACVOL 0x2003 /* DAC Volume & Mixing Control */
	46	#define CS4271_VOLA 0x2004 /* DAC Channel A Volume Control */
	47	#define CS4271_VOLB 0x2005 /* DAC Channel B Volume Control */
	48	#define CS4271_ADCCTL 0x2006 /* ADC Control */
	49	#define CS4271_MODE2 0x2007 /* Mode Control 2 */
	50	#define CS4271_CHIPID 0x2008 /* Chip ID */
	51
	52	#define CS4271_FIRSTREG CS4271_MODE1
	53	#define CS4271_LASTREG CS4271_MODE2
	54	#define CS4271_NR_REGS ((CS4271_LASTREG & 0xFF) + 1)
	55
	56	/* Bit masks for the CS4271 registers */
	57	#define CS4271_MODE1_MODE_MASK 0xC0
	58	#define CS4271_MODE1_MODE_1X 0x00
	59	#define CS4271_MODE1_MODE_2X 0x80
	60	#define CS4271_MODE1_MODE_4X 0xC0
	61
	62	#define CS4271_MODE1_DIV_MASK 0x30
	63	#define CS4271_MODE1_DIV_1 0x00
	64	#define CS4271_MODE1_DIV_15 0x10
	65	#define CS4271_MODE1_DIV_2 0x20
	66	#define CS4271_MODE1_DIV_3 0x30
	67
	68	#define CS4271_MODE1_MASTER 0x08
	69
	70	#define CS4271_MODE1_DAC_DIF_MASK 0x07
	71	#define CS4271_MODE1_DAC_DIF_LJ 0x00
	72	#define CS4271_MODE1_DAC_DIF_I2S 0x01
	73	#define CS4271_MODE1_DAC_DIF_RJ16 0x02
	74	#define CS4271_MODE1_DAC_DIF_RJ24 0x03
	75	#define CS4271_MODE1_DAC_DIF_RJ20 0x04
	76	#define CS4271_MODE1_DAC_DIF_RJ18 0x05
	77
	78	#define CS4271_DACCTL_AMUTE 0x80
	79	#define CS4271_DACCTL_IF_SLOW 0x40
	80
	81	#define CS4271_DACCTL_DEM_MASK 0x30
	82	#define CS4271_DACCTL_DEM_DIS 0x00
	83	#define CS4271_DACCTL_DEM_441 0x10
	84	#define CS4271_DACCTL_DEM_48 0x20
	85	#define CS4271_DACCTL_DEM_32 0x30
	86
	87	#define CS4271_DACCTL_SVRU 0x08
	88	#define CS4271_DACCTL_SRD 0x04
	89	#define CS4271_DACCTL_INVA 0x02
	90	#define CS4271_DACCTL_INVB 0x01
	91
	92	#define CS4271_DACVOL_BEQUA 0x40
	93	#define CS4271_DACVOL_SOFT 0x20
	94	#define CS4271_DACVOL_ZEROC 0x10
	95
	96	#define CS4271_DACVOL_ATAPI_MASK 0x0F
	97	#define CS4271_DACVOL_ATAPI_M_M 0x00
	98	#define CS4271_DACVOL_ATAPI_M_BR 0x01
	99	#define CS4271_DACVOL_ATAPI_M_BL 0x02
	100	#define CS4271_DACVOL_ATAPI_M_BLR2 0x03
101	#define CS4271_DACVOL_ATAPI_AR_M 0x04
102	#define CS4271_DACVOL_ATAPI_AR_BR 0x05
103	#define CS4271_DACVOL_ATAPI_AR_BL 0x06
104	#define CS4271_DACVOL_ATAPI_AR_BLR2 0x07
105	#define CS4271_DACVOL_ATAPI_AL_M 0x08
106	#define CS4271_DACVOL_ATAPI_AL_BR 0x09
107	#define CS4271_DACVOL_ATAPI_AL_BL 0x0A
108	#define CS4271_DACVOL_ATAPI_AL_BLR2 0x0B
109	#define CS4271_DACVOL_ATAPI_ALR2_M 0x0C
110	#define CS4271_DACVOL_ATAPI_ALR2_BR 0x0D
111	#define CS4271_DACVOL_ATAPI_ALR2_BL 0x0E
112	#define CS4271_DACVOL_ATAPI_ALR2_BLR2 0x0F
113
114	#define CS4271_VOLA_MUTE 0x80
115	#define CS4271_VOLA_VOL_MASK 0x7F
116	#define CS4271_VOLB_MUTE 0x80
117	#define CS4271_VOLB_VOL_MASK 0x7F
118
119	#define CS4271_ADCCTL_DITHER16 0x20
120
121	#define CS4271_ADCCTL_ADC_DIF_MASK 0x10
122	#define CS4271_ADCCTL_ADC_DIF_LJ 0x00
123	#define CS4271_ADCCTL_ADC_DIF_I2S 0x10
124
125	#define CS4271_ADCCTL_MUTEA 0x08
126	#define CS4271_ADCCTL_MUTEB 0x04
127	#define CS4271_ADCCTL_HPFDA 0x02
128	#define CS4271_ADCCTL_HPFDB 0x01
129
130	#define CS4271_MODE2_LOOP 0x10
131	#define CS4271_MODE2_MUTECAEQUB 0x08
132	#define CS4271_MODE2_FREEZE 0x04
133	#define CS4271_MODE2_CPEN 0x02
134	#define CS4271_MODE2_PDN 0x01
135
136	#define CS4271_CHIPID_PART_MASK 0xF0
137	#define CS4271_CHIPID_REV_MASK 0x0F
138
139	/*
140	* Default CS4271 power-up configuration
141	* Array contains non-existing in hw register at address 0
142	* Array do not include Chip ID, as codec driver does not use
143	* registers read operations at all
144	*/
145	static const u8 cs4271_dflt_reg[CS4271_NR_REGS] = {
146	0,
147	0,
148	CS4271_DACCTL_AMUTE,
149	CS4271_DACVOL_SOFT \| CS4271_DACVOL_ATAPI_AL_BR,
150	0,
151	0,
152	0,
153	0,
154	};
155
156	struct cs4271_private {
157	/* SND_SOC_I2C or SND_SOC_SPI */
158	enum snd_soc_control_type bus_type;
159	void *control_data;
160	unsigned int mclk;
161	bool master;
162	bool deemph;
163	/* Current sample rate for de-emphasis control */
164	int rate;
165	/* GPIO driving Reset pin, if any */
166	int gpio_nreset;
167	/* GPIO that disable serial bus, if any */
168	int gpio_disable;
169	};
170
171	struct cs4271_clk_cfg {
172	unsigned int ratio; /* MCLK / sample rate */
173	u8 speed_mode; /* codec speed mode: 1x, 2x, 4x */
174	u8 mclk_master; /* ratio bit mask for Master mode */
175	u8 mclk_slave; /* ratio bit mask for Slave mode */
176	};
177
178	static struct cs4271_clk_cfg cs4271_clk_tab[] = {
179	{64, CS4271_MODE1_MODE_4X, CS4271_MODE1_DIV_1, CS4271_MODE1_DIV_1},
180	{96, CS4271_MODE1_MODE_4X, CS4271_MODE1_DIV_15, CS4271_MODE1_DIV_1},
181	{128, CS4271_MODE1_MODE_2X, CS4271_MODE1_DIV_1, CS4271_MODE1_DIV_1},
182	{192, CS4271_MODE1_MODE_2X, CS4271_MODE1_DIV_15, CS4271_MODE1_DIV_1},
183	{256, CS4271_MODE1_MODE_1X, CS4271_MODE1_DIV_1, CS4271_MODE1_DIV_1},
184	{384, CS4271_MODE1_MODE_1X, CS4271_MODE1_DIV_15, CS4271_MODE1_DIV_1},
185	{512, CS4271_MODE1_MODE_1X, CS4271_MODE1_DIV_2, CS4271_MODE1_DIV_1},
186	{768, CS4271_MODE1_MODE_1X, CS4271_MODE1_DIV_3, CS4271_MODE1_DIV_3},
187	{1024, CS4271_MODE1_MODE_1X, CS4271_MODE1_DIV_3, CS4271_MODE1_DIV_3}
188	};
189
190	#define CS4171_NR_RATIOS ARRAY_SIZE(cs4271_clk_tab)
191
192	/*
193	* @freq is the desired MCLK rate
194	* MCLK rate should (c) be the sample rate, multiplied by one of the
195	* ratios listed in cs4271_mclk_fs_ratios table
196	*/
197	static int cs4271_set_dai_sysclk(struct snd_soc_dai *codec_dai,
198	int clk_id, unsigned int freq, int dir)
199	{
200	struct snd_soc_codec *codec = codec_dai->codec;
201	struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
202
203	cs4271->mclk = freq;
204	return 0;
205	}
206
207	static int cs4271_set_dai_fmt(struct snd_soc_dai *codec_dai,
208	unsigned int format)
209	{
210	struct snd_soc_codec *codec = codec_dai->codec;
211	struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
212	unsigned int val = 0;
0d42e6e7	213	int ret;
67b22517 AS	214
	215	switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
	216	case SND_SOC_DAIFMT_CBS_CFS:
	217	cs4271->master = 0;
	218	break;
	219	case SND_SOC_DAIFMT_CBM_CFM:
	220	cs4271->master = 1;
	221	val \|= CS4271_MODE1_MASTER;
	222	break;
	223	default:
	224	dev_err(codec->dev, "Invalid DAI format\n");
	225	return -EINVAL;
	226	}
	227
	228	switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
	229	case SND_SOC_DAIFMT_LEFT_J:
	230	val \|= CS4271_MODE1_DAC_DIF_LJ;
0d42e6e7	231	ret = snd_soc_update_bits(codec, CS4271_ADCCTL,
67b22517	232	CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_LJ);
0d42e6e7 AS	233	if (ret < 0)
0d42e6e7 AS	234	return ret;
67b22517 AS	235	break;
	236	case SND_SOC_DAIFMT_I2S:
	237	val \|= CS4271_MODE1_DAC_DIF_I2S;
0d42e6e7	238	ret = snd_soc_update_bits(codec, CS4271_ADCCTL,
67b22517	239	CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_I2S);
0d42e6e7 AS	240	if (ret < 0)
0d42e6e7 AS	241	return ret;
67b22517 AS	242	break;
	243	default:
	244	dev_err(codec->dev, "Invalid DAI format\n");
	245	return -EINVAL;
	246	}
	247
0d42e6e7	248	ret = snd_soc_update_bits(codec, CS4271_MODE1,
67b22517	249	CS4271_MODE1_DAC_DIF_MASK \| CS4271_MODE1_MASTER, val);
0d42e6e7 AS	250	if (ret < 0)
0d42e6e7 AS	251	return ret;
67b22517 AS	252	return 0;
	253	}
	254
	255	static int cs4271_deemph[] = {0, 44100, 48000, 32000};
	256
	257	static int cs4271_set_deemph(struct snd_soc_codec *codec)
	258	{
	259	struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
0d42e6e7	260	int i, ret;
67b22517 AS	261	int val = CS4271_DACCTL_DEM_DIS;
	262
	263	if (cs4271->deemph) {
	264	/* Find closest de-emphasis freq */
	265	val = 1;
	266	for (i = 2; i < ARRAY_SIZE(cs4271_deemph); i++)
	267	if (abs(cs4271_deemph[i] - cs4271->rate) <
	268	abs(cs4271_deemph[val] - cs4271->rate))
	269	val = i;
	270	val <<= 4;
	271	}
	272
0d42e6e7	273	ret = snd_soc_update_bits(codec, CS4271_DACCTL,
67b22517	274	CS4271_DACCTL_DEM_MASK, val);
0d42e6e7 AS	275	if (ret < 0)
	276	return ret;
	277	return 0;
67b22517 AS	278	}
	279
	280	static int cs4271_get_deemph(struct snd_kcontrol *kcontrol,
	281	struct snd_ctl_elem_value *ucontrol)
	282	{
	283	struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
	284	struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
	285
	286	ucontrol->value.enumerated.item[0] = cs4271->deemph;
	287	return 0;
	288	}
	289
	290	static int cs4271_put_deemph(struct snd_kcontrol *kcontrol,
	291	struct snd_ctl_elem_value *ucontrol)
	292	{
	293	struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
	294	struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
	295
	296	cs4271->deemph = ucontrol->value.enumerated.item[0];
	297	return cs4271_set_deemph(codec);
	298	}
	299
	300	static int cs4271_hw_params(struct snd_pcm_substream *substream,
	301	struct snd_pcm_hw_params *params,
	302	struct snd_soc_dai *dai)
	303	{
	304	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	305	struct snd_soc_codec *codec = rtd->codec;
	306	struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
0d42e6e7 AS	307	int i, ret;
0d42e6e7 AS	308	unsigned int ratio, val;
67b22517 AS	309
	310	cs4271->rate = params_rate(params);
	311	ratio = cs4271->mclk / cs4271->rate;
	312	for (i = 0; i < CS4171_NR_RATIOS; i++)
	313	if (cs4271_clk_tab[i].ratio == ratio)
	314	break;
	315
	316	if ((i == CS4171_NR_RATIOS) \|\| ((ratio == 1024) && cs4271->master)) {
	317	dev_err(codec->dev, "Invalid sample rate\n");
	318	return -EINVAL;
	319	}
	320
	321	/* Configure DAC */
	322	val = cs4271_clk_tab[i].speed_mode;
	323
	324	if (cs4271->master)
	325	val \|= cs4271_clk_tab[i].mclk_master;
	326	else
	327	val \|= cs4271_clk_tab[i].mclk_slave;
	328
0d42e6e7	329	ret = snd_soc_update_bits(codec, CS4271_MODE1,
67b22517	330	CS4271_MODE1_MODE_MASK \| CS4271_MODE1_DIV_MASK, val);
0d42e6e7 AS	331	if (ret < 0)
0d42e6e7 AS	332	return ret;
67b22517 AS	333
	334	return cs4271_set_deemph(codec);
	335	}
	336
	337	static int cs4271_digital_mute(struct snd_soc_dai *dai, int mute)
	338	{
	339	struct snd_soc_codec *codec = dai->codec;
0d42e6e7	340	int ret;
67b22517 AS	341	int val_a = 0;
	342	int val_b = 0;
	343
	344	if (mute) {
	345	val_a = CS4271_VOLA_MUTE;
	346	val_b = CS4271_VOLB_MUTE;
	347	}
	348
0d42e6e7 AS	349	ret = snd_soc_update_bits(codec, CS4271_VOLA, CS4271_VOLA_MUTE, val_a);
	350	if (ret < 0)
	351	return ret;
	352	ret = snd_soc_update_bits(codec, CS4271_VOLB, CS4271_VOLB_MUTE, val_b);
	353	if (ret < 0)
	354	return ret;
67b22517 AS	355
	356	return 0;
	357	}
	358
	359	/* CS4271 controls */
	360	static DECLARE_TLV_DB_SCALE(cs4271_dac_tlv, -12700, 100, 0);
	361
	362	static const struct snd_kcontrol_new cs4271_snd_controls[] = {
	363	SOC_DOUBLE_R_TLV("Master Playback Volume", CS4271_VOLA, CS4271_VOLB,
	364	0, 0x7F, 1, cs4271_dac_tlv),
	365	SOC_SINGLE("Digital Loopback Switch", CS4271_MODE2, 4, 1, 0),
	366	SOC_SINGLE("Soft Ramp Switch", CS4271_DACVOL, 5, 1, 0),
	367	SOC_SINGLE("Zero Cross Switch", CS4271_DACVOL, 4, 1, 0),
	368	SOC_SINGLE_BOOL_EXT("De-emphasis Switch", 0,
	369	cs4271_get_deemph, cs4271_put_deemph),
	370	SOC_SINGLE("Auto-Mute Switch", CS4271_DACCTL, 7, 1, 0),
	371	SOC_SINGLE("Slow Roll Off Filter Switch", CS4271_DACCTL, 6, 1, 0),
	372	SOC_SINGLE("Soft Volume Ramp-Up Switch", CS4271_DACCTL, 3, 1, 0),
	373	SOC_SINGLE("Soft Ramp-Down Switch", CS4271_DACCTL, 2, 1, 0),
	374	SOC_SINGLE("Left Channel Inversion Switch", CS4271_DACCTL, 1, 1, 0),
	375	SOC_SINGLE("Right Channel Inversion Switch", CS4271_DACCTL, 0, 1, 0),
	376	SOC_DOUBLE("Master Capture Switch", CS4271_ADCCTL, 3, 2, 1, 1),
	377	SOC_SINGLE("Dither 16-Bit Data Switch", CS4271_ADCCTL, 5, 1, 0),
	378	SOC_DOUBLE("High Pass Filter Switch", CS4271_ADCCTL, 1, 0, 1, 1),
	379	SOC_DOUBLE_R("Master Playback Switch", CS4271_VOLA, CS4271_VOLB,
	380	7, 1, 1),
	381	};
	382
	383	static struct snd_soc_dai_ops cs4271_dai_ops = {
	384	.hw_params = cs4271_hw_params,
	385	.set_sysclk = cs4271_set_dai_sysclk,
	386	.set_fmt = cs4271_set_dai_fmt,
	387	.digital_mute = cs4271_digital_mute,
	388	};
	389
16af7d60	390	static struct snd_soc_dai_driver cs4271_dai = {
67b22517 AS	391	.name = "cs4271-hifi",
	392	.playback = {
	393	.stream_name = "Playback",
	394	.channels_min = 2,
	395	.channels_max = 2,
383f8465	396	.rates = CS4271_PCM_RATES,
67b22517 AS	397	.formats = CS4271_PCM_FORMATS,
	398	},
	399	.capture = {
	400	.stream_name = "Capture",
	401	.channels_min = 2,
	402	.channels_max = 2,
383f8465	403	.rates = CS4271_PCM_RATES,
67b22517 AS	404	.formats = CS4271_PCM_FORMATS,
	405	},
	406	.ops = &cs4271_dai_ops,
	407	.symmetric_rates = 1,
	408	};
	409
	410	#ifdef CONFIG_PM
	411	static int cs4271_soc_suspend(struct snd_soc_codec *codec, pm_message_t mesg)
	412	{
0d42e6e7	413	int ret;
67b22517	414	/* Set power-down bit */
0d42e6e7 AS	415	ret = snd_soc_update_bits(codec, CS4271_MODE2, 0, CS4271_MODE2_PDN);
	416	if (ret < 0)
	417	return ret;
67b22517 AS	418	return 0;
	419	}
	420
	421	static int cs4271_soc_resume(struct snd_soc_codec *codec)
	422	{
0d42e6e7	423	int ret;
67b22517	424	/* Restore codec state */
0d42e6e7 AS	425	ret = snd_soc_cache_sync(codec);
	426	if (ret < 0)
	427	return ret;
67b22517	428	/* then disable the power-down bit */
0d42e6e7 AS	429	ret = snd_soc_update_bits(codec, CS4271_MODE2, CS4271_MODE2_PDN, 0);
	430	if (ret < 0)
	431	return ret;
67b22517 AS	432	return 0;
	433	}
	434	#else
	435	#define cs4271_soc_suspend NULL
	436	#define cs4271_soc_resume NULL
	437	#endif /* CONFIG_PM */
	438
	439	static int cs4271_probe(struct snd_soc_codec *codec)
	440	{
	441	struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
	442	struct cs4271_platform_data *cs4271plat = codec->dev->platform_data;
	443	int ret;
	444	int gpio_nreset = -EINVAL;
67b22517 AS	445
	446	codec->control_data = cs4271->control_data;
	447
a98a0bc6 AS	448	if (cs4271plat && gpio_is_valid(cs4271plat->gpio_nreset))
a98a0bc6 AS	449	gpio_nreset = cs4271plat->gpio_nreset;
67b22517 AS	450
	451	if (gpio_nreset >= 0)
	452	if (gpio_request(gpio_nreset, "CS4271 Reset"))
	453	gpio_nreset = -EINVAL;
	454	if (gpio_nreset >= 0) {
	455	/* Reset codec */
	456	gpio_direction_output(gpio_nreset, 0);
	457	udelay(1);
	458	gpio_set_value(gpio_nreset, 1);
	459	/* Give the codec time to wake up */
	460	udelay(1);
	461	}
	462
	463	cs4271->gpio_nreset = gpio_nreset;
67b22517 AS	464
	465	/*
	466	* In case of I2C, chip address specified in board data.
	467	* So cache IO operations use 8 bit codec register address.
	468	* In case of SPI, chip address and register address
	469	* passed together as 16 bit value.
	470	* Anyway, register address is masked with 0xFF inside
	471	* soc-cache code.
	472	*/
	473	if (cs4271->bus_type == SND_SOC_SPI)
	474	ret = snd_soc_codec_set_cache_io(codec, 16, 8,
	475	cs4271->bus_type);
	476	else
	477	ret = snd_soc_codec_set_cache_io(codec, 8, 8,
	478	cs4271->bus_type);
	479	if (ret) {
	480	dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
	481	return ret;
	482	}
	483
0d42e6e7	484	ret = snd_soc_update_bits(codec, CS4271_MODE2, 0,
67b22517	485	CS4271_MODE2_PDN \| CS4271_MODE2_CPEN);
0d42e6e7 AS	486	if (ret < 0)
	487	return ret;
	488	ret = snd_soc_update_bits(codec, CS4271_MODE2, CS4271_MODE2_PDN, 0);
	489	if (ret < 0)
	490	return ret;
67b22517 AS	491	/* Power-up sequence requires 85 uS */
	492	udelay(85);
	493
	494	return snd_soc_add_controls(codec, cs4271_snd_controls,
	495	ARRAY_SIZE(cs4271_snd_controls));
	496	}
	497
	498	static int cs4271_remove(struct snd_soc_codec *codec)
	499	{
	500	struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
a98a0bc6	501	int gpio_nreset;
67b22517 AS	502
67b22517 AS	503	gpio_nreset = cs4271->gpio_nreset;
67b22517 AS	504
	505	if (gpio_is_valid(gpio_nreset)) {
	506	/* Set codec to the reset state */
	507	gpio_set_value(gpio_nreset, 0);
	508	gpio_free(gpio_nreset);
	509	}
	510
67b22517 AS	511	return 0;
	512	};
	513
16af7d60	514	static struct snd_soc_codec_driver soc_codec_dev_cs4271 = {
67b22517 AS	515	.probe = cs4271_probe,
	516	.remove = cs4271_remove,
	517	.suspend = cs4271_soc_suspend,
	518	.resume = cs4271_soc_resume,
	519	.reg_cache_default = cs4271_dflt_reg,
	520	.reg_cache_size = ARRAY_SIZE(cs4271_dflt_reg),
	521	.reg_word_size = sizeof(cs4271_dflt_reg[0]),
	522	.compress_type = SND_SOC_FLAT_COMPRESSION,
	523	};
	524
	525	#if defined(CONFIG_SPI_MASTER)
	526	static int __devinit cs4271_spi_probe(struct spi_device *spi)
	527	{
	528	struct cs4271_private *cs4271;
	529
	530	cs4271 = devm_kzalloc(&spi->dev, sizeof(*cs4271), GFP_KERNEL);
	531	if (!cs4271)
	532	return -ENOMEM;
	533
	534	spi_set_drvdata(spi, cs4271);
	535	cs4271->control_data = spi;
	536	cs4271->bus_type = SND_SOC_SPI;
	537
	538	return snd_soc_register_codec(&spi->dev, &soc_codec_dev_cs4271,
	539	&cs4271_dai, 1);
	540	}
	541
	542	static int __devexit cs4271_spi_remove(struct spi_device *spi)
	543	{
	544	snd_soc_unregister_codec(&spi->dev);
	545	return 0;
	546	}
	547
	548	static struct spi_driver cs4271_spi_driver = {
	549	.driver = {
	550	.name = "cs4271",
	551	.owner = THIS_MODULE,
	552	},
	553	.probe = cs4271_spi_probe,
	554	.remove = __devexit_p(cs4271_spi_remove),
	555	};
	556	#endif /* defined(CONFIG_SPI_MASTER) */
	557
	558	#if defined(CONFIG_I2C) \|\| defined(CONFIG_I2C_MODULE)
79a54ea1	559	static const struct i2c_device_id cs4271_i2c_id[] = {
67b22517 AS	560	{"cs4271", 0},
	561	{}
	562	};
	563	MODULE_DEVICE_TABLE(i2c, cs4271_i2c_id);
	564
	565	static int __devinit cs4271_i2c_probe(struct i2c_client *client,
	566	const struct i2c_device_id *id)
	567	{
	568	struct cs4271_private *cs4271;
	569
	570	cs4271 = devm_kzalloc(&client->dev, sizeof(*cs4271), GFP_KERNEL);
	571	if (!cs4271)
	572	return -ENOMEM;
	573
	574	i2c_set_clientdata(client, cs4271);
	575	cs4271->control_data = client;
	576	cs4271->bus_type = SND_SOC_I2C;
	577
	578	return snd_soc_register_codec(&client->dev, &soc_codec_dev_cs4271,
	579	&cs4271_dai, 1);
	580	}
	581
	582	static int __devexit cs4271_i2c_remove(struct i2c_client *client)
	583	{
	584	snd_soc_unregister_codec(&client->dev);
	585	return 0;
	586	}
	587
	588	static struct i2c_driver cs4271_i2c_driver = {
	589	.driver = {
	590	.name = "cs4271",
	591	.owner = THIS_MODULE,
	592	},
	593	.id_table = cs4271_i2c_id,
	594	.probe = cs4271_i2c_probe,
	595	.remove = __devexit_p(cs4271_i2c_remove),
	596	};
	597	#endif /* defined(CONFIG_I2C) \|\| defined(CONFIG_I2C_MODULE) */
	598
	599	/*
	600	* We only register our serial bus driver here without
	601	* assignment to particular chip. So if any of the below
	602	* fails, there is some problem with I2C or SPI subsystem.
	603	* In most cases this module will be compiled with support
	604	* of only one serial bus.
	605	*/
	606	static int __init cs4271_modinit(void)
	607	{
	608	int ret;
	609
	610	#if defined(CONFIG_I2C) \|\| defined(CONFIG_I2C_MODULE)
	611	ret = i2c_add_driver(&cs4271_i2c_driver);
	612	if (ret) {
	613	pr_err("Failed to register CS4271 I2C driver: %d\n", ret);
	614	return ret;
	615	}
	616	#endif
	617
	618	#if defined(CONFIG_SPI_MASTER)
	619	ret = spi_register_driver(&cs4271_spi_driver);
	620	if (ret) {
	621	pr_err("Failed to register CS4271 SPI driver: %d\n", ret);
	622	return ret;
	623	}
624	#endif
625
626	return 0;
627	}
628	module_init(cs4271_modinit);
629
630	static void __exit cs4271_modexit(void)
631	{
632	#if defined(CONFIG_SPI_MASTER)
633	spi_unregister_driver(&cs4271_spi_driver);
634	#endif
635
636	#if defined(CONFIG_I2C) \|\| defined(CONFIG_I2C_MODULE)
637	i2c_del_driver(&cs4271_i2c_driver);
638	#endif
639	}
640	module_exit(cs4271_modexit);
641
642	MODULE_AUTHOR("Alexander Sverdlin <subaparts@yandex.ru>");
643	MODULE_DESCRIPTION("Cirrus Logic CS4271 ALSA SoC Codec Driver");
644	MODULE_LICENSE("GPL");