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ASoC: cs42l52: Replace TLV_DB_RANGE_HEAD with DECLARE_TLV_DB_RANGE
[deliverable/linux.git] / sound / soc / codecs / cs42l52.c
CommitLineData
dfe0f98b
BA		 1/*
2 * cs42l52.c -- CS42L52 ALSA SoC audio driver
3 *
4 * Copyright 2012 CirrusLogic, Inc.
5 *
6 * Author: Georgi Vlaev <joe@nucleusys.com>
7 * Author: Brian Austin <brian.austin@cirrus.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14
15#include <linux/module.h>
16#include <linux/moduleparam.h>
dfe0f98b
BA		 17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/delay.h>
391fc59d 20#include <linux/of_gpio.h>
dfe0f98b
BA		 21#include <linux/pm.h>
22#include <linux/i2c.h>
23#include <linux/input.h>
24#include <linux/regmap.h>
25#include <linux/slab.h>
26#include <linux/workqueue.h>
27#include <linux/platform_device.h>
dfe0f98b
BA		 28#include <sound/core.h>
29#include <sound/pcm.h>
30#include <sound/pcm_params.h>
31#include <sound/soc.h>
32#include <sound/soc-dapm.h>
33#include <sound/initval.h>
34#include <sound/tlv.h>
35#include <sound/cs42l52.h>
36#include "cs42l52.h"
37
38struct sp_config {
39 u8 spc, format, spfs;
40 u32 srate;
41};
42
43struct cs42l52_private {
44 struct regmap *regmap;
45 struct snd_soc_codec *codec;
46 struct device *dev;
47 struct sp_config config;
48 struct cs42l52_platform_data pdata;
49 u32 sysclk;
50 u8 mclksel;
51 u32 mclk;
52 u8 flags;
dfe0f98b
BA		 53 struct input_dev *beep;
54 struct work_struct beep_work;
55 int beep_rate;
dfe0f98b
BA		 56};
57
58static const struct reg_default cs42l52_reg_defaults[] = {
59 { CS42L52_PWRCTL1, 0x9F }, /* r02 PWRCTL 1 */
60 { CS42L52_PWRCTL2, 0x07 }, /* r03 PWRCTL 2 */
61 { CS42L52_PWRCTL3, 0xFF }, /* r04 PWRCTL 3 */
62 { CS42L52_CLK_CTL, 0xA0 }, /* r05 Clocking Ctl */
63 { CS42L52_IFACE_CTL1, 0x00 }, /* r06 Interface Ctl 1 */
64 { CS42L52_ADC_PGA_A, 0x80 }, /* r08 Input A Select */
65 { CS42L52_ADC_PGA_B, 0x80 }, /* r09 Input B Select */
66 { CS42L52_ANALOG_HPF_CTL, 0xA5 }, /* r0A Analog HPF Ctl */
67 { CS42L52_ADC_HPF_FREQ, 0x00 }, /* r0B ADC HPF Corner Freq */
68 { CS42L52_ADC_MISC_CTL, 0x00 }, /* r0C Misc. ADC Ctl */
69 { CS42L52_PB_CTL1, 0x60 }, /* r0D Playback Ctl 1 */
70 { CS42L52_MISC_CTL, 0x02 }, /* r0E Misc. Ctl */
71 { CS42L52_PB_CTL2, 0x00 }, /* r0F Playback Ctl 2 */
72 { CS42L52_MICA_CTL, 0x00 }, /* r10 MICA Amp Ctl */
73 { CS42L52_MICB_CTL, 0x00 }, /* r11 MICB Amp Ctl */
74 { CS42L52_PGAA_CTL, 0x00 }, /* r12 PGAA Vol, Misc. */
75 { CS42L52_PGAB_CTL, 0x00 }, /* r13 PGAB Vol, Misc. */
76 { CS42L52_PASSTHRUA_VOL, 0x00 }, /* r14 Bypass A Vol */
77 { CS42L52_PASSTHRUB_VOL, 0x00 }, /* r15 Bypass B Vol */
78 { CS42L52_ADCA_VOL, 0x00 }, /* r16 ADCA Volume */
79 { CS42L52_ADCB_VOL, 0x00 }, /* r17 ADCB Volume */
80 { CS42L52_ADCA_MIXER_VOL, 0x80 }, /* r18 ADCA Mixer Volume */
81 { CS42L52_ADCB_MIXER_VOL, 0x80 }, /* r19 ADCB Mixer Volume */
82 { CS42L52_PCMA_MIXER_VOL, 0x00 }, /* r1A PCMA Mixer Volume */
83 { CS42L52_PCMB_MIXER_VOL, 0x00 }, /* r1B PCMB Mixer Volume */
84 { CS42L52_BEEP_FREQ, 0x00 }, /* r1C Beep Freq on Time */
85 { CS42L52_BEEP_VOL, 0x00 }, /* r1D Beep Volume off Time */
86 { CS42L52_BEEP_TONE_CTL, 0x00 }, /* r1E Beep Tone Cfg. */
87 { CS42L52_TONE_CTL, 0x00 }, /* r1F Tone Ctl */
04d245b7 88 { CS42L52_MASTERA_VOL, 0x00 }, /* r20 Master A Volume */
dfe0f98b
BA		 89 { CS42L52_MASTERB_VOL, 0x00 }, /* r21 Master B Volume */
90 { CS42L52_HPA_VOL, 0x00 }, /* r22 Headphone A Volume */
91 { CS42L52_HPB_VOL, 0x00 }, /* r23 Headphone B Volume */
92 { CS42L52_SPKA_VOL, 0x00 }, /* r24 Speaker A Volume */
93 { CS42L52_SPKB_VOL, 0x00 }, /* r25 Speaker B Volume */
94 { CS42L52_ADC_PCM_MIXER, 0x00 }, /* r26 Channel Mixer and Swap */
95 { CS42L52_LIMITER_CTL1, 0x00 }, /* r27 Limit Ctl 1 Thresholds */
96 { CS42L52_LIMITER_CTL2, 0x7F }, /* r28 Limit Ctl 2 Release Rate */
97 { CS42L52_LIMITER_AT_RATE, 0xC0 }, /* r29 Limiter Attack Rate */
98 { CS42L52_ALC_CTL, 0x00 }, /* r2A ALC Ctl 1 Attack Rate */
99 { CS42L52_ALC_RATE, 0x3F }, /* r2B ALC Release Rate */
100 { CS42L52_ALC_THRESHOLD, 0x3f }, /* r2C ALC Thresholds */
101 { CS42L52_NOISE_GATE_CTL, 0x00 }, /* r2D Noise Gate Ctl */
102 { CS42L52_CLK_STATUS, 0x00 }, /* r2E Overflow and Clock Status */
103 { CS42L52_BATT_COMPEN, 0x00 }, /* r2F battery Compensation */
104 { CS42L52_BATT_LEVEL, 0x00 }, /* r30 VP Battery Level */
105 { CS42L52_SPK_STATUS, 0x00 }, /* r31 Speaker Status */
106 { CS42L52_TEM_CTL, 0x3B }, /* r32 Temp Ctl */
107 { CS42L52_THE_FOLDBACK, 0x00 }, /* r33 Foldback */
108};
109
110static bool cs42l52_readable_register(struct device *dev, unsigned int reg)
111{
112 switch (reg) {
113 case CS42L52_CHIP:
114 case CS42L52_PWRCTL1:
115 case CS42L52_PWRCTL2:
116 case CS42L52_PWRCTL3:
117 case CS42L52_CLK_CTL:
118 case CS42L52_IFACE_CTL1:
119 case CS42L52_IFACE_CTL2:
120 case CS42L52_ADC_PGA_A:
121 case CS42L52_ADC_PGA_B:
122 case CS42L52_ANALOG_HPF_CTL:
123 case CS42L52_ADC_HPF_FREQ:
124 case CS42L52_ADC_MISC_CTL:
125 case CS42L52_PB_CTL1:
126 case CS42L52_MISC_CTL:
127 case CS42L52_PB_CTL2:
128 case CS42L52_MICA_CTL:
129 case CS42L52_MICB_CTL:
130 case CS42L52_PGAA_CTL:
131 case CS42L52_PGAB_CTL:
132 case CS42L52_PASSTHRUA_VOL:
133 case CS42L52_PASSTHRUB_VOL:
134 case CS42L52_ADCA_VOL:
135 case CS42L52_ADCB_VOL:
136 case CS42L52_ADCA_MIXER_VOL:
137 case CS42L52_ADCB_MIXER_VOL:
138 case CS42L52_PCMA_MIXER_VOL:
139 case CS42L52_PCMB_MIXER_VOL:
140 case CS42L52_BEEP_FREQ:
141 case CS42L52_BEEP_VOL:
142 case CS42L52_BEEP_TONE_CTL:
143 case CS42L52_TONE_CTL:
144 case CS42L52_MASTERA_VOL:
145 case CS42L52_MASTERB_VOL:
146 case CS42L52_HPA_VOL:
147 case CS42L52_HPB_VOL:
148 case CS42L52_SPKA_VOL:
149 case CS42L52_SPKB_VOL:
150 case CS42L52_ADC_PCM_MIXER:
151 case CS42L52_LIMITER_CTL1:
152 case CS42L52_LIMITER_CTL2:
153 case CS42L52_LIMITER_AT_RATE:
154 case CS42L52_ALC_CTL:
155 case CS42L52_ALC_RATE:
156 case CS42L52_ALC_THRESHOLD:
157 case CS42L52_NOISE_GATE_CTL:
158 case CS42L52_CLK_STATUS:
159 case CS42L52_BATT_COMPEN:
160 case CS42L52_BATT_LEVEL:
161 case CS42L52_SPK_STATUS:
162 case CS42L52_TEM_CTL:
163 case CS42L52_THE_FOLDBACK:
164 case CS42L52_CHARGE_PUMP:
165 return true;
166 default:
167 return false;
168 }
169}
170
171static bool cs42l52_volatile_register(struct device *dev, unsigned int reg)
172{
173 switch (reg) {
174 case CS42L52_IFACE_CTL2:
175 case CS42L52_CLK_STATUS:
176 case CS42L52_BATT_LEVEL:
177 case CS42L52_SPK_STATUS:
178 case CS42L52_CHARGE_PUMP:
5c216cc3 179 return true;
dfe0f98b 180 default:
5c216cc3 181 return false;
dfe0f98b
BA		 182 }
183}
184
185static DECLARE_TLV_DB_SCALE(hl_tlv, -10200, 50, 0);
186
187static DECLARE_TLV_DB_SCALE(hpd_tlv, -9600, 50, 1);
188
189static DECLARE_TLV_DB_SCALE(ipd_tlv, -9600, 100, 0);
190
191static DECLARE_TLV_DB_SCALE(mic_tlv, 1600, 100, 0);
192
193static DECLARE_TLV_DB_SCALE(pga_tlv, -600, 50, 0);
194
8ac60a68
NS		 195static DECLARE_TLV_DB_SCALE(mix_tlv, -50, 50, 0);
196
8806d96d
BA		 197static DECLARE_TLV_DB_SCALE(beep_tlv, -56, 200, 0);
198
0a017768 199static const DECLARE_TLV_DB_RANGE(limiter_tlv,
dfe0f98b 200 0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0),
0a017768
LPC		 201 3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0)
202);
dfe0f98b
BA		 203
204static const char * const cs42l52_adca_text[] = {
205 "Input1A", "Input2A", "Input3A", "Input4A", "PGA Input Left"};
206
207static const char * const cs42l52_adcb_text[] = {
208 "Input1B", "Input2B", "Input3B", "Input4B", "PGA Input Right"};
209
4682a0a2
TI		 210static SOC_ENUM_SINGLE_DECL(adca_enum,
211 CS42L52_ADC_PGA_A, 5, cs42l52_adca_text);
dfe0f98b 212
4682a0a2
TI		 213static SOC_ENUM_SINGLE_DECL(adcb_enum,
214 CS42L52_ADC_PGA_B, 5, cs42l52_adcb_text);
dfe0f98b
BA		 215
216static const struct snd_kcontrol_new adca_mux =
217 SOC_DAPM_ENUM("Left ADC Input Capture Mux", adca_enum);
218
219static const struct snd_kcontrol_new adcb_mux =
220 SOC_DAPM_ENUM("Right ADC Input Capture Mux", adcb_enum);
221
222static const char * const mic_bias_level_text[] = {
223 "0.5 +VA", "0.6 +VA", "0.7 +VA",
224 "0.8 +VA", "0.83 +VA", "0.91 +VA"
225};
226
4682a0a2
TI		 227static SOC_ENUM_SINGLE_DECL(mic_bias_level_enum,
228 CS42L52_IFACE_CTL2, 0, mic_bias_level_text);
dfe0f98b 229
a3d36bc2 230static const char * const cs42l52_mic_text[] = { "MIC1", "MIC2" };
dfe0f98b 231
4682a0a2
TI		 232static SOC_ENUM_SINGLE_DECL(mica_enum,
233 CS42L52_MICA_CTL, 5, cs42l52_mic_text);
dfe0f98b 234
4682a0a2
TI		 235static SOC_ENUM_SINGLE_DECL(micb_enum,
236 CS42L52_MICB_CTL, 5, cs42l52_mic_text);
dfe0f98b 237
dfe0f98b
BA		 238static const char * const digital_output_mux_text[] = {"ADC", "DSP"};
239
4682a0a2
TI		 240static SOC_ENUM_SINGLE_DECL(digital_output_mux_enum,
241 CS42L52_ADC_MISC_CTL, 6,
242 digital_output_mux_text);
dfe0f98b
BA		 243
244static const struct snd_kcontrol_new digital_output_mux =
245 SOC_DAPM_ENUM("Digital Output Mux", digital_output_mux_enum);
246
247static const char * const hp_gain_num_text[] = {
248 "0.3959", "0.4571", "0.5111", "0.6047",
249 "0.7099", "0.8399", "1.000", "1.1430"
250};
251
4682a0a2
TI		 252static SOC_ENUM_SINGLE_DECL(hp_gain_enum,
253 CS42L52_PB_CTL1, 5,
254 hp_gain_num_text);
dfe0f98b
BA		 255
256static const char * const beep_pitch_text[] = {
257 "C4", "C5", "D5", "E5", "F5", "G5", "A5", "B5",
258 "C6", "D6", "E6", "F6", "G6", "A6", "B6", "C7"
259};
260
4682a0a2
TI		 261static SOC_ENUM_SINGLE_DECL(beep_pitch_enum,
262 CS42L52_BEEP_FREQ, 4,
263 beep_pitch_text);
dfe0f98b
BA		 264
265static const char * const beep_ontime_text[] = {
266 "86 ms", "430 ms", "780 ms", "1.20 s", "1.50 s",
267 "1.80 s", "2.20 s", "2.50 s", "2.80 s", "3.20 s",
268 "3.50 s", "3.80 s", "4.20 s", "4.50 s", "4.80 s", "5.20 s"
269};
270
4682a0a2
TI		 271static SOC_ENUM_SINGLE_DECL(beep_ontime_enum,
272 CS42L52_BEEP_FREQ, 0,
273 beep_ontime_text);
dfe0f98b
BA		 274
275static const char * const beep_offtime_text[] = {
276 "1.23 s", "2.58 s", "3.90 s", "5.20 s",
277 "6.60 s", "8.05 s", "9.35 s", "10.80 s"
278};
279
4682a0a2
TI		 280static SOC_ENUM_SINGLE_DECL(beep_offtime_enum,
281 CS42L52_BEEP_VOL, 5,
282 beep_offtime_text);
dfe0f98b
BA		 283
284static const char * const beep_config_text[] = {
285 "Off", "Single", "Multiple", "Continuous"
286};
287
4682a0a2
TI		 288static SOC_ENUM_SINGLE_DECL(beep_config_enum,
289 CS42L52_BEEP_TONE_CTL, 6,
290 beep_config_text);
dfe0f98b
BA		 291
292static const char * const beep_bass_text[] = {
293 "50 Hz", "100 Hz", "200 Hz", "250 Hz"
294};
295
4682a0a2
TI		 296static SOC_ENUM_SINGLE_DECL(beep_bass_enum,
297 CS42L52_BEEP_TONE_CTL, 1,
298 beep_bass_text);
dfe0f98b
BA		 299
300static const char * const beep_treble_text[] = {
301 "5 kHz", "7 kHz", "10 kHz", " 15 kHz"
302};
303
4682a0a2
TI		 304static SOC_ENUM_SINGLE_DECL(beep_treble_enum,
305 CS42L52_BEEP_TONE_CTL, 3,
306 beep_treble_text);
dfe0f98b
BA		 307
308static const char * const ng_threshold_text[] = {
309 "-34dB", "-37dB", "-40dB", "-43dB",
310 "-46dB", "-52dB", "-58dB", "-64dB"
311};
312
4682a0a2
TI		 313static SOC_ENUM_SINGLE_DECL(ng_threshold_enum,
314 CS42L52_NOISE_GATE_CTL, 2,
315 ng_threshold_text);
dfe0f98b
BA		 316
317static const char * const cs42l52_ng_delay_text[] = {
318 "50ms", "100ms", "150ms", "200ms"};
319
4682a0a2
TI		 320static SOC_ENUM_SINGLE_DECL(ng_delay_enum,
321 CS42L52_NOISE_GATE_CTL, 0,
322 cs42l52_ng_delay_text);
dfe0f98b
BA		 323
324static const char * const cs42l52_ng_type_text[] = {
325 "Apply Specific", "Apply All"
326};
327
4682a0a2
TI		 328static SOC_ENUM_SINGLE_DECL(ng_type_enum,
329 CS42L52_NOISE_GATE_CTL, 6,
330 cs42l52_ng_type_text);
dfe0f98b
BA		 331
332static const char * const left_swap_text[] = {
333 "Left", "LR 2", "Right"};
334
335static const char * const right_swap_text[] = {
336 "Right", "LR 2", "Left"};
337
338static const unsigned int swap_values[] = { 0, 1, 3 };
339
340static const struct soc_enum adca_swap_enum =
d31a33dd 341 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 2, 3,
dfe0f98b
BA		 342 ARRAY_SIZE(left_swap_text),
343 left_swap_text,
344 swap_values);
345
346static const struct snd_kcontrol_new adca_mixer =
347 SOC_DAPM_ENUM("Route", adca_swap_enum);
348
349static const struct soc_enum pcma_swap_enum =
d31a33dd 350 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 6, 3,
dfe0f98b
BA		 351 ARRAY_SIZE(left_swap_text),
352 left_swap_text,
353 swap_values);
354
355static const struct snd_kcontrol_new pcma_mixer =
356 SOC_DAPM_ENUM("Route", pcma_swap_enum);
357
358static const struct soc_enum adcb_swap_enum =
d31a33dd 359 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 0, 3,
dfe0f98b
BA		 360 ARRAY_SIZE(right_swap_text),
361 right_swap_text,
362 swap_values);
363
364static const struct snd_kcontrol_new adcb_mixer =
365 SOC_DAPM_ENUM("Route", adcb_swap_enum);
366
367static const struct soc_enum pcmb_swap_enum =
d31a33dd 368 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 4, 3,
dfe0f98b
BA		 369 ARRAY_SIZE(right_swap_text),
370 right_swap_text,
371 swap_values);
372
373static const struct snd_kcontrol_new pcmb_mixer =
374 SOC_DAPM_ENUM("Route", pcmb_swap_enum);
375
376
377static const struct snd_kcontrol_new passthrul_ctl =
378 SOC_DAPM_SINGLE("Switch", CS42L52_MISC_CTL, 6, 1, 0);
379
380static const struct snd_kcontrol_new passthrur_ctl =
381 SOC_DAPM_SINGLE("Switch", CS42L52_MISC_CTL, 7, 1, 0);
382
383static const struct snd_kcontrol_new spkl_ctl =
384 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 0, 1, 1);
385
386static const struct snd_kcontrol_new spkr_ctl =
387 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 2, 1, 1);
388
389static const struct snd_kcontrol_new hpl_ctl =
390 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 4, 1, 1);
391
392static const struct snd_kcontrol_new hpr_ctl =
393 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 6, 1, 1);
394
395static const struct snd_kcontrol_new cs42l52_snd_controls[] = {
396
397 SOC_DOUBLE_R_SX_TLV("Master Volume", CS42L52_MASTERA_VOL,
398 CS42L52_MASTERB_VOL, 0, 0x34, 0xE4, hl_tlv),
399
400 SOC_DOUBLE_R_SX_TLV("Headphone Volume", CS42L52_HPA_VOL,
a0465587 401 CS42L52_HPB_VOL, 0, 0x34, 0xC0, hpd_tlv),
dfe0f98b
BA		 402
403 SOC_ENUM("Headphone Analog Gain", hp_gain_enum),
404
405 SOC_DOUBLE_R_SX_TLV("Speaker Volume", CS42L52_SPKA_VOL,
a0465587 406 CS42L52_SPKB_VOL, 0, 0x40, 0xC0, hl_tlv),
dfe0f98b
BA		 407
408 SOC_DOUBLE_R_SX_TLV("Bypass Volume", CS42L52_PASSTHRUA_VOL,
a0465587 409 CS42L52_PASSTHRUB_VOL, 0, 0x88, 0x90, pga_tlv),
dfe0f98b
BA		 410
411 SOC_DOUBLE("Bypass Mute", CS42L52_MISC_CTL, 4, 5, 1, 0),
412
413 SOC_DOUBLE_R_TLV("MIC Gain Volume", CS42L52_MICA_CTL,
414 CS42L52_MICB_CTL, 0, 0x10, 0, mic_tlv),
415
416 SOC_ENUM("MIC Bias Level", mic_bias_level_enum),
417
418 SOC_DOUBLE_R_SX_TLV("ADC Volume", CS42L52_ADCA_VOL,
a0465587 419 CS42L52_ADCB_VOL, 0, 0xA0, 0x78, ipd_tlv),
dfe0f98b
BA		 420 SOC_DOUBLE_R_SX_TLV("ADC Mixer Volume",
421 CS42L52_ADCA_MIXER_VOL, CS42L52_ADCB_MIXER_VOL,
a0465587 422 0, 0x19, 0x7F, ipd_tlv),
dfe0f98b
BA		 423
424 SOC_DOUBLE("ADC Switch", CS42L52_ADC_MISC_CTL, 0, 1, 1, 0),
425
426 SOC_DOUBLE_R("ADC Mixer Switch", CS42L52_ADCA_MIXER_VOL,
427 CS42L52_ADCB_MIXER_VOL, 7, 1, 1),
428
429 SOC_DOUBLE_R_SX_TLV("PGA Volume", CS42L52_PGAA_CTL,
a0465587 430 CS42L52_PGAB_CTL, 0, 0x28, 0x24, pga_tlv),
dfe0f98b
BA		 431
432 SOC_DOUBLE_R_SX_TLV("PCM Mixer Volume",
433 CS42L52_PCMA_MIXER_VOL, CS42L52_PCMB_MIXER_VOL,
a0465587 434 0, 0x19, 0x7f, mix_tlv),
dfe0f98b
BA		 435 SOC_DOUBLE_R("PCM Mixer Switch",
436 CS42L52_PCMA_MIXER_VOL, CS42L52_PCMB_MIXER_VOL, 7, 1, 1),
437
438 SOC_ENUM("Beep Config", beep_config_enum),
439 SOC_ENUM("Beep Pitch", beep_pitch_enum),
440 SOC_ENUM("Beep on Time", beep_ontime_enum),
441 SOC_ENUM("Beep off Time", beep_offtime_enum),
8806d96d
BA		 442 SOC_SINGLE_SX_TLV("Beep Volume", CS42L52_BEEP_VOL,
443 0, 0x07, 0x1f, beep_tlv),
dfe0f98b
BA		 444 SOC_SINGLE("Beep Mixer Switch", CS42L52_BEEP_TONE_CTL, 5, 1, 1),
445 SOC_ENUM("Beep Treble Corner Freq", beep_treble_enum),
446 SOC_ENUM("Beep Bass Corner Freq", beep_bass_enum),
447
448 SOC_SINGLE("Tone Control Switch", CS42L52_BEEP_TONE_CTL, 0, 1, 1),
449 SOC_SINGLE_TLV("Treble Gain Volume",
450 CS42L52_TONE_CTL, 4, 15, 1, hl_tlv),
451 SOC_SINGLE_TLV("Bass Gain Volume",
452 CS42L52_TONE_CTL, 0, 15, 1, hl_tlv),
453
454 /* Limiter */
455 SOC_SINGLE_TLV("Limiter Max Threshold Volume",
456 CS42L52_LIMITER_CTL1, 5, 7, 0, limiter_tlv),
457 SOC_SINGLE_TLV("Limiter Cushion Threshold Volume",
458 CS42L52_LIMITER_CTL1, 2, 7, 0, limiter_tlv),
459 SOC_SINGLE_TLV("Limiter Release Rate Volume",
460 CS42L52_LIMITER_CTL2, 0, 63, 0, limiter_tlv),
461 SOC_SINGLE_TLV("Limiter Attack Rate Volume",
462 CS42L52_LIMITER_AT_RATE, 0, 63, 0, limiter_tlv),
463
464 SOC_SINGLE("Limiter SR Switch", CS42L52_LIMITER_CTL1, 1, 1, 0),
465 SOC_SINGLE("Limiter ZC Switch", CS42L52_LIMITER_CTL1, 0, 1, 0),
466 SOC_SINGLE("Limiter Switch", CS42L52_LIMITER_CTL2, 7, 1, 0),
467
468 /* ALC */
469 SOC_SINGLE_TLV("ALC Attack Rate Volume", CS42L52_ALC_CTL,
470 0, 63, 0, limiter_tlv),
471 SOC_SINGLE_TLV("ALC Release Rate Volume", CS42L52_ALC_RATE,
472 0, 63, 0, limiter_tlv),
473 SOC_SINGLE_TLV("ALC Max Threshold Volume", CS42L52_ALC_THRESHOLD,
474 5, 7, 0, limiter_tlv),
475 SOC_SINGLE_TLV("ALC Min Threshold Volume", CS42L52_ALC_THRESHOLD,
476 2, 7, 0, limiter_tlv),
477
478 SOC_DOUBLE_R("ALC SR Capture Switch", CS42L52_PGAA_CTL,
479 CS42L52_PGAB_CTL, 7, 1, 1),
480 SOC_DOUBLE_R("ALC ZC Capture Switch", CS42L52_PGAA_CTL,
481 CS42L52_PGAB_CTL, 6, 1, 1),
482 SOC_DOUBLE("ALC Capture Switch", CS42L52_ALC_CTL, 6, 7, 1, 0),
483
484 /* Noise gate */
485 SOC_ENUM("NG Type Switch", ng_type_enum),
486 SOC_SINGLE("NG Enable Switch", CS42L52_NOISE_GATE_CTL, 6, 1, 0),
487 SOC_SINGLE("NG Boost Switch", CS42L52_NOISE_GATE_CTL, 5, 1, 1),
488 SOC_ENUM("NG Threshold", ng_threshold_enum),
489 SOC_ENUM("NG Delay", ng_delay_enum),
490
491 SOC_DOUBLE("HPF Switch", CS42L52_ANALOG_HPF_CTL, 5, 7, 1, 0),
492
493 SOC_DOUBLE("Analog SR Switch", CS42L52_ANALOG_HPF_CTL, 1, 3, 1, 1),
494 SOC_DOUBLE("Analog ZC Switch", CS42L52_ANALOG_HPF_CTL, 0, 2, 1, 1),
495 SOC_SINGLE("Digital SR Switch", CS42L52_MISC_CTL, 1, 1, 0),
496 SOC_SINGLE("Digital ZC Switch", CS42L52_MISC_CTL, 0, 1, 0),
497 SOC_SINGLE("Deemphasis Switch", CS42L52_MISC_CTL, 2, 1, 0),
498
499 SOC_SINGLE("Batt Compensation Switch", CS42L52_BATT_COMPEN, 7, 1, 0),
500 SOC_SINGLE("Batt VP Monitor Switch", CS42L52_BATT_COMPEN, 6, 1, 0),
501 SOC_SINGLE("Batt VP ref", CS42L52_BATT_COMPEN, 0, 0x0f, 0),
502
503 SOC_SINGLE("PGA AIN1L Switch", CS42L52_ADC_PGA_A, 0, 1, 0),
504 SOC_SINGLE("PGA AIN1R Switch", CS42L52_ADC_PGA_B, 0, 1, 0),
505 SOC_SINGLE("PGA AIN2L Switch", CS42L52_ADC_PGA_A, 1, 1, 0),
506 SOC_SINGLE("PGA AIN2R Switch", CS42L52_ADC_PGA_B, 1, 1, 0),
507
508 SOC_SINGLE("PGA AIN3L Switch", CS42L52_ADC_PGA_A, 2, 1, 0),
509 SOC_SINGLE("PGA AIN3R Switch", CS42L52_ADC_PGA_B, 2, 1, 0),
510
511 SOC_SINGLE("PGA AIN4L Switch", CS42L52_ADC_PGA_A, 3, 1, 0),
512 SOC_SINGLE("PGA AIN4R Switch", CS42L52_ADC_PGA_B, 3, 1, 0),
513
514 SOC_SINGLE("PGA MICA Switch", CS42L52_ADC_PGA_A, 4, 1, 0),
515 SOC_SINGLE("PGA MICB Switch", CS42L52_ADC_PGA_B, 4, 1, 0),
516
517};
518
44b2ed54
BA		 519static const struct snd_kcontrol_new cs42l52_mica_controls[] = {
520 SOC_ENUM("MICA Select", mica_enum),
521};
522
523static const struct snd_kcontrol_new cs42l52_micb_controls[] = {
524 SOC_ENUM("MICB Select", micb_enum),
525};
526
527static int cs42l52_add_mic_controls(struct snd_soc_codec *codec)
528{
529 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
530 struct cs42l52_platform_data *pdata = &cs42l52->pdata;
531
532 if (!pdata->mica_diff_cfg)
533 snd_soc_add_codec_controls(codec, cs42l52_mica_controls,
534 ARRAY_SIZE(cs42l52_mica_controls));
535
536 if (!pdata->micb_diff_cfg)
537 snd_soc_add_codec_controls(codec, cs42l52_micb_controls,
538 ARRAY_SIZE(cs42l52_micb_controls));
539
540 return 0;
541}
542
dfe0f98b
BA		 543static const struct snd_soc_dapm_widget cs42l52_dapm_widgets[] = {
544
545 SND_SOC_DAPM_INPUT("AIN1L"),
546 SND_SOC_DAPM_INPUT("AIN1R"),
547 SND_SOC_DAPM_INPUT("AIN2L"),
548 SND_SOC_DAPM_INPUT("AIN2R"),
549 SND_SOC_DAPM_INPUT("AIN3L"),
550 SND_SOC_DAPM_INPUT("AIN3R"),
551 SND_SOC_DAPM_INPUT("AIN4L"),
552 SND_SOC_DAPM_INPUT("AIN4R"),
553 SND_SOC_DAPM_INPUT("MICA"),
554 SND_SOC_DAPM_INPUT("MICB"),
555 SND_SOC_DAPM_SIGGEN("Beep"),
556
557 SND_SOC_DAPM_AIF_OUT("AIFOUTL", NULL, 0,
558 SND_SOC_NOPM, 0, 0),
559 SND_SOC_DAPM_AIF_OUT("AIFOUTR", NULL, 0,
560 SND_SOC_NOPM, 0, 0),
561
dfe0f98b
BA		 562 SND_SOC_DAPM_ADC("ADC Left", NULL, CS42L52_PWRCTL1, 1, 1),
563 SND_SOC_DAPM_ADC("ADC Right", NULL, CS42L52_PWRCTL1, 2, 1),
564 SND_SOC_DAPM_PGA("PGA Left", CS42L52_PWRCTL1, 3, 1, NULL, 0),
565 SND_SOC_DAPM_PGA("PGA Right", CS42L52_PWRCTL1, 4, 1, NULL, 0),
566
567 SND_SOC_DAPM_MUX("ADC Left Mux", SND_SOC_NOPM, 0, 0, &adca_mux),
568 SND_SOC_DAPM_MUX("ADC Right Mux", SND_SOC_NOPM, 0, 0, &adcb_mux),
569
570 SND_SOC_DAPM_MUX("ADC Left Swap", SND_SOC_NOPM,
571 0, 0, &adca_mixer),
572 SND_SOC_DAPM_MUX("ADC Right Swap", SND_SOC_NOPM,
573 0, 0, &adcb_mixer),
574
575 SND_SOC_DAPM_MUX("Output Mux", SND_SOC_NOPM,
576 0, 0, &digital_output_mux),
577
578 SND_SOC_DAPM_PGA("PGA MICA", CS42L52_PWRCTL2, 1, 1, NULL, 0),
579 SND_SOC_DAPM_PGA("PGA MICB", CS42L52_PWRCTL2, 2, 1, NULL, 0),
580
581 SND_SOC_DAPM_SUPPLY("Mic Bias", CS42L52_PWRCTL2, 0, 1, NULL, 0),
582 SND_SOC_DAPM_SUPPLY("Charge Pump", CS42L52_PWRCTL1, 7, 1, NULL, 0),
583
584 SND_SOC_DAPM_AIF_IN("AIFINL", NULL, 0,
585 SND_SOC_NOPM, 0, 0),
586 SND_SOC_DAPM_AIF_IN("AIFINR", NULL, 0,
587 SND_SOC_NOPM, 0, 0),
588
589 SND_SOC_DAPM_DAC("DAC Left", NULL, SND_SOC_NOPM, 0, 0),
590 SND_SOC_DAPM_DAC("DAC Right", NULL, SND_SOC_NOPM, 0, 0),
591
592 SND_SOC_DAPM_SWITCH("Bypass Left", CS42L52_MISC_CTL,
593 6, 0, &passthrul_ctl),
594 SND_SOC_DAPM_SWITCH("Bypass Right", CS42L52_MISC_CTL,
595 7, 0, &passthrur_ctl),
596
597 SND_SOC_DAPM_MUX("PCM Left Swap", SND_SOC_NOPM,
598 0, 0, &pcma_mixer),
599 SND_SOC_DAPM_MUX("PCM Right Swap", SND_SOC_NOPM,
600 0, 0, &pcmb_mixer),
601
602 SND_SOC_DAPM_SWITCH("HP Left Amp", SND_SOC_NOPM, 0, 0, &hpl_ctl),
603 SND_SOC_DAPM_SWITCH("HP Right Amp", SND_SOC_NOPM, 0, 0, &hpr_ctl),
604
605 SND_SOC_DAPM_SWITCH("SPK Left Amp", SND_SOC_NOPM, 0, 0, &spkl_ctl),
606 SND_SOC_DAPM_SWITCH("SPK Right Amp", SND_SOC_NOPM, 0, 0, &spkr_ctl),
607
608 SND_SOC_DAPM_OUTPUT("HPOUTA"),
609 SND_SOC_DAPM_OUTPUT("HPOUTB"),
610 SND_SOC_DAPM_OUTPUT("SPKOUTA"),
611 SND_SOC_DAPM_OUTPUT("SPKOUTB"),
612
613};
614
615static const struct snd_soc_dapm_route cs42l52_audio_map[] = {
616
617 {"Capture", NULL, "AIFOUTL"},
618 {"Capture", NULL, "AIFOUTL"},
619
620 {"AIFOUTL", NULL, "Output Mux"},
621 {"AIFOUTR", NULL, "Output Mux"},
622
623 {"Output Mux", "ADC", "ADC Left"},
624 {"Output Mux", "ADC", "ADC Right"},
625
626 {"ADC Left", NULL, "Charge Pump"},
627 {"ADC Right", NULL, "Charge Pump"},
628
629 {"Charge Pump", NULL, "ADC Left Mux"},
630 {"Charge Pump", NULL, "ADC Right Mux"},
631
632 {"ADC Left Mux", "Input1A", "AIN1L"},
633 {"ADC Right Mux", "Input1B", "AIN1R"},
634 {"ADC Left Mux", "Input2A", "AIN2L"},
635 {"ADC Right Mux", "Input2B", "AIN2R"},
636 {"ADC Left Mux", "Input3A", "AIN3L"},
637 {"ADC Right Mux", "Input3B", "AIN3R"},
638 {"ADC Left Mux", "Input4A", "AIN4L"},
639 {"ADC Right Mux", "Input4B", "AIN4R"},
640 {"ADC Left Mux", "PGA Input Left", "PGA Left"},
641 {"ADC Right Mux", "PGA Input Right" , "PGA Right"},
642
643 {"PGA Left", "Switch", "AIN1L"},
644 {"PGA Right", "Switch", "AIN1R"},
645 {"PGA Left", "Switch", "AIN2L"},
646 {"PGA Right", "Switch", "AIN2R"},
647 {"PGA Left", "Switch", "AIN3L"},
648 {"PGA Right", "Switch", "AIN3R"},
649 {"PGA Left", "Switch", "AIN4L"},
650 {"PGA Right", "Switch", "AIN4R"},
651
652 {"PGA Left", "Switch", "PGA MICA"},
653 {"PGA MICA", NULL, "MICA"},
654
655 {"PGA Right", "Switch", "PGA MICB"},
656 {"PGA MICB", NULL, "MICB"},
657
658 {"HPOUTA", NULL, "HP Left Amp"},
659 {"HPOUTB", NULL, "HP Right Amp"},
660 {"HP Left Amp", NULL, "Bypass Left"},
661 {"HP Right Amp", NULL, "Bypass Right"},
662 {"Bypass Left", "Switch", "PGA Left"},
663 {"Bypass Right", "Switch", "PGA Right"},
664 {"HP Left Amp", "Switch", "DAC Left"},
665 {"HP Right Amp", "Switch", "DAC Right"},
666
667 {"SPKOUTA", NULL, "SPK Left Amp"},
668 {"SPKOUTB", NULL, "SPK Right Amp"},
669
670 {"SPK Left Amp", NULL, "Beep"},
671 {"SPK Right Amp", NULL, "Beep"},
672 {"SPK Left Amp", "Switch", "Playback"},
673 {"SPK Right Amp", "Switch", "Playback"},
674
675 {"DAC Left", NULL, "Beep"},
676 {"DAC Right", NULL, "Beep"},
677 {"DAC Left", NULL, "Playback"},
678 {"DAC Right", NULL, "Playback"},
679
680 {"Output Mux", "DSP", "Playback"},
681 {"Output Mux", "DSP", "Playback"},
682
683 {"AIFINL", NULL, "Playback"},
684 {"AIFINR", NULL, "Playback"},
685
686};
687
688struct cs42l52_clk_para {
689 u32 mclk;
690 u32 rate;
691 u8 speed;
692 u8 group;
693 u8 videoclk;
694 u8 ratio;
695 u8 mclkdiv2;
696};
697
698static const struct cs42l52_clk_para clk_map_table[] = {
699 /*8k*/
700 {12288000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
701 {18432000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
702 {12000000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
703 {24000000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
704 {27000000, 8000, CLK_QS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 0},
705
706 /*11.025k*/
707 {11289600, 11025, CLK_QS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
708 {16934400, 11025, CLK_QS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
709
710 /*16k*/
711 {12288000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
712 {18432000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
713 {12000000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
714 {24000000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
715 {27000000, 16000, CLK_HS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 1},
716
717 /*22.05k*/
718 {11289600, 22050, CLK_HS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
719 {16934400, 22050, CLK_HS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
720
721 /* 32k */
722 {12288000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
723 {18432000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
724 {12000000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
725 {24000000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
726 {27000000, 32000, CLK_SS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 0},
727
728 /* 44.1k */
729 {11289600, 44100, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
730 {16934400, 44100, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
731
732 /* 48k */
733 {12288000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
734 {18432000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
735 {12000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 0},
736 {24000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 1},
737 {27000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_27M_MCLK, CLK_R_125, 1},
738
739 /* 88.2k */
740 {11289600, 88200, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
741 {16934400, 88200, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
742
743 /* 96k */
744 {12288000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
745 {18432000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
746 {12000000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 0},
747 {24000000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 1},
748};
749
750static int cs42l52_get_clk(int mclk, int rate)
751{
3271a4fc 752 int i, ret = -EINVAL;
dfe0f98b
BA		 753 u_int mclk1, mclk2 = 0;
754
755 for (i = 0; i < ARRAY_SIZE(clk_map_table); i++) {
756 if (clk_map_table[i].rate == rate) {
757 mclk1 = clk_map_table[i].mclk;
758 if (abs(mclk - mclk1) < abs(mclk - mclk2)) {
759 mclk2 = mclk1;
760 ret = i;
761 }
762 }
763 }
dfe0f98b
BA		 764 return ret;
765}
766
767static int cs42l52_set_sysclk(struct snd_soc_dai *codec_dai,
768 int clk_id, unsigned int freq, int dir)
769{
770 struct snd_soc_codec *codec = codec_dai->codec;
771 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
772
773 if ((freq >= CS42L52_MIN_CLK) && (freq <= CS42L52_MAX_CLK)) {
774 cs42l52->sysclk = freq;
775 } else {
ec8f53fb 776 dev_err(codec->dev, "Invalid freq parameter\n");
dfe0f98b
BA		 777 return -EINVAL;
778 }
779 return 0;
780}
781
782static int cs42l52_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
783{
784 struct snd_soc_codec *codec = codec_dai->codec;
785 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
dfe0f98b
BA		 786 u8 iface = 0;
787
788 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
789 case SND_SOC_DAIFMT_CBM_CFM:
790 iface = CS42L52_IFACE_CTL1_MASTER;
791 break;
792 case SND_SOC_DAIFMT_CBS_CFS:
793 iface = CS42L52_IFACE_CTL1_SLAVE;
794 break;
795 default:
796 return -EINVAL;
797 }
798
799 /* interface format */
800 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
801 case SND_SOC_DAIFMT_I2S:
802 iface |= CS42L52_IFACE_CTL1_ADC_FMT_I2S |
803 CS42L52_IFACE_CTL1_DAC_FMT_I2S;
804 break;
805 case SND_SOC_DAIFMT_RIGHT_J:
806 iface |= CS42L52_IFACE_CTL1_DAC_FMT_RIGHT_J;
807 break;
808 case SND_SOC_DAIFMT_LEFT_J:
809 iface |= CS42L52_IFACE_CTL1_ADC_FMT_LEFT_J |
810 CS42L52_IFACE_CTL1_DAC_FMT_LEFT_J;
811 break;
812 case SND_SOC_DAIFMT_DSP_A:
813 iface |= CS42L52_IFACE_CTL1_DSP_MODE_EN;
814 break;
815 case SND_SOC_DAIFMT_DSP_B:
816 break;
817 default:
818 return -EINVAL;
819 }
820
821 /* clock inversion */
822 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
823 case SND_SOC_DAIFMT_NB_NF:
824 break;
825 case SND_SOC_DAIFMT_IB_IF:
826 iface |= CS42L52_IFACE_CTL1_INV_SCLK;
827 break;
828 case SND_SOC_DAIFMT_IB_NF:
829 iface |= CS42L52_IFACE_CTL1_INV_SCLK;
830 break;
831 case SND_SOC_DAIFMT_NB_IF:
832 break;
833 default:
5c855c8e 834 return -EINVAL;
dfe0f98b
BA		 835 }
836 cs42l52->config.format = iface;
837 snd_soc_write(codec, CS42L52_IFACE_CTL1, cs42l52->config.format);
838
839 return 0;
840}
841
842static int cs42l52_digital_mute(struct snd_soc_dai *dai, int mute)
843{
844 struct snd_soc_codec *codec = dai->codec;
845
846 if (mute)
847 snd_soc_update_bits(codec, CS42L52_PB_CTL1,
848 CS42L52_PB_CTL1_MUTE_MASK,
849 CS42L52_PB_CTL1_MUTE);
850 else
851 snd_soc_update_bits(codec, CS42L52_PB_CTL1,
852 CS42L52_PB_CTL1_MUTE_MASK,
853 CS42L52_PB_CTL1_UNMUTE);
854
855 return 0;
856}
857
858static int cs42l52_pcm_hw_params(struct snd_pcm_substream *substream,
859 struct snd_pcm_hw_params *params,
860 struct snd_soc_dai *dai)
861{
862 struct snd_soc_codec *codec = dai->codec;
863 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
864 u32 clk = 0;
865 int index;
866
867 index = cs42l52_get_clk(cs42l52->sysclk, params_rate(params));
868 if (index >= 0) {
869 cs42l52->sysclk = clk_map_table[index].mclk;
870
871 clk |= (clk_map_table[index].speed << CLK_SPEED_SHIFT) |
872 (clk_map_table[index].group << CLK_32K_SR_SHIFT) |
873 (clk_map_table[index].videoclk << CLK_27M_MCLK_SHIFT) |
874 (clk_map_table[index].ratio << CLK_RATIO_SHIFT) |
875 clk_map_table[index].mclkdiv2;
876
877 snd_soc_write(codec, CS42L52_CLK_CTL, clk);
878 } else {
879 dev_err(codec->dev, "can't get correct mclk\n");
880 return -EINVAL;
881 }
882
883 return 0;
884}
885
886static int cs42l52_set_bias_level(struct snd_soc_codec *codec,
887 enum snd_soc_bias_level level)
888{
889 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
890
891 switch (level) {
892 case SND_SOC_BIAS_ON:
893 break;
894 case SND_SOC_BIAS_PREPARE:
895 snd_soc_update_bits(codec, CS42L52_PWRCTL1,
896 CS42L52_PWRCTL1_PDN_CODEC, 0);
897 break;
898 case SND_SOC_BIAS_STANDBY:
43a0350f 899 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
dfe0f98b
BA		 900 regcache_cache_only(cs42l52->regmap, false);
901 regcache_sync(cs42l52->regmap);
902 }
903 snd_soc_write(codec, CS42L52_PWRCTL1, CS42L52_PWRCTL1_PDN_ALL);
904 break;
905 case SND_SOC_BIAS_OFF:
906 snd_soc_write(codec, CS42L52_PWRCTL1, CS42L52_PWRCTL1_PDN_ALL);
907 regcache_cache_only(cs42l52->regmap, true);
908 break;
909 }
dfe0f98b
BA		 910
911 return 0;
912}
913
914#define CS42L52_RATES (SNDRV_PCM_RATE_8000_96000)
915
916#define CS42L52_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE | \
917 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_U18_3LE | \
918 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_U20_3LE | \
919 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE)
920
921static struct snd_soc_dai_ops cs42l52_ops = {
922 .hw_params = cs42l52_pcm_hw_params,
923 .digital_mute = cs42l52_digital_mute,
924 .set_fmt = cs42l52_set_fmt,
925 .set_sysclk = cs42l52_set_sysclk,
926};
927
a7f44885 928static struct snd_soc_dai_driver cs42l52_dai = {
dfe0f98b
BA		 929 .name = "cs42l52",
930 .playback = {
931 .stream_name = "Playback",
932 .channels_min = 1,
933 .channels_max = 2,
934 .rates = CS42L52_RATES,
935 .formats = CS42L52_FORMATS,
936 },
937 .capture = {
938 .stream_name = "Capture",
939 .channels_min = 1,
940 .channels_max = 2,
941 .rates = CS42L52_RATES,
942 .formats = CS42L52_FORMATS,
943 },
944 .ops = &cs42l52_ops,
945};
946
dfe0f98b
BA		 947static int beep_rates[] = {
948 261, 522, 585, 667, 706, 774, 889, 1000,
949 1043, 1200, 1333, 1412, 1600, 1714, 2000, 2182
950};
951
952static void cs42l52_beep_work(struct work_struct *work)
953{
954 struct cs42l52_private *cs42l52 =
955 container_of(work, struct cs42l52_private, beep_work);
956 struct snd_soc_codec *codec = cs42l52->codec;
43a0350f 957 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
dfe0f98b
BA		 958 int i;
959 int val = 0;
960 int best = 0;
961
962 if (cs42l52->beep_rate) {
963 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
964 if (abs(cs42l52->beep_rate - beep_rates[i]) <
965 abs(cs42l52->beep_rate - beep_rates[best]))
966 best = i;
967 }
968
969 dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n",
970 beep_rates[best], cs42l52->beep_rate);
971
972 val = (best << CS42L52_BEEP_RATE_SHIFT);
973
974 snd_soc_dapm_enable_pin(dapm, "Beep");
975 } else {
976 dev_dbg(codec->dev, "Disabling beep\n");
977 snd_soc_dapm_disable_pin(dapm, "Beep");
978 }
979
980 snd_soc_update_bits(codec, CS42L52_BEEP_FREQ,
981 CS42L52_BEEP_RATE_MASK, val);
982
983 snd_soc_dapm_sync(dapm);
984}
985
986/* For usability define a way of injecting beep events for the device -
987 * many systems will not have a keyboard.
988 */
989static int cs42l52_beep_event(struct input_dev *dev, unsigned int type,
990 unsigned int code, int hz)
991{
992 struct snd_soc_codec *codec = input_get_drvdata(dev);
993 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
994
995 dev_dbg(codec->dev, "Beep event %x %x\n", code, hz);
996
997 switch (code) {
998 case SND_BELL:
999 if (hz)
1000 hz = 261;
1001 case SND_TONE:
1002 break;
1003 default:
1004 return -1;
1005 }
1006
1007 /* Kick the beep from a workqueue */
1008 cs42l52->beep_rate = hz;
1009 schedule_work(&cs42l52->beep_work);
1010 return 0;
1011}
1012
1013static ssize_t cs42l52_beep_set(struct device *dev,
1014 struct device_attribute *attr,
1015 const char *buf, size_t count)
1016{
1017 struct cs42l52_private *cs42l52 = dev_get_drvdata(dev);
1018 long int time;
1019 int ret;
1020
1021 ret = kstrtol(buf, 10, &time);
1022 if (ret != 0)
1023 return ret;
1024
1025 input_event(cs42l52->beep, EV_SND, SND_TONE, time);
1026
1027 return count;
1028}
1029
1030static DEVICE_ATTR(beep, 0200, NULL, cs42l52_beep_set);
1031
1032static void cs42l52_init_beep(struct snd_soc_codec *codec)
1033{
1034 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1035 int ret;
1036
e958f8b8 1037 cs42l52->beep = devm_input_allocate_device(codec->dev);
dfe0f98b
BA		 1038 if (!cs42l52->beep) {
1039 dev_err(codec->dev, "Failed to allocate beep device\n");
1040 return;
1041 }
1042
1043 INIT_WORK(&cs42l52->beep_work, cs42l52_beep_work);
1044 cs42l52->beep_rate = 0;
1045
1046 cs42l52->beep->name = "CS42L52 Beep Generator";
1047 cs42l52->beep->phys = dev_name(codec->dev);
1048 cs42l52->beep->id.bustype = BUS_I2C;
1049
1050 cs42l52->beep->evbit[0] = BIT_MASK(EV_SND);
1051 cs42l52->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
1052 cs42l52->beep->event = cs42l52_beep_event;
1053 cs42l52->beep->dev.parent = codec->dev;
1054 input_set_drvdata(cs42l52->beep, codec);
1055
1056 ret = input_register_device(cs42l52->beep);
1057 if (ret != 0) {
dfe0f98b
BA		 1058 cs42l52->beep = NULL;
1059 dev_err(codec->dev, "Failed to register beep device\n");
1060 }
1061
1062 ret = device_create_file(codec->dev, &dev_attr_beep);
1063 if (ret != 0) {
1064 dev_err(codec->dev, "Failed to create keyclick file: %d\n",
1065 ret);
1066 }
1067}
1068
1069static void cs42l52_free_beep(struct snd_soc_codec *codec)
1070{
1071 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1072
1073 device_remove_file(codec->dev, &dev_attr_beep);
dfe0f98b
BA		 1074 cancel_work_sync(&cs42l52->beep_work);
1075 cs42l52->beep = NULL;
1076
1077 snd_soc_update_bits(codec, CS42L52_BEEP_TONE_CTL,
1078 CS42L52_BEEP_EN_MASK, 0);
1079}
dfe0f98b
BA		 1080
1081static int cs42l52_probe(struct snd_soc_codec *codec)
1082{
1083 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
dfe0f98b 1084
dfe0f98b
BA		 1085 regcache_cache_only(cs42l52->regmap, true);
1086
44b2ed54
BA		 1087 cs42l52_add_mic_controls(codec);
1088
dfe0f98b
BA		 1089 cs42l52_init_beep(codec);
1090
dfe0f98b
BA		 1091 cs42l52->sysclk = CS42L52_DEFAULT_CLK;
1092 cs42l52->config.format = CS42L52_DEFAULT_FORMAT;
1093
5d6be5aa 1094 return 0;
dfe0f98b
BA		 1095}
1096
1097static int cs42l52_remove(struct snd_soc_codec *codec)
1098{
1099 cs42l52_free_beep(codec);
dfe0f98b
BA		 1100
1101 return 0;
1102}
1103
b5fbcbab 1104static const struct snd_soc_codec_driver soc_codec_dev_cs42l52 = {
dfe0f98b
BA		 1105 .probe = cs42l52_probe,
1106 .remove = cs42l52_remove,
dfe0f98b 1107 .set_bias_level = cs42l52_set_bias_level,
417c60e8 1108 .suspend_bias_off = true,
dfe0f98b
BA		 1109
1110 .dapm_widgets = cs42l52_dapm_widgets,
1111 .num_dapm_widgets = ARRAY_SIZE(cs42l52_dapm_widgets),
1112 .dapm_routes = cs42l52_audio_map,
1113 .num_dapm_routes = ARRAY_SIZE(cs42l52_audio_map),
1114
1115 .controls = cs42l52_snd_controls,
1116 .num_controls = ARRAY_SIZE(cs42l52_snd_controls),
1117};
1118
1119/* Current and threshold powerup sequence Pg37 */
1120static const struct reg_default cs42l52_threshold_patch[] = {
1121
1122 { 0x00, 0x99 },
1123 { 0x3E, 0xBA },
1124 { 0x47, 0x80 },
1125 { 0x32, 0xBB },
1126 { 0x32, 0x3B },
1127 { 0x00, 0x00 },
1128
1129};
1130
b5fbcbab 1131static const struct regmap_config cs42l52_regmap = {
dfe0f98b
BA		 1132 .reg_bits = 8,
1133 .val_bits = 8,
1134
1135 .max_register = CS42L52_MAX_REGISTER,
1136 .reg_defaults = cs42l52_reg_defaults,
1137 .num_reg_defaults = ARRAY_SIZE(cs42l52_reg_defaults),
1138 .readable_reg = cs42l52_readable_register,
1139 .volatile_reg = cs42l52_volatile_register,
1140 .cache_type = REGCACHE_RBTREE,
1141};
1142
1143static int cs42l52_i2c_probe(struct i2c_client *i2c_client,
1144 const struct i2c_device_id *id)
1145{
1146 struct cs42l52_private *cs42l52;
6dd17757 1147 struct cs42l52_platform_data *pdata = dev_get_platdata(&i2c_client->dev);
dfe0f98b
BA		 1148 int ret;
1149 unsigned int devid = 0;
1150 unsigned int reg;
391fc59d 1151 u32 val32;
dfe0f98b
BA		 1152
1153 cs42l52 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l52_private),
1154 GFP_KERNEL);
1155 if (cs42l52 == NULL)
1156 return -ENOMEM;
1157 cs42l52->dev = &i2c_client->dev;
1158
134b2f57 1159 cs42l52->regmap = devm_regmap_init_i2c(i2c_client, &cs42l52_regmap);
dfe0f98b
BA		 1160 if (IS_ERR(cs42l52->regmap)) {
1161 ret = PTR_ERR(cs42l52->regmap);
1162 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
134b2f57 1163 return ret;
dfe0f98b 1164 }
391fc59d
BA		 1165 if (pdata) {
1166 cs42l52->pdata = *pdata;
1167 } else {
1168 pdata = devm_kzalloc(&i2c_client->dev,
1169 sizeof(struct cs42l52_platform_data),
1170 GFP_KERNEL);
1171 if (!pdata) {
1172 dev_err(&i2c_client->dev, "could not allocate pdata\n");
1173 return -ENOMEM;
1174 }
1175 if (i2c_client->dev.of_node) {
1176 if (of_property_read_bool(i2c_client->dev.of_node,
1177 "cirrus,mica-differential-cfg"))
1178 pdata->mica_diff_cfg = true;
1179
1180 if (of_property_read_bool(i2c_client->dev.of_node,
1181 "cirrus,micb-differential-cfg"))
1182 pdata->micb_diff_cfg = true;
1183
1184 if (of_property_read_u32(i2c_client->dev.of_node,
1185 "cirrus,micbias-lvl", &val32) >= 0)
1186 pdata->micbias_lvl = val32;
1187
1188 if (of_property_read_u32(i2c_client->dev.of_node,
1189 "cirrus,chgfreq-divisor", &val32) >= 0)
69ae8489 1190 pdata->chgfreq = val32;
391fc59d
BA		 1191
1192 pdata->reset_gpio =
1193 of_get_named_gpio(i2c_client->dev.of_node,
1194 "cirrus,reset-gpio", 0);
1195 }
6dd17757 1196 cs42l52->pdata = *pdata;
391fc59d 1197 }
dfe0f98b 1198
6dd17757 1199 if (cs42l52->pdata.reset_gpio) {
4e17d2d3
AL		 1200 ret = devm_gpio_request_one(&i2c_client->dev,
1201 cs42l52->pdata.reset_gpio,
1202 GPIOF_OUT_INIT_HIGH,
1203 "CS42L52 /RST");
6dd17757
BA		 1204 if (ret < 0) {
1205 dev_err(&i2c_client->dev, "Failed to request /RST %d: %d\n",
1206 cs42l52->pdata.reset_gpio, ret);
1207 return ret;
1208 }
1209 gpio_set_value_cansleep(cs42l52->pdata.reset_gpio, 0);
1210 gpio_set_value_cansleep(cs42l52->pdata.reset_gpio, 1);
1211 }
1212
1213 i2c_set_clientdata(i2c_client, cs42l52);
dfe0f98b
BA		 1214
1215 ret = regmap_register_patch(cs42l52->regmap, cs42l52_threshold_patch,
1216 ARRAY_SIZE(cs42l52_threshold_patch));
1217 if (ret != 0)
1218 dev_warn(cs42l52->dev, "Failed to apply regmap patch: %d\n",
1219 ret);
1220
1221 ret = regmap_read(cs42l52->regmap, CS42L52_CHIP, &reg);
1222 devid = reg & CS42L52_CHIP_ID_MASK;
1223 if (devid != CS42L52_CHIP_ID) {
1224 ret = -ENODEV;
1225 dev_err(&i2c_client->dev,
1226 "CS42L52 Device ID (%X). Expected %X\n",
1227 devid, CS42L52_CHIP_ID);
134b2f57 1228 return ret;
dfe0f98b
BA		 1229 }
1230
e5f03af6 1231 dev_info(&i2c_client->dev, "Cirrus Logic CS42L52, Revision: %02X\n",
a14bf887 1232 reg & CS42L52_CHIP_REV_MASK);
e5f03af6 1233
153723f6 1234 /* Set Platform Data */
44b2ed54 1235 if (cs42l52->pdata.mica_diff_cfg)
153723f6
BA		 1236 regmap_update_bits(cs42l52->regmap, CS42L52_MICA_CTL,
1237 CS42L52_MIC_CTL_TYPE_MASK,
44b2ed54 1238 cs42l52->pdata.mica_diff_cfg <<
153723f6
BA		 1239 CS42L52_MIC_CTL_TYPE_SHIFT);
1240
44b2ed54 1241 if (cs42l52->pdata.micb_diff_cfg)
153723f6
BA		 1242 regmap_update_bits(cs42l52->regmap, CS42L52_MICB_CTL,
1243 CS42L52_MIC_CTL_TYPE_MASK,
44b2ed54 1244 cs42l52->pdata.micb_diff_cfg <<
153723f6
BA		 1245 CS42L52_MIC_CTL_TYPE_SHIFT);
1246
153723f6
BA		 1247 if (cs42l52->pdata.chgfreq)
1248 regmap_update_bits(cs42l52->regmap, CS42L52_CHARGE_PUMP,
1249 CS42L52_CHARGE_PUMP_MASK,
1250 cs42l52->pdata.chgfreq <<
1251 CS42L52_CHARGE_PUMP_SHIFT);
1252
1253 if (cs42l52->pdata.micbias_lvl)
1254 regmap_update_bits(cs42l52->regmap, CS42L52_IFACE_CTL2,
1255 CS42L52_IFACE_CTL2_BIAS_LVL,
1256 cs42l52->pdata.micbias_lvl);
dfe0f98b
BA		 1257
1258 ret = snd_soc_register_codec(&i2c_client->dev,
1259 &soc_codec_dev_cs42l52, &cs42l52_dai, 1);
1260 if (ret < 0)
134b2f57 1261 return ret;
dfe0f98b 1262 return 0;
dfe0f98b
BA		 1263}
1264
1265static int cs42l52_i2c_remove(struct i2c_client *client)
1266{
dfe0f98b 1267 snd_soc_unregister_codec(&client->dev);
dfe0f98b
BA		 1268 return 0;
1269}
1270
391fc59d
BA		 1271static const struct of_device_id cs42l52_of_match[] = {
1272 { .compatible = "cirrus,cs42l52", },
1273 {},
1274};
1275MODULE_DEVICE_TABLE(of, cs42l52_of_match);
1276
1277
dfe0f98b
BA		 1278static const struct i2c_device_id cs42l52_id[] = {
1279 { "cs42l52", 0 },
1280 { }
1281};
1282MODULE_DEVICE_TABLE(i2c, cs42l52_id);
1283
1284static struct i2c_driver cs42l52_i2c_driver = {
1285 .driver = {
1286 .name = "cs42l52",
1287 .owner = THIS_MODULE,
391fc59d 1288 .of_match_table = cs42l52_of_match,
dfe0f98b
BA		 1289 },
1290 .id_table = cs42l52_id,
1291 .probe = cs42l52_i2c_probe,
7a79e94e 1292 .remove = cs42l52_i2c_remove,
dfe0f98b
BA		 1293};
1294
dfe0f98b
BA		 1295module_i2c_driver(cs42l52_i2c_driver);
1296
1297MODULE_DESCRIPTION("ASoC CS42L52 driver");
1298MODULE_AUTHOR("Georgi Vlaev, Nucleus Systems Ltd, <joe@nucleusys.com>");
1299MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1300MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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