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ASoC: cs42l52: Reorganize MICA/B Config and Select
[deliverable/linux.git] / sound / soc / codecs / cs42l52.c
CommitLineData
dfe0f98b
BA		 1/*
2 * cs42l52.c -- CS42L52 ALSA SoC audio driver
3 *
4 * Copyright 2012 CirrusLogic, Inc.
5 *
6 * Author: Georgi Vlaev <joe@nucleusys.com>
7 * Author: Brian Austin <brian.austin@cirrus.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14
15#include <linux/module.h>
16#include <linux/moduleparam.h>
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BA		 17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/delay.h>
6dd17757 20#include <linux/gpio.h>
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BA		 21#include <linux/pm.h>
22#include <linux/i2c.h>
23#include <linux/input.h>
24#include <linux/regmap.h>
25#include <linux/slab.h>
26#include <linux/workqueue.h>
27#include <linux/platform_device.h>
dfe0f98b
BA		 28#include <sound/core.h>
29#include <sound/pcm.h>
30#include <sound/pcm_params.h>
31#include <sound/soc.h>
32#include <sound/soc-dapm.h>
33#include <sound/initval.h>
34#include <sound/tlv.h>
35#include <sound/cs42l52.h>
36#include "cs42l52.h"
37
38struct sp_config {
39 u8 spc, format, spfs;
40 u32 srate;
41};
42
43struct cs42l52_private {
44 struct regmap *regmap;
45 struct snd_soc_codec *codec;
46 struct device *dev;
47 struct sp_config config;
48 struct cs42l52_platform_data pdata;
49 u32 sysclk;
50 u8 mclksel;
51 u32 mclk;
52 u8 flags;
7ae10ed2 53#if IS_ENABLED(CONFIG_INPUT)
dfe0f98b
BA		 54 struct input_dev *beep;
55 struct work_struct beep_work;
56 int beep_rate;
57#endif
58};
59
60static const struct reg_default cs42l52_reg_defaults[] = {
61 { CS42L52_PWRCTL1, 0x9F }, /* r02 PWRCTL 1 */
62 { CS42L52_PWRCTL2, 0x07 }, /* r03 PWRCTL 2 */
63 { CS42L52_PWRCTL3, 0xFF }, /* r04 PWRCTL 3 */
64 { CS42L52_CLK_CTL, 0xA0 }, /* r05 Clocking Ctl */
65 { CS42L52_IFACE_CTL1, 0x00 }, /* r06 Interface Ctl 1 */
66 { CS42L52_ADC_PGA_A, 0x80 }, /* r08 Input A Select */
67 { CS42L52_ADC_PGA_B, 0x80 }, /* r09 Input B Select */
68 { CS42L52_ANALOG_HPF_CTL, 0xA5 }, /* r0A Analog HPF Ctl */
69 { CS42L52_ADC_HPF_FREQ, 0x00 }, /* r0B ADC HPF Corner Freq */
70 { CS42L52_ADC_MISC_CTL, 0x00 }, /* r0C Misc. ADC Ctl */
71 { CS42L52_PB_CTL1, 0x60 }, /* r0D Playback Ctl 1 */
72 { CS42L52_MISC_CTL, 0x02 }, /* r0E Misc. Ctl */
73 { CS42L52_PB_CTL2, 0x00 }, /* r0F Playback Ctl 2 */
74 { CS42L52_MICA_CTL, 0x00 }, /* r10 MICA Amp Ctl */
75 { CS42L52_MICB_CTL, 0x00 }, /* r11 MICB Amp Ctl */
76 { CS42L52_PGAA_CTL, 0x00 }, /* r12 PGAA Vol, Misc. */
77 { CS42L52_PGAB_CTL, 0x00 }, /* r13 PGAB Vol, Misc. */
78 { CS42L52_PASSTHRUA_VOL, 0x00 }, /* r14 Bypass A Vol */
79 { CS42L52_PASSTHRUB_VOL, 0x00 }, /* r15 Bypass B Vol */
80 { CS42L52_ADCA_VOL, 0x00 }, /* r16 ADCA Volume */
81 { CS42L52_ADCB_VOL, 0x00 }, /* r17 ADCB Volume */
82 { CS42L52_ADCA_MIXER_VOL, 0x80 }, /* r18 ADCA Mixer Volume */
83 { CS42L52_ADCB_MIXER_VOL, 0x80 }, /* r19 ADCB Mixer Volume */
84 { CS42L52_PCMA_MIXER_VOL, 0x00 }, /* r1A PCMA Mixer Volume */
85 { CS42L52_PCMB_MIXER_VOL, 0x00 }, /* r1B PCMB Mixer Volume */
86 { CS42L52_BEEP_FREQ, 0x00 }, /* r1C Beep Freq on Time */
87 { CS42L52_BEEP_VOL, 0x00 }, /* r1D Beep Volume off Time */
88 { CS42L52_BEEP_TONE_CTL, 0x00 }, /* r1E Beep Tone Cfg. */
89 { CS42L52_TONE_CTL, 0x00 }, /* r1F Tone Ctl */
04d245b7 90 { CS42L52_MASTERA_VOL, 0x00 }, /* r20 Master A Volume */
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BA		 91 { CS42L52_MASTERB_VOL, 0x00 }, /* r21 Master B Volume */
92 { CS42L52_HPA_VOL, 0x00 }, /* r22 Headphone A Volume */
93 { CS42L52_HPB_VOL, 0x00 }, /* r23 Headphone B Volume */
94 { CS42L52_SPKA_VOL, 0x00 }, /* r24 Speaker A Volume */
95 { CS42L52_SPKB_VOL, 0x00 }, /* r25 Speaker B Volume */
96 { CS42L52_ADC_PCM_MIXER, 0x00 }, /* r26 Channel Mixer and Swap */
97 { CS42L52_LIMITER_CTL1, 0x00 }, /* r27 Limit Ctl 1 Thresholds */
98 { CS42L52_LIMITER_CTL2, 0x7F }, /* r28 Limit Ctl 2 Release Rate */
99 { CS42L52_LIMITER_AT_RATE, 0xC0 }, /* r29 Limiter Attack Rate */
100 { CS42L52_ALC_CTL, 0x00 }, /* r2A ALC Ctl 1 Attack Rate */
101 { CS42L52_ALC_RATE, 0x3F }, /* r2B ALC Release Rate */
102 { CS42L52_ALC_THRESHOLD, 0x3f }, /* r2C ALC Thresholds */
103 { CS42L52_NOISE_GATE_CTL, 0x00 }, /* r2D Noise Gate Ctl */
104 { CS42L52_CLK_STATUS, 0x00 }, /* r2E Overflow and Clock Status */
105 { CS42L52_BATT_COMPEN, 0x00 }, /* r2F battery Compensation */
106 { CS42L52_BATT_LEVEL, 0x00 }, /* r30 VP Battery Level */
107 { CS42L52_SPK_STATUS, 0x00 }, /* r31 Speaker Status */
108 { CS42L52_TEM_CTL, 0x3B }, /* r32 Temp Ctl */
109 { CS42L52_THE_FOLDBACK, 0x00 }, /* r33 Foldback */
110};
111
112static bool cs42l52_readable_register(struct device *dev, unsigned int reg)
113{
114 switch (reg) {
115 case CS42L52_CHIP:
116 case CS42L52_PWRCTL1:
117 case CS42L52_PWRCTL2:
118 case CS42L52_PWRCTL3:
119 case CS42L52_CLK_CTL:
120 case CS42L52_IFACE_CTL1:
121 case CS42L52_IFACE_CTL2:
122 case CS42L52_ADC_PGA_A:
123 case CS42L52_ADC_PGA_B:
124 case CS42L52_ANALOG_HPF_CTL:
125 case CS42L52_ADC_HPF_FREQ:
126 case CS42L52_ADC_MISC_CTL:
127 case CS42L52_PB_CTL1:
128 case CS42L52_MISC_CTL:
129 case CS42L52_PB_CTL2:
130 case CS42L52_MICA_CTL:
131 case CS42L52_MICB_CTL:
132 case CS42L52_PGAA_CTL:
133 case CS42L52_PGAB_CTL:
134 case CS42L52_PASSTHRUA_VOL:
135 case CS42L52_PASSTHRUB_VOL:
136 case CS42L52_ADCA_VOL:
137 case CS42L52_ADCB_VOL:
138 case CS42L52_ADCA_MIXER_VOL:
139 case CS42L52_ADCB_MIXER_VOL:
140 case CS42L52_PCMA_MIXER_VOL:
141 case CS42L52_PCMB_MIXER_VOL:
142 case CS42L52_BEEP_FREQ:
143 case CS42L52_BEEP_VOL:
144 case CS42L52_BEEP_TONE_CTL:
145 case CS42L52_TONE_CTL:
146 case CS42L52_MASTERA_VOL:
147 case CS42L52_MASTERB_VOL:
148 case CS42L52_HPA_VOL:
149 case CS42L52_HPB_VOL:
150 case CS42L52_SPKA_VOL:
151 case CS42L52_SPKB_VOL:
152 case CS42L52_ADC_PCM_MIXER:
153 case CS42L52_LIMITER_CTL1:
154 case CS42L52_LIMITER_CTL2:
155 case CS42L52_LIMITER_AT_RATE:
156 case CS42L52_ALC_CTL:
157 case CS42L52_ALC_RATE:
158 case CS42L52_ALC_THRESHOLD:
159 case CS42L52_NOISE_GATE_CTL:
160 case CS42L52_CLK_STATUS:
161 case CS42L52_BATT_COMPEN:
162 case CS42L52_BATT_LEVEL:
163 case CS42L52_SPK_STATUS:
164 case CS42L52_TEM_CTL:
165 case CS42L52_THE_FOLDBACK:
166 case CS42L52_CHARGE_PUMP:
167 return true;
168 default:
169 return false;
170 }
171}
172
173static bool cs42l52_volatile_register(struct device *dev, unsigned int reg)
174{
175 switch (reg) {
176 case CS42L52_IFACE_CTL2:
177 case CS42L52_CLK_STATUS:
178 case CS42L52_BATT_LEVEL:
179 case CS42L52_SPK_STATUS:
180 case CS42L52_CHARGE_PUMP:
181 return 1;
182 default:
183 return 0;
184 }
185}
186
187static DECLARE_TLV_DB_SCALE(hl_tlv, -10200, 50, 0);
188
189static DECLARE_TLV_DB_SCALE(hpd_tlv, -9600, 50, 1);
190
191static DECLARE_TLV_DB_SCALE(ipd_tlv, -9600, 100, 0);
192
193static DECLARE_TLV_DB_SCALE(mic_tlv, 1600, 100, 0);
194
195static DECLARE_TLV_DB_SCALE(pga_tlv, -600, 50, 0);
196
8ac60a68
NS		 197static DECLARE_TLV_DB_SCALE(mix_tlv, -50, 50, 0);
198
8806d96d
BA		 199static DECLARE_TLV_DB_SCALE(beep_tlv, -56, 200, 0);
200
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BA		 201static const unsigned int limiter_tlv[] = {
202 TLV_DB_RANGE_HEAD(2),
203 0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0),
204 3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0),
205};
206
207static const char * const cs42l52_adca_text[] = {
208 "Input1A", "Input2A", "Input3A", "Input4A", "PGA Input Left"};
209
210static const char * const cs42l52_adcb_text[] = {
211 "Input1B", "Input2B", "Input3B", "Input4B", "PGA Input Right"};
212
213static const struct soc_enum adca_enum =
214 SOC_ENUM_SINGLE(CS42L52_ADC_PGA_A, 5,
215 ARRAY_SIZE(cs42l52_adca_text), cs42l52_adca_text);
216
217static const struct soc_enum adcb_enum =
218 SOC_ENUM_SINGLE(CS42L52_ADC_PGA_B, 5,
219 ARRAY_SIZE(cs42l52_adcb_text), cs42l52_adcb_text);
220
221static const struct snd_kcontrol_new adca_mux =
222 SOC_DAPM_ENUM("Left ADC Input Capture Mux", adca_enum);
223
224static const struct snd_kcontrol_new adcb_mux =
225 SOC_DAPM_ENUM("Right ADC Input Capture Mux", adcb_enum);
226
227static const char * const mic_bias_level_text[] = {
228 "0.5 +VA", "0.6 +VA", "0.7 +VA",
229 "0.8 +VA", "0.83 +VA", "0.91 +VA"
230};
231
232static const struct soc_enum mic_bias_level_enum =
0b6e81d1 233 SOC_ENUM_SINGLE(CS42L52_IFACE_CTL2, 0,
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BA		 234 ARRAY_SIZE(mic_bias_level_text), mic_bias_level_text);
235
a3d36bc2 236static const char * const cs42l52_mic_text[] = { "MIC1", "MIC2" };
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BA		 237
238static const struct soc_enum mica_enum =
239 SOC_ENUM_SINGLE(CS42L52_MICA_CTL, 5,
240 ARRAY_SIZE(cs42l52_mic_text), cs42l52_mic_text);
241
242static const struct soc_enum micb_enum =
243 SOC_ENUM_SINGLE(CS42L52_MICB_CTL, 5,
244 ARRAY_SIZE(cs42l52_mic_text), cs42l52_mic_text);
245
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BA		 246static const char * const digital_output_mux_text[] = {"ADC", "DSP"};
247
248static const struct soc_enum digital_output_mux_enum =
249 SOC_ENUM_SINGLE(CS42L52_ADC_MISC_CTL, 6,
250 ARRAY_SIZE(digital_output_mux_text),
251 digital_output_mux_text);
252
253static const struct snd_kcontrol_new digital_output_mux =
254 SOC_DAPM_ENUM("Digital Output Mux", digital_output_mux_enum);
255
256static const char * const hp_gain_num_text[] = {
257 "0.3959", "0.4571", "0.5111", "0.6047",
258 "0.7099", "0.8399", "1.000", "1.1430"
259};
260
261static const struct soc_enum hp_gain_enum =
7d8acf2c 262 SOC_ENUM_SINGLE(CS42L52_PB_CTL1, 5,
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BA		 263 ARRAY_SIZE(hp_gain_num_text), hp_gain_num_text);
264
265static const char * const beep_pitch_text[] = {
266 "C4", "C5", "D5", "E5", "F5", "G5", "A5", "B5",
267 "C6", "D6", "E6", "F6", "G6", "A6", "B6", "C7"
268};
269
270static const struct soc_enum beep_pitch_enum =
271 SOC_ENUM_SINGLE(CS42L52_BEEP_FREQ, 4,
272 ARRAY_SIZE(beep_pitch_text), beep_pitch_text);
273
274static const char * const beep_ontime_text[] = {
275 "86 ms", "430 ms", "780 ms", "1.20 s", "1.50 s",
276 "1.80 s", "2.20 s", "2.50 s", "2.80 s", "3.20 s",
277 "3.50 s", "3.80 s", "4.20 s", "4.50 s", "4.80 s", "5.20 s"
278};
279
280static const struct soc_enum beep_ontime_enum =
281 SOC_ENUM_SINGLE(CS42L52_BEEP_FREQ, 0,
282 ARRAY_SIZE(beep_ontime_text), beep_ontime_text);
283
284static const char * const beep_offtime_text[] = {
285 "1.23 s", "2.58 s", "3.90 s", "5.20 s",
286 "6.60 s", "8.05 s", "9.35 s", "10.80 s"
287};
288
289static const struct soc_enum beep_offtime_enum =
290 SOC_ENUM_SINGLE(CS42L52_BEEP_VOL, 5,
291 ARRAY_SIZE(beep_offtime_text), beep_offtime_text);
292
293static const char * const beep_config_text[] = {
294 "Off", "Single", "Multiple", "Continuous"
295};
296
297static const struct soc_enum beep_config_enum =
298 SOC_ENUM_SINGLE(CS42L52_BEEP_TONE_CTL, 6,
299 ARRAY_SIZE(beep_config_text), beep_config_text);
300
301static const char * const beep_bass_text[] = {
302 "50 Hz", "100 Hz", "200 Hz", "250 Hz"
303};
304
305static const struct soc_enum beep_bass_enum =
306 SOC_ENUM_SINGLE(CS42L52_BEEP_TONE_CTL, 1,
307 ARRAY_SIZE(beep_bass_text), beep_bass_text);
308
309static const char * const beep_treble_text[] = {
310 "5 kHz", "7 kHz", "10 kHz", " 15 kHz"
311};
312
313static const struct soc_enum beep_treble_enum =
314 SOC_ENUM_SINGLE(CS42L52_BEEP_TONE_CTL, 3,
315 ARRAY_SIZE(beep_treble_text), beep_treble_text);
316
317static const char * const ng_threshold_text[] = {
318 "-34dB", "-37dB", "-40dB", "-43dB",
319 "-46dB", "-52dB", "-58dB", "-64dB"
320};
321
322static const struct soc_enum ng_threshold_enum =
323 SOC_ENUM_SINGLE(CS42L52_NOISE_GATE_CTL, 2,
324 ARRAY_SIZE(ng_threshold_text), ng_threshold_text);
325
326static const char * const cs42l52_ng_delay_text[] = {
327 "50ms", "100ms", "150ms", "200ms"};
328
329static const struct soc_enum ng_delay_enum =
330 SOC_ENUM_SINGLE(CS42L52_NOISE_GATE_CTL, 0,
331 ARRAY_SIZE(cs42l52_ng_delay_text), cs42l52_ng_delay_text);
332
333static const char * const cs42l52_ng_type_text[] = {
334 "Apply Specific", "Apply All"
335};
336
337static const struct soc_enum ng_type_enum =
338 SOC_ENUM_SINGLE(CS42L52_NOISE_GATE_CTL, 6,
339 ARRAY_SIZE(cs42l52_ng_type_text), cs42l52_ng_type_text);
340
341static const char * const left_swap_text[] = {
342 "Left", "LR 2", "Right"};
343
344static const char * const right_swap_text[] = {
345 "Right", "LR 2", "Left"};
346
347static const unsigned int swap_values[] = { 0, 1, 3 };
348
349static const struct soc_enum adca_swap_enum =
350 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 2, 1,
351 ARRAY_SIZE(left_swap_text),
352 left_swap_text,
353 swap_values);
354
355static const struct snd_kcontrol_new adca_mixer =
356 SOC_DAPM_ENUM("Route", adca_swap_enum);
357
358static const struct soc_enum pcma_swap_enum =
359 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 6, 1,
360 ARRAY_SIZE(left_swap_text),
361 left_swap_text,
362 swap_values);
363
364static const struct snd_kcontrol_new pcma_mixer =
365 SOC_DAPM_ENUM("Route", pcma_swap_enum);
366
367static const struct soc_enum adcb_swap_enum =
368 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 0, 1,
369 ARRAY_SIZE(right_swap_text),
370 right_swap_text,
371 swap_values);
372
373static const struct snd_kcontrol_new adcb_mixer =
374 SOC_DAPM_ENUM("Route", adcb_swap_enum);
375
376static const struct soc_enum pcmb_swap_enum =
377 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 4, 1,
378 ARRAY_SIZE(right_swap_text),
379 right_swap_text,
380 swap_values);
381
382static const struct snd_kcontrol_new pcmb_mixer =
383 SOC_DAPM_ENUM("Route", pcmb_swap_enum);
384
385
386static const struct snd_kcontrol_new passthrul_ctl =
387 SOC_DAPM_SINGLE("Switch", CS42L52_MISC_CTL, 6, 1, 0);
388
389static const struct snd_kcontrol_new passthrur_ctl =
390 SOC_DAPM_SINGLE("Switch", CS42L52_MISC_CTL, 7, 1, 0);
391
392static const struct snd_kcontrol_new spkl_ctl =
393 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 0, 1, 1);
394
395static const struct snd_kcontrol_new spkr_ctl =
396 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 2, 1, 1);
397
398static const struct snd_kcontrol_new hpl_ctl =
399 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 4, 1, 1);
400
401static const struct snd_kcontrol_new hpr_ctl =
402 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 6, 1, 1);
403
404static const struct snd_kcontrol_new cs42l52_snd_controls[] = {
405
406 SOC_DOUBLE_R_SX_TLV("Master Volume", CS42L52_MASTERA_VOL,
407 CS42L52_MASTERB_VOL, 0, 0x34, 0xE4, hl_tlv),
408
409 SOC_DOUBLE_R_SX_TLV("Headphone Volume", CS42L52_HPA_VOL,
410 CS42L52_HPB_VOL, 0, 0x34, 0xCC, hpd_tlv),
411
412 SOC_ENUM("Headphone Analog Gain", hp_gain_enum),
413
414 SOC_DOUBLE_R_SX_TLV("Speaker Volume", CS42L52_SPKA_VOL,
99674c72 415 CS42L52_SPKB_VOL, 0, 0x1, 0xff, hl_tlv),
dfe0f98b
BA		 416
417 SOC_DOUBLE_R_SX_TLV("Bypass Volume", CS42L52_PASSTHRUA_VOL,
418 CS42L52_PASSTHRUB_VOL, 6, 0x18, 0x90, pga_tlv),
419
420 SOC_DOUBLE("Bypass Mute", CS42L52_MISC_CTL, 4, 5, 1, 0),
421
a3d36bc2
BA		 422 SOC_ENUM("MICA Select", mica_enum),
423 SOC_ENUM("MICB Select", micb_enum),
424
dfe0f98b
BA		 425 SOC_DOUBLE_R_TLV("MIC Gain Volume", CS42L52_MICA_CTL,
426 CS42L52_MICB_CTL, 0, 0x10, 0, mic_tlv),
427
428 SOC_ENUM("MIC Bias Level", mic_bias_level_enum),
429
430 SOC_DOUBLE_R_SX_TLV("ADC Volume", CS42L52_ADCA_VOL,
431 CS42L52_ADCB_VOL, 7, 0x80, 0xA0, ipd_tlv),
432 SOC_DOUBLE_R_SX_TLV("ADC Mixer Volume",
433 CS42L52_ADCA_MIXER_VOL, CS42L52_ADCB_MIXER_VOL,
434 6, 0x7f, 0x19, ipd_tlv),
435
436 SOC_DOUBLE("ADC Switch", CS42L52_ADC_MISC_CTL, 0, 1, 1, 0),
437
438 SOC_DOUBLE_R("ADC Mixer Switch", CS42L52_ADCA_MIXER_VOL,
439 CS42L52_ADCB_MIXER_VOL, 7, 1, 1),
440
441 SOC_DOUBLE_R_SX_TLV("PGA Volume", CS42L52_PGAA_CTL,
442 CS42L52_PGAB_CTL, 0, 0x28, 0x30, pga_tlv),
443
444 SOC_DOUBLE_R_SX_TLV("PCM Mixer Volume",
445 CS42L52_PCMA_MIXER_VOL, CS42L52_PCMB_MIXER_VOL,
8ac60a68 446 0, 0x7f, 0x19, mix_tlv),
dfe0f98b
BA		 447 SOC_DOUBLE_R("PCM Mixer Switch",
448 CS42L52_PCMA_MIXER_VOL, CS42L52_PCMB_MIXER_VOL, 7, 1, 1),
449
450 SOC_ENUM("Beep Config", beep_config_enum),
451 SOC_ENUM("Beep Pitch", beep_pitch_enum),
452 SOC_ENUM("Beep on Time", beep_ontime_enum),
453 SOC_ENUM("Beep off Time", beep_offtime_enum),
8806d96d
BA		 454 SOC_SINGLE_SX_TLV("Beep Volume", CS42L52_BEEP_VOL,
455 0, 0x07, 0x1f, beep_tlv),
dfe0f98b
BA		 456 SOC_SINGLE("Beep Mixer Switch", CS42L52_BEEP_TONE_CTL, 5, 1, 1),
457 SOC_ENUM("Beep Treble Corner Freq", beep_treble_enum),
458 SOC_ENUM("Beep Bass Corner Freq", beep_bass_enum),
459
460 SOC_SINGLE("Tone Control Switch", CS42L52_BEEP_TONE_CTL, 0, 1, 1),
461 SOC_SINGLE_TLV("Treble Gain Volume",
462 CS42L52_TONE_CTL, 4, 15, 1, hl_tlv),
463 SOC_SINGLE_TLV("Bass Gain Volume",
464 CS42L52_TONE_CTL, 0, 15, 1, hl_tlv),
465
466 /* Limiter */
467 SOC_SINGLE_TLV("Limiter Max Threshold Volume",
468 CS42L52_LIMITER_CTL1, 5, 7, 0, limiter_tlv),
469 SOC_SINGLE_TLV("Limiter Cushion Threshold Volume",
470 CS42L52_LIMITER_CTL1, 2, 7, 0, limiter_tlv),
471 SOC_SINGLE_TLV("Limiter Release Rate Volume",
472 CS42L52_LIMITER_CTL2, 0, 63, 0, limiter_tlv),
473 SOC_SINGLE_TLV("Limiter Attack Rate Volume",
474 CS42L52_LIMITER_AT_RATE, 0, 63, 0, limiter_tlv),
475
476 SOC_SINGLE("Limiter SR Switch", CS42L52_LIMITER_CTL1, 1, 1, 0),
477 SOC_SINGLE("Limiter ZC Switch", CS42L52_LIMITER_CTL1, 0, 1, 0),
478 SOC_SINGLE("Limiter Switch", CS42L52_LIMITER_CTL2, 7, 1, 0),
479
480 /* ALC */
481 SOC_SINGLE_TLV("ALC Attack Rate Volume", CS42L52_ALC_CTL,
482 0, 63, 0, limiter_tlv),
483 SOC_SINGLE_TLV("ALC Release Rate Volume", CS42L52_ALC_RATE,
484 0, 63, 0, limiter_tlv),
485 SOC_SINGLE_TLV("ALC Max Threshold Volume", CS42L52_ALC_THRESHOLD,
486 5, 7, 0, limiter_tlv),
487 SOC_SINGLE_TLV("ALC Min Threshold Volume", CS42L52_ALC_THRESHOLD,
488 2, 7, 0, limiter_tlv),
489
490 SOC_DOUBLE_R("ALC SR Capture Switch", CS42L52_PGAA_CTL,
491 CS42L52_PGAB_CTL, 7, 1, 1),
492 SOC_DOUBLE_R("ALC ZC Capture Switch", CS42L52_PGAA_CTL,
493 CS42L52_PGAB_CTL, 6, 1, 1),
494 SOC_DOUBLE("ALC Capture Switch", CS42L52_ALC_CTL, 6, 7, 1, 0),
495
496 /* Noise gate */
497 SOC_ENUM("NG Type Switch", ng_type_enum),
498 SOC_SINGLE("NG Enable Switch", CS42L52_NOISE_GATE_CTL, 6, 1, 0),
499 SOC_SINGLE("NG Boost Switch", CS42L52_NOISE_GATE_CTL, 5, 1, 1),
500 SOC_ENUM("NG Threshold", ng_threshold_enum),
501 SOC_ENUM("NG Delay", ng_delay_enum),
502
503 SOC_DOUBLE("HPF Switch", CS42L52_ANALOG_HPF_CTL, 5, 7, 1, 0),
504
505 SOC_DOUBLE("Analog SR Switch", CS42L52_ANALOG_HPF_CTL, 1, 3, 1, 1),
506 SOC_DOUBLE("Analog ZC Switch", CS42L52_ANALOG_HPF_CTL, 0, 2, 1, 1),
507 SOC_SINGLE("Digital SR Switch", CS42L52_MISC_CTL, 1, 1, 0),
508 SOC_SINGLE("Digital ZC Switch", CS42L52_MISC_CTL, 0, 1, 0),
509 SOC_SINGLE("Deemphasis Switch", CS42L52_MISC_CTL, 2, 1, 0),
510
511 SOC_SINGLE("Batt Compensation Switch", CS42L52_BATT_COMPEN, 7, 1, 0),
512 SOC_SINGLE("Batt VP Monitor Switch", CS42L52_BATT_COMPEN, 6, 1, 0),
513 SOC_SINGLE("Batt VP ref", CS42L52_BATT_COMPEN, 0, 0x0f, 0),
514
515 SOC_SINGLE("PGA AIN1L Switch", CS42L52_ADC_PGA_A, 0, 1, 0),
516 SOC_SINGLE("PGA AIN1R Switch", CS42L52_ADC_PGA_B, 0, 1, 0),
517 SOC_SINGLE("PGA AIN2L Switch", CS42L52_ADC_PGA_A, 1, 1, 0),
518 SOC_SINGLE("PGA AIN2R Switch", CS42L52_ADC_PGA_B, 1, 1, 0),
519
520 SOC_SINGLE("PGA AIN3L Switch", CS42L52_ADC_PGA_A, 2, 1, 0),
521 SOC_SINGLE("PGA AIN3R Switch", CS42L52_ADC_PGA_B, 2, 1, 0),
522
523 SOC_SINGLE("PGA AIN4L Switch", CS42L52_ADC_PGA_A, 3, 1, 0),
524 SOC_SINGLE("PGA AIN4R Switch", CS42L52_ADC_PGA_B, 3, 1, 0),
525
526 SOC_SINGLE("PGA MICA Switch", CS42L52_ADC_PGA_A, 4, 1, 0),
527 SOC_SINGLE("PGA MICB Switch", CS42L52_ADC_PGA_B, 4, 1, 0),
528
529};
530
531static const struct snd_soc_dapm_widget cs42l52_dapm_widgets[] = {
532
533 SND_SOC_DAPM_INPUT("AIN1L"),
534 SND_SOC_DAPM_INPUT("AIN1R"),
535 SND_SOC_DAPM_INPUT("AIN2L"),
536 SND_SOC_DAPM_INPUT("AIN2R"),
537 SND_SOC_DAPM_INPUT("AIN3L"),
538 SND_SOC_DAPM_INPUT("AIN3R"),
539 SND_SOC_DAPM_INPUT("AIN4L"),
540 SND_SOC_DAPM_INPUT("AIN4R"),
541 SND_SOC_DAPM_INPUT("MICA"),
542 SND_SOC_DAPM_INPUT("MICB"),
543 SND_SOC_DAPM_SIGGEN("Beep"),
544
545 SND_SOC_DAPM_AIF_OUT("AIFOUTL", NULL, 0,
546 SND_SOC_NOPM, 0, 0),
547 SND_SOC_DAPM_AIF_OUT("AIFOUTR", NULL, 0,
548 SND_SOC_NOPM, 0, 0),
549
dfe0f98b
BA		 550 SND_SOC_DAPM_ADC("ADC Left", NULL, CS42L52_PWRCTL1, 1, 1),
551 SND_SOC_DAPM_ADC("ADC Right", NULL, CS42L52_PWRCTL1, 2, 1),
552 SND_SOC_DAPM_PGA("PGA Left", CS42L52_PWRCTL1, 3, 1, NULL, 0),
553 SND_SOC_DAPM_PGA("PGA Right", CS42L52_PWRCTL1, 4, 1, NULL, 0),
554
555 SND_SOC_DAPM_MUX("ADC Left Mux", SND_SOC_NOPM, 0, 0, &adca_mux),
556 SND_SOC_DAPM_MUX("ADC Right Mux", SND_SOC_NOPM, 0, 0, &adcb_mux),
557
558 SND_SOC_DAPM_MUX("ADC Left Swap", SND_SOC_NOPM,
559 0, 0, &adca_mixer),
560 SND_SOC_DAPM_MUX("ADC Right Swap", SND_SOC_NOPM,
561 0, 0, &adcb_mixer),
562
563 SND_SOC_DAPM_MUX("Output Mux", SND_SOC_NOPM,
564 0, 0, &digital_output_mux),
565
566 SND_SOC_DAPM_PGA("PGA MICA", CS42L52_PWRCTL2, 1, 1, NULL, 0),
567 SND_SOC_DAPM_PGA("PGA MICB", CS42L52_PWRCTL2, 2, 1, NULL, 0),
568
569 SND_SOC_DAPM_SUPPLY("Mic Bias", CS42L52_PWRCTL2, 0, 1, NULL, 0),
570 SND_SOC_DAPM_SUPPLY("Charge Pump", CS42L52_PWRCTL1, 7, 1, NULL, 0),
571
572 SND_SOC_DAPM_AIF_IN("AIFINL", NULL, 0,
573 SND_SOC_NOPM, 0, 0),
574 SND_SOC_DAPM_AIF_IN("AIFINR", NULL, 0,
575 SND_SOC_NOPM, 0, 0),
576
577 SND_SOC_DAPM_DAC("DAC Left", NULL, SND_SOC_NOPM, 0, 0),
578 SND_SOC_DAPM_DAC("DAC Right", NULL, SND_SOC_NOPM, 0, 0),
579
580 SND_SOC_DAPM_SWITCH("Bypass Left", CS42L52_MISC_CTL,
581 6, 0, &passthrul_ctl),
582 SND_SOC_DAPM_SWITCH("Bypass Right", CS42L52_MISC_CTL,
583 7, 0, &passthrur_ctl),
584
585 SND_SOC_DAPM_MUX("PCM Left Swap", SND_SOC_NOPM,
586 0, 0, &pcma_mixer),
587 SND_SOC_DAPM_MUX("PCM Right Swap", SND_SOC_NOPM,
588 0, 0, &pcmb_mixer),
589
590 SND_SOC_DAPM_SWITCH("HP Left Amp", SND_SOC_NOPM, 0, 0, &hpl_ctl),
591 SND_SOC_DAPM_SWITCH("HP Right Amp", SND_SOC_NOPM, 0, 0, &hpr_ctl),
592
593 SND_SOC_DAPM_SWITCH("SPK Left Amp", SND_SOC_NOPM, 0, 0, &spkl_ctl),
594 SND_SOC_DAPM_SWITCH("SPK Right Amp", SND_SOC_NOPM, 0, 0, &spkr_ctl),
595
596 SND_SOC_DAPM_OUTPUT("HPOUTA"),
597 SND_SOC_DAPM_OUTPUT("HPOUTB"),
598 SND_SOC_DAPM_OUTPUT("SPKOUTA"),
599 SND_SOC_DAPM_OUTPUT("SPKOUTB"),
600
601};
602
603static const struct snd_soc_dapm_route cs42l52_audio_map[] = {
604
605 {"Capture", NULL, "AIFOUTL"},
606 {"Capture", NULL, "AIFOUTL"},
607
608 {"AIFOUTL", NULL, "Output Mux"},
609 {"AIFOUTR", NULL, "Output Mux"},
610
611 {"Output Mux", "ADC", "ADC Left"},
612 {"Output Mux", "ADC", "ADC Right"},
613
614 {"ADC Left", NULL, "Charge Pump"},
615 {"ADC Right", NULL, "Charge Pump"},
616
617 {"Charge Pump", NULL, "ADC Left Mux"},
618 {"Charge Pump", NULL, "ADC Right Mux"},
619
620 {"ADC Left Mux", "Input1A", "AIN1L"},
621 {"ADC Right Mux", "Input1B", "AIN1R"},
622 {"ADC Left Mux", "Input2A", "AIN2L"},
623 {"ADC Right Mux", "Input2B", "AIN2R"},
624 {"ADC Left Mux", "Input3A", "AIN3L"},
625 {"ADC Right Mux", "Input3B", "AIN3R"},
626 {"ADC Left Mux", "Input4A", "AIN4L"},
627 {"ADC Right Mux", "Input4B", "AIN4R"},
628 {"ADC Left Mux", "PGA Input Left", "PGA Left"},
629 {"ADC Right Mux", "PGA Input Right" , "PGA Right"},
630
631 {"PGA Left", "Switch", "AIN1L"},
632 {"PGA Right", "Switch", "AIN1R"},
633 {"PGA Left", "Switch", "AIN2L"},
634 {"PGA Right", "Switch", "AIN2R"},
635 {"PGA Left", "Switch", "AIN3L"},
636 {"PGA Right", "Switch", "AIN3R"},
637 {"PGA Left", "Switch", "AIN4L"},
638 {"PGA Right", "Switch", "AIN4R"},
639
640 {"PGA Left", "Switch", "PGA MICA"},
641 {"PGA MICA", NULL, "MICA"},
642
643 {"PGA Right", "Switch", "PGA MICB"},
644 {"PGA MICB", NULL, "MICB"},
645
646 {"HPOUTA", NULL, "HP Left Amp"},
647 {"HPOUTB", NULL, "HP Right Amp"},
648 {"HP Left Amp", NULL, "Bypass Left"},
649 {"HP Right Amp", NULL, "Bypass Right"},
650 {"Bypass Left", "Switch", "PGA Left"},
651 {"Bypass Right", "Switch", "PGA Right"},
652 {"HP Left Amp", "Switch", "DAC Left"},
653 {"HP Right Amp", "Switch", "DAC Right"},
654
655 {"SPKOUTA", NULL, "SPK Left Amp"},
656 {"SPKOUTB", NULL, "SPK Right Amp"},
657
658 {"SPK Left Amp", NULL, "Beep"},
659 {"SPK Right Amp", NULL, "Beep"},
660 {"SPK Left Amp", "Switch", "Playback"},
661 {"SPK Right Amp", "Switch", "Playback"},
662
663 {"DAC Left", NULL, "Beep"},
664 {"DAC Right", NULL, "Beep"},
665 {"DAC Left", NULL, "Playback"},
666 {"DAC Right", NULL, "Playback"},
667
668 {"Output Mux", "DSP", "Playback"},
669 {"Output Mux", "DSP", "Playback"},
670
671 {"AIFINL", NULL, "Playback"},
672 {"AIFINR", NULL, "Playback"},
673
674};
675
676struct cs42l52_clk_para {
677 u32 mclk;
678 u32 rate;
679 u8 speed;
680 u8 group;
681 u8 videoclk;
682 u8 ratio;
683 u8 mclkdiv2;
684};
685
686static const struct cs42l52_clk_para clk_map_table[] = {
687 /*8k*/
688 {12288000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
689 {18432000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
690 {12000000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
691 {24000000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
692 {27000000, 8000, CLK_QS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 0},
693
694 /*11.025k*/
695 {11289600, 11025, CLK_QS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
696 {16934400, 11025, CLK_QS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
697
698 /*16k*/
699 {12288000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
700 {18432000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
701 {12000000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
702 {24000000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
703 {27000000, 16000, CLK_HS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 1},
704
705 /*22.05k*/
706 {11289600, 22050, CLK_HS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
707 {16934400, 22050, CLK_HS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
708
709 /* 32k */
710 {12288000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
711 {18432000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
712 {12000000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
713 {24000000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
714 {27000000, 32000, CLK_SS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 0},
715
716 /* 44.1k */
717 {11289600, 44100, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
718 {16934400, 44100, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
719
720 /* 48k */
721 {12288000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
722 {18432000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
723 {12000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 0},
724 {24000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 1},
725 {27000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_27M_MCLK, CLK_R_125, 1},
726
727 /* 88.2k */
728 {11289600, 88200, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
729 {16934400, 88200, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
730
731 /* 96k */
732 {12288000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
733 {18432000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
734 {12000000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 0},
735 {24000000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 1},
736};
737
738static int cs42l52_get_clk(int mclk, int rate)
739{
3271a4fc 740 int i, ret = -EINVAL;
dfe0f98b
BA		 741 u_int mclk1, mclk2 = 0;
742
743 for (i = 0; i < ARRAY_SIZE(clk_map_table); i++) {
744 if (clk_map_table[i].rate == rate) {
745 mclk1 = clk_map_table[i].mclk;
746 if (abs(mclk - mclk1) < abs(mclk - mclk2)) {
747 mclk2 = mclk1;
748 ret = i;
749 }
750 }
751 }
dfe0f98b
BA		 752 return ret;
753}
754
755static int cs42l52_set_sysclk(struct snd_soc_dai *codec_dai,
756 int clk_id, unsigned int freq, int dir)
757{
758 struct snd_soc_codec *codec = codec_dai->codec;
759 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
760
761 if ((freq >= CS42L52_MIN_CLK) && (freq <= CS42L52_MAX_CLK)) {
762 cs42l52->sysclk = freq;
763 } else {
ec8f53fb 764 dev_err(codec->dev, "Invalid freq parameter\n");
dfe0f98b
BA		 765 return -EINVAL;
766 }
767 return 0;
768}
769
770static int cs42l52_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
771{
772 struct snd_soc_codec *codec = codec_dai->codec;
773 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
dfe0f98b
BA		 774 u8 iface = 0;
775
776 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
777 case SND_SOC_DAIFMT_CBM_CFM:
778 iface = CS42L52_IFACE_CTL1_MASTER;
779 break;
780 case SND_SOC_DAIFMT_CBS_CFS:
781 iface = CS42L52_IFACE_CTL1_SLAVE;
782 break;
783 default:
784 return -EINVAL;
785 }
786
787 /* interface format */
788 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
789 case SND_SOC_DAIFMT_I2S:
790 iface |= CS42L52_IFACE_CTL1_ADC_FMT_I2S |
791 CS42L52_IFACE_CTL1_DAC_FMT_I2S;
792 break;
793 case SND_SOC_DAIFMT_RIGHT_J:
794 iface |= CS42L52_IFACE_CTL1_DAC_FMT_RIGHT_J;
795 break;
796 case SND_SOC_DAIFMT_LEFT_J:
797 iface |= CS42L52_IFACE_CTL1_ADC_FMT_LEFT_J |
798 CS42L52_IFACE_CTL1_DAC_FMT_LEFT_J;
799 break;
800 case SND_SOC_DAIFMT_DSP_A:
801 iface |= CS42L52_IFACE_CTL1_DSP_MODE_EN;
802 break;
803 case SND_SOC_DAIFMT_DSP_B:
804 break;
805 default:
806 return -EINVAL;
807 }
808
809 /* clock inversion */
810 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
811 case SND_SOC_DAIFMT_NB_NF:
812 break;
813 case SND_SOC_DAIFMT_IB_IF:
814 iface |= CS42L52_IFACE_CTL1_INV_SCLK;
815 break;
816 case SND_SOC_DAIFMT_IB_NF:
817 iface |= CS42L52_IFACE_CTL1_INV_SCLK;
818 break;
819 case SND_SOC_DAIFMT_NB_IF:
820 break;
821 default:
5c855c8e 822 return -EINVAL;
dfe0f98b
BA		 823 }
824 cs42l52->config.format = iface;
825 snd_soc_write(codec, CS42L52_IFACE_CTL1, cs42l52->config.format);
826
827 return 0;
828}
829
830static int cs42l52_digital_mute(struct snd_soc_dai *dai, int mute)
831{
832 struct snd_soc_codec *codec = dai->codec;
833
834 if (mute)
835 snd_soc_update_bits(codec, CS42L52_PB_CTL1,
836 CS42L52_PB_CTL1_MUTE_MASK,
837 CS42L52_PB_CTL1_MUTE);
838 else
839 snd_soc_update_bits(codec, CS42L52_PB_CTL1,
840 CS42L52_PB_CTL1_MUTE_MASK,
841 CS42L52_PB_CTL1_UNMUTE);
842
843 return 0;
844}
845
846static int cs42l52_pcm_hw_params(struct snd_pcm_substream *substream,
847 struct snd_pcm_hw_params *params,
848 struct snd_soc_dai *dai)
849{
850 struct snd_soc_codec *codec = dai->codec;
851 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
852 u32 clk = 0;
853 int index;
854
855 index = cs42l52_get_clk(cs42l52->sysclk, params_rate(params));
856 if (index >= 0) {
857 cs42l52->sysclk = clk_map_table[index].mclk;
858
859 clk |= (clk_map_table[index].speed << CLK_SPEED_SHIFT) |
860 (clk_map_table[index].group << CLK_32K_SR_SHIFT) |
861 (clk_map_table[index].videoclk << CLK_27M_MCLK_SHIFT) |
862 (clk_map_table[index].ratio << CLK_RATIO_SHIFT) |
863 clk_map_table[index].mclkdiv2;
864
865 snd_soc_write(codec, CS42L52_CLK_CTL, clk);
866 } else {
867 dev_err(codec->dev, "can't get correct mclk\n");
868 return -EINVAL;
869 }
870
871 return 0;
872}
873
874static int cs42l52_set_bias_level(struct snd_soc_codec *codec,
875 enum snd_soc_bias_level level)
876{
877 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
878
879 switch (level) {
880 case SND_SOC_BIAS_ON:
881 break;
882 case SND_SOC_BIAS_PREPARE:
883 snd_soc_update_bits(codec, CS42L52_PWRCTL1,
884 CS42L52_PWRCTL1_PDN_CODEC, 0);
885 break;
886 case SND_SOC_BIAS_STANDBY:
887 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
888 regcache_cache_only(cs42l52->regmap, false);
889 regcache_sync(cs42l52->regmap);
890 }
891 snd_soc_write(codec, CS42L52_PWRCTL1, CS42L52_PWRCTL1_PDN_ALL);
892 break;
893 case SND_SOC_BIAS_OFF:
894 snd_soc_write(codec, CS42L52_PWRCTL1, CS42L52_PWRCTL1_PDN_ALL);
895 regcache_cache_only(cs42l52->regmap, true);
896 break;
897 }
898 codec->dapm.bias_level = level;
899
900 return 0;
901}
902
903#define CS42L52_RATES (SNDRV_PCM_RATE_8000_96000)
904
905#define CS42L52_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE | \
906 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_U18_3LE | \
907 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_U20_3LE | \
908 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE)
909
910static struct snd_soc_dai_ops cs42l52_ops = {
911 .hw_params = cs42l52_pcm_hw_params,
912 .digital_mute = cs42l52_digital_mute,
913 .set_fmt = cs42l52_set_fmt,
914 .set_sysclk = cs42l52_set_sysclk,
915};
916
a7f44885 917static struct snd_soc_dai_driver cs42l52_dai = {
dfe0f98b
BA		 918 .name = "cs42l52",
919 .playback = {
920 .stream_name = "Playback",
921 .channels_min = 1,
922 .channels_max = 2,
923 .rates = CS42L52_RATES,
924 .formats = CS42L52_FORMATS,
925 },
926 .capture = {
927 .stream_name = "Capture",
928 .channels_min = 1,
929 .channels_max = 2,
930 .rates = CS42L52_RATES,
931 .formats = CS42L52_FORMATS,
932 },
933 .ops = &cs42l52_ops,
934};
935
936static int cs42l52_suspend(struct snd_soc_codec *codec)
937{
938 cs42l52_set_bias_level(codec, SND_SOC_BIAS_OFF);
939
940 return 0;
941}
942
943static int cs42l52_resume(struct snd_soc_codec *codec)
944{
945 cs42l52_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
946
947 return 0;
948}
949
7ae10ed2 950#if IS_ENABLED(CONFIG_INPUT)
dfe0f98b
BA		 951static int beep_rates[] = {
952 261, 522, 585, 667, 706, 774, 889, 1000,
953 1043, 1200, 1333, 1412, 1600, 1714, 2000, 2182
954};
955
956static void cs42l52_beep_work(struct work_struct *work)
957{
958 struct cs42l52_private *cs42l52 =
959 container_of(work, struct cs42l52_private, beep_work);
960 struct snd_soc_codec *codec = cs42l52->codec;
961 struct snd_soc_dapm_context *dapm = &codec->dapm;
962 int i;
963 int val = 0;
964 int best = 0;
965
966 if (cs42l52->beep_rate) {
967 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
968 if (abs(cs42l52->beep_rate - beep_rates[i]) <
969 abs(cs42l52->beep_rate - beep_rates[best]))
970 best = i;
971 }
972
973 dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n",
974 beep_rates[best], cs42l52->beep_rate);
975
976 val = (best << CS42L52_BEEP_RATE_SHIFT);
977
978 snd_soc_dapm_enable_pin(dapm, "Beep");
979 } else {
980 dev_dbg(codec->dev, "Disabling beep\n");
981 snd_soc_dapm_disable_pin(dapm, "Beep");
982 }
983
984 snd_soc_update_bits(codec, CS42L52_BEEP_FREQ,
985 CS42L52_BEEP_RATE_MASK, val);
986
987 snd_soc_dapm_sync(dapm);
988}
989
990/* For usability define a way of injecting beep events for the device -
991 * many systems will not have a keyboard.
992 */
993static int cs42l52_beep_event(struct input_dev *dev, unsigned int type,
994 unsigned int code, int hz)
995{
996 struct snd_soc_codec *codec = input_get_drvdata(dev);
997 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
998
999 dev_dbg(codec->dev, "Beep event %x %x\n", code, hz);
1000
1001 switch (code) {
1002 case SND_BELL:
1003 if (hz)
1004 hz = 261;
1005 case SND_TONE:
1006 break;
1007 default:
1008 return -1;
1009 }
1010
1011 /* Kick the beep from a workqueue */
1012 cs42l52->beep_rate = hz;
1013 schedule_work(&cs42l52->beep_work);
1014 return 0;
1015}
1016
1017static ssize_t cs42l52_beep_set(struct device *dev,
1018 struct device_attribute *attr,
1019 const char *buf, size_t count)
1020{
1021 struct cs42l52_private *cs42l52 = dev_get_drvdata(dev);
1022 long int time;
1023 int ret;
1024
1025 ret = kstrtol(buf, 10, &time);
1026 if (ret != 0)
1027 return ret;
1028
1029 input_event(cs42l52->beep, EV_SND, SND_TONE, time);
1030
1031 return count;
1032}
1033
1034static DEVICE_ATTR(beep, 0200, NULL, cs42l52_beep_set);
1035
1036static void cs42l52_init_beep(struct snd_soc_codec *codec)
1037{
1038 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1039 int ret;
1040
e958f8b8 1041 cs42l52->beep = devm_input_allocate_device(codec->dev);
dfe0f98b
BA		 1042 if (!cs42l52->beep) {
1043 dev_err(codec->dev, "Failed to allocate beep device\n");
1044 return;
1045 }
1046
1047 INIT_WORK(&cs42l52->beep_work, cs42l52_beep_work);
1048 cs42l52->beep_rate = 0;
1049
1050 cs42l52->beep->name = "CS42L52 Beep Generator";
1051 cs42l52->beep->phys = dev_name(codec->dev);
1052 cs42l52->beep->id.bustype = BUS_I2C;
1053
1054 cs42l52->beep->evbit[0] = BIT_MASK(EV_SND);
1055 cs42l52->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
1056 cs42l52->beep->event = cs42l52_beep_event;
1057 cs42l52->beep->dev.parent = codec->dev;
1058 input_set_drvdata(cs42l52->beep, codec);
1059
1060 ret = input_register_device(cs42l52->beep);
1061 if (ret != 0) {
dfe0f98b
BA		 1062 cs42l52->beep = NULL;
1063 dev_err(codec->dev, "Failed to register beep device\n");
1064 }
1065
1066 ret = device_create_file(codec->dev, &dev_attr_beep);
1067 if (ret != 0) {
1068 dev_err(codec->dev, "Failed to create keyclick file: %d\n",
1069 ret);
1070 }
1071}
1072
1073static void cs42l52_free_beep(struct snd_soc_codec *codec)
1074{
1075 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1076
1077 device_remove_file(codec->dev, &dev_attr_beep);
dfe0f98b
BA		 1078 cancel_work_sync(&cs42l52->beep_work);
1079 cs42l52->beep = NULL;
1080
1081 snd_soc_update_bits(codec, CS42L52_BEEP_TONE_CTL,
1082 CS42L52_BEEP_EN_MASK, 0);
1083}
1084#else
1085static void cs42l52_init_beep(struct snd_soc_codec *codec)
1086{
1087}
1088
1089static void cs42l52_free_beep(struct snd_soc_codec *codec)
1090{
1091}
1092#endif
1093
1094static int cs42l52_probe(struct snd_soc_codec *codec)
1095{
1096 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1097 int ret;
1098
1099 codec->control_data = cs42l52->regmap;
1100 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
1101 if (ret < 0) {
1102 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1103 return ret;
1104 }
1105 regcache_cache_only(cs42l52->regmap, true);
1106
1107 cs42l52_init_beep(codec);
1108
1109 cs42l52_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1110
1111 cs42l52->sysclk = CS42L52_DEFAULT_CLK;
1112 cs42l52->config.format = CS42L52_DEFAULT_FORMAT;
1113
dfe0f98b
BA		 1114 return ret;
1115}
1116
1117static int cs42l52_remove(struct snd_soc_codec *codec)
1118{
1119 cs42l52_free_beep(codec);
1120 cs42l52_set_bias_level(codec, SND_SOC_BIAS_OFF);
1121
1122 return 0;
1123}
1124
a7f44885 1125static struct snd_soc_codec_driver soc_codec_dev_cs42l52 = {
dfe0f98b
BA		 1126 .probe = cs42l52_probe,
1127 .remove = cs42l52_remove,
1128 .suspend = cs42l52_suspend,
1129 .resume = cs42l52_resume,
1130 .set_bias_level = cs42l52_set_bias_level,
1131
1132 .dapm_widgets = cs42l52_dapm_widgets,
1133 .num_dapm_widgets = ARRAY_SIZE(cs42l52_dapm_widgets),
1134 .dapm_routes = cs42l52_audio_map,
1135 .num_dapm_routes = ARRAY_SIZE(cs42l52_audio_map),
1136
1137 .controls = cs42l52_snd_controls,
1138 .num_controls = ARRAY_SIZE(cs42l52_snd_controls),
1139};
1140
1141/* Current and threshold powerup sequence Pg37 */
1142static const struct reg_default cs42l52_threshold_patch[] = {
1143
1144 { 0x00, 0x99 },
1145 { 0x3E, 0xBA },
1146 { 0x47, 0x80 },
1147 { 0x32, 0xBB },
1148 { 0x32, 0x3B },
1149 { 0x00, 0x00 },
1150
1151};
1152
1153static struct regmap_config cs42l52_regmap = {
1154 .reg_bits = 8,
1155 .val_bits = 8,
1156
1157 .max_register = CS42L52_MAX_REGISTER,
1158 .reg_defaults = cs42l52_reg_defaults,
1159 .num_reg_defaults = ARRAY_SIZE(cs42l52_reg_defaults),
1160 .readable_reg = cs42l52_readable_register,
1161 .volatile_reg = cs42l52_volatile_register,
1162 .cache_type = REGCACHE_RBTREE,
1163};
1164
1165static int cs42l52_i2c_probe(struct i2c_client *i2c_client,
1166 const struct i2c_device_id *id)
1167{
1168 struct cs42l52_private *cs42l52;
6dd17757 1169 struct cs42l52_platform_data *pdata = dev_get_platdata(&i2c_client->dev);
dfe0f98b
BA		 1170 int ret;
1171 unsigned int devid = 0;
1172 unsigned int reg;
1173
1174 cs42l52 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l52_private),
1175 GFP_KERNEL);
1176 if (cs42l52 == NULL)
1177 return -ENOMEM;
1178 cs42l52->dev = &i2c_client->dev;
1179
134b2f57 1180 cs42l52->regmap = devm_regmap_init_i2c(i2c_client, &cs42l52_regmap);
dfe0f98b
BA		 1181 if (IS_ERR(cs42l52->regmap)) {
1182 ret = PTR_ERR(cs42l52->regmap);
1183 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
134b2f57 1184 return ret;
dfe0f98b
BA		 1185 }
1186
6dd17757
BA		 1187 if (pdata)
1188 cs42l52->pdata = *pdata;
dfe0f98b 1189
6dd17757
BA		 1190 if (cs42l52->pdata.reset_gpio) {
1191 ret = gpio_request_one(cs42l52->pdata.reset_gpio,
1192 GPIOF_OUT_INIT_HIGH, "CS42L52 /RST");
1193 if (ret < 0) {
1194 dev_err(&i2c_client->dev, "Failed to request /RST %d: %d\n",
1195 cs42l52->pdata.reset_gpio, ret);
1196 return ret;
1197 }
1198 gpio_set_value_cansleep(cs42l52->pdata.reset_gpio, 0);
1199 gpio_set_value_cansleep(cs42l52->pdata.reset_gpio, 1);
1200 }
1201
1202 i2c_set_clientdata(i2c_client, cs42l52);
dfe0f98b
BA		 1203
1204 ret = regmap_register_patch(cs42l52->regmap, cs42l52_threshold_patch,
1205 ARRAY_SIZE(cs42l52_threshold_patch));
1206 if (ret != 0)
1207 dev_warn(cs42l52->dev, "Failed to apply regmap patch: %d\n",
1208 ret);
1209
1210 ret = regmap_read(cs42l52->regmap, CS42L52_CHIP, &reg);
1211 devid = reg & CS42L52_CHIP_ID_MASK;
1212 if (devid != CS42L52_CHIP_ID) {
1213 ret = -ENODEV;
1214 dev_err(&i2c_client->dev,
1215 "CS42L52 Device ID (%X). Expected %X\n",
1216 devid, CS42L52_CHIP_ID);
134b2f57 1217 return ret;
dfe0f98b
BA		 1218 }
1219
e5f03af6
BA		 1220 dev_info(&i2c_client->dev, "Cirrus Logic CS42L52, Revision: %02X\n",
1221 reg & 0xFF);
1222
153723f6
BA		 1223 /* Set Platform Data */
1224 if (cs42l52->pdata.mica_cfg)
1225 regmap_update_bits(cs42l52->regmap, CS42L52_MICA_CTL,
1226 CS42L52_MIC_CTL_TYPE_MASK,
1227 cs42l52->pdata.mica_cfg <<
1228 CS42L52_MIC_CTL_TYPE_SHIFT);
1229
1230 if (cs42l52->pdata.micb_cfg)
1231 regmap_update_bits(cs42l52->regmap, CS42L52_MICB_CTL,
1232 CS42L52_MIC_CTL_TYPE_MASK,
1233 cs42l52->pdata.micb_cfg <<
1234 CS42L52_MIC_CTL_TYPE_SHIFT);
1235
153723f6
BA		 1236 if (cs42l52->pdata.chgfreq)
1237 regmap_update_bits(cs42l52->regmap, CS42L52_CHARGE_PUMP,
1238 CS42L52_CHARGE_PUMP_MASK,
1239 cs42l52->pdata.chgfreq <<
1240 CS42L52_CHARGE_PUMP_SHIFT);
1241
1242 if (cs42l52->pdata.micbias_lvl)
1243 regmap_update_bits(cs42l52->regmap, CS42L52_IFACE_CTL2,
1244 CS42L52_IFACE_CTL2_BIAS_LVL,
1245 cs42l52->pdata.micbias_lvl);
dfe0f98b
BA		 1246
1247 ret = snd_soc_register_codec(&i2c_client->dev,
1248 &soc_codec_dev_cs42l52, &cs42l52_dai, 1);
1249 if (ret < 0)
134b2f57 1250 return ret;
dfe0f98b 1251 return 0;
dfe0f98b
BA		 1252}
1253
1254static int cs42l52_i2c_remove(struct i2c_client *client)
1255{
dfe0f98b 1256 snd_soc_unregister_codec(&client->dev);
dfe0f98b
BA		 1257 return 0;
1258}
1259
1260static const struct i2c_device_id cs42l52_id[] = {
1261 { "cs42l52", 0 },
1262 { }
1263};
1264MODULE_DEVICE_TABLE(i2c, cs42l52_id);
1265
1266static struct i2c_driver cs42l52_i2c_driver = {
1267 .driver = {
1268 .name = "cs42l52",
1269 .owner = THIS_MODULE,
1270 },
1271 .id_table = cs42l52_id,
1272 .probe = cs42l52_i2c_probe,
7a79e94e 1273 .remove = cs42l52_i2c_remove,
dfe0f98b
BA		 1274};
1275
dfe0f98b
BA		 1276module_i2c_driver(cs42l52_i2c_driver);
1277
1278MODULE_DESCRIPTION("ASoC CS42L52 driver");
1279MODULE_AUTHOR("Georgi Vlaev, Nucleus Systems Ltd, <joe@nucleusys.com>");
1280MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1281MODULE_LICENSE("GPL");
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