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ASoC: cs42l73: Add DMIC's as DAPM inputs.
[deliverable/linux.git] / sound / soc / codecs / cs42l73.c
CommitLineData
6d10c914
BA		 1/*
2 * cs42l73.c -- CS42L73 ALSA Soc Audio driver
3 *
4 * Copyright 2011 Cirrus Logic, Inc.
5 *
6 * Authors: Georgi Vlaev, Nucleus Systems Ltd, <joe@nucleusys.com>
7 * Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/delay.h>
20#include <linux/pm.h>
21#include <linux/i2c.h>
22#include <linux/regmap.h>
23#include <linux/slab.h>
24#include <sound/core.h>
25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/soc.h>
28#include <sound/soc-dapm.h>
29#include <sound/initval.h>
30#include <sound/tlv.h>
31#include "cs42l73.h"
32
33struct sp_config {
34 u8 spc, mmcc, spfs;
35 u32 srate;
36};
37struct cs42l73_private {
38 struct sp_config config[3];
39 struct regmap *regmap;
40 u32 sysclk;
41 u8 mclksel;
42 u32 mclk;
43};
44
404417e6 45static const struct reg_default cs42l73_reg_defaults[] = {
6d10c914
BA		 46 { 6, 0xF1 }, /* r06 - Power Ctl 1 */
47 { 7, 0xDF }, /* r07 - Power Ctl 2 */
48 { 8, 0x3F }, /* r08 - Power Ctl 3 */
49 { 9, 0x50 }, /* r09 - Charge Pump Freq */
50 { 10, 0x53 }, /* r0A - Output Load MicBias Short Detect */
51 { 11, 0x00 }, /* r0B - DMIC Master Clock Ctl */
52 { 12, 0x00 }, /* r0C - Aux PCM Ctl */
53 { 13, 0x15 }, /* r0D - Aux PCM Master Clock Ctl */
54 { 14, 0x00 }, /* r0E - Audio PCM Ctl */
55 { 15, 0x15 }, /* r0F - Audio PCM Master Clock Ctl */
56 { 16, 0x00 }, /* r10 - Voice PCM Ctl */
57 { 17, 0x15 }, /* r11 - Voice PCM Master Clock Ctl */
58 { 18, 0x00 }, /* r12 - Voice/Aux Sample Rate */
59 { 19, 0x06 }, /* r13 - Misc I/O Path Ctl */
60 { 20, 0x00 }, /* r14 - ADC Input Path Ctl */
61 { 21, 0x00 }, /* r15 - MICA Preamp, PGA Volume */
62 { 22, 0x00 }, /* r16 - MICB Preamp, PGA Volume */
63 { 23, 0x00 }, /* r17 - Input Path A Digital Volume */
64 { 24, 0x00 }, /* r18 - Input Path B Digital Volume */
65 { 25, 0x00 }, /* r19 - Playback Digital Ctl */
66 { 26, 0x00 }, /* r1A - HP/LO Left Digital Volume */
67 { 27, 0x00 }, /* r1B - HP/LO Right Digital Volume */
68 { 28, 0x00 }, /* r1C - Speakerphone Digital Volume */
69 { 29, 0x00 }, /* r1D - Ear/SPKLO Digital Volume */
70 { 30, 0x00 }, /* r1E - HP Left Analog Volume */
71 { 31, 0x00 }, /* r1F - HP Right Analog Volume */
72 { 32, 0x00 }, /* r20 - LO Left Analog Volume */
73 { 33, 0x00 }, /* r21 - LO Right Analog Volume */
74 { 34, 0x00 }, /* r22 - Stereo Input Path Advisory Volume */
75 { 35, 0x00 }, /* r23 - Aux PCM Input Advisory Volume */
76 { 36, 0x00 }, /* r24 - Audio PCM Input Advisory Volume */
77 { 37, 0x00 }, /* r25 - Voice PCM Input Advisory Volume */
78 { 38, 0x00 }, /* r26 - Limiter Attack Rate HP/LO */
79 { 39, 0x7F }, /* r27 - Limter Ctl, Release Rate HP/LO */
80 { 40, 0x00 }, /* r28 - Limter Threshold HP/LO */
81 { 41, 0x00 }, /* r29 - Limiter Attack Rate Speakerphone */
82 { 42, 0x3F }, /* r2A - Limter Ctl, Release Rate Speakerphone */
83 { 43, 0x00 }, /* r2B - Limter Threshold Speakerphone */
84 { 44, 0x00 }, /* r2C - Limiter Attack Rate Ear/SPKLO */
85 { 45, 0x3F }, /* r2D - Limter Ctl, Release Rate Ear/SPKLO */
86 { 46, 0x00 }, /* r2E - Limter Threshold Ear/SPKLO */
87 { 47, 0x00 }, /* r2F - ALC Enable, Attack Rate Left/Right */
88 { 48, 0x3F }, /* r30 - ALC Release Rate Left/Right */
89 { 49, 0x00 }, /* r31 - ALC Threshold Left/Right */
90 { 50, 0x00 }, /* r32 - Noise Gate Ctl Left/Right */
91 { 51, 0x00 }, /* r33 - ALC/NG Misc Ctl */
92 { 52, 0x18 }, /* r34 - Mixer Ctl */
93 { 53, 0x3F }, /* r35 - HP/LO Left Mixer Input Path Volume */
94 { 54, 0x3F }, /* r36 - HP/LO Right Mixer Input Path Volume */
95 { 55, 0x3F }, /* r37 - HP/LO Left Mixer Aux PCM Volume */
96 { 56, 0x3F }, /* r38 - HP/LO Right Mixer Aux PCM Volume */
97 { 57, 0x3F }, /* r39 - HP/LO Left Mixer Audio PCM Volume */
98 { 58, 0x3F }, /* r3A - HP/LO Right Mixer Audio PCM Volume */
99 { 59, 0x3F }, /* r3B - HP/LO Left Mixer Voice PCM Mono Volume */
100 { 60, 0x3F }, /* r3C - HP/LO Right Mixer Voice PCM Mono Volume */
101 { 61, 0x3F }, /* r3D - Aux PCM Left Mixer Input Path Volume */
102 { 62, 0x3F }, /* r3E - Aux PCM Right Mixer Input Path Volume */
103 { 63, 0x3F }, /* r3F - Aux PCM Left Mixer Volume */
104 { 64, 0x3F }, /* r40 - Aux PCM Left Mixer Volume */
105 { 65, 0x3F }, /* r41 - Aux PCM Left Mixer Audio PCM L Volume */
106 { 66, 0x3F }, /* r42 - Aux PCM Right Mixer Audio PCM R Volume */
107 { 67, 0x3F }, /* r43 - Aux PCM Left Mixer Voice PCM Volume */
108 { 68, 0x3F }, /* r44 - Aux PCM Right Mixer Voice PCM Volume */
109 { 69, 0x3F }, /* r45 - Audio PCM Left Input Path Volume */
110 { 70, 0x3F }, /* r46 - Audio PCM Right Input Path Volume */
111 { 71, 0x3F }, /* r47 - Audio PCM Left Mixer Aux PCM L Volume */
112 { 72, 0x3F }, /* r48 - Audio PCM Right Mixer Aux PCM R Volume */
113 { 73, 0x3F }, /* r49 - Audio PCM Left Mixer Volume */
114 { 74, 0x3F }, /* r4A - Audio PCM Right Mixer Volume */
115 { 75, 0x3F }, /* r4B - Audio PCM Left Mixer Voice PCM Volume */
116 { 76, 0x3F }, /* r4C - Audio PCM Right Mixer Voice PCM Volume */
117 { 77, 0x3F }, /* r4D - Voice PCM Left Input Path Volume */
118 { 78, 0x3F }, /* r4E - Voice PCM Right Input Path Volume */
119 { 79, 0x3F }, /* r4F - Voice PCM Left Mixer Aux PCM L Volume */
120 { 80, 0x3F }, /* r50 - Voice PCM Right Mixer Aux PCM R Volume */
121 { 81, 0x3F }, /* r51 - Voice PCM Left Mixer Audio PCM L Volume */
122 { 82, 0x3F }, /* r52 - Voice PCM Right Mixer Audio PCM R Volume */
123 { 83, 0x3F }, /* r53 - Voice PCM Left Mixer Voice PCM Volume */
124 { 84, 0x3F }, /* r54 - Voice PCM Right Mixer Voice PCM Volume */
125 { 85, 0xAA }, /* r55 - Mono Mixer Ctl */
126 { 86, 0x3F }, /* r56 - SPK Mono Mixer Input Path Volume */
127 { 87, 0x3F }, /* r57 - SPK Mono Mixer Aux PCM Mono/L/R Volume */
128 { 88, 0x3F }, /* r58 - SPK Mono Mixer Audio PCM Mono/L/R Volume */
129 { 89, 0x3F }, /* r59 - SPK Mono Mixer Voice PCM Mono Volume */
130 { 90, 0x3F }, /* r5A - SPKLO Mono Mixer Input Path Mono Volume */
131 { 91, 0x3F }, /* r5B - SPKLO Mono Mixer Aux Mono/L/R Volume */
132 { 92, 0x3F }, /* r5C - SPKLO Mono Mixer Audio Mono/L/R Volume */
133 { 93, 0x3F }, /* r5D - SPKLO Mono Mixer Voice Mono Volume */
134 { 94, 0x00 }, /* r5E - Interrupt Mask 1 */
135 { 95, 0x00 }, /* r5F - Interrupt Mask 2 */
136};
137
138static bool cs42l73_volatile_register(struct device *dev, unsigned int reg)
139{
140 switch (reg) {
141 case CS42L73_IS1:
142 case CS42L73_IS2:
143 return true;
144 default:
145 return false;
146 }
147}
148
149static bool cs42l73_readable_register(struct device *dev, unsigned int reg)
150{
151 switch (reg) {
152 case CS42L73_DEVID_AB:
153 case CS42L73_DEVID_CD:
154 case CS42L73_DEVID_E:
155 case CS42L73_REVID:
156 case CS42L73_PWRCTL1:
157 case CS42L73_PWRCTL2:
158 case CS42L73_PWRCTL3:
159 case CS42L73_CPFCHC:
160 case CS42L73_OLMBMSDC:
161 case CS42L73_DMMCC:
162 case CS42L73_XSPC:
163 case CS42L73_XSPMMCC:
164 case CS42L73_ASPC:
165 case CS42L73_ASPMMCC:
166 case CS42L73_VSPC:
167 case CS42L73_VSPMMCC:
168 case CS42L73_VXSPFS:
169 case CS42L73_MIOPC:
170 case CS42L73_ADCIPC:
171 case CS42L73_MICAPREPGAAVOL:
172 case CS42L73_MICBPREPGABVOL:
173 case CS42L73_IPADVOL:
174 case CS42L73_IPBDVOL:
175 case CS42L73_PBDC:
176 case CS42L73_HLADVOL:
177 case CS42L73_HLBDVOL:
178 case CS42L73_SPKDVOL:
179 case CS42L73_ESLDVOL:
180 case CS42L73_HPAAVOL:
181 case CS42L73_HPBAVOL:
182 case CS42L73_LOAAVOL:
183 case CS42L73_LOBAVOL:
184 case CS42L73_STRINV:
185 case CS42L73_XSPINV:
186 case CS42L73_ASPINV:
187 case CS42L73_VSPINV:
188 case CS42L73_LIMARATEHL:
189 case CS42L73_LIMRRATEHL:
190 case CS42L73_LMAXHL:
191 case CS42L73_LIMARATESPK:
192 case CS42L73_LIMRRATESPK:
193 case CS42L73_LMAXSPK:
194 case CS42L73_LIMARATEESL:
195 case CS42L73_LIMRRATEESL:
196 case CS42L73_LMAXESL:
197 case CS42L73_ALCARATE:
198 case CS42L73_ALCRRATE:
199 case CS42L73_ALCMINMAX:
200 case CS42L73_NGCAB:
201 case CS42L73_ALCNGMC:
202 case CS42L73_MIXERCTL:
203 case CS42L73_HLAIPAA:
204 case CS42L73_HLBIPBA:
205 case CS42L73_HLAXSPAA:
206 case CS42L73_HLBXSPBA:
207 case CS42L73_HLAASPAA:
208 case CS42L73_HLBASPBA:
209 case CS42L73_HLAVSPMA:
210 case CS42L73_HLBVSPMA:
211 case CS42L73_XSPAIPAA:
212 case CS42L73_XSPBIPBA:
213 case CS42L73_XSPAXSPAA:
214 case CS42L73_XSPBXSPBA:
215 case CS42L73_XSPAASPAA:
216 case CS42L73_XSPAASPBA:
217 case CS42L73_XSPAVSPMA:
218 case CS42L73_XSPBVSPMA:
219 case CS42L73_ASPAIPAA:
220 case CS42L73_ASPBIPBA:
221 case CS42L73_ASPAXSPAA:
222 case CS42L73_ASPBXSPBA:
223 case CS42L73_ASPAASPAA:
224 case CS42L73_ASPBASPBA:
225 case CS42L73_ASPAVSPMA:
226 case CS42L73_ASPBVSPMA:
227 case CS42L73_VSPAIPAA:
228 case CS42L73_VSPBIPBA:
229 case CS42L73_VSPAXSPAA:
230 case CS42L73_VSPBXSPBA:
231 case CS42L73_VSPAASPAA:
232 case CS42L73_VSPBASPBA:
233 case CS42L73_VSPAVSPMA:
234 case CS42L73_VSPBVSPMA:
235 case CS42L73_MMIXCTL:
236 case CS42L73_SPKMIPMA:
237 case CS42L73_SPKMXSPA:
238 case CS42L73_SPKMASPA:
239 case CS42L73_SPKMVSPMA:
240 case CS42L73_ESLMIPMA:
241 case CS42L73_ESLMXSPA:
242 case CS42L73_ESLMASPA:
243 case CS42L73_ESLMVSPMA:
244 case CS42L73_IM1:
245 case CS42L73_IM2:
246 return true;
247 default:
248 return false;
249 }
250}
251
252static const unsigned int hpaloa_tlv[] = {
253 TLV_DB_RANGE_HEAD(2),
254 0, 13, TLV_DB_SCALE_ITEM(-7600, 200, 0),
255 14, 75, TLV_DB_SCALE_ITEM(-4900, 100, 0),
256};
257
258static DECLARE_TLV_DB_SCALE(adc_boost_tlv, 0, 2500, 0);
259
260static DECLARE_TLV_DB_SCALE(hl_tlv, -10200, 50, 0);
261
262static DECLARE_TLV_DB_SCALE(ipd_tlv, -9600, 100, 0);
263
264static DECLARE_TLV_DB_SCALE(micpga_tlv, -600, 50, 0);
265
266static const unsigned int limiter_tlv[] = {
267 TLV_DB_RANGE_HEAD(2),
268 0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0),
269 3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0),
270};
271
272static const DECLARE_TLV_DB_SCALE(attn_tlv, -6300, 100, 1);
273
274static const char * const cs42l73_pgaa_text[] = { "Line A", "Mic 1" };
275static const char * const cs42l73_pgab_text[] = { "Line B", "Mic 2" };
276
277static const struct soc_enum pgaa_enum =
278 SOC_ENUM_SINGLE(CS42L73_ADCIPC, 3,
279 ARRAY_SIZE(cs42l73_pgaa_text), cs42l73_pgaa_text);
280
281static const struct soc_enum pgab_enum =
282 SOC_ENUM_SINGLE(CS42L73_ADCIPC, 7,
283 ARRAY_SIZE(cs42l73_pgab_text), cs42l73_pgab_text);
284
285static const struct snd_kcontrol_new pgaa_mux =
286 SOC_DAPM_ENUM("Left Analog Input Capture Mux", pgaa_enum);
287
288static const struct snd_kcontrol_new pgab_mux =
289 SOC_DAPM_ENUM("Right Analog Input Capture Mux", pgab_enum);
290
291static const struct snd_kcontrol_new input_left_mixer[] = {
292 SOC_DAPM_SINGLE("ADC Left Input", CS42L73_PWRCTL1,
293 5, 1, 1),
294 SOC_DAPM_SINGLE("DMIC Left Input", CS42L73_PWRCTL1,
295 4, 1, 1),
296};
297
298static const struct snd_kcontrol_new input_right_mixer[] = {
299 SOC_DAPM_SINGLE("ADC Right Input", CS42L73_PWRCTL1,
300 7, 1, 1),
301 SOC_DAPM_SINGLE("DMIC Right Input", CS42L73_PWRCTL1,
302 6, 1, 1),
303};
304
305static const char * const cs42l73_ng_delay_text[] = {
306 "50ms", "100ms", "150ms", "200ms" };
307
308static const struct soc_enum ng_delay_enum =
309 SOC_ENUM_SINGLE(CS42L73_NGCAB, 0,
310 ARRAY_SIZE(cs42l73_ng_delay_text), cs42l73_ng_delay_text);
311
312static const char * const charge_pump_freq_text[] = {
313 "0", "1", "2", "3", "4",
314 "5", "6", "7", "8", "9",
315 "10", "11", "12", "13", "14", "15" };
316
317static const struct soc_enum charge_pump_enum =
318 SOC_ENUM_SINGLE(CS42L73_CPFCHC, 4,
319 ARRAY_SIZE(charge_pump_freq_text), charge_pump_freq_text);
320
321static const char * const cs42l73_mono_mix_texts[] = {
322 "Left", "Right", "Mono Mix"};
323
324static const unsigned int cs42l73_mono_mix_values[] = { 0, 1, 2 };
325
326static const struct soc_enum spk_asp_enum =
327 SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 6, 1,
328 ARRAY_SIZE(cs42l73_mono_mix_texts),
329 cs42l73_mono_mix_texts,
330 cs42l73_mono_mix_values);
331
332static const struct snd_kcontrol_new spk_asp_mixer =
333 SOC_DAPM_ENUM("Route", spk_asp_enum);
334
335static const struct soc_enum spk_xsp_enum =
336 SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 4, 3,
337 ARRAY_SIZE(cs42l73_mono_mix_texts),
338 cs42l73_mono_mix_texts,
339 cs42l73_mono_mix_values);
340
341static const struct snd_kcontrol_new spk_xsp_mixer =
342 SOC_DAPM_ENUM("Route", spk_xsp_enum);
343
344static const struct soc_enum esl_asp_enum =
345 SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 2, 5,
346 ARRAY_SIZE(cs42l73_mono_mix_texts),
347 cs42l73_mono_mix_texts,
348 cs42l73_mono_mix_values);
349
350static const struct snd_kcontrol_new esl_asp_mixer =
351 SOC_DAPM_ENUM("Route", esl_asp_enum);
352
353static const struct soc_enum esl_xsp_enum =
354 SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 0, 7,
355 ARRAY_SIZE(cs42l73_mono_mix_texts),
356 cs42l73_mono_mix_texts,
357 cs42l73_mono_mix_values);
358
359static const struct snd_kcontrol_new esl_xsp_mixer =
360 SOC_DAPM_ENUM("Route", esl_xsp_enum);
361
362static const char * const cs42l73_ip_swap_text[] = {
363 "Stereo", "Mono A", "Mono B", "Swap A-B"};
364
365static const struct soc_enum ip_swap_enum =
366 SOC_ENUM_SINGLE(CS42L73_MIOPC, 6,
367 ARRAY_SIZE(cs42l73_ip_swap_text), cs42l73_ip_swap_text);
368
369static const char * const cs42l73_spo_mixer_text[] = {"Mono", "Stereo"};
370
371static const struct soc_enum vsp_output_mux_enum =
372 SOC_ENUM_SINGLE(CS42L73_MIXERCTL, 5,
373 ARRAY_SIZE(cs42l73_spo_mixer_text), cs42l73_spo_mixer_text);
374
375static const struct soc_enum xsp_output_mux_enum =
376 SOC_ENUM_SINGLE(CS42L73_MIXERCTL, 4,
377 ARRAY_SIZE(cs42l73_spo_mixer_text), cs42l73_spo_mixer_text);
378
379static const struct snd_kcontrol_new vsp_output_mux =
380 SOC_DAPM_ENUM("Route", vsp_output_mux_enum);
381
382static const struct snd_kcontrol_new xsp_output_mux =
383 SOC_DAPM_ENUM("Route", xsp_output_mux_enum);
384
385static const struct snd_kcontrol_new hp_amp_ctl =
386 SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 0, 1, 1);
387
388static const struct snd_kcontrol_new lo_amp_ctl =
389 SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 1, 1, 1);
390
391static const struct snd_kcontrol_new spk_amp_ctl =
392 SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 2, 1, 1);
393
394static const struct snd_kcontrol_new spklo_amp_ctl =
395 SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 4, 1, 1);
396
397static const struct snd_kcontrol_new ear_amp_ctl =
398 SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 3, 1, 1);
399
400static const struct snd_kcontrol_new cs42l73_snd_controls[] = {
401 SOC_DOUBLE_R_SX_TLV("Headphone Analog Playback Volume",
1d99f243
BA		 402 CS42L73_HPAAVOL, CS42L73_HPBAVOL, 0,
403 0x41, 0x4B, hpaloa_tlv),
6d10c914
BA		 404
405 SOC_DOUBLE_R_SX_TLV("LineOut Analog Playback Volume", CS42L73_LOAAVOL,
1d99f243 406 CS42L73_LOBAVOL, 0, 0x41, 0x4B, hpaloa_tlv),
6d10c914
BA		 407
408 SOC_DOUBLE_R_SX_TLV("Input PGA Analog Volume", CS42L73_MICAPREPGAAVOL,
1d99f243
BA		 409 CS42L73_MICBPREPGABVOL, 5, 0x34,
410 0x24, micpga_tlv),
6d10c914
BA		 411
412 SOC_DOUBLE_R("MIC Preamp Switch", CS42L73_MICAPREPGAAVOL,
413 CS42L73_MICBPREPGABVOL, 6, 1, 1),
414
415 SOC_DOUBLE_R_SX_TLV("Input Path Digital Volume", CS42L73_IPADVOL,
1d99f243 416 CS42L73_IPBDVOL, 0, 0xA0, 0x6C, ipd_tlv),
6d10c914
BA		 417
418 SOC_DOUBLE_R_SX_TLV("HL Digital Playback Volume",
1d99f243
BA		 419 CS42L73_HLADVOL, CS42L73_HLBDVOL,
420 0, 0x34, 0xE4, hl_tlv),
6d10c914
BA		 421
422 SOC_SINGLE_TLV("ADC A Boost Volume",
423 CS42L73_ADCIPC, 2, 0x01, 1, adc_boost_tlv),
424
425 SOC_SINGLE_TLV("ADC B Boost Volume",
1d99f243 426 CS42L73_ADCIPC, 6, 0x01, 1, adc_boost_tlv),
6d10c914 427
1d99f243
BA		 428 SOC_SINGLE_SX_TLV("Speakerphone Digital Volume",
429 CS42L73_SPKDVOL, 0, 0x34, 0xE4, hl_tlv),
6d10c914 430
1d99f243
BA		 431 SOC_SINGLE_SX_TLV("Ear Speaker Digital Volume",
432 CS42L73_ESLDVOL, 0, 0x34, 0xE4, hl_tlv),
6d10c914
BA		 433
434 SOC_DOUBLE_R("Headphone Analog Playback Switch", CS42L73_HPAAVOL,
435 CS42L73_HPBAVOL, 7, 1, 1),
436
437 SOC_DOUBLE_R("LineOut Analog Playback Switch", CS42L73_LOAAVOL,
438 CS42L73_LOBAVOL, 7, 1, 1),
439 SOC_DOUBLE("Input Path Digital Switch", CS42L73_ADCIPC, 0, 4, 1, 1),
440 SOC_DOUBLE("HL Digital Playback Switch", CS42L73_PBDC, 0,
441 1, 1, 1),
442 SOC_SINGLE("Speakerphone Digital Playback Switch", CS42L73_PBDC, 2, 1,
443 1),
444 SOC_SINGLE("Ear Speaker Digital Playback Switch", CS42L73_PBDC, 3, 1,
445 1),
446
447 SOC_SINGLE("PGA Soft-Ramp Switch", CS42L73_MIOPC, 3, 1, 0),
448 SOC_SINGLE("Analog Zero Cross Switch", CS42L73_MIOPC, 2, 1, 0),
449 SOC_SINGLE("Digital Soft-Ramp Switch", CS42L73_MIOPC, 1, 1, 0),
450 SOC_SINGLE("Analog Output Soft-Ramp Switch", CS42L73_MIOPC, 0, 1, 0),
451
452 SOC_DOUBLE("ADC Signal Polarity Switch", CS42L73_ADCIPC, 1, 5, 1,
453 0),
454
455 SOC_SINGLE("HL Limiter Attack Rate", CS42L73_LIMARATEHL, 0, 0x3F,
456 0),
457 SOC_SINGLE("HL Limiter Release Rate", CS42L73_LIMRRATEHL, 0,
458 0x3F, 0),
459
460
461 SOC_SINGLE("HL Limiter Switch", CS42L73_LIMRRATEHL, 7, 1, 0),
462 SOC_SINGLE("HL Limiter All Channels Switch", CS42L73_LIMRRATEHL, 6, 1,
463 0),
464
465 SOC_SINGLE_TLV("HL Limiter Max Threshold Volume", CS42L73_LMAXHL, 5, 7,
466 1, limiter_tlv),
467
468 SOC_SINGLE_TLV("HL Limiter Cushion Volume", CS42L73_LMAXHL, 2, 7, 1,
469 limiter_tlv),
470
471 SOC_SINGLE("SPK Limiter Attack Rate Volume", CS42L73_LIMARATESPK, 0,
472 0x3F, 0),
473 SOC_SINGLE("SPK Limiter Release Rate Volume", CS42L73_LIMRRATESPK, 0,
474 0x3F, 0),
475 SOC_SINGLE("SPK Limiter Switch", CS42L73_LIMRRATESPK, 7, 1, 0),
476 SOC_SINGLE("SPK Limiter All Channels Switch", CS42L73_LIMRRATESPK,
477 6, 1, 0),
478 SOC_SINGLE_TLV("SPK Limiter Max Threshold Volume", CS42L73_LMAXSPK, 5,
479 7, 1, limiter_tlv),
480
481 SOC_SINGLE_TLV("SPK Limiter Cushion Volume", CS42L73_LMAXSPK, 2, 7, 1,
482 limiter_tlv),
483
484 SOC_SINGLE("ESL Limiter Attack Rate Volume", CS42L73_LIMARATEESL, 0,
485 0x3F, 0),
486 SOC_SINGLE("ESL Limiter Release Rate Volume", CS42L73_LIMRRATEESL, 0,
487 0x3F, 0),
488 SOC_SINGLE("ESL Limiter Switch", CS42L73_LIMRRATEESL, 7, 1, 0),
489 SOC_SINGLE_TLV("ESL Limiter Max Threshold Volume", CS42L73_LMAXESL, 5,
490 7, 1, limiter_tlv),
491
492 SOC_SINGLE_TLV("ESL Limiter Cushion Volume", CS42L73_LMAXESL, 2, 7, 1,
493 limiter_tlv),
494
495 SOC_SINGLE("ALC Attack Rate Volume", CS42L73_ALCARATE, 0, 0x3F, 0),
496 SOC_SINGLE("ALC Release Rate Volume", CS42L73_ALCRRATE, 0, 0x3F, 0),
497 SOC_DOUBLE("ALC Switch", CS42L73_ALCARATE, 6, 7, 1, 0),
498 SOC_SINGLE_TLV("ALC Max Threshold Volume", CS42L73_ALCMINMAX, 5, 7, 0,
499 limiter_tlv),
500 SOC_SINGLE_TLV("ALC Min Threshold Volume", CS42L73_ALCMINMAX, 2, 7, 0,
501 limiter_tlv),
502
503 SOC_DOUBLE("NG Enable Switch", CS42L73_NGCAB, 6, 7, 1, 0),
504 SOC_SINGLE("NG Boost Switch", CS42L73_NGCAB, 5, 1, 0),
505 /*
506 NG Threshold depends on NG_BOOTSAB, which selects
507 between two threshold scales in decibels.
508 Set linear values for now ..
509 */
510 SOC_SINGLE("NG Threshold", CS42L73_NGCAB, 2, 7, 0),
511 SOC_ENUM("NG Delay", ng_delay_enum),
512
513 SOC_ENUM("Charge Pump Frequency", charge_pump_enum),
514
515 SOC_DOUBLE_R_TLV("XSP-IP Volume",
516 CS42L73_XSPAIPAA, CS42L73_XSPBIPBA, 0, 0x3F, 1,
517 attn_tlv),
518 SOC_DOUBLE_R_TLV("XSP-XSP Volume",
519 CS42L73_XSPAXSPAA, CS42L73_XSPBXSPBA, 0, 0x3F, 1,
520 attn_tlv),
521 SOC_DOUBLE_R_TLV("XSP-ASP Volume",
522 CS42L73_XSPAASPAA, CS42L73_XSPAASPBA, 0, 0x3F, 1,
523 attn_tlv),
524 SOC_DOUBLE_R_TLV("XSP-VSP Volume",
525 CS42L73_XSPAVSPMA, CS42L73_XSPBVSPMA, 0, 0x3F, 1,
526 attn_tlv),
527
528 SOC_DOUBLE_R_TLV("ASP-IP Volume",
529 CS42L73_ASPAIPAA, CS42L73_ASPBIPBA, 0, 0x3F, 1,
530 attn_tlv),
531 SOC_DOUBLE_R_TLV("ASP-XSP Volume",
532 CS42L73_ASPAXSPAA, CS42L73_ASPBXSPBA, 0, 0x3F, 1,
533 attn_tlv),
534 SOC_DOUBLE_R_TLV("ASP-ASP Volume",
535 CS42L73_ASPAASPAA, CS42L73_ASPBASPBA, 0, 0x3F, 1,
536 attn_tlv),
537 SOC_DOUBLE_R_TLV("ASP-VSP Volume",
538 CS42L73_ASPAVSPMA, CS42L73_ASPBVSPMA, 0, 0x3F, 1,
539 attn_tlv),
540
541 SOC_DOUBLE_R_TLV("VSP-IP Volume",
542 CS42L73_VSPAIPAA, CS42L73_VSPBIPBA, 0, 0x3F, 1,
543 attn_tlv),
544 SOC_DOUBLE_R_TLV("VSP-XSP Volume",
545 CS42L73_VSPAXSPAA, CS42L73_VSPBXSPBA, 0, 0x3F, 1,
546 attn_tlv),
547 SOC_DOUBLE_R_TLV("VSP-ASP Volume",
548 CS42L73_VSPAASPAA, CS42L73_VSPBASPBA, 0, 0x3F, 1,
549 attn_tlv),
550 SOC_DOUBLE_R_TLV("VSP-VSP Volume",
551 CS42L73_VSPAVSPMA, CS42L73_VSPBVSPMA, 0, 0x3F, 1,
552 attn_tlv),
553
554 SOC_DOUBLE_R_TLV("HL-IP Volume",
555 CS42L73_HLAIPAA, CS42L73_HLBIPBA, 0, 0x3F, 1,
556 attn_tlv),
557 SOC_DOUBLE_R_TLV("HL-XSP Volume",
558 CS42L73_HLAXSPAA, CS42L73_HLBXSPBA, 0, 0x3F, 1,
559 attn_tlv),
560 SOC_DOUBLE_R_TLV("HL-ASP Volume",
561 CS42L73_HLAASPAA, CS42L73_HLBASPBA, 0, 0x3F, 1,
562 attn_tlv),
563 SOC_DOUBLE_R_TLV("HL-VSP Volume",
564 CS42L73_HLAVSPMA, CS42L73_HLBVSPMA, 0, 0x3F, 1,
565 attn_tlv),
566
567 SOC_SINGLE_TLV("SPK-IP Mono Volume",
5807c3bf 568 CS42L73_SPKMIPMA, 0, 0x3F, 1, attn_tlv),
6d10c914 569 SOC_SINGLE_TLV("SPK-XSP Mono Volume",
5807c3bf 570 CS42L73_SPKMXSPA, 0, 0x3F, 1, attn_tlv),
6d10c914 571 SOC_SINGLE_TLV("SPK-ASP Mono Volume",
5807c3bf 572 CS42L73_SPKMASPA, 0, 0x3F, 1, attn_tlv),
6d10c914 573 SOC_SINGLE_TLV("SPK-VSP Mono Volume",
5807c3bf 574 CS42L73_SPKMVSPMA, 0, 0x3F, 1, attn_tlv),
6d10c914
BA		 575
576 SOC_SINGLE_TLV("ESL-IP Mono Volume",
5807c3bf 577 CS42L73_ESLMIPMA, 0, 0x3F, 1, attn_tlv),
6d10c914 578 SOC_SINGLE_TLV("ESL-XSP Mono Volume",
5807c3bf 579 CS42L73_ESLMXSPA, 0, 0x3F, 1, attn_tlv),
6d10c914 580 SOC_SINGLE_TLV("ESL-ASP Mono Volume",
5807c3bf 581 CS42L73_ESLMASPA, 0, 0x3F, 1, attn_tlv),
6d10c914 582 SOC_SINGLE_TLV("ESL-VSP Mono Volume",
5807c3bf 583 CS42L73_ESLMVSPMA, 0, 0x3F, 1, attn_tlv),
6d10c914
BA		 584
585 SOC_ENUM("IP Digital Swap/Mono Select", ip_swap_enum),
586
587 SOC_ENUM("VSPOUT Mono/Stereo Select", vsp_output_mux_enum),
588 SOC_ENUM("XSPOUT Mono/Stereo Select", xsp_output_mux_enum),
589};
590
591static const struct snd_soc_dapm_widget cs42l73_dapm_widgets[] = {
a1ad500e
PH		 592 SND_SOC_DAPM_INPUT("DMICA"),
593 SND_SOC_DAPM_INPUT("DMICB"),
6d10c914
BA		 594 SND_SOC_DAPM_INPUT("LINEINA"),
595 SND_SOC_DAPM_INPUT("LINEINB"),
596 SND_SOC_DAPM_INPUT("MIC1"),
597 SND_SOC_DAPM_SUPPLY("MIC1 Bias", CS42L73_PWRCTL2, 6, 1, NULL, 0),
598 SND_SOC_DAPM_INPUT("MIC2"),
599 SND_SOC_DAPM_SUPPLY("MIC2 Bias", CS42L73_PWRCTL2, 7, 1, NULL, 0),
600
33d0188c 601 SND_SOC_DAPM_AIF_OUT("XSPOUTL", NULL, 0,
6d10c914 602 CS42L73_PWRCTL2, 1, 1),
33d0188c 603 SND_SOC_DAPM_AIF_OUT("XSPOUTR", NULL, 0,
6d10c914 604 CS42L73_PWRCTL2, 1, 1),
33d0188c 605 SND_SOC_DAPM_AIF_OUT("ASPOUTL", NULL, 0,
6d10c914 606 CS42L73_PWRCTL2, 3, 1),
33d0188c 607 SND_SOC_DAPM_AIF_OUT("ASPOUTR", NULL, 0,
6d10c914 608 CS42L73_PWRCTL2, 3, 1),
33d0188c 609 SND_SOC_DAPM_AIF_OUT("VSPOUTL", NULL, 0,
6d10c914 610 CS42L73_PWRCTL2, 4, 1),
33d0188c 611 SND_SOC_DAPM_AIF_OUT("VSPOUTR", NULL, 0,
6d10c914
BA		 612 CS42L73_PWRCTL2, 4, 1),
613
614 SND_SOC_DAPM_PGA("PGA Left", SND_SOC_NOPM, 0, 0, NULL, 0),
615 SND_SOC_DAPM_PGA("PGA Right", SND_SOC_NOPM, 0, 0, NULL, 0),
616
617 SND_SOC_DAPM_MUX("PGA Left Mux", SND_SOC_NOPM, 0, 0, &pgaa_mux),
618 SND_SOC_DAPM_MUX("PGA Right Mux", SND_SOC_NOPM, 0, 0, &pgab_mux),
619
620 SND_SOC_DAPM_ADC("ADC Left", NULL, CS42L73_PWRCTL1, 7, 1),
621 SND_SOC_DAPM_ADC("ADC Right", NULL, CS42L73_PWRCTL1, 5, 1),
622 SND_SOC_DAPM_ADC("DMIC Left", NULL, CS42L73_PWRCTL1, 6, 1),
623 SND_SOC_DAPM_ADC("DMIC Right", NULL, CS42L73_PWRCTL1, 4, 1),
624
625 SND_SOC_DAPM_MIXER_NAMED_CTL("Input Left Capture", SND_SOC_NOPM,
626 0, 0, input_left_mixer,
627 ARRAY_SIZE(input_left_mixer)),
628
629 SND_SOC_DAPM_MIXER_NAMED_CTL("Input Right Capture", SND_SOC_NOPM,
630 0, 0, input_right_mixer,
631 ARRAY_SIZE(input_right_mixer)),
632
633 SND_SOC_DAPM_MIXER("ASPL Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
634 SND_SOC_DAPM_MIXER("ASPR Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
635 SND_SOC_DAPM_MIXER("XSPL Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
636 SND_SOC_DAPM_MIXER("XSPR Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
637 SND_SOC_DAPM_MIXER("VSPL Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
638 SND_SOC_DAPM_MIXER("VSPR Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
639
33d0188c 640 SND_SOC_DAPM_AIF_IN("XSPINL", NULL, 0,
6d10c914 641 CS42L73_PWRCTL2, 0, 1),
33d0188c 642 SND_SOC_DAPM_AIF_IN("XSPINR", NULL, 0,
6d10c914 643 CS42L73_PWRCTL2, 0, 1),
33d0188c 644 SND_SOC_DAPM_AIF_IN("XSPINM", NULL, 0,
6d10c914
BA		 645 CS42L73_PWRCTL2, 0, 1),
646
33d0188c 647 SND_SOC_DAPM_AIF_IN("ASPINL", NULL, 0,
6d10c914 648 CS42L73_PWRCTL2, 2, 1),
33d0188c 649 SND_SOC_DAPM_AIF_IN("ASPINR", NULL, 0,
6d10c914 650 CS42L73_PWRCTL2, 2, 1),
33d0188c 651 SND_SOC_DAPM_AIF_IN("ASPINM", NULL, 0,
6d10c914
BA		 652 CS42L73_PWRCTL2, 2, 1),
653
33d0188c 654 SND_SOC_DAPM_AIF_IN("VSPIN", NULL, 0,
6d10c914
BA		 655 CS42L73_PWRCTL2, 4, 1),
656
657 SND_SOC_DAPM_MIXER("HL Left Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
658 SND_SOC_DAPM_MIXER("HL Right Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
659 SND_SOC_DAPM_MIXER("SPK Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
660 SND_SOC_DAPM_MIXER("ESL Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
661
662 SND_SOC_DAPM_MUX("ESL-XSP Mux", SND_SOC_NOPM,
663 0, 0, &esl_xsp_mixer),
664
665 SND_SOC_DAPM_MUX("ESL-ASP Mux", SND_SOC_NOPM,
666 0, 0, &esl_asp_mixer),
667
668 SND_SOC_DAPM_MUX("SPK-ASP Mux", SND_SOC_NOPM,
669 0, 0, &spk_asp_mixer),
670
671 SND_SOC_DAPM_MUX("SPK-XSP Mux", SND_SOC_NOPM,
672 0, 0, &spk_xsp_mixer),
673
674 SND_SOC_DAPM_PGA("HL Left DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
675 SND_SOC_DAPM_PGA("HL Right DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
676 SND_SOC_DAPM_PGA("SPK DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
677 SND_SOC_DAPM_PGA("ESL DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
678
679 SND_SOC_DAPM_SWITCH("HP Amp", CS42L73_PWRCTL3, 0, 1,
680 &hp_amp_ctl),
681 SND_SOC_DAPM_SWITCH("LO Amp", CS42L73_PWRCTL3, 1, 1,
682 &lo_amp_ctl),
683 SND_SOC_DAPM_SWITCH("SPK Amp", CS42L73_PWRCTL3, 2, 1,
684 &spk_amp_ctl),
685 SND_SOC_DAPM_SWITCH("EAR Amp", CS42L73_PWRCTL3, 3, 1,
686 &ear_amp_ctl),
687 SND_SOC_DAPM_SWITCH("SPKLO Amp", CS42L73_PWRCTL3, 4, 1,
688 &spklo_amp_ctl),
689
690 SND_SOC_DAPM_OUTPUT("HPOUTA"),
691 SND_SOC_DAPM_OUTPUT("HPOUTB"),
692 SND_SOC_DAPM_OUTPUT("LINEOUTA"),
693 SND_SOC_DAPM_OUTPUT("LINEOUTB"),
694 SND_SOC_DAPM_OUTPUT("EAROUT"),
695 SND_SOC_DAPM_OUTPUT("SPKOUT"),
696 SND_SOC_DAPM_OUTPUT("SPKLINEOUT"),
697};
698
699static const struct snd_soc_dapm_route cs42l73_audio_map[] = {
700
701 /* SPKLO EARSPK Paths */
702 {"EAROUT", NULL, "EAR Amp"},
703 {"SPKLINEOUT", NULL, "SPKLO Amp"},
704
705 {"EAR Amp", "Switch", "ESL DAC"},
706 {"SPKLO Amp", "Switch", "ESL DAC"},
707
708 {"ESL DAC", "ESL-ASP Mono Volume", "ESL Mixer"},
709 {"ESL DAC", "ESL-XSP Mono Volume", "ESL Mixer"},
710 {"ESL DAC", "ESL-VSP Mono Volume", "VSPIN"},
711 /* Loopback */
712 {"ESL DAC", "ESL-IP Mono Volume", "Input Left Capture"},
713 {"ESL DAC", "ESL-IP Mono Volume", "Input Right Capture"},
714
715 {"ESL Mixer", NULL, "ESL-ASP Mux"},
716 {"ESL Mixer", NULL, "ESL-XSP Mux"},
717
718 {"ESL-ASP Mux", "Left", "ASPINL"},
719 {"ESL-ASP Mux", "Right", "ASPINR"},
720 {"ESL-ASP Mux", "Mono Mix", "ASPINM"},
721
722 {"ESL-XSP Mux", "Left", "XSPINL"},
723 {"ESL-XSP Mux", "Right", "XSPINR"},
724 {"ESL-XSP Mux", "Mono Mix", "XSPINM"},
725
726 /* Speakerphone Paths */
727 {"SPKOUT", NULL, "SPK Amp"},
728 {"SPK Amp", "Switch", "SPK DAC"},
729
730 {"SPK DAC", "SPK-ASP Mono Volume", "SPK Mixer"},
731 {"SPK DAC", "SPK-XSP Mono Volume", "SPK Mixer"},
732 {"SPK DAC", "SPK-VSP Mono Volume", "VSPIN"},
733 /* Loopback */
734 {"SPK DAC", "SPK-IP Mono Volume", "Input Left Capture"},
735 {"SPK DAC", "SPK-IP Mono Volume", "Input Right Capture"},
736
737 {"SPK Mixer", NULL, "SPK-ASP Mux"},
738 {"SPK Mixer", NULL, "SPK-XSP Mux"},
739
740 {"SPK-ASP Mux", "Left", "ASPINL"},
741 {"SPK-ASP Mux", "Mono Mix", "ASPINM"},
742 {"SPK-ASP Mux", "Right", "ASPINR"},
743
744 {"SPK-XSP Mux", "Left", "XSPINL"},
745 {"SPK-XSP Mux", "Mono Mix", "XSPINM"},
746 {"SPK-XSP Mux", "Right", "XSPINR"},
747
748 /* HP LineOUT Paths */
749 {"HPOUTA", NULL, "HP Amp"},
750 {"HPOUTB", NULL, "HP Amp"},
751 {"LINEOUTA", NULL, "LO Amp"},
752 {"LINEOUTB", NULL, "LO Amp"},
753
754 {"HP Amp", "Switch", "HL Left DAC"},
755 {"HP Amp", "Switch", "HL Right DAC"},
756 {"LO Amp", "Switch", "HL Left DAC"},
757 {"LO Amp", "Switch", "HL Right DAC"},
758
759 {"HL Left DAC", "HL-XSP Volume", "HL Left Mixer"},
760 {"HL Right DAC", "HL-XSP Volume", "HL Right Mixer"},
761 {"HL Left DAC", "HL-ASP Volume", "HL Left Mixer"},
762 {"HL Right DAC", "HL-ASP Volume", "HL Right Mixer"},
763 {"HL Left DAC", "HL-VSP Volume", "HL Left Mixer"},
764 {"HL Right DAC", "HL-VSP Volume", "HL Right Mixer"},
765 /* Loopback */
766 {"HL Left DAC", "HL-IP Volume", "HL Left Mixer"},
767 {"HL Right DAC", "HL-IP Volume", "HL Right Mixer"},
768 {"HL Left Mixer", NULL, "Input Left Capture"},
769 {"HL Right Mixer", NULL, "Input Right Capture"},
770
771 {"HL Left Mixer", NULL, "ASPINL"},
772 {"HL Right Mixer", NULL, "ASPINR"},
773 {"HL Left Mixer", NULL, "XSPINL"},
774 {"HL Right Mixer", NULL, "XSPINR"},
775 {"HL Left Mixer", NULL, "VSPIN"},
776 {"HL Right Mixer", NULL, "VSPIN"},
777
33d0188c
BA		 778 {"ASPINL", NULL, "ASP Playback"},
779 {"ASPINM", NULL, "ASP Playback"},
780 {"ASPINR", NULL, "ASP Playback"},
781 {"XSPINL", NULL, "XSP Playback"},
782 {"XSPINM", NULL, "XSP Playback"},
783 {"XSPINR", NULL, "XSP Playback"},
784 {"VSPIN", NULL, "VSP Playback"},
785
6d10c914
BA		 786 /* Capture Paths */
787 {"MIC1", NULL, "MIC1 Bias"},
788 {"PGA Left Mux", "Mic 1", "MIC1"},
789 {"MIC2", NULL, "MIC2 Bias"},
790 {"PGA Right Mux", "Mic 2", "MIC2"},
791
792 {"PGA Left Mux", "Line A", "LINEINA"},
793 {"PGA Right Mux", "Line B", "LINEINB"},
794
795 {"PGA Left", NULL, "PGA Left Mux"},
796 {"PGA Right", NULL, "PGA Right Mux"},
797
798 {"ADC Left", NULL, "PGA Left"},
799 {"ADC Right", NULL, "PGA Right"},
a1ad500e
PH		 800 {"DMIC Left", NULL, "DMICA"},
801 {"DMIC Right", NULL, "DMICB"},
6d10c914
BA		 802
803 {"Input Left Capture", "ADC Left Input", "ADC Left"},
804 {"Input Right Capture", "ADC Right Input", "ADC Right"},
805 {"Input Left Capture", "DMIC Left Input", "DMIC Left"},
806 {"Input Right Capture", "DMIC Right Input", "DMIC Right"},
807
808 /* Audio Capture */
809 {"ASPL Output Mixer", NULL, "Input Left Capture"},
810 {"ASPR Output Mixer", NULL, "Input Right Capture"},
811
812 {"ASPOUTL", "ASP-IP Volume", "ASPL Output Mixer"},
813 {"ASPOUTR", "ASP-IP Volume", "ASPR Output Mixer"},
814
815 /* Auxillary Capture */
816 {"XSPL Output Mixer", NULL, "Input Left Capture"},
817 {"XSPR Output Mixer", NULL, "Input Right Capture"},
818
819 {"XSPOUTL", "XSP-IP Volume", "XSPL Output Mixer"},
820 {"XSPOUTR", "XSP-IP Volume", "XSPR Output Mixer"},
821
822 {"XSPOUTL", NULL, "XSPL Output Mixer"},
823 {"XSPOUTR", NULL, "XSPR Output Mixer"},
824
825 /* Voice Capture */
826 {"VSPL Output Mixer", NULL, "Input Left Capture"},
827 {"VSPR Output Mixer", NULL, "Input Left Capture"},
828
829 {"VSPOUTL", "VSP-IP Volume", "VSPL Output Mixer"},
830 {"VSPOUTR", "VSP-IP Volume", "VSPR Output Mixer"},
831
832 {"VSPOUTL", NULL, "VSPL Output Mixer"},
833 {"VSPOUTR", NULL, "VSPR Output Mixer"},
33d0188c
BA		 834
835 {"ASP Capture", NULL, "ASPOUTL"},
836 {"ASP Capture", NULL, "ASPOUTR"},
837 {"XSP Capture", NULL, "XSPOUTL"},
838 {"XSP Capture", NULL, "XSPOUTR"},
839 {"VSP Capture", NULL, "VSPOUTL"},
840 {"VSP Capture", NULL, "VSPOUTR"},
6d10c914
BA		 841};
842
843struct cs42l73_mclk_div {
844 u32 mclk;
845 u32 srate;
846 u8 mmcc;
847};
848
849static struct cs42l73_mclk_div cs42l73_mclk_coeffs[] = {
850 /* MCLK, Sample Rate, xMMCC[5:0] */
851 {5644800, 11025, 0x30},
852 {5644800, 22050, 0x20},
853 {5644800, 44100, 0x10},
854
855 {6000000, 8000, 0x39},
856 {6000000, 11025, 0x33},
857 {6000000, 12000, 0x31},
858 {6000000, 16000, 0x29},
859 {6000000, 22050, 0x23},
860 {6000000, 24000, 0x21},
861 {6000000, 32000, 0x19},
862 {6000000, 44100, 0x13},
863 {6000000, 48000, 0x11},
864
865 {6144000, 8000, 0x38},
866 {6144000, 12000, 0x30},
867 {6144000, 16000, 0x28},
868 {6144000, 24000, 0x20},
869 {6144000, 32000, 0x18},
870 {6144000, 48000, 0x10},
871
872 {6500000, 8000, 0x3C},
873 {6500000, 11025, 0x35},
874 {6500000, 12000, 0x34},
875 {6500000, 16000, 0x2C},
876 {6500000, 22050, 0x25},
877 {6500000, 24000, 0x24},
878 {6500000, 32000, 0x1C},
879 {6500000, 44100, 0x15},
880 {6500000, 48000, 0x14},
881
882 {6400000, 8000, 0x3E},
883 {6400000, 11025, 0x37},
884 {6400000, 12000, 0x36},
885 {6400000, 16000, 0x2E},
886 {6400000, 22050, 0x27},
887 {6400000, 24000, 0x26},
888 {6400000, 32000, 0x1E},
889 {6400000, 44100, 0x17},
890 {6400000, 48000, 0x16},
891};
892
893struct cs42l73_mclkx_div {
894 u32 mclkx;
895 u8 ratio;
896 u8 mclkdiv;
897};
898
899static struct cs42l73_mclkx_div cs42l73_mclkx_coeffs[] = {
900 {5644800, 1, 0}, /* 5644800 */
901 {6000000, 1, 0}, /* 6000000 */
902 {6144000, 1, 0}, /* 6144000 */
903 {11289600, 2, 2}, /* 5644800 */
904 {12288000, 2, 2}, /* 6144000 */
905 {12000000, 2, 2}, /* 6000000 */
906 {13000000, 2, 2}, /* 6500000 */
907 {19200000, 3, 3}, /* 6400000 */
908 {24000000, 4, 4}, /* 6000000 */
909 {26000000, 4, 4}, /* 6500000 */
910 {38400000, 6, 5} /* 6400000 */
911};
912
913static int cs42l73_get_mclkx_coeff(int mclkx)
914{
915 int i;
916
917 for (i = 0; i < ARRAY_SIZE(cs42l73_mclkx_coeffs); i++) {
918 if (cs42l73_mclkx_coeffs[i].mclkx == mclkx)
919 return i;
920 }
921 return -EINVAL;
922}
923
924static int cs42l73_get_mclk_coeff(int mclk, int srate)
925{
926 int i;
927
928 for (i = 0; i < ARRAY_SIZE(cs42l73_mclk_coeffs); i++) {
929 if (cs42l73_mclk_coeffs[i].mclk == mclk &&
930 cs42l73_mclk_coeffs[i].srate == srate)
931 return i;
932 }
933 return -EINVAL;
934
935}
936
937static int cs42l73_set_mclk(struct snd_soc_dai *dai, unsigned int freq)
938{
939 struct snd_soc_codec *codec = dai->codec;
940 struct cs42l73_private *priv = snd_soc_codec_get_drvdata(codec);
941
942 int mclkx_coeff;
943 u32 mclk = 0;
944 u8 dmmcc = 0;
945
946 /* MCLKX -> MCLK */
947 mclkx_coeff = cs42l73_get_mclkx_coeff(freq);
86fc4998
JJ		 948 if (mclkx_coeff < 0)
949 return mclkx_coeff;
6d10c914
BA		 950
951 mclk = cs42l73_mclkx_coeffs[mclkx_coeff].mclkx /
952 cs42l73_mclkx_coeffs[mclkx_coeff].ratio;
953
954 dev_dbg(codec->dev, "MCLK%u %u <-> internal MCLK %u\n",
955 priv->mclksel + 1, cs42l73_mclkx_coeffs[mclkx_coeff].mclkx,
956 mclk);
957
958 dmmcc = (priv->mclksel << 4) |
959 (cs42l73_mclkx_coeffs[mclkx_coeff].mclkdiv << 1);
960
961 snd_soc_write(codec, CS42L73_DMMCC, dmmcc);
962
963 priv->sysclk = mclkx_coeff;
964 priv->mclk = mclk;
965
966 return 0;
967}
968
969static int cs42l73_set_sysclk(struct snd_soc_dai *dai,
970 int clk_id, unsigned int freq, int dir)
971{
972 struct snd_soc_codec *codec = dai->codec;
973 struct cs42l73_private *priv = snd_soc_codec_get_drvdata(codec);
974
975 switch (clk_id) {
976 case CS42L73_CLKID_MCLK1:
977 break;
978 case CS42L73_CLKID_MCLK2:
979 break;
980 default:
981 return -EINVAL;
982 }
983
984 if ((cs42l73_set_mclk(dai, freq)) < 0) {
985 dev_err(codec->dev, "Unable to set MCLK for dai %s\n",
986 dai->name);
987 return -EINVAL;
988 }
989
990 priv->mclksel = clk_id;
991
992 return 0;
993}
994
995static int cs42l73_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
996{
997 struct snd_soc_codec *codec = codec_dai->codec;
998 struct cs42l73_private *priv = snd_soc_codec_get_drvdata(codec);
999 u8 id = codec_dai->id;
dbb1f516 1000 unsigned int inv, format;
6d10c914
BA		 1001 u8 spc, mmcc;
1002
1003 spc = snd_soc_read(codec, CS42L73_SPC(id));
1004 mmcc = snd_soc_read(codec, CS42L73_MMCC(id));
1005
1006 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1007 case SND_SOC_DAIFMT_CBM_CFM:
1008 mmcc |= MS_MASTER;
1009 break;
1010
1011 case SND_SOC_DAIFMT_CBS_CFS:
1012 mmcc &= ~MS_MASTER;
1013 break;
1014
1015 default:
1016 return -EINVAL;
1017 }
1018
1019 format = (fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1020 inv = (fmt & SND_SOC_DAIFMT_INV_MASK);
1021
1022 switch (format) {
1023 case SND_SOC_DAIFMT_I2S:
1024 spc &= ~SPDIF_PCM;
1025 break;
1026 case SND_SOC_DAIFMT_DSP_A:
1027 case SND_SOC_DAIFMT_DSP_B:
1028 if (mmcc & MS_MASTER) {
1029 dev_err(codec->dev,
1030 "PCM format in slave mode only\n");
1031 return -EINVAL;
1032 }
1033 if (id == CS42L73_ASP) {
1034 dev_err(codec->dev,
1035 "PCM format is not supported on ASP port\n");
1036 return -EINVAL;
1037 }
1038 spc |= SPDIF_PCM;
1039 break;
1040 default:
1041 return -EINVAL;
1042 }
1043
1044 if (spc & SPDIF_PCM) {
7b282cbb
AL		 1045 /* Clear PCM mode, clear PCM_BIT_ORDER bit for MSB->LSB */
1046 spc &= ~(PCM_MODE_MASK | PCM_BIT_ORDER);
6d10c914
BA		 1047 switch (format) {
1048 case SND_SOC_DAIFMT_DSP_B:
1049 if (inv == SND_SOC_DAIFMT_IB_IF)
717b8fae 1050 spc |= PCM_MODE0;
6d10c914 1051 if (inv == SND_SOC_DAIFMT_IB_NF)
717b8fae 1052 spc |= PCM_MODE1;
6d10c914
BA		 1053 break;
1054 case SND_SOC_DAIFMT_DSP_A:
1055 if (inv == SND_SOC_DAIFMT_IB_IF)
717b8fae 1056 spc |= PCM_MODE1;
6d10c914
BA		 1057 break;
1058 default:
1059 return -EINVAL;
1060 }
1061 }
1062
1063 priv->config[id].spc = spc;
1064 priv->config[id].mmcc = mmcc;
1065
1066 return 0;
1067}
1068
1069static u32 cs42l73_asrc_rates[] = {
1070 8000, 11025, 12000, 16000, 22050,
1071 24000, 32000, 44100, 48000
1072};
1073
1074static unsigned int cs42l73_get_xspfs_coeff(u32 rate)
1075{
1076 int i;
1077 for (i = 0; i < ARRAY_SIZE(cs42l73_asrc_rates); i++) {
1078 if (cs42l73_asrc_rates[i] == rate)
1079 return i + 1;
1080 }
1081 return 0; /* 0 = Don't know */
1082}
1083
1084static void cs42l73_update_asrc(struct snd_soc_codec *codec, int id, int srate)
1085{
1086 u8 spfs = 0;
1087
1088 if (srate > 0)
1089 spfs = cs42l73_get_xspfs_coeff(srate);
1090
1091 switch (id) {
1092 case CS42L73_XSP:
1093 snd_soc_update_bits(codec, CS42L73_VXSPFS, 0x0f, spfs);
1094 break;
1095 case CS42L73_ASP:
1096 snd_soc_update_bits(codec, CS42L73_ASPC, 0x3c, spfs << 2);
1097 break;
1098 case CS42L73_VSP:
1099 snd_soc_update_bits(codec, CS42L73_VXSPFS, 0xf0, spfs << 4);
1100 break;
1101 default:
1102 break;
1103 }
1104}
1105
1106static int cs42l73_pcm_hw_params(struct snd_pcm_substream *substream,
1107 struct snd_pcm_hw_params *params,
1108 struct snd_soc_dai *dai)
1109{
e6968a17 1110 struct snd_soc_codec *codec = dai->codec;
6d10c914
BA		 1111 struct cs42l73_private *priv = snd_soc_codec_get_drvdata(codec);
1112 int id = dai->id;
1113 int mclk_coeff;
1114 int srate = params_rate(params);
1115
1116 if (priv->config[id].mmcc & MS_MASTER) {
1117 /* CS42L73 Master */
1118 /* MCLK -> srate */
1119 mclk_coeff =
1120 cs42l73_get_mclk_coeff(priv->mclk, srate);
1121
1122 if (mclk_coeff < 0)
1123 return -EINVAL;
1124
1125 dev_dbg(codec->dev,
1126 "DAI[%d]: MCLK %u, srate %u, MMCC[5:0] = %x\n",
1127 id, priv->mclk, srate,
1128 cs42l73_mclk_coeffs[mclk_coeff].mmcc);
1129
1130 priv->config[id].mmcc &= 0xC0;
1131 priv->config[id].mmcc |= cs42l73_mclk_coeffs[mclk_coeff].mmcc;
1132 priv->config[id].spc &= 0xFC;
44bed483 1133 priv->config[id].spc |= MCK_SCLK_MCLK;
6d10c914
BA		 1134 } else {
1135 /* CS42L73 Slave */
1136 priv->config[id].spc &= 0xFC;
1137 priv->config[id].spc |= MCK_SCLK_64FS;
1138 }
1139 /* Update ASRCs */
1140 priv->config[id].srate = srate;
1141
1142 snd_soc_write(codec, CS42L73_SPC(id), priv->config[id].spc);
1143 snd_soc_write(codec, CS42L73_MMCC(id), priv->config[id].mmcc);
1144
1145 cs42l73_update_asrc(codec, id, srate);
1146
1147 return 0;
1148}
1149
1150static int cs42l73_set_bias_level(struct snd_soc_codec *codec,
1151 enum snd_soc_bias_level level)
1152{
1153 struct cs42l73_private *cs42l73 = snd_soc_codec_get_drvdata(codec);
1154
1155 switch (level) {
1156 case SND_SOC_BIAS_ON:
1157 snd_soc_update_bits(codec, CS42L73_DMMCC, MCLKDIS, 0);
1158 snd_soc_update_bits(codec, CS42L73_PWRCTL1, PDN, 0);
1159 break;
1160
1161 case SND_SOC_BIAS_PREPARE:
1162 break;
1163
1164 case SND_SOC_BIAS_STANDBY:
1165 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1166 regcache_cache_only(cs42l73->regmap, false);
1167 regcache_sync(cs42l73->regmap);
1168 }
1169 snd_soc_update_bits(codec, CS42L73_PWRCTL1, PDN, 1);
1170 break;
1171
1172 case SND_SOC_BIAS_OFF:
1173 snd_soc_update_bits(codec, CS42L73_PWRCTL1, PDN, 1);
1174 snd_soc_update_bits(codec, CS42L73_DMMCC, MCLKDIS, 1);
1175 break;
1176 }
1177 codec->dapm.bias_level = level;
1178 return 0;
1179}
1180
1181static int cs42l73_set_tristate(struct snd_soc_dai *dai, int tristate)
1182{
1183 struct snd_soc_codec *codec = dai->codec;
1184 int id = dai->id;
1185
1186 return snd_soc_update_bits(codec, CS42L73_SPC(id),
1187 0x7F, tristate << 7);
1188}
1189
1190static struct snd_pcm_hw_constraint_list constraints_12_24 = {
1191 .count = ARRAY_SIZE(cs42l73_asrc_rates),
1192 .list = cs42l73_asrc_rates,
1193};
1194
1195static int cs42l73_pcm_startup(struct snd_pcm_substream *substream,
1196 struct snd_soc_dai *dai)
1197{
1198 snd_pcm_hw_constraint_list(substream->runtime, 0,
1199 SNDRV_PCM_HW_PARAM_RATE,
1200 &constraints_12_24);
1201 return 0;
1202}
1203
1204/* SNDRV_PCM_RATE_KNOT -> 12000, 24000 Hz, limit with constraint list */
1205#define CS42L73_RATES (SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_KNOT)
1206
1207
1208#define CS42L73_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1209 SNDRV_PCM_FMTBIT_S24_LE)
1210
890754a8 1211static const struct snd_soc_dai_ops cs42l73_ops = {
6d10c914
BA		 1212 .startup = cs42l73_pcm_startup,
1213 .hw_params = cs42l73_pcm_hw_params,
1214 .set_fmt = cs42l73_set_dai_fmt,
1215 .set_sysclk = cs42l73_set_sysclk,
1216 .set_tristate = cs42l73_set_tristate,
1217};
1218
1219static struct snd_soc_dai_driver cs42l73_dai[] = {
1220 {
1221 .name = "cs42l73-xsp",
1222 .id = CS42L73_XSP,
1223 .playback = {
1224 .stream_name = "XSP Playback",
1225 .channels_min = 1,
1226 .channels_max = 2,
1227 .rates = CS42L73_RATES,
1228 .formats = CS42L73_FORMATS,
1229 },
1230 .capture = {
1231 .stream_name = "XSP Capture",
1232 .channels_min = 1,
1233 .channels_max = 2,
1234 .rates = CS42L73_RATES,
1235 .formats = CS42L73_FORMATS,
1236 },
1237 .ops = &cs42l73_ops,
1238 .symmetric_rates = 1,
1239 },
1240 {
1241 .name = "cs42l73-asp",
1242 .id = CS42L73_ASP,
1243 .playback = {
1244 .stream_name = "ASP Playback",
1245 .channels_min = 2,
1246 .channels_max = 2,
1247 .rates = CS42L73_RATES,
1248 .formats = CS42L73_FORMATS,
1249 },
1250 .capture = {
1251 .stream_name = "ASP Capture",
1252 .channels_min = 2,
1253 .channels_max = 2,
1254 .rates = CS42L73_RATES,
1255 .formats = CS42L73_FORMATS,
1256 },
1257 .ops = &cs42l73_ops,
1258 .symmetric_rates = 1,
1259 },
1260 {
1261 .name = "cs42l73-vsp",
1262 .id = CS42L73_VSP,
1263 .playback = {
1264 .stream_name = "VSP Playback",
1265 .channels_min = 1,
1266 .channels_max = 2,
1267 .rates = CS42L73_RATES,
1268 .formats = CS42L73_FORMATS,
1269 },
1270 .capture = {
1271 .stream_name = "VSP Capture",
1272 .channels_min = 1,
1273 .channels_max = 2,
1274 .rates = CS42L73_RATES,
1275 .formats = CS42L73_FORMATS,
1276 },
1277 .ops = &cs42l73_ops,
1278 .symmetric_rates = 1,
1279 }
1280};
1281
84b315ee 1282static int cs42l73_suspend(struct snd_soc_codec *codec)
6d10c914
BA		 1283{
1284 cs42l73_set_bias_level(codec, SND_SOC_BIAS_OFF);
1285
1286 return 0;
1287}
1288
1289static int cs42l73_resume(struct snd_soc_codec *codec)
1290{
6d10c914
BA		 1291 cs42l73_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1292 return 0;
1293}
1294
1295static int cs42l73_probe(struct snd_soc_codec *codec)
1296{
1297 int ret;
1298 struct cs42l73_private *cs42l73 = snd_soc_codec_get_drvdata(codec);
1299
1300 codec->control_data = cs42l73->regmap;
1301
1302 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
1303 if (ret < 0) {
1304 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1305 return ret;
1306 }
1307
1308 regcache_cache_only(cs42l73->regmap, true);
1309
1310 cs42l73_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1311
1312 cs42l73->mclksel = CS42L73_CLKID_MCLK1; /* MCLK1 as master clk */
1313 cs42l73->mclk = 0;
1314
1315 return ret;
1316}
1317
1318static int cs42l73_remove(struct snd_soc_codec *codec)
1319{
1320 cs42l73_set_bias_level(codec, SND_SOC_BIAS_OFF);
1321 return 0;
1322}
1323
1324static struct snd_soc_codec_driver soc_codec_dev_cs42l73 = {
1325 .probe = cs42l73_probe,
1326 .remove = cs42l73_remove,
1327 .suspend = cs42l73_suspend,
1328 .resume = cs42l73_resume,
1329 .set_bias_level = cs42l73_set_bias_level,
1330
1331 .dapm_widgets = cs42l73_dapm_widgets,
1332 .num_dapm_widgets = ARRAY_SIZE(cs42l73_dapm_widgets),
1333 .dapm_routes = cs42l73_audio_map,
1334 .num_dapm_routes = ARRAY_SIZE(cs42l73_audio_map),
1335
1336 .controls = cs42l73_snd_controls,
1337 .num_controls = ARRAY_SIZE(cs42l73_snd_controls),
1338};
1339
1340static struct regmap_config cs42l73_regmap = {
1341 .reg_bits = 8,
1342 .val_bits = 8,
1343
1344 .max_register = CS42L73_MAX_REGISTER,
1345 .reg_defaults = cs42l73_reg_defaults,
1346 .num_reg_defaults = ARRAY_SIZE(cs42l73_reg_defaults),
1347 .volatile_reg = cs42l73_volatile_register,
1348 .readable_reg = cs42l73_readable_register,
1349 .cache_type = REGCACHE_RBTREE,
1350};
1351
1352static __devinit int cs42l73_i2c_probe(struct i2c_client *i2c_client,
1353 const struct i2c_device_id *id)
1354{
1355 struct cs42l73_private *cs42l73;
1356 int ret;
1357 unsigned int devid = 0;
1358 unsigned int reg;
1359
cc0b401a
BA		 1360 cs42l73 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l73_private),
1361 GFP_KERNEL);
6d10c914
BA		 1362 if (!cs42l73) {
1363 dev_err(&i2c_client->dev, "could not allocate codec\n");
1364 return -ENOMEM;
1365 }
1366
1367 i2c_set_clientdata(i2c_client, cs42l73);
1368
571f6a7f 1369 cs42l73->regmap = devm_regmap_init_i2c(i2c_client, &cs42l73_regmap);
6d10c914
BA		 1370 if (IS_ERR(cs42l73->regmap)) {
1371 ret = PTR_ERR(cs42l73->regmap);
1372 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
571f6a7f 1373 return ret;
6d10c914
BA		 1374 }
1375 /* initialize codec */
1376 ret = regmap_read(cs42l73->regmap, CS42L73_DEVID_AB, &reg);
1377 devid = (reg & 0xFF) << 12;
1378
1379 ret = regmap_read(cs42l73->regmap, CS42L73_DEVID_CD, &reg);
1380 devid |= (reg & 0xFF) << 4;
1381
1382 ret = regmap_read(cs42l73->regmap, CS42L73_DEVID_E, &reg);
1383 devid |= (reg & 0xF0) >> 4;
1384
1385
1386 if (devid != CS42L73_DEVID) {
ea075615 1387 ret = -ENODEV;
6d10c914
BA		 1388 dev_err(&i2c_client->dev,
1389 "CS42L73 Device ID (%X). Expected %X\n",
1390 devid, CS42L73_DEVID);
571f6a7f 1391 return ret;
6d10c914
BA		 1392 }
1393
1394 ret = regmap_read(cs42l73->regmap, CS42L73_REVID, &reg);
1395 if (ret < 0) {
1396 dev_err(&i2c_client->dev, "Get Revision ID failed\n");
571f6a7f 1397 return ret;;
6d10c914
BA		 1398 }
1399
1400 dev_info(&i2c_client->dev,
8421f620 1401 "Cirrus Logic CS42L73, Revision: %02X\n", reg & 0xFF);
6d10c914
BA		 1402
1403 regcache_cache_only(cs42l73->regmap, true);
1404
1405 ret = snd_soc_register_codec(&i2c_client->dev,
1406 &soc_codec_dev_cs42l73, cs42l73_dai,
1407 ARRAY_SIZE(cs42l73_dai));
1408 if (ret < 0)
571f6a7f 1409 return ret;
6d10c914 1410 return 0;
6d10c914
BA		 1411}
1412
1413static __devexit int cs42l73_i2c_remove(struct i2c_client *client)
1414{
6d10c914 1415 snd_soc_unregister_codec(&client->dev);
6d10c914
BA		 1416 return 0;
1417}
1418
1419static const struct i2c_device_id cs42l73_id[] = {
1420 {"cs42l73", 0},
1421 {}
1422};
1423
1424MODULE_DEVICE_TABLE(i2c, cs42l73_id);
1425
1426static struct i2c_driver cs42l73_i2c_driver = {
1427 .driver = {
1428 .name = "cs42l73",
1429 .owner = THIS_MODULE,
1430 },
1431 .id_table = cs42l73_id,
1432 .probe = cs42l73_i2c_probe,
1433 .remove = __devexit_p(cs42l73_i2c_remove),
1434
1435};
1436
5edd3c27 1437module_i2c_driver(cs42l73_i2c_driver);
6d10c914
BA		 1438
1439MODULE_DESCRIPTION("ASoC CS42L73 driver");
1440MODULE_AUTHOR("Georgi Vlaev, Nucleus Systems Ltd, <joe@nucleusys.com>");
1441MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1442MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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