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567e4f98 SC |
1 | /* |
2 | * es8328.c -- ES8328 ALSA SoC Audio driver | |
3 | * | |
4 | * Copyright 2014 Sutajio Ko-Usagi PTE LTD | |
5 | * | |
6 | * Author: Sean Cross <xobs@kosagi.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/clk.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/of_device.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/pm.h> | |
18 | #include <linux/regmap.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/regulator/consumer.h> | |
21 | #include <sound/core.h> | |
22 | #include <sound/initval.h> | |
23 | #include <sound/pcm.h> | |
24 | #include <sound/pcm_params.h> | |
25 | #include <sound/soc.h> | |
26 | #include <sound/tlv.h> | |
27 | #include "es8328.h" | |
28 | ||
45749c91 JK |
29 | static const unsigned int rates_12288[] = { |
30 | 8000, 12000, 16000, 24000, 32000, 48000, 96000, | |
31 | }; | |
567e4f98 | 32 | |
45749c91 JK |
33 | static const int ratios_12288[] = { |
34 | 10, 7, 6, 4, 3, 2, 0, | |
35 | }; | |
36 | ||
37 | static const struct snd_pcm_hw_constraint_list constraints_12288 = { | |
38 | .count = ARRAY_SIZE(rates_12288), | |
39 | .list = rates_12288, | |
40 | }; | |
41 | ||
42 | static const unsigned int rates_11289[] = { | |
43 | 8018, 11025, 22050, 44100, 88200, | |
44 | }; | |
45 | ||
46 | static const int ratios_11289[] = { | |
47 | 9, 7, 4, 2, 0, | |
48 | }; | |
49 | ||
50 | static const struct snd_pcm_hw_constraint_list constraints_11289 = { | |
51 | .count = ARRAY_SIZE(rates_11289), | |
52 | .list = rates_11289, | |
567e4f98 SC |
53 | }; |
54 | ||
55 | /* regulator supplies for sgtl5000, VDDD is an optional external supply */ | |
56 | enum sgtl5000_regulator_supplies { | |
57 | DVDD, | |
58 | AVDD, | |
59 | PVDD, | |
60 | HPVDD, | |
61 | ES8328_SUPPLY_NUM | |
62 | }; | |
63 | ||
64 | /* vddd is optional supply */ | |
65 | static const char * const supply_names[ES8328_SUPPLY_NUM] = { | |
66 | "DVDD", | |
67 | "AVDD", | |
68 | "PVDD", | |
69 | "HPVDD", | |
70 | }; | |
71 | ||
45749c91 JK |
72 | #define ES8328_RATES (SNDRV_PCM_RATE_96000 | \ |
73 | SNDRV_PCM_RATE_48000 | \ | |
74 | SNDRV_PCM_RATE_44100 | \ | |
75 | SNDRV_PCM_RATE_32000 | \ | |
567e4f98 | 76 | SNDRV_PCM_RATE_22050 | \ |
45749c91 JK |
77 | SNDRV_PCM_RATE_16000 | \ |
78 | SNDRV_PCM_RATE_11025 | \ | |
79 | SNDRV_PCM_RATE_8000) | |
779e86a3 JK |
80 | #define ES8328_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ |
81 | SNDRV_PCM_FMTBIT_S18_3LE | \ | |
82 | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
83 | SNDRV_PCM_FMTBIT_S24_LE | \ | |
84 | SNDRV_PCM_FMTBIT_S32_LE) | |
567e4f98 SC |
85 | |
86 | struct es8328_priv { | |
87 | struct regmap *regmap; | |
88 | struct clk *clk; | |
89 | int playback_fs; | |
90 | bool deemph; | |
45749c91 JK |
91 | int mclkdiv2; |
92 | const struct snd_pcm_hw_constraint_list *sysclk_constraints; | |
93 | const int *mclk_ratios; | |
567e4f98 SC |
94 | struct regulator_bulk_data supplies[ES8328_SUPPLY_NUM]; |
95 | }; | |
96 | ||
97 | /* | |
98 | * ES8328 Controls | |
99 | */ | |
100 | ||
101 | static const char * const adcpol_txt[] = {"Normal", "L Invert", "R Invert", | |
102 | "L + R Invert"}; | |
103 | static SOC_ENUM_SINGLE_DECL(adcpol, | |
104 | ES8328_ADCCONTROL6, 6, adcpol_txt); | |
105 | ||
106 | static const DECLARE_TLV_DB_SCALE(play_tlv, -3000, 100, 0); | |
107 | static const DECLARE_TLV_DB_SCALE(dac_adc_tlv, -9600, 50, 0); | |
108 | static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 300, 0); | |
109 | static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0); | |
110 | static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 300, 0); | |
111 | ||
84ebac4d JK |
112 | static const struct { |
113 | int rate; | |
114 | unsigned int val; | |
115 | } deemph_settings[] = { | |
116 | { 0, ES8328_DACCONTROL6_DEEMPH_OFF }, | |
117 | { 32000, ES8328_DACCONTROL6_DEEMPH_32k }, | |
118 | { 44100, ES8328_DACCONTROL6_DEEMPH_44_1k }, | |
119 | { 48000, ES8328_DACCONTROL6_DEEMPH_48k }, | |
120 | }; | |
567e4f98 SC |
121 | |
122 | static int es8328_set_deemph(struct snd_soc_codec *codec) | |
123 | { | |
124 | struct es8328_priv *es8328 = snd_soc_codec_get_drvdata(codec); | |
125 | int val, i, best; | |
126 | ||
127 | /* | |
128 | * If we're using deemphasis select the nearest available sample | |
129 | * rate. | |
130 | */ | |
131 | if (es8328->deemph) { | |
84ebac4d JK |
132 | best = 0; |
133 | for (i = 1; i < ARRAY_SIZE(deemph_settings); i++) { | |
134 | if (abs(deemph_settings[i].rate - es8328->playback_fs) < | |
135 | abs(deemph_settings[best].rate - es8328->playback_fs)) | |
567e4f98 SC |
136 | best = i; |
137 | } | |
138 | ||
84ebac4d | 139 | val = deemph_settings[best].val; |
567e4f98 | 140 | } else { |
84ebac4d | 141 | val = ES8328_DACCONTROL6_DEEMPH_OFF; |
567e4f98 SC |
142 | } |
143 | ||
144 | dev_dbg(codec->dev, "Set deemphasis %d\n", val); | |
145 | ||
84ebac4d JK |
146 | return snd_soc_update_bits(codec, ES8328_DACCONTROL6, |
147 | ES8328_DACCONTROL6_DEEMPH_MASK, val); | |
567e4f98 SC |
148 | } |
149 | ||
150 | static int es8328_get_deemph(struct snd_kcontrol *kcontrol, | |
151 | struct snd_ctl_elem_value *ucontrol) | |
152 | { | |
153 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); | |
154 | struct es8328_priv *es8328 = snd_soc_codec_get_drvdata(codec); | |
155 | ||
d223b0e7 | 156 | ucontrol->value.integer.value[0] = es8328->deemph; |
567e4f98 SC |
157 | return 0; |
158 | } | |
159 | ||
160 | static int es8328_put_deemph(struct snd_kcontrol *kcontrol, | |
161 | struct snd_ctl_elem_value *ucontrol) | |
162 | { | |
163 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); | |
164 | struct es8328_priv *es8328 = snd_soc_codec_get_drvdata(codec); | |
7ab8a54e | 165 | unsigned int deemph = ucontrol->value.integer.value[0]; |
567e4f98 SC |
166 | int ret; |
167 | ||
168 | if (deemph > 1) | |
169 | return -EINVAL; | |
170 | ||
171 | ret = es8328_set_deemph(codec); | |
172 | if (ret < 0) | |
173 | return ret; | |
174 | ||
175 | es8328->deemph = deemph; | |
176 | ||
177 | return 0; | |
178 | } | |
179 | ||
180 | ||
181 | ||
182 | static const struct snd_kcontrol_new es8328_snd_controls[] = { | |
183 | SOC_DOUBLE_R_TLV("Capture Digital Volume", | |
184 | ES8328_ADCCONTROL8, ES8328_ADCCONTROL9, | |
185 | 0, 0xc0, 1, dac_adc_tlv), | |
186 | SOC_SINGLE("Capture ZC Switch", ES8328_ADCCONTROL7, 6, 1, 0), | |
187 | ||
188 | SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0, | |
189 | es8328_get_deemph, es8328_put_deemph), | |
190 | ||
191 | SOC_ENUM("Capture Polarity", adcpol), | |
192 | ||
193 | SOC_SINGLE_TLV("Left Mixer Left Bypass Volume", | |
194 | ES8328_DACCONTROL17, 3, 7, 1, bypass_tlv), | |
195 | SOC_SINGLE_TLV("Left Mixer Right Bypass Volume", | |
196 | ES8328_DACCONTROL19, 3, 7, 1, bypass_tlv), | |
197 | SOC_SINGLE_TLV("Right Mixer Left Bypass Volume", | |
198 | ES8328_DACCONTROL18, 3, 7, 1, bypass_tlv), | |
199 | SOC_SINGLE_TLV("Right Mixer Right Bypass Volume", | |
200 | ES8328_DACCONTROL20, 3, 7, 1, bypass_tlv), | |
201 | ||
202 | SOC_DOUBLE_R_TLV("PCM Volume", | |
203 | ES8328_LDACVOL, ES8328_RDACVOL, | |
204 | 0, ES8328_DACVOL_MAX, 1, dac_adc_tlv), | |
205 | ||
206 | SOC_DOUBLE_R_TLV("Output 1 Playback Volume", | |
207 | ES8328_LOUT1VOL, ES8328_ROUT1VOL, | |
208 | 0, ES8328_OUT1VOL_MAX, 0, play_tlv), | |
209 | ||
210 | SOC_DOUBLE_R_TLV("Output 2 Playback Volume", | |
211 | ES8328_LOUT2VOL, ES8328_ROUT2VOL, | |
212 | 0, ES8328_OUT2VOL_MAX, 0, play_tlv), | |
213 | ||
214 | SOC_DOUBLE_TLV("Mic PGA Volume", ES8328_ADCCONTROL1, | |
215 | 4, 0, 8, 0, mic_tlv), | |
216 | }; | |
217 | ||
218 | /* | |
219 | * DAPM Controls | |
220 | */ | |
221 | ||
222 | static const char * const es8328_line_texts[] = { | |
223 | "Line 1", "Line 2", "PGA", "Differential"}; | |
224 | ||
225 | static const struct soc_enum es8328_lline_enum = | |
226 | SOC_ENUM_SINGLE(ES8328_DACCONTROL16, 3, | |
227 | ARRAY_SIZE(es8328_line_texts), | |
228 | es8328_line_texts); | |
229 | static const struct snd_kcontrol_new es8328_left_line_controls = | |
230 | SOC_DAPM_ENUM("Route", es8328_lline_enum); | |
231 | ||
232 | static const struct soc_enum es8328_rline_enum = | |
233 | SOC_ENUM_SINGLE(ES8328_DACCONTROL16, 0, | |
234 | ARRAY_SIZE(es8328_line_texts), | |
235 | es8328_line_texts); | |
236 | static const struct snd_kcontrol_new es8328_right_line_controls = | |
237 | SOC_DAPM_ENUM("Route", es8328_lline_enum); | |
238 | ||
239 | /* Left Mixer */ | |
240 | static const struct snd_kcontrol_new es8328_left_mixer_controls[] = { | |
352d52e2 JK |
241 | SOC_DAPM_SINGLE("Playback Switch", ES8328_DACCONTROL17, 7, 1, 0), |
242 | SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL17, 6, 1, 0), | |
243 | SOC_DAPM_SINGLE("Right Playback Switch", ES8328_DACCONTROL18, 7, 1, 0), | |
244 | SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL18, 6, 1, 0), | |
567e4f98 SC |
245 | }; |
246 | ||
247 | /* Right Mixer */ | |
248 | static const struct snd_kcontrol_new es8328_right_mixer_controls[] = { | |
352d52e2 JK |
249 | SOC_DAPM_SINGLE("Left Playback Switch", ES8328_DACCONTROL19, 7, 1, 0), |
250 | SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL19, 6, 1, 0), | |
251 | SOC_DAPM_SINGLE("Playback Switch", ES8328_DACCONTROL20, 7, 1, 0), | |
252 | SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL20, 6, 1, 0), | |
567e4f98 SC |
253 | }; |
254 | ||
255 | static const char * const es8328_pga_sel[] = { | |
256 | "Line 1", "Line 2", "Line 3", "Differential"}; | |
257 | ||
258 | /* Left PGA Mux */ | |
259 | static const struct soc_enum es8328_lpga_enum = | |
260 | SOC_ENUM_SINGLE(ES8328_ADCCONTROL2, 6, | |
261 | ARRAY_SIZE(es8328_pga_sel), | |
262 | es8328_pga_sel); | |
263 | static const struct snd_kcontrol_new es8328_left_pga_controls = | |
264 | SOC_DAPM_ENUM("Route", es8328_lpga_enum); | |
265 | ||
266 | /* Right PGA Mux */ | |
267 | static const struct soc_enum es8328_rpga_enum = | |
268 | SOC_ENUM_SINGLE(ES8328_ADCCONTROL2, 4, | |
269 | ARRAY_SIZE(es8328_pga_sel), | |
270 | es8328_pga_sel); | |
271 | static const struct snd_kcontrol_new es8328_right_pga_controls = | |
272 | SOC_DAPM_ENUM("Route", es8328_rpga_enum); | |
273 | ||
274 | /* Differential Mux */ | |
275 | static const char * const es8328_diff_sel[] = {"Line 1", "Line 2"}; | |
276 | static SOC_ENUM_SINGLE_DECL(diffmux, | |
277 | ES8328_ADCCONTROL3, 7, es8328_diff_sel); | |
278 | static const struct snd_kcontrol_new es8328_diffmux_controls = | |
279 | SOC_DAPM_ENUM("Route", diffmux); | |
280 | ||
281 | /* Mono ADC Mux */ | |
282 | static const char * const es8328_mono_mux[] = {"Stereo", "Mono (Left)", | |
283 | "Mono (Right)", "Digital Mono"}; | |
284 | static SOC_ENUM_SINGLE_DECL(monomux, | |
285 | ES8328_ADCCONTROL3, 3, es8328_mono_mux); | |
286 | static const struct snd_kcontrol_new es8328_monomux_controls = | |
287 | SOC_DAPM_ENUM("Route", monomux); | |
288 | ||
289 | static const struct snd_soc_dapm_widget es8328_dapm_widgets[] = { | |
290 | SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0, | |
291 | &es8328_diffmux_controls), | |
292 | SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0, | |
293 | &es8328_monomux_controls), | |
294 | SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0, | |
295 | &es8328_monomux_controls), | |
296 | ||
297 | SND_SOC_DAPM_MUX("Left PGA Mux", ES8328_ADCPOWER, | |
298 | ES8328_ADCPOWER_AINL_OFF, 1, | |
299 | &es8328_left_pga_controls), | |
300 | SND_SOC_DAPM_MUX("Right PGA Mux", ES8328_ADCPOWER, | |
301 | ES8328_ADCPOWER_AINR_OFF, 1, | |
302 | &es8328_right_pga_controls), | |
303 | ||
304 | SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0, | |
305 | &es8328_left_line_controls), | |
306 | SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0, | |
307 | &es8328_right_line_controls), | |
308 | ||
309 | SND_SOC_DAPM_ADC("Right ADC", "Right Capture", ES8328_ADCPOWER, | |
310 | ES8328_ADCPOWER_ADCR_OFF, 1), | |
311 | SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ES8328_ADCPOWER, | |
312 | ES8328_ADCPOWER_ADCL_OFF, 1), | |
313 | ||
314 | SND_SOC_DAPM_SUPPLY("Mic Bias", ES8328_ADCPOWER, | |
315 | ES8328_ADCPOWER_MIC_BIAS_OFF, 1, NULL, 0), | |
316 | SND_SOC_DAPM_SUPPLY("Mic Bias Gen", ES8328_ADCPOWER, | |
317 | ES8328_ADCPOWER_ADC_BIAS_GEN_OFF, 1, NULL, 0), | |
318 | ||
319 | SND_SOC_DAPM_SUPPLY("DAC STM", ES8328_CHIPPOWER, | |
320 | ES8328_CHIPPOWER_DACSTM_RESET, 1, NULL, 0), | |
321 | SND_SOC_DAPM_SUPPLY("ADC STM", ES8328_CHIPPOWER, | |
322 | ES8328_CHIPPOWER_ADCSTM_RESET, 1, NULL, 0), | |
323 | ||
324 | SND_SOC_DAPM_SUPPLY("DAC DIG", ES8328_CHIPPOWER, | |
325 | ES8328_CHIPPOWER_DACDIG_OFF, 1, NULL, 0), | |
326 | SND_SOC_DAPM_SUPPLY("ADC DIG", ES8328_CHIPPOWER, | |
327 | ES8328_CHIPPOWER_ADCDIG_OFF, 1, NULL, 0), | |
328 | ||
329 | SND_SOC_DAPM_SUPPLY("DAC DLL", ES8328_CHIPPOWER, | |
330 | ES8328_CHIPPOWER_DACDLL_OFF, 1, NULL, 0), | |
331 | SND_SOC_DAPM_SUPPLY("ADC DLL", ES8328_CHIPPOWER, | |
332 | ES8328_CHIPPOWER_ADCDLL_OFF, 1, NULL, 0), | |
333 | ||
334 | SND_SOC_DAPM_SUPPLY("ADC Vref", ES8328_CHIPPOWER, | |
335 | ES8328_CHIPPOWER_ADCVREF_OFF, 1, NULL, 0), | |
336 | SND_SOC_DAPM_SUPPLY("DAC Vref", ES8328_CHIPPOWER, | |
337 | ES8328_CHIPPOWER_DACVREF_OFF, 1, NULL, 0), | |
338 | ||
339 | SND_SOC_DAPM_DAC("Right DAC", "Right Playback", ES8328_DACPOWER, | |
340 | ES8328_DACPOWER_RDAC_OFF, 1), | |
341 | SND_SOC_DAPM_DAC("Left DAC", "Left Playback", ES8328_DACPOWER, | |
342 | ES8328_DACPOWER_LDAC_OFF, 1), | |
343 | ||
344 | SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0, | |
345 | &es8328_left_mixer_controls[0], | |
346 | ARRAY_SIZE(es8328_left_mixer_controls)), | |
347 | SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0, | |
348 | &es8328_right_mixer_controls[0], | |
349 | ARRAY_SIZE(es8328_right_mixer_controls)), | |
350 | ||
351 | SND_SOC_DAPM_PGA("Right Out 2", ES8328_DACPOWER, | |
352 | ES8328_DACPOWER_ROUT2_ON, 0, NULL, 0), | |
353 | SND_SOC_DAPM_PGA("Left Out 2", ES8328_DACPOWER, | |
354 | ES8328_DACPOWER_LOUT2_ON, 0, NULL, 0), | |
355 | SND_SOC_DAPM_PGA("Right Out 1", ES8328_DACPOWER, | |
356 | ES8328_DACPOWER_ROUT1_ON, 0, NULL, 0), | |
357 | SND_SOC_DAPM_PGA("Left Out 1", ES8328_DACPOWER, | |
358 | ES8328_DACPOWER_LOUT1_ON, 0, NULL, 0), | |
359 | ||
360 | SND_SOC_DAPM_OUTPUT("LOUT1"), | |
361 | SND_SOC_DAPM_OUTPUT("ROUT1"), | |
362 | SND_SOC_DAPM_OUTPUT("LOUT2"), | |
363 | SND_SOC_DAPM_OUTPUT("ROUT2"), | |
364 | ||
365 | SND_SOC_DAPM_INPUT("LINPUT1"), | |
366 | SND_SOC_DAPM_INPUT("LINPUT2"), | |
367 | SND_SOC_DAPM_INPUT("RINPUT1"), | |
368 | SND_SOC_DAPM_INPUT("RINPUT2"), | |
369 | }; | |
370 | ||
371 | static const struct snd_soc_dapm_route es8328_dapm_routes[] = { | |
372 | ||
373 | { "Left Line Mux", "Line 1", "LINPUT1" }, | |
374 | { "Left Line Mux", "Line 2", "LINPUT2" }, | |
375 | { "Left Line Mux", "PGA", "Left PGA Mux" }, | |
376 | { "Left Line Mux", "Differential", "Differential Mux" }, | |
377 | ||
378 | { "Right Line Mux", "Line 1", "RINPUT1" }, | |
379 | { "Right Line Mux", "Line 2", "RINPUT2" }, | |
380 | { "Right Line Mux", "PGA", "Right PGA Mux" }, | |
381 | { "Right Line Mux", "Differential", "Differential Mux" }, | |
382 | ||
383 | { "Left PGA Mux", "Line 1", "LINPUT1" }, | |
384 | { "Left PGA Mux", "Line 2", "LINPUT2" }, | |
385 | { "Left PGA Mux", "Differential", "Differential Mux" }, | |
386 | ||
387 | { "Right PGA Mux", "Line 1", "RINPUT1" }, | |
388 | { "Right PGA Mux", "Line 2", "RINPUT2" }, | |
389 | { "Right PGA Mux", "Differential", "Differential Mux" }, | |
390 | ||
391 | { "Differential Mux", "Line 1", "LINPUT1" }, | |
392 | { "Differential Mux", "Line 1", "RINPUT1" }, | |
393 | { "Differential Mux", "Line 2", "LINPUT2" }, | |
394 | { "Differential Mux", "Line 2", "RINPUT2" }, | |
395 | ||
396 | { "Left ADC Mux", "Stereo", "Left PGA Mux" }, | |
397 | { "Left ADC Mux", "Mono (Left)", "Left PGA Mux" }, | |
398 | { "Left ADC Mux", "Digital Mono", "Left PGA Mux" }, | |
399 | ||
400 | { "Right ADC Mux", "Stereo", "Right PGA Mux" }, | |
401 | { "Right ADC Mux", "Mono (Right)", "Right PGA Mux" }, | |
402 | { "Right ADC Mux", "Digital Mono", "Right PGA Mux" }, | |
403 | ||
404 | { "Left ADC", NULL, "Left ADC Mux" }, | |
405 | { "Right ADC", NULL, "Right ADC Mux" }, | |
406 | ||
407 | { "ADC DIG", NULL, "ADC STM" }, | |
408 | { "ADC DIG", NULL, "ADC Vref" }, | |
409 | { "ADC DIG", NULL, "ADC DLL" }, | |
410 | ||
411 | { "Left ADC", NULL, "ADC DIG" }, | |
412 | { "Right ADC", NULL, "ADC DIG" }, | |
413 | ||
414 | { "Mic Bias", NULL, "Mic Bias Gen" }, | |
415 | ||
416 | { "Left Line Mux", "Line 1", "LINPUT1" }, | |
417 | { "Left Line Mux", "Line 2", "LINPUT2" }, | |
418 | { "Left Line Mux", "PGA", "Left PGA Mux" }, | |
419 | { "Left Line Mux", "Differential", "Differential Mux" }, | |
420 | ||
421 | { "Right Line Mux", "Line 1", "RINPUT1" }, | |
422 | { "Right Line Mux", "Line 2", "RINPUT2" }, | |
423 | { "Right Line Mux", "PGA", "Right PGA Mux" }, | |
424 | { "Right Line Mux", "Differential", "Differential Mux" }, | |
425 | ||
426 | { "Left Out 1", NULL, "Left DAC" }, | |
427 | { "Right Out 1", NULL, "Right DAC" }, | |
428 | { "Left Out 2", NULL, "Left DAC" }, | |
429 | { "Right Out 2", NULL, "Right DAC" }, | |
430 | ||
431 | { "Left Mixer", "Playback Switch", "Left DAC" }, | |
432 | { "Left Mixer", "Left Bypass Switch", "Left Line Mux" }, | |
433 | { "Left Mixer", "Right Playback Switch", "Right DAC" }, | |
434 | { "Left Mixer", "Right Bypass Switch", "Right Line Mux" }, | |
435 | ||
436 | { "Right Mixer", "Left Playback Switch", "Left DAC" }, | |
437 | { "Right Mixer", "Left Bypass Switch", "Left Line Mux" }, | |
438 | { "Right Mixer", "Playback Switch", "Right DAC" }, | |
439 | { "Right Mixer", "Right Bypass Switch", "Right Line Mux" }, | |
440 | ||
441 | { "DAC DIG", NULL, "DAC STM" }, | |
442 | { "DAC DIG", NULL, "DAC Vref" }, | |
443 | { "DAC DIG", NULL, "DAC DLL" }, | |
444 | ||
445 | { "Left DAC", NULL, "DAC DIG" }, | |
446 | { "Right DAC", NULL, "DAC DIG" }, | |
447 | ||
448 | { "Left Out 1", NULL, "Left Mixer" }, | |
449 | { "LOUT1", NULL, "Left Out 1" }, | |
450 | { "Right Out 1", NULL, "Right Mixer" }, | |
451 | { "ROUT1", NULL, "Right Out 1" }, | |
452 | ||
453 | { "Left Out 2", NULL, "Left Mixer" }, | |
454 | { "LOUT2", NULL, "Left Out 2" }, | |
455 | { "Right Out 2", NULL, "Right Mixer" }, | |
456 | { "ROUT2", NULL, "Right Out 2" }, | |
457 | }; | |
458 | ||
459 | static int es8328_mute(struct snd_soc_dai *dai, int mute) | |
460 | { | |
461 | return snd_soc_update_bits(dai->codec, ES8328_DACCONTROL3, | |
462 | ES8328_DACCONTROL3_DACMUTE, | |
463 | mute ? ES8328_DACCONTROL3_DACMUTE : 0); | |
464 | } | |
465 | ||
45749c91 JK |
466 | static int es8328_startup(struct snd_pcm_substream *substream, |
467 | struct snd_soc_dai *dai) | |
468 | { | |
469 | struct snd_soc_codec *codec = dai->codec; | |
470 | struct es8328_priv *es8328 = snd_soc_codec_get_drvdata(codec); | |
471 | ||
472 | if (es8328->sysclk_constraints) | |
473 | snd_pcm_hw_constraint_list(substream->runtime, 0, | |
474 | SNDRV_PCM_HW_PARAM_RATE, | |
475 | es8328->sysclk_constraints); | |
476 | ||
477 | return 0; | |
478 | } | |
479 | ||
567e4f98 SC |
480 | static int es8328_hw_params(struct snd_pcm_substream *substream, |
481 | struct snd_pcm_hw_params *params, | |
482 | struct snd_soc_dai *dai) | |
483 | { | |
484 | struct snd_soc_codec *codec = dai->codec; | |
485 | struct es8328_priv *es8328 = snd_soc_codec_get_drvdata(codec); | |
567e4f98 SC |
486 | int i; |
487 | int reg; | |
779e86a3 | 488 | int wl; |
45749c91 JK |
489 | int ratio; |
490 | ||
491 | if (!es8328->sysclk_constraints) { | |
492 | dev_err(codec->dev, "No MCLK configured\n"); | |
493 | return -EINVAL; | |
494 | } | |
567e4f98 SC |
495 | |
496 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
497 | reg = ES8328_DACCONTROL2; | |
498 | else | |
499 | reg = ES8328_ADCCONTROL5; | |
500 | ||
45749c91 JK |
501 | for (i = 0; i < es8328->sysclk_constraints->count; i++) |
502 | if (es8328->sysclk_constraints->list[i] == params_rate(params)) | |
503 | break; | |
504 | ||
505 | if (i == es8328->sysclk_constraints->count) { | |
506 | dev_err(codec->dev, "LRCLK %d unsupported with current clock\n", | |
507 | params_rate(params)); | |
567e4f98 SC |
508 | return -EINVAL; |
509 | } | |
45749c91 JK |
510 | |
511 | ratio = es8328->mclk_ratios[i]; | |
779e86a3 | 512 | snd_soc_update_bits(codec, ES8328_MASTERMODE, |
45749c91 JK |
513 | ES8328_MASTERMODE_MCLKDIV2, |
514 | es8328->mclkdiv2 ? ES8328_MASTERMODE_MCLKDIV2 : 0); | |
779e86a3 JK |
515 | |
516 | switch (params_width(params)) { | |
517 | case 16: | |
518 | wl = 3; | |
519 | break; | |
520 | case 18: | |
521 | wl = 2; | |
522 | break; | |
523 | case 20: | |
524 | wl = 1; | |
525 | break; | |
526 | case 24: | |
527 | wl = 0; | |
528 | break; | |
529 | case 32: | |
530 | wl = 4; | |
531 | break; | |
532 | default: | |
533 | return -EINVAL; | |
534 | } | |
567e4f98 | 535 | |
567e4f98 | 536 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
8865c95e JK |
537 | snd_soc_update_bits(codec, ES8328_DACCONTROL1, |
538 | ES8328_DACCONTROL1_DACWL_MASK, | |
779e86a3 | 539 | wl << ES8328_DACCONTROL1_DACWL_SHIFT); |
8865c95e | 540 | |
567e4f98 SC |
541 | es8328->playback_fs = params_rate(params); |
542 | es8328_set_deemph(codec); | |
8865c95e JK |
543 | } else |
544 | snd_soc_update_bits(codec, ES8328_ADCCONTROL4, | |
545 | ES8328_ADCCONTROL4_ADCWL_MASK, | |
779e86a3 | 546 | wl << ES8328_ADCCONTROL4_ADCWL_SHIFT); |
567e4f98 SC |
547 | |
548 | return snd_soc_update_bits(codec, reg, ES8328_RATEMASK, ratio); | |
549 | } | |
550 | ||
45749c91 JK |
551 | static int es8328_set_sysclk(struct snd_soc_dai *codec_dai, |
552 | int clk_id, unsigned int freq, int dir) | |
553 | { | |
554 | struct snd_soc_codec *codec = codec_dai->codec; | |
555 | struct es8328_priv *es8328 = snd_soc_codec_get_drvdata(codec); | |
556 | int mclkdiv2 = 0; | |
557 | ||
558 | switch (freq) { | |
559 | case 0: | |
560 | es8328->sysclk_constraints = NULL; | |
561 | es8328->mclk_ratios = NULL; | |
562 | break; | |
563 | case 22579200: | |
564 | mclkdiv2 = 1; | |
565 | /* fallthru */ | |
566 | case 11289600: | |
567 | es8328->sysclk_constraints = &constraints_11289; | |
568 | es8328->mclk_ratios = ratios_11289; | |
569 | break; | |
570 | case 24576000: | |
571 | mclkdiv2 = 1; | |
572 | /* fallthru */ | |
573 | case 12288000: | |
574 | es8328->sysclk_constraints = &constraints_12288; | |
575 | es8328->mclk_ratios = ratios_12288; | |
576 | break; | |
577 | default: | |
578 | return -EINVAL; | |
579 | } | |
580 | ||
581 | es8328->mclkdiv2 = mclkdiv2; | |
582 | return 0; | |
583 | } | |
584 | ||
567e4f98 SC |
585 | static int es8328_set_dai_fmt(struct snd_soc_dai *codec_dai, |
586 | unsigned int fmt) | |
587 | { | |
588 | struct snd_soc_codec *codec = codec_dai->codec; | |
8865c95e JK |
589 | u8 dac_mode = 0; |
590 | u8 adc_mode = 0; | |
567e4f98 SC |
591 | |
592 | /* set master/slave audio interface */ | |
593 | if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBM_CFM) | |
594 | return -EINVAL; | |
595 | ||
596 | /* interface format */ | |
597 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
598 | case SND_SOC_DAIFMT_I2S: | |
57e41f3f JK |
599 | dac_mode |= ES8328_DACCONTROL1_DACFORMAT_I2S; |
600 | adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_I2S; | |
567e4f98 SC |
601 | break; |
602 | case SND_SOC_DAIFMT_RIGHT_J: | |
57e41f3f JK |
603 | dac_mode |= ES8328_DACCONTROL1_DACFORMAT_RJUST; |
604 | adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_RJUST; | |
567e4f98 SC |
605 | break; |
606 | case SND_SOC_DAIFMT_LEFT_J: | |
57e41f3f JK |
607 | dac_mode |= ES8328_DACCONTROL1_DACFORMAT_LJUST; |
608 | adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_LJUST; | |
567e4f98 SC |
609 | break; |
610 | default: | |
611 | return -EINVAL; | |
612 | } | |
613 | ||
614 | /* clock inversion */ | |
615 | if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF) | |
616 | return -EINVAL; | |
617 | ||
8865c95e JK |
618 | snd_soc_update_bits(codec, ES8328_DACCONTROL1, |
619 | ES8328_DACCONTROL1_DACFORMAT_MASK, dac_mode); | |
620 | snd_soc_update_bits(codec, ES8328_ADCCONTROL4, | |
621 | ES8328_ADCCONTROL4_ADCFORMAT_MASK, adc_mode); | |
567e4f98 SC |
622 | |
623 | /* Master serial port mode, with BCLK generated automatically */ | |
420c470d JK |
624 | snd_soc_update_bits(codec, ES8328_MASTERMODE, |
625 | ES8328_MASTERMODE_MSC, ES8328_MASTERMODE_MSC); | |
567e4f98 SC |
626 | |
627 | return 0; | |
628 | } | |
629 | ||
630 | static int es8328_set_bias_level(struct snd_soc_codec *codec, | |
631 | enum snd_soc_bias_level level) | |
632 | { | |
633 | switch (level) { | |
634 | case SND_SOC_BIAS_ON: | |
635 | break; | |
636 | ||
637 | case SND_SOC_BIAS_PREPARE: | |
638 | /* VREF, VMID=2x50k, digital enabled */ | |
639 | snd_soc_write(codec, ES8328_CHIPPOWER, 0); | |
640 | snd_soc_update_bits(codec, ES8328_CONTROL1, | |
641 | ES8328_CONTROL1_VMIDSEL_MASK | | |
642 | ES8328_CONTROL1_ENREF, | |
643 | ES8328_CONTROL1_VMIDSEL_50k | | |
644 | ES8328_CONTROL1_ENREF); | |
645 | break; | |
646 | ||
647 | case SND_SOC_BIAS_STANDBY: | |
2aff57e3 | 648 | if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) { |
567e4f98 SC |
649 | snd_soc_update_bits(codec, ES8328_CONTROL1, |
650 | ES8328_CONTROL1_VMIDSEL_MASK | | |
651 | ES8328_CONTROL1_ENREF, | |
652 | ES8328_CONTROL1_VMIDSEL_5k | | |
653 | ES8328_CONTROL1_ENREF); | |
654 | ||
655 | /* Charge caps */ | |
656 | msleep(100); | |
657 | } | |
658 | ||
659 | snd_soc_write(codec, ES8328_CONTROL2, | |
660 | ES8328_CONTROL2_OVERCURRENT_ON | | |
661 | ES8328_CONTROL2_THERMAL_SHUTDOWN_ON); | |
662 | ||
663 | /* VREF, VMID=2*500k, digital stopped */ | |
664 | snd_soc_update_bits(codec, ES8328_CONTROL1, | |
665 | ES8328_CONTROL1_VMIDSEL_MASK | | |
666 | ES8328_CONTROL1_ENREF, | |
667 | ES8328_CONTROL1_VMIDSEL_500k | | |
668 | ES8328_CONTROL1_ENREF); | |
669 | break; | |
670 | ||
671 | case SND_SOC_BIAS_OFF: | |
672 | snd_soc_update_bits(codec, ES8328_CONTROL1, | |
673 | ES8328_CONTROL1_VMIDSEL_MASK | | |
674 | ES8328_CONTROL1_ENREF, | |
675 | 0); | |
676 | break; | |
677 | } | |
567e4f98 SC |
678 | return 0; |
679 | } | |
680 | ||
681 | static const struct snd_soc_dai_ops es8328_dai_ops = { | |
45749c91 | 682 | .startup = es8328_startup, |
567e4f98 SC |
683 | .hw_params = es8328_hw_params, |
684 | .digital_mute = es8328_mute, | |
45749c91 | 685 | .set_sysclk = es8328_set_sysclk, |
567e4f98 SC |
686 | .set_fmt = es8328_set_dai_fmt, |
687 | }; | |
688 | ||
689 | static struct snd_soc_dai_driver es8328_dai = { | |
690 | .name = "es8328-hifi-analog", | |
691 | .playback = { | |
692 | .stream_name = "Playback", | |
693 | .channels_min = 2, | |
694 | .channels_max = 2, | |
695 | .rates = ES8328_RATES, | |
696 | .formats = ES8328_FORMATS, | |
697 | }, | |
698 | .capture = { | |
699 | .stream_name = "Capture", | |
700 | .channels_min = 2, | |
701 | .channels_max = 2, | |
702 | .rates = ES8328_RATES, | |
703 | .formats = ES8328_FORMATS, | |
704 | }, | |
705 | .ops = &es8328_dai_ops, | |
ca0d8797 | 706 | .symmetric_rates = 1, |
567e4f98 SC |
707 | }; |
708 | ||
709 | static int es8328_suspend(struct snd_soc_codec *codec) | |
710 | { | |
711 | struct es8328_priv *es8328; | |
712 | int ret; | |
713 | ||
714 | es8328 = snd_soc_codec_get_drvdata(codec); | |
715 | ||
567e4f98 SC |
716 | clk_disable_unprepare(es8328->clk); |
717 | ||
718 | ret = regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), | |
719 | es8328->supplies); | |
720 | if (ret) { | |
721 | dev_err(codec->dev, "unable to disable regulators\n"); | |
722 | return ret; | |
723 | } | |
724 | return 0; | |
725 | } | |
726 | ||
727 | static int es8328_resume(struct snd_soc_codec *codec) | |
728 | { | |
729 | struct regmap *regmap = dev_get_regmap(codec->dev, NULL); | |
730 | struct es8328_priv *es8328; | |
731 | int ret; | |
732 | ||
733 | es8328 = snd_soc_codec_get_drvdata(codec); | |
734 | ||
735 | ret = clk_prepare_enable(es8328->clk); | |
736 | if (ret) { | |
737 | dev_err(codec->dev, "unable to enable clock\n"); | |
738 | return ret; | |
739 | } | |
740 | ||
741 | ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies), | |
742 | es8328->supplies); | |
743 | if (ret) { | |
744 | dev_err(codec->dev, "unable to enable regulators\n"); | |
745 | return ret; | |
746 | } | |
747 | ||
748 | regcache_mark_dirty(regmap); | |
749 | ret = regcache_sync(regmap); | |
750 | if (ret) { | |
751 | dev_err(codec->dev, "unable to sync regcache\n"); | |
752 | return ret; | |
753 | } | |
754 | ||
567e4f98 SC |
755 | return 0; |
756 | } | |
757 | ||
758 | static int es8328_codec_probe(struct snd_soc_codec *codec) | |
759 | { | |
760 | struct es8328_priv *es8328; | |
761 | int ret; | |
762 | ||
763 | es8328 = snd_soc_codec_get_drvdata(codec); | |
764 | ||
765 | ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies), | |
766 | es8328->supplies); | |
767 | if (ret) { | |
768 | dev_err(codec->dev, "unable to enable regulators\n"); | |
769 | return ret; | |
770 | } | |
771 | ||
772 | /* Setup clocks */ | |
773 | es8328->clk = devm_clk_get(codec->dev, NULL); | |
774 | if (IS_ERR(es8328->clk)) { | |
775 | dev_err(codec->dev, "codec clock missing or invalid\n"); | |
75c3daaa | 776 | ret = PTR_ERR(es8328->clk); |
567e4f98 SC |
777 | goto clk_fail; |
778 | } | |
779 | ||
780 | ret = clk_prepare_enable(es8328->clk); | |
781 | if (ret) { | |
782 | dev_err(codec->dev, "unable to prepare codec clk\n"); | |
783 | goto clk_fail; | |
784 | } | |
785 | ||
786 | return 0; | |
787 | ||
788 | clk_fail: | |
789 | regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), | |
790 | es8328->supplies); | |
791 | return ret; | |
792 | } | |
793 | ||
794 | static int es8328_remove(struct snd_soc_codec *codec) | |
795 | { | |
796 | struct es8328_priv *es8328; | |
797 | ||
798 | es8328 = snd_soc_codec_get_drvdata(codec); | |
799 | ||
800 | if (es8328->clk) | |
801 | clk_disable_unprepare(es8328->clk); | |
802 | ||
803 | regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), | |
804 | es8328->supplies); | |
805 | ||
806 | return 0; | |
807 | } | |
808 | ||
809 | const struct regmap_config es8328_regmap_config = { | |
810 | .reg_bits = 8, | |
811 | .val_bits = 8, | |
812 | .max_register = ES8328_REG_MAX, | |
813 | .cache_type = REGCACHE_RBTREE, | |
f2ed04a4 | 814 | .use_single_rw = true, |
567e4f98 SC |
815 | }; |
816 | EXPORT_SYMBOL_GPL(es8328_regmap_config); | |
817 | ||
818 | static struct snd_soc_codec_driver es8328_codec_driver = { | |
819 | .probe = es8328_codec_probe, | |
820 | .suspend = es8328_suspend, | |
821 | .resume = es8328_resume, | |
822 | .remove = es8328_remove, | |
823 | .set_bias_level = es8328_set_bias_level, | |
8d01370f LPC |
824 | .suspend_bias_off = true, |
825 | ||
567e4f98 SC |
826 | .controls = es8328_snd_controls, |
827 | .num_controls = ARRAY_SIZE(es8328_snd_controls), | |
828 | .dapm_widgets = es8328_dapm_widgets, | |
829 | .num_dapm_widgets = ARRAY_SIZE(es8328_dapm_widgets), | |
830 | .dapm_routes = es8328_dapm_routes, | |
831 | .num_dapm_routes = ARRAY_SIZE(es8328_dapm_routes), | |
832 | }; | |
833 | ||
834 | int es8328_probe(struct device *dev, struct regmap *regmap) | |
835 | { | |
836 | struct es8328_priv *es8328; | |
837 | int ret; | |
838 | int i; | |
839 | ||
840 | if (IS_ERR(regmap)) | |
841 | return PTR_ERR(regmap); | |
842 | ||
843 | es8328 = devm_kzalloc(dev, sizeof(*es8328), GFP_KERNEL); | |
844 | if (es8328 == NULL) | |
845 | return -ENOMEM; | |
846 | ||
847 | es8328->regmap = regmap; | |
848 | ||
849 | for (i = 0; i < ARRAY_SIZE(es8328->supplies); i++) | |
850 | es8328->supplies[i].supply = supply_names[i]; | |
851 | ||
852 | ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(es8328->supplies), | |
853 | es8328->supplies); | |
854 | if (ret) { | |
855 | dev_err(dev, "unable to get regulators\n"); | |
856 | return ret; | |
857 | } | |
858 | ||
859 | dev_set_drvdata(dev, es8328); | |
860 | ||
861 | return snd_soc_register_codec(dev, | |
862 | &es8328_codec_driver, &es8328_dai, 1); | |
863 | } | |
864 | EXPORT_SYMBOL_GPL(es8328_probe); | |
865 | ||
866 | MODULE_DESCRIPTION("ASoC ES8328 driver"); | |
867 | MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>"); | |
868 | MODULE_LICENSE("GPL"); |