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3b097d64 LPC |
1 | /* |
2 | * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * You should have received a copy of the GNU General Public License along | |
9 | * with this program; if not, write to the Free Software Foundation, Inc., | |
10 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
11 | * | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/slab.h> | |
68bfcafa | 18 | #include <linux/io.h> |
dd1b18ab | 19 | #include <linux/regmap.h> |
3b097d64 LPC |
20 | |
21 | #include <linux/delay.h> | |
22 | ||
23 | #include <sound/core.h> | |
24 | #include <sound/pcm.h> | |
25 | #include <sound/pcm_params.h> | |
26 | #include <sound/initval.h> | |
3b097d64 | 27 | #include <sound/soc.h> |
a484a9a3 | 28 | #include <sound/tlv.h> |
3b097d64 LPC |
29 | |
30 | #define JZ4740_REG_CODEC_1 0x0 | |
dd1b18ab | 31 | #define JZ4740_REG_CODEC_2 0x4 |
3b097d64 LPC |
32 | |
33 | #define JZ4740_CODEC_1_LINE_ENABLE BIT(29) | |
34 | #define JZ4740_CODEC_1_MIC_ENABLE BIT(28) | |
35 | #define JZ4740_CODEC_1_SW1_ENABLE BIT(27) | |
36 | #define JZ4740_CODEC_1_ADC_ENABLE BIT(26) | |
37 | #define JZ4740_CODEC_1_SW2_ENABLE BIT(25) | |
38 | #define JZ4740_CODEC_1_DAC_ENABLE BIT(24) | |
39 | #define JZ4740_CODEC_1_VREF_DISABLE BIT(20) | |
40 | #define JZ4740_CODEC_1_VREF_AMP_DISABLE BIT(19) | |
41 | #define JZ4740_CODEC_1_VREF_PULLDOWN BIT(18) | |
42 | #define JZ4740_CODEC_1_VREF_LOW_CURRENT BIT(17) | |
43 | #define JZ4740_CODEC_1_VREF_HIGH_CURRENT BIT(16) | |
44 | #define JZ4740_CODEC_1_HEADPHONE_DISABLE BIT(14) | |
45 | #define JZ4740_CODEC_1_HEADPHONE_AMP_CHANGE_ANY BIT(13) | |
46 | #define JZ4740_CODEC_1_HEADPHONE_CHARGE BIT(12) | |
47 | #define JZ4740_CODEC_1_HEADPHONE_PULLDOWN (BIT(11) | BIT(10)) | |
48 | #define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M BIT(9) | |
49 | #define JZ4740_CODEC_1_HEADPHONE_POWERDOWN BIT(8) | |
50 | #define JZ4740_CODEC_1_SUSPEND BIT(1) | |
51 | #define JZ4740_CODEC_1_RESET BIT(0) | |
52 | ||
53 | #define JZ4740_CODEC_1_LINE_ENABLE_OFFSET 29 | |
54 | #define JZ4740_CODEC_1_MIC_ENABLE_OFFSET 28 | |
55 | #define JZ4740_CODEC_1_SW1_ENABLE_OFFSET 27 | |
56 | #define JZ4740_CODEC_1_ADC_ENABLE_OFFSET 26 | |
57 | #define JZ4740_CODEC_1_SW2_ENABLE_OFFSET 25 | |
58 | #define JZ4740_CODEC_1_DAC_ENABLE_OFFSET 24 | |
59 | #define JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET 14 | |
60 | #define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET 8 | |
61 | ||
62 | #define JZ4740_CODEC_2_INPUT_VOLUME_MASK 0x1f0000 | |
63 | #define JZ4740_CODEC_2_SAMPLE_RATE_MASK 0x000f00 | |
64 | #define JZ4740_CODEC_2_MIC_BOOST_GAIN_MASK 0x000030 | |
65 | #define JZ4740_CODEC_2_HEADPHONE_VOLUME_MASK 0x000003 | |
66 | ||
67 | #define JZ4740_CODEC_2_INPUT_VOLUME_OFFSET 16 | |
68 | #define JZ4740_CODEC_2_SAMPLE_RATE_OFFSET 8 | |
69 | #define JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET 4 | |
70 | #define JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET 0 | |
71 | ||
dd1b18ab LPC |
72 | static const struct reg_default jz4740_codec_reg_defaults[] = { |
73 | { JZ4740_REG_CODEC_1, 0x021b2302 }, | |
74 | { JZ4740_REG_CODEC_2, 0x00170803 }, | |
3b097d64 LPC |
75 | }; |
76 | ||
77 | struct jz4740_codec { | |
dd1b18ab | 78 | struct regmap *regmap; |
3b097d64 LPC |
79 | }; |
80 | ||
4689ac53 | 81 | static const DECLARE_TLV_DB_RANGE(jz4740_mic_tlv, |
a484a9a3 | 82 | 0, 2, TLV_DB_SCALE_ITEM(0, 600, 0), |
4689ac53 LPC |
83 | 3, 3, TLV_DB_SCALE_ITEM(2000, 0, 0) |
84 | ); | |
a484a9a3 LPC |
85 | |
86 | static const DECLARE_TLV_DB_SCALE(jz4740_out_tlv, 0, 200, 0); | |
87 | static const DECLARE_TLV_DB_SCALE(jz4740_in_tlv, -3450, 150, 0); | |
88 | ||
3b097d64 | 89 | static const struct snd_kcontrol_new jz4740_codec_controls[] = { |
a484a9a3 LPC |
90 | SOC_SINGLE_TLV("Master Playback Volume", JZ4740_REG_CODEC_2, |
91 | JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET, 3, 0, | |
92 | jz4740_out_tlv), | |
93 | SOC_SINGLE_TLV("Master Capture Volume", JZ4740_REG_CODEC_2, | |
94 | JZ4740_CODEC_2_INPUT_VOLUME_OFFSET, 31, 0, | |
95 | jz4740_in_tlv), | |
3b097d64 LPC |
96 | SOC_SINGLE("Master Playback Switch", JZ4740_REG_CODEC_1, |
97 | JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET, 1, 1), | |
a484a9a3 LPC |
98 | SOC_SINGLE_TLV("Mic Capture Volume", JZ4740_REG_CODEC_2, |
99 | JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET, 3, 0, | |
100 | jz4740_mic_tlv), | |
3b097d64 LPC |
101 | }; |
102 | ||
103 | static const struct snd_kcontrol_new jz4740_codec_output_controls[] = { | |
104 | SOC_DAPM_SINGLE("Bypass Switch", JZ4740_REG_CODEC_1, | |
105 | JZ4740_CODEC_1_SW1_ENABLE_OFFSET, 1, 0), | |
106 | SOC_DAPM_SINGLE("DAC Switch", JZ4740_REG_CODEC_1, | |
107 | JZ4740_CODEC_1_SW2_ENABLE_OFFSET, 1, 0), | |
108 | }; | |
109 | ||
110 | static const struct snd_kcontrol_new jz4740_codec_input_controls[] = { | |
111 | SOC_DAPM_SINGLE("Line Capture Switch", JZ4740_REG_CODEC_1, | |
112 | JZ4740_CODEC_1_LINE_ENABLE_OFFSET, 1, 0), | |
113 | SOC_DAPM_SINGLE("Mic Capture Switch", JZ4740_REG_CODEC_1, | |
114 | JZ4740_CODEC_1_MIC_ENABLE_OFFSET, 1, 0), | |
115 | }; | |
116 | ||
117 | static const struct snd_soc_dapm_widget jz4740_codec_dapm_widgets[] = { | |
118 | SND_SOC_DAPM_ADC("ADC", "Capture", JZ4740_REG_CODEC_1, | |
119 | JZ4740_CODEC_1_ADC_ENABLE_OFFSET, 0), | |
120 | SND_SOC_DAPM_DAC("DAC", "Playback", JZ4740_REG_CODEC_1, | |
121 | JZ4740_CODEC_1_DAC_ENABLE_OFFSET, 0), | |
122 | ||
123 | SND_SOC_DAPM_MIXER("Output Mixer", JZ4740_REG_CODEC_1, | |
124 | JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET, 1, | |
125 | jz4740_codec_output_controls, | |
126 | ARRAY_SIZE(jz4740_codec_output_controls)), | |
127 | ||
128 | SND_SOC_DAPM_MIXER_NAMED_CTL("Input Mixer", SND_SOC_NOPM, 0, 0, | |
129 | jz4740_codec_input_controls, | |
130 | ARRAY_SIZE(jz4740_codec_input_controls)), | |
131 | SND_SOC_DAPM_MIXER("Line Input", SND_SOC_NOPM, 0, 0, NULL, 0), | |
132 | ||
133 | SND_SOC_DAPM_OUTPUT("LOUT"), | |
134 | SND_SOC_DAPM_OUTPUT("ROUT"), | |
135 | ||
136 | SND_SOC_DAPM_INPUT("MIC"), | |
137 | SND_SOC_DAPM_INPUT("LIN"), | |
138 | SND_SOC_DAPM_INPUT("RIN"), | |
139 | }; | |
140 | ||
141 | static const struct snd_soc_dapm_route jz4740_codec_dapm_routes[] = { | |
142 | {"Line Input", NULL, "LIN"}, | |
143 | {"Line Input", NULL, "RIN"}, | |
144 | ||
145 | {"Input Mixer", "Line Capture Switch", "Line Input"}, | |
146 | {"Input Mixer", "Mic Capture Switch", "MIC"}, | |
147 | ||
148 | {"ADC", NULL, "Input Mixer"}, | |
149 | ||
150 | {"Output Mixer", "Bypass Switch", "Input Mixer"}, | |
151 | {"Output Mixer", "DAC Switch", "DAC"}, | |
152 | ||
153 | {"LOUT", NULL, "Output Mixer"}, | |
154 | {"ROUT", NULL, "Output Mixer"}, | |
155 | }; | |
156 | ||
157 | static int jz4740_codec_hw_params(struct snd_pcm_substream *substream, | |
158 | struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) | |
159 | { | |
dd1b18ab | 160 | struct jz4740_codec *jz4740_codec = snd_soc_codec_get_drvdata(dai->codec); |
3b097d64 | 161 | uint32_t val; |
3b097d64 LPC |
162 | |
163 | switch (params_rate(params)) { | |
164 | case 8000: | |
165 | val = 0; | |
166 | break; | |
167 | case 11025: | |
168 | val = 1; | |
169 | break; | |
170 | case 12000: | |
171 | val = 2; | |
172 | break; | |
173 | case 16000: | |
174 | val = 3; | |
175 | break; | |
176 | case 22050: | |
177 | val = 4; | |
178 | break; | |
179 | case 24000: | |
180 | val = 5; | |
181 | break; | |
182 | case 32000: | |
183 | val = 6; | |
184 | break; | |
185 | case 44100: | |
186 | val = 7; | |
187 | break; | |
188 | case 48000: | |
189 | val = 8; | |
190 | break; | |
191 | default: | |
192 | return -EINVAL; | |
193 | } | |
194 | ||
195 | val <<= JZ4740_CODEC_2_SAMPLE_RATE_OFFSET; | |
196 | ||
dd1b18ab | 197 | regmap_update_bits(jz4740_codec->regmap, JZ4740_REG_CODEC_2, |
3b097d64 LPC |
198 | JZ4740_CODEC_2_SAMPLE_RATE_MASK, val); |
199 | ||
200 | return 0; | |
201 | } | |
202 | ||
85e7652d | 203 | static const struct snd_soc_dai_ops jz4740_codec_dai_ops = { |
3b097d64 LPC |
204 | .hw_params = jz4740_codec_hw_params, |
205 | }; | |
206 | ||
f0fba2ad LG |
207 | static struct snd_soc_dai_driver jz4740_codec_dai = { |
208 | .name = "jz4740-hifi", | |
3b097d64 LPC |
209 | .playback = { |
210 | .stream_name = "Playback", | |
211 | .channels_min = 2, | |
212 | .channels_max = 2, | |
213 | .rates = SNDRV_PCM_RATE_8000_48000, | |
214 | .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8, | |
215 | }, | |
216 | .capture = { | |
217 | .stream_name = "Capture", | |
218 | .channels_min = 2, | |
219 | .channels_max = 2, | |
220 | .rates = SNDRV_PCM_RATE_8000_48000, | |
221 | .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8, | |
222 | }, | |
223 | .ops = &jz4740_codec_dai_ops, | |
224 | .symmetric_rates = 1, | |
225 | }; | |
3b097d64 | 226 | |
dd1b18ab | 227 | static void jz4740_codec_wakeup(struct regmap *regmap) |
3b097d64 | 228 | { |
dd1b18ab | 229 | regmap_update_bits(regmap, JZ4740_REG_CODEC_1, |
3b097d64 LPC |
230 | JZ4740_CODEC_1_RESET, JZ4740_CODEC_1_RESET); |
231 | udelay(2); | |
232 | ||
dd1b18ab | 233 | regmap_update_bits(regmap, JZ4740_REG_CODEC_1, |
3b097d64 LPC |
234 | JZ4740_CODEC_1_SUSPEND | JZ4740_CODEC_1_RESET, 0); |
235 | ||
dd1b18ab | 236 | regcache_sync(regmap); |
3b097d64 LPC |
237 | } |
238 | ||
239 | static int jz4740_codec_set_bias_level(struct snd_soc_codec *codec, | |
240 | enum snd_soc_bias_level level) | |
241 | { | |
dd1b18ab LPC |
242 | struct jz4740_codec *jz4740_codec = snd_soc_codec_get_drvdata(codec); |
243 | struct regmap *regmap = jz4740_codec->regmap; | |
3b097d64 LPC |
244 | unsigned int mask; |
245 | unsigned int value; | |
246 | ||
247 | switch (level) { | |
248 | case SND_SOC_BIAS_ON: | |
249 | break; | |
250 | case SND_SOC_BIAS_PREPARE: | |
251 | mask = JZ4740_CODEC_1_VREF_DISABLE | | |
252 | JZ4740_CODEC_1_VREF_AMP_DISABLE | | |
253 | JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M; | |
254 | value = 0; | |
255 | ||
dd1b18ab | 256 | regmap_update_bits(regmap, JZ4740_REG_CODEC_1, mask, value); |
3b097d64 LPC |
257 | break; |
258 | case SND_SOC_BIAS_STANDBY: | |
259 | /* The only way to clear the suspend flag is to reset the codec */ | |
40d62f23 | 260 | if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) |
dd1b18ab | 261 | jz4740_codec_wakeup(regmap); |
3b097d64 LPC |
262 | |
263 | mask = JZ4740_CODEC_1_VREF_DISABLE | | |
264 | JZ4740_CODEC_1_VREF_AMP_DISABLE | | |
265 | JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M; | |
266 | value = JZ4740_CODEC_1_VREF_DISABLE | | |
267 | JZ4740_CODEC_1_VREF_AMP_DISABLE | | |
268 | JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M; | |
269 | ||
dd1b18ab | 270 | regmap_update_bits(regmap, JZ4740_REG_CODEC_1, mask, value); |
3b097d64 LPC |
271 | break; |
272 | case SND_SOC_BIAS_OFF: | |
273 | mask = JZ4740_CODEC_1_SUSPEND; | |
274 | value = JZ4740_CODEC_1_SUSPEND; | |
275 | ||
dd1b18ab LPC |
276 | regmap_update_bits(regmap, JZ4740_REG_CODEC_1, mask, value); |
277 | regcache_mark_dirty(regmap); | |
3b097d64 LPC |
278 | break; |
279 | default: | |
280 | break; | |
281 | } | |
282 | ||
3b097d64 LPC |
283 | return 0; |
284 | } | |
285 | ||
f0fba2ad | 286 | static int jz4740_codec_dev_probe(struct snd_soc_codec *codec) |
3b097d64 | 287 | { |
dd1b18ab LPC |
288 | struct jz4740_codec *jz4740_codec = snd_soc_codec_get_drvdata(codec); |
289 | ||
290 | regmap_update_bits(jz4740_codec->regmap, JZ4740_REG_CODEC_1, | |
f0fba2ad | 291 | JZ4740_CODEC_1_SW2_ENABLE, JZ4740_CODEC_1_SW2_ENABLE); |
3b097d64 | 292 | |
3b097d64 LPC |
293 | return 0; |
294 | } | |
295 | ||
f0fba2ad | 296 | static struct snd_soc_codec_driver soc_codec_dev_jz4740_codec = { |
3b097d64 | 297 | .probe = jz4740_codec_dev_probe, |
f0fba2ad | 298 | .set_bias_level = jz4740_codec_set_bias_level, |
2a93f709 | 299 | .suspend_bias_off = true, |
67447912 LPC |
300 | |
301 | .controls = jz4740_codec_controls, | |
302 | .num_controls = ARRAY_SIZE(jz4740_codec_controls), | |
303 | .dapm_widgets = jz4740_codec_dapm_widgets, | |
304 | .num_dapm_widgets = ARRAY_SIZE(jz4740_codec_dapm_widgets), | |
305 | .dapm_routes = jz4740_codec_dapm_routes, | |
306 | .num_dapm_routes = ARRAY_SIZE(jz4740_codec_dapm_routes), | |
3b097d64 | 307 | }; |
3b097d64 | 308 | |
dd1b18ab LPC |
309 | static const struct regmap_config jz4740_codec_regmap_config = { |
310 | .reg_bits = 32, | |
311 | .reg_stride = 4, | |
312 | .val_bits = 32, | |
313 | .max_register = JZ4740_REG_CODEC_2, | |
314 | ||
315 | .reg_defaults = jz4740_codec_reg_defaults, | |
316 | .num_reg_defaults = ARRAY_SIZE(jz4740_codec_reg_defaults), | |
317 | .cache_type = REGCACHE_RBTREE, | |
318 | }; | |
319 | ||
7a79e94e | 320 | static int jz4740_codec_probe(struct platform_device *pdev) |
3b097d64 LPC |
321 | { |
322 | int ret; | |
323 | struct jz4740_codec *jz4740_codec; | |
3b097d64 | 324 | struct resource *mem; |
dd1b18ab | 325 | void __iomem *base; |
3b097d64 | 326 | |
558460c6 AL |
327 | jz4740_codec = devm_kzalloc(&pdev->dev, sizeof(*jz4740_codec), |
328 | GFP_KERNEL); | |
3b097d64 LPC |
329 | if (!jz4740_codec) |
330 | return -ENOMEM; | |
331 | ||
332 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
b25b5aa0 TR |
333 | base = devm_ioremap_resource(&pdev->dev, mem); |
334 | if (IS_ERR(base)) | |
335 | return PTR_ERR(base); | |
3b097d64 | 336 | |
dd1b18ab LPC |
337 | jz4740_codec->regmap = devm_regmap_init_mmio(&pdev->dev, base, |
338 | &jz4740_codec_regmap_config); | |
339 | if (IS_ERR(jz4740_codec->regmap)) | |
340 | return PTR_ERR(jz4740_codec->regmap); | |
341 | ||
3b097d64 LPC |
342 | platform_set_drvdata(pdev, jz4740_codec); |
343 | ||
f0fba2ad LG |
344 | ret = snd_soc_register_codec(&pdev->dev, |
345 | &soc_codec_dev_jz4740_codec, &jz4740_codec_dai, 1); | |
355d74b5 | 346 | if (ret) |
3b097d64 | 347 | dev_err(&pdev->dev, "Failed to register codec\n"); |
3b097d64 | 348 | |
3b097d64 LPC |
349 | return ret; |
350 | } | |
351 | ||
7a79e94e | 352 | static int jz4740_codec_remove(struct platform_device *pdev) |
3b097d64 | 353 | { |
f0fba2ad | 354 | snd_soc_unregister_codec(&pdev->dev); |
3b097d64 | 355 | |
3b097d64 LPC |
356 | return 0; |
357 | } | |
358 | ||
359 | static struct platform_driver jz4740_codec_driver = { | |
360 | .probe = jz4740_codec_probe, | |
7a79e94e | 361 | .remove = jz4740_codec_remove, |
3b097d64 LPC |
362 | .driver = { |
363 | .name = "jz4740-codec", | |
3b097d64 LPC |
364 | }, |
365 | }; | |
366 | ||
5bbcc3c0 | 367 | module_platform_driver(jz4740_codec_driver); |
3b097d64 LPC |
368 | |
369 | MODULE_DESCRIPTION("JZ4740 SoC internal codec driver"); | |
370 | MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); | |
371 | MODULE_LICENSE("GPL v2"); | |
372 | MODULE_ALIAS("platform:jz4740-codec"); |