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3b097d64 LPC |
1 | /* |
2 | * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * You should have received a copy of the GNU General Public License along | |
9 | * with this program; if not, write to the Free Software Foundation, Inc., | |
10 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
11 | * | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/slab.h> | |
68bfcafa | 18 | #include <linux/io.h> |
3b097d64 LPC |
19 | |
20 | #include <linux/delay.h> | |
21 | ||
22 | #include <sound/core.h> | |
23 | #include <sound/pcm.h> | |
24 | #include <sound/pcm_params.h> | |
25 | #include <sound/initval.h> | |
3b097d64 | 26 | #include <sound/soc.h> |
a484a9a3 | 27 | #include <sound/tlv.h> |
3b097d64 LPC |
28 | |
29 | #define JZ4740_REG_CODEC_1 0x0 | |
30 | #define JZ4740_REG_CODEC_2 0x1 | |
31 | ||
32 | #define JZ4740_CODEC_1_LINE_ENABLE BIT(29) | |
33 | #define JZ4740_CODEC_1_MIC_ENABLE BIT(28) | |
34 | #define JZ4740_CODEC_1_SW1_ENABLE BIT(27) | |
35 | #define JZ4740_CODEC_1_ADC_ENABLE BIT(26) | |
36 | #define JZ4740_CODEC_1_SW2_ENABLE BIT(25) | |
37 | #define JZ4740_CODEC_1_DAC_ENABLE BIT(24) | |
38 | #define JZ4740_CODEC_1_VREF_DISABLE BIT(20) | |
39 | #define JZ4740_CODEC_1_VREF_AMP_DISABLE BIT(19) | |
40 | #define JZ4740_CODEC_1_VREF_PULLDOWN BIT(18) | |
41 | #define JZ4740_CODEC_1_VREF_LOW_CURRENT BIT(17) | |
42 | #define JZ4740_CODEC_1_VREF_HIGH_CURRENT BIT(16) | |
43 | #define JZ4740_CODEC_1_HEADPHONE_DISABLE BIT(14) | |
44 | #define JZ4740_CODEC_1_HEADPHONE_AMP_CHANGE_ANY BIT(13) | |
45 | #define JZ4740_CODEC_1_HEADPHONE_CHARGE BIT(12) | |
46 | #define JZ4740_CODEC_1_HEADPHONE_PULLDOWN (BIT(11) | BIT(10)) | |
47 | #define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M BIT(9) | |
48 | #define JZ4740_CODEC_1_HEADPHONE_POWERDOWN BIT(8) | |
49 | #define JZ4740_CODEC_1_SUSPEND BIT(1) | |
50 | #define JZ4740_CODEC_1_RESET BIT(0) | |
51 | ||
52 | #define JZ4740_CODEC_1_LINE_ENABLE_OFFSET 29 | |
53 | #define JZ4740_CODEC_1_MIC_ENABLE_OFFSET 28 | |
54 | #define JZ4740_CODEC_1_SW1_ENABLE_OFFSET 27 | |
55 | #define JZ4740_CODEC_1_ADC_ENABLE_OFFSET 26 | |
56 | #define JZ4740_CODEC_1_SW2_ENABLE_OFFSET 25 | |
57 | #define JZ4740_CODEC_1_DAC_ENABLE_OFFSET 24 | |
58 | #define JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET 14 | |
59 | #define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET 8 | |
60 | ||
61 | #define JZ4740_CODEC_2_INPUT_VOLUME_MASK 0x1f0000 | |
62 | #define JZ4740_CODEC_2_SAMPLE_RATE_MASK 0x000f00 | |
63 | #define JZ4740_CODEC_2_MIC_BOOST_GAIN_MASK 0x000030 | |
64 | #define JZ4740_CODEC_2_HEADPHONE_VOLUME_MASK 0x000003 | |
65 | ||
66 | #define JZ4740_CODEC_2_INPUT_VOLUME_OFFSET 16 | |
67 | #define JZ4740_CODEC_2_SAMPLE_RATE_OFFSET 8 | |
68 | #define JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET 4 | |
69 | #define JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET 0 | |
70 | ||
71 | static const uint32_t jz4740_codec_regs[] = { | |
72 | 0x021b2302, 0x00170803, | |
73 | }; | |
74 | ||
75 | struct jz4740_codec { | |
76 | void __iomem *base; | |
3b097d64 LPC |
77 | }; |
78 | ||
3b097d64 LPC |
79 | static unsigned int jz4740_codec_read(struct snd_soc_codec *codec, |
80 | unsigned int reg) | |
81 | { | |
f0fba2ad | 82 | struct jz4740_codec *jz4740_codec = snd_soc_codec_get_drvdata(codec); |
3b097d64 LPC |
83 | return readl(jz4740_codec->base + (reg << 2)); |
84 | } | |
85 | ||
86 | static int jz4740_codec_write(struct snd_soc_codec *codec, unsigned int reg, | |
87 | unsigned int val) | |
88 | { | |
f0fba2ad LG |
89 | struct jz4740_codec *jz4740_codec = snd_soc_codec_get_drvdata(codec); |
90 | u32 *cache = codec->reg_cache; | |
3b097d64 | 91 | |
f0fba2ad | 92 | cache[reg] = val; |
3b097d64 LPC |
93 | writel(val, jz4740_codec->base + (reg << 2)); |
94 | ||
95 | return 0; | |
96 | } | |
97 | ||
a484a9a3 LPC |
98 | static const unsigned int jz4740_mic_tlv[] = { |
99 | TLV_DB_RANGE_HEAD(2), | |
100 | 0, 2, TLV_DB_SCALE_ITEM(0, 600, 0), | |
101 | 3, 3, TLV_DB_SCALE_ITEM(2000, 0, 0), | |
102 | }; | |
103 | ||
104 | static const DECLARE_TLV_DB_SCALE(jz4740_out_tlv, 0, 200, 0); | |
105 | static const DECLARE_TLV_DB_SCALE(jz4740_in_tlv, -3450, 150, 0); | |
106 | ||
3b097d64 | 107 | static const struct snd_kcontrol_new jz4740_codec_controls[] = { |
a484a9a3 LPC |
108 | SOC_SINGLE_TLV("Master Playback Volume", JZ4740_REG_CODEC_2, |
109 | JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET, 3, 0, | |
110 | jz4740_out_tlv), | |
111 | SOC_SINGLE_TLV("Master Capture Volume", JZ4740_REG_CODEC_2, | |
112 | JZ4740_CODEC_2_INPUT_VOLUME_OFFSET, 31, 0, | |
113 | jz4740_in_tlv), | |
3b097d64 LPC |
114 | SOC_SINGLE("Master Playback Switch", JZ4740_REG_CODEC_1, |
115 | JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET, 1, 1), | |
a484a9a3 LPC |
116 | SOC_SINGLE_TLV("Mic Capture Volume", JZ4740_REG_CODEC_2, |
117 | JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET, 3, 0, | |
118 | jz4740_mic_tlv), | |
3b097d64 LPC |
119 | }; |
120 | ||
121 | static const struct snd_kcontrol_new jz4740_codec_output_controls[] = { | |
122 | SOC_DAPM_SINGLE("Bypass Switch", JZ4740_REG_CODEC_1, | |
123 | JZ4740_CODEC_1_SW1_ENABLE_OFFSET, 1, 0), | |
124 | SOC_DAPM_SINGLE("DAC Switch", JZ4740_REG_CODEC_1, | |
125 | JZ4740_CODEC_1_SW2_ENABLE_OFFSET, 1, 0), | |
126 | }; | |
127 | ||
128 | static const struct snd_kcontrol_new jz4740_codec_input_controls[] = { | |
129 | SOC_DAPM_SINGLE("Line Capture Switch", JZ4740_REG_CODEC_1, | |
130 | JZ4740_CODEC_1_LINE_ENABLE_OFFSET, 1, 0), | |
131 | SOC_DAPM_SINGLE("Mic Capture Switch", JZ4740_REG_CODEC_1, | |
132 | JZ4740_CODEC_1_MIC_ENABLE_OFFSET, 1, 0), | |
133 | }; | |
134 | ||
135 | static const struct snd_soc_dapm_widget jz4740_codec_dapm_widgets[] = { | |
136 | SND_SOC_DAPM_ADC("ADC", "Capture", JZ4740_REG_CODEC_1, | |
137 | JZ4740_CODEC_1_ADC_ENABLE_OFFSET, 0), | |
138 | SND_SOC_DAPM_DAC("DAC", "Playback", JZ4740_REG_CODEC_1, | |
139 | JZ4740_CODEC_1_DAC_ENABLE_OFFSET, 0), | |
140 | ||
141 | SND_SOC_DAPM_MIXER("Output Mixer", JZ4740_REG_CODEC_1, | |
142 | JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET, 1, | |
143 | jz4740_codec_output_controls, | |
144 | ARRAY_SIZE(jz4740_codec_output_controls)), | |
145 | ||
146 | SND_SOC_DAPM_MIXER_NAMED_CTL("Input Mixer", SND_SOC_NOPM, 0, 0, | |
147 | jz4740_codec_input_controls, | |
148 | ARRAY_SIZE(jz4740_codec_input_controls)), | |
149 | SND_SOC_DAPM_MIXER("Line Input", SND_SOC_NOPM, 0, 0, NULL, 0), | |
150 | ||
151 | SND_SOC_DAPM_OUTPUT("LOUT"), | |
152 | SND_SOC_DAPM_OUTPUT("ROUT"), | |
153 | ||
154 | SND_SOC_DAPM_INPUT("MIC"), | |
155 | SND_SOC_DAPM_INPUT("LIN"), | |
156 | SND_SOC_DAPM_INPUT("RIN"), | |
157 | }; | |
158 | ||
159 | static const struct snd_soc_dapm_route jz4740_codec_dapm_routes[] = { | |
160 | {"Line Input", NULL, "LIN"}, | |
161 | {"Line Input", NULL, "RIN"}, | |
162 | ||
163 | {"Input Mixer", "Line Capture Switch", "Line Input"}, | |
164 | {"Input Mixer", "Mic Capture Switch", "MIC"}, | |
165 | ||
166 | {"ADC", NULL, "Input Mixer"}, | |
167 | ||
168 | {"Output Mixer", "Bypass Switch", "Input Mixer"}, | |
169 | {"Output Mixer", "DAC Switch", "DAC"}, | |
170 | ||
171 | {"LOUT", NULL, "Output Mixer"}, | |
172 | {"ROUT", NULL, "Output Mixer"}, | |
173 | }; | |
174 | ||
175 | static int jz4740_codec_hw_params(struct snd_pcm_substream *substream, | |
176 | struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) | |
177 | { | |
178 | uint32_t val; | |
e6968a17 | 179 | struct snd_soc_codec *codec = dai->codec; |
3b097d64 LPC |
180 | |
181 | switch (params_rate(params)) { | |
182 | case 8000: | |
183 | val = 0; | |
184 | break; | |
185 | case 11025: | |
186 | val = 1; | |
187 | break; | |
188 | case 12000: | |
189 | val = 2; | |
190 | break; | |
191 | case 16000: | |
192 | val = 3; | |
193 | break; | |
194 | case 22050: | |
195 | val = 4; | |
196 | break; | |
197 | case 24000: | |
198 | val = 5; | |
199 | break; | |
200 | case 32000: | |
201 | val = 6; | |
202 | break; | |
203 | case 44100: | |
204 | val = 7; | |
205 | break; | |
206 | case 48000: | |
207 | val = 8; | |
208 | break; | |
209 | default: | |
210 | return -EINVAL; | |
211 | } | |
212 | ||
213 | val <<= JZ4740_CODEC_2_SAMPLE_RATE_OFFSET; | |
214 | ||
215 | snd_soc_update_bits(codec, JZ4740_REG_CODEC_2, | |
216 | JZ4740_CODEC_2_SAMPLE_RATE_MASK, val); | |
217 | ||
218 | return 0; | |
219 | } | |
220 | ||
85e7652d | 221 | static const struct snd_soc_dai_ops jz4740_codec_dai_ops = { |
3b097d64 LPC |
222 | .hw_params = jz4740_codec_hw_params, |
223 | }; | |
224 | ||
f0fba2ad LG |
225 | static struct snd_soc_dai_driver jz4740_codec_dai = { |
226 | .name = "jz4740-hifi", | |
3b097d64 LPC |
227 | .playback = { |
228 | .stream_name = "Playback", | |
229 | .channels_min = 2, | |
230 | .channels_max = 2, | |
231 | .rates = SNDRV_PCM_RATE_8000_48000, | |
232 | .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8, | |
233 | }, | |
234 | .capture = { | |
235 | .stream_name = "Capture", | |
236 | .channels_min = 2, | |
237 | .channels_max = 2, | |
238 | .rates = SNDRV_PCM_RATE_8000_48000, | |
239 | .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8, | |
240 | }, | |
241 | .ops = &jz4740_codec_dai_ops, | |
242 | .symmetric_rates = 1, | |
243 | }; | |
3b097d64 LPC |
244 | |
245 | static void jz4740_codec_wakeup(struct snd_soc_codec *codec) | |
246 | { | |
247 | int i; | |
248 | uint32_t *cache = codec->reg_cache; | |
249 | ||
250 | snd_soc_update_bits(codec, JZ4740_REG_CODEC_1, | |
251 | JZ4740_CODEC_1_RESET, JZ4740_CODEC_1_RESET); | |
252 | udelay(2); | |
253 | ||
254 | snd_soc_update_bits(codec, JZ4740_REG_CODEC_1, | |
255 | JZ4740_CODEC_1_SUSPEND | JZ4740_CODEC_1_RESET, 0); | |
256 | ||
257 | for (i = 0; i < ARRAY_SIZE(jz4740_codec_regs); ++i) | |
258 | jz4740_codec_write(codec, i, cache[i]); | |
259 | } | |
260 | ||
261 | static int jz4740_codec_set_bias_level(struct snd_soc_codec *codec, | |
262 | enum snd_soc_bias_level level) | |
263 | { | |
264 | unsigned int mask; | |
265 | unsigned int value; | |
266 | ||
267 | switch (level) { | |
268 | case SND_SOC_BIAS_ON: | |
269 | break; | |
270 | case SND_SOC_BIAS_PREPARE: | |
271 | mask = JZ4740_CODEC_1_VREF_DISABLE | | |
272 | JZ4740_CODEC_1_VREF_AMP_DISABLE | | |
273 | JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M; | |
274 | value = 0; | |
275 | ||
276 | snd_soc_update_bits(codec, JZ4740_REG_CODEC_1, mask, value); | |
277 | break; | |
278 | case SND_SOC_BIAS_STANDBY: | |
279 | /* The only way to clear the suspend flag is to reset the codec */ | |
ce6120cc | 280 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) |
3b097d64 LPC |
281 | jz4740_codec_wakeup(codec); |
282 | ||
283 | mask = JZ4740_CODEC_1_VREF_DISABLE | | |
284 | JZ4740_CODEC_1_VREF_AMP_DISABLE | | |
285 | JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M; | |
286 | value = JZ4740_CODEC_1_VREF_DISABLE | | |
287 | JZ4740_CODEC_1_VREF_AMP_DISABLE | | |
288 | JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M; | |
289 | ||
290 | snd_soc_update_bits(codec, JZ4740_REG_CODEC_1, mask, value); | |
291 | break; | |
292 | case SND_SOC_BIAS_OFF: | |
293 | mask = JZ4740_CODEC_1_SUSPEND; | |
294 | value = JZ4740_CODEC_1_SUSPEND; | |
295 | ||
296 | snd_soc_update_bits(codec, JZ4740_REG_CODEC_1, mask, value); | |
297 | break; | |
298 | default: | |
299 | break; | |
300 | } | |
301 | ||
ce6120cc | 302 | codec->dapm.bias_level = level; |
3b097d64 LPC |
303 | |
304 | return 0; | |
305 | } | |
306 | ||
f0fba2ad | 307 | static int jz4740_codec_dev_probe(struct snd_soc_codec *codec) |
3b097d64 | 308 | { |
f0fba2ad LG |
309 | snd_soc_update_bits(codec, JZ4740_REG_CODEC_1, |
310 | JZ4740_CODEC_1_SW2_ENABLE, JZ4740_CODEC_1_SW2_ENABLE); | |
3b097d64 | 311 | |
f0fba2ad LG |
312 | jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
313 | ||
3b097d64 LPC |
314 | return 0; |
315 | } | |
316 | ||
f0fba2ad | 317 | static int jz4740_codec_dev_remove(struct snd_soc_codec *codec) |
3b097d64 | 318 | { |
f0fba2ad | 319 | jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_OFF); |
3b097d64 LPC |
320 | |
321 | return 0; | |
322 | } | |
323 | ||
324 | #ifdef CONFIG_PM_SLEEP | |
325 | ||
84b315ee | 326 | static int jz4740_codec_suspend(struct snd_soc_codec *codec) |
3b097d64 | 327 | { |
3b097d64 LPC |
328 | return jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_OFF); |
329 | } | |
330 | ||
f0fba2ad | 331 | static int jz4740_codec_resume(struct snd_soc_codec *codec) |
3b097d64 | 332 | { |
3b097d64 LPC |
333 | return jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
334 | } | |
335 | ||
336 | #else | |
337 | #define jz4740_codec_suspend NULL | |
338 | #define jz4740_codec_resume NULL | |
339 | #endif | |
340 | ||
f0fba2ad | 341 | static struct snd_soc_codec_driver soc_codec_dev_jz4740_codec = { |
3b097d64 LPC |
342 | .probe = jz4740_codec_dev_probe, |
343 | .remove = jz4740_codec_dev_remove, | |
344 | .suspend = jz4740_codec_suspend, | |
345 | .resume = jz4740_codec_resume, | |
f0fba2ad LG |
346 | .read = jz4740_codec_read, |
347 | .write = jz4740_codec_write, | |
348 | .set_bias_level = jz4740_codec_set_bias_level, | |
349 | .reg_cache_default = jz4740_codec_regs, | |
350 | .reg_word_size = sizeof(u32), | |
351 | .reg_cache_size = 2, | |
67447912 LPC |
352 | |
353 | .controls = jz4740_codec_controls, | |
354 | .num_controls = ARRAY_SIZE(jz4740_codec_controls), | |
355 | .dapm_widgets = jz4740_codec_dapm_widgets, | |
356 | .num_dapm_widgets = ARRAY_SIZE(jz4740_codec_dapm_widgets), | |
357 | .dapm_routes = jz4740_codec_dapm_routes, | |
358 | .num_dapm_routes = ARRAY_SIZE(jz4740_codec_dapm_routes), | |
3b097d64 | 359 | }; |
3b097d64 LPC |
360 | |
361 | static int __devinit jz4740_codec_probe(struct platform_device *pdev) | |
362 | { | |
363 | int ret; | |
364 | struct jz4740_codec *jz4740_codec; | |
3b097d64 LPC |
365 | struct resource *mem; |
366 | ||
558460c6 AL |
367 | jz4740_codec = devm_kzalloc(&pdev->dev, sizeof(*jz4740_codec), |
368 | GFP_KERNEL); | |
3b097d64 LPC |
369 | if (!jz4740_codec) |
370 | return -ENOMEM; | |
371 | ||
372 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
355d74b5 LPC |
373 | jz4740_codec->base = devm_request_and_ioremap(&pdev->dev, mem); |
374 | if (!jz4740_codec->base) | |
375 | return -EBUSY; | |
3b097d64 | 376 | |
3b097d64 LPC |
377 | platform_set_drvdata(pdev, jz4740_codec); |
378 | ||
f0fba2ad LG |
379 | ret = snd_soc_register_codec(&pdev->dev, |
380 | &soc_codec_dev_jz4740_codec, &jz4740_codec_dai, 1); | |
355d74b5 | 381 | if (ret) |
3b097d64 | 382 | dev_err(&pdev->dev, "Failed to register codec\n"); |
3b097d64 | 383 | |
3b097d64 LPC |
384 | return ret; |
385 | } | |
386 | ||
387 | static int __devexit jz4740_codec_remove(struct platform_device *pdev) | |
388 | { | |
f0fba2ad | 389 | snd_soc_unregister_codec(&pdev->dev); |
3b097d64 | 390 | |
3b097d64 | 391 | platform_set_drvdata(pdev, NULL); |
3b097d64 LPC |
392 | |
393 | return 0; | |
394 | } | |
395 | ||
396 | static struct platform_driver jz4740_codec_driver = { | |
397 | .probe = jz4740_codec_probe, | |
398 | .remove = __devexit_p(jz4740_codec_remove), | |
399 | .driver = { | |
400 | .name = "jz4740-codec", | |
401 | .owner = THIS_MODULE, | |
402 | }, | |
403 | }; | |
404 | ||
5bbcc3c0 | 405 | module_platform_driver(jz4740_codec_driver); |
3b097d64 LPC |
406 | |
407 | MODULE_DESCRIPTION("JZ4740 SoC internal codec driver"); | |
408 | MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); | |
409 | MODULE_LICENSE("GPL v2"); | |
410 | MODULE_ALIAS("platform:jz4740-codec"); |