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ASoC: lm49453: Fix adc, mic and sidetone volume ranges
[deliverable/linux.git] / sound / soc / codecs / lm49453.c
CommitLineData
dbf7a733
SR		 1/*
2 * lm49453.c - LM49453 ALSA Soc Audio driver
3 *
4 * Copyright (c) 2012 Texas Instruments, Inc
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * Initially based on sound/soc/codecs/wm8350.c
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
dbf7a733
SR		 15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/regmap.h>
21#include <linux/slab.h>
22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/tlv.h>
28#include <sound/jack.h>
29#include <sound/initval.h>
30#include <asm/div64.h>
31#include "lm49453.h"
32
33static struct reg_default lm49453_reg_defs[] = {
34 { 0, 0x00 },
35 { 1, 0x00 },
36 { 2, 0x00 },
37 { 3, 0x00 },
38 { 4, 0x00 },
39 { 5, 0x00 },
40 { 6, 0x00 },
41 { 7, 0x00 },
42 { 8, 0x00 },
43 { 9, 0x00 },
44 { 10, 0x00 },
45 { 11, 0x00 },
46 { 12, 0x00 },
47 { 13, 0x00 },
48 { 14, 0x00 },
49 { 15, 0x00 },
50 { 16, 0x00 },
51 { 17, 0x00 },
52 { 18, 0x00 },
53 { 19, 0x00 },
54 { 20, 0x00 },
55 { 21, 0x00 },
56 { 22, 0x00 },
57 { 23, 0x00 },
58 { 32, 0x00 },
59 { 33, 0x00 },
60 { 35, 0x00 },
61 { 36, 0x00 },
62 { 37, 0x00 },
63 { 46, 0x00 },
64 { 48, 0x00 },
65 { 49, 0x00 },
66 { 51, 0x00 },
67 { 56, 0x00 },
68 { 58, 0x00 },
69 { 59, 0x00 },
70 { 60, 0x00 },
71 { 61, 0x00 },
72 { 62, 0x00 },
73 { 63, 0x00 },
74 { 64, 0x00 },
75 { 65, 0x00 },
76 { 66, 0x00 },
77 { 67, 0x00 },
78 { 68, 0x00 },
79 { 69, 0x00 },
80 { 70, 0x00 },
81 { 71, 0x00 },
82 { 72, 0x00 },
83 { 73, 0x00 },
84 { 74, 0x00 },
85 { 75, 0x00 },
86 { 76, 0x00 },
87 { 77, 0x00 },
88 { 78, 0x00 },
89 { 79, 0x00 },
90 { 80, 0x00 },
91 { 81, 0x00 },
92 { 82, 0x00 },
93 { 83, 0x00 },
94 { 85, 0x00 },
95 { 85, 0x00 },
96 { 86, 0x00 },
97 { 87, 0x00 },
98 { 88, 0x00 },
99 { 89, 0x00 },
100 { 90, 0x00 },
101 { 91, 0x00 },
102 { 92, 0x00 },
103 { 93, 0x00 },
104 { 94, 0x00 },
105 { 95, 0x00 },
106 { 96, 0x01 },
107 { 97, 0x00 },
108 { 98, 0x00 },
109 { 99, 0x00 },
110 { 100, 0x00 },
111 { 101, 0x00 },
112 { 102, 0x00 },
113 { 103, 0x01 },
114 { 105, 0x01 },
115 { 106, 0x00 },
116 { 107, 0x01 },
117 { 107, 0x00 },
118 { 108, 0x00 },
119 { 109, 0x00 },
120 { 110, 0x00 },
121 { 111, 0x02 },
122 { 112, 0x02 },
123 { 113, 0x00 },
124 { 121, 0x80 },
125 { 122, 0xBB },
126 { 123, 0x80 },
127 { 124, 0xBB },
128 { 128, 0x00 },
129 { 130, 0x00 },
130 { 131, 0x00 },
131 { 132, 0x00 },
132 { 133, 0x0A },
133 { 134, 0x0A },
134 { 135, 0x0A },
135 { 136, 0x0F },
136 { 137, 0x00 },
137 { 138, 0x73 },
138 { 139, 0x33 },
139 { 140, 0x73 },
140 { 141, 0x33 },
141 { 142, 0x73 },
142 { 143, 0x33 },
143 { 144, 0x73 },
144 { 145, 0x33 },
145 { 146, 0x73 },
146 { 147, 0x33 },
147 { 148, 0x73 },
148 { 149, 0x33 },
149 { 150, 0x73 },
150 { 151, 0x33 },
151 { 152, 0x00 },
152 { 153, 0x00 },
153 { 154, 0x00 },
154 { 155, 0x00 },
155 { 176, 0x00 },
156 { 177, 0x00 },
157 { 178, 0x00 },
158 { 179, 0x00 },
159 { 180, 0x00 },
160 { 181, 0x00 },
161 { 182, 0x00 },
162 { 183, 0x00 },
163 { 184, 0x00 },
164 { 185, 0x00 },
165 { 186, 0x00 },
166 { 189, 0x00 },
167 { 188, 0x00 },
168 { 194, 0x00 },
169 { 195, 0x00 },
170 { 196, 0x00 },
171 { 197, 0x00 },
172 { 200, 0x00 },
173 { 201, 0x00 },
174 { 202, 0x00 },
175 { 203, 0x00 },
176 { 204, 0x00 },
177 { 205, 0x00 },
178 { 208, 0x00 },
179 { 209, 0x00 },
180 { 210, 0x00 },
181 { 211, 0x00 },
182 { 213, 0x00 },
183 { 214, 0x00 },
184 { 215, 0x00 },
185 { 216, 0x00 },
186 { 217, 0x00 },
187 { 218, 0x00 },
188 { 219, 0x00 },
189 { 221, 0x00 },
190 { 222, 0x00 },
191 { 224, 0x00 },
192 { 225, 0x00 },
193 { 226, 0x00 },
194 { 227, 0x00 },
195 { 228, 0x00 },
196 { 229, 0x00 },
197 { 230, 0x13 },
198 { 231, 0x00 },
199 { 232, 0x80 },
200 { 233, 0x0C },
201 { 234, 0xDD },
202 { 235, 0x00 },
203 { 236, 0x04 },
204 { 237, 0x00 },
205 { 238, 0x00 },
206 { 239, 0x00 },
207 { 240, 0x00 },
208 { 241, 0x00 },
209 { 242, 0x00 },
210 { 243, 0x00 },
211 { 244, 0x00 },
212 { 245, 0x00 },
213 { 248, 0x00 },
214 { 249, 0x00 },
215 { 254, 0x00 },
216 { 255, 0x00 },
217};
218
219/* codec private data */
220struct lm49453_priv {
221 struct regmap *regmap;
222 int fs_rate;
223};
224
225/* capture path controls */
226
227static const char *lm49453_mic2mode_text[] = {"Single Ended", "Differential"};
228
229static const SOC_ENUM_SINGLE_DECL(lm49453_mic2mode_enum, LM49453_P0_MICR_REG, 5,
230 lm49453_mic2mode_text);
231
232static const char *lm49453_dmic_cfg_text[] = {"DMICDAT1", "DMICDAT2"};
233
234static const SOC_ENUM_SINGLE_DECL(lm49453_dmic12_cfg_enum,
235 LM49453_P0_DIGITAL_MIC1_CONFIG_REG,
236 7, lm49453_dmic_cfg_text);
237
238static const SOC_ENUM_SINGLE_DECL(lm49453_dmic34_cfg_enum,
239 LM49453_P0_DIGITAL_MIC2_CONFIG_REG,
240 7, lm49453_dmic_cfg_text);
241
242/* MUX Controls */
243static const char *lm49453_adcl_mux_text[] = { "MIC1", "Aux_L" };
244
245static const char *lm49453_adcr_mux_text[] = { "MIC2", "Aux_R" };
246
247static const struct soc_enum lm49453_adcl_enum =
248 SOC_ENUM_SINGLE(LM49453_P0_ANALOG_MIXER_ADC_REG, 0,
249 ARRAY_SIZE(lm49453_adcl_mux_text),
250 lm49453_adcl_mux_text);
251
252static const struct soc_enum lm49453_adcr_enum =
253 SOC_ENUM_SINGLE(LM49453_P0_ANALOG_MIXER_ADC_REG, 1,
254 ARRAY_SIZE(lm49453_adcr_mux_text),
255 lm49453_adcr_mux_text);
256
257static const struct snd_kcontrol_new lm49453_adcl_mux_control =
258 SOC_DAPM_ENUM("ADC Left Mux", lm49453_adcl_enum);
259
260static const struct snd_kcontrol_new lm49453_adcr_mux_control =
261 SOC_DAPM_ENUM("ADC Right Mux", lm49453_adcr_enum);
262
263static const struct snd_kcontrol_new lm49453_headset_left_mixer[] = {
264SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHPL1_REG, 0, 1, 0),
265SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHPL1_REG, 1, 1, 0),
266SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHPL1_REG, 2, 1, 0),
267SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHPL1_REG, 3, 1, 0),
268SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHPL1_REG, 4, 1, 0),
269SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHPL1_REG, 5, 1, 0),
270SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHPL1_REG, 6, 1, 0),
271SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHPL1_REG, 7, 1, 0),
272SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHPL2_REG, 0, 1, 0),
273SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHPL2_REG, 1, 1, 0),
274SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHPL2_REG, 2, 1, 0),
275SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHPL2_REG, 3, 1, 0),
276SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHPL2_REG, 4, 1, 0),
277SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHPL2_REG, 5, 1, 0),
278SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHPL2_REG, 6, 1, 0),
279SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHPL2_REG, 7, 1, 0),
280SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 0, 0, 0),
281};
282
283static const struct snd_kcontrol_new lm49453_headset_right_mixer[] = {
284SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHPR1_REG, 0, 1, 0),
285SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHPR1_REG, 1, 1, 0),
286SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHPR1_REG, 2, 1, 0),
287SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHPR1_REG, 3, 1, 0),
288SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHPR1_REG, 4, 1, 0),
289SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHPR1_REG, 5, 1, 0),
290SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHPR1_REG, 6, 1, 0),
291SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHPR1_REG, 7, 1, 0),
292SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHPR2_REG, 0, 1, 0),
293SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHPR2_REG, 1, 1, 0),
294SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHPR2_REG, 2, 1, 0),
295SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHPR2_REG, 3, 1, 0),
296SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHPR2_REG, 4, 1, 0),
297SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHPR2_REG, 5, 1, 0),
298SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHPR2_REG, 6, 1, 0),
299SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHPR2_REG, 7, 1, 0),
300SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 1, 0, 0),
301};
302
303static const struct snd_kcontrol_new lm49453_speaker_left_mixer[] = {
304SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLSL1_REG, 0, 1, 0),
305SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLSL1_REG, 1, 1, 0),
306SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLSL1_REG, 2, 1, 0),
307SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLSL1_REG, 3, 1, 0),
308SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLSL1_REG, 4, 1, 0),
309SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLSL1_REG, 5, 1, 0),
310SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLSL1_REG, 6, 1, 0),
311SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLSL1_REG, 7, 1, 0),
312SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLSL2_REG, 0, 1, 0),
313SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLSL2_REG, 1, 1, 0),
314SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLSL2_REG, 2, 1, 0),
315SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLSL2_REG, 3, 1, 0),
316SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLSL2_REG, 4, 1, 0),
317SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLSL2_REG, 5, 1, 0),
318SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLSL2_REG, 6, 1, 0),
319SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLSL2_REG, 7, 1, 0),
320SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 2, 0, 0),
321};
322
323static const struct snd_kcontrol_new lm49453_speaker_right_mixer[] = {
324SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLSR1_REG, 0, 1, 0),
325SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLSR1_REG, 1, 1, 0),
326SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLSR1_REG, 2, 1, 0),
327SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLSR1_REG, 3, 1, 0),
328SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLSR1_REG, 4, 1, 0),
329SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLSR1_REG, 5, 1, 0),
330SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLSR1_REG, 6, 1, 0),
331SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLSR1_REG, 7, 1, 0),
332SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLSR2_REG, 0, 1, 0),
333SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLSR2_REG, 1, 1, 0),
334SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLSR2_REG, 2, 1, 0),
335SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLSR2_REG, 3, 1, 0),
336SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLSR2_REG, 4, 1, 0),
337SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLSR2_REG, 5, 1, 0),
338SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLSR2_REG, 6, 1, 0),
339SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLSR2_REG, 7, 1, 0),
340SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 3, 0, 0),
341};
342
343static const struct snd_kcontrol_new lm49453_haptic_left_mixer[] = {
344SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHAL1_REG, 0, 1, 0),
345SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHAL1_REG, 1, 1, 0),
346SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHAL1_REG, 2, 1, 0),
347SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHAL1_REG, 3, 1, 0),
348SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHAL1_REG, 4, 1, 0),
349SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHAL1_REG, 5, 1, 0),
350SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHAL1_REG, 6, 1, 0),
351SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHAL1_REG, 7, 1, 0),
352SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHAL2_REG, 0, 1, 0),
353SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHAL2_REG, 1, 1, 0),
354SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHAL2_REG, 2, 1, 0),
355SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHAL2_REG, 3, 1, 0),
356SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHAL2_REG, 4, 1, 0),
357SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHAL2_REG, 5, 1, 0),
358SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHAL2_REG, 6, 1, 0),
359SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHAL2_REG, 7, 1, 0),
360SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 4, 0, 0),
361};
362
363static const struct snd_kcontrol_new lm49453_haptic_right_mixer[] = {
364SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHAR1_REG, 0, 1, 0),
365SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHAR1_REG, 1, 1, 0),
366SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHAR1_REG, 2, 1, 0),
367SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHAR1_REG, 3, 1, 0),
368SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHAR1_REG, 4, 1, 0),
369SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHAR1_REG, 5, 1, 0),
370SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHAR1_REG, 6, 1, 0),
371SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHAR1_REG, 7, 1, 0),
372SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHAR2_REG, 0, 1, 0),
373SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHAR2_REG, 1, 1, 0),
374SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHAR2_REG, 2, 1, 0),
375SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHAR2_REG, 3, 1, 0),
376SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHAR2_REG, 4, 1, 0),
377SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHAR2_REG, 5, 1, 0),
378SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHAR2_REG, 6, 1, 0),
379SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHAR2_REG, 7, 1, 0),
380SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 5, 0, 0),
381};
382
383static const struct snd_kcontrol_new lm49453_lineout_left_mixer[] = {
384SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLOL1_REG, 0, 1, 0),
385SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLOL1_REG, 1, 1, 0),
386SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLOL1_REG, 2, 1, 0),
387SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLOL1_REG, 3, 1, 0),
388SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLOL1_REG, 4, 1, 0),
389SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLOL1_REG, 5, 1, 0),
390SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLOL1_REG, 6, 1, 0),
391SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLOL1_REG, 7, 1, 0),
392SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLOL2_REG, 0, 1, 0),
393SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLOL2_REG, 1, 1, 0),
394SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLOL2_REG, 2, 1, 0),
395SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLOL2_REG, 3, 1, 0),
396SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLOL2_REG, 4, 1, 0),
397SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLOL2_REG, 5, 1, 0),
398SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLOL2_REG, 6, 1, 0),
399SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLOL2_REG, 7, 1, 0),
400SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 6, 0, 0),
401};
402
403static const struct snd_kcontrol_new lm49453_lineout_right_mixer[] = {
404SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLOR1_REG, 0, 1, 0),
405SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLOR1_REG, 1, 1, 0),
406SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLOR1_REG, 2, 1, 0),
407SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLOR1_REG, 3, 1, 0),
408SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLOR1_REG, 4, 1, 0),
409SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLOR1_REG, 5, 1, 0),
410SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLOR1_REG, 6, 1, 0),
411SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLOR1_REG, 7, 1, 0),
412SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLOR2_REG, 0, 1, 0),
413SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLOR2_REG, 1, 1, 0),
414SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLOR2_REG, 2, 1, 0),
415SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLOR2_REG, 3, 1, 0),
416SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLOR2_REG, 4, 1, 0),
417SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLOR2_REG, 5, 1, 0),
418SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLOR2_REG, 6, 1, 0),
419SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLOR2_REG, 7, 1, 0),
420SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 7, 0, 0),
421};
422
423static const struct snd_kcontrol_new lm49453_port1_tx1_mixer[] = {
424SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX1_REG, 0, 1, 0),
425SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX1_REG, 1, 1, 0),
426SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX1_REG, 2, 1, 0),
427SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX1_REG, 3, 1, 0),
428SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX1_REG, 4, 1, 0),
429SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX1_REG, 5, 1, 0),
430SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_PORT1_TX1_REG, 6, 1, 0),
431SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_PORT1_TX1_REG, 7, 1, 0),
432};
433
434static const struct snd_kcontrol_new lm49453_port1_tx2_mixer[] = {
435SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX2_REG, 0, 1, 0),
436SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX2_REG, 1, 1, 0),
437SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX2_REG, 2, 1, 0),
438SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX2_REG, 3, 1, 0),
439SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX2_REG, 4, 1, 0),
440SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX2_REG, 5, 1, 0),
441SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_PORT1_TX2_REG, 6, 1, 0),
442SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_PORT1_TX2_REG, 7, 1, 0),
443};
444
445static const struct snd_kcontrol_new lm49453_port1_tx3_mixer[] = {
446SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX3_REG, 0, 1, 0),
447SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX3_REG, 1, 1, 0),
448SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX3_REG, 2, 1, 0),
449SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX3_REG, 3, 1, 0),
450SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX3_REG, 4, 1, 0),
451SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX3_REG, 5, 1, 0),
452SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_PORT1_TX3_REG, 6, 1, 0),
453};
454
455static const struct snd_kcontrol_new lm49453_port1_tx4_mixer[] = {
456SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX4_REG, 0, 1, 0),
457SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX4_REG, 1, 1, 0),
458SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX4_REG, 2, 1, 0),
459SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX4_REG, 3, 1, 0),
460SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX4_REG, 4, 1, 0),
461SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX4_REG, 5, 1, 0),
462SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_PORT1_TX4_REG, 6, 1, 0),
463};
464
465static const struct snd_kcontrol_new lm49453_port1_tx5_mixer[] = {
466SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX5_REG, 0, 1, 0),
467SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX5_REG, 1, 1, 0),
468SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX5_REG, 2, 1, 0),
469SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX5_REG, 3, 1, 0),
470SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX5_REG, 4, 1, 0),
471SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX5_REG, 5, 1, 0),
472SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_PORT1_TX5_REG, 6, 1, 0),
473};
474
475static const struct snd_kcontrol_new lm49453_port1_tx6_mixer[] = {
476SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX6_REG, 0, 1, 0),
477SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX6_REG, 1, 1, 0),
478SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX6_REG, 2, 1, 0),
479SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX6_REG, 3, 1, 0),
480SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX6_REG, 4, 1, 0),
481SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX6_REG, 5, 1, 0),
482SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_PORT1_TX6_REG, 6, 1, 0),
483};
484
485static const struct snd_kcontrol_new lm49453_port1_tx7_mixer[] = {
486SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX7_REG, 0, 1, 0),
487SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX7_REG, 1, 1, 0),
488SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX7_REG, 2, 1, 0),
489SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX7_REG, 3, 1, 0),
490SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX7_REG, 4, 1, 0),
491SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX7_REG, 5, 1, 0),
492SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_PORT1_TX7_REG, 6, 1, 0),
493};
494
495static const struct snd_kcontrol_new lm49453_port1_tx8_mixer[] = {
496SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX8_REG, 0, 1, 0),
497SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX8_REG, 1, 1, 0),
498SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX8_REG, 2, 1, 0),
499SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX8_REG, 3, 1, 0),
500SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX8_REG, 4, 1, 0),
501SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX8_REG, 5, 1, 0),
502SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_PORT1_TX8_REG, 6, 1, 0),
503};
504
505static const struct snd_kcontrol_new lm49453_port2_tx1_mixer[] = {
506SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT2_TX1_REG, 0, 1, 0),
507SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT2_TX1_REG, 1, 1, 0),
508SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT2_TX1_REG, 2, 1, 0),
509SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT2_TX1_REG, 3, 1, 0),
510SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT2_TX1_REG, 4, 1, 0),
511SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT2_TX1_REG, 5, 1, 0),
512SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_PORT2_TX1_REG, 6, 1, 0),
513SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_PORT2_TX1_REG, 7, 1, 0),
514};
515
516static const struct snd_kcontrol_new lm49453_port2_tx2_mixer[] = {
517SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT2_TX2_REG, 0, 1, 0),
518SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT2_TX2_REG, 1, 1, 0),
519SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT2_TX2_REG, 2, 1, 0),
520SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT2_TX2_REG, 3, 1, 0),
521SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT2_TX2_REG, 4, 1, 0),
522SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT2_TX2_REG, 5, 1, 0),
523SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_PORT2_TX2_REG, 6, 1, 0),
524SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_PORT2_TX2_REG, 7, 1, 0),
525};
526
527/* TLV Declarations */
88ac4392
MSR		 528static const DECLARE_TLV_DB_SCALE(adc_dac_tlv, -7650, 150, 1);
529static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 200, 1);
530static const DECLARE_TLV_DB_SCALE(port_tlv, -1800, 600, 0);
531static const DECLARE_TLV_DB_SCALE(stn_tlv, -7200, 150, 0);
dbf7a733
SR		 532
533static const struct snd_kcontrol_new lm49453_sidetone_mixer_controls[] = {
534/* Sidetone supports mono only */
535SOC_DAPM_SINGLE_TLV("Sidetone ADCL Volume", LM49453_P0_STN_VOL_ADCL_REG,
88ac4392 536 0, 0x3F, 0, stn_tlv),
dbf7a733 537SOC_DAPM_SINGLE_TLV("Sidetone ADCR Volume", LM49453_P0_STN_VOL_ADCR_REG,
88ac4392 538 0, 0x3F, 0, stn_tlv),
dbf7a733 539SOC_DAPM_SINGLE_TLV("Sidetone DMIC1L Volume", LM49453_P0_STN_VOL_DMIC1L_REG,
88ac4392 540 0, 0x3F, 0, stn_tlv),
dbf7a733 541SOC_DAPM_SINGLE_TLV("Sidetone DMIC1R Volume", LM49453_P0_STN_VOL_DMIC1R_REG,
88ac4392 542 0, 0x3F, 0, stn_tlv),
dbf7a733 543SOC_DAPM_SINGLE_TLV("Sidetone DMIC2L Volume", LM49453_P0_STN_VOL_DMIC2L_REG,
88ac4392 544 0, 0x3F, 0, stn_tlv),
dbf7a733 545SOC_DAPM_SINGLE_TLV("Sidetone DMIC2R Volume", LM49453_P0_STN_VOL_DMIC2R_REG,
88ac4392 546 0, 0x3F, 0, stn_tlv),
dbf7a733
SR		 547};
548
549static const struct snd_kcontrol_new lm49453_snd_controls[] = {
550 /* mic1 and mic2 supports mono only */
88ac4392
MSR		 551 SOC_SINGLE_TLV("Mic1 Volume", LM49453_P0_MICL_REG, 0, 15, 0, mic_tlv),
552 SOC_SINGLE_TLV("Mic2 Volume", LM49453_P0_MICR_REG, 0, 15, 0, mic_tlv),
553
554 SOC_SINGLE_TLV("ADCL Volume", LM49453_P0_ADC_LEVELL_REG, 0, 63,
555 0, adc_dac_tlv),
556 SOC_SINGLE_TLV("ADCR Volume", LM49453_P0_ADC_LEVELR_REG, 0, 63,
557 0, adc_dac_tlv),
dbf7a733
SR		 558
559 SOC_DOUBLE_R_TLV("DMIC1 Volume", LM49453_P0_DMIC1_LEVELL_REG,
88ac4392 560 LM49453_P0_DMIC1_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
dbf7a733 561 SOC_DOUBLE_R_TLV("DMIC2 Volume", LM49453_P0_DMIC2_LEVELL_REG,
88ac4392 562 LM49453_P0_DMIC2_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
dbf7a733
SR		 563
564 SOC_DAPM_ENUM("Mic2Mode", lm49453_mic2mode_enum),
565 SOC_DAPM_ENUM("DMIC12 SRC", lm49453_dmic12_cfg_enum),
566 SOC_DAPM_ENUM("DMIC34 SRC", lm49453_dmic34_cfg_enum),
567
568 /* Capture path filter enable */
569 SOC_SINGLE("DMIC1 HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG,
570 0, 1, 0),
571 SOC_SINGLE("DMIC2 HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG,
572 1, 1, 0),
573 SOC_SINGLE("ADC HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG,
574 2, 1, 0),
575
576 SOC_DOUBLE_R_TLV("DAC HP Volume", LM49453_P0_DAC_HP_LEVELL_REG,
88ac4392 577 LM49453_P0_DAC_HP_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
dbf7a733 578 SOC_DOUBLE_R_TLV("DAC LO Volume", LM49453_P0_DAC_LO_LEVELL_REG,
88ac4392 579 LM49453_P0_DAC_LO_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
dbf7a733 580 SOC_DOUBLE_R_TLV("DAC LS Volume", LM49453_P0_DAC_LS_LEVELL_REG,
88ac4392 581 LM49453_P0_DAC_LS_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
dbf7a733 582 SOC_DOUBLE_R_TLV("DAC HA Volume", LM49453_P0_DAC_HA_LEVELL_REG,
88ac4392 583 LM49453_P0_DAC_HA_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
dbf7a733
SR		 584
585 SOC_SINGLE_TLV("EP Volume", LM49453_P0_DAC_LS_LEVELL_REG,
88ac4392 586 0, 63, 0, adc_dac_tlv),
dbf7a733
SR		 587
588 SOC_SINGLE_TLV("PORT1_1_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
589 0, 3, 0, port_tlv),
590 SOC_SINGLE_TLV("PORT1_2_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
591 2, 3, 0, port_tlv),
592 SOC_SINGLE_TLV("PORT1_3_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
593 4, 3, 0, port_tlv),
594 SOC_SINGLE_TLV("PORT1_4_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
595 6, 3, 0, port_tlv),
596 SOC_SINGLE_TLV("PORT1_5_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
597 0, 3, 0, port_tlv),
598 SOC_SINGLE_TLV("PORT1_6_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
599 2, 3, 0, port_tlv),
600 SOC_SINGLE_TLV("PORT1_7_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
601 4, 3, 0, port_tlv),
602 SOC_SINGLE_TLV("PORT1_8_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
603 6, 3, 0, port_tlv),
604
605 SOC_SINGLE_TLV("PORT2_1_RX_LVL Volume", LM49453_P0_PORT2_RX_LVL_REG,
606 0, 3, 0, port_tlv),
607 SOC_SINGLE_TLV("PORT2_2_RX_LVL Volume", LM49453_P0_PORT2_RX_LVL_REG,
608 2, 3, 0, port_tlv),
609
610 SOC_SINGLE("Port1 Playback Switch", LM49453_P0_AUDIO_PORT1_BASIC_REG,
611 1, 1, 0),
612 SOC_SINGLE("Port2 Playback Switch", LM49453_P0_AUDIO_PORT2_BASIC_REG,
613 1, 1, 0),
614 SOC_SINGLE("Port1 Capture Switch", LM49453_P0_AUDIO_PORT1_BASIC_REG,
615 2, 1, 0),
616 SOC_SINGLE("Port2 Capture Switch", LM49453_P0_AUDIO_PORT2_BASIC_REG,
617 2, 1, 0)
618
619};
620
621/* DAPM widgets */
622static const struct snd_soc_dapm_widget lm49453_dapm_widgets[] = {
623
624 /* All end points HP,EP, LS, Lineout and Haptic */
625 SND_SOC_DAPM_OUTPUT("HPOUTL"),
626 SND_SOC_DAPM_OUTPUT("HPOUTR"),
627 SND_SOC_DAPM_OUTPUT("EPOUT"),
628 SND_SOC_DAPM_OUTPUT("LSOUTL"),
629 SND_SOC_DAPM_OUTPUT("LSOUTR"),
630 SND_SOC_DAPM_OUTPUT("LOOUTR"),
631 SND_SOC_DAPM_OUTPUT("LOOUTL"),
632 SND_SOC_DAPM_OUTPUT("HAOUTL"),
633 SND_SOC_DAPM_OUTPUT("HAOUTR"),
634
635 SND_SOC_DAPM_INPUT("AMIC1"),
636 SND_SOC_DAPM_INPUT("AMIC2"),
637 SND_SOC_DAPM_INPUT("DMIC1DAT"),
638 SND_SOC_DAPM_INPUT("DMIC2DAT"),
639 SND_SOC_DAPM_INPUT("AUXL"),
640 SND_SOC_DAPM_INPUT("AUXR"),
641
642 SND_SOC_DAPM_PGA("PORT1_1_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
643 SND_SOC_DAPM_PGA("PORT1_2_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
644 SND_SOC_DAPM_PGA("PORT1_3_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
645 SND_SOC_DAPM_PGA("PORT1_4_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
646 SND_SOC_DAPM_PGA("PORT1_5_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
647 SND_SOC_DAPM_PGA("PORT1_6_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
648 SND_SOC_DAPM_PGA("PORT1_7_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
649 SND_SOC_DAPM_PGA("PORT1_8_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
650 SND_SOC_DAPM_PGA("PORT2_1_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
651 SND_SOC_DAPM_PGA("PORT2_2_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
652
653 SND_SOC_DAPM_SUPPLY("AMIC1Bias", LM49453_P0_MICL_REG, 6, 0, NULL, 0),
654 SND_SOC_DAPM_SUPPLY("AMIC2Bias", LM49453_P0_MICR_REG, 6, 0, NULL, 0),
655
656 /* playback path driver enables */
657 SND_SOC_DAPM_OUT_DRV("Headset Switch",
658 LM49453_P0_PMC_SETUP_REG, 0, 0, NULL, 0),
659 SND_SOC_DAPM_OUT_DRV("Earpiece Switch",
660 LM49453_P0_EP_REG, 0, 0, NULL, 0),
661 SND_SOC_DAPM_OUT_DRV("Speaker Left Switch",
662 LM49453_P0_DIS_PKVL_FB_REG, 0, 1, NULL, 0),
663 SND_SOC_DAPM_OUT_DRV("Speaker Right Switch",
664 LM49453_P0_DIS_PKVL_FB_REG, 1, 1, NULL, 0),
665 SND_SOC_DAPM_OUT_DRV("Haptic Left Switch",
666 LM49453_P0_DIS_PKVL_FB_REG, 2, 1, NULL, 0),
667 SND_SOC_DAPM_OUT_DRV("Haptic Right Switch",
668 LM49453_P0_DIS_PKVL_FB_REG, 3, 1, NULL, 0),
669
670 /* DAC */
671 SND_SOC_DAPM_DAC("HPL DAC", "Headset", SND_SOC_NOPM, 0, 0),
672 SND_SOC_DAPM_DAC("HPR DAC", "Headset", SND_SOC_NOPM, 0, 0),
673 SND_SOC_DAPM_DAC("LSL DAC", "Speaker", SND_SOC_NOPM, 0, 0),
674 SND_SOC_DAPM_DAC("LSR DAC", "Speaker", SND_SOC_NOPM, 0, 0),
675 SND_SOC_DAPM_DAC("HAL DAC", "Haptic", SND_SOC_NOPM, 0, 0),
676 SND_SOC_DAPM_DAC("HAR DAC", "Haptic", SND_SOC_NOPM, 0, 0),
677 SND_SOC_DAPM_DAC("LOL DAC", "Lineout", SND_SOC_NOPM, 0, 0),
678 SND_SOC_DAPM_DAC("LOR DAC", "Lineout", SND_SOC_NOPM, 0, 0),
679
680
681 SND_SOC_DAPM_PGA("AUXL Input",
682 LM49453_P0_ANALOG_MIXER_ADC_REG, 2, 0, NULL, 0),
683 SND_SOC_DAPM_PGA("AUXR Input",
684 LM49453_P0_ANALOG_MIXER_ADC_REG, 3, 0, NULL, 0),
685
686 SND_SOC_DAPM_PGA("Sidetone", SND_SOC_NOPM, 0, 0, NULL, 0),
687
688 /* ADC */
689 SND_SOC_DAPM_ADC("DMIC1 Left", "Capture", SND_SOC_NOPM, 1, 0),
690 SND_SOC_DAPM_ADC("DMIC1 Right", "Capture", SND_SOC_NOPM, 1, 0),
691 SND_SOC_DAPM_ADC("DMIC2 Left", "Capture", SND_SOC_NOPM, 1, 0),
692 SND_SOC_DAPM_ADC("DMIC2 Right", "Capture", SND_SOC_NOPM, 1, 0),
693
694 SND_SOC_DAPM_ADC("ADC Left", "Capture", SND_SOC_NOPM, 1, 0),
695 SND_SOC_DAPM_ADC("ADC Right", "Capture", SND_SOC_NOPM, 0, 0),
696
697 SND_SOC_DAPM_MUX("ADCL Mux", SND_SOC_NOPM, 0, 0,
698 &lm49453_adcl_mux_control),
699 SND_SOC_DAPM_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0,
700 &lm49453_adcr_mux_control),
701
702 SND_SOC_DAPM_MUX("Mic1 Input",
703 SND_SOC_NOPM, 0, 0, &lm49453_adcl_mux_control),
704
705 SND_SOC_DAPM_MUX("Mic2 Input",
706 SND_SOC_NOPM, 0, 0, &lm49453_adcr_mux_control),
707
708 /* AIF */
709 SND_SOC_DAPM_AIF_IN("PORT1_SDI", NULL, 0,
710 LM49453_P0_PULL_CONFIG1_REG, 2, 0),
711 SND_SOC_DAPM_AIF_IN("PORT2_SDI", NULL, 0,
712 LM49453_P0_PULL_CONFIG1_REG, 6, 0),
713
714 SND_SOC_DAPM_AIF_OUT("PORT1_SDO", NULL, 0,
715 LM49453_P0_PULL_CONFIG1_REG, 3, 0),
716 SND_SOC_DAPM_AIF_OUT("PORT2_SDO", NULL, 0,
717 LM49453_P0_PULL_CONFIG1_REG, 7, 0),
718
719 /* Port1 TX controls */
720 SND_SOC_DAPM_OUT_DRV("P1_1_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
721 SND_SOC_DAPM_OUT_DRV("P1_2_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
722 SND_SOC_DAPM_OUT_DRV("P1_3_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
723 SND_SOC_DAPM_OUT_DRV("P1_4_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
724 SND_SOC_DAPM_OUT_DRV("P1_5_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
725 SND_SOC_DAPM_OUT_DRV("P1_6_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
726 SND_SOC_DAPM_OUT_DRV("P1_7_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
727 SND_SOC_DAPM_OUT_DRV("P1_8_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
728
729 /* Port2 TX controls */
730 SND_SOC_DAPM_OUT_DRV("P2_1_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
731 SND_SOC_DAPM_OUT_DRV("P2_2_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
732
733 /* Sidetone Mixer */
734 SND_SOC_DAPM_MIXER("Sidetone Mixer", SND_SOC_NOPM, 0, 0,
735 lm49453_sidetone_mixer_controls,
736 ARRAY_SIZE(lm49453_sidetone_mixer_controls)),
737
738 /* DAC MIXERS */
739 SND_SOC_DAPM_MIXER("HPL Mixer", SND_SOC_NOPM, 0, 0,
740 lm49453_headset_left_mixer,
741 ARRAY_SIZE(lm49453_headset_left_mixer)),
742 SND_SOC_DAPM_MIXER("HPR Mixer", SND_SOC_NOPM, 0, 0,
743 lm49453_headset_right_mixer,
744 ARRAY_SIZE(lm49453_headset_right_mixer)),
745 SND_SOC_DAPM_MIXER("LOL Mixer", SND_SOC_NOPM, 0, 0,
746 lm49453_lineout_left_mixer,
747 ARRAY_SIZE(lm49453_lineout_left_mixer)),
748 SND_SOC_DAPM_MIXER("LOR Mixer", SND_SOC_NOPM, 0, 0,
749 lm49453_lineout_right_mixer,
750 ARRAY_SIZE(lm49453_lineout_right_mixer)),
751 SND_SOC_DAPM_MIXER("LSL Mixer", SND_SOC_NOPM, 0, 0,
752 lm49453_speaker_left_mixer,
753 ARRAY_SIZE(lm49453_speaker_left_mixer)),
754 SND_SOC_DAPM_MIXER("LSR Mixer", SND_SOC_NOPM, 0, 0,
755 lm49453_speaker_right_mixer,
756 ARRAY_SIZE(lm49453_speaker_right_mixer)),
757 SND_SOC_DAPM_MIXER("HAL Mixer", SND_SOC_NOPM, 0, 0,
758 lm49453_haptic_left_mixer,
759 ARRAY_SIZE(lm49453_haptic_left_mixer)),
760 SND_SOC_DAPM_MIXER("HAR Mixer", SND_SOC_NOPM, 0, 0,
761 lm49453_haptic_right_mixer,
762 ARRAY_SIZE(lm49453_haptic_right_mixer)),
763
764 /* Capture Mixer */
765 SND_SOC_DAPM_MIXER("Port1_1 Mixer", SND_SOC_NOPM, 0, 0,
766 lm49453_port1_tx1_mixer,
767 ARRAY_SIZE(lm49453_port1_tx1_mixer)),
768 SND_SOC_DAPM_MIXER("Port1_2 Mixer", SND_SOC_NOPM, 0, 0,
769 lm49453_port1_tx2_mixer,
770 ARRAY_SIZE(lm49453_port1_tx2_mixer)),
771 SND_SOC_DAPM_MIXER("Port1_3 Mixer", SND_SOC_NOPM, 0, 0,
772 lm49453_port1_tx3_mixer,
773 ARRAY_SIZE(lm49453_port1_tx3_mixer)),
774 SND_SOC_DAPM_MIXER("Port1_4 Mixer", SND_SOC_NOPM, 0, 0,
775 lm49453_port1_tx4_mixer,
776 ARRAY_SIZE(lm49453_port1_tx4_mixer)),
777 SND_SOC_DAPM_MIXER("Port1_5 Mixer", SND_SOC_NOPM, 0, 0,
778 lm49453_port1_tx5_mixer,
779 ARRAY_SIZE(lm49453_port1_tx5_mixer)),
780 SND_SOC_DAPM_MIXER("Port1_6 Mixer", SND_SOC_NOPM, 0, 0,
781 lm49453_port1_tx6_mixer,
782 ARRAY_SIZE(lm49453_port1_tx6_mixer)),
783 SND_SOC_DAPM_MIXER("Port1_7 Mixer", SND_SOC_NOPM, 0, 0,
784 lm49453_port1_tx7_mixer,
785 ARRAY_SIZE(lm49453_port1_tx7_mixer)),
786 SND_SOC_DAPM_MIXER("Port1_8 Mixer", SND_SOC_NOPM, 0, 0,
787 lm49453_port1_tx8_mixer,
788 ARRAY_SIZE(lm49453_port1_tx8_mixer)),
789
790 SND_SOC_DAPM_MIXER("Port2_1 Mixer", SND_SOC_NOPM, 0, 0,
791 lm49453_port2_tx1_mixer,
792 ARRAY_SIZE(lm49453_port2_tx1_mixer)),
793 SND_SOC_DAPM_MIXER("Port2_2 Mixer", SND_SOC_NOPM, 0, 0,
794 lm49453_port2_tx2_mixer,
795 ARRAY_SIZE(lm49453_port2_tx2_mixer)),
796};
797
798static const struct snd_soc_dapm_route lm49453_audio_map[] = {
799 /* Port SDI mapping */
800 { "PORT1_1_RX", "Port1 Playback Switch", "PORT1_SDI" },
801 { "PORT1_2_RX", "Port1 Playback Switch", "PORT1_SDI" },
802 { "PORT1_3_RX", "Port1 Playback Switch", "PORT1_SDI" },
803 { "PORT1_4_RX", "Port1 Playback Switch", "PORT1_SDI" },
804 { "PORT1_5_RX", "Port1 Playback Switch", "PORT1_SDI" },
805 { "PORT1_6_RX", "Port1 Playback Switch", "PORT1_SDI" },
806 { "PORT1_7_RX", "Port1 Playback Switch", "PORT1_SDI" },
807 { "PORT1_8_RX", "Port1 Playback Switch", "PORT1_SDI" },
808
809 { "PORT2_1_RX", "Port2 Playback Switch", "PORT2_SDI" },
810 { "PORT2_2_RX", "Port2 Playback Switch", "PORT2_SDI" },
811
812 /* HP mapping */
813 { "HPL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
814 { "HPL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
815 { "HPL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
816 { "HPL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
817 { "HPL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
818 { "HPL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
819 { "HPL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
820 { "HPL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
821
822 { "HPL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
823 { "HPL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
824
825 { "HPL Mixer", "ADCL Switch", "ADC Left" },
826 { "HPL Mixer", "ADCR Switch", "ADC Right" },
827 { "HPL Mixer", "DMIC1L Switch", "DMIC1 Left" },
828 { "HPL Mixer", "DMIC1R Switch", "DMIC1 Right" },
829 { "HPL Mixer", "DMIC2L Switch", "DMIC2 Left" },
830 { "HPL Mixer", "DMIC2R Switch", "DMIC2 Right" },
831 { "HPL Mixer", "Sidetone Switch", "Sidetone" },
832
833 { "HPL DAC", NULL, "HPL Mixer" },
834
835 { "HPR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
836 { "HPR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
837 { "HPR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
838 { "HPR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
839 { "HPR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
840 { "HPR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
841 { "HPR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
842 { "HPR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
843
844 /* Port 2 */
845 { "HPR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
846 { "HPR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
847
848 { "HPR Mixer", "ADCL Switch", "ADC Left" },
849 { "HPR Mixer", "ADCR Switch", "ADC Right" },
850 { "HPR Mixer", "DMIC1L Switch", "DMIC1 Left" },
851 { "HPR Mixer", "DMIC1R Switch", "DMIC1 Right" },
852 { "HPR Mixer", "DMIC2L Switch", "DMIC2 Left" },
853 { "HPR Mixer", "DMIC2L Switch", "DMIC2 Right" },
854 { "HPR Mixer", "Sidetone Switch", "Sidetone" },
855
856 { "HPR DAC", NULL, "HPR Mixer" },
857
858 { "HPOUTL", "Headset Switch", "HPL DAC"},
859 { "HPOUTR", "Headset Switch", "HPR DAC"},
860
861 /* EP map */
862 { "EPOUT", "Earpiece Switch", "HPL DAC" },
863
864 /* Speaker map */
865 { "LSL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
866 { "LSL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
867 { "LSL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
868 { "LSL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
869 { "LSL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
870 { "LSL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
871 { "LSL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
872 { "LSL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
873
874 /* Port 2 */
875 { "LSL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
876 { "LSL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
877
878 { "LSL Mixer", "ADCL Switch", "ADC Left" },
879 { "LSL Mixer", "ADCR Switch", "ADC Right" },
880 { "LSL Mixer", "DMIC1L Switch", "DMIC1 Left" },
881 { "LSL Mixer", "DMIC1R Switch", "DMIC1 Right" },
882 { "LSL Mixer", "DMIC2L Switch", "DMIC2 Left" },
883 { "LSL Mixer", "DMIC2R Switch", "DMIC2 Right" },
884 { "LSL Mixer", "Sidetone Switch", "Sidetone" },
885
886 { "LSL DAC", NULL, "LSL Mixer" },
887
888 { "LSR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
889 { "LSR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
890 { "LSR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
891 { "LSR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
892 { "LSR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
893 { "LSR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
894 { "LSR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
895 { "LSR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
896
897 /* Port 2 */
898 { "LSR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
899 { "LSR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
900
901 { "LSR Mixer", "ADCL Switch", "ADC Left" },
902 { "LSR Mixer", "ADCR Switch", "ADC Right" },
903 { "LSR Mixer", "DMIC1L Switch", "DMIC1 Left" },
904 { "LSR Mixer", "DMIC1R Switch", "DMIC1 Right" },
905 { "LSR Mixer", "DMIC2L Switch", "DMIC2 Left" },
906 { "LSR Mixer", "DMIC2R Switch", "DMIC2 Right" },
907 { "LSR Mixer", "Sidetone Switch", "Sidetone" },
908
909 { "LSR DAC", NULL, "LSR Mixer" },
910
911 { "LSOUTL", "Speaker Left Switch", "LSL DAC"},
912 { "LSOUTR", "Speaker Left Switch", "LSR DAC"},
913
914 /* Haptic map */
915 { "HAL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
916 { "HAL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
917 { "HAL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
918 { "HAL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
919 { "HAL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
920 { "HAL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
921 { "HAL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
922 { "HAL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
923
924 /* Port 2 */
925 { "HAL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
926 { "HAL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
927
928 { "HAL Mixer", "ADCL Switch", "ADC Left" },
929 { "HAL Mixer", "ADCR Switch", "ADC Right" },
930 { "HAL Mixer", "DMIC1L Switch", "DMIC1 Left" },
931 { "HAL Mixer", "DMIC1R Switch", "DMIC1 Right" },
932 { "HAL Mixer", "DMIC2L Switch", "DMIC2 Left" },
933 { "HAL Mixer", "DMIC2R Switch", "DMIC2 Right" },
934 { "HAL Mixer", "Sidetone Switch", "Sidetone" },
935
936 { "HAL DAC", NULL, "HAL Mixer" },
937
938 { "HAR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
939 { "HAR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
940 { "HAR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
941 { "HAR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
942 { "HAR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
943 { "HAR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
944 { "HAR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
945 { "HAR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
946
947 /* Port 2 */
948 { "HAR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
949 { "HAR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
950
951 { "HAR Mixer", "ADCL Switch", "ADC Left" },
952 { "HAR Mixer", "ADCR Switch", "ADC Right" },
953 { "HAR Mixer", "DMIC1L Switch", "DMIC1 Left" },
954 { "HAR Mixer", "DMIC1R Switch", "DMIC1 Right" },
955 { "HAR Mixer", "DMIC2L Switch", "DMIC2 Left" },
956 { "HAR Mixer", "DMIC2R Switch", "DMIC2 Right" },
957 { "HAR Mixer", "Sideton Switch", "Sidetone" },
958
959 { "HAR DAC", NULL, "HAR Mixer" },
960
961 { "HAOUTL", "Haptic Left Switch", "HAL DAC" },
962 { "HAOUTR", "Haptic Right Switch", "HAR DAC" },
963
964 /* Lineout map */
965 { "LOL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
966 { "LOL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
967 { "LOL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
968 { "LOL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
969 { "LOL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
970 { "LOL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
971 { "LOL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
972 { "LOL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
973
974 /* Port 2 */
975 { "LOL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
976 { "LOL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
977
978 { "LOL Mixer", "ADCL Switch", "ADC Left" },
979 { "LOL Mixer", "ADCR Switch", "ADC Right" },
980 { "LOL Mixer", "DMIC1L Switch", "DMIC1 Left" },
981 { "LOL Mixer", "DMIC1R Switch", "DMIC1 Right" },
982 { "LOL Mixer", "DMIC2L Switch", "DMIC2 Left" },
983 { "LOL Mixer", "DMIC2R Switch", "DMIC2 Right" },
984 { "LOL Mixer", "Sidetone Switch", "Sidetone" },
985
986 { "LOL DAC", NULL, "LOL Mixer" },
987
988 { "LOR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
989 { "LOR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
990 { "LOR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
991 { "LOR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
992 { "LOR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
993 { "LOR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
994 { "LOR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
995 { "LOR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
996
997 /* Port 2 */
998 { "LOR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
999 { "LOR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
1000
1001 { "LOR Mixer", "ADCL Switch", "ADC Left" },
1002 { "LOR Mixer", "ADCR Switch", "ADC Right" },
1003 { "LOR Mixer", "DMIC1L Switch", "DMIC1 Left" },
1004 { "LOR Mixer", "DMIC1R Switch", "DMIC1 Right" },
1005 { "LOR Mixer", "DMIC2L Switch", "DMIC2 Left" },
1006 { "LOR Mixer", "DMIC2R Switch", "DMIC2 Right" },
1007 { "LOR Mixer", "Sidetone Switch", "Sidetone" },
1008
1009 { "LOR DAC", NULL, "LOR Mixer" },
1010
1011 { "LOOUTL", NULL, "LOL DAC" },
1012 { "LOOUTR", NULL, "LOR DAC" },
1013
1014 /* TX map */
1015 /* Port1 mappings */
1016 { "Port1_1 Mixer", "ADCL Switch", "ADC Left" },
1017 { "Port1_1 Mixer", "ADCR Switch", "ADC Right" },
1018 { "Port1_1 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1019 { "Port1_1 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1020 { "Port1_1 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1021 { "Port1_1 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1022
1023 { "Port1_2 Mixer", "ADCL Switch", "ADC Left" },
1024 { "Port1_2 Mixer", "ADCR Switch", "ADC Right" },
1025 { "Port1_2 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1026 { "Port1_2 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1027 { "Port1_2 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1028 { "Port1_2 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1029
1030 { "Port1_3 Mixer", "ADCL Switch", "ADC Left" },
1031 { "Port1_3 Mixer", "ADCR Switch", "ADC Right" },
1032 { "Port1_3 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1033 { "Port1_3 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1034 { "Port1_3 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1035 { "Port1_3 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1036
1037 { "Port1_4 Mixer", "ADCL Switch", "ADC Left" },
1038 { "Port1_4 Mixer", "ADCR Switch", "ADC Right" },
1039 { "Port1_4 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1040 { "Port1_4 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1041 { "Port1_4 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1042 { "Port1_4 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1043
1044 { "Port1_5 Mixer", "ADCL Switch", "ADC Left" },
1045 { "Port1_5 Mixer", "ADCR Switch", "ADC Right" },
1046 { "Port1_5 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1047 { "Port1_5 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1048 { "Port1_5 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1049 { "Port1_5 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1050
1051 { "Port1_6 Mixer", "ADCL Switch", "ADC Left" },
1052 { "Port1_6 Mixer", "ADCR Switch", "ADC Right" },
1053 { "Port1_6 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1054 { "Port1_6 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1055 { "Port1_6 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1056 { "Port1_6 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1057
1058 { "Port1_7 Mixer", "ADCL Switch", "ADC Left" },
1059 { "Port1_7 Mixer", "ADCR Switch", "ADC Right" },
1060 { "Port1_7 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1061 { "Port1_7 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1062 { "Port1_7 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1063 { "Port1_7 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1064
1065 { "Port1_8 Mixer", "ADCL Switch", "ADC Left" },
1066 { "Port1_8 Mixer", "ADCR Switch", "ADC Right" },
1067 { "Port1_8 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1068 { "Port1_8 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1069 { "Port1_8 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1070 { "Port1_8 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1071
1072 { "Port2_1 Mixer", "ADCL Switch", "ADC Left" },
1073 { "Port2_1 Mixer", "ADCR Switch", "ADC Right" },
1074 { "Port2_1 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1075 { "Port2_1 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1076 { "Port2_1 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1077 { "Port2_1 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1078
1079 { "Port2_2 Mixer", "ADCL Switch", "ADC Left" },
1080 { "Port2_2 Mixer", "ADCR Switch", "ADC Right" },
1081 { "Port2_2 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1082 { "Port2_2 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1083 { "Port2_2 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1084 { "Port2_2 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1085
1086 { "P1_1_TX", NULL, "Port1_1 Mixer" },
1087 { "P1_2_TX", NULL, "Port1_2 Mixer" },
1088 { "P1_3_TX", NULL, "Port1_3 Mixer" },
1089 { "P1_4_TX", NULL, "Port1_4 Mixer" },
1090 { "P1_5_TX", NULL, "Port1_5 Mixer" },
1091 { "P1_6_TX", NULL, "Port1_6 Mixer" },
1092 { "P1_7_TX", NULL, "Port1_7 Mixer" },
1093 { "P1_8_TX", NULL, "Port1_8 Mixer" },
1094
1095 { "P2_1_TX", NULL, "Port2_1 Mixer" },
1096 { "P2_2_TX", NULL, "Port2_2 Mixer" },
1097
1098 { "PORT1_SDO", "Port1 Capture Switch", "P1_1_TX"},
1099 { "PORT1_SDO", "Port1 Capture Switch", "P1_2_TX"},
1100 { "PORT1_SDO", "Port1 Capture Switch", "P1_3_TX"},
1101 { "PORT1_SDO", "Port1 Capture Switch", "P1_4_TX"},
1102 { "PORT1_SDO", "Port1 Capture Switch", "P1_5_TX"},
1103 { "PORT1_SDO", "Port1 Capture Switch", "P1_6_TX"},
1104 { "PORT1_SDO", "Port1 Capture Switch", "P1_7_TX"},
1105 { "PORT1_SDO", "Port1 Capture Switch", "P1_8_TX"},
1106
1107 { "PORT2_SDO", "Port2 Capture Switch", "P2_1_TX"},
1108 { "PORT2_SDO", "Port2 Capture Switch", "P2_2_TX"},
1109
1110 { "Mic1 Input", NULL, "AMIC1" },
1111 { "Mic2 Input", NULL, "AMIC2" },
1112
1113 { "AUXL Input", NULL, "AUXL" },
1114 { "AUXR Input", NULL, "AUXR" },
1115
1116 /* AUX connections */
1117 { "ADCL Mux", "Aux_L", "AUXL Input" },
1118 { "ADCL Mux", "MIC1", "Mic1 Input" },
1119
1120 { "ADCR Mux", "Aux_R", "AUXR Input" },
1121 { "ADCR Mux", "MIC2", "Mic2 Input" },
1122
1123 /* ADC connection */
1124 { "ADC Left", NULL, "ADCL Mux"},
1125 { "ADC Right", NULL, "ADCR Mux"},
1126
1127 { "DMIC1 Left", NULL, "DMIC1DAT"},
1128 { "DMIC1 Right", NULL, "DMIC1DAT"},
1129 { "DMIC2 Left", NULL, "DMIC2DAT"},
1130 { "DMIC2 Right", NULL, "DMIC2DAT"},
1131
1132 /* Sidetone map */
1133 { "Sidetone Mixer", NULL, "ADC Left" },
1134 { "Sidetone Mixer", NULL, "ADC Right" },
1135 { "Sidetone Mixer", NULL, "DMIC1 Left" },
1136 { "Sidetone Mixer", NULL, "DMIC1 Right" },
1137 { "Sidetone Mixer", NULL, "DMIC2 Left" },
1138 { "Sidetone Mixer", NULL, "DMIC2 Right" },
1139
1140 { "Sidetone", "Sidetone Switch", "Sidetone Mixer" },
1141};
1142
1143static int lm49453_hw_params(struct snd_pcm_substream *substream,
1144 struct snd_pcm_hw_params *params,
1145 struct snd_soc_dai *dai)
1146{
e6968a17 1147 struct snd_soc_codec *codec = dai->codec;
dbf7a733
SR		 1148 struct lm49453_priv *lm49453 = snd_soc_codec_get_drvdata(codec);
1149 u16 clk_div = 0;
1150
1151 lm49453->fs_rate = params_rate(params);
1152
1153 /* Setting DAC clock dividers based on substream sample rate. */
1154 switch (lm49453->fs_rate) {
1155 case 8000:
1156 case 16000:
1157 case 32000:
1158 case 24000:
1159 case 48000:
1160 clk_div = 256;
1161 break;
1162 case 11025:
1163 case 22050:
1164 case 44100:
1165 clk_div = 216;
1166 break;
1167 case 96000:
1168 clk_div = 127;
1169 break;
1170 default:
1171 return -EINVAL;
1172 }
1173
1174 snd_soc_write(codec, LM49453_P0_ADC_CLK_DIV_REG, clk_div);
1175 snd_soc_write(codec, LM49453_P0_DAC_HP_CLK_DIV_REG, clk_div);
1176
1177 return 0;
1178}
1179
1180static int lm49453_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
1181{
1182 struct snd_soc_codec *codec = codec_dai->codec;
1183
7e811ae7 1184 u16 aif_val;
dbf7a733
SR		 1185 int mode = 0;
1186 int clk_phase = 0;
1187 int clk_shift = 0;
1188
1189 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1190 case SND_SOC_DAIFMT_CBS_CFS:
7e811ae7 1191 aif_val = 0;
dbf7a733
SR		 1192 break;
1193 case SND_SOC_DAIFMT_CBS_CFM:
7e811ae7 1194 aif_val = LM49453_AUDIO_PORT1_BASIC_SYNC_MS;
dbf7a733
SR		 1195 break;
1196 case SND_SOC_DAIFMT_CBM_CFS:
7e811ae7 1197 aif_val = LM49453_AUDIO_PORT1_BASIC_CLK_MS;
dbf7a733
SR		 1198 break;
1199 case SND_SOC_DAIFMT_CBM_CFM:
1200 aif_val = LM49453_AUDIO_PORT1_BASIC_CLK_MS |
7e811ae7 1201 LM49453_AUDIO_PORT1_BASIC_SYNC_MS;
dbf7a733
SR		 1202 break;
1203 default:
1204 return -EINVAL;
1205 }
1206
1207
1208 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1209 case SND_SOC_DAIFMT_I2S:
1210 break;
1211 case SND_SOC_DAIFMT_DSP_A:
1212 mode = 1;
1213 clk_phase = (1 << 5);
1214 clk_shift = 1;
1215 break;
1216 case SND_SOC_DAIFMT_DSP_B:
1217 mode = 1;
1218 clk_phase = (1 << 5);
1219 clk_shift = 0;
1220 break;
1221 default:
1222 return -EINVAL;
1223 }
1224
1225 snd_soc_update_bits(codec, LM49453_P0_AUDIO_PORT1_BASIC_REG,
ec20f2f8 1226 LM49453_AUDIO_PORT1_BASIC_FMT_MASK|BIT(0)|BIT(5),
dbf7a733
SR		 1227 (aif_val | mode | clk_phase));
1228
1229 snd_soc_write(codec, LM49453_P0_AUDIO_PORT1_RX_MSB_REG, clk_shift);
1230
1231 return 0;
1232}
1233
1234static int lm49453_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
1235 unsigned int freq, int dir)
1236{
1237 struct snd_soc_codec *codec = dai->codec;
1238 u16 pll_clk = 0;
1239
1240 switch (freq) {
1241 case 12288000:
1242 case 26000000:
1243 case 19200000:
1244 /* pll clk slection */
1245 pll_clk = 0;
1246 break;
1247 case 48000:
1248 case 32576:
1249 /* fll clk slection */
1250 pll_clk = BIT(4);
1251 return 0;
1252 default:
1253 return -EINVAL;
1254 }
1255
1256 snd_soc_update_bits(codec, LM49453_P0_PMC_SETUP_REG, BIT(4), pll_clk);
1257
1258 return 0;
1259}
1260
1261static int lm49453_hp_mute(struct snd_soc_dai *dai, int mute)
1262{
1263 snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(1)|BIT(0),
1264 (mute ? (BIT(1)|BIT(0)) : 0));
1265 return 0;
1266}
1267
1268static int lm49453_lo_mute(struct snd_soc_dai *dai, int mute)
1269{
1270 snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(3)|BIT(2),
1271 (mute ? (BIT(3)|BIT(2)) : 0));
1272 return 0;
1273}
1274
1275static int lm49453_ls_mute(struct snd_soc_dai *dai, int mute)
1276{
1277 snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(5)|BIT(4),
1278 (mute ? (BIT(5)|BIT(4)) : 0));
1279 return 0;
1280}
1281
1282static int lm49453_ep_mute(struct snd_soc_dai *dai, int mute)
1283{
1284 snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(4),
1285 (mute ? BIT(4) : 0));
1286 return 0;
1287}
1288
1289static int lm49453_ha_mute(struct snd_soc_dai *dai, int mute)
1290{
1291 snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(7)|BIT(6),
1292 (mute ? (BIT(7)|BIT(6)) : 0));
1293 return 0;
1294}
1295
1296static int lm49453_set_bias_level(struct snd_soc_codec *codec,
1297 enum snd_soc_bias_level level)
1298{
1299 struct lm49453_priv *lm49453 = snd_soc_codec_get_drvdata(codec);
1300
1301 switch (level) {
1302 case SND_SOC_BIAS_ON:
1303 case SND_SOC_BIAS_PREPARE:
1304 break;
1305
1306 case SND_SOC_BIAS_STANDBY:
1307 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
1308 regcache_sync(lm49453->regmap);
1309
1310 snd_soc_update_bits(codec, LM49453_P0_PMC_SETUP_REG,
1311 LM49453_PMC_SETUP_CHIP_EN, LM49453_CHIP_EN);
1312 break;
1313
1314 case SND_SOC_BIAS_OFF:
1315 snd_soc_update_bits(codec, LM49453_P0_PMC_SETUP_REG,
1316 LM49453_PMC_SETUP_CHIP_EN, 0);
1317 break;
1318 }
1319
1320 codec->dapm.bias_level = level;
1321
1322 return 0;
1323}
1324
1325/* Formates supported by LM49453 driver. */
1326#define LM49453_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1327 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1328
1329static struct snd_soc_dai_ops lm49453_headset_dai_ops = {
1330 .hw_params = lm49453_hw_params,
1331 .set_sysclk = lm49453_set_dai_sysclk,
1332 .set_fmt = lm49453_set_dai_fmt,
1333 .digital_mute = lm49453_hp_mute,
1334};
1335
1336static struct snd_soc_dai_ops lm49453_speaker_dai_ops = {
1337 .hw_params = lm49453_hw_params,
1338 .set_sysclk = lm49453_set_dai_sysclk,
1339 .set_fmt = lm49453_set_dai_fmt,
1340 .digital_mute = lm49453_ls_mute,
1341};
1342
1343static struct snd_soc_dai_ops lm49453_haptic_dai_ops = {
1344 .hw_params = lm49453_hw_params,
1345 .set_sysclk = lm49453_set_dai_sysclk,
1346 .set_fmt = lm49453_set_dai_fmt,
1347 .digital_mute = lm49453_ha_mute,
1348};
1349
1350static struct snd_soc_dai_ops lm49453_ep_dai_ops = {
1351 .hw_params = lm49453_hw_params,
1352 .set_sysclk = lm49453_set_dai_sysclk,
1353 .set_fmt = lm49453_set_dai_fmt,
1354 .digital_mute = lm49453_ep_mute,
1355};
1356
1357static struct snd_soc_dai_ops lm49453_lineout_dai_ops = {
1358 .hw_params = lm49453_hw_params,
1359 .set_sysclk = lm49453_set_dai_sysclk,
1360 .set_fmt = lm49453_set_dai_fmt,
1361 .digital_mute = lm49453_lo_mute,
1362};
1363
1364/* LM49453 dai structure. */
cd86e3ce 1365static struct snd_soc_dai_driver lm49453_dai[] = {
dbf7a733
SR		 1366 {
1367 .name = "LM49453 Headset",
1368 .playback = {
1369 .stream_name = "Headset",
1370 .channels_min = 2,
1371 .channels_max = 2,
1372 .rates = SNDRV_PCM_RATE_8000_192000,
1373 .formats = LM49453_FORMATS,
1374 },
1375 .capture = {
1376 .stream_name = "Capture",
1377 .channels_min = 1,
1378 .channels_max = 5,
1379 .rates = SNDRV_PCM_RATE_8000_192000,
1380 .formats = LM49453_FORMATS,
1381 },
1382 .ops = &lm49453_headset_dai_ops,
1383 .symmetric_rates = 1,
1384 },
1385 {
1386 .name = "LM49453 Speaker",
1387 .playback = {
1388 .stream_name = "Speaker",
1389 .channels_min = 2,
1390 .channels_max = 2,
1391 .rates = SNDRV_PCM_RATE_8000_192000,
1392 .formats = LM49453_FORMATS,
1393 },
1394 .ops = &lm49453_speaker_dai_ops,
1395 },
1396 {
1397 .name = "LM49453 Haptic",
1398 .playback = {
1399 .stream_name = "Haptic",
1400 .channels_min = 2,
1401 .channels_max = 2,
1402 .rates = SNDRV_PCM_RATE_8000_192000,
1403 .formats = LM49453_FORMATS,
1404 },
1405 .ops = &lm49453_haptic_dai_ops,
1406 },
1407 {
1408 .name = "LM49453 Earpiece",
1409 .playback = {
1410 .stream_name = "Earpiece",
1411 .channels_min = 1,
1412 .channels_max = 1,
1413 .rates = SNDRV_PCM_RATE_8000_192000,
1414 .formats = LM49453_FORMATS,
1415 },
1416 .ops = &lm49453_ep_dai_ops,
1417 },
1418 {
1419 .name = "LM49453 line out",
1420 .playback = {
1421 .stream_name = "Lineout",
1422 .channels_min = 2,
1423 .channels_max = 2,
1424 .rates = SNDRV_PCM_RATE_8000_192000,
1425 .formats = LM49453_FORMATS,
1426 },
1427 .ops = &lm49453_lineout_dai_ops,
1428 },
1429};
1430
1431static int lm49453_suspend(struct snd_soc_codec *codec)
1432{
1433 lm49453_set_bias_level(codec, SND_SOC_BIAS_OFF);
1434 return 0;
1435}
1436
1437static int lm49453_resume(struct snd_soc_codec *codec)
1438{
1439 lm49453_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1440 return 0;
1441}
1442
1443static int lm49453_probe(struct snd_soc_codec *codec)
1444{
1445 struct lm49453_priv *lm49453 = snd_soc_codec_get_drvdata(codec);
1446 int ret = 0;
1447
1448 codec->control_data = lm49453->regmap;
1449
1450 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
1451 if (ret < 0) {
1452 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1453 return ret;
1454 }
1455
1456 return 0;
1457}
1458
1459/* power down chip */
1460static int lm49453_remove(struct snd_soc_codec *codec)
1461{
1462 lm49453_set_bias_level(codec, SND_SOC_BIAS_OFF);
1463 return 0;
1464}
1465
1466static struct snd_soc_codec_driver soc_codec_dev_lm49453 = {
1467 .probe = lm49453_probe,
1468 .remove = lm49453_remove,
1469 .suspend = lm49453_suspend,
1470 .resume = lm49453_resume,
1471 .set_bias_level = lm49453_set_bias_level,
1472 .controls = lm49453_snd_controls,
1473 .num_controls = ARRAY_SIZE(lm49453_snd_controls),
1474 .dapm_widgets = lm49453_dapm_widgets,
1475 .num_dapm_widgets = ARRAY_SIZE(lm49453_dapm_widgets),
1476 .dapm_routes = lm49453_audio_map,
1477 .num_dapm_routes = ARRAY_SIZE(lm49453_audio_map),
1478 .idle_bias_off = true,
1479};
1480
1481static const struct regmap_config lm49453_regmap_config = {
1482 .reg_bits = 8,
1483 .val_bits = 8,
1484
1485 .max_register = LM49453_MAX_REGISTER,
1486 .reg_defaults = lm49453_reg_defs,
1487 .num_reg_defaults = ARRAY_SIZE(lm49453_reg_defs),
1488 .cache_type = REGCACHE_RBTREE,
1489};
1490
bd479f6f
BP		 1491static int lm49453_i2c_probe(struct i2c_client *i2c,
1492 const struct i2c_device_id *id)
dbf7a733
SR		 1493{
1494 struct lm49453_priv *lm49453;
1495 int ret = 0;
1496
1497 lm49453 = devm_kzalloc(&i2c->dev, sizeof(struct lm49453_priv),
1498 GFP_KERNEL);
1499
1500 if (lm49453 == NULL)
1501 return -ENOMEM;
1502
1503 i2c_set_clientdata(i2c, lm49453);
1504
2fadf6a8 1505 lm49453->regmap = devm_regmap_init_i2c(i2c, &lm49453_regmap_config);
dbf7a733
SR		 1506 if (IS_ERR(lm49453->regmap)) {
1507 ret = PTR_ERR(lm49453->regmap);
1508 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1509 ret);
1510 return ret;
1511 }
1512
1513 ret = snd_soc_register_codec(&i2c->dev,
1514 &soc_codec_dev_lm49453,
1515 lm49453_dai, ARRAY_SIZE(lm49453_dai));
2fadf6a8 1516 if (ret < 0)
dbf7a733 1517 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
dbf7a733
SR		 1518
1519 return ret;
1520}
1521
bd479f6f 1522static int lm49453_i2c_remove(struct i2c_client *client)
dbf7a733 1523{
dbf7a733 1524 snd_soc_unregister_codec(&client->dev);
dbf7a733
SR		 1525 return 0;
1526}
1527
1528static const struct i2c_device_id lm49453_i2c_id[] = {
1529 { "lm49453", 0 },
1530 { }
1531};
1532MODULE_DEVICE_TABLE(i2c, lm49453_i2c_id);
1533
1534static struct i2c_driver lm49453_i2c_driver = {
1535 .driver = {
1536 .name = "lm49453",
1537 .owner = THIS_MODULE,
1538 },
1539 .probe = lm49453_i2c_probe,
bd479f6f 1540 .remove = lm49453_i2c_remove,
dbf7a733
SR		 1541 .id_table = lm49453_i2c_id,
1542};
1543
1544module_i2c_driver(lm49453_i2c_driver);
1545
1546MODULE_DESCRIPTION("ASoC LM49453 driver");
665010c2 1547MODULE_AUTHOR("M R Swami Reddy <MR.Swami.Reddy@ti.com>");
dbf7a733 1548MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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