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83f7cbc4 KM |
1 | /* |
2 | * max98090.c -- MAX98090 ALSA SoC Audio driver | |
3 | * based on Rev0p8 datasheet | |
4 | * | |
5 | * Copyright (C) 2012 Renesas Solutions Corp. | |
6 | * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | |
7 | * | |
8 | * Based on | |
9 | * | |
10 | * max98095.c | |
11 | * Copyright 2011 Maxim Integrated Products | |
12 | * | |
13 | * https://github.com/hardkernel/linux/commit/\ | |
14 | * 3417d7166b17113b3b33b0a337c74d1c7cc313df#sound/soc/codecs/max98090.c | |
15 | * Copyright 2011 Maxim Integrated Products | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or modify | |
18 | * it under the terms of the GNU General Public License version 2 as | |
19 | * published by the Free Software Foundation. | |
20 | */ | |
21 | ||
22 | #include <linux/i2c.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/regmap.h> | |
25 | #include <sound/soc.h> | |
26 | #include <sound/tlv.h> | |
27 | ||
28 | /* | |
29 | * | |
30 | * MAX98090 Registers Definition | |
31 | * | |
32 | */ | |
33 | ||
34 | /* RESET / STATUS / INTERRUPT REGISTERS */ | |
35 | #define MAX98090_0x00_SW_RESET 0x00 | |
36 | #define MAX98090_0x01_INT_STS 0x01 | |
37 | #define MAX98090_0x02_JACK_STS 0x02 | |
38 | #define MAX98090_0x03_INT_MASK 0x03 | |
39 | ||
40 | /* QUICK SETUP REGISTERS */ | |
41 | #define MAX98090_0x04_SYS_CLK 0x04 | |
42 | #define MAX98090_0x05_SAMPLE_RATE 0x05 | |
43 | #define MAX98090_0x06_DAI_IF 0x06 | |
44 | #define MAX98090_0x07_DAC_PATH 0x07 | |
45 | #define MAX98090_0x08_MIC_TO_ADC 0x08 | |
46 | #define MAX98090_0x09_LINE_TO_ADC 0x09 | |
47 | #define MAX98090_0x0A_ANALOG_MIC_LOOP 0x0A | |
48 | #define MAX98090_0x0B_ANALOG_LINE_LOOP 0x0B | |
49 | ||
50 | /* ANALOG INPUT CONFIGURATION REGISTERS */ | |
51 | #define MAX98090_0x0D_INPUT_CONFIG 0x0D | |
52 | #define MAX98090_0x0E_LINE_IN_LVL 0x0E | |
53 | #define MAX98090_0x0F_LINI_IN_CFG 0x0F | |
54 | #define MAX98090_0x10_MIC1_IN_LVL 0x10 | |
55 | #define MAX98090_0x11_MIC2_IN_LVL 0x11 | |
56 | ||
57 | /* MICROPHONE CONFIGURATION REGISTERS */ | |
58 | #define MAX98090_0x12_MIC_BIAS_VOL 0x12 | |
59 | #define MAX98090_0x13_DIGITAL_MIC_CFG 0x13 | |
60 | #define MAX98090_0x14_DIGITAL_MIC_MODE 0x14 | |
61 | ||
62 | /* ADC PATH AND CONFIGURATION REGISTERS */ | |
63 | #define MAX98090_0x15_L_ADC_MIX 0x15 | |
64 | #define MAX98090_0x16_R_ADC_MIX 0x16 | |
65 | #define MAX98090_0x17_L_ADC_LVL 0x17 | |
66 | #define MAX98090_0x18_R_ADC_LVL 0x18 | |
67 | #define MAX98090_0x19_ADC_BIQUAD_LVL 0x19 | |
68 | #define MAX98090_0x1A_ADC_SIDETONE 0x1A | |
69 | ||
70 | /* CLOCK CONFIGURATION REGISTERS */ | |
71 | #define MAX98090_0x1B_SYS_CLK 0x1B | |
72 | #define MAX98090_0x1C_CLK_MODE 0x1C | |
73 | #define MAX98090_0x1D_ANY_CLK1 0x1D | |
74 | #define MAX98090_0x1E_ANY_CLK2 0x1E | |
75 | #define MAX98090_0x1F_ANY_CLK3 0x1F | |
76 | #define MAX98090_0x20_ANY_CLK4 0x20 | |
77 | #define MAX98090_0x21_MASTER_MODE 0x21 | |
78 | ||
79 | /* INTERFACE CONTROL REGISTERS */ | |
80 | #define MAX98090_0x22_DAI_IF_FMT 0x22 | |
81 | #define MAX98090_0x23_DAI_TDM_FMT1 0x23 | |
82 | #define MAX98090_0x24_DAI_TDM_FMT2 0x24 | |
83 | #define MAX98090_0x25_DAI_IO_CFG 0x25 | |
84 | #define MAX98090_0x26_FILTER_CFG 0x26 | |
85 | #define MAX98090_0x27_DAI_PLAYBACK_LVL 0x27 | |
86 | #define MAX98090_0x28_EQ_PLAYBACK_LVL 0x28 | |
87 | ||
88 | /* HEADPHONE CONTROL REGISTERS */ | |
89 | #define MAX98090_0x29_L_HP_MIX 0x29 | |
90 | #define MAX98090_0x2A_R_HP_MIX 0x2A | |
91 | #define MAX98090_0x2B_HP_CTR 0x2B | |
92 | #define MAX98090_0x2C_L_HP_VOL 0x2C | |
93 | #define MAX98090_0x2D_R_HP_VOL 0x2D | |
94 | ||
95 | /* SPEAKER CONFIGURATION REGISTERS */ | |
96 | #define MAX98090_0x2E_L_SPK_MIX 0x2E | |
97 | #define MAX98090_0x2F_R_SPK_MIX 0x2F | |
98 | #define MAX98090_0x30_SPK_CTR 0x30 | |
99 | #define MAX98090_0x31_L_SPK_VOL 0x31 | |
100 | #define MAX98090_0x32_R_SPK_VOL 0x32 | |
101 | ||
102 | /* ALC CONFIGURATION REGISTERS */ | |
103 | #define MAX98090_0x33_ALC_TIMING 0x33 | |
104 | #define MAX98090_0x34_ALC_COMPRESSOR 0x34 | |
105 | #define MAX98090_0x35_ALC_EXPANDER 0x35 | |
106 | #define MAX98090_0x36_ALC_GAIN 0x36 | |
107 | ||
108 | /* RECEIVER AND LINE_OUTPUT REGISTERS */ | |
109 | #define MAX98090_0x37_RCV_LOUT_L_MIX 0x37 | |
110 | #define MAX98090_0x38_RCV_LOUT_L_CNTL 0x38 | |
111 | #define MAX98090_0x39_RCV_LOUT_L_VOL 0x39 | |
112 | #define MAX98090_0x3A_LOUT_R_MIX 0x3A | |
113 | #define MAX98090_0x3B_LOUT_R_CNTL 0x3B | |
114 | #define MAX98090_0x3C_LOUT_R_VOL 0x3C | |
115 | ||
116 | /* JACK DETECT AND ENABLE REGISTERS */ | |
117 | #define MAX98090_0x3D_JACK_DETECT 0x3D | |
118 | #define MAX98090_0x3E_IN_ENABLE 0x3E | |
119 | #define MAX98090_0x3F_OUT_ENABLE 0x3F | |
120 | #define MAX98090_0x40_LVL_CTR 0x40 | |
121 | #define MAX98090_0x41_DSP_FILTER_ENABLE 0x41 | |
122 | ||
123 | /* BIAS AND POWER MODE CONFIGURATION REGISTERS */ | |
124 | #define MAX98090_0x42_BIAS_CTR 0x42 | |
125 | #define MAX98090_0x43_DAC_CTR 0x43 | |
126 | #define MAX98090_0x44_ADC_CTR 0x44 | |
127 | #define MAX98090_0x45_DEV_SHUTDOWN 0x45 | |
128 | ||
129 | /* REVISION ID REGISTER */ | |
130 | #define MAX98090_0xFF_REV_ID 0xFF | |
131 | ||
132 | #define MAX98090_REG_MAX_CACHED 0x45 | |
133 | #define MAX98090_REG_END 0xFF | |
134 | ||
135 | /* | |
136 | * | |
137 | * MAX98090 Registers Bit Fields | |
138 | * | |
139 | */ | |
140 | ||
141 | /* MAX98090_0x06_DAI_IF */ | |
142 | #define MAX98090_DAI_IF_MASK 0x3F | |
143 | #define MAX98090_RJ_M (1 << 5) | |
144 | #define MAX98090_RJ_S (1 << 4) | |
145 | #define MAX98090_LJ_M (1 << 3) | |
146 | #define MAX98090_LJ_S (1 << 2) | |
147 | #define MAX98090_I2S_M (1 << 1) | |
148 | #define MAX98090_I2S_S (1 << 0) | |
149 | ||
150 | /* MAX98090_0x45_DEV_SHUTDOWN */ | |
151 | #define MAX98090_SHDNRUN (1 << 7) | |
152 | ||
153 | /* codec private data */ | |
154 | struct max98090_priv { | |
155 | struct regmap *regmap; | |
156 | }; | |
157 | ||
158 | static const struct reg_default max98090_reg_defaults[] = { | |
159 | /* RESET / STATUS / INTERRUPT REGISTERS */ | |
160 | {MAX98090_0x00_SW_RESET, 0x00}, | |
161 | {MAX98090_0x01_INT_STS, 0x00}, | |
162 | {MAX98090_0x02_JACK_STS, 0x00}, | |
163 | {MAX98090_0x03_INT_MASK, 0x04}, | |
164 | ||
165 | /* QUICK SETUP REGISTERS */ | |
166 | {MAX98090_0x04_SYS_CLK, 0x00}, | |
167 | {MAX98090_0x05_SAMPLE_RATE, 0x00}, | |
168 | {MAX98090_0x06_DAI_IF, 0x00}, | |
169 | {MAX98090_0x07_DAC_PATH, 0x00}, | |
170 | {MAX98090_0x08_MIC_TO_ADC, 0x00}, | |
171 | {MAX98090_0x09_LINE_TO_ADC, 0x00}, | |
172 | {MAX98090_0x0A_ANALOG_MIC_LOOP, 0x00}, | |
173 | {MAX98090_0x0B_ANALOG_LINE_LOOP, 0x00}, | |
174 | ||
175 | /* ANALOG INPUT CONFIGURATION REGISTERS */ | |
176 | {MAX98090_0x0D_INPUT_CONFIG, 0x00}, | |
177 | {MAX98090_0x0E_LINE_IN_LVL, 0x1B}, | |
178 | {MAX98090_0x0F_LINI_IN_CFG, 0x00}, | |
179 | {MAX98090_0x10_MIC1_IN_LVL, 0x11}, | |
180 | {MAX98090_0x11_MIC2_IN_LVL, 0x11}, | |
181 | ||
182 | /* MICROPHONE CONFIGURATION REGISTERS */ | |
183 | {MAX98090_0x12_MIC_BIAS_VOL, 0x00}, | |
184 | {MAX98090_0x13_DIGITAL_MIC_CFG, 0x00}, | |
185 | {MAX98090_0x14_DIGITAL_MIC_MODE, 0x00}, | |
186 | ||
187 | /* ADC PATH AND CONFIGURATION REGISTERS */ | |
188 | {MAX98090_0x15_L_ADC_MIX, 0x00}, | |
189 | {MAX98090_0x16_R_ADC_MIX, 0x00}, | |
190 | {MAX98090_0x17_L_ADC_LVL, 0x03}, | |
191 | {MAX98090_0x18_R_ADC_LVL, 0x03}, | |
192 | {MAX98090_0x19_ADC_BIQUAD_LVL, 0x00}, | |
193 | {MAX98090_0x1A_ADC_SIDETONE, 0x00}, | |
194 | ||
195 | /* CLOCK CONFIGURATION REGISTERS */ | |
196 | {MAX98090_0x1B_SYS_CLK, 0x00}, | |
197 | {MAX98090_0x1C_CLK_MODE, 0x00}, | |
198 | {MAX98090_0x1D_ANY_CLK1, 0x00}, | |
199 | {MAX98090_0x1E_ANY_CLK2, 0x00}, | |
200 | {MAX98090_0x1F_ANY_CLK3, 0x00}, | |
201 | {MAX98090_0x20_ANY_CLK4, 0x00}, | |
202 | {MAX98090_0x21_MASTER_MODE, 0x00}, | |
203 | ||
204 | /* INTERFACE CONTROL REGISTERS */ | |
205 | {MAX98090_0x22_DAI_IF_FMT, 0x00}, | |
206 | {MAX98090_0x23_DAI_TDM_FMT1, 0x00}, | |
207 | {MAX98090_0x24_DAI_TDM_FMT2, 0x00}, | |
208 | {MAX98090_0x25_DAI_IO_CFG, 0x00}, | |
209 | {MAX98090_0x26_FILTER_CFG, 0x80}, | |
210 | {MAX98090_0x27_DAI_PLAYBACK_LVL, 0x00}, | |
211 | {MAX98090_0x28_EQ_PLAYBACK_LVL, 0x00}, | |
212 | ||
213 | /* HEADPHONE CONTROL REGISTERS */ | |
214 | {MAX98090_0x29_L_HP_MIX, 0x00}, | |
215 | {MAX98090_0x2A_R_HP_MIX, 0x00}, | |
216 | {MAX98090_0x2B_HP_CTR, 0x00}, | |
217 | {MAX98090_0x2C_L_HP_VOL, 0x1A}, | |
218 | {MAX98090_0x2D_R_HP_VOL, 0x1A}, | |
219 | ||
220 | /* SPEAKER CONFIGURATION REGISTERS */ | |
221 | {MAX98090_0x2E_L_SPK_MIX, 0x00}, | |
222 | {MAX98090_0x2F_R_SPK_MIX, 0x00}, | |
223 | {MAX98090_0x30_SPK_CTR, 0x00}, | |
224 | {MAX98090_0x31_L_SPK_VOL, 0x2C}, | |
225 | {MAX98090_0x32_R_SPK_VOL, 0x2C}, | |
226 | ||
227 | /* ALC CONFIGURATION REGISTERS */ | |
228 | {MAX98090_0x33_ALC_TIMING, 0x00}, | |
229 | {MAX98090_0x34_ALC_COMPRESSOR, 0x00}, | |
230 | {MAX98090_0x35_ALC_EXPANDER, 0x00}, | |
231 | {MAX98090_0x36_ALC_GAIN, 0x00}, | |
232 | ||
233 | /* RECEIVER AND LINE_OUTPUT REGISTERS */ | |
234 | {MAX98090_0x37_RCV_LOUT_L_MIX, 0x00}, | |
235 | {MAX98090_0x38_RCV_LOUT_L_CNTL, 0x00}, | |
236 | {MAX98090_0x39_RCV_LOUT_L_VOL, 0x15}, | |
237 | {MAX98090_0x3A_LOUT_R_MIX, 0x00}, | |
238 | {MAX98090_0x3B_LOUT_R_CNTL, 0x00}, | |
239 | {MAX98090_0x3C_LOUT_R_VOL, 0x15}, | |
240 | ||
241 | /* JACK DETECT AND ENABLE REGISTERS */ | |
242 | {MAX98090_0x3D_JACK_DETECT, 0x00}, | |
243 | {MAX98090_0x3E_IN_ENABLE, 0x00}, | |
244 | {MAX98090_0x3F_OUT_ENABLE, 0x00}, | |
245 | {MAX98090_0x40_LVL_CTR, 0x00}, | |
246 | {MAX98090_0x41_DSP_FILTER_ENABLE, 0x00}, | |
247 | ||
248 | /* BIAS AND POWER MODE CONFIGURATION REGISTERS */ | |
249 | {MAX98090_0x42_BIAS_CTR, 0x00}, | |
250 | {MAX98090_0x43_DAC_CTR, 0x00}, | |
251 | {MAX98090_0x44_ADC_CTR, 0x06}, | |
252 | {MAX98090_0x45_DEV_SHUTDOWN, 0x00}, | |
253 | }; | |
254 | ||
255 | static const unsigned int max98090_hp_tlv[] = { | |
256 | TLV_DB_RANGE_HEAD(5), | |
257 | 0x0, 0x6, TLV_DB_SCALE_ITEM(-6700, 400, 0), | |
258 | 0x7, 0xE, TLV_DB_SCALE_ITEM(-4000, 300, 0), | |
259 | 0xF, 0x15, TLV_DB_SCALE_ITEM(-1700, 200, 0), | |
260 | 0x16, 0x1B, TLV_DB_SCALE_ITEM(-400, 100, 0), | |
261 | 0x1C, 0x1F, TLV_DB_SCALE_ITEM(150, 50, 0), | |
262 | }; | |
263 | ||
264 | static struct snd_kcontrol_new max98090_snd_controls[] = { | |
265 | SOC_DOUBLE_R_TLV("Headphone Volume", MAX98090_0x2C_L_HP_VOL, | |
266 | MAX98090_0x2D_R_HP_VOL, 0, 31, 0, max98090_hp_tlv), | |
267 | }; | |
268 | ||
269 | /* Left HeadPhone Mixer Switch */ | |
270 | static struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = { | |
271 | SOC_DAPM_SINGLE("DACR Switch", MAX98090_0x29_L_HP_MIX, 1, 1, 0), | |
272 | SOC_DAPM_SINGLE("DACL Switch", MAX98090_0x29_L_HP_MIX, 0, 1, 0), | |
273 | }; | |
274 | ||
275 | /* Right HeadPhone Mixer Switch */ | |
276 | static struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = { | |
277 | SOC_DAPM_SINGLE("DACR Switch", MAX98090_0x2A_R_HP_MIX, 1, 1, 0), | |
278 | SOC_DAPM_SINGLE("DACL Switch", MAX98090_0x2A_R_HP_MIX, 0, 1, 0), | |
279 | }; | |
280 | ||
281 | static struct snd_soc_dapm_widget max98090_dapm_widgets[] = { | |
282 | /* Output */ | |
283 | SND_SOC_DAPM_OUTPUT("HPL"), | |
284 | SND_SOC_DAPM_OUTPUT("HPR"), | |
285 | ||
286 | /* PGA */ | |
287 | SND_SOC_DAPM_PGA("HPL Out", MAX98090_0x3F_OUT_ENABLE, 7, 0, NULL, 0), | |
288 | SND_SOC_DAPM_PGA("HPR Out", MAX98090_0x3F_OUT_ENABLE, 6, 0, NULL, 0), | |
289 | ||
290 | /* Mixer */ | |
291 | SND_SOC_DAPM_MIXER("HPL Mixer", SND_SOC_NOPM, 0, 0, | |
292 | max98090_left_hp_mixer_controls, | |
293 | ARRAY_SIZE(max98090_left_hp_mixer_controls)), | |
294 | ||
295 | SND_SOC_DAPM_MIXER("HPR Mixer", SND_SOC_NOPM, 0, 0, | |
296 | max98090_right_hp_mixer_controls, | |
297 | ARRAY_SIZE(max98090_right_hp_mixer_controls)), | |
298 | ||
299 | /* DAC */ | |
300 | SND_SOC_DAPM_DAC("DACL", "Hifi Playback", MAX98090_0x3F_OUT_ENABLE, 0, 0), | |
301 | SND_SOC_DAPM_DAC("DACR", "Hifi Playback", MAX98090_0x3F_OUT_ENABLE, 1, 0), | |
302 | }; | |
303 | ||
304 | static struct snd_soc_dapm_route max98090_audio_map[] = { | |
305 | /* Output */ | |
306 | {"HPL", NULL, "HPL Out"}, | |
307 | {"HPR", NULL, "HPR Out"}, | |
308 | ||
309 | /* PGA */ | |
310 | {"HPL Out", NULL, "HPL Mixer"}, | |
311 | {"HPR Out", NULL, "HPR Mixer"}, | |
312 | ||
313 | /* Mixer*/ | |
314 | {"HPL Mixer", "DACR Switch", "DACR"}, | |
315 | {"HPL Mixer", "DACL Switch", "DACL"}, | |
316 | ||
317 | {"HPR Mixer", "DACR Switch", "DACR"}, | |
318 | {"HPR Mixer", "DACL Switch", "DACL"}, | |
319 | }; | |
320 | ||
321 | static bool max98090_volatile(struct device *dev, unsigned int reg) | |
322 | { | |
323 | if ((reg == MAX98090_0x01_INT_STS) || | |
324 | (reg == MAX98090_0x02_JACK_STS) || | |
325 | (reg > MAX98090_REG_MAX_CACHED)) | |
326 | return true; | |
327 | ||
328 | return false; | |
329 | } | |
330 | ||
331 | static int max98090_dai_hw_params(struct snd_pcm_substream *substream, | |
332 | struct snd_pcm_hw_params *params, | |
333 | struct snd_soc_dai *dai) | |
334 | { | |
335 | struct snd_soc_codec *codec = dai->codec; | |
336 | unsigned int val; | |
337 | ||
338 | switch (params_rate(params)) { | |
339 | case 96000: | |
340 | val = 1 << 5; | |
341 | break; | |
342 | case 32000: | |
343 | val = 1 << 4; | |
344 | break; | |
345 | case 48000: | |
346 | val = 1 << 3; | |
347 | break; | |
348 | case 44100: | |
349 | val = 1 << 2; | |
350 | break; | |
351 | case 16000: | |
352 | val = 1 << 1; | |
353 | break; | |
354 | case 8000: | |
355 | val = 1 << 0; | |
356 | break; | |
357 | default: | |
358 | dev_err(codec->dev, "unsupported rate\n"); | |
359 | return -EINVAL; | |
360 | } | |
361 | snd_soc_update_bits(codec, MAX98090_0x05_SAMPLE_RATE, 0x03F, val); | |
362 | ||
363 | return 0; | |
364 | } | |
365 | ||
366 | static int max98090_dai_set_sysclk(struct snd_soc_dai *dai, | |
367 | int clk_id, unsigned int freq, int dir) | |
368 | { | |
369 | struct snd_soc_codec *codec = dai->codec; | |
370 | unsigned int val; | |
371 | ||
372 | snd_soc_update_bits(codec, MAX98090_0x45_DEV_SHUTDOWN, | |
373 | MAX98090_SHDNRUN, 0); | |
374 | ||
375 | switch (freq) { | |
376 | case 26000000: | |
377 | val = 1 << 7; | |
378 | break; | |
379 | case 19200000: | |
380 | val = 1 << 6; | |
381 | break; | |
382 | case 13000000: | |
383 | val = 1 << 5; | |
384 | break; | |
385 | case 12288000: | |
386 | val = 1 << 4; | |
387 | break; | |
388 | case 12000000: | |
389 | val = 1 << 3; | |
390 | break; | |
391 | case 11289600: | |
392 | val = 1 << 2; | |
393 | break; | |
394 | default: | |
395 | dev_err(codec->dev, "Invalid master clock frequency\n"); | |
396 | return -EINVAL; | |
397 | } | |
398 | snd_soc_update_bits(codec, MAX98090_0x04_SYS_CLK, 0xFD, val); | |
399 | ||
400 | snd_soc_update_bits(codec, MAX98090_0x45_DEV_SHUTDOWN, | |
401 | MAX98090_SHDNRUN, MAX98090_SHDNRUN); | |
402 | ||
403 | dev_dbg(dai->dev, "sysclk is %uHz\n", freq); | |
404 | ||
405 | return 0; | |
406 | } | |
407 | ||
408 | static int max98090_dai_set_fmt(struct snd_soc_dai *dai, | |
409 | unsigned int fmt) | |
410 | { | |
411 | struct snd_soc_codec *codec = dai->codec; | |
412 | int is_master; | |
413 | u8 val; | |
414 | ||
415 | /* master/slave mode */ | |
416 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
417 | case SND_SOC_DAIFMT_CBM_CFM: | |
418 | is_master = 1; | |
419 | break; | |
420 | case SND_SOC_DAIFMT_CBS_CFS: | |
421 | is_master = 0; | |
422 | break; | |
423 | default: | |
424 | dev_err(codec->dev, "unsupported clock\n"); | |
425 | return -EINVAL; | |
426 | } | |
427 | ||
428 | /* format */ | |
429 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
430 | case SND_SOC_DAIFMT_I2S: | |
431 | val = (is_master) ? MAX98090_I2S_M : MAX98090_I2S_S; | |
432 | break; | |
433 | case SND_SOC_DAIFMT_RIGHT_J: | |
434 | val = (is_master) ? MAX98090_RJ_M : MAX98090_RJ_S; | |
435 | break; | |
436 | case SND_SOC_DAIFMT_LEFT_J: | |
437 | val = (is_master) ? MAX98090_LJ_M : MAX98090_LJ_S; | |
438 | break; | |
439 | default: | |
440 | dev_err(codec->dev, "unsupported format\n"); | |
441 | return -EINVAL; | |
442 | } | |
443 | snd_soc_update_bits(codec, MAX98090_0x06_DAI_IF, | |
444 | MAX98090_DAI_IF_MASK, val); | |
445 | ||
446 | return 0; | |
447 | } | |
448 | ||
449 | #define MAX98090_RATES SNDRV_PCM_RATE_8000_96000 | |
450 | #define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) | |
451 | ||
452 | static struct snd_soc_dai_ops max98090_dai_ops = { | |
453 | .set_sysclk = max98090_dai_set_sysclk, | |
454 | .set_fmt = max98090_dai_set_fmt, | |
455 | .hw_params = max98090_dai_hw_params, | |
456 | }; | |
457 | ||
458 | static struct snd_soc_dai_driver max98090_dai = { | |
459 | .name = "max98090-Hifi", | |
460 | .playback = { | |
461 | .stream_name = "Playback", | |
462 | .channels_min = 1, | |
463 | .channels_max = 2, | |
464 | .rates = MAX98090_RATES, | |
465 | .formats = MAX98090_FORMATS, | |
466 | }, | |
467 | .ops = &max98090_dai_ops, | |
468 | }; | |
469 | ||
470 | static int max98090_probe(struct snd_soc_codec *codec) | |
471 | { | |
472 | struct max98090_priv *priv = snd_soc_codec_get_drvdata(codec); | |
473 | struct device *dev = codec->dev; | |
474 | int ret; | |
475 | ||
476 | codec->control_data = priv->regmap; | |
477 | ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP); | |
478 | if (ret < 0) { | |
479 | dev_err(dev, "Failed to set cache I/O: %d\n", ret); | |
480 | return ret; | |
481 | } | |
482 | ||
483 | /* Device active */ | |
484 | snd_soc_update_bits(codec, MAX98090_0x45_DEV_SHUTDOWN, | |
485 | MAX98090_SHDNRUN, MAX98090_SHDNRUN); | |
486 | ||
487 | return 0; | |
488 | } | |
489 | ||
490 | static int max98090_remove(struct snd_soc_codec *codec) | |
491 | { | |
492 | return 0; | |
493 | } | |
494 | ||
495 | static struct snd_soc_codec_driver soc_codec_dev_max98090 = { | |
496 | .probe = max98090_probe, | |
497 | .remove = max98090_remove, | |
498 | .controls = max98090_snd_controls, | |
499 | .num_controls = ARRAY_SIZE(max98090_snd_controls), | |
500 | .dapm_widgets = max98090_dapm_widgets, | |
501 | .num_dapm_widgets = ARRAY_SIZE(max98090_dapm_widgets), | |
502 | .dapm_routes = max98090_audio_map, | |
503 | .num_dapm_routes = ARRAY_SIZE(max98090_audio_map), | |
504 | }; | |
505 | ||
506 | static const struct regmap_config max98090_regmap = { | |
507 | .reg_bits = 8, | |
508 | .val_bits = 8, | |
509 | .max_register = MAX98090_REG_END, | |
510 | .volatile_reg = max98090_volatile, | |
511 | .cache_type = REGCACHE_RBTREE, | |
512 | .reg_defaults = max98090_reg_defaults, | |
513 | .num_reg_defaults = ARRAY_SIZE(max98090_reg_defaults), | |
514 | }; | |
515 | ||
516 | static int max98090_i2c_probe(struct i2c_client *i2c, | |
517 | const struct i2c_device_id *id) | |
518 | { | |
519 | struct max98090_priv *priv; | |
520 | struct device *dev = &i2c->dev; | |
521 | unsigned int val; | |
522 | int ret; | |
523 | ||
524 | priv = devm_kzalloc(dev, sizeof(struct max98090_priv), | |
525 | GFP_KERNEL); | |
526 | if (!priv) | |
527 | return -ENOMEM; | |
528 | ||
529 | priv->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap); | |
530 | if (IS_ERR(priv->regmap)) { | |
531 | ret = PTR_ERR(priv->regmap); | |
532 | dev_err(dev, "Failed to init regmap: %d\n", ret); | |
533 | return ret; | |
534 | } | |
535 | ||
536 | i2c_set_clientdata(i2c, priv); | |
537 | ||
538 | ret = regmap_read(priv->regmap, MAX98090_0xFF_REV_ID, &val); | |
539 | if (ret < 0) { | |
540 | dev_err(dev, "Failed to read device revision: %d\n", ret); | |
541 | return ret; | |
542 | } | |
543 | dev_info(dev, "revision 0x%02x\n", val); | |
544 | ||
545 | ret = snd_soc_register_codec(dev, | |
546 | &soc_codec_dev_max98090, | |
547 | &max98090_dai, 1); | |
548 | ||
549 | return ret; | |
550 | } | |
551 | ||
552 | static int max98090_i2c_remove(struct i2c_client *client) | |
553 | { | |
554 | snd_soc_unregister_codec(&client->dev); | |
555 | return 0; | |
556 | } | |
557 | ||
558 | static const struct i2c_device_id max98090_i2c_id[] = { | |
559 | { "max98090", 0 }, | |
560 | { } | |
561 | }; | |
562 | MODULE_DEVICE_TABLE(i2c, max98090_i2c_id); | |
563 | ||
564 | static struct i2c_driver max98090_i2c_driver = { | |
565 | .driver = { | |
566 | .name = "max98090", | |
567 | .owner = THIS_MODULE, | |
568 | }, | |
569 | .probe = max98090_i2c_probe, | |
570 | .remove = max98090_i2c_remove, | |
571 | .id_table = max98090_i2c_id, | |
572 | }; | |
573 | module_i2c_driver(max98090_i2c_driver); | |
574 | ||
575 | MODULE_DESCRIPTION("ALSA SoC MAX98090 driver"); | |
576 | MODULE_AUTHOR("Peter Hsiang, Kuninori Morimoto"); | |
577 | MODULE_LICENSE("GPL"); |