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685e4215 JW |
1 | /* |
2 | * max98090.c -- MAX98090 ALSA SoC Audio driver | |
3 | * | |
4 | * Copyright 2011-2012 Maxim Integrated Products | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/delay.h> | |
12 | #include <linux/i2c.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/pm.h> | |
15 | #include <linux/pm_runtime.h> | |
16 | #include <linux/regmap.h> | |
17 | #include <linux/slab.h> | |
18 | #include <sound/jack.h> | |
19 | #include <sound/pcm.h> | |
20 | #include <sound/pcm_params.h> | |
21 | #include <sound/soc.h> | |
22 | #include <sound/tlv.h> | |
23 | #include <sound/max98090.h> | |
24 | #include "max98090.h" | |
25 | ||
685e4215 JW |
26 | #define DEBUG |
27 | #define EXTMIC_METHOD | |
28 | #define EXTMIC_METHOD_TEST | |
29 | ||
30 | /* Allows for sparsely populated register maps */ | |
31 | static struct reg_default max98090_reg[] = { | |
32 | { 0x00, 0x00 }, /* 00 Software Reset */ | |
33 | { 0x03, 0x04 }, /* 03 Interrupt Masks */ | |
34 | { 0x04, 0x00 }, /* 04 System Clock Quick */ | |
35 | { 0x05, 0x00 }, /* 05 Sample Rate Quick */ | |
36 | { 0x06, 0x00 }, /* 06 DAI Interface Quick */ | |
37 | { 0x07, 0x00 }, /* 07 DAC Path Quick */ | |
38 | { 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */ | |
39 | { 0x09, 0x00 }, /* 09 Line to ADC Quick */ | |
40 | { 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */ | |
41 | { 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */ | |
42 | { 0x0C, 0x00 }, /* 0C Reserved */ | |
43 | { 0x0D, 0x00 }, /* 0D Input Config */ | |
44 | { 0x0E, 0x1B }, /* 0E Line Input Level */ | |
45 | { 0x0F, 0x00 }, /* 0F Line Config */ | |
46 | ||
47 | { 0x10, 0x14 }, /* 10 Mic1 Input Level */ | |
48 | { 0x11, 0x14 }, /* 11 Mic2 Input Level */ | |
49 | { 0x12, 0x00 }, /* 12 Mic Bias Voltage */ | |
50 | { 0x13, 0x00 }, /* 13 Digital Mic Config */ | |
51 | { 0x14, 0x00 }, /* 14 Digital Mic Mode */ | |
52 | { 0x15, 0x00 }, /* 15 Left ADC Mixer */ | |
53 | { 0x16, 0x00 }, /* 16 Right ADC Mixer */ | |
54 | { 0x17, 0x03 }, /* 17 Left ADC Level */ | |
55 | { 0x18, 0x03 }, /* 18 Right ADC Level */ | |
56 | { 0x19, 0x00 }, /* 19 ADC Biquad Level */ | |
57 | { 0x1A, 0x00 }, /* 1A ADC Sidetone */ | |
58 | { 0x1B, 0x00 }, /* 1B System Clock */ | |
59 | { 0x1C, 0x00 }, /* 1C Clock Mode */ | |
60 | { 0x1D, 0x00 }, /* 1D Any Clock 1 */ | |
61 | { 0x1E, 0x00 }, /* 1E Any Clock 2 */ | |
62 | { 0x1F, 0x00 }, /* 1F Any Clock 3 */ | |
63 | ||
64 | { 0x20, 0x00 }, /* 20 Any Clock 4 */ | |
65 | { 0x21, 0x00 }, /* 21 Master Mode */ | |
66 | { 0x22, 0x00 }, /* 22 Interface Format */ | |
67 | { 0x23, 0x00 }, /* 23 TDM Format 1*/ | |
68 | { 0x24, 0x00 }, /* 24 TDM Format 2*/ | |
69 | { 0x25, 0x00 }, /* 25 I/O Configuration */ | |
70 | { 0x26, 0x80 }, /* 26 Filter Config */ | |
71 | { 0x27, 0x00 }, /* 27 DAI Playback Level */ | |
72 | { 0x28, 0x00 }, /* 28 EQ Playback Level */ | |
73 | { 0x29, 0x00 }, /* 29 Left HP Mixer */ | |
74 | { 0x2A, 0x00 }, /* 2A Right HP Mixer */ | |
75 | { 0x2B, 0x00 }, /* 2B HP Control */ | |
76 | { 0x2C, 0x1A }, /* 2C Left HP Volume */ | |
77 | { 0x2D, 0x1A }, /* 2D Right HP Volume */ | |
78 | { 0x2E, 0x00 }, /* 2E Left Spk Mixer */ | |
79 | { 0x2F, 0x00 }, /* 2F Right Spk Mixer */ | |
80 | ||
81 | { 0x30, 0x00 }, /* 30 Spk Control */ | |
82 | { 0x31, 0x2C }, /* 31 Left Spk Volume */ | |
83 | { 0x32, 0x2C }, /* 32 Right Spk Volume */ | |
84 | { 0x33, 0x00 }, /* 33 ALC Timing */ | |
85 | { 0x34, 0x00 }, /* 34 ALC Compressor */ | |
86 | { 0x35, 0x00 }, /* 35 ALC Expander */ | |
87 | { 0x36, 0x00 }, /* 36 ALC Gain */ | |
88 | { 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */ | |
89 | { 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */ | |
90 | { 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */ | |
91 | { 0x3A, 0x00 }, /* 3A Line OutR Mixer */ | |
92 | { 0x3B, 0x00 }, /* 3B Line OutR Control */ | |
93 | { 0x3C, 0x15 }, /* 3C Line OutR Volume */ | |
94 | { 0x3D, 0x00 }, /* 3D Jack Detect */ | |
95 | { 0x3E, 0x00 }, /* 3E Input Enable */ | |
96 | { 0x3F, 0x00 }, /* 3F Output Enable */ | |
97 | ||
98 | { 0x40, 0x00 }, /* 40 Level Control */ | |
99 | { 0x41, 0x00 }, /* 41 DSP Filter Enable */ | |
100 | { 0x42, 0x00 }, /* 42 Bias Control */ | |
101 | { 0x43, 0x00 }, /* 43 DAC Control */ | |
102 | { 0x44, 0x06 }, /* 44 ADC Control */ | |
103 | { 0x45, 0x00 }, /* 45 Device Shutdown */ | |
104 | { 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */ | |
105 | { 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */ | |
106 | { 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */ | |
107 | { 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */ | |
108 | { 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */ | |
109 | { 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */ | |
110 | { 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */ | |
111 | { 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */ | |
112 | { 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */ | |
113 | { 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */ | |
114 | ||
115 | { 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */ | |
116 | { 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */ | |
117 | { 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */ | |
118 | { 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */ | |
119 | { 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */ | |
120 | { 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */ | |
121 | { 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */ | |
122 | { 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */ | |
123 | { 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */ | |
124 | { 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */ | |
125 | { 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */ | |
126 | { 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */ | |
127 | { 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */ | |
128 | { 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */ | |
129 | { 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */ | |
130 | { 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */ | |
131 | ||
132 | { 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */ | |
133 | { 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */ | |
134 | { 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */ | |
135 | { 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */ | |
136 | { 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */ | |
137 | { 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */ | |
138 | { 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */ | |
139 | { 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */ | |
140 | { 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */ | |
141 | { 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */ | |
142 | { 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */ | |
143 | { 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */ | |
144 | { 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */ | |
145 | { 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */ | |
146 | { 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */ | |
147 | { 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */ | |
148 | ||
149 | { 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */ | |
150 | { 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */ | |
151 | { 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */ | |
152 | { 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */ | |
153 | { 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */ | |
154 | { 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */ | |
155 | { 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */ | |
156 | { 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */ | |
157 | { 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */ | |
158 | { 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */ | |
159 | { 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */ | |
160 | { 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */ | |
161 | { 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */ | |
162 | { 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */ | |
163 | { 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */ | |
164 | { 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */ | |
165 | ||
166 | { 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */ | |
167 | { 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */ | |
168 | { 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */ | |
169 | { 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */ | |
170 | { 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */ | |
171 | { 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */ | |
172 | { 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */ | |
173 | { 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */ | |
174 | { 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */ | |
175 | { 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */ | |
176 | { 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */ | |
177 | { 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */ | |
178 | { 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */ | |
179 | { 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */ | |
180 | { 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */ | |
181 | { 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */ | |
182 | ||
183 | { 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */ | |
184 | { 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */ | |
185 | { 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */ | |
186 | { 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */ | |
187 | { 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */ | |
188 | { 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */ | |
189 | { 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */ | |
190 | { 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */ | |
191 | { 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */ | |
192 | { 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */ | |
193 | { 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */ | |
194 | { 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */ | |
195 | { 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */ | |
196 | { 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */ | |
197 | { 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */ | |
198 | { 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */ | |
199 | ||
200 | { 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */ | |
201 | { 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */ | |
202 | { 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */ | |
203 | { 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */ | |
204 | { 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */ | |
205 | { 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */ | |
206 | { 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */ | |
207 | { 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */ | |
208 | { 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */ | |
209 | { 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */ | |
210 | { 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */ | |
211 | { 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */ | |
212 | { 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */ | |
213 | { 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */ | |
214 | { 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */ | |
215 | { 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */ | |
216 | ||
217 | { 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */ | |
218 | { 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */ | |
219 | { 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */ | |
220 | { 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */ | |
221 | { 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */ | |
222 | { 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */ | |
223 | { 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */ | |
224 | { 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */ | |
225 | { 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */ | |
226 | { 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */ | |
227 | { 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */ | |
228 | { 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */ | |
229 | { 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */ | |
230 | { 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */ | |
231 | { 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */ | |
232 | { 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */ | |
233 | ||
234 | { 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */ | |
235 | { 0xC1, 0x00 }, /* C1 Record TDM Slot */ | |
236 | { 0xC2, 0x00 }, /* C2 Sample Rate */ | |
237 | { 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */ | |
238 | { 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */ | |
239 | { 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */ | |
240 | { 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */ | |
241 | { 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */ | |
242 | { 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */ | |
243 | { 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */ | |
244 | { 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */ | |
245 | { 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */ | |
246 | { 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */ | |
247 | { 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */ | |
248 | { 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */ | |
249 | { 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */ | |
250 | ||
251 | { 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */ | |
252 | { 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */ | |
253 | }; | |
254 | ||
255 | static bool max98090_volatile_register(struct device *dev, unsigned int reg) | |
256 | { | |
257 | switch (reg) { | |
258 | case M98090_REG_DEVICE_STATUS: | |
259 | case M98090_REG_JACK_STATUS: | |
260 | case M98090_REG_REVISION_ID: | |
261 | return true; | |
262 | default: | |
263 | return false; | |
264 | } | |
265 | } | |
266 | ||
267 | static bool max98090_readable_register(struct device *dev, unsigned int reg) | |
268 | { | |
269 | switch (reg) { | |
270 | case M98090_REG_DEVICE_STATUS: | |
271 | case M98090_REG_JACK_STATUS: | |
272 | case M98090_REG_INTERRUPT_S: | |
273 | case M98090_REG_RESERVED: | |
274 | case M98090_REG_LINE_INPUT_CONFIG: | |
275 | case M98090_REG_LINE_INPUT_LEVEL: | |
276 | case M98090_REG_INPUT_MODE: | |
277 | case M98090_REG_MIC1_INPUT_LEVEL: | |
278 | case M98090_REG_MIC2_INPUT_LEVEL: | |
279 | case M98090_REG_MIC_BIAS_VOLTAGE: | |
280 | case M98090_REG_DIGITAL_MIC_ENABLE: | |
281 | case M98090_REG_DIGITAL_MIC_CONFIG: | |
282 | case M98090_REG_LEFT_ADC_MIXER: | |
283 | case M98090_REG_RIGHT_ADC_MIXER: | |
284 | case M98090_REG_LEFT_ADC_LEVEL: | |
285 | case M98090_REG_RIGHT_ADC_LEVEL: | |
286 | case M98090_REG_ADC_BIQUAD_LEVEL: | |
287 | case M98090_REG_ADC_SIDETONE: | |
288 | case M98090_REG_SYSTEM_CLOCK: | |
289 | case M98090_REG_CLOCK_MODE: | |
290 | case M98090_REG_CLOCK_RATIO_NI_MSB: | |
291 | case M98090_REG_CLOCK_RATIO_NI_LSB: | |
292 | case M98090_REG_CLOCK_RATIO_MI_MSB: | |
293 | case M98090_REG_CLOCK_RATIO_MI_LSB: | |
294 | case M98090_REG_MASTER_MODE: | |
295 | case M98090_REG_INTERFACE_FORMAT: | |
296 | case M98090_REG_TDM_CONTROL: | |
297 | case M98090_REG_TDM_FORMAT: | |
298 | case M98090_REG_IO_CONFIGURATION: | |
299 | case M98090_REG_FILTER_CONFIG: | |
300 | case M98090_REG_DAI_PLAYBACK_LEVEL: | |
301 | case M98090_REG_DAI_PLAYBACK_LEVEL_EQ: | |
302 | case M98090_REG_LEFT_HP_MIXER: | |
303 | case M98090_REG_RIGHT_HP_MIXER: | |
304 | case M98090_REG_HP_CONTROL: | |
305 | case M98090_REG_LEFT_HP_VOLUME: | |
306 | case M98090_REG_RIGHT_HP_VOLUME: | |
307 | case M98090_REG_LEFT_SPK_MIXER: | |
308 | case M98090_REG_RIGHT_SPK_MIXER: | |
309 | case M98090_REG_SPK_CONTROL: | |
310 | case M98090_REG_LEFT_SPK_VOLUME: | |
311 | case M98090_REG_RIGHT_SPK_VOLUME: | |
312 | case M98090_REG_DRC_TIMING: | |
313 | case M98090_REG_DRC_COMPRESSOR: | |
314 | case M98090_REG_DRC_EXPANDER: | |
315 | case M98090_REG_DRC_GAIN: | |
316 | case M98090_REG_RCV_LOUTL_MIXER: | |
317 | case M98090_REG_RCV_LOUTL_CONTROL: | |
318 | case M98090_REG_RCV_LOUTL_VOLUME: | |
319 | case M98090_REG_LOUTR_MIXER: | |
320 | case M98090_REG_LOUTR_CONTROL: | |
321 | case M98090_REG_LOUTR_VOLUME: | |
322 | case M98090_REG_JACK_DETECT: | |
323 | case M98090_REG_INPUT_ENABLE: | |
324 | case M98090_REG_OUTPUT_ENABLE: | |
325 | case M98090_REG_LEVEL_CONTROL: | |
326 | case M98090_REG_DSP_FILTER_ENABLE: | |
327 | case M98090_REG_BIAS_CONTROL: | |
328 | case M98090_REG_DAC_CONTROL: | |
329 | case M98090_REG_ADC_CONTROL: | |
330 | case M98090_REG_DEVICE_SHUTDOWN: | |
331 | case M98090_REG_EQUALIZER_BASE ... M98090_REG_EQUALIZER_BASE + 0x68: | |
332 | case M98090_REG_RECORD_BIQUAD_BASE ... M98090_REG_RECORD_BIQUAD_BASE + 0x0E: | |
333 | case M98090_REG_DMIC3_VOLUME: | |
334 | case M98090_REG_DMIC4_VOLUME: | |
335 | case M98090_REG_DMIC34_BQ_PREATTEN: | |
336 | case M98090_REG_RECORD_TDM_SLOT: | |
337 | case M98090_REG_SAMPLE_RATE: | |
338 | case M98090_REG_DMIC34_BIQUAD_BASE ... M98090_REG_DMIC34_BIQUAD_BASE + 0x0E: | |
e126a646 | 339 | case M98090_REG_REVISION_ID: |
685e4215 JW |
340 | return true; |
341 | default: | |
342 | return false; | |
343 | } | |
344 | } | |
345 | ||
346 | static int max98090_reset(struct max98090_priv *max98090) | |
347 | { | |
348 | int ret; | |
349 | ||
350 | /* Reset the codec by writing to this write-only reset register */ | |
351 | ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET, | |
352 | M98090_SWRESET_MASK); | |
353 | if (ret < 0) { | |
354 | dev_err(max98090->codec->dev, | |
355 | "Failed to reset codec: %d\n", ret); | |
356 | return ret; | |
357 | } | |
358 | ||
359 | msleep(20); | |
360 | return ret; | |
361 | } | |
362 | ||
363 | static const unsigned int max98090_micboost_tlv[] = { | |
364 | TLV_DB_RANGE_HEAD(2), | |
365 | 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0), | |
366 | 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0), | |
367 | }; | |
368 | ||
369 | static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv, 0, 100, 0); | |
370 | ||
371 | static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv, | |
372 | -600, 600, 0); | |
373 | ||
374 | static const unsigned int max98090_line_tlv[] = { | |
375 | TLV_DB_RANGE_HEAD(2), | |
376 | 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0), | |
377 | 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0), | |
378 | }; | |
379 | ||
380 | static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv, 0, 600, 0); | |
381 | static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0); | |
382 | ||
383 | static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv, 0, 600, 0); | |
384 | static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0); | |
385 | ||
386 | static const DECLARE_TLV_DB_SCALE(max98090_sidetone_tlv, -6050, 200, 0); | |
387 | ||
388 | static const DECLARE_TLV_DB_SCALE(max98090_alc_tlv, -1500, 100, 0); | |
389 | static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0); | |
390 | static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0); | |
391 | static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0); | |
392 | ||
393 | static const unsigned int max98090_mixout_tlv[] = { | |
394 | TLV_DB_RANGE_HEAD(2), | |
395 | 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0), | |
396 | 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0), | |
397 | }; | |
398 | ||
399 | static const unsigned int max98090_hp_tlv[] = { | |
400 | TLV_DB_RANGE_HEAD(5), | |
401 | 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0), | |
402 | 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0), | |
403 | 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0), | |
404 | 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0), | |
405 | 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0), | |
406 | }; | |
407 | ||
408 | static const unsigned int max98090_spk_tlv[] = { | |
409 | TLV_DB_RANGE_HEAD(5), | |
410 | 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0), | |
411 | 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0), | |
412 | 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0), | |
413 | 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0), | |
414 | 30, 39, TLV_DB_SCALE_ITEM(950, 50, 0), | |
415 | }; | |
416 | ||
417 | static const unsigned int max98090_rcv_lout_tlv[] = { | |
418 | TLV_DB_RANGE_HEAD(5), | |
419 | 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0), | |
420 | 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0), | |
421 | 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0), | |
422 | 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0), | |
423 | 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0), | |
424 | }; | |
425 | ||
426 | static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol, | |
427 | struct snd_ctl_elem_value *ucontrol) | |
428 | { | |
429 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
430 | struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); | |
431 | struct soc_mixer_control *mc = | |
432 | (struct soc_mixer_control *)kcontrol->private_value; | |
433 | unsigned int mask = (1 << fls(mc->max)) - 1; | |
434 | unsigned int val = snd_soc_read(codec, mc->reg); | |
435 | unsigned int *select; | |
436 | ||
437 | switch (mc->reg) { | |
438 | case M98090_REG_MIC1_INPUT_LEVEL: | |
439 | select = &(max98090->pa1en); | |
440 | break; | |
441 | case M98090_REG_MIC2_INPUT_LEVEL: | |
442 | select = &(max98090->pa2en); | |
443 | break; | |
444 | case M98090_REG_ADC_SIDETONE: | |
445 | select = &(max98090->sidetone); | |
446 | break; | |
447 | default: | |
448 | return -EINVAL; | |
449 | } | |
450 | ||
451 | val = (val >> mc->shift) & mask; | |
452 | ||
453 | if (val >= 1) { | |
454 | /* If on, return the volume */ | |
455 | val = val - 1; | |
456 | *select = val; | |
457 | } else { | |
458 | /* If off, return last stored value */ | |
459 | val = *select; | |
460 | } | |
461 | ||
462 | ucontrol->value.integer.value[0] = val; | |
463 | return 0; | |
464 | } | |
465 | ||
466 | static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol, | |
467 | struct snd_ctl_elem_value *ucontrol) | |
468 | { | |
469 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
470 | struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); | |
471 | struct soc_mixer_control *mc = | |
472 | (struct soc_mixer_control *)kcontrol->private_value; | |
473 | unsigned int mask = (1 << fls(mc->max)) - 1; | |
474 | unsigned int sel = ucontrol->value.integer.value[0]; | |
475 | unsigned int val = snd_soc_read(codec, mc->reg); | |
476 | unsigned int *select; | |
477 | ||
478 | switch (mc->reg) { | |
479 | case M98090_REG_MIC1_INPUT_LEVEL: | |
480 | select = &(max98090->pa1en); | |
481 | break; | |
482 | case M98090_REG_MIC2_INPUT_LEVEL: | |
483 | select = &(max98090->pa2en); | |
484 | break; | |
485 | case M98090_REG_ADC_SIDETONE: | |
486 | select = &(max98090->sidetone); | |
487 | break; | |
488 | default: | |
489 | return -EINVAL; | |
490 | } | |
491 | ||
492 | val = (val >> mc->shift) & mask; | |
493 | ||
494 | *select = sel; | |
495 | ||
496 | /* Setting a volume is only valid if it is already On */ | |
497 | if (val >= 1) { | |
498 | sel = sel + 1; | |
499 | } else { | |
500 | /* Write what was already there */ | |
501 | sel = val; | |
502 | } | |
503 | ||
504 | snd_soc_update_bits(codec, mc->reg, | |
505 | mask << mc->shift, | |
506 | sel << mc->shift); | |
507 | ||
508 | return 0; | |
509 | } | |
510 | ||
4ca74feb | 511 | static const char *max98090_perf_pwr_text[] = |
685e4215 | 512 | { "High Performance", "Low Power" }; |
4ca74feb | 513 | static const char *max98090_pwr_perf_text[] = |
685e4215 JW |
514 | { "Low Power", "High Performance" }; |
515 | ||
2907cbcc TI |
516 | static SOC_ENUM_SINGLE_DECL(max98090_vcmbandgap_enum, |
517 | M98090_REG_BIAS_CONTROL, | |
518 | M98090_VCM_MODE_SHIFT, | |
519 | max98090_pwr_perf_text); | |
685e4215 | 520 | |
4ca74feb | 521 | static const char *max98090_osr128_text[] = { "64*fs", "128*fs" }; |
685e4215 | 522 | |
2907cbcc TI |
523 | static SOC_ENUM_SINGLE_DECL(max98090_osr128_enum, |
524 | M98090_REG_ADC_CONTROL, | |
525 | M98090_OSR128_SHIFT, | |
526 | max98090_osr128_text); | |
685e4215 JW |
527 | |
528 | static const char *max98090_mode_text[] = { "Voice", "Music" }; | |
529 | ||
2907cbcc TI |
530 | static SOC_ENUM_SINGLE_DECL(max98090_mode_enum, |
531 | M98090_REG_FILTER_CONFIG, | |
532 | M98090_MODE_SHIFT, | |
533 | max98090_mode_text); | |
685e4215 | 534 | |
2907cbcc TI |
535 | static SOC_ENUM_SINGLE_DECL(max98090_filter_dmic34mode_enum, |
536 | M98090_REG_FILTER_CONFIG, | |
537 | M98090_FLT_DMIC34MODE_SHIFT, | |
538 | max98090_mode_text); | |
685e4215 | 539 | |
4ca74feb | 540 | static const char *max98090_drcatk_text[] = |
685e4215 JW |
541 | { "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" }; |
542 | ||
2907cbcc TI |
543 | static SOC_ENUM_SINGLE_DECL(max98090_drcatk_enum, |
544 | M98090_REG_DRC_TIMING, | |
545 | M98090_DRCATK_SHIFT, | |
546 | max98090_drcatk_text); | |
685e4215 | 547 | |
4ca74feb | 548 | static const char *max98090_drcrls_text[] = |
685e4215 JW |
549 | { "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" }; |
550 | ||
2907cbcc TI |
551 | static SOC_ENUM_SINGLE_DECL(max98090_drcrls_enum, |
552 | M98090_REG_DRC_TIMING, | |
553 | M98090_DRCRLS_SHIFT, | |
554 | max98090_drcrls_text); | |
685e4215 | 555 | |
4ca74feb | 556 | static const char *max98090_alccmp_text[] = |
685e4215 JW |
557 | { "1:1", "1:1.5", "1:2", "1:4", "1:INF" }; |
558 | ||
2907cbcc TI |
559 | static SOC_ENUM_SINGLE_DECL(max98090_alccmp_enum, |
560 | M98090_REG_DRC_COMPRESSOR, | |
561 | M98090_DRCCMP_SHIFT, | |
562 | max98090_alccmp_text); | |
685e4215 | 563 | |
4ca74feb | 564 | static const char *max98090_drcexp_text[] = { "1:1", "2:1", "3:1" }; |
685e4215 | 565 | |
2907cbcc TI |
566 | static SOC_ENUM_SINGLE_DECL(max98090_drcexp_enum, |
567 | M98090_REG_DRC_EXPANDER, | |
568 | M98090_DRCEXP_SHIFT, | |
569 | max98090_drcexp_text); | |
685e4215 | 570 | |
2907cbcc TI |
571 | static SOC_ENUM_SINGLE_DECL(max98090_dac_perfmode_enum, |
572 | M98090_REG_DAC_CONTROL, | |
573 | M98090_PERFMODE_SHIFT, | |
574 | max98090_perf_pwr_text); | |
685e4215 | 575 | |
2907cbcc TI |
576 | static SOC_ENUM_SINGLE_DECL(max98090_dachp_enum, |
577 | M98090_REG_DAC_CONTROL, | |
578 | M98090_DACHP_SHIFT, | |
579 | max98090_pwr_perf_text); | |
685e4215 | 580 | |
2907cbcc TI |
581 | static SOC_ENUM_SINGLE_DECL(max98090_adchp_enum, |
582 | M98090_REG_ADC_CONTROL, | |
583 | M98090_ADCHP_SHIFT, | |
584 | max98090_pwr_perf_text); | |
685e4215 JW |
585 | |
586 | static const struct snd_kcontrol_new max98090_snd_controls[] = { | |
587 | SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum), | |
588 | ||
589 | SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG, | |
590 | M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0), | |
591 | ||
592 | SOC_SINGLE_EXT_TLV("MIC1 Boost Volume", | |
593 | M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT, | |
594 | M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv, | |
595 | max98090_put_enab_tlv, max98090_micboost_tlv), | |
596 | ||
597 | SOC_SINGLE_EXT_TLV("MIC2 Boost Volume", | |
598 | M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT, | |
599 | M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv, | |
600 | max98090_put_enab_tlv, max98090_micboost_tlv), | |
601 | ||
602 | SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL, | |
603 | M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1, | |
604 | max98090_mic_tlv), | |
605 | ||
606 | SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL, | |
607 | M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1, | |
608 | max98090_mic_tlv), | |
609 | ||
610 | SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume", | |
611 | M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG135_SHIFT, 0, | |
612 | M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv), | |
613 | ||
614 | SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume", | |
615 | M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG246_SHIFT, 0, | |
616 | M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv), | |
617 | ||
618 | SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL, | |
619 | M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1, | |
620 | max98090_line_tlv), | |
621 | ||
622 | SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL, | |
623 | M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1, | |
624 | max98090_line_tlv), | |
625 | ||
626 | SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE, | |
627 | M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0), | |
628 | SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE, | |
629 | M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0), | |
630 | ||
631 | SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL, | |
632 | M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0, | |
633 | max98090_avg_tlv), | |
634 | SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL, | |
635 | M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0, | |
636 | max98090_avg_tlv), | |
637 | ||
638 | SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL, | |
639 | M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1, | |
640 | max98090_av_tlv), | |
641 | SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL, | |
642 | M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1, | |
643 | max98090_av_tlv), | |
644 | ||
645 | SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum), | |
646 | SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL, | |
647 | M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0), | |
648 | SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum), | |
649 | ||
650 | SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION, | |
651 | M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0), | |
652 | SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION, | |
653 | M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0), | |
654 | SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION, | |
655 | M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0), | |
656 | SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION, | |
657 | M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1), | |
658 | SOC_ENUM("Filter Mode", max98090_mode_enum), | |
659 | SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG, | |
660 | M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0), | |
661 | SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG, | |
662 | M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0), | |
663 | SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL, | |
664 | M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv), | |
665 | SOC_SINGLE_EXT_TLV("Digital Sidetone Volume", | |
666 | M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT, | |
667 | M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv, | |
668 | max98090_put_enab_tlv, max98090_micboost_tlv), | |
669 | SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL, | |
670 | M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0, | |
671 | max98090_dvg_tlv), | |
672 | SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL, | |
673 | M98090_DV_SHIFT, M98090_DV_NUM - 1, 1, | |
674 | max98090_dv_tlv), | |
675 | SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105), | |
676 | SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE, | |
677 | M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0), | |
678 | SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE, | |
679 | M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0), | |
680 | SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE, | |
681 | M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0), | |
682 | SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ, | |
683 | M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1, | |
684 | 1), | |
685 | SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ, | |
686 | M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1, | |
687 | max98090_dv_tlv), | |
688 | ||
689 | SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING, | |
690 | M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0), | |
691 | SOC_ENUM("ALC Attack Time", max98090_drcatk_enum), | |
692 | SOC_ENUM("ALC Release Time", max98090_drcrls_enum), | |
693 | SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN, | |
694 | M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0, | |
695 | max98090_alcmakeup_tlv), | |
696 | SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum), | |
697 | SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum), | |
698 | SOC_SINGLE_TLV("ALC Compression Threshold Volume", | |
699 | M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT, | |
700 | M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv), | |
701 | SOC_SINGLE_TLV("ALC Expansion Threshold Volume", | |
702 | M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT, | |
703 | M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv), | |
704 | ||
705 | SOC_ENUM("DAC HP Playback Performance Mode", | |
706 | max98090_dac_perfmode_enum), | |
707 | SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum), | |
708 | ||
709 | SOC_SINGLE_TLV("Headphone Left Mixer Volume", | |
710 | M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT, | |
711 | M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv), | |
712 | SOC_SINGLE_TLV("Headphone Right Mixer Volume", | |
713 | M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT, | |
714 | M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv), | |
715 | ||
716 | SOC_SINGLE_TLV("Speaker Left Mixer Volume", | |
717 | M98090_REG_SPK_CONTROL, M98090_MIXSPLG_SHIFT, | |
718 | M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv), | |
719 | SOC_SINGLE_TLV("Speaker Right Mixer Volume", | |
720 | M98090_REG_SPK_CONTROL, M98090_MIXSPRG_SHIFT, | |
721 | M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv), | |
722 | ||
723 | SOC_SINGLE_TLV("Receiver Left Mixer Volume", | |
724 | M98090_REG_RCV_LOUTL_CONTROL, M98090_MIXRCVLG_SHIFT, | |
725 | M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv), | |
726 | SOC_SINGLE_TLV("Receiver Right Mixer Volume", | |
727 | M98090_REG_LOUTR_CONTROL, M98090_MIXRCVRG_SHIFT, | |
728 | M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv), | |
729 | ||
730 | SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME, | |
731 | M98090_REG_RIGHT_HP_VOLUME, M98090_HPVOLL_SHIFT, | |
732 | M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv), | |
733 | ||
734 | SOC_DOUBLE_R_RANGE_TLV("Speaker Volume", | |
735 | M98090_REG_LEFT_SPK_VOLUME, M98090_REG_RIGHT_SPK_VOLUME, | |
736 | M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24, | |
737 | 0, max98090_spk_tlv), | |
738 | ||
739 | SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME, | |
740 | M98090_REG_LOUTR_VOLUME, M98090_RCVLVOL_SHIFT, | |
741 | M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv), | |
742 | ||
743 | SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME, | |
744 | M98090_HPLM_SHIFT, 1, 1), | |
745 | SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME, | |
746 | M98090_HPRM_SHIFT, 1, 1), | |
747 | ||
748 | SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME, | |
749 | M98090_SPLM_SHIFT, 1, 1), | |
750 | SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME, | |
751 | M98090_SPRM_SHIFT, 1, 1), | |
752 | ||
753 | SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME, | |
754 | M98090_RCVLM_SHIFT, 1, 1), | |
755 | SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME, | |
756 | M98090_RCVRM_SHIFT, 1, 1), | |
757 | ||
758 | SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL, | |
759 | M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1), | |
760 | SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL, | |
761 | M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1), | |
762 | SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL, | |
763 | M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1), | |
764 | ||
765 | SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE, 15), | |
766 | SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE, | |
767 | M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0), | |
768 | }; | |
769 | ||
770 | static const struct snd_kcontrol_new max98091_snd_controls[] = { | |
771 | ||
772 | SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE, | |
773 | M98090_DMIC34_ZEROPAD_SHIFT, | |
774 | M98090_DMIC34_ZEROPAD_NUM - 1, 0), | |
775 | ||
776 | SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum), | |
777 | SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG, | |
778 | M98090_FLT_DMIC34HPF_SHIFT, | |
779 | M98090_FLT_DMIC34HPF_NUM - 1, 0), | |
780 | ||
781 | SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME, | |
782 | M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0, | |
783 | max98090_avg_tlv), | |
784 | SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME, | |
785 | M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0, | |
786 | max98090_avg_tlv), | |
787 | ||
788 | SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME, | |
789 | M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1, | |
790 | max98090_av_tlv), | |
791 | SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME, | |
792 | M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1, | |
793 | max98090_av_tlv), | |
794 | ||
795 | SND_SOC_BYTES("DMIC34 Biquad Coefficients", | |
796 | M98090_REG_DMIC34_BIQUAD_BASE, 15), | |
797 | SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE, | |
798 | M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0), | |
799 | ||
800 | SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume", | |
801 | M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT, | |
802 | M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv), | |
803 | }; | |
804 | ||
805 | static int max98090_micinput_event(struct snd_soc_dapm_widget *w, | |
806 | struct snd_kcontrol *kcontrol, int event) | |
807 | { | |
808 | struct snd_soc_codec *codec = w->codec; | |
809 | struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); | |
810 | ||
811 | unsigned int val = snd_soc_read(codec, w->reg); | |
812 | ||
813 | if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) | |
814 | val = (val & M98090_MIC_PA1EN_MASK) >> M98090_MIC_PA1EN_SHIFT; | |
815 | else | |
816 | val = (val & M98090_MIC_PA2EN_MASK) >> M98090_MIC_PA2EN_SHIFT; | |
817 | ||
818 | ||
819 | if (val >= 1) { | |
820 | if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) { | |
821 | max98090->pa1en = val - 1; /* Update for volatile */ | |
822 | } else { | |
823 | max98090->pa2en = val - 1; /* Update for volatile */ | |
824 | } | |
825 | } | |
826 | ||
827 | switch (event) { | |
828 | case SND_SOC_DAPM_POST_PMU: | |
829 | /* If turning on, set to most recently selected volume */ | |
830 | if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) | |
831 | val = max98090->pa1en + 1; | |
832 | else | |
833 | val = max98090->pa2en + 1; | |
834 | break; | |
835 | case SND_SOC_DAPM_POST_PMD: | |
836 | /* If turning off, turn off */ | |
837 | val = 0; | |
838 | break; | |
839 | default: | |
840 | return -EINVAL; | |
841 | } | |
842 | ||
843 | if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) | |
844 | snd_soc_update_bits(codec, w->reg, M98090_MIC_PA1EN_MASK, | |
845 | val << M98090_MIC_PA1EN_SHIFT); | |
846 | else | |
847 | snd_soc_update_bits(codec, w->reg, M98090_MIC_PA2EN_MASK, | |
848 | val << M98090_MIC_PA2EN_SHIFT); | |
849 | ||
850 | return 0; | |
851 | } | |
852 | ||
853 | static const char *mic1_mux_text[] = { "IN12", "IN56" }; | |
854 | ||
2907cbcc TI |
855 | static SOC_ENUM_SINGLE_DECL(mic1_mux_enum, |
856 | M98090_REG_INPUT_MODE, | |
857 | M98090_EXTMIC1_SHIFT, | |
858 | mic1_mux_text); | |
685e4215 JW |
859 | |
860 | static const struct snd_kcontrol_new max98090_mic1_mux = | |
861 | SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum); | |
862 | ||
863 | static const char *mic2_mux_text[] = { "IN34", "IN56" }; | |
864 | ||
2907cbcc TI |
865 | static SOC_ENUM_SINGLE_DECL(mic2_mux_enum, |
866 | M98090_REG_INPUT_MODE, | |
867 | M98090_EXTMIC2_SHIFT, | |
868 | mic2_mux_text); | |
685e4215 JW |
869 | |
870 | static const struct snd_kcontrol_new max98090_mic2_mux = | |
871 | SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum); | |
872 | ||
fd5f940f AB |
873 | static const char *dmic_mux_text[] = { "ADC", "DMIC" }; |
874 | ||
ba513116 | 875 | static SOC_ENUM_SINGLE_VIRT_DECL(dmic_mux_enum, dmic_mux_text); |
fd5f940f AB |
876 | |
877 | static const struct snd_kcontrol_new max98090_dmic_mux = | |
878 | SOC_DAPM_ENUM_VIRT("DMIC Mux", dmic_mux_enum); | |
879 | ||
4ca74feb | 880 | static const char *max98090_micpre_text[] = { "Off", "On" }; |
685e4215 | 881 | |
2907cbcc TI |
882 | static SOC_ENUM_SINGLE_DECL(max98090_pa1en_enum, |
883 | M98090_REG_MIC1_INPUT_LEVEL, | |
884 | M98090_MIC_PA1EN_SHIFT, | |
885 | max98090_micpre_text); | |
685e4215 | 886 | |
2907cbcc TI |
887 | static SOC_ENUM_SINGLE_DECL(max98090_pa2en_enum, |
888 | M98090_REG_MIC2_INPUT_LEVEL, | |
889 | M98090_MIC_PA2EN_SHIFT, | |
890 | max98090_micpre_text); | |
685e4215 JW |
891 | |
892 | /* LINEA mixer switch */ | |
893 | static const struct snd_kcontrol_new max98090_linea_mixer_controls[] = { | |
894 | SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG, | |
895 | M98090_IN1SEEN_SHIFT, 1, 0), | |
896 | SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG, | |
897 | M98090_IN3SEEN_SHIFT, 1, 0), | |
898 | SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG, | |
899 | M98090_IN5SEEN_SHIFT, 1, 0), | |
900 | SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG, | |
901 | M98090_IN34DIFF_SHIFT, 1, 0), | |
902 | }; | |
903 | ||
904 | /* LINEB mixer switch */ | |
905 | static const struct snd_kcontrol_new max98090_lineb_mixer_controls[] = { | |
906 | SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG, | |
907 | M98090_IN2SEEN_SHIFT, 1, 0), | |
908 | SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG, | |
909 | M98090_IN4SEEN_SHIFT, 1, 0), | |
910 | SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG, | |
911 | M98090_IN6SEEN_SHIFT, 1, 0), | |
912 | SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG, | |
913 | M98090_IN56DIFF_SHIFT, 1, 0), | |
914 | }; | |
915 | ||
916 | /* Left ADC mixer switch */ | |
917 | static const struct snd_kcontrol_new max98090_left_adc_mixer_controls[] = { | |
918 | SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER, | |
919 | M98090_MIXADL_IN12DIFF_SHIFT, 1, 0), | |
920 | SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER, | |
921 | M98090_MIXADL_IN34DIFF_SHIFT, 1, 0), | |
922 | SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER, | |
923 | M98090_MIXADL_IN65DIFF_SHIFT, 1, 0), | |
924 | SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER, | |
925 | M98090_MIXADL_LINEA_SHIFT, 1, 0), | |
926 | SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER, | |
927 | M98090_MIXADL_LINEB_SHIFT, 1, 0), | |
928 | SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER, | |
929 | M98090_MIXADL_MIC1_SHIFT, 1, 0), | |
930 | SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER, | |
931 | M98090_MIXADL_MIC2_SHIFT, 1, 0), | |
932 | }; | |
933 | ||
934 | /* Right ADC mixer switch */ | |
935 | static const struct snd_kcontrol_new max98090_right_adc_mixer_controls[] = { | |
936 | SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER, | |
937 | M98090_MIXADR_IN12DIFF_SHIFT, 1, 0), | |
938 | SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER, | |
939 | M98090_MIXADR_IN34DIFF_SHIFT, 1, 0), | |
940 | SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER, | |
941 | M98090_MIXADR_IN65DIFF_SHIFT, 1, 0), | |
942 | SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER, | |
943 | M98090_MIXADR_LINEA_SHIFT, 1, 0), | |
944 | SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER, | |
945 | M98090_MIXADR_LINEB_SHIFT, 1, 0), | |
946 | SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER, | |
947 | M98090_MIXADR_MIC1_SHIFT, 1, 0), | |
948 | SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER, | |
949 | M98090_MIXADR_MIC2_SHIFT, 1, 0), | |
950 | }; | |
951 | ||
952 | static const char *lten_mux_text[] = { "Normal", "Loopthrough" }; | |
953 | ||
2907cbcc TI |
954 | static SOC_ENUM_SINGLE_DECL(ltenl_mux_enum, |
955 | M98090_REG_IO_CONFIGURATION, | |
956 | M98090_LTEN_SHIFT, | |
957 | lten_mux_text); | |
685e4215 | 958 | |
2907cbcc TI |
959 | static SOC_ENUM_SINGLE_DECL(ltenr_mux_enum, |
960 | M98090_REG_IO_CONFIGURATION, | |
961 | M98090_LTEN_SHIFT, | |
962 | lten_mux_text); | |
685e4215 JW |
963 | |
964 | static const struct snd_kcontrol_new max98090_ltenl_mux = | |
965 | SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum); | |
966 | ||
967 | static const struct snd_kcontrol_new max98090_ltenr_mux = | |
968 | SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum); | |
969 | ||
970 | static const char *lben_mux_text[] = { "Normal", "Loopback" }; | |
971 | ||
2907cbcc TI |
972 | static SOC_ENUM_SINGLE_DECL(lbenl_mux_enum, |
973 | M98090_REG_IO_CONFIGURATION, | |
974 | M98090_LBEN_SHIFT, | |
975 | lben_mux_text); | |
685e4215 | 976 | |
2907cbcc TI |
977 | static SOC_ENUM_SINGLE_DECL(lbenr_mux_enum, |
978 | M98090_REG_IO_CONFIGURATION, | |
979 | M98090_LBEN_SHIFT, | |
980 | lben_mux_text); | |
685e4215 JW |
981 | |
982 | static const struct snd_kcontrol_new max98090_lbenl_mux = | |
983 | SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum); | |
984 | ||
985 | static const struct snd_kcontrol_new max98090_lbenr_mux = | |
986 | SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum); | |
987 | ||
988 | static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" }; | |
989 | ||
990 | static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" }; | |
991 | ||
2907cbcc TI |
992 | static SOC_ENUM_SINGLE_DECL(stenl_mux_enum, |
993 | M98090_REG_ADC_SIDETONE, | |
994 | M98090_DSTSL_SHIFT, | |
995 | stenl_mux_text); | |
685e4215 | 996 | |
2907cbcc TI |
997 | static SOC_ENUM_SINGLE_DECL(stenr_mux_enum, |
998 | M98090_REG_ADC_SIDETONE, | |
999 | M98090_DSTSR_SHIFT, | |
1000 | stenr_mux_text); | |
685e4215 JW |
1001 | |
1002 | static const struct snd_kcontrol_new max98090_stenl_mux = | |
1003 | SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum); | |
1004 | ||
1005 | static const struct snd_kcontrol_new max98090_stenr_mux = | |
1006 | SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum); | |
1007 | ||
1008 | /* Left speaker mixer switch */ | |
1009 | static const struct | |
1010 | snd_kcontrol_new max98090_left_speaker_mixer_controls[] = { | |
1011 | SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER, | |
1012 | M98090_MIXSPL_DACL_SHIFT, 1, 0), | |
1013 | SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER, | |
1014 | M98090_MIXSPL_DACR_SHIFT, 1, 0), | |
1015 | SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER, | |
1016 | M98090_MIXSPL_LINEA_SHIFT, 1, 0), | |
1017 | SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER, | |
1018 | M98090_MIXSPL_LINEB_SHIFT, 1, 0), | |
1019 | SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER, | |
1020 | M98090_MIXSPL_MIC1_SHIFT, 1, 0), | |
1021 | SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER, | |
1022 | M98090_MIXSPL_MIC2_SHIFT, 1, 0), | |
1023 | }; | |
1024 | ||
1025 | /* Right speaker mixer switch */ | |
1026 | static const struct | |
1027 | snd_kcontrol_new max98090_right_speaker_mixer_controls[] = { | |
1028 | SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER, | |
1029 | M98090_MIXSPR_DACL_SHIFT, 1, 0), | |
1030 | SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER, | |
1031 | M98090_MIXSPR_DACR_SHIFT, 1, 0), | |
1032 | SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER, | |
1033 | M98090_MIXSPR_LINEA_SHIFT, 1, 0), | |
1034 | SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER, | |
1035 | M98090_MIXSPR_LINEB_SHIFT, 1, 0), | |
1036 | SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER, | |
1037 | M98090_MIXSPR_MIC1_SHIFT, 1, 0), | |
1038 | SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER, | |
1039 | M98090_MIXSPR_MIC2_SHIFT, 1, 0), | |
1040 | }; | |
1041 | ||
1042 | /* Left headphone mixer switch */ | |
1043 | static const struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = { | |
1044 | SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER, | |
1045 | M98090_MIXHPL_DACL_SHIFT, 1, 0), | |
1046 | SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER, | |
1047 | M98090_MIXHPL_DACR_SHIFT, 1, 0), | |
1048 | SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER, | |
1049 | M98090_MIXHPL_LINEA_SHIFT, 1, 0), | |
1050 | SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER, | |
1051 | M98090_MIXHPL_LINEB_SHIFT, 1, 0), | |
1052 | SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER, | |
1053 | M98090_MIXHPL_MIC1_SHIFT, 1, 0), | |
1054 | SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER, | |
1055 | M98090_MIXHPL_MIC2_SHIFT, 1, 0), | |
1056 | }; | |
1057 | ||
1058 | /* Right headphone mixer switch */ | |
1059 | static const struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = { | |
1060 | SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER, | |
1061 | M98090_MIXHPR_DACL_SHIFT, 1, 0), | |
1062 | SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER, | |
1063 | M98090_MIXHPR_DACR_SHIFT, 1, 0), | |
1064 | SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER, | |
1065 | M98090_MIXHPR_LINEA_SHIFT, 1, 0), | |
1066 | SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER, | |
1067 | M98090_MIXHPR_LINEB_SHIFT, 1, 0), | |
1068 | SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER, | |
1069 | M98090_MIXHPR_MIC1_SHIFT, 1, 0), | |
1070 | SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER, | |
1071 | M98090_MIXHPR_MIC2_SHIFT, 1, 0), | |
1072 | }; | |
1073 | ||
1074 | /* Left receiver mixer switch */ | |
1075 | static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls[] = { | |
1076 | SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER, | |
1077 | M98090_MIXRCVL_DACL_SHIFT, 1, 0), | |
1078 | SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER, | |
1079 | M98090_MIXRCVL_DACR_SHIFT, 1, 0), | |
1080 | SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER, | |
1081 | M98090_MIXRCVL_LINEA_SHIFT, 1, 0), | |
1082 | SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER, | |
1083 | M98090_MIXRCVL_LINEB_SHIFT, 1, 0), | |
1084 | SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER, | |
1085 | M98090_MIXRCVL_MIC1_SHIFT, 1, 0), | |
1086 | SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER, | |
1087 | M98090_MIXRCVL_MIC2_SHIFT, 1, 0), | |
1088 | }; | |
1089 | ||
1090 | /* Right receiver mixer switch */ | |
1091 | static const struct snd_kcontrol_new max98090_right_rcv_mixer_controls[] = { | |
1092 | SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER, | |
1093 | M98090_MIXRCVR_DACL_SHIFT, 1, 0), | |
1094 | SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER, | |
1095 | M98090_MIXRCVR_DACR_SHIFT, 1, 0), | |
1096 | SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER, | |
1097 | M98090_MIXRCVR_LINEA_SHIFT, 1, 0), | |
1098 | SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER, | |
1099 | M98090_MIXRCVR_LINEB_SHIFT, 1, 0), | |
1100 | SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER, | |
1101 | M98090_MIXRCVR_MIC1_SHIFT, 1, 0), | |
1102 | SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER, | |
1103 | M98090_MIXRCVR_MIC2_SHIFT, 1, 0), | |
1104 | }; | |
1105 | ||
1106 | static const char *linmod_mux_text[] = { "Left Only", "Left and Right" }; | |
1107 | ||
2907cbcc TI |
1108 | static SOC_ENUM_SINGLE_DECL(linmod_mux_enum, |
1109 | M98090_REG_LOUTR_MIXER, | |
1110 | M98090_LINMOD_SHIFT, | |
1111 | linmod_mux_text); | |
685e4215 JW |
1112 | |
1113 | static const struct snd_kcontrol_new max98090_linmod_mux = | |
1114 | SOC_DAPM_ENUM("LINMOD Mux", linmod_mux_enum); | |
1115 | ||
1116 | static const char *mixhpsel_mux_text[] = { "DAC Only", "HP Mixer" }; | |
1117 | ||
1118 | /* | |
1119 | * This is a mux as it selects the HP output, but to DAPM it is a Mixer enable | |
1120 | */ | |
2907cbcc TI |
1121 | static SOC_ENUM_SINGLE_DECL(mixhplsel_mux_enum, |
1122 | M98090_REG_HP_CONTROL, | |
1123 | M98090_MIXHPLSEL_SHIFT, | |
1124 | mixhpsel_mux_text); | |
685e4215 JW |
1125 | |
1126 | static const struct snd_kcontrol_new max98090_mixhplsel_mux = | |
1127 | SOC_DAPM_ENUM("MIXHPLSEL Mux", mixhplsel_mux_enum); | |
1128 | ||
2907cbcc TI |
1129 | static SOC_ENUM_SINGLE_DECL(mixhprsel_mux_enum, |
1130 | M98090_REG_HP_CONTROL, | |
1131 | M98090_MIXHPRSEL_SHIFT, | |
1132 | mixhpsel_mux_text); | |
685e4215 JW |
1133 | |
1134 | static const struct snd_kcontrol_new max98090_mixhprsel_mux = | |
1135 | SOC_DAPM_ENUM("MIXHPRSEL Mux", mixhprsel_mux_enum); | |
1136 | ||
1137 | static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = { | |
1138 | ||
1139 | SND_SOC_DAPM_INPUT("MIC1"), | |
1140 | SND_SOC_DAPM_INPUT("MIC2"), | |
1141 | SND_SOC_DAPM_INPUT("DMICL"), | |
1142 | SND_SOC_DAPM_INPUT("DMICR"), | |
1143 | SND_SOC_DAPM_INPUT("IN1"), | |
1144 | SND_SOC_DAPM_INPUT("IN2"), | |
1145 | SND_SOC_DAPM_INPUT("IN3"), | |
1146 | SND_SOC_DAPM_INPUT("IN4"), | |
1147 | SND_SOC_DAPM_INPUT("IN5"), | |
1148 | SND_SOC_DAPM_INPUT("IN6"), | |
1149 | SND_SOC_DAPM_INPUT("IN12"), | |
1150 | SND_SOC_DAPM_INPUT("IN34"), | |
1151 | SND_SOC_DAPM_INPUT("IN56"), | |
1152 | ||
1153 | SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE, | |
1154 | M98090_MBEN_SHIFT, 0, NULL, 0), | |
1155 | SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN, | |
1156 | M98090_SHDNN_SHIFT, 0, NULL, 0), | |
1157 | SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION, | |
1158 | M98090_SDIEN_SHIFT, 0, NULL, 0), | |
1159 | SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION, | |
1160 | M98090_SDOEN_SHIFT, 0, NULL, 0), | |
1161 | SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE, | |
1162 | M98090_DIGMICL_SHIFT, 0, NULL, 0), | |
1163 | SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE, | |
1164 | M98090_DIGMICR_SHIFT, 0, NULL, 0), | |
1165 | SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG, | |
1166 | M98090_AHPF_SHIFT, 0, NULL, 0), | |
1167 | ||
1168 | /* | |
1169 | * Note: Sysclk and misc power supplies are taken care of by SHDN | |
1170 | */ | |
1171 | ||
1172 | SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM, | |
1173 | 0, 0, &max98090_mic1_mux), | |
1174 | ||
1175 | SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM, | |
1176 | 0, 0, &max98090_mic2_mux), | |
1177 | ||
fd5f940f AB |
1178 | SND_SOC_DAPM_VIRT_MUX("DMIC Mux", SND_SOC_NOPM, |
1179 | 0, 0, &max98090_dmic_mux), | |
1180 | ||
685e4215 JW |
1181 | SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL, |
1182 | M98090_MIC_PA1EN_SHIFT, 0, NULL, 0, max98090_micinput_event, | |
1183 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), | |
1184 | ||
1185 | SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL, | |
1186 | M98090_MIC_PA2EN_SHIFT, 0, NULL, 0, max98090_micinput_event, | |
1187 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), | |
1188 | ||
1189 | SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM, 0, 0, | |
1190 | &max98090_linea_mixer_controls[0], | |
1191 | ARRAY_SIZE(max98090_linea_mixer_controls)), | |
1192 | ||
1193 | SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM, 0, 0, | |
1194 | &max98090_lineb_mixer_controls[0], | |
1195 | ARRAY_SIZE(max98090_lineb_mixer_controls)), | |
1196 | ||
1197 | SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE, | |
1198 | M98090_LINEAEN_SHIFT, 0, NULL, 0), | |
1199 | SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE, | |
1200 | M98090_LINEBEN_SHIFT, 0, NULL, 0), | |
1201 | ||
1202 | SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0, | |
1203 | &max98090_left_adc_mixer_controls[0], | |
1204 | ARRAY_SIZE(max98090_left_adc_mixer_controls)), | |
1205 | ||
1206 | SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0, | |
1207 | &max98090_right_adc_mixer_controls[0], | |
1208 | ARRAY_SIZE(max98090_right_adc_mixer_controls)), | |
1209 | ||
1210 | SND_SOC_DAPM_ADC("ADCL", NULL, M98090_REG_INPUT_ENABLE, | |
1211 | M98090_ADLEN_SHIFT, 0), | |
1212 | SND_SOC_DAPM_ADC("ADCR", NULL, M98090_REG_INPUT_ENABLE, | |
1213 | M98090_ADREN_SHIFT, 0), | |
1214 | ||
1215 | SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0, | |
1216 | SND_SOC_NOPM, 0, 0), | |
1217 | SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1, | |
1218 | SND_SOC_NOPM, 0, 0), | |
1219 | ||
1220 | SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM, | |
1221 | 0, 0, &max98090_lbenl_mux), | |
1222 | ||
1223 | SND_SOC_DAPM_MUX("LBENR Mux", SND_SOC_NOPM, | |
1224 | 0, 0, &max98090_lbenr_mux), | |
1225 | ||
1226 | SND_SOC_DAPM_MUX("LTENL Mux", SND_SOC_NOPM, | |
1227 | 0, 0, &max98090_ltenl_mux), | |
1228 | ||
1229 | SND_SOC_DAPM_MUX("LTENR Mux", SND_SOC_NOPM, | |
1230 | 0, 0, &max98090_ltenr_mux), | |
1231 | ||
1232 | SND_SOC_DAPM_MUX("STENL Mux", SND_SOC_NOPM, | |
1233 | 0, 0, &max98090_stenl_mux), | |
1234 | ||
1235 | SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM, | |
1236 | 0, 0, &max98090_stenr_mux), | |
1237 | ||
1238 | SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0), | |
1239 | SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0), | |
1240 | ||
1241 | SND_SOC_DAPM_DAC("DACL", NULL, M98090_REG_OUTPUT_ENABLE, | |
1242 | M98090_DALEN_SHIFT, 0), | |
1243 | SND_SOC_DAPM_DAC("DACR", NULL, M98090_REG_OUTPUT_ENABLE, | |
1244 | M98090_DAREN_SHIFT, 0), | |
1245 | ||
1246 | SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0, | |
1247 | &max98090_left_hp_mixer_controls[0], | |
1248 | ARRAY_SIZE(max98090_left_hp_mixer_controls)), | |
1249 | ||
1250 | SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0, | |
1251 | &max98090_right_hp_mixer_controls[0], | |
1252 | ARRAY_SIZE(max98090_right_hp_mixer_controls)), | |
1253 | ||
1254 | SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0, | |
1255 | &max98090_left_speaker_mixer_controls[0], | |
1256 | ARRAY_SIZE(max98090_left_speaker_mixer_controls)), | |
1257 | ||
1258 | SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0, | |
1259 | &max98090_right_speaker_mixer_controls[0], | |
1260 | ARRAY_SIZE(max98090_right_speaker_mixer_controls)), | |
1261 | ||
1262 | SND_SOC_DAPM_MIXER("Left Receiver Mixer", SND_SOC_NOPM, 0, 0, | |
1263 | &max98090_left_rcv_mixer_controls[0], | |
1264 | ARRAY_SIZE(max98090_left_rcv_mixer_controls)), | |
1265 | ||
1266 | SND_SOC_DAPM_MIXER("Right Receiver Mixer", SND_SOC_NOPM, 0, 0, | |
1267 | &max98090_right_rcv_mixer_controls[0], | |
1268 | ARRAY_SIZE(max98090_right_rcv_mixer_controls)), | |
1269 | ||
1270 | SND_SOC_DAPM_MUX("LINMOD Mux", M98090_REG_LOUTR_MIXER, | |
1271 | M98090_LINMOD_SHIFT, 0, &max98090_linmod_mux), | |
1272 | ||
1273 | SND_SOC_DAPM_MUX("MIXHPLSEL Mux", M98090_REG_HP_CONTROL, | |
1274 | M98090_MIXHPLSEL_SHIFT, 0, &max98090_mixhplsel_mux), | |
1275 | ||
1276 | SND_SOC_DAPM_MUX("MIXHPRSEL Mux", M98090_REG_HP_CONTROL, | |
1277 | M98090_MIXHPRSEL_SHIFT, 0, &max98090_mixhprsel_mux), | |
1278 | ||
1279 | SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE, | |
1280 | M98090_HPLEN_SHIFT, 0, NULL, 0), | |
1281 | SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE, | |
1282 | M98090_HPREN_SHIFT, 0, NULL, 0), | |
1283 | ||
1284 | SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE, | |
1285 | M98090_SPLEN_SHIFT, 0, NULL, 0), | |
1286 | SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE, | |
1287 | M98090_SPREN_SHIFT, 0, NULL, 0), | |
1288 | ||
1289 | SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE, | |
1290 | M98090_RCVLEN_SHIFT, 0, NULL, 0), | |
1291 | SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE, | |
1292 | M98090_RCVREN_SHIFT, 0, NULL, 0), | |
1293 | ||
1294 | SND_SOC_DAPM_OUTPUT("HPL"), | |
1295 | SND_SOC_DAPM_OUTPUT("HPR"), | |
1296 | SND_SOC_DAPM_OUTPUT("SPKL"), | |
1297 | SND_SOC_DAPM_OUTPUT("SPKR"), | |
1298 | SND_SOC_DAPM_OUTPUT("RCVL"), | |
1299 | SND_SOC_DAPM_OUTPUT("RCVR"), | |
1300 | }; | |
1301 | ||
1302 | static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = { | |
1303 | ||
1304 | SND_SOC_DAPM_INPUT("DMIC3"), | |
1305 | SND_SOC_DAPM_INPUT("DMIC4"), | |
1306 | ||
1307 | SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE, | |
1308 | M98090_DIGMIC3_SHIFT, 0, NULL, 0), | |
1309 | SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE, | |
1310 | M98090_DIGMIC4_SHIFT, 0, NULL, 0), | |
1311 | }; | |
1312 | ||
1313 | static const struct snd_soc_dapm_route max98090_dapm_routes[] = { | |
1314 | ||
1315 | {"MIC1 Input", NULL, "MIC1"}, | |
1316 | {"MIC2 Input", NULL, "MIC2"}, | |
1317 | ||
1318 | {"DMICL", NULL, "DMICL_ENA"}, | |
1319 | {"DMICR", NULL, "DMICR_ENA"}, | |
1320 | {"DMICL", NULL, "AHPF"}, | |
1321 | {"DMICR", NULL, "AHPF"}, | |
1322 | ||
1323 | /* MIC1 input mux */ | |
1324 | {"MIC1 Mux", "IN12", "IN12"}, | |
1325 | {"MIC1 Mux", "IN56", "IN56"}, | |
1326 | ||
1327 | /* MIC2 input mux */ | |
1328 | {"MIC2 Mux", "IN34", "IN34"}, | |
1329 | {"MIC2 Mux", "IN56", "IN56"}, | |
1330 | ||
1331 | {"MIC1 Input", NULL, "MIC1 Mux"}, | |
1332 | {"MIC2 Input", NULL, "MIC2 Mux"}, | |
1333 | ||
1334 | /* Left ADC input mixer */ | |
1335 | {"Left ADC Mixer", "IN12 Switch", "IN12"}, | |
1336 | {"Left ADC Mixer", "IN34 Switch", "IN34"}, | |
1337 | {"Left ADC Mixer", "IN56 Switch", "IN56"}, | |
1338 | {"Left ADC Mixer", "LINEA Switch", "LINEA Input"}, | |
1339 | {"Left ADC Mixer", "LINEB Switch", "LINEB Input"}, | |
1340 | {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1341 | {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1342 | ||
1343 | /* Right ADC input mixer */ | |
1344 | {"Right ADC Mixer", "IN12 Switch", "IN12"}, | |
1345 | {"Right ADC Mixer", "IN34 Switch", "IN34"}, | |
1346 | {"Right ADC Mixer", "IN56 Switch", "IN56"}, | |
1347 | {"Right ADC Mixer", "LINEA Switch", "LINEA Input"}, | |
1348 | {"Right ADC Mixer", "LINEB Switch", "LINEB Input"}, | |
1349 | {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1350 | {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1351 | ||
1352 | /* Line A input mixer */ | |
1353 | {"LINEA Mixer", "IN1 Switch", "IN1"}, | |
1354 | {"LINEA Mixer", "IN3 Switch", "IN3"}, | |
1355 | {"LINEA Mixer", "IN5 Switch", "IN5"}, | |
1356 | {"LINEA Mixer", "IN34 Switch", "IN34"}, | |
1357 | ||
1358 | /* Line B input mixer */ | |
1359 | {"LINEB Mixer", "IN2 Switch", "IN2"}, | |
1360 | {"LINEB Mixer", "IN4 Switch", "IN4"}, | |
1361 | {"LINEB Mixer", "IN6 Switch", "IN6"}, | |
1362 | {"LINEB Mixer", "IN56 Switch", "IN56"}, | |
1363 | ||
1364 | {"LINEA Input", NULL, "LINEA Mixer"}, | |
1365 | {"LINEB Input", NULL, "LINEB Mixer"}, | |
1366 | ||
1367 | /* Inputs */ | |
1368 | {"ADCL", NULL, "Left ADC Mixer"}, | |
1369 | {"ADCR", NULL, "Right ADC Mixer"}, | |
1370 | {"ADCL", NULL, "SHDN"}, | |
1371 | {"ADCR", NULL, "SHDN"}, | |
1372 | ||
fd5f940f AB |
1373 | {"DMIC Mux", "ADC", "ADCL"}, |
1374 | {"DMIC Mux", "ADC", "ADCR"}, | |
1375 | {"DMIC Mux", "DMIC", "DMICL"}, | |
1376 | {"DMIC Mux", "DMIC", "DMICR"}, | |
1377 | ||
1378 | {"LBENL Mux", "Normal", "DMIC Mux"}, | |
685e4215 | 1379 | {"LBENL Mux", "Loopback", "LTENL Mux"}, |
fd5f940f | 1380 | {"LBENR Mux", "Normal", "DMIC Mux"}, |
685e4215 JW |
1381 | {"LBENR Mux", "Loopback", "LTENR Mux"}, |
1382 | ||
1383 | {"AIFOUTL", NULL, "LBENL Mux"}, | |
1384 | {"AIFOUTR", NULL, "LBENR Mux"}, | |
1385 | {"AIFOUTL", NULL, "SHDN"}, | |
1386 | {"AIFOUTR", NULL, "SHDN"}, | |
1387 | {"AIFOUTL", NULL, "SDOEN"}, | |
1388 | {"AIFOUTR", NULL, "SDOEN"}, | |
1389 | ||
1390 | {"LTENL Mux", "Normal", "AIFINL"}, | |
1391 | {"LTENL Mux", "Loopthrough", "LBENL Mux"}, | |
1392 | {"LTENR Mux", "Normal", "AIFINR"}, | |
1393 | {"LTENR Mux", "Loopthrough", "LBENR Mux"}, | |
1394 | ||
1395 | {"DACL", NULL, "LTENL Mux"}, | |
1396 | {"DACR", NULL, "LTENR Mux"}, | |
1397 | ||
1398 | {"STENL Mux", "Sidetone Left", "ADCL"}, | |
1399 | {"STENL Mux", "Sidetone Left", "DMICL"}, | |
1400 | {"STENR Mux", "Sidetone Right", "ADCR"}, | |
1401 | {"STENR Mux", "Sidetone Right", "DMICR"}, | |
1402 | {"DACL", "NULL", "STENL Mux"}, | |
1403 | {"DACR", "NULL", "STENL Mux"}, | |
1404 | ||
1405 | {"AIFINL", NULL, "SHDN"}, | |
1406 | {"AIFINR", NULL, "SHDN"}, | |
1407 | {"AIFINL", NULL, "SDIEN"}, | |
1408 | {"AIFINR", NULL, "SDIEN"}, | |
1409 | {"DACL", NULL, "SHDN"}, | |
1410 | {"DACR", NULL, "SHDN"}, | |
1411 | ||
1412 | /* Left headphone output mixer */ | |
1413 | {"Left Headphone Mixer", "Left DAC Switch", "DACL"}, | |
1414 | {"Left Headphone Mixer", "Right DAC Switch", "DACR"}, | |
1415 | {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1416 | {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1417 | {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"}, | |
1418 | {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"}, | |
1419 | ||
1420 | /* Right headphone output mixer */ | |
1421 | {"Right Headphone Mixer", "Left DAC Switch", "DACL"}, | |
1422 | {"Right Headphone Mixer", "Right DAC Switch", "DACR"}, | |
1423 | {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1424 | {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1425 | {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"}, | |
1426 | {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"}, | |
1427 | ||
1428 | /* Left speaker output mixer */ | |
1429 | {"Left Speaker Mixer", "Left DAC Switch", "DACL"}, | |
1430 | {"Left Speaker Mixer", "Right DAC Switch", "DACR"}, | |
1431 | {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1432 | {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1433 | {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"}, | |
1434 | {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"}, | |
1435 | ||
1436 | /* Right speaker output mixer */ | |
1437 | {"Right Speaker Mixer", "Left DAC Switch", "DACL"}, | |
1438 | {"Right Speaker Mixer", "Right DAC Switch", "DACR"}, | |
1439 | {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1440 | {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1441 | {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"}, | |
1442 | {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"}, | |
1443 | ||
1444 | /* Left Receiver output mixer */ | |
1445 | {"Left Receiver Mixer", "Left DAC Switch", "DACL"}, | |
1446 | {"Left Receiver Mixer", "Right DAC Switch", "DACR"}, | |
1447 | {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1448 | {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1449 | {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"}, | |
1450 | {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"}, | |
1451 | ||
1452 | /* Right Receiver output mixer */ | |
1453 | {"Right Receiver Mixer", "Left DAC Switch", "DACL"}, | |
1454 | {"Right Receiver Mixer", "Right DAC Switch", "DACR"}, | |
1455 | {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1456 | {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1457 | {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"}, | |
1458 | {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"}, | |
1459 | ||
1460 | {"MIXHPLSEL Mux", "HP Mixer", "Left Headphone Mixer"}, | |
1461 | ||
1462 | /* | |
1463 | * Disable this for lowest power if bypassing | |
1464 | * the DAC with an analog signal | |
1465 | */ | |
1466 | {"HP Left Out", NULL, "DACL"}, | |
1467 | {"HP Left Out", NULL, "MIXHPLSEL Mux"}, | |
1468 | ||
1469 | {"MIXHPRSEL Mux", "HP Mixer", "Right Headphone Mixer"}, | |
1470 | ||
1471 | /* | |
1472 | * Disable this for lowest power if bypassing | |
1473 | * the DAC with an analog signal | |
1474 | */ | |
1475 | {"HP Right Out", NULL, "DACR"}, | |
1476 | {"HP Right Out", NULL, "MIXHPRSEL Mux"}, | |
1477 | ||
1478 | {"SPK Left Out", NULL, "Left Speaker Mixer"}, | |
1479 | {"SPK Right Out", NULL, "Right Speaker Mixer"}, | |
1480 | {"RCV Left Out", NULL, "Left Receiver Mixer"}, | |
1481 | ||
1482 | {"LINMOD Mux", "Left and Right", "Right Receiver Mixer"}, | |
1483 | {"LINMOD Mux", "Left Only", "Left Receiver Mixer"}, | |
1484 | {"RCV Right Out", NULL, "LINMOD Mux"}, | |
1485 | ||
1486 | {"HPL", NULL, "HP Left Out"}, | |
1487 | {"HPR", NULL, "HP Right Out"}, | |
1488 | {"SPKL", NULL, "SPK Left Out"}, | |
1489 | {"SPKR", NULL, "SPK Right Out"}, | |
1490 | {"RCVL", NULL, "RCV Left Out"}, | |
1491 | {"RCVR", NULL, "RCV Right Out"}, | |
1492 | ||
1493 | }; | |
1494 | ||
1495 | static const struct snd_soc_dapm_route max98091_dapm_routes[] = { | |
1496 | ||
1497 | /* DMIC inputs */ | |
1498 | {"DMIC3", NULL, "DMIC3_ENA"}, | |
1499 | {"DMIC4", NULL, "DMIC4_ENA"}, | |
1500 | {"DMIC3", NULL, "AHPF"}, | |
1501 | {"DMIC4", NULL, "AHPF"}, | |
1502 | ||
1503 | }; | |
1504 | ||
1505 | static int max98090_add_widgets(struct snd_soc_codec *codec) | |
1506 | { | |
1507 | struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); | |
1508 | struct snd_soc_dapm_context *dapm = &codec->dapm; | |
1509 | ||
1510 | snd_soc_add_codec_controls(codec, max98090_snd_controls, | |
1511 | ARRAY_SIZE(max98090_snd_controls)); | |
1512 | ||
1513 | if (max98090->devtype == MAX98091) { | |
1514 | snd_soc_add_codec_controls(codec, max98091_snd_controls, | |
1515 | ARRAY_SIZE(max98091_snd_controls)); | |
1516 | } | |
1517 | ||
1518 | snd_soc_dapm_new_controls(dapm, max98090_dapm_widgets, | |
1519 | ARRAY_SIZE(max98090_dapm_widgets)); | |
1520 | ||
1521 | snd_soc_dapm_add_routes(dapm, max98090_dapm_routes, | |
1522 | ARRAY_SIZE(max98090_dapm_routes)); | |
1523 | ||
1524 | if (max98090->devtype == MAX98091) { | |
1525 | snd_soc_dapm_new_controls(dapm, max98091_dapm_widgets, | |
1526 | ARRAY_SIZE(max98091_dapm_widgets)); | |
1527 | ||
1528 | snd_soc_dapm_add_routes(dapm, max98091_dapm_routes, | |
1529 | ARRAY_SIZE(max98091_dapm_routes)); | |
1530 | ||
1531 | } | |
1532 | ||
1533 | return 0; | |
1534 | } | |
1535 | ||
1536 | static const int pclk_rates[] = { | |
1537 | 12000000, 12000000, 13000000, 13000000, | |
1538 | 16000000, 16000000, 19200000, 19200000 | |
1539 | }; | |
1540 | ||
1541 | static const int lrclk_rates[] = { | |
1542 | 8000, 16000, 8000, 16000, | |
1543 | 8000, 16000, 8000, 16000 | |
1544 | }; | |
1545 | ||
1546 | static const int user_pclk_rates[] = { | |
1547 | 13000000, 13000000 | |
1548 | }; | |
1549 | ||
1550 | static const int user_lrclk_rates[] = { | |
1551 | 44100, 48000 | |
1552 | }; | |
1553 | ||
1554 | static const unsigned long long ni_value[] = { | |
1555 | 3528, 768 | |
1556 | }; | |
1557 | ||
1558 | static const unsigned long long mi_value[] = { | |
1559 | 8125, 1625 | |
1560 | }; | |
1561 | ||
1562 | static void max98090_configure_bclk(struct snd_soc_codec *codec) | |
1563 | { | |
1564 | struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); | |
1565 | unsigned long long ni; | |
1566 | int i; | |
1567 | ||
1568 | if (!max98090->sysclk) { | |
1569 | dev_err(codec->dev, "No SYSCLK configured\n"); | |
1570 | return; | |
1571 | } | |
1572 | ||
1573 | if (!max98090->bclk || !max98090->lrclk) { | |
1574 | dev_err(codec->dev, "No audio clocks configured\n"); | |
1575 | return; | |
1576 | } | |
1577 | ||
1578 | /* Skip configuration when operating as slave */ | |
1579 | if (!(snd_soc_read(codec, M98090_REG_MASTER_MODE) & | |
1580 | M98090_MAS_MASK)) { | |
1581 | return; | |
1582 | } | |
1583 | ||
1584 | /* Check for supported PCLK to LRCLK ratios */ | |
1585 | for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) { | |
1586 | if ((pclk_rates[i] == max98090->sysclk) && | |
1587 | (lrclk_rates[i] == max98090->lrclk)) { | |
1588 | dev_dbg(codec->dev, | |
1589 | "Found supported PCLK to LRCLK rates 0x%x\n", | |
1590 | i + 0x8); | |
1591 | ||
1592 | snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, | |
1593 | M98090_FREQ_MASK, | |
1594 | (i + 0x8) << M98090_FREQ_SHIFT); | |
1595 | snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, | |
1596 | M98090_USE_M1_MASK, 0); | |
1597 | return; | |
1598 | } | |
1599 | } | |
1600 | ||
1601 | /* Check for user calculated MI and NI ratios */ | |
1602 | for (i = 0; i < ARRAY_SIZE(user_pclk_rates); i++) { | |
1603 | if ((user_pclk_rates[i] == max98090->sysclk) && | |
1604 | (user_lrclk_rates[i] == max98090->lrclk)) { | |
1605 | dev_dbg(codec->dev, | |
1606 | "Found user supported PCLK to LRCLK rates\n"); | |
1607 | dev_dbg(codec->dev, "i %d ni %lld mi %lld\n", | |
1608 | i, ni_value[i], mi_value[i]); | |
1609 | ||
1610 | snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, | |
1611 | M98090_FREQ_MASK, 0); | |
1612 | snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, | |
1613 | M98090_USE_M1_MASK, | |
1614 | 1 << M98090_USE_M1_SHIFT); | |
1615 | ||
1616 | snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB, | |
1617 | (ni_value[i] >> 8) & 0x7F); | |
1618 | snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB, | |
1619 | ni_value[i] & 0xFF); | |
1620 | snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_MSB, | |
1621 | (mi_value[i] >> 8) & 0x7F); | |
1622 | snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_LSB, | |
1623 | mi_value[i] & 0xFF); | |
1624 | ||
1625 | return; | |
1626 | } | |
1627 | } | |
1628 | ||
1629 | /* | |
1630 | * Calculate based on MI = 65536 (not as good as either method above) | |
1631 | */ | |
1632 | snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, | |
1633 | M98090_FREQ_MASK, 0); | |
1634 | snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, | |
1635 | M98090_USE_M1_MASK, 0); | |
1636 | ||
1637 | /* | |
1638 | * Configure NI when operating as master | |
1639 | * Note: There is a small, but significant audio quality improvement | |
1640 | * by calculating ni and mi. | |
1641 | */ | |
1642 | ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL) | |
1643 | * (unsigned long long int)max98090->lrclk; | |
1644 | do_div(ni, (unsigned long long int)max98090->sysclk); | |
1645 | dev_info(codec->dev, "No better method found\n"); | |
1646 | dev_info(codec->dev, "Calculating ni %lld with mi 65536\n", ni); | |
1647 | snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB, | |
1648 | (ni >> 8) & 0x7F); | |
1649 | snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB, ni & 0xFF); | |
1650 | } | |
1651 | ||
1652 | static int max98090_dai_set_fmt(struct snd_soc_dai *codec_dai, | |
1653 | unsigned int fmt) | |
1654 | { | |
1655 | struct snd_soc_codec *codec = codec_dai->codec; | |
1656 | struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); | |
1657 | struct max98090_cdata *cdata; | |
1658 | u8 regval; | |
1659 | ||
1660 | max98090->dai_fmt = fmt; | |
1661 | cdata = &max98090->dai[0]; | |
1662 | ||
1663 | if (fmt != cdata->fmt) { | |
1664 | cdata->fmt = fmt; | |
1665 | ||
1666 | regval = 0; | |
1667 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1668 | case SND_SOC_DAIFMT_CBS_CFS: | |
1669 | /* Set to slave mode PLL - MAS mode off */ | |
1670 | snd_soc_write(codec, | |
1671 | M98090_REG_CLOCK_RATIO_NI_MSB, 0x00); | |
1672 | snd_soc_write(codec, | |
1673 | M98090_REG_CLOCK_RATIO_NI_LSB, 0x00); | |
1674 | snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, | |
1675 | M98090_USE_M1_MASK, 0); | |
1676 | break; | |
1677 | case SND_SOC_DAIFMT_CBM_CFM: | |
1678 | /* Set to master mode */ | |
1679 | if (max98090->tdm_slots == 4) { | |
1680 | /* TDM */ | |
1681 | regval |= M98090_MAS_MASK | | |
1682 | M98090_BSEL_64; | |
1683 | } else if (max98090->tdm_slots == 3) { | |
1684 | /* TDM */ | |
1685 | regval |= M98090_MAS_MASK | | |
1686 | M98090_BSEL_48; | |
1687 | } else { | |
1688 | /* Few TDM slots, or No TDM */ | |
1689 | regval |= M98090_MAS_MASK | | |
1690 | M98090_BSEL_32; | |
1691 | } | |
1692 | break; | |
1693 | case SND_SOC_DAIFMT_CBS_CFM: | |
1694 | case SND_SOC_DAIFMT_CBM_CFS: | |
1695 | default: | |
1696 | dev_err(codec->dev, "DAI clock mode unsupported"); | |
1697 | return -EINVAL; | |
1698 | } | |
1699 | snd_soc_write(codec, M98090_REG_MASTER_MODE, regval); | |
1700 | ||
1701 | regval = 0; | |
1702 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1703 | case SND_SOC_DAIFMT_I2S: | |
1704 | regval |= M98090_DLY_MASK; | |
1705 | break; | |
1706 | case SND_SOC_DAIFMT_LEFT_J: | |
1707 | break; | |
1708 | case SND_SOC_DAIFMT_RIGHT_J: | |
1709 | regval |= M98090_RJ_MASK; | |
1710 | break; | |
1711 | case SND_SOC_DAIFMT_DSP_A: | |
1712 | /* Not supported mode */ | |
1713 | default: | |
1714 | dev_err(codec->dev, "DAI format unsupported"); | |
1715 | return -EINVAL; | |
1716 | } | |
1717 | ||
1718 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1719 | case SND_SOC_DAIFMT_NB_NF: | |
1720 | break; | |
1721 | case SND_SOC_DAIFMT_NB_IF: | |
1722 | regval |= M98090_WCI_MASK; | |
1723 | break; | |
1724 | case SND_SOC_DAIFMT_IB_NF: | |
1725 | regval |= M98090_BCI_MASK; | |
1726 | break; | |
1727 | case SND_SOC_DAIFMT_IB_IF: | |
1728 | regval |= M98090_BCI_MASK|M98090_WCI_MASK; | |
1729 | break; | |
1730 | default: | |
1731 | dev_err(codec->dev, "DAI invert mode unsupported"); | |
1732 | return -EINVAL; | |
1733 | } | |
1734 | ||
1735 | /* | |
1736 | * This accommodates an inverted logic in the MAX98090 chip | |
1737 | * for Bit Clock Invert (BCI). The inverted logic is only | |
1738 | * seen for the case of TDM mode. The remaining cases have | |
1739 | * normal logic. | |
1740 | */ | |
959b6250 | 1741 | if (max98090->tdm_slots > 1) |
685e4215 | 1742 | regval ^= M98090_BCI_MASK; |
685e4215 JW |
1743 | |
1744 | snd_soc_write(codec, | |
1745 | M98090_REG_INTERFACE_FORMAT, regval); | |
1746 | } | |
1747 | ||
1748 | return 0; | |
1749 | } | |
1750 | ||
1751 | static int max98090_set_tdm_slot(struct snd_soc_dai *codec_dai, | |
1752 | unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) | |
1753 | { | |
1754 | struct snd_soc_codec *codec = codec_dai->codec; | |
1755 | struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); | |
1756 | struct max98090_cdata *cdata; | |
1757 | cdata = &max98090->dai[0]; | |
1758 | ||
1759 | if (slots < 0 || slots > 4) | |
1760 | return -EINVAL; | |
1761 | ||
1762 | max98090->tdm_slots = slots; | |
1763 | max98090->tdm_width = slot_width; | |
1764 | ||
1765 | if (max98090->tdm_slots > 1) { | |
1766 | /* SLOTL SLOTR SLOTDLY */ | |
1767 | snd_soc_write(codec, M98090_REG_TDM_FORMAT, | |
1768 | 0 << M98090_TDM_SLOTL_SHIFT | | |
1769 | 1 << M98090_TDM_SLOTR_SHIFT | | |
1770 | 0 << M98090_TDM_SLOTDLY_SHIFT); | |
1771 | ||
1772 | /* FSW TDM */ | |
1773 | snd_soc_update_bits(codec, M98090_REG_TDM_CONTROL, | |
1774 | M98090_TDM_MASK, | |
1775 | M98090_TDM_MASK); | |
1776 | } | |
1777 | ||
1778 | /* | |
1779 | * Normally advisable to set TDM first, but this permits either order | |
1780 | */ | |
1781 | cdata->fmt = 0; | |
1782 | max98090_dai_set_fmt(codec_dai, max98090->dai_fmt); | |
1783 | ||
1784 | return 0; | |
1785 | } | |
1786 | ||
1787 | static int max98090_set_bias_level(struct snd_soc_codec *codec, | |
1788 | enum snd_soc_bias_level level) | |
1789 | { | |
1790 | struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); | |
1791 | int ret; | |
1792 | ||
1793 | switch (level) { | |
1794 | case SND_SOC_BIAS_ON: | |
685e4215 JW |
1795 | if (max98090->jack_state == M98090_JACK_STATE_HEADSET) { |
1796 | /* | |
1797 | * Set to normal bias level. | |
1798 | */ | |
1799 | snd_soc_update_bits(codec, M98090_REG_MIC_BIAS_VOLTAGE, | |
1800 | M98090_MBVSEL_MASK, M98090_MBVSEL_2V8); | |
1801 | } | |
1802 | break; | |
1803 | ||
1804 | case SND_SOC_BIAS_PREPARE: | |
1805 | break; | |
1806 | ||
1807 | case SND_SOC_BIAS_STANDBY: | |
c42c8922 DR |
1808 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { |
1809 | ret = regcache_sync(max98090->regmap); | |
1810 | if (ret != 0) { | |
1811 | dev_err(codec->dev, | |
1812 | "Failed to sync cache: %d\n", ret); | |
1813 | return ret; | |
1814 | } | |
1815 | } | |
1816 | break; | |
1817 | ||
685e4215 JW |
1818 | case SND_SOC_BIAS_OFF: |
1819 | /* Set internal pull-up to lowest power mode */ | |
1820 | snd_soc_update_bits(codec, M98090_REG_JACK_DETECT, | |
1821 | M98090_JDWK_MASK, M98090_JDWK_MASK); | |
1822 | regcache_mark_dirty(max98090->regmap); | |
1823 | break; | |
1824 | } | |
1825 | codec->dapm.bias_level = level; | |
1826 | return 0; | |
1827 | } | |
1828 | ||
1829 | static const int comp_pclk_rates[] = { | |
1830 | 11289600, 12288000, 12000000, 13000000, 19200000 | |
1831 | }; | |
1832 | ||
1833 | static const int dmic_micclk[] = { | |
1834 | 2, 2, 2, 2, 4, 2 | |
1835 | }; | |
1836 | ||
1837 | static const int comp_lrclk_rates[] = { | |
1838 | 8000, 16000, 32000, 44100, 48000, 96000 | |
1839 | }; | |
1840 | ||
1841 | static const int dmic_comp[6][6] = { | |
1842 | {7, 8, 3, 3, 3, 3}, | |
1843 | {7, 8, 3, 3, 3, 3}, | |
1844 | {7, 8, 3, 3, 3, 3}, | |
1845 | {7, 8, 3, 1, 1, 1}, | |
1846 | {7, 8, 3, 1, 2, 2}, | |
1847 | {7, 8, 3, 3, 3, 3} | |
1848 | }; | |
1849 | ||
1850 | static int max98090_dai_hw_params(struct snd_pcm_substream *substream, | |
1851 | struct snd_pcm_hw_params *params, | |
1852 | struct snd_soc_dai *dai) | |
1853 | { | |
1854 | struct snd_soc_codec *codec = dai->codec; | |
1855 | struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); | |
1856 | struct max98090_cdata *cdata; | |
1857 | int i, j; | |
1858 | ||
1859 | cdata = &max98090->dai[0]; | |
1860 | max98090->bclk = snd_soc_params_to_bclk(params); | |
1861 | if (params_channels(params) == 1) | |
1862 | max98090->bclk *= 2; | |
1863 | ||
1864 | max98090->lrclk = params_rate(params); | |
1865 | ||
7821afc4 MB |
1866 | switch (params_width(params)) { |
1867 | case 16: | |
685e4215 JW |
1868 | snd_soc_update_bits(codec, M98090_REG_INTERFACE_FORMAT, |
1869 | M98090_WS_MASK, 0); | |
1870 | break; | |
1871 | default: | |
1872 | return -EINVAL; | |
1873 | } | |
1874 | ||
1875 | max98090_configure_bclk(codec); | |
1876 | ||
1877 | cdata->rate = max98090->lrclk; | |
1878 | ||
1879 | /* Update filter mode */ | |
1880 | if (max98090->lrclk < 24000) | |
1881 | snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG, | |
1882 | M98090_MODE_MASK, 0); | |
1883 | else | |
1884 | snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG, | |
1885 | M98090_MODE_MASK, M98090_MODE_MASK); | |
1886 | ||
1887 | /* Update sample rate mode */ | |
1888 | if (max98090->lrclk < 50000) | |
1889 | snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG, | |
1890 | M98090_DHF_MASK, 0); | |
1891 | else | |
1892 | snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG, | |
1893 | M98090_DHF_MASK, M98090_DHF_MASK); | |
1894 | ||
1895 | /* Check for supported PCLK to LRCLK ratios */ | |
1896 | for (j = 0; j < ARRAY_SIZE(comp_pclk_rates); j++) { | |
1897 | if (comp_pclk_rates[j] == max98090->sysclk) { | |
1898 | break; | |
1899 | } | |
1900 | } | |
1901 | ||
1902 | for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) { | |
1903 | if (max98090->lrclk <= (comp_lrclk_rates[i] + | |
1904 | comp_lrclk_rates[i + 1]) / 2) { | |
1905 | break; | |
1906 | } | |
1907 | } | |
1908 | ||
1909 | snd_soc_update_bits(codec, M98090_REG_DIGITAL_MIC_ENABLE, | |
1910 | M98090_MICCLK_MASK, | |
1911 | dmic_micclk[j] << M98090_MICCLK_SHIFT); | |
1912 | ||
1913 | snd_soc_update_bits(codec, M98090_REG_DIGITAL_MIC_CONFIG, | |
1914 | M98090_DMIC_COMP_MASK, | |
1915 | dmic_comp[j][i] << M98090_DMIC_COMP_SHIFT); | |
1916 | ||
1917 | return 0; | |
1918 | } | |
1919 | ||
1920 | /* | |
1921 | * PLL / Sysclk | |
1922 | */ | |
1923 | static int max98090_dai_set_sysclk(struct snd_soc_dai *dai, | |
1924 | int clk_id, unsigned int freq, int dir) | |
1925 | { | |
1926 | struct snd_soc_codec *codec = dai->codec; | |
1927 | struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); | |
1928 | ||
1929 | /* Requested clock frequency is already setup */ | |
1930 | if (freq == max98090->sysclk) | |
1931 | return 0; | |
1932 | ||
1933 | /* Setup clocks for slave mode, and using the PLL | |
1934 | * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) | |
1935 | * 0x02 (when master clk is 20MHz to 40MHz).. | |
1936 | * 0x03 (when master clk is 40MHz to 60MHz).. | |
1937 | */ | |
1938 | if ((freq >= 10000000) && (freq < 20000000)) { | |
1939 | snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK, | |
1940 | M98090_PSCLK_DIV1); | |
1941 | } else if ((freq >= 20000000) && (freq < 40000000)) { | |
1942 | snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK, | |
1943 | M98090_PSCLK_DIV2); | |
1944 | } else if ((freq >= 40000000) && (freq < 60000000)) { | |
1945 | snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK, | |
1946 | M98090_PSCLK_DIV4); | |
1947 | } else { | |
1948 | dev_err(codec->dev, "Invalid master clock frequency\n"); | |
1949 | return -EINVAL; | |
1950 | } | |
1951 | ||
1952 | max98090->sysclk = freq; | |
1953 | ||
1954 | max98090_configure_bclk(codec); | |
1955 | ||
1956 | return 0; | |
1957 | } | |
1958 | ||
1959 | static int max98090_dai_digital_mute(struct snd_soc_dai *codec_dai, int mute) | |
1960 | { | |
1961 | struct snd_soc_codec *codec = codec_dai->codec; | |
1962 | int regval; | |
1963 | ||
1964 | regval = mute ? M98090_DVM_MASK : 0; | |
1965 | snd_soc_update_bits(codec, M98090_REG_DAI_PLAYBACK_LEVEL, | |
1966 | M98090_DVM_MASK, regval); | |
1967 | ||
1968 | return 0; | |
1969 | } | |
1970 | ||
1971 | static void max98090_jack_work(struct work_struct *work) | |
1972 | { | |
1973 | struct max98090_priv *max98090 = container_of(work, | |
1974 | struct max98090_priv, | |
1975 | jack_work.work); | |
1976 | struct snd_soc_codec *codec = max98090->codec; | |
1977 | struct snd_soc_dapm_context *dapm = &codec->dapm; | |
1978 | int status = 0; | |
1979 | int reg; | |
1980 | ||
1981 | /* Read a second time */ | |
1982 | if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) { | |
1983 | ||
1984 | /* Strong pull up allows mic detection */ | |
1985 | snd_soc_update_bits(codec, M98090_REG_JACK_DETECT, | |
1986 | M98090_JDWK_MASK, 0); | |
1987 | ||
1988 | msleep(50); | |
1989 | ||
1990 | reg = snd_soc_read(codec, M98090_REG_JACK_STATUS); | |
1991 | ||
1992 | /* Weak pull up allows only insertion detection */ | |
1993 | snd_soc_update_bits(codec, M98090_REG_JACK_DETECT, | |
1994 | M98090_JDWK_MASK, M98090_JDWK_MASK); | |
1995 | } else { | |
1996 | reg = snd_soc_read(codec, M98090_REG_JACK_STATUS); | |
1997 | } | |
1998 | ||
1999 | reg = snd_soc_read(codec, M98090_REG_JACK_STATUS); | |
2000 | ||
2001 | switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) { | |
2002 | case M98090_LSNS_MASK | M98090_JKSNS_MASK: | |
2003 | dev_dbg(codec->dev, "No Headset Detected\n"); | |
2004 | ||
2005 | max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; | |
2006 | ||
2007 | status |= 0; | |
2008 | ||
2009 | break; | |
2010 | ||
2011 | case 0: | |
2012 | if (max98090->jack_state == | |
2013 | M98090_JACK_STATE_HEADSET) { | |
2014 | ||
2015 | dev_dbg(codec->dev, | |
2016 | "Headset Button Down Detected\n"); | |
2017 | ||
2018 | /* | |
2019 | * max98090_headset_button_event(codec) | |
2020 | * could be defined, then called here. | |
2021 | */ | |
2022 | ||
2023 | status |= SND_JACK_HEADSET; | |
2024 | status |= SND_JACK_BTN_0; | |
2025 | ||
2026 | break; | |
2027 | } | |
2028 | ||
2029 | /* Line is reported as Headphone */ | |
2030 | /* Nokia Headset is reported as Headphone */ | |
2031 | /* Mono Headphone is reported as Headphone */ | |
2032 | dev_dbg(codec->dev, "Headphone Detected\n"); | |
2033 | ||
2034 | max98090->jack_state = M98090_JACK_STATE_HEADPHONE; | |
2035 | ||
2036 | status |= SND_JACK_HEADPHONE; | |
2037 | ||
2038 | break; | |
2039 | ||
2040 | case M98090_JKSNS_MASK: | |
2041 | dev_dbg(codec->dev, "Headset Detected\n"); | |
2042 | ||
2043 | max98090->jack_state = M98090_JACK_STATE_HEADSET; | |
2044 | ||
2045 | status |= SND_JACK_HEADSET; | |
2046 | ||
2047 | break; | |
2048 | ||
2049 | default: | |
2050 | dev_dbg(codec->dev, "Unrecognized Jack Status\n"); | |
2051 | break; | |
2052 | } | |
2053 | ||
2054 | snd_soc_jack_report(max98090->jack, status, | |
2055 | SND_JACK_HEADSET | SND_JACK_BTN_0); | |
2056 | ||
2057 | snd_soc_dapm_sync(dapm); | |
2058 | } | |
2059 | ||
2060 | static irqreturn_t max98090_interrupt(int irq, void *data) | |
2061 | { | |
2062 | struct snd_soc_codec *codec = data; | |
2063 | struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); | |
2064 | int ret; | |
2065 | unsigned int mask; | |
2066 | unsigned int active; | |
2067 | ||
2068 | dev_dbg(codec->dev, "***** max98090_interrupt *****\n"); | |
2069 | ||
2070 | ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask); | |
2071 | ||
2072 | if (ret != 0) { | |
2073 | dev_err(codec->dev, | |
2074 | "failed to read M98090_REG_INTERRUPT_S: %d\n", | |
2075 | ret); | |
2076 | return IRQ_NONE; | |
2077 | } | |
2078 | ||
2079 | ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active); | |
2080 | ||
2081 | if (ret != 0) { | |
2082 | dev_err(codec->dev, | |
2083 | "failed to read M98090_REG_DEVICE_STATUS: %d\n", | |
2084 | ret); | |
2085 | return IRQ_NONE; | |
2086 | } | |
2087 | ||
2088 | dev_dbg(codec->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n", | |
2089 | active, mask, active & mask); | |
2090 | ||
2091 | active &= mask; | |
2092 | ||
2093 | if (!active) | |
2094 | return IRQ_NONE; | |
2095 | ||
959b6250 | 2096 | if (active & M98090_CLD_MASK) |
685e4215 | 2097 | dev_err(codec->dev, "M98090_CLD_MASK\n"); |
685e4215 | 2098 | |
959b6250 | 2099 | if (active & M98090_SLD_MASK) |
685e4215 | 2100 | dev_dbg(codec->dev, "M98090_SLD_MASK\n"); |
685e4215 | 2101 | |
959b6250 | 2102 | if (active & M98090_ULK_MASK) |
685e4215 | 2103 | dev_err(codec->dev, "M98090_ULK_MASK\n"); |
685e4215 JW |
2104 | |
2105 | if (active & M98090_JDET_MASK) { | |
2106 | dev_dbg(codec->dev, "M98090_JDET_MASK\n"); | |
2107 | ||
2108 | pm_wakeup_event(codec->dev, 100); | |
2109 | ||
2df7c6aa MB |
2110 | queue_delayed_work(system_power_efficient_wq, |
2111 | &max98090->jack_work, | |
2112 | msecs_to_jiffies(100)); | |
685e4215 JW |
2113 | } |
2114 | ||
959b6250 | 2115 | if (active & M98090_DRCACT_MASK) |
685e4215 | 2116 | dev_dbg(codec->dev, "M98090_DRCACT_MASK\n"); |
685e4215 | 2117 | |
959b6250 | 2118 | if (active & M98090_DRCCLP_MASK) |
685e4215 | 2119 | dev_err(codec->dev, "M98090_DRCCLP_MASK\n"); |
685e4215 JW |
2120 | |
2121 | return IRQ_HANDLED; | |
2122 | } | |
2123 | ||
2124 | /** | |
2125 | * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ | |
2126 | * | |
2127 | * @codec: MAX98090 codec | |
2128 | * @jack: jack to report detection events on | |
2129 | * | |
2130 | * Enable microphone detection via IRQ on the MAX98090. If GPIOs are | |
2131 | * being used to bring out signals to the processor then only platform | |
2132 | * data configuration is needed for MAX98090 and processor GPIOs should | |
2133 | * be configured using snd_soc_jack_add_gpios() instead. | |
2134 | * | |
2135 | * If no jack is supplied detection will be disabled. | |
2136 | */ | |
2137 | int max98090_mic_detect(struct snd_soc_codec *codec, | |
2138 | struct snd_soc_jack *jack) | |
2139 | { | |
2140 | struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); | |
2141 | ||
2142 | dev_dbg(codec->dev, "max98090_mic_detect\n"); | |
2143 | ||
2144 | max98090->jack = jack; | |
2145 | if (jack) { | |
2146 | snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S, | |
2147 | M98090_IJDET_MASK, | |
2148 | 1 << M98090_IJDET_SHIFT); | |
2149 | } else { | |
2150 | snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S, | |
2151 | M98090_IJDET_MASK, | |
2152 | 0); | |
2153 | } | |
2154 | ||
2155 | /* Send an initial empty report */ | |
2156 | snd_soc_jack_report(max98090->jack, 0, | |
2157 | SND_JACK_HEADSET | SND_JACK_BTN_0); | |
2158 | ||
2df7c6aa MB |
2159 | queue_delayed_work(system_power_efficient_wq, |
2160 | &max98090->jack_work, | |
2161 | msecs_to_jiffies(100)); | |
685e4215 JW |
2162 | |
2163 | return 0; | |
2164 | } | |
2165 | EXPORT_SYMBOL_GPL(max98090_mic_detect); | |
2166 | ||
2167 | #define MAX98090_RATES SNDRV_PCM_RATE_8000_96000 | |
2168 | #define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) | |
2169 | ||
2170 | static struct snd_soc_dai_ops max98090_dai_ops = { | |
2171 | .set_sysclk = max98090_dai_set_sysclk, | |
2172 | .set_fmt = max98090_dai_set_fmt, | |
2173 | .set_tdm_slot = max98090_set_tdm_slot, | |
2174 | .hw_params = max98090_dai_hw_params, | |
2175 | .digital_mute = max98090_dai_digital_mute, | |
2176 | }; | |
2177 | ||
2178 | static struct snd_soc_dai_driver max98090_dai[] = { | |
2179 | { | |
2180 | .name = "HiFi", | |
2181 | .playback = { | |
2182 | .stream_name = "HiFi Playback", | |
2183 | .channels_min = 2, | |
2184 | .channels_max = 2, | |
2185 | .rates = MAX98090_RATES, | |
2186 | .formats = MAX98090_FORMATS, | |
2187 | }, | |
2188 | .capture = { | |
2189 | .stream_name = "HiFi Capture", | |
2190 | .channels_min = 1, | |
2191 | .channels_max = 2, | |
2192 | .rates = MAX98090_RATES, | |
2193 | .formats = MAX98090_FORMATS, | |
2194 | }, | |
2195 | .ops = &max98090_dai_ops, | |
2196 | } | |
2197 | }; | |
2198 | ||
2199 | static void max98090_handle_pdata(struct snd_soc_codec *codec) | |
2200 | { | |
2201 | struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); | |
2202 | struct max98090_pdata *pdata = max98090->pdata; | |
2203 | ||
2204 | if (!pdata) { | |
2205 | dev_err(codec->dev, "No platform data\n"); | |
2206 | return; | |
2207 | } | |
2208 | ||
2209 | } | |
2210 | ||
2211 | static int max98090_probe(struct snd_soc_codec *codec) | |
2212 | { | |
2213 | struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); | |
2214 | struct max98090_cdata *cdata; | |
2215 | int ret = 0; | |
2216 | ||
2217 | dev_dbg(codec->dev, "max98090_probe\n"); | |
2218 | ||
2219 | max98090->codec = codec; | |
2220 | ||
685e4215 JW |
2221 | /* Reset the codec, the DSP core, and disable all interrupts */ |
2222 | max98090_reset(max98090); | |
2223 | ||
2224 | /* Initialize private data */ | |
2225 | ||
2226 | max98090->sysclk = (unsigned)-1; | |
2227 | ||
2228 | cdata = &max98090->dai[0]; | |
2229 | cdata->rate = (unsigned)-1; | |
2230 | cdata->fmt = (unsigned)-1; | |
2231 | ||
2232 | max98090->lin_state = 0; | |
2233 | max98090->pa1en = 0; | |
2234 | max98090->pa2en = 0; | |
2235 | max98090->extmic_mux = 0; | |
2236 | ||
2237 | ret = snd_soc_read(codec, M98090_REG_REVISION_ID); | |
2238 | if (ret < 0) { | |
2239 | dev_err(codec->dev, "Failed to read device revision: %d\n", | |
2240 | ret); | |
2241 | goto err_access; | |
2242 | } | |
2243 | ||
2244 | if ((ret >= M98090_REVA) && (ret <= M98090_REVA + 0x0f)) { | |
2245 | max98090->devtype = MAX98090; | |
2246 | dev_info(codec->dev, "MAX98090 REVID=0x%02x\n", ret); | |
2247 | } else if ((ret >= M98091_REVA) && (ret <= M98091_REVA + 0x0f)) { | |
2248 | max98090->devtype = MAX98091; | |
2249 | dev_info(codec->dev, "MAX98091 REVID=0x%02x\n", ret); | |
2250 | } else { | |
2251 | max98090->devtype = MAX98090; | |
2252 | dev_err(codec->dev, "Unrecognized revision 0x%02x\n", ret); | |
2253 | } | |
2254 | ||
2255 | max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; | |
2256 | ||
2257 | INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work); | |
2258 | ||
2259 | /* Enable jack detection */ | |
2260 | snd_soc_write(codec, M98090_REG_JACK_DETECT, | |
2261 | M98090_JDETEN_MASK | M98090_JDEB_25MS); | |
2262 | ||
2263 | /* Register for interrupts */ | |
2264 | dev_dbg(codec->dev, "irq = %d\n", max98090->irq); | |
2265 | ||
2266 | ret = request_threaded_irq(max98090->irq, NULL, | |
3d15aacb | 2267 | max98090_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT, |
685e4215 JW |
2268 | "max98090_interrupt", codec); |
2269 | if (ret < 0) { | |
2270 | dev_err(codec->dev, "request_irq failed: %d\n", | |
2271 | ret); | |
2272 | } | |
2273 | ||
2274 | /* | |
2275 | * Clear any old interrupts. | |
2276 | * An old interrupt ocurring prior to installing the ISR | |
2277 | * can keep a new interrupt from generating a trigger. | |
2278 | */ | |
2279 | snd_soc_read(codec, M98090_REG_DEVICE_STATUS); | |
2280 | ||
2281 | /* High Performance is default */ | |
2282 | snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL, | |
2283 | M98090_DACHP_MASK, | |
2284 | 1 << M98090_DACHP_SHIFT); | |
2285 | snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL, | |
2286 | M98090_PERFMODE_MASK, | |
2287 | 0 << M98090_PERFMODE_SHIFT); | |
2288 | snd_soc_update_bits(codec, M98090_REG_ADC_CONTROL, | |
2289 | M98090_ADCHP_MASK, | |
2290 | 1 << M98090_ADCHP_SHIFT); | |
2291 | ||
2292 | /* Turn on VCM bandgap reference */ | |
2293 | snd_soc_write(codec, M98090_REG_BIAS_CONTROL, | |
2294 | M98090_VCM_MODE_MASK); | |
2295 | ||
2296 | max98090_handle_pdata(codec); | |
2297 | ||
2298 | max98090_add_widgets(codec); | |
2299 | ||
2300 | err_access: | |
2301 | return ret; | |
2302 | } | |
2303 | ||
2304 | static int max98090_remove(struct snd_soc_codec *codec) | |
2305 | { | |
2306 | struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); | |
2307 | ||
2308 | cancel_delayed_work_sync(&max98090->jack_work); | |
2309 | ||
2310 | return 0; | |
2311 | } | |
2312 | ||
2313 | static struct snd_soc_codec_driver soc_codec_dev_max98090 = { | |
2314 | .probe = max98090_probe, | |
2315 | .remove = max98090_remove, | |
2316 | .set_bias_level = max98090_set_bias_level, | |
2317 | }; | |
2318 | ||
2319 | static const struct regmap_config max98090_regmap = { | |
2320 | .reg_bits = 8, | |
2321 | .val_bits = 8, | |
2322 | ||
2323 | .max_register = MAX98090_MAX_REGISTER, | |
2324 | .reg_defaults = max98090_reg, | |
2325 | .num_reg_defaults = ARRAY_SIZE(max98090_reg), | |
2326 | .volatile_reg = max98090_volatile_register, | |
2327 | .readable_reg = max98090_readable_register, | |
2328 | .cache_type = REGCACHE_RBTREE, | |
2329 | }; | |
2330 | ||
2331 | static int max98090_i2c_probe(struct i2c_client *i2c, | |
2332 | const struct i2c_device_id *id) | |
2333 | { | |
2334 | struct max98090_priv *max98090; | |
2335 | int ret; | |
2336 | ||
2337 | pr_debug("max98090_i2c_probe\n"); | |
2338 | ||
2339 | max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv), | |
2340 | GFP_KERNEL); | |
2341 | if (max98090 == NULL) | |
2342 | return -ENOMEM; | |
2343 | ||
2344 | max98090->devtype = id->driver_data; | |
2345 | i2c_set_clientdata(i2c, max98090); | |
685e4215 JW |
2346 | max98090->pdata = i2c->dev.platform_data; |
2347 | max98090->irq = i2c->irq; | |
2348 | ||
a3a6cc84 | 2349 | max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap); |
685e4215 JW |
2350 | if (IS_ERR(max98090->regmap)) { |
2351 | ret = PTR_ERR(max98090->regmap); | |
2352 | dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret); | |
2353 | goto err_enable; | |
2354 | } | |
2355 | ||
2356 | ret = snd_soc_register_codec(&i2c->dev, | |
2357 | &soc_codec_dev_max98090, max98090_dai, | |
2358 | ARRAY_SIZE(max98090_dai)); | |
685e4215 JW |
2359 | err_enable: |
2360 | return ret; | |
2361 | } | |
2362 | ||
2363 | static int max98090_i2c_remove(struct i2c_client *client) | |
2364 | { | |
685e4215 | 2365 | snd_soc_unregister_codec(&client->dev); |
685e4215 JW |
2366 | return 0; |
2367 | } | |
2368 | ||
3722dc8e | 2369 | #ifdef CONFIG_PM_RUNTIME |
685e4215 JW |
2370 | static int max98090_runtime_resume(struct device *dev) |
2371 | { | |
2372 | struct max98090_priv *max98090 = dev_get_drvdata(dev); | |
2373 | ||
2374 | regcache_cache_only(max98090->regmap, false); | |
2375 | ||
2376 | regcache_sync(max98090->regmap); | |
2377 | ||
2378 | return 0; | |
2379 | } | |
2380 | ||
2381 | static int max98090_runtime_suspend(struct device *dev) | |
2382 | { | |
2383 | struct max98090_priv *max98090 = dev_get_drvdata(dev); | |
2384 | ||
2385 | regcache_cache_only(max98090->regmap, true); | |
2386 | ||
2387 | return 0; | |
2388 | } | |
3722dc8e | 2389 | #endif |
685e4215 | 2390 | |
3e12af7e | 2391 | static const struct dev_pm_ops max98090_pm = { |
685e4215 JW |
2392 | SET_RUNTIME_PM_OPS(max98090_runtime_suspend, |
2393 | max98090_runtime_resume, NULL) | |
2394 | }; | |
2395 | ||
2396 | static const struct i2c_device_id max98090_i2c_id[] = { | |
2397 | { "max98090", MAX98090 }, | |
2398 | { } | |
2399 | }; | |
2400 | MODULE_DEVICE_TABLE(i2c, max98090_i2c_id); | |
2401 | ||
2951f93f SW |
2402 | static const struct of_device_id max98090_of_match[] = { |
2403 | { .compatible = "maxim,max98090", }, | |
2404 | { } | |
2405 | }; | |
2406 | MODULE_DEVICE_TABLE(of, max98090_of_match); | |
2407 | ||
685e4215 JW |
2408 | static struct i2c_driver max98090_i2c_driver = { |
2409 | .driver = { | |
2410 | .name = "max98090", | |
2411 | .owner = THIS_MODULE, | |
2412 | .pm = &max98090_pm, | |
2951f93f | 2413 | .of_match_table = of_match_ptr(max98090_of_match), |
685e4215 JW |
2414 | }, |
2415 | .probe = max98090_i2c_probe, | |
2416 | .remove = max98090_i2c_remove, | |
2417 | .id_table = max98090_i2c_id, | |
2418 | }; | |
2419 | ||
2420 | module_i2c_driver(max98090_i2c_driver); | |
2421 | ||
2422 | MODULE_DESCRIPTION("ALSA SoC MAX98090 driver"); | |
2423 | MODULE_AUTHOR("Peter Hsiang, Jesse Marroqin, Jerry Wong"); | |
2424 | MODULE_LICENSE("GPL"); |