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ASoC: max98090: Fix reset at resume time
[deliverable/linux.git] / sound / soc / codecs / max98090.c
CommitLineData
685e4215
JW		 1/*
2 * max98090.c -- MAX98090 ALSA SoC Audio driver
3 *
4 * Copyright 2011-2012 Maxim Integrated Products
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/delay.h>
12#include <linux/i2c.h>
13#include <linux/module.h>
14#include <linux/pm.h>
15#include <linux/pm_runtime.h>
16#include <linux/regmap.h>
17#include <linux/slab.h>
18#include <sound/jack.h>
19#include <sound/pcm.h>
20#include <sound/pcm_params.h>
21#include <sound/soc.h>
22#include <sound/tlv.h>
23#include <sound/max98090.h>
24#include "max98090.h"
25
685e4215
JW		 26#define DEBUG
27#define EXTMIC_METHOD
28#define EXTMIC_METHOD_TEST
29
30/* Allows for sparsely populated register maps */
31static struct reg_default max98090_reg[] = {
32 { 0x00, 0x00 }, /* 00 Software Reset */
33 { 0x03, 0x04 }, /* 03 Interrupt Masks */
34 { 0x04, 0x00 }, /* 04 System Clock Quick */
35 { 0x05, 0x00 }, /* 05 Sample Rate Quick */
36 { 0x06, 0x00 }, /* 06 DAI Interface Quick */
37 { 0x07, 0x00 }, /* 07 DAC Path Quick */
38 { 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */
39 { 0x09, 0x00 }, /* 09 Line to ADC Quick */
40 { 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */
41 { 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */
42 { 0x0C, 0x00 }, /* 0C Reserved */
43 { 0x0D, 0x00 }, /* 0D Input Config */
44 { 0x0E, 0x1B }, /* 0E Line Input Level */
45 { 0x0F, 0x00 }, /* 0F Line Config */
46
47 { 0x10, 0x14 }, /* 10 Mic1 Input Level */
48 { 0x11, 0x14 }, /* 11 Mic2 Input Level */
49 { 0x12, 0x00 }, /* 12 Mic Bias Voltage */
50 { 0x13, 0x00 }, /* 13 Digital Mic Config */
51 { 0x14, 0x00 }, /* 14 Digital Mic Mode */
52 { 0x15, 0x00 }, /* 15 Left ADC Mixer */
53 { 0x16, 0x00 }, /* 16 Right ADC Mixer */
54 { 0x17, 0x03 }, /* 17 Left ADC Level */
55 { 0x18, 0x03 }, /* 18 Right ADC Level */
56 { 0x19, 0x00 }, /* 19 ADC Biquad Level */
57 { 0x1A, 0x00 }, /* 1A ADC Sidetone */
58 { 0x1B, 0x00 }, /* 1B System Clock */
59 { 0x1C, 0x00 }, /* 1C Clock Mode */
60 { 0x1D, 0x00 }, /* 1D Any Clock 1 */
61 { 0x1E, 0x00 }, /* 1E Any Clock 2 */
62 { 0x1F, 0x00 }, /* 1F Any Clock 3 */
63
64 { 0x20, 0x00 }, /* 20 Any Clock 4 */
65 { 0x21, 0x00 }, /* 21 Master Mode */
66 { 0x22, 0x00 }, /* 22 Interface Format */
67 { 0x23, 0x00 }, /* 23 TDM Format 1*/
68 { 0x24, 0x00 }, /* 24 TDM Format 2*/
69 { 0x25, 0x00 }, /* 25 I/O Configuration */
70 { 0x26, 0x80 }, /* 26 Filter Config */
71 { 0x27, 0x00 }, /* 27 DAI Playback Level */
72 { 0x28, 0x00 }, /* 28 EQ Playback Level */
73 { 0x29, 0x00 }, /* 29 Left HP Mixer */
74 { 0x2A, 0x00 }, /* 2A Right HP Mixer */
75 { 0x2B, 0x00 }, /* 2B HP Control */
76 { 0x2C, 0x1A }, /* 2C Left HP Volume */
77 { 0x2D, 0x1A }, /* 2D Right HP Volume */
78 { 0x2E, 0x00 }, /* 2E Left Spk Mixer */
79 { 0x2F, 0x00 }, /* 2F Right Spk Mixer */
80
81 { 0x30, 0x00 }, /* 30 Spk Control */
82 { 0x31, 0x2C }, /* 31 Left Spk Volume */
83 { 0x32, 0x2C }, /* 32 Right Spk Volume */
84 { 0x33, 0x00 }, /* 33 ALC Timing */
85 { 0x34, 0x00 }, /* 34 ALC Compressor */
86 { 0x35, 0x00 }, /* 35 ALC Expander */
87 { 0x36, 0x00 }, /* 36 ALC Gain */
88 { 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */
89 { 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */
90 { 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */
91 { 0x3A, 0x00 }, /* 3A Line OutR Mixer */
92 { 0x3B, 0x00 }, /* 3B Line OutR Control */
93 { 0x3C, 0x15 }, /* 3C Line OutR Volume */
94 { 0x3D, 0x00 }, /* 3D Jack Detect */
95 { 0x3E, 0x00 }, /* 3E Input Enable */
96 { 0x3F, 0x00 }, /* 3F Output Enable */
97
98 { 0x40, 0x00 }, /* 40 Level Control */
99 { 0x41, 0x00 }, /* 41 DSP Filter Enable */
100 { 0x42, 0x00 }, /* 42 Bias Control */
101 { 0x43, 0x00 }, /* 43 DAC Control */
102 { 0x44, 0x06 }, /* 44 ADC Control */
103 { 0x45, 0x00 }, /* 45 Device Shutdown */
104 { 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */
105 { 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */
106 { 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */
107 { 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */
108 { 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */
109 { 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */
110 { 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */
111 { 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */
112 { 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */
113 { 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */
114
115 { 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */
116 { 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */
117 { 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */
118 { 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */
119 { 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */
120 { 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */
121 { 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */
122 { 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */
123 { 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */
124 { 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */
125 { 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */
126 { 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */
127 { 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */
128 { 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */
129 { 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */
130 { 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */
131
132 { 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */
133 { 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */
134 { 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */
135 { 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */
136 { 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */
137 { 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */
138 { 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */
139 { 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */
140 { 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */
141 { 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */
142 { 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */
143 { 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */
144 { 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */
145 { 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */
146 { 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */
147 { 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */
148
149 { 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */
150 { 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */
151 { 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */
152 { 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */
153 { 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */
154 { 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */
155 { 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */
156 { 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */
157 { 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */
158 { 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */
159 { 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */
160 { 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */
161 { 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */
162 { 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */
163 { 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */
164 { 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */
165
166 { 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */
167 { 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */
168 { 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */
169 { 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */
170 { 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */
171 { 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */
172 { 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */
173 { 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */
174 { 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */
175 { 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */
176 { 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */
177 { 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */
178 { 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */
179 { 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */
180 { 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */
181 { 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */
182
183 { 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */
184 { 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */
185 { 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */
186 { 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */
187 { 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */
188 { 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */
189 { 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */
190 { 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */
191 { 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */
192 { 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */
193 { 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */
194 { 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */
195 { 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */
196 { 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */
197 { 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */
198 { 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */
199
200 { 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */
201 { 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */
202 { 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */
203 { 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */
204 { 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */
205 { 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */
206 { 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */
207 { 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */
208 { 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */
209 { 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */
210 { 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */
211 { 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */
212 { 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */
213 { 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */
214 { 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */
215 { 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */
216
217 { 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */
218 { 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */
219 { 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */
220 { 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */
221 { 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */
222 { 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */
223 { 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */
224 { 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */
225 { 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */
226 { 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */
227 { 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */
228 { 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */
229 { 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */
230 { 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */
231 { 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */
232 { 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */
233
234 { 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */
235 { 0xC1, 0x00 }, /* C1 Record TDM Slot */
236 { 0xC2, 0x00 }, /* C2 Sample Rate */
237 { 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */
238 { 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */
239 { 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */
240 { 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */
241 { 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */
242 { 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */
243 { 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */
244 { 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */
245 { 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */
246 { 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */
247 { 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */
248 { 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */
249 { 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */
250
251 { 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */
252 { 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */
253};
254
255static bool max98090_volatile_register(struct device *dev, unsigned int reg)
256{
257 switch (reg) {
25b4ab43 258 case M98090_REG_SOFTWARE_RESET:
685e4215
JW		 259 case M98090_REG_DEVICE_STATUS:
260 case M98090_REG_JACK_STATUS:
261 case M98090_REG_REVISION_ID:
262 return true;
263 default:
264 return false;
265 }
266}
267
268static bool max98090_readable_register(struct device *dev, unsigned int reg)
269{
270 switch (reg) {
271 case M98090_REG_DEVICE_STATUS:
272 case M98090_REG_JACK_STATUS:
273 case M98090_REG_INTERRUPT_S:
274 case M98090_REG_RESERVED:
275 case M98090_REG_LINE_INPUT_CONFIG:
276 case M98090_REG_LINE_INPUT_LEVEL:
277 case M98090_REG_INPUT_MODE:
278 case M98090_REG_MIC1_INPUT_LEVEL:
279 case M98090_REG_MIC2_INPUT_LEVEL:
280 case M98090_REG_MIC_BIAS_VOLTAGE:
281 case M98090_REG_DIGITAL_MIC_ENABLE:
282 case M98090_REG_DIGITAL_MIC_CONFIG:
283 case M98090_REG_LEFT_ADC_MIXER:
284 case M98090_REG_RIGHT_ADC_MIXER:
285 case M98090_REG_LEFT_ADC_LEVEL:
286 case M98090_REG_RIGHT_ADC_LEVEL:
287 case M98090_REG_ADC_BIQUAD_LEVEL:
288 case M98090_REG_ADC_SIDETONE:
289 case M98090_REG_SYSTEM_CLOCK:
290 case M98090_REG_CLOCK_MODE:
291 case M98090_REG_CLOCK_RATIO_NI_MSB:
292 case M98090_REG_CLOCK_RATIO_NI_LSB:
293 case M98090_REG_CLOCK_RATIO_MI_MSB:
294 case M98090_REG_CLOCK_RATIO_MI_LSB:
295 case M98090_REG_MASTER_MODE:
296 case M98090_REG_INTERFACE_FORMAT:
297 case M98090_REG_TDM_CONTROL:
298 case M98090_REG_TDM_FORMAT:
299 case M98090_REG_IO_CONFIGURATION:
300 case M98090_REG_FILTER_CONFIG:
301 case M98090_REG_DAI_PLAYBACK_LEVEL:
302 case M98090_REG_DAI_PLAYBACK_LEVEL_EQ:
303 case M98090_REG_LEFT_HP_MIXER:
304 case M98090_REG_RIGHT_HP_MIXER:
305 case M98090_REG_HP_CONTROL:
306 case M98090_REG_LEFT_HP_VOLUME:
307 case M98090_REG_RIGHT_HP_VOLUME:
308 case M98090_REG_LEFT_SPK_MIXER:
309 case M98090_REG_RIGHT_SPK_MIXER:
310 case M98090_REG_SPK_CONTROL:
311 case M98090_REG_LEFT_SPK_VOLUME:
312 case M98090_REG_RIGHT_SPK_VOLUME:
313 case M98090_REG_DRC_TIMING:
314 case M98090_REG_DRC_COMPRESSOR:
315 case M98090_REG_DRC_EXPANDER:
316 case M98090_REG_DRC_GAIN:
317 case M98090_REG_RCV_LOUTL_MIXER:
318 case M98090_REG_RCV_LOUTL_CONTROL:
319 case M98090_REG_RCV_LOUTL_VOLUME:
320 case M98090_REG_LOUTR_MIXER:
321 case M98090_REG_LOUTR_CONTROL:
322 case M98090_REG_LOUTR_VOLUME:
323 case M98090_REG_JACK_DETECT:
324 case M98090_REG_INPUT_ENABLE:
325 case M98090_REG_OUTPUT_ENABLE:
326 case M98090_REG_LEVEL_CONTROL:
327 case M98090_REG_DSP_FILTER_ENABLE:
328 case M98090_REG_BIAS_CONTROL:
329 case M98090_REG_DAC_CONTROL:
330 case M98090_REG_ADC_CONTROL:
331 case M98090_REG_DEVICE_SHUTDOWN:
332 case M98090_REG_EQUALIZER_BASE ... M98090_REG_EQUALIZER_BASE + 0x68:
333 case M98090_REG_RECORD_BIQUAD_BASE ... M98090_REG_RECORD_BIQUAD_BASE + 0x0E:
334 case M98090_REG_DMIC3_VOLUME:
335 case M98090_REG_DMIC4_VOLUME:
336 case M98090_REG_DMIC34_BQ_PREATTEN:
337 case M98090_REG_RECORD_TDM_SLOT:
338 case M98090_REG_SAMPLE_RATE:
339 case M98090_REG_DMIC34_BIQUAD_BASE ... M98090_REG_DMIC34_BIQUAD_BASE + 0x0E:
e126a646 340 case M98090_REG_REVISION_ID:
685e4215
JW		 341 return true;
342 default:
343 return false;
344 }
345}
346
347static int max98090_reset(struct max98090_priv *max98090)
348{
349 int ret;
350
351 /* Reset the codec by writing to this write-only reset register */
352 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET,
353 M98090_SWRESET_MASK);
354 if (ret < 0) {
355 dev_err(max98090->codec->dev,
356 "Failed to reset codec: %d\n", ret);
357 return ret;
358 }
359
360 msleep(20);
361 return ret;
362}
363
364static const unsigned int max98090_micboost_tlv[] = {
365 TLV_DB_RANGE_HEAD(2),
366 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
367 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0),
368};
369
370static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv, 0, 100, 0);
371
372static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv,
373 -600, 600, 0);
374
375static const unsigned int max98090_line_tlv[] = {
376 TLV_DB_RANGE_HEAD(2),
377 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0),
378 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0),
379};
380
381static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv, 0, 600, 0);
382static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0);
383
384static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv, 0, 600, 0);
385static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0);
386
387static const DECLARE_TLV_DB_SCALE(max98090_sidetone_tlv, -6050, 200, 0);
388
389static const DECLARE_TLV_DB_SCALE(max98090_alc_tlv, -1500, 100, 0);
390static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0);
391static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0);
392static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0);
729af1ce 393static const DECLARE_TLV_DB_SCALE(max98090_sdg_tlv, 50, 200, 0);
685e4215
JW		 394
395static const unsigned int max98090_mixout_tlv[] = {
396 TLV_DB_RANGE_HEAD(2),
397 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0),
398 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0),
399};
400
401static const unsigned int max98090_hp_tlv[] = {
402 TLV_DB_RANGE_HEAD(5),
403 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
404 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
405 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
406 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
407 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0),
408};
409
410static const unsigned int max98090_spk_tlv[] = {
411 TLV_DB_RANGE_HEAD(5),
412 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0),
413 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0),
414 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0),
415 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0),
416 30, 39, TLV_DB_SCALE_ITEM(950, 50, 0),
417};
418
419static const unsigned int max98090_rcv_lout_tlv[] = {
420 TLV_DB_RANGE_HEAD(5),
421 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
422 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
423 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
424 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
425 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0),
426};
427
428static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol,
429 struct snd_ctl_elem_value *ucontrol)
430{
431 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
432 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
433 struct soc_mixer_control *mc =
434 (struct soc_mixer_control *)kcontrol->private_value;
435 unsigned int mask = (1 << fls(mc->max)) - 1;
436 unsigned int val = snd_soc_read(codec, mc->reg);
437 unsigned int *select;
438
439 switch (mc->reg) {
440 case M98090_REG_MIC1_INPUT_LEVEL:
441 select = &(max98090->pa1en);
442 break;
443 case M98090_REG_MIC2_INPUT_LEVEL:
444 select = &(max98090->pa2en);
445 break;
446 case M98090_REG_ADC_SIDETONE:
447 select = &(max98090->sidetone);
448 break;
449 default:
450 return -EINVAL;
451 }
452
453 val = (val >> mc->shift) & mask;
454
455 if (val >= 1) {
456 /* If on, return the volume */
457 val = val - 1;
458 *select = val;
459 } else {
460 /* If off, return last stored value */
461 val = *select;
462 }
463
464 ucontrol->value.integer.value[0] = val;
465 return 0;
466}
467
468static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol,
469 struct snd_ctl_elem_value *ucontrol)
470{
471 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
472 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
473 struct soc_mixer_control *mc =
474 (struct soc_mixer_control *)kcontrol->private_value;
475 unsigned int mask = (1 << fls(mc->max)) - 1;
476 unsigned int sel = ucontrol->value.integer.value[0];
477 unsigned int val = snd_soc_read(codec, mc->reg);
478 unsigned int *select;
479
480 switch (mc->reg) {
481 case M98090_REG_MIC1_INPUT_LEVEL:
482 select = &(max98090->pa1en);
483 break;
484 case M98090_REG_MIC2_INPUT_LEVEL:
485 select = &(max98090->pa2en);
486 break;
487 case M98090_REG_ADC_SIDETONE:
488 select = &(max98090->sidetone);
489 break;
490 default:
491 return -EINVAL;
492 }
493
494 val = (val >> mc->shift) & mask;
495
496 *select = sel;
497
498 /* Setting a volume is only valid if it is already On */
499 if (val >= 1) {
500 sel = sel + 1;
501 } else {
502 /* Write what was already there */
503 sel = val;
504 }
505
506 snd_soc_update_bits(codec, mc->reg,
507 mask << mc->shift,
508 sel << mc->shift);
509
510 return 0;
511}
512
4ca74feb 513static const char *max98090_perf_pwr_text[] =
685e4215 514 { "High Performance", "Low Power" };
4ca74feb 515static const char *max98090_pwr_perf_text[] =
685e4215
JW		 516 { "Low Power", "High Performance" };
517
2907cbcc
TI		 518static SOC_ENUM_SINGLE_DECL(max98090_vcmbandgap_enum,
519 M98090_REG_BIAS_CONTROL,
520 M98090_VCM_MODE_SHIFT,
521 max98090_pwr_perf_text);
685e4215 522
4ca74feb 523static const char *max98090_osr128_text[] = { "64*fs", "128*fs" };
685e4215 524
2907cbcc
TI		 525static SOC_ENUM_SINGLE_DECL(max98090_osr128_enum,
526 M98090_REG_ADC_CONTROL,
527 M98090_OSR128_SHIFT,
528 max98090_osr128_text);
685e4215
JW		 529
530static const char *max98090_mode_text[] = { "Voice", "Music" };
531
2907cbcc
TI		 532static SOC_ENUM_SINGLE_DECL(max98090_mode_enum,
533 M98090_REG_FILTER_CONFIG,
534 M98090_MODE_SHIFT,
535 max98090_mode_text);
685e4215 536
2907cbcc
TI		 537static SOC_ENUM_SINGLE_DECL(max98090_filter_dmic34mode_enum,
538 M98090_REG_FILTER_CONFIG,
539 M98090_FLT_DMIC34MODE_SHIFT,
540 max98090_mode_text);
685e4215 541
4ca74feb 542static const char *max98090_drcatk_text[] =
685e4215
JW		 543 { "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" };
544
2907cbcc
TI		 545static SOC_ENUM_SINGLE_DECL(max98090_drcatk_enum,
546 M98090_REG_DRC_TIMING,
547 M98090_DRCATK_SHIFT,
548 max98090_drcatk_text);
685e4215 549
4ca74feb 550static const char *max98090_drcrls_text[] =
685e4215
JW		 551 { "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" };
552
2907cbcc
TI		 553static SOC_ENUM_SINGLE_DECL(max98090_drcrls_enum,
554 M98090_REG_DRC_TIMING,
555 M98090_DRCRLS_SHIFT,
556 max98090_drcrls_text);
685e4215 557
4ca74feb 558static const char *max98090_alccmp_text[] =
685e4215
JW		 559 { "1:1", "1:1.5", "1:2", "1:4", "1:INF" };
560
2907cbcc
TI		 561static SOC_ENUM_SINGLE_DECL(max98090_alccmp_enum,
562 M98090_REG_DRC_COMPRESSOR,
563 M98090_DRCCMP_SHIFT,
564 max98090_alccmp_text);
685e4215 565
4ca74feb 566static const char *max98090_drcexp_text[] = { "1:1", "2:1", "3:1" };
685e4215 567
2907cbcc
TI		 568static SOC_ENUM_SINGLE_DECL(max98090_drcexp_enum,
569 M98090_REG_DRC_EXPANDER,
570 M98090_DRCEXP_SHIFT,
571 max98090_drcexp_text);
685e4215 572
2907cbcc
TI		 573static SOC_ENUM_SINGLE_DECL(max98090_dac_perfmode_enum,
574 M98090_REG_DAC_CONTROL,
575 M98090_PERFMODE_SHIFT,
576 max98090_perf_pwr_text);
685e4215 577
2907cbcc
TI		 578static SOC_ENUM_SINGLE_DECL(max98090_dachp_enum,
579 M98090_REG_DAC_CONTROL,
580 M98090_DACHP_SHIFT,
581 max98090_pwr_perf_text);
685e4215 582
2907cbcc
TI		 583static SOC_ENUM_SINGLE_DECL(max98090_adchp_enum,
584 M98090_REG_ADC_CONTROL,
585 M98090_ADCHP_SHIFT,
586 max98090_pwr_perf_text);
685e4215
JW		 587
588static const struct snd_kcontrol_new max98090_snd_controls[] = {
589 SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum),
590
591 SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG,
592 M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0),
593
594 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
595 M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT,
596 M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv,
597 max98090_put_enab_tlv, max98090_micboost_tlv),
598
599 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
600 M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT,
601 M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv,
602 max98090_put_enab_tlv, max98090_micboost_tlv),
603
604 SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL,
605 M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1,
606 max98090_mic_tlv),
607
608 SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL,
609 M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1,
610 max98090_mic_tlv),
611
612 SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume",
613 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG135_SHIFT, 0,
614 M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv),
615
616 SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume",
617 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG246_SHIFT, 0,
618 M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv),
619
620 SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL,
621 M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1,
622 max98090_line_tlv),
623
624 SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL,
625 M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1,
626 max98090_line_tlv),
627
628 SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
629 M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0),
630 SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
631 M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0),
632
633 SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL,
634 M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0,
635 max98090_avg_tlv),
636 SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL,
637 M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0,
638 max98090_avg_tlv),
639
640 SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL,
641 M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1,
642 max98090_av_tlv),
643 SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL,
644 M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1,
645 max98090_av_tlv),
646
647 SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum),
648 SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL,
649 M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0),
650 SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum),
651
652 SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION,
653 M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0),
654 SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION,
655 M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0),
656 SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION,
657 M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0),
658 SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION,
659 M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1),
660 SOC_ENUM("Filter Mode", max98090_mode_enum),
661 SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG,
662 M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0),
663 SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG,
664 M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0),
665 SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL,
666 M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv),
667 SOC_SINGLE_EXT_TLV("Digital Sidetone Volume",
668 M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT,
669 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv,
729af1ce 670 max98090_put_enab_tlv, max98090_sdg_tlv),
685e4215
JW		 671 SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
672 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0,
673 max98090_dvg_tlv),
674 SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
675 M98090_DV_SHIFT, M98090_DV_NUM - 1, 1,
676 max98090_dv_tlv),
677 SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105),
678 SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
679 M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0),
680 SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
681 M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0),
682 SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
683 M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0),
684 SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
685 M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1,
686 1),
687 SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
688 M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1,
689 max98090_dv_tlv),
690
691 SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING,
692 M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0),
693 SOC_ENUM("ALC Attack Time", max98090_drcatk_enum),
694 SOC_ENUM("ALC Release Time", max98090_drcrls_enum),
695 SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN,
696 M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0,
697 max98090_alcmakeup_tlv),
698 SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum),
699 SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum),
700 SOC_SINGLE_TLV("ALC Compression Threshold Volume",
701 M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT,
702 M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv),
703 SOC_SINGLE_TLV("ALC Expansion Threshold Volume",
704 M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT,
705 M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv),
706
707 SOC_ENUM("DAC HP Playback Performance Mode",
708 max98090_dac_perfmode_enum),
709 SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum),
710
711 SOC_SINGLE_TLV("Headphone Left Mixer Volume",
712 M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT,
713 M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv),
714 SOC_SINGLE_TLV("Headphone Right Mixer Volume",
715 M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT,
716 M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv),
717
718 SOC_SINGLE_TLV("Speaker Left Mixer Volume",
719 M98090_REG_SPK_CONTROL, M98090_MIXSPLG_SHIFT,
720 M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv),
721 SOC_SINGLE_TLV("Speaker Right Mixer Volume",
722 M98090_REG_SPK_CONTROL, M98090_MIXSPRG_SHIFT,
723 M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv),
724
725 SOC_SINGLE_TLV("Receiver Left Mixer Volume",
726 M98090_REG_RCV_LOUTL_CONTROL, M98090_MIXRCVLG_SHIFT,
727 M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv),
728 SOC_SINGLE_TLV("Receiver Right Mixer Volume",
729 M98090_REG_LOUTR_CONTROL, M98090_MIXRCVRG_SHIFT,
730 M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv),
731
732 SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME,
733 M98090_REG_RIGHT_HP_VOLUME, M98090_HPVOLL_SHIFT,
734 M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv),
735
736 SOC_DOUBLE_R_RANGE_TLV("Speaker Volume",
737 M98090_REG_LEFT_SPK_VOLUME, M98090_REG_RIGHT_SPK_VOLUME,
738 M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24,
739 0, max98090_spk_tlv),
740
741 SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME,
742 M98090_REG_LOUTR_VOLUME, M98090_RCVLVOL_SHIFT,
743 M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv),
744
745 SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME,
746 M98090_HPLM_SHIFT, 1, 1),
747 SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME,
748 M98090_HPRM_SHIFT, 1, 1),
749
750 SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME,
751 M98090_SPLM_SHIFT, 1, 1),
752 SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME,
753 M98090_SPRM_SHIFT, 1, 1),
754
755 SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME,
756 M98090_RCVLM_SHIFT, 1, 1),
757 SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME,
758 M98090_RCVRM_SHIFT, 1, 1),
759
760 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL,
761 M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1),
762 SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL,
763 M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1),
764 SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL,
765 M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1),
766
767 SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE, 15),
768 SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
769 M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0),
770};
771
772static const struct snd_kcontrol_new max98091_snd_controls[] = {
773
774 SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE,
775 M98090_DMIC34_ZEROPAD_SHIFT,
776 M98090_DMIC34_ZEROPAD_NUM - 1, 0),
777
778 SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum),
779 SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG,
780 M98090_FLT_DMIC34HPF_SHIFT,
781 M98090_FLT_DMIC34HPF_NUM - 1, 0),
782
783 SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME,
784 M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0,
785 max98090_avg_tlv),
786 SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME,
787 M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0,
788 max98090_avg_tlv),
789
790 SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME,
791 M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1,
792 max98090_av_tlv),
793 SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME,
794 M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1,
795 max98090_av_tlv),
796
797 SND_SOC_BYTES("DMIC34 Biquad Coefficients",
798 M98090_REG_DMIC34_BIQUAD_BASE, 15),
799 SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
800 M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0),
801
802 SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume",
803 M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT,
804 M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv),
805};
806
807static int max98090_micinput_event(struct snd_soc_dapm_widget *w,
808 struct snd_kcontrol *kcontrol, int event)
809{
810 struct snd_soc_codec *codec = w->codec;
811 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
812
813 unsigned int val = snd_soc_read(codec, w->reg);
814
815 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
816 val = (val & M98090_MIC_PA1EN_MASK) >> M98090_MIC_PA1EN_SHIFT;
817 else
818 val = (val & M98090_MIC_PA2EN_MASK) >> M98090_MIC_PA2EN_SHIFT;
819
820
821 if (val >= 1) {
822 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) {
823 max98090->pa1en = val - 1; /* Update for volatile */
824 } else {
825 max98090->pa2en = val - 1; /* Update for volatile */
826 }
827 }
828
829 switch (event) {
830 case SND_SOC_DAPM_POST_PMU:
831 /* If turning on, set to most recently selected volume */
832 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
833 val = max98090->pa1en + 1;
834 else
835 val = max98090->pa2en + 1;
836 break;
837 case SND_SOC_DAPM_POST_PMD:
838 /* If turning off, turn off */
839 val = 0;
840 break;
841 default:
842 return -EINVAL;
843 }
844
845 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
846 snd_soc_update_bits(codec, w->reg, M98090_MIC_PA1EN_MASK,
847 val << M98090_MIC_PA1EN_SHIFT);
848 else
849 snd_soc_update_bits(codec, w->reg, M98090_MIC_PA2EN_MASK,
850 val << M98090_MIC_PA2EN_SHIFT);
851
852 return 0;
853}
854
855static const char *mic1_mux_text[] = { "IN12", "IN56" };
856
2907cbcc
TI		 857static SOC_ENUM_SINGLE_DECL(mic1_mux_enum,
858 M98090_REG_INPUT_MODE,
859 M98090_EXTMIC1_SHIFT,
860 mic1_mux_text);
685e4215
JW		 861
862static const struct snd_kcontrol_new max98090_mic1_mux =
863 SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum);
864
865static const char *mic2_mux_text[] = { "IN34", "IN56" };
866
2907cbcc
TI		 867static SOC_ENUM_SINGLE_DECL(mic2_mux_enum,
868 M98090_REG_INPUT_MODE,
869 M98090_EXTMIC2_SHIFT,
870 mic2_mux_text);
685e4215
JW		 871
872static const struct snd_kcontrol_new max98090_mic2_mux =
873 SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum);
874
fd5f940f
AB		 875static const char *dmic_mux_text[] = { "ADC", "DMIC" };
876
ba513116 877static SOC_ENUM_SINGLE_VIRT_DECL(dmic_mux_enum, dmic_mux_text);
fd5f940f
AB		 878
879static const struct snd_kcontrol_new max98090_dmic_mux =
880 SOC_DAPM_ENUM_VIRT("DMIC Mux", dmic_mux_enum);
881
4ca74feb 882static const char *max98090_micpre_text[] = { "Off", "On" };
685e4215 883
2907cbcc
TI		 884static SOC_ENUM_SINGLE_DECL(max98090_pa1en_enum,
885 M98090_REG_MIC1_INPUT_LEVEL,
886 M98090_MIC_PA1EN_SHIFT,
887 max98090_micpre_text);
685e4215 888
2907cbcc
TI		 889static SOC_ENUM_SINGLE_DECL(max98090_pa2en_enum,
890 M98090_REG_MIC2_INPUT_LEVEL,
891 M98090_MIC_PA2EN_SHIFT,
892 max98090_micpre_text);
685e4215
JW		 893
894/* LINEA mixer switch */
895static const struct snd_kcontrol_new max98090_linea_mixer_controls[] = {
896 SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG,
897 M98090_IN1SEEN_SHIFT, 1, 0),
898 SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG,
899 M98090_IN3SEEN_SHIFT, 1, 0),
900 SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG,
901 M98090_IN5SEEN_SHIFT, 1, 0),
902 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG,
903 M98090_IN34DIFF_SHIFT, 1, 0),
904};
905
906/* LINEB mixer switch */
907static const struct snd_kcontrol_new max98090_lineb_mixer_controls[] = {
908 SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG,
909 M98090_IN2SEEN_SHIFT, 1, 0),
910 SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG,
911 M98090_IN4SEEN_SHIFT, 1, 0),
912 SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG,
913 M98090_IN6SEEN_SHIFT, 1, 0),
914 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG,
915 M98090_IN56DIFF_SHIFT, 1, 0),
916};
917
918/* Left ADC mixer switch */
919static const struct snd_kcontrol_new max98090_left_adc_mixer_controls[] = {
920 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER,
921 M98090_MIXADL_IN12DIFF_SHIFT, 1, 0),
922 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER,
923 M98090_MIXADL_IN34DIFF_SHIFT, 1, 0),
924 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER,
925 M98090_MIXADL_IN65DIFF_SHIFT, 1, 0),
926 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER,
927 M98090_MIXADL_LINEA_SHIFT, 1, 0),
928 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER,
929 M98090_MIXADL_LINEB_SHIFT, 1, 0),
930 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER,
931 M98090_MIXADL_MIC1_SHIFT, 1, 0),
932 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER,
933 M98090_MIXADL_MIC2_SHIFT, 1, 0),
934};
935
936/* Right ADC mixer switch */
937static const struct snd_kcontrol_new max98090_right_adc_mixer_controls[] = {
938 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER,
939 M98090_MIXADR_IN12DIFF_SHIFT, 1, 0),
940 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER,
941 M98090_MIXADR_IN34DIFF_SHIFT, 1, 0),
942 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER,
943 M98090_MIXADR_IN65DIFF_SHIFT, 1, 0),
944 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER,
945 M98090_MIXADR_LINEA_SHIFT, 1, 0),
946 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER,
947 M98090_MIXADR_LINEB_SHIFT, 1, 0),
948 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER,
949 M98090_MIXADR_MIC1_SHIFT, 1, 0),
950 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER,
951 M98090_MIXADR_MIC2_SHIFT, 1, 0),
952};
953
954static const char *lten_mux_text[] = { "Normal", "Loopthrough" };
955
2907cbcc
TI		 956static SOC_ENUM_SINGLE_DECL(ltenl_mux_enum,
957 M98090_REG_IO_CONFIGURATION,
958 M98090_LTEN_SHIFT,
959 lten_mux_text);
685e4215 960
2907cbcc
TI		 961static SOC_ENUM_SINGLE_DECL(ltenr_mux_enum,
962 M98090_REG_IO_CONFIGURATION,
963 M98090_LTEN_SHIFT,
964 lten_mux_text);
685e4215
JW		 965
966static const struct snd_kcontrol_new max98090_ltenl_mux =
967 SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum);
968
969static const struct snd_kcontrol_new max98090_ltenr_mux =
970 SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum);
971
972static const char *lben_mux_text[] = { "Normal", "Loopback" };
973
2907cbcc
TI		 974static SOC_ENUM_SINGLE_DECL(lbenl_mux_enum,
975 M98090_REG_IO_CONFIGURATION,
976 M98090_LBEN_SHIFT,
977 lben_mux_text);
685e4215 978
2907cbcc
TI		 979static SOC_ENUM_SINGLE_DECL(lbenr_mux_enum,
980 M98090_REG_IO_CONFIGURATION,
981 M98090_LBEN_SHIFT,
982 lben_mux_text);
685e4215
JW		 983
984static const struct snd_kcontrol_new max98090_lbenl_mux =
985 SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum);
986
987static const struct snd_kcontrol_new max98090_lbenr_mux =
988 SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum);
989
990static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" };
991
992static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" };
993
2907cbcc
TI		 994static SOC_ENUM_SINGLE_DECL(stenl_mux_enum,
995 M98090_REG_ADC_SIDETONE,
996 M98090_DSTSL_SHIFT,
997 stenl_mux_text);
685e4215 998
2907cbcc
TI		 999static SOC_ENUM_SINGLE_DECL(stenr_mux_enum,
1000 M98090_REG_ADC_SIDETONE,
1001 M98090_DSTSR_SHIFT,
1002 stenr_mux_text);
685e4215
JW		 1003
1004static const struct snd_kcontrol_new max98090_stenl_mux =
1005 SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum);
1006
1007static const struct snd_kcontrol_new max98090_stenr_mux =
1008 SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum);
1009
1010/* Left speaker mixer switch */
1011static const struct
1012 snd_kcontrol_new max98090_left_speaker_mixer_controls[] = {
1013 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER,
1014 M98090_MIXSPL_DACL_SHIFT, 1, 0),
1015 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER,
1016 M98090_MIXSPL_DACR_SHIFT, 1, 0),
1017 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER,
1018 M98090_MIXSPL_LINEA_SHIFT, 1, 0),
1019 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER,
1020 M98090_MIXSPL_LINEB_SHIFT, 1, 0),
1021 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER,
1022 M98090_MIXSPL_MIC1_SHIFT, 1, 0),
1023 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER,
1024 M98090_MIXSPL_MIC2_SHIFT, 1, 0),
1025};
1026
1027/* Right speaker mixer switch */
1028static const struct
1029 snd_kcontrol_new max98090_right_speaker_mixer_controls[] = {
1030 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
1031 M98090_MIXSPR_DACL_SHIFT, 1, 0),
1032 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
1033 M98090_MIXSPR_DACR_SHIFT, 1, 0),
1034 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER,
1035 M98090_MIXSPR_LINEA_SHIFT, 1, 0),
1036 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER,
1037 M98090_MIXSPR_LINEB_SHIFT, 1, 0),
1038 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER,
1039 M98090_MIXSPR_MIC1_SHIFT, 1, 0),
1040 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER,
1041 M98090_MIXSPR_MIC2_SHIFT, 1, 0),
1042};
1043
1044/* Left headphone mixer switch */
1045static const struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = {
1046 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER,
1047 M98090_MIXHPL_DACL_SHIFT, 1, 0),
1048 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER,
1049 M98090_MIXHPL_DACR_SHIFT, 1, 0),
1050 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER,
1051 M98090_MIXHPL_LINEA_SHIFT, 1, 0),
1052 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER,
1053 M98090_MIXHPL_LINEB_SHIFT, 1, 0),
1054 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER,
1055 M98090_MIXHPL_MIC1_SHIFT, 1, 0),
1056 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER,
1057 M98090_MIXHPL_MIC2_SHIFT, 1, 0),
1058};
1059
1060/* Right headphone mixer switch */
1061static const struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = {
1062 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER,
1063 M98090_MIXHPR_DACL_SHIFT, 1, 0),
1064 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER,
1065 M98090_MIXHPR_DACR_SHIFT, 1, 0),
1066 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER,
1067 M98090_MIXHPR_LINEA_SHIFT, 1, 0),
1068 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER,
1069 M98090_MIXHPR_LINEB_SHIFT, 1, 0),
1070 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER,
1071 M98090_MIXHPR_MIC1_SHIFT, 1, 0),
1072 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER,
1073 M98090_MIXHPR_MIC2_SHIFT, 1, 0),
1074};
1075
1076/* Left receiver mixer switch */
1077static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls[] = {
1078 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1079 M98090_MIXRCVL_DACL_SHIFT, 1, 0),
1080 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1081 M98090_MIXRCVL_DACR_SHIFT, 1, 0),
1082 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER,
1083 M98090_MIXRCVL_LINEA_SHIFT, 1, 0),
1084 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER,
1085 M98090_MIXRCVL_LINEB_SHIFT, 1, 0),
1086 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER,
1087 M98090_MIXRCVL_MIC1_SHIFT, 1, 0),
1088 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER,
1089 M98090_MIXRCVL_MIC2_SHIFT, 1, 0),
1090};
1091
1092/* Right receiver mixer switch */
1093static const struct snd_kcontrol_new max98090_right_rcv_mixer_controls[] = {
1094 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER,
1095 M98090_MIXRCVR_DACL_SHIFT, 1, 0),
1096 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER,
1097 M98090_MIXRCVR_DACR_SHIFT, 1, 0),
1098 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER,
1099 M98090_MIXRCVR_LINEA_SHIFT, 1, 0),
1100 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER,
1101 M98090_MIXRCVR_LINEB_SHIFT, 1, 0),
1102 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER,
1103 M98090_MIXRCVR_MIC1_SHIFT, 1, 0),
1104 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER,
1105 M98090_MIXRCVR_MIC2_SHIFT, 1, 0),
1106};
1107
1108static const char *linmod_mux_text[] = { "Left Only", "Left and Right" };
1109
2907cbcc
TI		 1110static SOC_ENUM_SINGLE_DECL(linmod_mux_enum,
1111 M98090_REG_LOUTR_MIXER,
1112 M98090_LINMOD_SHIFT,
1113 linmod_mux_text);
685e4215
JW		 1114
1115static const struct snd_kcontrol_new max98090_linmod_mux =
1116 SOC_DAPM_ENUM("LINMOD Mux", linmod_mux_enum);
1117
1118static const char *mixhpsel_mux_text[] = { "DAC Only", "HP Mixer" };
1119
1120/*
1121 * This is a mux as it selects the HP output, but to DAPM it is a Mixer enable
1122 */
2907cbcc
TI		 1123static SOC_ENUM_SINGLE_DECL(mixhplsel_mux_enum,
1124 M98090_REG_HP_CONTROL,
1125 M98090_MIXHPLSEL_SHIFT,
1126 mixhpsel_mux_text);
685e4215
JW		 1127
1128static const struct snd_kcontrol_new max98090_mixhplsel_mux =
1129 SOC_DAPM_ENUM("MIXHPLSEL Mux", mixhplsel_mux_enum);
1130
2907cbcc
TI		 1131static SOC_ENUM_SINGLE_DECL(mixhprsel_mux_enum,
1132 M98090_REG_HP_CONTROL,
1133 M98090_MIXHPRSEL_SHIFT,
1134 mixhpsel_mux_text);
685e4215
JW		 1135
1136static const struct snd_kcontrol_new max98090_mixhprsel_mux =
1137 SOC_DAPM_ENUM("MIXHPRSEL Mux", mixhprsel_mux_enum);
1138
1139static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = {
1140
1141 SND_SOC_DAPM_INPUT("MIC1"),
1142 SND_SOC_DAPM_INPUT("MIC2"),
1143 SND_SOC_DAPM_INPUT("DMICL"),
1144 SND_SOC_DAPM_INPUT("DMICR"),
1145 SND_SOC_DAPM_INPUT("IN1"),
1146 SND_SOC_DAPM_INPUT("IN2"),
1147 SND_SOC_DAPM_INPUT("IN3"),
1148 SND_SOC_DAPM_INPUT("IN4"),
1149 SND_SOC_DAPM_INPUT("IN5"),
1150 SND_SOC_DAPM_INPUT("IN6"),
1151 SND_SOC_DAPM_INPUT("IN12"),
1152 SND_SOC_DAPM_INPUT("IN34"),
1153 SND_SOC_DAPM_INPUT("IN56"),
1154
1155 SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE,
1156 M98090_MBEN_SHIFT, 0, NULL, 0),
1157 SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN,
1158 M98090_SHDNN_SHIFT, 0, NULL, 0),
1159 SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION,
1160 M98090_SDIEN_SHIFT, 0, NULL, 0),
1161 SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION,
1162 M98090_SDOEN_SHIFT, 0, NULL, 0),
1163 SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1164 M98090_DIGMICL_SHIFT, 0, NULL, 0),
1165 SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1166 M98090_DIGMICR_SHIFT, 0, NULL, 0),
1167 SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG,
1168 M98090_AHPF_SHIFT, 0, NULL, 0),
1169
1170/*
1171 * Note: Sysclk and misc power supplies are taken care of by SHDN
1172 */
1173
1174 SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM,
1175 0, 0, &max98090_mic1_mux),
1176
1177 SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM,
1178 0, 0, &max98090_mic2_mux),
1179
fd5f940f
AB		 1180 SND_SOC_DAPM_VIRT_MUX("DMIC Mux", SND_SOC_NOPM,
1181 0, 0, &max98090_dmic_mux),
1182
685e4215
JW		 1183 SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL,
1184 M98090_MIC_PA1EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1185 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1186
1187 SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL,
1188 M98090_MIC_PA2EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1189 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1190
1191 SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM, 0, 0,
1192 &max98090_linea_mixer_controls[0],
1193 ARRAY_SIZE(max98090_linea_mixer_controls)),
1194
1195 SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM, 0, 0,
1196 &max98090_lineb_mixer_controls[0],
1197 ARRAY_SIZE(max98090_lineb_mixer_controls)),
1198
1199 SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE,
1200 M98090_LINEAEN_SHIFT, 0, NULL, 0),
1201 SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE,
1202 M98090_LINEBEN_SHIFT, 0, NULL, 0),
1203
1204 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
1205 &max98090_left_adc_mixer_controls[0],
1206 ARRAY_SIZE(max98090_left_adc_mixer_controls)),
1207
1208 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
1209 &max98090_right_adc_mixer_controls[0],
1210 ARRAY_SIZE(max98090_right_adc_mixer_controls)),
1211
1212 SND_SOC_DAPM_ADC("ADCL", NULL, M98090_REG_INPUT_ENABLE,
1213 M98090_ADLEN_SHIFT, 0),
1214 SND_SOC_DAPM_ADC("ADCR", NULL, M98090_REG_INPUT_ENABLE,
1215 M98090_ADREN_SHIFT, 0),
1216
1217 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0,
1218 SND_SOC_NOPM, 0, 0),
1219 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1,
1220 SND_SOC_NOPM, 0, 0),
1221
1222 SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM,
1223 0, 0, &max98090_lbenl_mux),
1224
1225 SND_SOC_DAPM_MUX("LBENR Mux", SND_SOC_NOPM,
1226 0, 0, &max98090_lbenr_mux),
1227
1228 SND_SOC_DAPM_MUX("LTENL Mux", SND_SOC_NOPM,
1229 0, 0, &max98090_ltenl_mux),
1230
1231 SND_SOC_DAPM_MUX("LTENR Mux", SND_SOC_NOPM,
1232 0, 0, &max98090_ltenr_mux),
1233
1234 SND_SOC_DAPM_MUX("STENL Mux", SND_SOC_NOPM,
1235 0, 0, &max98090_stenl_mux),
1236
1237 SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM,
1238 0, 0, &max98090_stenr_mux),
1239
1240 SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
1241 SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0),
1242
1243 SND_SOC_DAPM_DAC("DACL", NULL, M98090_REG_OUTPUT_ENABLE,
1244 M98090_DALEN_SHIFT, 0),
1245 SND_SOC_DAPM_DAC("DACR", NULL, M98090_REG_OUTPUT_ENABLE,
1246 M98090_DAREN_SHIFT, 0),
1247
1248 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
1249 &max98090_left_hp_mixer_controls[0],
1250 ARRAY_SIZE(max98090_left_hp_mixer_controls)),
1251
1252 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
1253 &max98090_right_hp_mixer_controls[0],
1254 ARRAY_SIZE(max98090_right_hp_mixer_controls)),
1255
1256 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
1257 &max98090_left_speaker_mixer_controls[0],
1258 ARRAY_SIZE(max98090_left_speaker_mixer_controls)),
1259
1260 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
1261 &max98090_right_speaker_mixer_controls[0],
1262 ARRAY_SIZE(max98090_right_speaker_mixer_controls)),
1263
1264 SND_SOC_DAPM_MIXER("Left Receiver Mixer", SND_SOC_NOPM, 0, 0,
1265 &max98090_left_rcv_mixer_controls[0],
1266 ARRAY_SIZE(max98090_left_rcv_mixer_controls)),
1267
1268 SND_SOC_DAPM_MIXER("Right Receiver Mixer", SND_SOC_NOPM, 0, 0,
1269 &max98090_right_rcv_mixer_controls[0],
1270 ARRAY_SIZE(max98090_right_rcv_mixer_controls)),
1271
1272 SND_SOC_DAPM_MUX("LINMOD Mux", M98090_REG_LOUTR_MIXER,
1273 M98090_LINMOD_SHIFT, 0, &max98090_linmod_mux),
1274
1275 SND_SOC_DAPM_MUX("MIXHPLSEL Mux", M98090_REG_HP_CONTROL,
1276 M98090_MIXHPLSEL_SHIFT, 0, &max98090_mixhplsel_mux),
1277
1278 SND_SOC_DAPM_MUX("MIXHPRSEL Mux", M98090_REG_HP_CONTROL,
1279 M98090_MIXHPRSEL_SHIFT, 0, &max98090_mixhprsel_mux),
1280
1281 SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE,
1282 M98090_HPLEN_SHIFT, 0, NULL, 0),
1283 SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE,
1284 M98090_HPREN_SHIFT, 0, NULL, 0),
1285
1286 SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE,
1287 M98090_SPLEN_SHIFT, 0, NULL, 0),
1288 SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE,
1289 M98090_SPREN_SHIFT, 0, NULL, 0),
1290
1291 SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE,
1292 M98090_RCVLEN_SHIFT, 0, NULL, 0),
1293 SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE,
1294 M98090_RCVREN_SHIFT, 0, NULL, 0),
1295
1296 SND_SOC_DAPM_OUTPUT("HPL"),
1297 SND_SOC_DAPM_OUTPUT("HPR"),
1298 SND_SOC_DAPM_OUTPUT("SPKL"),
1299 SND_SOC_DAPM_OUTPUT("SPKR"),
1300 SND_SOC_DAPM_OUTPUT("RCVL"),
1301 SND_SOC_DAPM_OUTPUT("RCVR"),
1302};
1303
1304static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = {
1305
1306 SND_SOC_DAPM_INPUT("DMIC3"),
1307 SND_SOC_DAPM_INPUT("DMIC4"),
1308
1309 SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1310 M98090_DIGMIC3_SHIFT, 0, NULL, 0),
1311 SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1312 M98090_DIGMIC4_SHIFT, 0, NULL, 0),
1313};
1314
1315static const struct snd_soc_dapm_route max98090_dapm_routes[] = {
1316
1317 {"MIC1 Input", NULL, "MIC1"},
1318 {"MIC2 Input", NULL, "MIC2"},
1319
1320 {"DMICL", NULL, "DMICL_ENA"},
1321 {"DMICR", NULL, "DMICR_ENA"},
1322 {"DMICL", NULL, "AHPF"},
1323 {"DMICR", NULL, "AHPF"},
1324
1325 /* MIC1 input mux */
1326 {"MIC1 Mux", "IN12", "IN12"},
1327 {"MIC1 Mux", "IN56", "IN56"},
1328
1329 /* MIC2 input mux */
1330 {"MIC2 Mux", "IN34", "IN34"},
1331 {"MIC2 Mux", "IN56", "IN56"},
1332
1333 {"MIC1 Input", NULL, "MIC1 Mux"},
1334 {"MIC2 Input", NULL, "MIC2 Mux"},
1335
1336 /* Left ADC input mixer */
1337 {"Left ADC Mixer", "IN12 Switch", "IN12"},
1338 {"Left ADC Mixer", "IN34 Switch", "IN34"},
1339 {"Left ADC Mixer", "IN56 Switch", "IN56"},
1340 {"Left ADC Mixer", "LINEA Switch", "LINEA Input"},
1341 {"Left ADC Mixer", "LINEB Switch", "LINEB Input"},
1342 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1343 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1344
1345 /* Right ADC input mixer */
1346 {"Right ADC Mixer", "IN12 Switch", "IN12"},
1347 {"Right ADC Mixer", "IN34 Switch", "IN34"},
1348 {"Right ADC Mixer", "IN56 Switch", "IN56"},
1349 {"Right ADC Mixer", "LINEA Switch", "LINEA Input"},
1350 {"Right ADC Mixer", "LINEB Switch", "LINEB Input"},
1351 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1352 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1353
1354 /* Line A input mixer */
1355 {"LINEA Mixer", "IN1 Switch", "IN1"},
1356 {"LINEA Mixer", "IN3 Switch", "IN3"},
1357 {"LINEA Mixer", "IN5 Switch", "IN5"},
1358 {"LINEA Mixer", "IN34 Switch", "IN34"},
1359
1360 /* Line B input mixer */
1361 {"LINEB Mixer", "IN2 Switch", "IN2"},
1362 {"LINEB Mixer", "IN4 Switch", "IN4"},
1363 {"LINEB Mixer", "IN6 Switch", "IN6"},
1364 {"LINEB Mixer", "IN56 Switch", "IN56"},
1365
1366 {"LINEA Input", NULL, "LINEA Mixer"},
1367 {"LINEB Input", NULL, "LINEB Mixer"},
1368
1369 /* Inputs */
1370 {"ADCL", NULL, "Left ADC Mixer"},
1371 {"ADCR", NULL, "Right ADC Mixer"},
1372 {"ADCL", NULL, "SHDN"},
1373 {"ADCR", NULL, "SHDN"},
1374
fd5f940f
AB		 1375 {"DMIC Mux", "ADC", "ADCL"},
1376 {"DMIC Mux", "ADC", "ADCR"},
1377 {"DMIC Mux", "DMIC", "DMICL"},
1378 {"DMIC Mux", "DMIC", "DMICR"},
1379
1380 {"LBENL Mux", "Normal", "DMIC Mux"},
685e4215 1381 {"LBENL Mux", "Loopback", "LTENL Mux"},
fd5f940f 1382 {"LBENR Mux", "Normal", "DMIC Mux"},
685e4215
JW		 1383 {"LBENR Mux", "Loopback", "LTENR Mux"},
1384
1385 {"AIFOUTL", NULL, "LBENL Mux"},
1386 {"AIFOUTR", NULL, "LBENR Mux"},
1387 {"AIFOUTL", NULL, "SHDN"},
1388 {"AIFOUTR", NULL, "SHDN"},
1389 {"AIFOUTL", NULL, "SDOEN"},
1390 {"AIFOUTR", NULL, "SDOEN"},
1391
1392 {"LTENL Mux", "Normal", "AIFINL"},
1393 {"LTENL Mux", "Loopthrough", "LBENL Mux"},
1394 {"LTENR Mux", "Normal", "AIFINR"},
1395 {"LTENR Mux", "Loopthrough", "LBENR Mux"},
1396
1397 {"DACL", NULL, "LTENL Mux"},
1398 {"DACR", NULL, "LTENR Mux"},
1399
1400 {"STENL Mux", "Sidetone Left", "ADCL"},
1401 {"STENL Mux", "Sidetone Left", "DMICL"},
1402 {"STENR Mux", "Sidetone Right", "ADCR"},
1403 {"STENR Mux", "Sidetone Right", "DMICR"},
1404 {"DACL", "NULL", "STENL Mux"},
1405 {"DACR", "NULL", "STENL Mux"},
1406
1407 {"AIFINL", NULL, "SHDN"},
1408 {"AIFINR", NULL, "SHDN"},
1409 {"AIFINL", NULL, "SDIEN"},
1410 {"AIFINR", NULL, "SDIEN"},
1411 {"DACL", NULL, "SHDN"},
1412 {"DACR", NULL, "SHDN"},
1413
1414 /* Left headphone output mixer */
1415 {"Left Headphone Mixer", "Left DAC Switch", "DACL"},
1416 {"Left Headphone Mixer", "Right DAC Switch", "DACR"},
1417 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1418 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1419 {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"},
1420 {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"},
1421
1422 /* Right headphone output mixer */
1423 {"Right Headphone Mixer", "Left DAC Switch", "DACL"},
1424 {"Right Headphone Mixer", "Right DAC Switch", "DACR"},
1425 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1426 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1427 {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"},
1428 {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"},
1429
1430 /* Left speaker output mixer */
1431 {"Left Speaker Mixer", "Left DAC Switch", "DACL"},
1432 {"Left Speaker Mixer", "Right DAC Switch", "DACR"},
1433 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1434 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1435 {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"},
1436 {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"},
1437
1438 /* Right speaker output mixer */
1439 {"Right Speaker Mixer", "Left DAC Switch", "DACL"},
1440 {"Right Speaker Mixer", "Right DAC Switch", "DACR"},
1441 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1442 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1443 {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"},
1444 {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"},
1445
1446 /* Left Receiver output mixer */
1447 {"Left Receiver Mixer", "Left DAC Switch", "DACL"},
1448 {"Left Receiver Mixer", "Right DAC Switch", "DACR"},
1449 {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1450 {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1451 {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"},
1452 {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"},
1453
1454 /* Right Receiver output mixer */
1455 {"Right Receiver Mixer", "Left DAC Switch", "DACL"},
1456 {"Right Receiver Mixer", "Right DAC Switch", "DACR"},
1457 {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1458 {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1459 {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"},
1460 {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"},
1461
1462 {"MIXHPLSEL Mux", "HP Mixer", "Left Headphone Mixer"},
1463
1464 /*
1465 * Disable this for lowest power if bypassing
1466 * the DAC with an analog signal
1467 */
1468 {"HP Left Out", NULL, "DACL"},
1469 {"HP Left Out", NULL, "MIXHPLSEL Mux"},
1470
1471 {"MIXHPRSEL Mux", "HP Mixer", "Right Headphone Mixer"},
1472
1473 /*
1474 * Disable this for lowest power if bypassing
1475 * the DAC with an analog signal
1476 */
1477 {"HP Right Out", NULL, "DACR"},
1478 {"HP Right Out", NULL, "MIXHPRSEL Mux"},
1479
1480 {"SPK Left Out", NULL, "Left Speaker Mixer"},
1481 {"SPK Right Out", NULL, "Right Speaker Mixer"},
1482 {"RCV Left Out", NULL, "Left Receiver Mixer"},
1483
1484 {"LINMOD Mux", "Left and Right", "Right Receiver Mixer"},
1485 {"LINMOD Mux", "Left Only", "Left Receiver Mixer"},
1486 {"RCV Right Out", NULL, "LINMOD Mux"},
1487
1488 {"HPL", NULL, "HP Left Out"},
1489 {"HPR", NULL, "HP Right Out"},
1490 {"SPKL", NULL, "SPK Left Out"},
1491 {"SPKR", NULL, "SPK Right Out"},
1492 {"RCVL", NULL, "RCV Left Out"},
1493 {"RCVR", NULL, "RCV Right Out"},
1494
1495};
1496
1497static const struct snd_soc_dapm_route max98091_dapm_routes[] = {
1498
1499 /* DMIC inputs */
1500 {"DMIC3", NULL, "DMIC3_ENA"},
1501 {"DMIC4", NULL, "DMIC4_ENA"},
1502 {"DMIC3", NULL, "AHPF"},
1503 {"DMIC4", NULL, "AHPF"},
1504
1505};
1506
1507static int max98090_add_widgets(struct snd_soc_codec *codec)
1508{
1509 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1510 struct snd_soc_dapm_context *dapm = &codec->dapm;
1511
1512 snd_soc_add_codec_controls(codec, max98090_snd_controls,
1513 ARRAY_SIZE(max98090_snd_controls));
1514
1515 if (max98090->devtype == MAX98091) {
1516 snd_soc_add_codec_controls(codec, max98091_snd_controls,
1517 ARRAY_SIZE(max98091_snd_controls));
1518 }
1519
1520 snd_soc_dapm_new_controls(dapm, max98090_dapm_widgets,
1521 ARRAY_SIZE(max98090_dapm_widgets));
1522
1523 snd_soc_dapm_add_routes(dapm, max98090_dapm_routes,
1524 ARRAY_SIZE(max98090_dapm_routes));
1525
1526 if (max98090->devtype == MAX98091) {
1527 snd_soc_dapm_new_controls(dapm, max98091_dapm_widgets,
1528 ARRAY_SIZE(max98091_dapm_widgets));
1529
1530 snd_soc_dapm_add_routes(dapm, max98091_dapm_routes,
1531 ARRAY_SIZE(max98091_dapm_routes));
1532
1533 }
1534
1535 return 0;
1536}
1537
1538static const int pclk_rates[] = {
1539 12000000, 12000000, 13000000, 13000000,
1540 16000000, 16000000, 19200000, 19200000
1541};
1542
1543static const int lrclk_rates[] = {
1544 8000, 16000, 8000, 16000,
1545 8000, 16000, 8000, 16000
1546};
1547
1548static const int user_pclk_rates[] = {
1549 13000000, 13000000
1550};
1551
1552static const int user_lrclk_rates[] = {
1553 44100, 48000
1554};
1555
1556static const unsigned long long ni_value[] = {
1557 3528, 768
1558};
1559
1560static const unsigned long long mi_value[] = {
1561 8125, 1625
1562};
1563
1564static void max98090_configure_bclk(struct snd_soc_codec *codec)
1565{
1566 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1567 unsigned long long ni;
1568 int i;
1569
1570 if (!max98090->sysclk) {
1571 dev_err(codec->dev, "No SYSCLK configured\n");
1572 return;
1573 }
1574
1575 if (!max98090->bclk || !max98090->lrclk) {
1576 dev_err(codec->dev, "No audio clocks configured\n");
1577 return;
1578 }
1579
1580 /* Skip configuration when operating as slave */
1581 if (!(snd_soc_read(codec, M98090_REG_MASTER_MODE) &
1582 M98090_MAS_MASK)) {
1583 return;
1584 }
1585
1586 /* Check for supported PCLK to LRCLK ratios */
1587 for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) {
1588 if ((pclk_rates[i] == max98090->sysclk) &&
1589 (lrclk_rates[i] == max98090->lrclk)) {
1590 dev_dbg(codec->dev,
1591 "Found supported PCLK to LRCLK rates 0x%x\n",
1592 i + 0x8);
1593
1594 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1595 M98090_FREQ_MASK,
1596 (i + 0x8) << M98090_FREQ_SHIFT);
1597 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1598 M98090_USE_M1_MASK, 0);
1599 return;
1600 }
1601 }
1602
1603 /* Check for user calculated MI and NI ratios */
1604 for (i = 0; i < ARRAY_SIZE(user_pclk_rates); i++) {
1605 if ((user_pclk_rates[i] == max98090->sysclk) &&
1606 (user_lrclk_rates[i] == max98090->lrclk)) {
1607 dev_dbg(codec->dev,
1608 "Found user supported PCLK to LRCLK rates\n");
1609 dev_dbg(codec->dev, "i %d ni %lld mi %lld\n",
1610 i, ni_value[i], mi_value[i]);
1611
1612 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1613 M98090_FREQ_MASK, 0);
1614 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1615 M98090_USE_M1_MASK,
1616 1 << M98090_USE_M1_SHIFT);
1617
1618 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB,
1619 (ni_value[i] >> 8) & 0x7F);
1620 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB,
1621 ni_value[i] & 0xFF);
1622 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_MSB,
1623 (mi_value[i] >> 8) & 0x7F);
1624 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_LSB,
1625 mi_value[i] & 0xFF);
1626
1627 return;
1628 }
1629 }
1630
1631 /*
1632 * Calculate based on MI = 65536 (not as good as either method above)
1633 */
1634 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1635 M98090_FREQ_MASK, 0);
1636 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1637 M98090_USE_M1_MASK, 0);
1638
1639 /*
1640 * Configure NI when operating as master
1641 * Note: There is a small, but significant audio quality improvement
1642 * by calculating ni and mi.
1643 */
1644 ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL)
1645 * (unsigned long long int)max98090->lrclk;
1646 do_div(ni, (unsigned long long int)max98090->sysclk);
1647 dev_info(codec->dev, "No better method found\n");
1648 dev_info(codec->dev, "Calculating ni %lld with mi 65536\n", ni);
1649 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB,
1650 (ni >> 8) & 0x7F);
1651 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB, ni & 0xFF);
1652}
1653
1654static int max98090_dai_set_fmt(struct snd_soc_dai *codec_dai,
1655 unsigned int fmt)
1656{
1657 struct snd_soc_codec *codec = codec_dai->codec;
1658 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1659 struct max98090_cdata *cdata;
1660 u8 regval;
1661
1662 max98090->dai_fmt = fmt;
1663 cdata = &max98090->dai[0];
1664
1665 if (fmt != cdata->fmt) {
1666 cdata->fmt = fmt;
1667
1668 regval = 0;
1669 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1670 case SND_SOC_DAIFMT_CBS_CFS:
1671 /* Set to slave mode PLL - MAS mode off */
1672 snd_soc_write(codec,
1673 M98090_REG_CLOCK_RATIO_NI_MSB, 0x00);
1674 snd_soc_write(codec,
1675 M98090_REG_CLOCK_RATIO_NI_LSB, 0x00);
1676 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1677 M98090_USE_M1_MASK, 0);
1678 break;
1679 case SND_SOC_DAIFMT_CBM_CFM:
1680 /* Set to master mode */
1681 if (max98090->tdm_slots == 4) {
1682 /* TDM */
1683 regval |= M98090_MAS_MASK |
1684 M98090_BSEL_64;
1685 } else if (max98090->tdm_slots == 3) {
1686 /* TDM */
1687 regval |= M98090_MAS_MASK |
1688 M98090_BSEL_48;
1689 } else {
1690 /* Few TDM slots, or No TDM */
1691 regval |= M98090_MAS_MASK |
1692 M98090_BSEL_32;
1693 }
1694 break;
1695 case SND_SOC_DAIFMT_CBS_CFM:
1696 case SND_SOC_DAIFMT_CBM_CFS:
1697 default:
1698 dev_err(codec->dev, "DAI clock mode unsupported");
1699 return -EINVAL;
1700 }
1701 snd_soc_write(codec, M98090_REG_MASTER_MODE, regval);
1702
1703 regval = 0;
1704 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1705 case SND_SOC_DAIFMT_I2S:
1706 regval |= M98090_DLY_MASK;
1707 break;
1708 case SND_SOC_DAIFMT_LEFT_J:
1709 break;
1710 case SND_SOC_DAIFMT_RIGHT_J:
1711 regval |= M98090_RJ_MASK;
1712 break;
1713 case SND_SOC_DAIFMT_DSP_A:
1714 /* Not supported mode */
1715 default:
1716 dev_err(codec->dev, "DAI format unsupported");
1717 return -EINVAL;
1718 }
1719
1720 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1721 case SND_SOC_DAIFMT_NB_NF:
1722 break;
1723 case SND_SOC_DAIFMT_NB_IF:
1724 regval |= M98090_WCI_MASK;
1725 break;
1726 case SND_SOC_DAIFMT_IB_NF:
1727 regval |= M98090_BCI_MASK;
1728 break;
1729 case SND_SOC_DAIFMT_IB_IF:
1730 regval |= M98090_BCI_MASK|M98090_WCI_MASK;
1731 break;
1732 default:
1733 dev_err(codec->dev, "DAI invert mode unsupported");
1734 return -EINVAL;
1735 }
1736
1737 /*
1738 * This accommodates an inverted logic in the MAX98090 chip
1739 * for Bit Clock Invert (BCI). The inverted logic is only
1740 * seen for the case of TDM mode. The remaining cases have
1741 * normal logic.
1742 */
959b6250 1743 if (max98090->tdm_slots > 1)
685e4215 1744 regval ^= M98090_BCI_MASK;
685e4215
JW		 1745
1746 snd_soc_write(codec,
1747 M98090_REG_INTERFACE_FORMAT, regval);
1748 }
1749
1750 return 0;
1751}
1752
1753static int max98090_set_tdm_slot(struct snd_soc_dai *codec_dai,
1754 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1755{
1756 struct snd_soc_codec *codec = codec_dai->codec;
1757 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1758 struct max98090_cdata *cdata;
1759 cdata = &max98090->dai[0];
1760
1761 if (slots < 0 || slots > 4)
1762 return -EINVAL;
1763
1764 max98090->tdm_slots = slots;
1765 max98090->tdm_width = slot_width;
1766
1767 if (max98090->tdm_slots > 1) {
1768 /* SLOTL SLOTR SLOTDLY */
1769 snd_soc_write(codec, M98090_REG_TDM_FORMAT,
1770 0 << M98090_TDM_SLOTL_SHIFT |
1771 1 << M98090_TDM_SLOTR_SHIFT |
1772 0 << M98090_TDM_SLOTDLY_SHIFT);
1773
1774 /* FSW TDM */
1775 snd_soc_update_bits(codec, M98090_REG_TDM_CONTROL,
1776 M98090_TDM_MASK,
1777 M98090_TDM_MASK);
1778 }
1779
1780 /*
1781 * Normally advisable to set TDM first, but this permits either order
1782 */
1783 cdata->fmt = 0;
1784 max98090_dai_set_fmt(codec_dai, max98090->dai_fmt);
1785
1786 return 0;
1787}
1788
1789static int max98090_set_bias_level(struct snd_soc_codec *codec,
1790 enum snd_soc_bias_level level)
1791{
1792 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1793 int ret;
1794
1795 switch (level) {
1796 case SND_SOC_BIAS_ON:
685e4215
JW		 1797 if (max98090->jack_state == M98090_JACK_STATE_HEADSET) {
1798 /*
1799 * Set to normal bias level.
1800 */
1801 snd_soc_update_bits(codec, M98090_REG_MIC_BIAS_VOLTAGE,
1802 M98090_MBVSEL_MASK, M98090_MBVSEL_2V8);
1803 }
1804 break;
1805
1806 case SND_SOC_BIAS_PREPARE:
1807 break;
1808
1809 case SND_SOC_BIAS_STANDBY:
c42c8922
DR		 1810 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1811 ret = regcache_sync(max98090->regmap);
1812 if (ret != 0) {
1813 dev_err(codec->dev,
1814 "Failed to sync cache: %d\n", ret);
1815 return ret;
1816 }
1817 }
1818 break;
1819
685e4215
JW		 1820 case SND_SOC_BIAS_OFF:
1821 /* Set internal pull-up to lowest power mode */
1822 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
1823 M98090_JDWK_MASK, M98090_JDWK_MASK);
1824 regcache_mark_dirty(max98090->regmap);
1825 break;
1826 }
1827 codec->dapm.bias_level = level;
1828 return 0;
1829}
1830
1831static const int comp_pclk_rates[] = {
1832 11289600, 12288000, 12000000, 13000000, 19200000
1833};
1834
1835static const int dmic_micclk[] = {
1836 2, 2, 2, 2, 4, 2
1837};
1838
1839static const int comp_lrclk_rates[] = {
1840 8000, 16000, 32000, 44100, 48000, 96000
1841};
1842
1843static const int dmic_comp[6][6] = {
1844 {7, 8, 3, 3, 3, 3},
1845 {7, 8, 3, 3, 3, 3},
1846 {7, 8, 3, 3, 3, 3},
1847 {7, 8, 3, 1, 1, 1},
1848 {7, 8, 3, 1, 2, 2},
1849 {7, 8, 3, 3, 3, 3}
1850};
1851
1852static int max98090_dai_hw_params(struct snd_pcm_substream *substream,
1853 struct snd_pcm_hw_params *params,
1854 struct snd_soc_dai *dai)
1855{
1856 struct snd_soc_codec *codec = dai->codec;
1857 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1858 struct max98090_cdata *cdata;
1859 int i, j;
1860
1861 cdata = &max98090->dai[0];
1862 max98090->bclk = snd_soc_params_to_bclk(params);
1863 if (params_channels(params) == 1)
1864 max98090->bclk *= 2;
1865
1866 max98090->lrclk = params_rate(params);
1867
7821afc4
MB		 1868 switch (params_width(params)) {
1869 case 16:
685e4215
JW		 1870 snd_soc_update_bits(codec, M98090_REG_INTERFACE_FORMAT,
1871 M98090_WS_MASK, 0);
1872 break;
1873 default:
1874 return -EINVAL;
1875 }
1876
1877 max98090_configure_bclk(codec);
1878
1879 cdata->rate = max98090->lrclk;
1880
1881 /* Update filter mode */
1882 if (max98090->lrclk < 24000)
1883 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1884 M98090_MODE_MASK, 0);
1885 else
1886 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1887 M98090_MODE_MASK, M98090_MODE_MASK);
1888
1889 /* Update sample rate mode */
1890 if (max98090->lrclk < 50000)
1891 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1892 M98090_DHF_MASK, 0);
1893 else
1894 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1895 M98090_DHF_MASK, M98090_DHF_MASK);
1896
1897 /* Check for supported PCLK to LRCLK ratios */
1898 for (j = 0; j < ARRAY_SIZE(comp_pclk_rates); j++) {
1899 if (comp_pclk_rates[j] == max98090->sysclk) {
1900 break;
1901 }
1902 }
1903
1904 for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) {
1905 if (max98090->lrclk <= (comp_lrclk_rates[i] +
1906 comp_lrclk_rates[i + 1]) / 2) {
1907 break;
1908 }
1909 }
1910
1911 snd_soc_update_bits(codec, M98090_REG_DIGITAL_MIC_ENABLE,
1912 M98090_MICCLK_MASK,
1913 dmic_micclk[j] << M98090_MICCLK_SHIFT);
1914
1915 snd_soc_update_bits(codec, M98090_REG_DIGITAL_MIC_CONFIG,
1916 M98090_DMIC_COMP_MASK,
1917 dmic_comp[j][i] << M98090_DMIC_COMP_SHIFT);
1918
1919 return 0;
1920}
1921
1922/*
1923 * PLL / Sysclk
1924 */
1925static int max98090_dai_set_sysclk(struct snd_soc_dai *dai,
1926 int clk_id, unsigned int freq, int dir)
1927{
1928 struct snd_soc_codec *codec = dai->codec;
1929 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1930
1931 /* Requested clock frequency is already setup */
1932 if (freq == max98090->sysclk)
1933 return 0;
1934
1935 /* Setup clocks for slave mode, and using the PLL
1936 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
1937 * 0x02 (when master clk is 20MHz to 40MHz)..
1938 * 0x03 (when master clk is 40MHz to 60MHz)..
1939 */
1940 if ((freq >= 10000000) && (freq < 20000000)) {
1941 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
1942 M98090_PSCLK_DIV1);
1943 } else if ((freq >= 20000000) && (freq < 40000000)) {
1944 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
1945 M98090_PSCLK_DIV2);
1946 } else if ((freq >= 40000000) && (freq < 60000000)) {
1947 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
1948 M98090_PSCLK_DIV4);
1949 } else {
1950 dev_err(codec->dev, "Invalid master clock frequency\n");
1951 return -EINVAL;
1952 }
1953
1954 max98090->sysclk = freq;
1955
1956 max98090_configure_bclk(codec);
1957
1958 return 0;
1959}
1960
1961static int max98090_dai_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1962{
1963 struct snd_soc_codec *codec = codec_dai->codec;
1964 int regval;
1965
1966 regval = mute ? M98090_DVM_MASK : 0;
1967 snd_soc_update_bits(codec, M98090_REG_DAI_PLAYBACK_LEVEL,
1968 M98090_DVM_MASK, regval);
1969
1970 return 0;
1971}
1972
1973static void max98090_jack_work(struct work_struct *work)
1974{
1975 struct max98090_priv *max98090 = container_of(work,
1976 struct max98090_priv,
1977 jack_work.work);
1978 struct snd_soc_codec *codec = max98090->codec;
1979 struct snd_soc_dapm_context *dapm = &codec->dapm;
1980 int status = 0;
1981 int reg;
1982
1983 /* Read a second time */
1984 if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) {
1985
1986 /* Strong pull up allows mic detection */
1987 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
1988 M98090_JDWK_MASK, 0);
1989
1990 msleep(50);
1991
1992 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
1993
1994 /* Weak pull up allows only insertion detection */
1995 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
1996 M98090_JDWK_MASK, M98090_JDWK_MASK);
1997 } else {
1998 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
1999 }
2000
2001 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
2002
2003 switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) {
2004 case M98090_LSNS_MASK | M98090_JKSNS_MASK:
2005 dev_dbg(codec->dev, "No Headset Detected\n");
2006
2007 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
2008
2009 status |= 0;
2010
2011 break;
2012
2013 case 0:
2014 if (max98090->jack_state ==
2015 M98090_JACK_STATE_HEADSET) {
2016
2017 dev_dbg(codec->dev,
2018 "Headset Button Down Detected\n");
2019
2020 /*
2021 * max98090_headset_button_event(codec)
2022 * could be defined, then called here.
2023 */
2024
2025 status |= SND_JACK_HEADSET;
2026 status |= SND_JACK_BTN_0;
2027
2028 break;
2029 }
2030
2031 /* Line is reported as Headphone */
2032 /* Nokia Headset is reported as Headphone */
2033 /* Mono Headphone is reported as Headphone */
2034 dev_dbg(codec->dev, "Headphone Detected\n");
2035
2036 max98090->jack_state = M98090_JACK_STATE_HEADPHONE;
2037
2038 status |= SND_JACK_HEADPHONE;
2039
2040 break;
2041
2042 case M98090_JKSNS_MASK:
2043 dev_dbg(codec->dev, "Headset Detected\n");
2044
2045 max98090->jack_state = M98090_JACK_STATE_HEADSET;
2046
2047 status |= SND_JACK_HEADSET;
2048
2049 break;
2050
2051 default:
2052 dev_dbg(codec->dev, "Unrecognized Jack Status\n");
2053 break;
2054 }
2055
2056 snd_soc_jack_report(max98090->jack, status,
2057 SND_JACK_HEADSET | SND_JACK_BTN_0);
2058
2059 snd_soc_dapm_sync(dapm);
2060}
2061
2062static irqreturn_t max98090_interrupt(int irq, void *data)
2063{
2064 struct snd_soc_codec *codec = data;
2065 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2066 int ret;
2067 unsigned int mask;
2068 unsigned int active;
2069
2070 dev_dbg(codec->dev, "***** max98090_interrupt *****\n");
2071
2072 ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
2073
2074 if (ret != 0) {
2075 dev_err(codec->dev,
2076 "failed to read M98090_REG_INTERRUPT_S: %d\n",
2077 ret);
2078 return IRQ_NONE;
2079 }
2080
2081 ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active);
2082
2083 if (ret != 0) {
2084 dev_err(codec->dev,
2085 "failed to read M98090_REG_DEVICE_STATUS: %d\n",
2086 ret);
2087 return IRQ_NONE;
2088 }
2089
2090 dev_dbg(codec->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n",
2091 active, mask, active & mask);
2092
2093 active &= mask;
2094
2095 if (!active)
2096 return IRQ_NONE;
2097
959b6250 2098 if (active & M98090_CLD_MASK)
685e4215 2099 dev_err(codec->dev, "M98090_CLD_MASK\n");
685e4215 2100
959b6250 2101 if (active & M98090_SLD_MASK)
685e4215 2102 dev_dbg(codec->dev, "M98090_SLD_MASK\n");
685e4215 2103
959b6250 2104 if (active & M98090_ULK_MASK)
685e4215 2105 dev_err(codec->dev, "M98090_ULK_MASK\n");
685e4215
JW		 2106
2107 if (active & M98090_JDET_MASK) {
2108 dev_dbg(codec->dev, "M98090_JDET_MASK\n");
2109
2110 pm_wakeup_event(codec->dev, 100);
2111
2df7c6aa
MB		 2112 queue_delayed_work(system_power_efficient_wq,
2113 &max98090->jack_work,
2114 msecs_to_jiffies(100));
685e4215
JW		 2115 }
2116
959b6250 2117 if (active & M98090_DRCACT_MASK)
685e4215 2118 dev_dbg(codec->dev, "M98090_DRCACT_MASK\n");
685e4215 2119
959b6250 2120 if (active & M98090_DRCCLP_MASK)
685e4215 2121 dev_err(codec->dev, "M98090_DRCCLP_MASK\n");
685e4215
JW		 2122
2123 return IRQ_HANDLED;
2124}
2125
2126/**
2127 * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ
2128 *
2129 * @codec: MAX98090 codec
2130 * @jack: jack to report detection events on
2131 *
2132 * Enable microphone detection via IRQ on the MAX98090. If GPIOs are
2133 * being used to bring out signals to the processor then only platform
2134 * data configuration is needed for MAX98090 and processor GPIOs should
2135 * be configured using snd_soc_jack_add_gpios() instead.
2136 *
2137 * If no jack is supplied detection will be disabled.
2138 */
2139int max98090_mic_detect(struct snd_soc_codec *codec,
2140 struct snd_soc_jack *jack)
2141{
2142 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2143
2144 dev_dbg(codec->dev, "max98090_mic_detect\n");
2145
2146 max98090->jack = jack;
2147 if (jack) {
2148 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2149 M98090_IJDET_MASK,
2150 1 << M98090_IJDET_SHIFT);
2151 } else {
2152 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2153 M98090_IJDET_MASK,
2154 0);
2155 }
2156
2157 /* Send an initial empty report */
2158 snd_soc_jack_report(max98090->jack, 0,
2159 SND_JACK_HEADSET | SND_JACK_BTN_0);
2160
2df7c6aa
MB		 2161 queue_delayed_work(system_power_efficient_wq,
2162 &max98090->jack_work,
2163 msecs_to_jiffies(100));
685e4215
JW		 2164
2165 return 0;
2166}
2167EXPORT_SYMBOL_GPL(max98090_mic_detect);
2168
2169#define MAX98090_RATES SNDRV_PCM_RATE_8000_96000
2170#define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
2171
2172static struct snd_soc_dai_ops max98090_dai_ops = {
2173 .set_sysclk = max98090_dai_set_sysclk,
2174 .set_fmt = max98090_dai_set_fmt,
2175 .set_tdm_slot = max98090_set_tdm_slot,
2176 .hw_params = max98090_dai_hw_params,
2177 .digital_mute = max98090_dai_digital_mute,
2178};
2179
2180static struct snd_soc_dai_driver max98090_dai[] = {
2181{
2182 .name = "HiFi",
2183 .playback = {
2184 .stream_name = "HiFi Playback",
2185 .channels_min = 2,
2186 .channels_max = 2,
2187 .rates = MAX98090_RATES,
2188 .formats = MAX98090_FORMATS,
2189 },
2190 .capture = {
2191 .stream_name = "HiFi Capture",
2192 .channels_min = 1,
2193 .channels_max = 2,
2194 .rates = MAX98090_RATES,
2195 .formats = MAX98090_FORMATS,
2196 },
2197 .ops = &max98090_dai_ops,
2198}
2199};
2200
2201static void max98090_handle_pdata(struct snd_soc_codec *codec)
2202{
2203 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2204 struct max98090_pdata *pdata = max98090->pdata;
2205
2206 if (!pdata) {
2207 dev_err(codec->dev, "No platform data\n");
2208 return;
2209 }
2210
2211}
2212
2213static int max98090_probe(struct snd_soc_codec *codec)
2214{
2215 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2216 struct max98090_cdata *cdata;
2217 int ret = 0;
2218
2219 dev_dbg(codec->dev, "max98090_probe\n");
2220
2221 max98090->codec = codec;
2222
685e4215
JW		 2223 /* Reset the codec, the DSP core, and disable all interrupts */
2224 max98090_reset(max98090);
2225
2226 /* Initialize private data */
2227
2228 max98090->sysclk = (unsigned)-1;
2229
2230 cdata = &max98090->dai[0];
2231 cdata->rate = (unsigned)-1;
2232 cdata->fmt = (unsigned)-1;
2233
2234 max98090->lin_state = 0;
2235 max98090->pa1en = 0;
2236 max98090->pa2en = 0;
2237 max98090->extmic_mux = 0;
2238
2239 ret = snd_soc_read(codec, M98090_REG_REVISION_ID);
2240 if (ret < 0) {
2241 dev_err(codec->dev, "Failed to read device revision: %d\n",
2242 ret);
2243 goto err_access;
2244 }
2245
2246 if ((ret >= M98090_REVA) && (ret <= M98090_REVA + 0x0f)) {
2247 max98090->devtype = MAX98090;
2248 dev_info(codec->dev, "MAX98090 REVID=0x%02x\n", ret);
2249 } else if ((ret >= M98091_REVA) && (ret <= M98091_REVA + 0x0f)) {
2250 max98090->devtype = MAX98091;
2251 dev_info(codec->dev, "MAX98091 REVID=0x%02x\n", ret);
2252 } else {
2253 max98090->devtype = MAX98090;
2254 dev_err(codec->dev, "Unrecognized revision 0x%02x\n", ret);
2255 }
2256
2257 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
2258
2259 INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work);
2260
2261 /* Enable jack detection */
2262 snd_soc_write(codec, M98090_REG_JACK_DETECT,
2263 M98090_JDETEN_MASK | M98090_JDEB_25MS);
2264
2265 /* Register for interrupts */
2266 dev_dbg(codec->dev, "irq = %d\n", max98090->irq);
2267
2268 ret = request_threaded_irq(max98090->irq, NULL,
3d15aacb 2269 max98090_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
685e4215
JW		 2270 "max98090_interrupt", codec);
2271 if (ret < 0) {
2272 dev_err(codec->dev, "request_irq failed: %d\n",
2273 ret);
2274 }
2275
2276 /*
2277 * Clear any old interrupts.
2278 * An old interrupt ocurring prior to installing the ISR
2279 * can keep a new interrupt from generating a trigger.
2280 */
2281 snd_soc_read(codec, M98090_REG_DEVICE_STATUS);
2282
2283 /* High Performance is default */
2284 snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL,
2285 M98090_DACHP_MASK,
2286 1 << M98090_DACHP_SHIFT);
2287 snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL,
2288 M98090_PERFMODE_MASK,
2289 0 << M98090_PERFMODE_SHIFT);
2290 snd_soc_update_bits(codec, M98090_REG_ADC_CONTROL,
2291 M98090_ADCHP_MASK,
2292 1 << M98090_ADCHP_SHIFT);
2293
2294 /* Turn on VCM bandgap reference */
2295 snd_soc_write(codec, M98090_REG_BIAS_CONTROL,
2296 M98090_VCM_MODE_MASK);
2297
2298 max98090_handle_pdata(codec);
2299
2300 max98090_add_widgets(codec);
2301
2302err_access:
2303 return ret;
2304}
2305
2306static int max98090_remove(struct snd_soc_codec *codec)
2307{
2308 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2309
2310 cancel_delayed_work_sync(&max98090->jack_work);
2311
2312 return 0;
2313}
2314
2315static struct snd_soc_codec_driver soc_codec_dev_max98090 = {
2316 .probe = max98090_probe,
2317 .remove = max98090_remove,
2318 .set_bias_level = max98090_set_bias_level,
2319};
2320
2321static const struct regmap_config max98090_regmap = {
2322 .reg_bits = 8,
2323 .val_bits = 8,
2324
2325 .max_register = MAX98090_MAX_REGISTER,
2326 .reg_defaults = max98090_reg,
2327 .num_reg_defaults = ARRAY_SIZE(max98090_reg),
2328 .volatile_reg = max98090_volatile_register,
2329 .readable_reg = max98090_readable_register,
2330 .cache_type = REGCACHE_RBTREE,
2331};
2332
2333static int max98090_i2c_probe(struct i2c_client *i2c,
2334 const struct i2c_device_id *id)
2335{
2336 struct max98090_priv *max98090;
2337 int ret;
2338
2339 pr_debug("max98090_i2c_probe\n");
2340
2341 max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv),
2342 GFP_KERNEL);
2343 if (max98090 == NULL)
2344 return -ENOMEM;
2345
2346 max98090->devtype = id->driver_data;
2347 i2c_set_clientdata(i2c, max98090);
685e4215
JW		 2348 max98090->pdata = i2c->dev.platform_data;
2349 max98090->irq = i2c->irq;
2350
a3a6cc84 2351 max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap);
685e4215
JW		 2352 if (IS_ERR(max98090->regmap)) {
2353 ret = PTR_ERR(max98090->regmap);
2354 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
2355 goto err_enable;
2356 }
2357
2358 ret = snd_soc_register_codec(&i2c->dev,
2359 &soc_codec_dev_max98090, max98090_dai,
2360 ARRAY_SIZE(max98090_dai));
685e4215
JW		 2361err_enable:
2362 return ret;
2363}
2364
2365static int max98090_i2c_remove(struct i2c_client *client)
2366{
685e4215 2367 snd_soc_unregister_codec(&client->dev);
685e4215
JW		 2368 return 0;
2369}
2370
3722dc8e 2371#ifdef CONFIG_PM_RUNTIME
685e4215
JW		 2372static int max98090_runtime_resume(struct device *dev)
2373{
2374 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2375
2376 regcache_cache_only(max98090->regmap, false);
2377
25b4ab43
LG		 2378 max98090_reset(max98090);
2379
685e4215
JW		 2380 regcache_sync(max98090->regmap);
2381
2382 return 0;
2383}
2384
2385static int max98090_runtime_suspend(struct device *dev)
2386{
2387 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2388
2389 regcache_cache_only(max98090->regmap, true);
2390
2391 return 0;
2392}
3722dc8e 2393#endif
685e4215 2394
3e12af7e 2395static const struct dev_pm_ops max98090_pm = {
685e4215
JW		 2396 SET_RUNTIME_PM_OPS(max98090_runtime_suspend,
2397 max98090_runtime_resume, NULL)
2398};
2399
2400static const struct i2c_device_id max98090_i2c_id[] = {
2401 { "max98090", MAX98090 },
2402 { }
2403};
2404MODULE_DEVICE_TABLE(i2c, max98090_i2c_id);
2405
2951f93f
SW		 2406static const struct of_device_id max98090_of_match[] = {
2407 { .compatible = "maxim,max98090", },
2408 { }
2409};
2410MODULE_DEVICE_TABLE(of, max98090_of_match);
2411
685e4215
JW		 2412static struct i2c_driver max98090_i2c_driver = {
2413 .driver = {
2414 .name = "max98090",
2415 .owner = THIS_MODULE,
2416 .pm = &max98090_pm,
2951f93f 2417 .of_match_table = of_match_ptr(max98090_of_match),
685e4215
JW		 2418 },
2419 .probe = max98090_i2c_probe,
2420 .remove = max98090_i2c_remove,
2421 .id_table = max98090_i2c_id,
2422};
2423
2424module_i2c_driver(max98090_i2c_driver);
2425
2426MODULE_DESCRIPTION("ALSA SoC MAX98090 driver");
2427MODULE_AUTHOR("Peter Hsiang, Jesse Marroqin, Jerry Wong");
2428MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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