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ASoC: max98090: Add ACPI probing support
[deliverable/linux.git] / sound / soc / codecs / max98090.c
CommitLineData
685e4215
JW		 1/*
2 * max98090.c -- MAX98090 ALSA SoC Audio driver
3 *
4 * Copyright 2011-2012 Maxim Integrated Products
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/delay.h>
12#include <linux/i2c.h>
13#include <linux/module.h>
14#include <linux/pm.h>
15#include <linux/pm_runtime.h>
16#include <linux/regmap.h>
17#include <linux/slab.h>
70f29d38 18#include <linux/acpi.h>
685e4215
JW		 19#include <sound/jack.h>
20#include <sound/pcm.h>
21#include <sound/pcm_params.h>
22#include <sound/soc.h>
23#include <sound/tlv.h>
24#include <sound/max98090.h>
25#include "max98090.h"
26
685e4215
JW		 27#define DEBUG
28#define EXTMIC_METHOD
29#define EXTMIC_METHOD_TEST
30
31/* Allows for sparsely populated register maps */
32static struct reg_default max98090_reg[] = {
33 { 0x00, 0x00 }, /* 00 Software Reset */
34 { 0x03, 0x04 }, /* 03 Interrupt Masks */
35 { 0x04, 0x00 }, /* 04 System Clock Quick */
36 { 0x05, 0x00 }, /* 05 Sample Rate Quick */
37 { 0x06, 0x00 }, /* 06 DAI Interface Quick */
38 { 0x07, 0x00 }, /* 07 DAC Path Quick */
39 { 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */
40 { 0x09, 0x00 }, /* 09 Line to ADC Quick */
41 { 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */
42 { 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */
43 { 0x0C, 0x00 }, /* 0C Reserved */
44 { 0x0D, 0x00 }, /* 0D Input Config */
45 { 0x0E, 0x1B }, /* 0E Line Input Level */
46 { 0x0F, 0x00 }, /* 0F Line Config */
47
48 { 0x10, 0x14 }, /* 10 Mic1 Input Level */
49 { 0x11, 0x14 }, /* 11 Mic2 Input Level */
50 { 0x12, 0x00 }, /* 12 Mic Bias Voltage */
51 { 0x13, 0x00 }, /* 13 Digital Mic Config */
52 { 0x14, 0x00 }, /* 14 Digital Mic Mode */
53 { 0x15, 0x00 }, /* 15 Left ADC Mixer */
54 { 0x16, 0x00 }, /* 16 Right ADC Mixer */
55 { 0x17, 0x03 }, /* 17 Left ADC Level */
56 { 0x18, 0x03 }, /* 18 Right ADC Level */
57 { 0x19, 0x00 }, /* 19 ADC Biquad Level */
58 { 0x1A, 0x00 }, /* 1A ADC Sidetone */
59 { 0x1B, 0x00 }, /* 1B System Clock */
60 { 0x1C, 0x00 }, /* 1C Clock Mode */
61 { 0x1D, 0x00 }, /* 1D Any Clock 1 */
62 { 0x1E, 0x00 }, /* 1E Any Clock 2 */
63 { 0x1F, 0x00 }, /* 1F Any Clock 3 */
64
65 { 0x20, 0x00 }, /* 20 Any Clock 4 */
66 { 0x21, 0x00 }, /* 21 Master Mode */
67 { 0x22, 0x00 }, /* 22 Interface Format */
68 { 0x23, 0x00 }, /* 23 TDM Format 1*/
69 { 0x24, 0x00 }, /* 24 TDM Format 2*/
70 { 0x25, 0x00 }, /* 25 I/O Configuration */
71 { 0x26, 0x80 }, /* 26 Filter Config */
72 { 0x27, 0x00 }, /* 27 DAI Playback Level */
73 { 0x28, 0x00 }, /* 28 EQ Playback Level */
74 { 0x29, 0x00 }, /* 29 Left HP Mixer */
75 { 0x2A, 0x00 }, /* 2A Right HP Mixer */
76 { 0x2B, 0x00 }, /* 2B HP Control */
77 { 0x2C, 0x1A }, /* 2C Left HP Volume */
78 { 0x2D, 0x1A }, /* 2D Right HP Volume */
79 { 0x2E, 0x00 }, /* 2E Left Spk Mixer */
80 { 0x2F, 0x00 }, /* 2F Right Spk Mixer */
81
82 { 0x30, 0x00 }, /* 30 Spk Control */
83 { 0x31, 0x2C }, /* 31 Left Spk Volume */
84 { 0x32, 0x2C }, /* 32 Right Spk Volume */
85 { 0x33, 0x00 }, /* 33 ALC Timing */
86 { 0x34, 0x00 }, /* 34 ALC Compressor */
87 { 0x35, 0x00 }, /* 35 ALC Expander */
88 { 0x36, 0x00 }, /* 36 ALC Gain */
89 { 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */
90 { 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */
91 { 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */
92 { 0x3A, 0x00 }, /* 3A Line OutR Mixer */
93 { 0x3B, 0x00 }, /* 3B Line OutR Control */
94 { 0x3C, 0x15 }, /* 3C Line OutR Volume */
95 { 0x3D, 0x00 }, /* 3D Jack Detect */
96 { 0x3E, 0x00 }, /* 3E Input Enable */
97 { 0x3F, 0x00 }, /* 3F Output Enable */
98
99 { 0x40, 0x00 }, /* 40 Level Control */
100 { 0x41, 0x00 }, /* 41 DSP Filter Enable */
101 { 0x42, 0x00 }, /* 42 Bias Control */
102 { 0x43, 0x00 }, /* 43 DAC Control */
103 { 0x44, 0x06 }, /* 44 ADC Control */
104 { 0x45, 0x00 }, /* 45 Device Shutdown */
105 { 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */
106 { 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */
107 { 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */
108 { 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */
109 { 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */
110 { 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */
111 { 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */
112 { 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */
113 { 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */
114 { 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */
115
116 { 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */
117 { 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */
118 { 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */
119 { 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */
120 { 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */
121 { 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */
122 { 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */
123 { 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */
124 { 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */
125 { 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */
126 { 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */
127 { 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */
128 { 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */
129 { 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */
130 { 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */
131 { 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */
132
133 { 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */
134 { 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */
135 { 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */
136 { 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */
137 { 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */
138 { 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */
139 { 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */
140 { 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */
141 { 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */
142 { 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */
143 { 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */
144 { 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */
145 { 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */
146 { 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */
147 { 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */
148 { 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */
149
150 { 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */
151 { 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */
152 { 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */
153 { 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */
154 { 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */
155 { 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */
156 { 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */
157 { 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */
158 { 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */
159 { 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */
160 { 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */
161 { 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */
162 { 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */
163 { 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */
164 { 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */
165 { 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */
166
167 { 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */
168 { 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */
169 { 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */
170 { 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */
171 { 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */
172 { 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */
173 { 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */
174 { 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */
175 { 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */
176 { 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */
177 { 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */
178 { 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */
179 { 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */
180 { 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */
181 { 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */
182 { 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */
183
184 { 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */
185 { 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */
186 { 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */
187 { 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */
188 { 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */
189 { 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */
190 { 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */
191 { 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */
192 { 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */
193 { 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */
194 { 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */
195 { 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */
196 { 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */
197 { 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */
198 { 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */
199 { 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */
200
201 { 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */
202 { 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */
203 { 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */
204 { 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */
205 { 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */
206 { 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */
207 { 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */
208 { 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */
209 { 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */
210 { 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */
211 { 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */
212 { 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */
213 { 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */
214 { 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */
215 { 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */
216 { 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */
217
218 { 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */
219 { 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */
220 { 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */
221 { 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */
222 { 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */
223 { 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */
224 { 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */
225 { 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */
226 { 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */
227 { 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */
228 { 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */
229 { 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */
230 { 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */
231 { 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */
232 { 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */
233 { 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */
234
235 { 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */
236 { 0xC1, 0x00 }, /* C1 Record TDM Slot */
237 { 0xC2, 0x00 }, /* C2 Sample Rate */
238 { 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */
239 { 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */
240 { 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */
241 { 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */
242 { 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */
243 { 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */
244 { 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */
245 { 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */
246 { 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */
247 { 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */
248 { 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */
249 { 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */
250 { 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */
251
252 { 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */
253 { 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */
254};
255
256static bool max98090_volatile_register(struct device *dev, unsigned int reg)
257{
258 switch (reg) {
259 case M98090_REG_DEVICE_STATUS:
260 case M98090_REG_JACK_STATUS:
261 case M98090_REG_REVISION_ID:
262 return true;
263 default:
264 return false;
265 }
266}
267
268static bool max98090_readable_register(struct device *dev, unsigned int reg)
269{
270 switch (reg) {
271 case M98090_REG_DEVICE_STATUS:
272 case M98090_REG_JACK_STATUS:
273 case M98090_REG_INTERRUPT_S:
274 case M98090_REG_RESERVED:
275 case M98090_REG_LINE_INPUT_CONFIG:
276 case M98090_REG_LINE_INPUT_LEVEL:
277 case M98090_REG_INPUT_MODE:
278 case M98090_REG_MIC1_INPUT_LEVEL:
279 case M98090_REG_MIC2_INPUT_LEVEL:
280 case M98090_REG_MIC_BIAS_VOLTAGE:
281 case M98090_REG_DIGITAL_MIC_ENABLE:
282 case M98090_REG_DIGITAL_MIC_CONFIG:
283 case M98090_REG_LEFT_ADC_MIXER:
284 case M98090_REG_RIGHT_ADC_MIXER:
285 case M98090_REG_LEFT_ADC_LEVEL:
286 case M98090_REG_RIGHT_ADC_LEVEL:
287 case M98090_REG_ADC_BIQUAD_LEVEL:
288 case M98090_REG_ADC_SIDETONE:
289 case M98090_REG_SYSTEM_CLOCK:
290 case M98090_REG_CLOCK_MODE:
291 case M98090_REG_CLOCK_RATIO_NI_MSB:
292 case M98090_REG_CLOCK_RATIO_NI_LSB:
293 case M98090_REG_CLOCK_RATIO_MI_MSB:
294 case M98090_REG_CLOCK_RATIO_MI_LSB:
295 case M98090_REG_MASTER_MODE:
296 case M98090_REG_INTERFACE_FORMAT:
297 case M98090_REG_TDM_CONTROL:
298 case M98090_REG_TDM_FORMAT:
299 case M98090_REG_IO_CONFIGURATION:
300 case M98090_REG_FILTER_CONFIG:
301 case M98090_REG_DAI_PLAYBACK_LEVEL:
302 case M98090_REG_DAI_PLAYBACK_LEVEL_EQ:
303 case M98090_REG_LEFT_HP_MIXER:
304 case M98090_REG_RIGHT_HP_MIXER:
305 case M98090_REG_HP_CONTROL:
306 case M98090_REG_LEFT_HP_VOLUME:
307 case M98090_REG_RIGHT_HP_VOLUME:
308 case M98090_REG_LEFT_SPK_MIXER:
309 case M98090_REG_RIGHT_SPK_MIXER:
310 case M98090_REG_SPK_CONTROL:
311 case M98090_REG_LEFT_SPK_VOLUME:
312 case M98090_REG_RIGHT_SPK_VOLUME:
313 case M98090_REG_DRC_TIMING:
314 case M98090_REG_DRC_COMPRESSOR:
315 case M98090_REG_DRC_EXPANDER:
316 case M98090_REG_DRC_GAIN:
317 case M98090_REG_RCV_LOUTL_MIXER:
318 case M98090_REG_RCV_LOUTL_CONTROL:
319 case M98090_REG_RCV_LOUTL_VOLUME:
320 case M98090_REG_LOUTR_MIXER:
321 case M98090_REG_LOUTR_CONTROL:
322 case M98090_REG_LOUTR_VOLUME:
323 case M98090_REG_JACK_DETECT:
324 case M98090_REG_INPUT_ENABLE:
325 case M98090_REG_OUTPUT_ENABLE:
326 case M98090_REG_LEVEL_CONTROL:
327 case M98090_REG_DSP_FILTER_ENABLE:
328 case M98090_REG_BIAS_CONTROL:
329 case M98090_REG_DAC_CONTROL:
330 case M98090_REG_ADC_CONTROL:
331 case M98090_REG_DEVICE_SHUTDOWN:
332 case M98090_REG_EQUALIZER_BASE ... M98090_REG_EQUALIZER_BASE + 0x68:
333 case M98090_REG_RECORD_BIQUAD_BASE ... M98090_REG_RECORD_BIQUAD_BASE + 0x0E:
334 case M98090_REG_DMIC3_VOLUME:
335 case M98090_REG_DMIC4_VOLUME:
336 case M98090_REG_DMIC34_BQ_PREATTEN:
337 case M98090_REG_RECORD_TDM_SLOT:
338 case M98090_REG_SAMPLE_RATE:
339 case M98090_REG_DMIC34_BIQUAD_BASE ... M98090_REG_DMIC34_BIQUAD_BASE + 0x0E:
e126a646 340 case M98090_REG_REVISION_ID:
685e4215
JW		 341 return true;
342 default:
343 return false;
344 }
345}
346
347static int max98090_reset(struct max98090_priv *max98090)
348{
349 int ret;
350
351 /* Reset the codec by writing to this write-only reset register */
352 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET,
353 M98090_SWRESET_MASK);
354 if (ret < 0) {
355 dev_err(max98090->codec->dev,
356 "Failed to reset codec: %d\n", ret);
357 return ret;
358 }
359
360 msleep(20);
361 return ret;
362}
363
364static const unsigned int max98090_micboost_tlv[] = {
365 TLV_DB_RANGE_HEAD(2),
366 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
367 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0),
368};
369
370static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv, 0, 100, 0);
371
372static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv,
373 -600, 600, 0);
374
375static const unsigned int max98090_line_tlv[] = {
376 TLV_DB_RANGE_HEAD(2),
377 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0),
378 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0),
379};
380
381static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv, 0, 600, 0);
382static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0);
383
384static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv, 0, 600, 0);
385static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0);
386
387static const DECLARE_TLV_DB_SCALE(max98090_sidetone_tlv, -6050, 200, 0);
388
389static const DECLARE_TLV_DB_SCALE(max98090_alc_tlv, -1500, 100, 0);
390static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0);
391static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0);
392static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0);
393
394static const unsigned int max98090_mixout_tlv[] = {
395 TLV_DB_RANGE_HEAD(2),
396 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0),
397 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0),
398};
399
400static const unsigned int max98090_hp_tlv[] = {
401 TLV_DB_RANGE_HEAD(5),
402 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
403 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
404 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
405 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
406 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0),
407};
408
409static const unsigned int max98090_spk_tlv[] = {
410 TLV_DB_RANGE_HEAD(5),
411 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0),
412 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0),
413 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0),
414 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0),
415 30, 39, TLV_DB_SCALE_ITEM(950, 50, 0),
416};
417
418static const unsigned int max98090_rcv_lout_tlv[] = {
419 TLV_DB_RANGE_HEAD(5),
420 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
421 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
422 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
423 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
424 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0),
425};
426
427static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol,
428 struct snd_ctl_elem_value *ucontrol)
429{
430 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
431 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
432 struct soc_mixer_control *mc =
433 (struct soc_mixer_control *)kcontrol->private_value;
434 unsigned int mask = (1 << fls(mc->max)) - 1;
435 unsigned int val = snd_soc_read(codec, mc->reg);
436 unsigned int *select;
437
438 switch (mc->reg) {
439 case M98090_REG_MIC1_INPUT_LEVEL:
440 select = &(max98090->pa1en);
441 break;
442 case M98090_REG_MIC2_INPUT_LEVEL:
443 select = &(max98090->pa2en);
444 break;
445 case M98090_REG_ADC_SIDETONE:
446 select = &(max98090->sidetone);
447 break;
448 default:
449 return -EINVAL;
450 }
451
452 val = (val >> mc->shift) & mask;
453
454 if (val >= 1) {
455 /* If on, return the volume */
456 val = val - 1;
457 *select = val;
458 } else {
459 /* If off, return last stored value */
460 val = *select;
461 }
462
463 ucontrol->value.integer.value[0] = val;
464 return 0;
465}
466
467static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol,
468 struct snd_ctl_elem_value *ucontrol)
469{
470 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
471 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
472 struct soc_mixer_control *mc =
473 (struct soc_mixer_control *)kcontrol->private_value;
474 unsigned int mask = (1 << fls(mc->max)) - 1;
475 unsigned int sel = ucontrol->value.integer.value[0];
476 unsigned int val = snd_soc_read(codec, mc->reg);
477 unsigned int *select;
478
479 switch (mc->reg) {
480 case M98090_REG_MIC1_INPUT_LEVEL:
481 select = &(max98090->pa1en);
482 break;
483 case M98090_REG_MIC2_INPUT_LEVEL:
484 select = &(max98090->pa2en);
485 break;
486 case M98090_REG_ADC_SIDETONE:
487 select = &(max98090->sidetone);
488 break;
489 default:
490 return -EINVAL;
491 }
492
493 val = (val >> mc->shift) & mask;
494
495 *select = sel;
496
497 /* Setting a volume is only valid if it is already On */
498 if (val >= 1) {
499 sel = sel + 1;
500 } else {
501 /* Write what was already there */
502 sel = val;
503 }
504
505 snd_soc_update_bits(codec, mc->reg,
506 mask << mc->shift,
507 sel << mc->shift);
508
509 return 0;
510}
511
4ca74feb 512static const char *max98090_perf_pwr_text[] =
685e4215 513 { "High Performance", "Low Power" };
4ca74feb 514static const char *max98090_pwr_perf_text[] =
685e4215
JW		 515 { "Low Power", "High Performance" };
516
2907cbcc
TI		 517static SOC_ENUM_SINGLE_DECL(max98090_vcmbandgap_enum,
518 M98090_REG_BIAS_CONTROL,
519 M98090_VCM_MODE_SHIFT,
520 max98090_pwr_perf_text);
685e4215 521
4ca74feb 522static const char *max98090_osr128_text[] = { "64*fs", "128*fs" };
685e4215 523
2907cbcc
TI		 524static SOC_ENUM_SINGLE_DECL(max98090_osr128_enum,
525 M98090_REG_ADC_CONTROL,
526 M98090_OSR128_SHIFT,
527 max98090_osr128_text);
685e4215
JW		 528
529static const char *max98090_mode_text[] = { "Voice", "Music" };
530
2907cbcc
TI		 531static SOC_ENUM_SINGLE_DECL(max98090_mode_enum,
532 M98090_REG_FILTER_CONFIG,
533 M98090_MODE_SHIFT,
534 max98090_mode_text);
685e4215 535
2907cbcc
TI		 536static SOC_ENUM_SINGLE_DECL(max98090_filter_dmic34mode_enum,
537 M98090_REG_FILTER_CONFIG,
538 M98090_FLT_DMIC34MODE_SHIFT,
539 max98090_mode_text);
685e4215 540
4ca74feb 541static const char *max98090_drcatk_text[] =
685e4215
JW		 542 { "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" };
543
2907cbcc
TI		 544static SOC_ENUM_SINGLE_DECL(max98090_drcatk_enum,
545 M98090_REG_DRC_TIMING,
546 M98090_DRCATK_SHIFT,
547 max98090_drcatk_text);
685e4215 548
4ca74feb 549static const char *max98090_drcrls_text[] =
685e4215
JW		 550 { "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" };
551
2907cbcc
TI		 552static SOC_ENUM_SINGLE_DECL(max98090_drcrls_enum,
553 M98090_REG_DRC_TIMING,
554 M98090_DRCRLS_SHIFT,
555 max98090_drcrls_text);
685e4215 556
4ca74feb 557static const char *max98090_alccmp_text[] =
685e4215
JW		 558 { "1:1", "1:1.5", "1:2", "1:4", "1:INF" };
559
2907cbcc
TI		 560static SOC_ENUM_SINGLE_DECL(max98090_alccmp_enum,
561 M98090_REG_DRC_COMPRESSOR,
562 M98090_DRCCMP_SHIFT,
563 max98090_alccmp_text);
685e4215 564
4ca74feb 565static const char *max98090_drcexp_text[] = { "1:1", "2:1", "3:1" };
685e4215 566
2907cbcc
TI		 567static SOC_ENUM_SINGLE_DECL(max98090_drcexp_enum,
568 M98090_REG_DRC_EXPANDER,
569 M98090_DRCEXP_SHIFT,
570 max98090_drcexp_text);
685e4215 571
2907cbcc
TI		 572static SOC_ENUM_SINGLE_DECL(max98090_dac_perfmode_enum,
573 M98090_REG_DAC_CONTROL,
574 M98090_PERFMODE_SHIFT,
575 max98090_perf_pwr_text);
685e4215 576
2907cbcc
TI		 577static SOC_ENUM_SINGLE_DECL(max98090_dachp_enum,
578 M98090_REG_DAC_CONTROL,
579 M98090_DACHP_SHIFT,
580 max98090_pwr_perf_text);
685e4215 581
2907cbcc
TI		 582static SOC_ENUM_SINGLE_DECL(max98090_adchp_enum,
583 M98090_REG_ADC_CONTROL,
584 M98090_ADCHP_SHIFT,
585 max98090_pwr_perf_text);
685e4215
JW		 586
587static const struct snd_kcontrol_new max98090_snd_controls[] = {
588 SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum),
589
590 SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG,
591 M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0),
592
593 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
594 M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT,
595 M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv,
596 max98090_put_enab_tlv, max98090_micboost_tlv),
597
598 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
599 M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT,
600 M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv,
601 max98090_put_enab_tlv, max98090_micboost_tlv),
602
603 SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL,
604 M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1,
605 max98090_mic_tlv),
606
607 SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL,
608 M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1,
609 max98090_mic_tlv),
610
611 SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume",
612 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG135_SHIFT, 0,
613 M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv),
614
615 SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume",
616 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG246_SHIFT, 0,
617 M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv),
618
619 SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL,
620 M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1,
621 max98090_line_tlv),
622
623 SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL,
624 M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1,
625 max98090_line_tlv),
626
627 SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
628 M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0),
629 SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
630 M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0),
631
632 SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL,
633 M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0,
634 max98090_avg_tlv),
635 SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL,
636 M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0,
637 max98090_avg_tlv),
638
639 SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL,
640 M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1,
641 max98090_av_tlv),
642 SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL,
643 M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1,
644 max98090_av_tlv),
645
646 SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum),
647 SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL,
648 M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0),
649 SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum),
650
651 SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION,
652 M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0),
653 SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION,
654 M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0),
655 SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION,
656 M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0),
657 SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION,
658 M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1),
659 SOC_ENUM("Filter Mode", max98090_mode_enum),
660 SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG,
661 M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0),
662 SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG,
663 M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0),
664 SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL,
665 M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv),
666 SOC_SINGLE_EXT_TLV("Digital Sidetone Volume",
667 M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT,
668 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv,
669 max98090_put_enab_tlv, max98090_micboost_tlv),
670 SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
671 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0,
672 max98090_dvg_tlv),
673 SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
674 M98090_DV_SHIFT, M98090_DV_NUM - 1, 1,
675 max98090_dv_tlv),
676 SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105),
677 SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
678 M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0),
679 SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
680 M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0),
681 SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
682 M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0),
683 SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
684 M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1,
685 1),
686 SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
687 M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1,
688 max98090_dv_tlv),
689
690 SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING,
691 M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0),
692 SOC_ENUM("ALC Attack Time", max98090_drcatk_enum),
693 SOC_ENUM("ALC Release Time", max98090_drcrls_enum),
694 SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN,
695 M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0,
696 max98090_alcmakeup_tlv),
697 SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum),
698 SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum),
699 SOC_SINGLE_TLV("ALC Compression Threshold Volume",
700 M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT,
701 M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv),
702 SOC_SINGLE_TLV("ALC Expansion Threshold Volume",
703 M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT,
704 M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv),
705
706 SOC_ENUM("DAC HP Playback Performance Mode",
707 max98090_dac_perfmode_enum),
708 SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum),
709
710 SOC_SINGLE_TLV("Headphone Left Mixer Volume",
711 M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT,
712 M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv),
713 SOC_SINGLE_TLV("Headphone Right Mixer Volume",
714 M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT,
715 M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv),
716
717 SOC_SINGLE_TLV("Speaker Left Mixer Volume",
718 M98090_REG_SPK_CONTROL, M98090_MIXSPLG_SHIFT,
719 M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv),
720 SOC_SINGLE_TLV("Speaker Right Mixer Volume",
721 M98090_REG_SPK_CONTROL, M98090_MIXSPRG_SHIFT,
722 M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv),
723
724 SOC_SINGLE_TLV("Receiver Left Mixer Volume",
725 M98090_REG_RCV_LOUTL_CONTROL, M98090_MIXRCVLG_SHIFT,
726 M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv),
727 SOC_SINGLE_TLV("Receiver Right Mixer Volume",
728 M98090_REG_LOUTR_CONTROL, M98090_MIXRCVRG_SHIFT,
729 M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv),
730
731 SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME,
732 M98090_REG_RIGHT_HP_VOLUME, M98090_HPVOLL_SHIFT,
733 M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv),
734
735 SOC_DOUBLE_R_RANGE_TLV("Speaker Volume",
736 M98090_REG_LEFT_SPK_VOLUME, M98090_REG_RIGHT_SPK_VOLUME,
737 M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24,
738 0, max98090_spk_tlv),
739
740 SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME,
741 M98090_REG_LOUTR_VOLUME, M98090_RCVLVOL_SHIFT,
742 M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv),
743
744 SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME,
745 M98090_HPLM_SHIFT, 1, 1),
746 SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME,
747 M98090_HPRM_SHIFT, 1, 1),
748
749 SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME,
750 M98090_SPLM_SHIFT, 1, 1),
751 SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME,
752 M98090_SPRM_SHIFT, 1, 1),
753
754 SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME,
755 M98090_RCVLM_SHIFT, 1, 1),
756 SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME,
757 M98090_RCVRM_SHIFT, 1, 1),
758
759 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL,
760 M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1),
761 SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL,
762 M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1),
763 SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL,
764 M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1),
765
766 SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE, 15),
767 SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
768 M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0),
769};
770
771static const struct snd_kcontrol_new max98091_snd_controls[] = {
772
773 SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE,
774 M98090_DMIC34_ZEROPAD_SHIFT,
775 M98090_DMIC34_ZEROPAD_NUM - 1, 0),
776
777 SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum),
778 SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG,
779 M98090_FLT_DMIC34HPF_SHIFT,
780 M98090_FLT_DMIC34HPF_NUM - 1, 0),
781
782 SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME,
783 M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0,
784 max98090_avg_tlv),
785 SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME,
786 M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0,
787 max98090_avg_tlv),
788
789 SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME,
790 M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1,
791 max98090_av_tlv),
792 SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME,
793 M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1,
794 max98090_av_tlv),
795
796 SND_SOC_BYTES("DMIC34 Biquad Coefficients",
797 M98090_REG_DMIC34_BIQUAD_BASE, 15),
798 SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
799 M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0),
800
801 SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume",
802 M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT,
803 M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv),
804};
805
806static int max98090_micinput_event(struct snd_soc_dapm_widget *w,
807 struct snd_kcontrol *kcontrol, int event)
808{
809 struct snd_soc_codec *codec = w->codec;
810 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
811
812 unsigned int val = snd_soc_read(codec, w->reg);
813
814 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
815 val = (val & M98090_MIC_PA1EN_MASK) >> M98090_MIC_PA1EN_SHIFT;
816 else
817 val = (val & M98090_MIC_PA2EN_MASK) >> M98090_MIC_PA2EN_SHIFT;
818
819
820 if (val >= 1) {
821 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) {
822 max98090->pa1en = val - 1; /* Update for volatile */
823 } else {
824 max98090->pa2en = val - 1; /* Update for volatile */
825 }
826 }
827
828 switch (event) {
829 case SND_SOC_DAPM_POST_PMU:
830 /* If turning on, set to most recently selected volume */
831 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
832 val = max98090->pa1en + 1;
833 else
834 val = max98090->pa2en + 1;
835 break;
836 case SND_SOC_DAPM_POST_PMD:
837 /* If turning off, turn off */
838 val = 0;
839 break;
840 default:
841 return -EINVAL;
842 }
843
844 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
845 snd_soc_update_bits(codec, w->reg, M98090_MIC_PA1EN_MASK,
846 val << M98090_MIC_PA1EN_SHIFT);
847 else
848 snd_soc_update_bits(codec, w->reg, M98090_MIC_PA2EN_MASK,
849 val << M98090_MIC_PA2EN_SHIFT);
850
851 return 0;
852}
853
854static const char *mic1_mux_text[] = { "IN12", "IN56" };
855
2907cbcc
TI		 856static SOC_ENUM_SINGLE_DECL(mic1_mux_enum,
857 M98090_REG_INPUT_MODE,
858 M98090_EXTMIC1_SHIFT,
859 mic1_mux_text);
685e4215
JW		 860
861static const struct snd_kcontrol_new max98090_mic1_mux =
862 SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum);
863
864static const char *mic2_mux_text[] = { "IN34", "IN56" };
865
2907cbcc
TI		 866static SOC_ENUM_SINGLE_DECL(mic2_mux_enum,
867 M98090_REG_INPUT_MODE,
868 M98090_EXTMIC2_SHIFT,
869 mic2_mux_text);
685e4215
JW		 870
871static const struct snd_kcontrol_new max98090_mic2_mux =
872 SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum);
873
fd5f940f
AB		 874static const char *dmic_mux_text[] = { "ADC", "DMIC" };
875
ba513116 876static SOC_ENUM_SINGLE_VIRT_DECL(dmic_mux_enum, dmic_mux_text);
fd5f940f
AB		 877
878static const struct snd_kcontrol_new max98090_dmic_mux =
879 SOC_DAPM_ENUM_VIRT("DMIC Mux", dmic_mux_enum);
880
4ca74feb 881static const char *max98090_micpre_text[] = { "Off", "On" };
685e4215 882
2907cbcc
TI		 883static SOC_ENUM_SINGLE_DECL(max98090_pa1en_enum,
884 M98090_REG_MIC1_INPUT_LEVEL,
885 M98090_MIC_PA1EN_SHIFT,
886 max98090_micpre_text);
685e4215 887
2907cbcc
TI		 888static SOC_ENUM_SINGLE_DECL(max98090_pa2en_enum,
889 M98090_REG_MIC2_INPUT_LEVEL,
890 M98090_MIC_PA2EN_SHIFT,
891 max98090_micpre_text);
685e4215
JW		 892
893/* LINEA mixer switch */
894static const struct snd_kcontrol_new max98090_linea_mixer_controls[] = {
895 SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG,
896 M98090_IN1SEEN_SHIFT, 1, 0),
897 SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG,
898 M98090_IN3SEEN_SHIFT, 1, 0),
899 SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG,
900 M98090_IN5SEEN_SHIFT, 1, 0),
901 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG,
902 M98090_IN34DIFF_SHIFT, 1, 0),
903};
904
905/* LINEB mixer switch */
906static const struct snd_kcontrol_new max98090_lineb_mixer_controls[] = {
907 SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG,
908 M98090_IN2SEEN_SHIFT, 1, 0),
909 SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG,
910 M98090_IN4SEEN_SHIFT, 1, 0),
911 SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG,
912 M98090_IN6SEEN_SHIFT, 1, 0),
913 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG,
914 M98090_IN56DIFF_SHIFT, 1, 0),
915};
916
917/* Left ADC mixer switch */
918static const struct snd_kcontrol_new max98090_left_adc_mixer_controls[] = {
919 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER,
920 M98090_MIXADL_IN12DIFF_SHIFT, 1, 0),
921 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER,
922 M98090_MIXADL_IN34DIFF_SHIFT, 1, 0),
923 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER,
924 M98090_MIXADL_IN65DIFF_SHIFT, 1, 0),
925 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER,
926 M98090_MIXADL_LINEA_SHIFT, 1, 0),
927 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER,
928 M98090_MIXADL_LINEB_SHIFT, 1, 0),
929 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER,
930 M98090_MIXADL_MIC1_SHIFT, 1, 0),
931 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER,
932 M98090_MIXADL_MIC2_SHIFT, 1, 0),
933};
934
935/* Right ADC mixer switch */
936static const struct snd_kcontrol_new max98090_right_adc_mixer_controls[] = {
937 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER,
938 M98090_MIXADR_IN12DIFF_SHIFT, 1, 0),
939 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER,
940 M98090_MIXADR_IN34DIFF_SHIFT, 1, 0),
941 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER,
942 M98090_MIXADR_IN65DIFF_SHIFT, 1, 0),
943 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER,
944 M98090_MIXADR_LINEA_SHIFT, 1, 0),
945 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER,
946 M98090_MIXADR_LINEB_SHIFT, 1, 0),
947 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER,
948 M98090_MIXADR_MIC1_SHIFT, 1, 0),
949 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER,
950 M98090_MIXADR_MIC2_SHIFT, 1, 0),
951};
952
953static const char *lten_mux_text[] = { "Normal", "Loopthrough" };
954
2907cbcc
TI		 955static SOC_ENUM_SINGLE_DECL(ltenl_mux_enum,
956 M98090_REG_IO_CONFIGURATION,
957 M98090_LTEN_SHIFT,
958 lten_mux_text);
685e4215 959
2907cbcc
TI		 960static SOC_ENUM_SINGLE_DECL(ltenr_mux_enum,
961 M98090_REG_IO_CONFIGURATION,
962 M98090_LTEN_SHIFT,
963 lten_mux_text);
685e4215
JW		 964
965static const struct snd_kcontrol_new max98090_ltenl_mux =
966 SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum);
967
968static const struct snd_kcontrol_new max98090_ltenr_mux =
969 SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum);
970
971static const char *lben_mux_text[] = { "Normal", "Loopback" };
972
2907cbcc
TI		 973static SOC_ENUM_SINGLE_DECL(lbenl_mux_enum,
974 M98090_REG_IO_CONFIGURATION,
975 M98090_LBEN_SHIFT,
976 lben_mux_text);
685e4215 977
2907cbcc
TI		 978static SOC_ENUM_SINGLE_DECL(lbenr_mux_enum,
979 M98090_REG_IO_CONFIGURATION,
980 M98090_LBEN_SHIFT,
981 lben_mux_text);
685e4215
JW		 982
983static const struct snd_kcontrol_new max98090_lbenl_mux =
984 SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum);
985
986static const struct snd_kcontrol_new max98090_lbenr_mux =
987 SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum);
988
989static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" };
990
991static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" };
992
2907cbcc
TI		 993static SOC_ENUM_SINGLE_DECL(stenl_mux_enum,
994 M98090_REG_ADC_SIDETONE,
995 M98090_DSTSL_SHIFT,
996 stenl_mux_text);
685e4215 997
2907cbcc
TI		 998static SOC_ENUM_SINGLE_DECL(stenr_mux_enum,
999 M98090_REG_ADC_SIDETONE,
1000 M98090_DSTSR_SHIFT,
1001 stenr_mux_text);
685e4215
JW		 1002
1003static const struct snd_kcontrol_new max98090_stenl_mux =
1004 SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum);
1005
1006static const struct snd_kcontrol_new max98090_stenr_mux =
1007 SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum);
1008
1009/* Left speaker mixer switch */
1010static const struct
1011 snd_kcontrol_new max98090_left_speaker_mixer_controls[] = {
1012 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER,
1013 M98090_MIXSPL_DACL_SHIFT, 1, 0),
1014 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER,
1015 M98090_MIXSPL_DACR_SHIFT, 1, 0),
1016 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER,
1017 M98090_MIXSPL_LINEA_SHIFT, 1, 0),
1018 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER,
1019 M98090_MIXSPL_LINEB_SHIFT, 1, 0),
1020 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER,
1021 M98090_MIXSPL_MIC1_SHIFT, 1, 0),
1022 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER,
1023 M98090_MIXSPL_MIC2_SHIFT, 1, 0),
1024};
1025
1026/* Right speaker mixer switch */
1027static const struct
1028 snd_kcontrol_new max98090_right_speaker_mixer_controls[] = {
1029 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
1030 M98090_MIXSPR_DACL_SHIFT, 1, 0),
1031 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
1032 M98090_MIXSPR_DACR_SHIFT, 1, 0),
1033 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER,
1034 M98090_MIXSPR_LINEA_SHIFT, 1, 0),
1035 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER,
1036 M98090_MIXSPR_LINEB_SHIFT, 1, 0),
1037 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER,
1038 M98090_MIXSPR_MIC1_SHIFT, 1, 0),
1039 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER,
1040 M98090_MIXSPR_MIC2_SHIFT, 1, 0),
1041};
1042
1043/* Left headphone mixer switch */
1044static const struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = {
1045 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER,
1046 M98090_MIXHPL_DACL_SHIFT, 1, 0),
1047 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER,
1048 M98090_MIXHPL_DACR_SHIFT, 1, 0),
1049 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER,
1050 M98090_MIXHPL_LINEA_SHIFT, 1, 0),
1051 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER,
1052 M98090_MIXHPL_LINEB_SHIFT, 1, 0),
1053 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER,
1054 M98090_MIXHPL_MIC1_SHIFT, 1, 0),
1055 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER,
1056 M98090_MIXHPL_MIC2_SHIFT, 1, 0),
1057};
1058
1059/* Right headphone mixer switch */
1060static const struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = {
1061 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER,
1062 M98090_MIXHPR_DACL_SHIFT, 1, 0),
1063 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER,
1064 M98090_MIXHPR_DACR_SHIFT, 1, 0),
1065 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER,
1066 M98090_MIXHPR_LINEA_SHIFT, 1, 0),
1067 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER,
1068 M98090_MIXHPR_LINEB_SHIFT, 1, 0),
1069 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER,
1070 M98090_MIXHPR_MIC1_SHIFT, 1, 0),
1071 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER,
1072 M98090_MIXHPR_MIC2_SHIFT, 1, 0),
1073};
1074
1075/* Left receiver mixer switch */
1076static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls[] = {
1077 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1078 M98090_MIXRCVL_DACL_SHIFT, 1, 0),
1079 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1080 M98090_MIXRCVL_DACR_SHIFT, 1, 0),
1081 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER,
1082 M98090_MIXRCVL_LINEA_SHIFT, 1, 0),
1083 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER,
1084 M98090_MIXRCVL_LINEB_SHIFT, 1, 0),
1085 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER,
1086 M98090_MIXRCVL_MIC1_SHIFT, 1, 0),
1087 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER,
1088 M98090_MIXRCVL_MIC2_SHIFT, 1, 0),
1089};
1090
1091/* Right receiver mixer switch */
1092static const struct snd_kcontrol_new max98090_right_rcv_mixer_controls[] = {
1093 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER,
1094 M98090_MIXRCVR_DACL_SHIFT, 1, 0),
1095 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER,
1096 M98090_MIXRCVR_DACR_SHIFT, 1, 0),
1097 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER,
1098 M98090_MIXRCVR_LINEA_SHIFT, 1, 0),
1099 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER,
1100 M98090_MIXRCVR_LINEB_SHIFT, 1, 0),
1101 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER,
1102 M98090_MIXRCVR_MIC1_SHIFT, 1, 0),
1103 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER,
1104 M98090_MIXRCVR_MIC2_SHIFT, 1, 0),
1105};
1106
1107static const char *linmod_mux_text[] = { "Left Only", "Left and Right" };
1108
2907cbcc
TI		 1109static SOC_ENUM_SINGLE_DECL(linmod_mux_enum,
1110 M98090_REG_LOUTR_MIXER,
1111 M98090_LINMOD_SHIFT,
1112 linmod_mux_text);
685e4215
JW		 1113
1114static const struct snd_kcontrol_new max98090_linmod_mux =
1115 SOC_DAPM_ENUM("LINMOD Mux", linmod_mux_enum);
1116
1117static const char *mixhpsel_mux_text[] = { "DAC Only", "HP Mixer" };
1118
1119/*
1120 * This is a mux as it selects the HP output, but to DAPM it is a Mixer enable
1121 */
2907cbcc
TI		 1122static SOC_ENUM_SINGLE_DECL(mixhplsel_mux_enum,
1123 M98090_REG_HP_CONTROL,
1124 M98090_MIXHPLSEL_SHIFT,
1125 mixhpsel_mux_text);
685e4215
JW		 1126
1127static const struct snd_kcontrol_new max98090_mixhplsel_mux =
1128 SOC_DAPM_ENUM("MIXHPLSEL Mux", mixhplsel_mux_enum);
1129
2907cbcc
TI		 1130static SOC_ENUM_SINGLE_DECL(mixhprsel_mux_enum,
1131 M98090_REG_HP_CONTROL,
1132 M98090_MIXHPRSEL_SHIFT,
1133 mixhpsel_mux_text);
685e4215
JW		 1134
1135static const struct snd_kcontrol_new max98090_mixhprsel_mux =
1136 SOC_DAPM_ENUM("MIXHPRSEL Mux", mixhprsel_mux_enum);
1137
1138static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = {
1139
1140 SND_SOC_DAPM_INPUT("MIC1"),
1141 SND_SOC_DAPM_INPUT("MIC2"),
1142 SND_SOC_DAPM_INPUT("DMICL"),
1143 SND_SOC_DAPM_INPUT("DMICR"),
1144 SND_SOC_DAPM_INPUT("IN1"),
1145 SND_SOC_DAPM_INPUT("IN2"),
1146 SND_SOC_DAPM_INPUT("IN3"),
1147 SND_SOC_DAPM_INPUT("IN4"),
1148 SND_SOC_DAPM_INPUT("IN5"),
1149 SND_SOC_DAPM_INPUT("IN6"),
1150 SND_SOC_DAPM_INPUT("IN12"),
1151 SND_SOC_DAPM_INPUT("IN34"),
1152 SND_SOC_DAPM_INPUT("IN56"),
1153
1154 SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE,
1155 M98090_MBEN_SHIFT, 0, NULL, 0),
1156 SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN,
1157 M98090_SHDNN_SHIFT, 0, NULL, 0),
1158 SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION,
1159 M98090_SDIEN_SHIFT, 0, NULL, 0),
1160 SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION,
1161 M98090_SDOEN_SHIFT, 0, NULL, 0),
1162 SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1163 M98090_DIGMICL_SHIFT, 0, NULL, 0),
1164 SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1165 M98090_DIGMICR_SHIFT, 0, NULL, 0),
1166 SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG,
1167 M98090_AHPF_SHIFT, 0, NULL, 0),
1168
1169/*
1170 * Note: Sysclk and misc power supplies are taken care of by SHDN
1171 */
1172
1173 SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM,
1174 0, 0, &max98090_mic1_mux),
1175
1176 SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM,
1177 0, 0, &max98090_mic2_mux),
1178
fd5f940f
AB		 1179 SND_SOC_DAPM_VIRT_MUX("DMIC Mux", SND_SOC_NOPM,
1180 0, 0, &max98090_dmic_mux),
1181
685e4215
JW		 1182 SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL,
1183 M98090_MIC_PA1EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1184 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1185
1186 SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL,
1187 M98090_MIC_PA2EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1188 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1189
1190 SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM, 0, 0,
1191 &max98090_linea_mixer_controls[0],
1192 ARRAY_SIZE(max98090_linea_mixer_controls)),
1193
1194 SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM, 0, 0,
1195 &max98090_lineb_mixer_controls[0],
1196 ARRAY_SIZE(max98090_lineb_mixer_controls)),
1197
1198 SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE,
1199 M98090_LINEAEN_SHIFT, 0, NULL, 0),
1200 SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE,
1201 M98090_LINEBEN_SHIFT, 0, NULL, 0),
1202
1203 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
1204 &max98090_left_adc_mixer_controls[0],
1205 ARRAY_SIZE(max98090_left_adc_mixer_controls)),
1206
1207 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
1208 &max98090_right_adc_mixer_controls[0],
1209 ARRAY_SIZE(max98090_right_adc_mixer_controls)),
1210
1211 SND_SOC_DAPM_ADC("ADCL", NULL, M98090_REG_INPUT_ENABLE,
1212 M98090_ADLEN_SHIFT, 0),
1213 SND_SOC_DAPM_ADC("ADCR", NULL, M98090_REG_INPUT_ENABLE,
1214 M98090_ADREN_SHIFT, 0),
1215
1216 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0,
1217 SND_SOC_NOPM, 0, 0),
1218 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1,
1219 SND_SOC_NOPM, 0, 0),
1220
1221 SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM,
1222 0, 0, &max98090_lbenl_mux),
1223
1224 SND_SOC_DAPM_MUX("LBENR Mux", SND_SOC_NOPM,
1225 0, 0, &max98090_lbenr_mux),
1226
1227 SND_SOC_DAPM_MUX("LTENL Mux", SND_SOC_NOPM,
1228 0, 0, &max98090_ltenl_mux),
1229
1230 SND_SOC_DAPM_MUX("LTENR Mux", SND_SOC_NOPM,
1231 0, 0, &max98090_ltenr_mux),
1232
1233 SND_SOC_DAPM_MUX("STENL Mux", SND_SOC_NOPM,
1234 0, 0, &max98090_stenl_mux),
1235
1236 SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM,
1237 0, 0, &max98090_stenr_mux),
1238
1239 SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
1240 SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0),
1241
1242 SND_SOC_DAPM_DAC("DACL", NULL, M98090_REG_OUTPUT_ENABLE,
1243 M98090_DALEN_SHIFT, 0),
1244 SND_SOC_DAPM_DAC("DACR", NULL, M98090_REG_OUTPUT_ENABLE,
1245 M98090_DAREN_SHIFT, 0),
1246
1247 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
1248 &max98090_left_hp_mixer_controls[0],
1249 ARRAY_SIZE(max98090_left_hp_mixer_controls)),
1250
1251 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
1252 &max98090_right_hp_mixer_controls[0],
1253 ARRAY_SIZE(max98090_right_hp_mixer_controls)),
1254
1255 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
1256 &max98090_left_speaker_mixer_controls[0],
1257 ARRAY_SIZE(max98090_left_speaker_mixer_controls)),
1258
1259 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
1260 &max98090_right_speaker_mixer_controls[0],
1261 ARRAY_SIZE(max98090_right_speaker_mixer_controls)),
1262
1263 SND_SOC_DAPM_MIXER("Left Receiver Mixer", SND_SOC_NOPM, 0, 0,
1264 &max98090_left_rcv_mixer_controls[0],
1265 ARRAY_SIZE(max98090_left_rcv_mixer_controls)),
1266
1267 SND_SOC_DAPM_MIXER("Right Receiver Mixer", SND_SOC_NOPM, 0, 0,
1268 &max98090_right_rcv_mixer_controls[0],
1269 ARRAY_SIZE(max98090_right_rcv_mixer_controls)),
1270
1271 SND_SOC_DAPM_MUX("LINMOD Mux", M98090_REG_LOUTR_MIXER,
1272 M98090_LINMOD_SHIFT, 0, &max98090_linmod_mux),
1273
1274 SND_SOC_DAPM_MUX("MIXHPLSEL Mux", M98090_REG_HP_CONTROL,
1275 M98090_MIXHPLSEL_SHIFT, 0, &max98090_mixhplsel_mux),
1276
1277 SND_SOC_DAPM_MUX("MIXHPRSEL Mux", M98090_REG_HP_CONTROL,
1278 M98090_MIXHPRSEL_SHIFT, 0, &max98090_mixhprsel_mux),
1279
1280 SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE,
1281 M98090_HPLEN_SHIFT, 0, NULL, 0),
1282 SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE,
1283 M98090_HPREN_SHIFT, 0, NULL, 0),
1284
1285 SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE,
1286 M98090_SPLEN_SHIFT, 0, NULL, 0),
1287 SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE,
1288 M98090_SPREN_SHIFT, 0, NULL, 0),
1289
1290 SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE,
1291 M98090_RCVLEN_SHIFT, 0, NULL, 0),
1292 SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE,
1293 M98090_RCVREN_SHIFT, 0, NULL, 0),
1294
1295 SND_SOC_DAPM_OUTPUT("HPL"),
1296 SND_SOC_DAPM_OUTPUT("HPR"),
1297 SND_SOC_DAPM_OUTPUT("SPKL"),
1298 SND_SOC_DAPM_OUTPUT("SPKR"),
1299 SND_SOC_DAPM_OUTPUT("RCVL"),
1300 SND_SOC_DAPM_OUTPUT("RCVR"),
1301};
1302
1303static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = {
1304
1305 SND_SOC_DAPM_INPUT("DMIC3"),
1306 SND_SOC_DAPM_INPUT("DMIC4"),
1307
1308 SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1309 M98090_DIGMIC3_SHIFT, 0, NULL, 0),
1310 SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1311 M98090_DIGMIC4_SHIFT, 0, NULL, 0),
1312};
1313
1314static const struct snd_soc_dapm_route max98090_dapm_routes[] = {
1315
1316 {"MIC1 Input", NULL, "MIC1"},
1317 {"MIC2 Input", NULL, "MIC2"},
1318
1319 {"DMICL", NULL, "DMICL_ENA"},
1320 {"DMICR", NULL, "DMICR_ENA"},
1321 {"DMICL", NULL, "AHPF"},
1322 {"DMICR", NULL, "AHPF"},
1323
1324 /* MIC1 input mux */
1325 {"MIC1 Mux", "IN12", "IN12"},
1326 {"MIC1 Mux", "IN56", "IN56"},
1327
1328 /* MIC2 input mux */
1329 {"MIC2 Mux", "IN34", "IN34"},
1330 {"MIC2 Mux", "IN56", "IN56"},
1331
1332 {"MIC1 Input", NULL, "MIC1 Mux"},
1333 {"MIC2 Input", NULL, "MIC2 Mux"},
1334
1335 /* Left ADC input mixer */
1336 {"Left ADC Mixer", "IN12 Switch", "IN12"},
1337 {"Left ADC Mixer", "IN34 Switch", "IN34"},
1338 {"Left ADC Mixer", "IN56 Switch", "IN56"},
1339 {"Left ADC Mixer", "LINEA Switch", "LINEA Input"},
1340 {"Left ADC Mixer", "LINEB Switch", "LINEB Input"},
1341 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1342 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1343
1344 /* Right ADC input mixer */
1345 {"Right ADC Mixer", "IN12 Switch", "IN12"},
1346 {"Right ADC Mixer", "IN34 Switch", "IN34"},
1347 {"Right ADC Mixer", "IN56 Switch", "IN56"},
1348 {"Right ADC Mixer", "LINEA Switch", "LINEA Input"},
1349 {"Right ADC Mixer", "LINEB Switch", "LINEB Input"},
1350 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1351 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1352
1353 /* Line A input mixer */
1354 {"LINEA Mixer", "IN1 Switch", "IN1"},
1355 {"LINEA Mixer", "IN3 Switch", "IN3"},
1356 {"LINEA Mixer", "IN5 Switch", "IN5"},
1357 {"LINEA Mixer", "IN34 Switch", "IN34"},
1358
1359 /* Line B input mixer */
1360 {"LINEB Mixer", "IN2 Switch", "IN2"},
1361 {"LINEB Mixer", "IN4 Switch", "IN4"},
1362 {"LINEB Mixer", "IN6 Switch", "IN6"},
1363 {"LINEB Mixer", "IN56 Switch", "IN56"},
1364
1365 {"LINEA Input", NULL, "LINEA Mixer"},
1366 {"LINEB Input", NULL, "LINEB Mixer"},
1367
1368 /* Inputs */
1369 {"ADCL", NULL, "Left ADC Mixer"},
1370 {"ADCR", NULL, "Right ADC Mixer"},
1371 {"ADCL", NULL, "SHDN"},
1372 {"ADCR", NULL, "SHDN"},
1373
fd5f940f
AB		 1374 {"DMIC Mux", "ADC", "ADCL"},
1375 {"DMIC Mux", "ADC", "ADCR"},
1376 {"DMIC Mux", "DMIC", "DMICL"},
1377 {"DMIC Mux", "DMIC", "DMICR"},
1378
1379 {"LBENL Mux", "Normal", "DMIC Mux"},
685e4215 1380 {"LBENL Mux", "Loopback", "LTENL Mux"},
fd5f940f 1381 {"LBENR Mux", "Normal", "DMIC Mux"},
685e4215
JW		 1382 {"LBENR Mux", "Loopback", "LTENR Mux"},
1383
1384 {"AIFOUTL", NULL, "LBENL Mux"},
1385 {"AIFOUTR", NULL, "LBENR Mux"},
1386 {"AIFOUTL", NULL, "SHDN"},
1387 {"AIFOUTR", NULL, "SHDN"},
1388 {"AIFOUTL", NULL, "SDOEN"},
1389 {"AIFOUTR", NULL, "SDOEN"},
1390
1391 {"LTENL Mux", "Normal", "AIFINL"},
1392 {"LTENL Mux", "Loopthrough", "LBENL Mux"},
1393 {"LTENR Mux", "Normal", "AIFINR"},
1394 {"LTENR Mux", "Loopthrough", "LBENR Mux"},
1395
1396 {"DACL", NULL, "LTENL Mux"},
1397 {"DACR", NULL, "LTENR Mux"},
1398
1399 {"STENL Mux", "Sidetone Left", "ADCL"},
1400 {"STENL Mux", "Sidetone Left", "DMICL"},
1401 {"STENR Mux", "Sidetone Right", "ADCR"},
1402 {"STENR Mux", "Sidetone Right", "DMICR"},
1403 {"DACL", "NULL", "STENL Mux"},
1404 {"DACR", "NULL", "STENL Mux"},
1405
1406 {"AIFINL", NULL, "SHDN"},
1407 {"AIFINR", NULL, "SHDN"},
1408 {"AIFINL", NULL, "SDIEN"},
1409 {"AIFINR", NULL, "SDIEN"},
1410 {"DACL", NULL, "SHDN"},
1411 {"DACR", NULL, "SHDN"},
1412
1413 /* Left headphone output mixer */
1414 {"Left Headphone Mixer", "Left DAC Switch", "DACL"},
1415 {"Left Headphone Mixer", "Right DAC Switch", "DACR"},
1416 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1417 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1418 {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"},
1419 {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"},
1420
1421 /* Right headphone output mixer */
1422 {"Right Headphone Mixer", "Left DAC Switch", "DACL"},
1423 {"Right Headphone Mixer", "Right DAC Switch", "DACR"},
1424 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1425 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1426 {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"},
1427 {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"},
1428
1429 /* Left speaker output mixer */
1430 {"Left Speaker Mixer", "Left DAC Switch", "DACL"},
1431 {"Left Speaker Mixer", "Right DAC Switch", "DACR"},
1432 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1433 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1434 {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"},
1435 {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"},
1436
1437 /* Right speaker output mixer */
1438 {"Right Speaker Mixer", "Left DAC Switch", "DACL"},
1439 {"Right Speaker Mixer", "Right DAC Switch", "DACR"},
1440 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1441 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1442 {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"},
1443 {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"},
1444
1445 /* Left Receiver output mixer */
1446 {"Left Receiver Mixer", "Left DAC Switch", "DACL"},
1447 {"Left Receiver Mixer", "Right DAC Switch", "DACR"},
1448 {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1449 {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1450 {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"},
1451 {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"},
1452
1453 /* Right Receiver output mixer */
1454 {"Right Receiver Mixer", "Left DAC Switch", "DACL"},
1455 {"Right Receiver Mixer", "Right DAC Switch", "DACR"},
1456 {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1457 {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1458 {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"},
1459 {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"},
1460
1461 {"MIXHPLSEL Mux", "HP Mixer", "Left Headphone Mixer"},
1462
1463 /*
1464 * Disable this for lowest power if bypassing
1465 * the DAC with an analog signal
1466 */
1467 {"HP Left Out", NULL, "DACL"},
1468 {"HP Left Out", NULL, "MIXHPLSEL Mux"},
1469
1470 {"MIXHPRSEL Mux", "HP Mixer", "Right Headphone Mixer"},
1471
1472 /*
1473 * Disable this for lowest power if bypassing
1474 * the DAC with an analog signal
1475 */
1476 {"HP Right Out", NULL, "DACR"},
1477 {"HP Right Out", NULL, "MIXHPRSEL Mux"},
1478
1479 {"SPK Left Out", NULL, "Left Speaker Mixer"},
1480 {"SPK Right Out", NULL, "Right Speaker Mixer"},
1481 {"RCV Left Out", NULL, "Left Receiver Mixer"},
1482
1483 {"LINMOD Mux", "Left and Right", "Right Receiver Mixer"},
1484 {"LINMOD Mux", "Left Only", "Left Receiver Mixer"},
1485 {"RCV Right Out", NULL, "LINMOD Mux"},
1486
1487 {"HPL", NULL, "HP Left Out"},
1488 {"HPR", NULL, "HP Right Out"},
1489 {"SPKL", NULL, "SPK Left Out"},
1490 {"SPKR", NULL, "SPK Right Out"},
1491 {"RCVL", NULL, "RCV Left Out"},
1492 {"RCVR", NULL, "RCV Right Out"},
1493
1494};
1495
1496static const struct snd_soc_dapm_route max98091_dapm_routes[] = {
1497
1498 /* DMIC inputs */
1499 {"DMIC3", NULL, "DMIC3_ENA"},
1500 {"DMIC4", NULL, "DMIC4_ENA"},
1501 {"DMIC3", NULL, "AHPF"},
1502 {"DMIC4", NULL, "AHPF"},
1503
1504};
1505
1506static int max98090_add_widgets(struct snd_soc_codec *codec)
1507{
1508 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1509 struct snd_soc_dapm_context *dapm = &codec->dapm;
1510
1511 snd_soc_add_codec_controls(codec, max98090_snd_controls,
1512 ARRAY_SIZE(max98090_snd_controls));
1513
1514 if (max98090->devtype == MAX98091) {
1515 snd_soc_add_codec_controls(codec, max98091_snd_controls,
1516 ARRAY_SIZE(max98091_snd_controls));
1517 }
1518
1519 snd_soc_dapm_new_controls(dapm, max98090_dapm_widgets,
1520 ARRAY_SIZE(max98090_dapm_widgets));
1521
1522 snd_soc_dapm_add_routes(dapm, max98090_dapm_routes,
1523 ARRAY_SIZE(max98090_dapm_routes));
1524
1525 if (max98090->devtype == MAX98091) {
1526 snd_soc_dapm_new_controls(dapm, max98091_dapm_widgets,
1527 ARRAY_SIZE(max98091_dapm_widgets));
1528
1529 snd_soc_dapm_add_routes(dapm, max98091_dapm_routes,
1530 ARRAY_SIZE(max98091_dapm_routes));
1531
1532 }
1533
1534 return 0;
1535}
1536
1537static const int pclk_rates[] = {
1538 12000000, 12000000, 13000000, 13000000,
1539 16000000, 16000000, 19200000, 19200000
1540};
1541
1542static const int lrclk_rates[] = {
1543 8000, 16000, 8000, 16000,
1544 8000, 16000, 8000, 16000
1545};
1546
1547static const int user_pclk_rates[] = {
1548 13000000, 13000000
1549};
1550
1551static const int user_lrclk_rates[] = {
1552 44100, 48000
1553};
1554
1555static const unsigned long long ni_value[] = {
1556 3528, 768
1557};
1558
1559static const unsigned long long mi_value[] = {
1560 8125, 1625
1561};
1562
1563static void max98090_configure_bclk(struct snd_soc_codec *codec)
1564{
1565 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1566 unsigned long long ni;
1567 int i;
1568
1569 if (!max98090->sysclk) {
1570 dev_err(codec->dev, "No SYSCLK configured\n");
1571 return;
1572 }
1573
1574 if (!max98090->bclk || !max98090->lrclk) {
1575 dev_err(codec->dev, "No audio clocks configured\n");
1576 return;
1577 }
1578
1579 /* Skip configuration when operating as slave */
1580 if (!(snd_soc_read(codec, M98090_REG_MASTER_MODE) &
1581 M98090_MAS_MASK)) {
1582 return;
1583 }
1584
1585 /* Check for supported PCLK to LRCLK ratios */
1586 for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) {
1587 if ((pclk_rates[i] == max98090->sysclk) &&
1588 (lrclk_rates[i] == max98090->lrclk)) {
1589 dev_dbg(codec->dev,
1590 "Found supported PCLK to LRCLK rates 0x%x\n",
1591 i + 0x8);
1592
1593 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1594 M98090_FREQ_MASK,
1595 (i + 0x8) << M98090_FREQ_SHIFT);
1596 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1597 M98090_USE_M1_MASK, 0);
1598 return;
1599 }
1600 }
1601
1602 /* Check for user calculated MI and NI ratios */
1603 for (i = 0; i < ARRAY_SIZE(user_pclk_rates); i++) {
1604 if ((user_pclk_rates[i] == max98090->sysclk) &&
1605 (user_lrclk_rates[i] == max98090->lrclk)) {
1606 dev_dbg(codec->dev,
1607 "Found user supported PCLK to LRCLK rates\n");
1608 dev_dbg(codec->dev, "i %d ni %lld mi %lld\n",
1609 i, ni_value[i], mi_value[i]);
1610
1611 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1612 M98090_FREQ_MASK, 0);
1613 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1614 M98090_USE_M1_MASK,
1615 1 << M98090_USE_M1_SHIFT);
1616
1617 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB,
1618 (ni_value[i] >> 8) & 0x7F);
1619 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB,
1620 ni_value[i] & 0xFF);
1621 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_MSB,
1622 (mi_value[i] >> 8) & 0x7F);
1623 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_LSB,
1624 mi_value[i] & 0xFF);
1625
1626 return;
1627 }
1628 }
1629
1630 /*
1631 * Calculate based on MI = 65536 (not as good as either method above)
1632 */
1633 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1634 M98090_FREQ_MASK, 0);
1635 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1636 M98090_USE_M1_MASK, 0);
1637
1638 /*
1639 * Configure NI when operating as master
1640 * Note: There is a small, but significant audio quality improvement
1641 * by calculating ni and mi.
1642 */
1643 ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL)
1644 * (unsigned long long int)max98090->lrclk;
1645 do_div(ni, (unsigned long long int)max98090->sysclk);
1646 dev_info(codec->dev, "No better method found\n");
1647 dev_info(codec->dev, "Calculating ni %lld with mi 65536\n", ni);
1648 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB,
1649 (ni >> 8) & 0x7F);
1650 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB, ni & 0xFF);
1651}
1652
1653static int max98090_dai_set_fmt(struct snd_soc_dai *codec_dai,
1654 unsigned int fmt)
1655{
1656 struct snd_soc_codec *codec = codec_dai->codec;
1657 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1658 struct max98090_cdata *cdata;
1659 u8 regval;
1660
1661 max98090->dai_fmt = fmt;
1662 cdata = &max98090->dai[0];
1663
1664 if (fmt != cdata->fmt) {
1665 cdata->fmt = fmt;
1666
1667 regval = 0;
1668 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1669 case SND_SOC_DAIFMT_CBS_CFS:
1670 /* Set to slave mode PLL - MAS mode off */
1671 snd_soc_write(codec,
1672 M98090_REG_CLOCK_RATIO_NI_MSB, 0x00);
1673 snd_soc_write(codec,
1674 M98090_REG_CLOCK_RATIO_NI_LSB, 0x00);
1675 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1676 M98090_USE_M1_MASK, 0);
1677 break;
1678 case SND_SOC_DAIFMT_CBM_CFM:
1679 /* Set to master mode */
1680 if (max98090->tdm_slots == 4) {
1681 /* TDM */
1682 regval |= M98090_MAS_MASK |
1683 M98090_BSEL_64;
1684 } else if (max98090->tdm_slots == 3) {
1685 /* TDM */
1686 regval |= M98090_MAS_MASK |
1687 M98090_BSEL_48;
1688 } else {
1689 /* Few TDM slots, or No TDM */
1690 regval |= M98090_MAS_MASK |
1691 M98090_BSEL_32;
1692 }
1693 break;
1694 case SND_SOC_DAIFMT_CBS_CFM:
1695 case SND_SOC_DAIFMT_CBM_CFS:
1696 default:
1697 dev_err(codec->dev, "DAI clock mode unsupported");
1698 return -EINVAL;
1699 }
1700 snd_soc_write(codec, M98090_REG_MASTER_MODE, regval);
1701
1702 regval = 0;
1703 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1704 case SND_SOC_DAIFMT_I2S:
1705 regval |= M98090_DLY_MASK;
1706 break;
1707 case SND_SOC_DAIFMT_LEFT_J:
1708 break;
1709 case SND_SOC_DAIFMT_RIGHT_J:
1710 regval |= M98090_RJ_MASK;
1711 break;
1712 case SND_SOC_DAIFMT_DSP_A:
1713 /* Not supported mode */
1714 default:
1715 dev_err(codec->dev, "DAI format unsupported");
1716 return -EINVAL;
1717 }
1718
1719 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1720 case SND_SOC_DAIFMT_NB_NF:
1721 break;
1722 case SND_SOC_DAIFMT_NB_IF:
1723 regval |= M98090_WCI_MASK;
1724 break;
1725 case SND_SOC_DAIFMT_IB_NF:
1726 regval |= M98090_BCI_MASK;
1727 break;
1728 case SND_SOC_DAIFMT_IB_IF:
1729 regval |= M98090_BCI_MASK|M98090_WCI_MASK;
1730 break;
1731 default:
1732 dev_err(codec->dev, "DAI invert mode unsupported");
1733 return -EINVAL;
1734 }
1735
1736 /*
1737 * This accommodates an inverted logic in the MAX98090 chip
1738 * for Bit Clock Invert (BCI). The inverted logic is only
1739 * seen for the case of TDM mode. The remaining cases have
1740 * normal logic.
1741 */
959b6250 1742 if (max98090->tdm_slots > 1)
685e4215 1743 regval ^= M98090_BCI_MASK;
685e4215
JW		 1744
1745 snd_soc_write(codec,
1746 M98090_REG_INTERFACE_FORMAT, regval);
1747 }
1748
1749 return 0;
1750}
1751
1752static int max98090_set_tdm_slot(struct snd_soc_dai *codec_dai,
1753 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1754{
1755 struct snd_soc_codec *codec = codec_dai->codec;
1756 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1757 struct max98090_cdata *cdata;
1758 cdata = &max98090->dai[0];
1759
1760 if (slots < 0 || slots > 4)
1761 return -EINVAL;
1762
1763 max98090->tdm_slots = slots;
1764 max98090->tdm_width = slot_width;
1765
1766 if (max98090->tdm_slots > 1) {
1767 /* SLOTL SLOTR SLOTDLY */
1768 snd_soc_write(codec, M98090_REG_TDM_FORMAT,
1769 0 << M98090_TDM_SLOTL_SHIFT |
1770 1 << M98090_TDM_SLOTR_SHIFT |
1771 0 << M98090_TDM_SLOTDLY_SHIFT);
1772
1773 /* FSW TDM */
1774 snd_soc_update_bits(codec, M98090_REG_TDM_CONTROL,
1775 M98090_TDM_MASK,
1776 M98090_TDM_MASK);
1777 }
1778
1779 /*
1780 * Normally advisable to set TDM first, but this permits either order
1781 */
1782 cdata->fmt = 0;
1783 max98090_dai_set_fmt(codec_dai, max98090->dai_fmt);
1784
1785 return 0;
1786}
1787
1788static int max98090_set_bias_level(struct snd_soc_codec *codec,
1789 enum snd_soc_bias_level level)
1790{
1791 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1792 int ret;
1793
1794 switch (level) {
1795 case SND_SOC_BIAS_ON:
685e4215
JW		 1796 if (max98090->jack_state == M98090_JACK_STATE_HEADSET) {
1797 /*
1798 * Set to normal bias level.
1799 */
1800 snd_soc_update_bits(codec, M98090_REG_MIC_BIAS_VOLTAGE,
1801 M98090_MBVSEL_MASK, M98090_MBVSEL_2V8);
1802 }
1803 break;
1804
1805 case SND_SOC_BIAS_PREPARE:
1806 break;
1807
1808 case SND_SOC_BIAS_STANDBY:
c42c8922
DR		 1809 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1810 ret = regcache_sync(max98090->regmap);
1811 if (ret != 0) {
1812 dev_err(codec->dev,
1813 "Failed to sync cache: %d\n", ret);
1814 return ret;
1815 }
1816 }
1817 break;
1818
685e4215
JW		 1819 case SND_SOC_BIAS_OFF:
1820 /* Set internal pull-up to lowest power mode */
1821 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
1822 M98090_JDWK_MASK, M98090_JDWK_MASK);
1823 regcache_mark_dirty(max98090->regmap);
1824 break;
1825 }
1826 codec->dapm.bias_level = level;
1827 return 0;
1828}
1829
1830static const int comp_pclk_rates[] = {
1831 11289600, 12288000, 12000000, 13000000, 19200000
1832};
1833
1834static const int dmic_micclk[] = {
1835 2, 2, 2, 2, 4, 2
1836};
1837
1838static const int comp_lrclk_rates[] = {
1839 8000, 16000, 32000, 44100, 48000, 96000
1840};
1841
1842static const int dmic_comp[6][6] = {
1843 {7, 8, 3, 3, 3, 3},
1844 {7, 8, 3, 3, 3, 3},
1845 {7, 8, 3, 3, 3, 3},
1846 {7, 8, 3, 1, 1, 1},
1847 {7, 8, 3, 1, 2, 2},
1848 {7, 8, 3, 3, 3, 3}
1849};
1850
1851static int max98090_dai_hw_params(struct snd_pcm_substream *substream,
1852 struct snd_pcm_hw_params *params,
1853 struct snd_soc_dai *dai)
1854{
1855 struct snd_soc_codec *codec = dai->codec;
1856 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1857 struct max98090_cdata *cdata;
1858 int i, j;
1859
1860 cdata = &max98090->dai[0];
1861 max98090->bclk = snd_soc_params_to_bclk(params);
1862 if (params_channels(params) == 1)
1863 max98090->bclk *= 2;
1864
1865 max98090->lrclk = params_rate(params);
1866
7821afc4
MB		 1867 switch (params_width(params)) {
1868 case 16:
685e4215
JW		 1869 snd_soc_update_bits(codec, M98090_REG_INTERFACE_FORMAT,
1870 M98090_WS_MASK, 0);
1871 break;
1872 default:
1873 return -EINVAL;
1874 }
1875
1876 max98090_configure_bclk(codec);
1877
1878 cdata->rate = max98090->lrclk;
1879
1880 /* Update filter mode */
1881 if (max98090->lrclk < 24000)
1882 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1883 M98090_MODE_MASK, 0);
1884 else
1885 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1886 M98090_MODE_MASK, M98090_MODE_MASK);
1887
1888 /* Update sample rate mode */
1889 if (max98090->lrclk < 50000)
1890 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1891 M98090_DHF_MASK, 0);
1892 else
1893 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1894 M98090_DHF_MASK, M98090_DHF_MASK);
1895
1896 /* Check for supported PCLK to LRCLK ratios */
1897 for (j = 0; j < ARRAY_SIZE(comp_pclk_rates); j++) {
1898 if (comp_pclk_rates[j] == max98090->sysclk) {
1899 break;
1900 }
1901 }
1902
1903 for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) {
1904 if (max98090->lrclk <= (comp_lrclk_rates[i] +
1905 comp_lrclk_rates[i + 1]) / 2) {
1906 break;
1907 }
1908 }
1909
1910 snd_soc_update_bits(codec, M98090_REG_DIGITAL_MIC_ENABLE,
1911 M98090_MICCLK_MASK,
1912 dmic_micclk[j] << M98090_MICCLK_SHIFT);
1913
1914 snd_soc_update_bits(codec, M98090_REG_DIGITAL_MIC_CONFIG,
1915 M98090_DMIC_COMP_MASK,
1916 dmic_comp[j][i] << M98090_DMIC_COMP_SHIFT);
1917
1918 return 0;
1919}
1920
1921/*
1922 * PLL / Sysclk
1923 */
1924static int max98090_dai_set_sysclk(struct snd_soc_dai *dai,
1925 int clk_id, unsigned int freq, int dir)
1926{
1927 struct snd_soc_codec *codec = dai->codec;
1928 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1929
1930 /* Requested clock frequency is already setup */
1931 if (freq == max98090->sysclk)
1932 return 0;
1933
1934 /* Setup clocks for slave mode, and using the PLL
1935 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
1936 * 0x02 (when master clk is 20MHz to 40MHz)..
1937 * 0x03 (when master clk is 40MHz to 60MHz)..
1938 */
1939 if ((freq >= 10000000) && (freq < 20000000)) {
1940 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
1941 M98090_PSCLK_DIV1);
1942 } else if ((freq >= 20000000) && (freq < 40000000)) {
1943 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
1944 M98090_PSCLK_DIV2);
1945 } else if ((freq >= 40000000) && (freq < 60000000)) {
1946 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
1947 M98090_PSCLK_DIV4);
1948 } else {
1949 dev_err(codec->dev, "Invalid master clock frequency\n");
1950 return -EINVAL;
1951 }
1952
1953 max98090->sysclk = freq;
1954
1955 max98090_configure_bclk(codec);
1956
1957 return 0;
1958}
1959
1960static int max98090_dai_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1961{
1962 struct snd_soc_codec *codec = codec_dai->codec;
1963 int regval;
1964
1965 regval = mute ? M98090_DVM_MASK : 0;
1966 snd_soc_update_bits(codec, M98090_REG_DAI_PLAYBACK_LEVEL,
1967 M98090_DVM_MASK, regval);
1968
1969 return 0;
1970}
1971
1972static void max98090_jack_work(struct work_struct *work)
1973{
1974 struct max98090_priv *max98090 = container_of(work,
1975 struct max98090_priv,
1976 jack_work.work);
1977 struct snd_soc_codec *codec = max98090->codec;
1978 struct snd_soc_dapm_context *dapm = &codec->dapm;
1979 int status = 0;
1980 int reg;
1981
1982 /* Read a second time */
1983 if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) {
1984
1985 /* Strong pull up allows mic detection */
1986 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
1987 M98090_JDWK_MASK, 0);
1988
1989 msleep(50);
1990
1991 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
1992
1993 /* Weak pull up allows only insertion detection */
1994 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
1995 M98090_JDWK_MASK, M98090_JDWK_MASK);
1996 } else {
1997 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
1998 }
1999
2000 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
2001
2002 switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) {
2003 case M98090_LSNS_MASK | M98090_JKSNS_MASK:
2004 dev_dbg(codec->dev, "No Headset Detected\n");
2005
2006 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
2007
2008 status |= 0;
2009
2010 break;
2011
2012 case 0:
2013 if (max98090->jack_state ==
2014 M98090_JACK_STATE_HEADSET) {
2015
2016 dev_dbg(codec->dev,
2017 "Headset Button Down Detected\n");
2018
2019 /*
2020 * max98090_headset_button_event(codec)
2021 * could be defined, then called here.
2022 */
2023
2024 status |= SND_JACK_HEADSET;
2025 status |= SND_JACK_BTN_0;
2026
2027 break;
2028 }
2029
2030 /* Line is reported as Headphone */
2031 /* Nokia Headset is reported as Headphone */
2032 /* Mono Headphone is reported as Headphone */
2033 dev_dbg(codec->dev, "Headphone Detected\n");
2034
2035 max98090->jack_state = M98090_JACK_STATE_HEADPHONE;
2036
2037 status |= SND_JACK_HEADPHONE;
2038
2039 break;
2040
2041 case M98090_JKSNS_MASK:
2042 dev_dbg(codec->dev, "Headset Detected\n");
2043
2044 max98090->jack_state = M98090_JACK_STATE_HEADSET;
2045
2046 status |= SND_JACK_HEADSET;
2047
2048 break;
2049
2050 default:
2051 dev_dbg(codec->dev, "Unrecognized Jack Status\n");
2052 break;
2053 }
2054
2055 snd_soc_jack_report(max98090->jack, status,
2056 SND_JACK_HEADSET | SND_JACK_BTN_0);
2057
2058 snd_soc_dapm_sync(dapm);
2059}
2060
2061static irqreturn_t max98090_interrupt(int irq, void *data)
2062{
2063 struct snd_soc_codec *codec = data;
2064 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2065 int ret;
2066 unsigned int mask;
2067 unsigned int active;
2068
2069 dev_dbg(codec->dev, "***** max98090_interrupt *****\n");
2070
2071 ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
2072
2073 if (ret != 0) {
2074 dev_err(codec->dev,
2075 "failed to read M98090_REG_INTERRUPT_S: %d\n",
2076 ret);
2077 return IRQ_NONE;
2078 }
2079
2080 ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active);
2081
2082 if (ret != 0) {
2083 dev_err(codec->dev,
2084 "failed to read M98090_REG_DEVICE_STATUS: %d\n",
2085 ret);
2086 return IRQ_NONE;
2087 }
2088
2089 dev_dbg(codec->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n",
2090 active, mask, active & mask);
2091
2092 active &= mask;
2093
2094 if (!active)
2095 return IRQ_NONE;
2096
959b6250 2097 if (active & M98090_CLD_MASK)
685e4215 2098 dev_err(codec->dev, "M98090_CLD_MASK\n");
685e4215 2099
959b6250 2100 if (active & M98090_SLD_MASK)
685e4215 2101 dev_dbg(codec->dev, "M98090_SLD_MASK\n");
685e4215 2102
959b6250 2103 if (active & M98090_ULK_MASK)
685e4215 2104 dev_err(codec->dev, "M98090_ULK_MASK\n");
685e4215
JW		 2105
2106 if (active & M98090_JDET_MASK) {
2107 dev_dbg(codec->dev, "M98090_JDET_MASK\n");
2108
2109 pm_wakeup_event(codec->dev, 100);
2110
2df7c6aa
MB		 2111 queue_delayed_work(system_power_efficient_wq,
2112 &max98090->jack_work,
2113 msecs_to_jiffies(100));
685e4215
JW		 2114 }
2115
959b6250 2116 if (active & M98090_DRCACT_MASK)
685e4215 2117 dev_dbg(codec->dev, "M98090_DRCACT_MASK\n");
685e4215 2118
959b6250 2119 if (active & M98090_DRCCLP_MASK)
685e4215 2120 dev_err(codec->dev, "M98090_DRCCLP_MASK\n");
685e4215
JW		 2121
2122 return IRQ_HANDLED;
2123}
2124
2125/**
2126 * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ
2127 *
2128 * @codec: MAX98090 codec
2129 * @jack: jack to report detection events on
2130 *
2131 * Enable microphone detection via IRQ on the MAX98090. If GPIOs are
2132 * being used to bring out signals to the processor then only platform
2133 * data configuration is needed for MAX98090 and processor GPIOs should
2134 * be configured using snd_soc_jack_add_gpios() instead.
2135 *
2136 * If no jack is supplied detection will be disabled.
2137 */
2138int max98090_mic_detect(struct snd_soc_codec *codec,
2139 struct snd_soc_jack *jack)
2140{
2141 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2142
2143 dev_dbg(codec->dev, "max98090_mic_detect\n");
2144
2145 max98090->jack = jack;
2146 if (jack) {
2147 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2148 M98090_IJDET_MASK,
2149 1 << M98090_IJDET_SHIFT);
2150 } else {
2151 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2152 M98090_IJDET_MASK,
2153 0);
2154 }
2155
2156 /* Send an initial empty report */
2157 snd_soc_jack_report(max98090->jack, 0,
2158 SND_JACK_HEADSET | SND_JACK_BTN_0);
2159
2df7c6aa
MB		 2160 queue_delayed_work(system_power_efficient_wq,
2161 &max98090->jack_work,
2162 msecs_to_jiffies(100));
685e4215
JW		 2163
2164 return 0;
2165}
2166EXPORT_SYMBOL_GPL(max98090_mic_detect);
2167
2168#define MAX98090_RATES SNDRV_PCM_RATE_8000_96000
2169#define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
2170
2171static struct snd_soc_dai_ops max98090_dai_ops = {
2172 .set_sysclk = max98090_dai_set_sysclk,
2173 .set_fmt = max98090_dai_set_fmt,
2174 .set_tdm_slot = max98090_set_tdm_slot,
2175 .hw_params = max98090_dai_hw_params,
2176 .digital_mute = max98090_dai_digital_mute,
2177};
2178
2179static struct snd_soc_dai_driver max98090_dai[] = {
2180{
2181 .name = "HiFi",
2182 .playback = {
2183 .stream_name = "HiFi Playback",
2184 .channels_min = 2,
2185 .channels_max = 2,
2186 .rates = MAX98090_RATES,
2187 .formats = MAX98090_FORMATS,
2188 },
2189 .capture = {
2190 .stream_name = "HiFi Capture",
2191 .channels_min = 1,
2192 .channels_max = 2,
2193 .rates = MAX98090_RATES,
2194 .formats = MAX98090_FORMATS,
2195 },
2196 .ops = &max98090_dai_ops,
2197}
2198};
2199
2200static void max98090_handle_pdata(struct snd_soc_codec *codec)
2201{
2202 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2203 struct max98090_pdata *pdata = max98090->pdata;
2204
2205 if (!pdata) {
2206 dev_err(codec->dev, "No platform data\n");
2207 return;
2208 }
2209
2210}
2211
2212static int max98090_probe(struct snd_soc_codec *codec)
2213{
2214 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2215 struct max98090_cdata *cdata;
2216 int ret = 0;
2217
2218 dev_dbg(codec->dev, "max98090_probe\n");
2219
2220 max98090->codec = codec;
2221
685e4215
JW		 2222 /* Reset the codec, the DSP core, and disable all interrupts */
2223 max98090_reset(max98090);
2224
2225 /* Initialize private data */
2226
2227 max98090->sysclk = (unsigned)-1;
2228
2229 cdata = &max98090->dai[0];
2230 cdata->rate = (unsigned)-1;
2231 cdata->fmt = (unsigned)-1;
2232
2233 max98090->lin_state = 0;
2234 max98090->pa1en = 0;
2235 max98090->pa2en = 0;
2236 max98090->extmic_mux = 0;
2237
2238 ret = snd_soc_read(codec, M98090_REG_REVISION_ID);
2239 if (ret < 0) {
2240 dev_err(codec->dev, "Failed to read device revision: %d\n",
2241 ret);
2242 goto err_access;
2243 }
2244
2245 if ((ret >= M98090_REVA) && (ret <= M98090_REVA + 0x0f)) {
2246 max98090->devtype = MAX98090;
2247 dev_info(codec->dev, "MAX98090 REVID=0x%02x\n", ret);
2248 } else if ((ret >= M98091_REVA) && (ret <= M98091_REVA + 0x0f)) {
2249 max98090->devtype = MAX98091;
2250 dev_info(codec->dev, "MAX98091 REVID=0x%02x\n", ret);
2251 } else {
2252 max98090->devtype = MAX98090;
2253 dev_err(codec->dev, "Unrecognized revision 0x%02x\n", ret);
2254 }
2255
2256 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
2257
2258 INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work);
2259
2260 /* Enable jack detection */
2261 snd_soc_write(codec, M98090_REG_JACK_DETECT,
2262 M98090_JDETEN_MASK | M98090_JDEB_25MS);
2263
2264 /* Register for interrupts */
2265 dev_dbg(codec->dev, "irq = %d\n", max98090->irq);
2266
2267 ret = request_threaded_irq(max98090->irq, NULL,
3d15aacb 2268 max98090_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
685e4215
JW		 2269 "max98090_interrupt", codec);
2270 if (ret < 0) {
2271 dev_err(codec->dev, "request_irq failed: %d\n",
2272 ret);
2273 }
2274
2275 /*
2276 * Clear any old interrupts.
2277 * An old interrupt ocurring prior to installing the ISR
2278 * can keep a new interrupt from generating a trigger.
2279 */
2280 snd_soc_read(codec, M98090_REG_DEVICE_STATUS);
2281
2282 /* High Performance is default */
2283 snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL,
2284 M98090_DACHP_MASK,
2285 1 << M98090_DACHP_SHIFT);
2286 snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL,
2287 M98090_PERFMODE_MASK,
2288 0 << M98090_PERFMODE_SHIFT);
2289 snd_soc_update_bits(codec, M98090_REG_ADC_CONTROL,
2290 M98090_ADCHP_MASK,
2291 1 << M98090_ADCHP_SHIFT);
2292
2293 /* Turn on VCM bandgap reference */
2294 snd_soc_write(codec, M98090_REG_BIAS_CONTROL,
2295 M98090_VCM_MODE_MASK);
2296
2297 max98090_handle_pdata(codec);
2298
2299 max98090_add_widgets(codec);
2300
2301err_access:
2302 return ret;
2303}
2304
2305static int max98090_remove(struct snd_soc_codec *codec)
2306{
2307 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2308
2309 cancel_delayed_work_sync(&max98090->jack_work);
2310
2311 return 0;
2312}
2313
2314static struct snd_soc_codec_driver soc_codec_dev_max98090 = {
2315 .probe = max98090_probe,
2316 .remove = max98090_remove,
2317 .set_bias_level = max98090_set_bias_level,
2318};
2319
2320static const struct regmap_config max98090_regmap = {
2321 .reg_bits = 8,
2322 .val_bits = 8,
2323
2324 .max_register = MAX98090_MAX_REGISTER,
2325 .reg_defaults = max98090_reg,
2326 .num_reg_defaults = ARRAY_SIZE(max98090_reg),
2327 .volatile_reg = max98090_volatile_register,
2328 .readable_reg = max98090_readable_register,
2329 .cache_type = REGCACHE_RBTREE,
2330};
2331
2332static int max98090_i2c_probe(struct i2c_client *i2c,
70f29d38 2333 const struct i2c_device_id *i2c_id)
685e4215
JW		 2334{
2335 struct max98090_priv *max98090;
70f29d38
JN		 2336 const struct acpi_device_id *acpi_id;
2337 kernel_ulong_t driver_data = 0;
685e4215
JW		 2338 int ret;
2339
2340 pr_debug("max98090_i2c_probe\n");
2341
2342 max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv),
2343 GFP_KERNEL);
2344 if (max98090 == NULL)
2345 return -ENOMEM;
2346
70f29d38
JN		 2347 if (ACPI_HANDLE(&i2c->dev)) {
2348 acpi_id = acpi_match_device(i2c->dev.driver->acpi_match_table,
2349 &i2c->dev);
2350 if (!acpi_id) {
2351 dev_err(&i2c->dev, "No driver data\n");
2352 return -EINVAL;
2353 }
2354 driver_data = acpi_id->driver_data;
2355 } else if (i2c_id) {
2356 driver_data = i2c_id->driver_data;
2357 }
2358
2359 max98090->devtype = driver_data;
685e4215 2360 i2c_set_clientdata(i2c, max98090);
685e4215
JW		 2361 max98090->pdata = i2c->dev.platform_data;
2362 max98090->irq = i2c->irq;
2363
a3a6cc84 2364 max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap);
685e4215
JW		 2365 if (IS_ERR(max98090->regmap)) {
2366 ret = PTR_ERR(max98090->regmap);
2367 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
2368 goto err_enable;
2369 }
2370
2371 ret = snd_soc_register_codec(&i2c->dev,
2372 &soc_codec_dev_max98090, max98090_dai,
2373 ARRAY_SIZE(max98090_dai));
685e4215
JW		 2374err_enable:
2375 return ret;
2376}
2377
2378static int max98090_i2c_remove(struct i2c_client *client)
2379{
685e4215 2380 snd_soc_unregister_codec(&client->dev);
685e4215
JW		 2381 return 0;
2382}
2383
3722dc8e 2384#ifdef CONFIG_PM_RUNTIME
685e4215
JW		 2385static int max98090_runtime_resume(struct device *dev)
2386{
2387 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2388
2389 regcache_cache_only(max98090->regmap, false);
2390
2391 regcache_sync(max98090->regmap);
2392
2393 return 0;
2394}
2395
2396static int max98090_runtime_suspend(struct device *dev)
2397{
2398 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2399
2400 regcache_cache_only(max98090->regmap, true);
2401
2402 return 0;
2403}
3722dc8e 2404#endif
685e4215 2405
3e12af7e 2406static const struct dev_pm_ops max98090_pm = {
685e4215
JW		 2407 SET_RUNTIME_PM_OPS(max98090_runtime_suspend,
2408 max98090_runtime_resume, NULL)
2409};
2410
2411static const struct i2c_device_id max98090_i2c_id[] = {
2412 { "max98090", MAX98090 },
2413 { }
2414};
2415MODULE_DEVICE_TABLE(i2c, max98090_i2c_id);
2416
2951f93f
SW		 2417static const struct of_device_id max98090_of_match[] = {
2418 { .compatible = "maxim,max98090", },
2419 { }
2420};
2421MODULE_DEVICE_TABLE(of, max98090_of_match);
2422
70f29d38
JN		 2423#ifdef CONFIG_ACPI
2424static struct acpi_device_id max98090_acpi_match[] = {
2425 { "193C9890", MAX98090 },
2426 { }
2427};
2428MODULE_DEVICE_TABLE(acpi, max98090_acpi_match);
2429#endif
2430
685e4215
JW		 2431static struct i2c_driver max98090_i2c_driver = {
2432 .driver = {
2433 .name = "max98090",
2434 .owner = THIS_MODULE,
2435 .pm = &max98090_pm,
2951f93f 2436 .of_match_table = of_match_ptr(max98090_of_match),
70f29d38 2437 .acpi_match_table = ACPI_PTR(max98090_acpi_match),
685e4215
JW		 2438 },
2439 .probe = max98090_i2c_probe,
2440 .remove = max98090_i2c_remove,
2441 .id_table = max98090_i2c_id,
2442};
2443
2444module_i2c_driver(max98090_i2c_driver);
2445
2446MODULE_DESCRIPTION("ALSA SoC MAX98090 driver");
2447MODULE_AUTHOR("Peter Hsiang, Jesse Marroqin, Jerry Wong");
2448MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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