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ASoC: max98090: Different comp tables for different pclks
[deliverable/linux.git] / sound / soc / codecs / max98090.c
CommitLineData
685e4215
JW		 1/*
2 * max98090.c -- MAX98090 ALSA SoC Audio driver
3 *
4 * Copyright 2011-2012 Maxim Integrated Products
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/delay.h>
12#include <linux/i2c.h>
13#include <linux/module.h>
6e1f29d4 14#include <linux/of.h>
685e4215
JW		 15#include <linux/pm.h>
16#include <linux/pm_runtime.h>
17#include <linux/regmap.h>
18#include <linux/slab.h>
70f29d38 19#include <linux/acpi.h>
b10ab7b8 20#include <linux/clk.h>
685e4215
JW		 21#include <sound/jack.h>
22#include <sound/pcm.h>
23#include <sound/pcm_params.h>
24#include <sound/soc.h>
25#include <sound/tlv.h>
26#include <sound/max98090.h>
27#include "max98090.h"
28
685e4215
JW		 29/* Allows for sparsely populated register maps */
30static struct reg_default max98090_reg[] = {
31 { 0x00, 0x00 }, /* 00 Software Reset */
32 { 0x03, 0x04 }, /* 03 Interrupt Masks */
33 { 0x04, 0x00 }, /* 04 System Clock Quick */
34 { 0x05, 0x00 }, /* 05 Sample Rate Quick */
35 { 0x06, 0x00 }, /* 06 DAI Interface Quick */
36 { 0x07, 0x00 }, /* 07 DAC Path Quick */
37 { 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */
38 { 0x09, 0x00 }, /* 09 Line to ADC Quick */
39 { 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */
40 { 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */
41 { 0x0C, 0x00 }, /* 0C Reserved */
42 { 0x0D, 0x00 }, /* 0D Input Config */
43 { 0x0E, 0x1B }, /* 0E Line Input Level */
44 { 0x0F, 0x00 }, /* 0F Line Config */
45
46 { 0x10, 0x14 }, /* 10 Mic1 Input Level */
47 { 0x11, 0x14 }, /* 11 Mic2 Input Level */
48 { 0x12, 0x00 }, /* 12 Mic Bias Voltage */
49 { 0x13, 0x00 }, /* 13 Digital Mic Config */
50 { 0x14, 0x00 }, /* 14 Digital Mic Mode */
51 { 0x15, 0x00 }, /* 15 Left ADC Mixer */
52 { 0x16, 0x00 }, /* 16 Right ADC Mixer */
53 { 0x17, 0x03 }, /* 17 Left ADC Level */
54 { 0x18, 0x03 }, /* 18 Right ADC Level */
55 { 0x19, 0x00 }, /* 19 ADC Biquad Level */
56 { 0x1A, 0x00 }, /* 1A ADC Sidetone */
57 { 0x1B, 0x00 }, /* 1B System Clock */
58 { 0x1C, 0x00 }, /* 1C Clock Mode */
59 { 0x1D, 0x00 }, /* 1D Any Clock 1 */
60 { 0x1E, 0x00 }, /* 1E Any Clock 2 */
61 { 0x1F, 0x00 }, /* 1F Any Clock 3 */
62
63 { 0x20, 0x00 }, /* 20 Any Clock 4 */
64 { 0x21, 0x00 }, /* 21 Master Mode */
65 { 0x22, 0x00 }, /* 22 Interface Format */
66 { 0x23, 0x00 }, /* 23 TDM Format 1*/
67 { 0x24, 0x00 }, /* 24 TDM Format 2*/
68 { 0x25, 0x00 }, /* 25 I/O Configuration */
69 { 0x26, 0x80 }, /* 26 Filter Config */
70 { 0x27, 0x00 }, /* 27 DAI Playback Level */
71 { 0x28, 0x00 }, /* 28 EQ Playback Level */
72 { 0x29, 0x00 }, /* 29 Left HP Mixer */
73 { 0x2A, 0x00 }, /* 2A Right HP Mixer */
74 { 0x2B, 0x00 }, /* 2B HP Control */
75 { 0x2C, 0x1A }, /* 2C Left HP Volume */
76 { 0x2D, 0x1A }, /* 2D Right HP Volume */
77 { 0x2E, 0x00 }, /* 2E Left Spk Mixer */
78 { 0x2F, 0x00 }, /* 2F Right Spk Mixer */
79
80 { 0x30, 0x00 }, /* 30 Spk Control */
81 { 0x31, 0x2C }, /* 31 Left Spk Volume */
82 { 0x32, 0x2C }, /* 32 Right Spk Volume */
83 { 0x33, 0x00 }, /* 33 ALC Timing */
84 { 0x34, 0x00 }, /* 34 ALC Compressor */
85 { 0x35, 0x00 }, /* 35 ALC Expander */
86 { 0x36, 0x00 }, /* 36 ALC Gain */
87 { 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */
88 { 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */
89 { 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */
90 { 0x3A, 0x00 }, /* 3A Line OutR Mixer */
91 { 0x3B, 0x00 }, /* 3B Line OutR Control */
92 { 0x3C, 0x15 }, /* 3C Line OutR Volume */
93 { 0x3D, 0x00 }, /* 3D Jack Detect */
94 { 0x3E, 0x00 }, /* 3E Input Enable */
95 { 0x3F, 0x00 }, /* 3F Output Enable */
96
97 { 0x40, 0x00 }, /* 40 Level Control */
98 { 0x41, 0x00 }, /* 41 DSP Filter Enable */
99 { 0x42, 0x00 }, /* 42 Bias Control */
100 { 0x43, 0x00 }, /* 43 DAC Control */
101 { 0x44, 0x06 }, /* 44 ADC Control */
102 { 0x45, 0x00 }, /* 45 Device Shutdown */
103 { 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */
104 { 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */
105 { 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */
106 { 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */
107 { 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */
108 { 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */
109 { 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */
110 { 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */
111 { 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */
112 { 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */
113
114 { 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */
115 { 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */
116 { 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */
117 { 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */
118 { 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */
119 { 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */
120 { 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */
121 { 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */
122 { 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */
123 { 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */
124 { 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */
125 { 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */
126 { 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */
127 { 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */
128 { 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */
129 { 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */
130
131 { 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */
132 { 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */
133 { 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */
134 { 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */
135 { 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */
136 { 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */
137 { 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */
138 { 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */
139 { 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */
140 { 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */
141 { 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */
142 { 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */
143 { 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */
144 { 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */
145 { 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */
146 { 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */
147
148 { 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */
149 { 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */
150 { 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */
151 { 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */
152 { 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */
153 { 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */
154 { 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */
155 { 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */
156 { 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */
157 { 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */
158 { 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */
159 { 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */
160 { 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */
161 { 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */
162 { 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */
163 { 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */
164
165 { 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */
166 { 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */
167 { 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */
168 { 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */
169 { 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */
170 { 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */
171 { 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */
172 { 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */
173 { 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */
174 { 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */
175 { 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */
176 { 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */
177 { 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */
178 { 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */
179 { 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */
180 { 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */
181
182 { 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */
183 { 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */
184 { 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */
185 { 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */
186 { 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */
187 { 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */
188 { 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */
189 { 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */
190 { 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */
191 { 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */
192 { 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */
193 { 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */
194 { 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */
195 { 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */
196 { 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */
197 { 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */
198
199 { 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */
200 { 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */
201 { 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */
202 { 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */
203 { 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */
204 { 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */
205 { 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */
206 { 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */
207 { 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */
208 { 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */
209 { 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */
210 { 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */
211 { 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */
212 { 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */
213 { 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */
214 { 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */
215
216 { 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */
217 { 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */
218 { 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */
219 { 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */
220 { 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */
221 { 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */
222 { 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */
223 { 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */
224 { 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */
225 { 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */
226 { 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */
227 { 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */
228 { 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */
229 { 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */
230 { 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */
231 { 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */
232
233 { 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */
234 { 0xC1, 0x00 }, /* C1 Record TDM Slot */
235 { 0xC2, 0x00 }, /* C2 Sample Rate */
236 { 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */
237 { 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */
238 { 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */
239 { 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */
240 { 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */
241 { 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */
242 { 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */
243 { 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */
244 { 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */
245 { 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */
246 { 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */
247 { 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */
248 { 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */
249
250 { 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */
251 { 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */
252};
253
254static bool max98090_volatile_register(struct device *dev, unsigned int reg)
255{
256 switch (reg) {
25b4ab43 257 case M98090_REG_SOFTWARE_RESET:
685e4215
JW		 258 case M98090_REG_DEVICE_STATUS:
259 case M98090_REG_JACK_STATUS:
260 case M98090_REG_REVISION_ID:
261 return true;
262 default:
263 return false;
264 }
265}
266
267static bool max98090_readable_register(struct device *dev, unsigned int reg)
268{
269 switch (reg) {
270 case M98090_REG_DEVICE_STATUS:
271 case M98090_REG_JACK_STATUS:
272 case M98090_REG_INTERRUPT_S:
273 case M98090_REG_RESERVED:
274 case M98090_REG_LINE_INPUT_CONFIG:
275 case M98090_REG_LINE_INPUT_LEVEL:
276 case M98090_REG_INPUT_MODE:
277 case M98090_REG_MIC1_INPUT_LEVEL:
278 case M98090_REG_MIC2_INPUT_LEVEL:
279 case M98090_REG_MIC_BIAS_VOLTAGE:
280 case M98090_REG_DIGITAL_MIC_ENABLE:
281 case M98090_REG_DIGITAL_MIC_CONFIG:
282 case M98090_REG_LEFT_ADC_MIXER:
283 case M98090_REG_RIGHT_ADC_MIXER:
284 case M98090_REG_LEFT_ADC_LEVEL:
285 case M98090_REG_RIGHT_ADC_LEVEL:
286 case M98090_REG_ADC_BIQUAD_LEVEL:
287 case M98090_REG_ADC_SIDETONE:
288 case M98090_REG_SYSTEM_CLOCK:
289 case M98090_REG_CLOCK_MODE:
290 case M98090_REG_CLOCK_RATIO_NI_MSB:
291 case M98090_REG_CLOCK_RATIO_NI_LSB:
292 case M98090_REG_CLOCK_RATIO_MI_MSB:
293 case M98090_REG_CLOCK_RATIO_MI_LSB:
294 case M98090_REG_MASTER_MODE:
295 case M98090_REG_INTERFACE_FORMAT:
296 case M98090_REG_TDM_CONTROL:
297 case M98090_REG_TDM_FORMAT:
298 case M98090_REG_IO_CONFIGURATION:
299 case M98090_REG_FILTER_CONFIG:
300 case M98090_REG_DAI_PLAYBACK_LEVEL:
301 case M98090_REG_DAI_PLAYBACK_LEVEL_EQ:
302 case M98090_REG_LEFT_HP_MIXER:
303 case M98090_REG_RIGHT_HP_MIXER:
304 case M98090_REG_HP_CONTROL:
305 case M98090_REG_LEFT_HP_VOLUME:
306 case M98090_REG_RIGHT_HP_VOLUME:
307 case M98090_REG_LEFT_SPK_MIXER:
308 case M98090_REG_RIGHT_SPK_MIXER:
309 case M98090_REG_SPK_CONTROL:
310 case M98090_REG_LEFT_SPK_VOLUME:
311 case M98090_REG_RIGHT_SPK_VOLUME:
312 case M98090_REG_DRC_TIMING:
313 case M98090_REG_DRC_COMPRESSOR:
314 case M98090_REG_DRC_EXPANDER:
315 case M98090_REG_DRC_GAIN:
316 case M98090_REG_RCV_LOUTL_MIXER:
317 case M98090_REG_RCV_LOUTL_CONTROL:
318 case M98090_REG_RCV_LOUTL_VOLUME:
319 case M98090_REG_LOUTR_MIXER:
320 case M98090_REG_LOUTR_CONTROL:
321 case M98090_REG_LOUTR_VOLUME:
322 case M98090_REG_JACK_DETECT:
323 case M98090_REG_INPUT_ENABLE:
324 case M98090_REG_OUTPUT_ENABLE:
325 case M98090_REG_LEVEL_CONTROL:
326 case M98090_REG_DSP_FILTER_ENABLE:
327 case M98090_REG_BIAS_CONTROL:
328 case M98090_REG_DAC_CONTROL:
329 case M98090_REG_ADC_CONTROL:
330 case M98090_REG_DEVICE_SHUTDOWN:
331 case M98090_REG_EQUALIZER_BASE ... M98090_REG_EQUALIZER_BASE + 0x68:
332 case M98090_REG_RECORD_BIQUAD_BASE ... M98090_REG_RECORD_BIQUAD_BASE + 0x0E:
333 case M98090_REG_DMIC3_VOLUME:
334 case M98090_REG_DMIC4_VOLUME:
335 case M98090_REG_DMIC34_BQ_PREATTEN:
336 case M98090_REG_RECORD_TDM_SLOT:
337 case M98090_REG_SAMPLE_RATE:
338 case M98090_REG_DMIC34_BIQUAD_BASE ... M98090_REG_DMIC34_BIQUAD_BASE + 0x0E:
e126a646 339 case M98090_REG_REVISION_ID:
685e4215
JW		 340 return true;
341 default:
342 return false;
343 }
344}
345
346static int max98090_reset(struct max98090_priv *max98090)
347{
348 int ret;
349
350 /* Reset the codec by writing to this write-only reset register */
351 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET,
352 M98090_SWRESET_MASK);
353 if (ret < 0) {
354 dev_err(max98090->codec->dev,
355 "Failed to reset codec: %d\n", ret);
356 return ret;
357 }
358
359 msleep(20);
360 return ret;
361}
362
363static const unsigned int max98090_micboost_tlv[] = {
364 TLV_DB_RANGE_HEAD(2),
365 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
366 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0),
367};
368
369static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv, 0, 100, 0);
370
371static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv,
372 -600, 600, 0);
373
374static const unsigned int max98090_line_tlv[] = {
375 TLV_DB_RANGE_HEAD(2),
376 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0),
377 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0),
378};
379
380static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv, 0, 600, 0);
381static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0);
382
383static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv, 0, 600, 0);
384static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0);
385
386static const DECLARE_TLV_DB_SCALE(max98090_sidetone_tlv, -6050, 200, 0);
387
388static const DECLARE_TLV_DB_SCALE(max98090_alc_tlv, -1500, 100, 0);
389static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0);
390static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0);
391static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0);
729af1ce 392static const DECLARE_TLV_DB_SCALE(max98090_sdg_tlv, 50, 200, 0);
685e4215
JW		 393
394static const unsigned int max98090_mixout_tlv[] = {
395 TLV_DB_RANGE_HEAD(2),
396 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0),
397 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0),
398};
399
400static const unsigned int max98090_hp_tlv[] = {
401 TLV_DB_RANGE_HEAD(5),
402 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
403 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
404 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
405 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
406 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0),
407};
408
409static const unsigned int max98090_spk_tlv[] = {
410 TLV_DB_RANGE_HEAD(5),
411 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0),
412 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0),
413 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0),
414 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0),
415 30, 39, TLV_DB_SCALE_ITEM(950, 50, 0),
416};
417
418static const unsigned int max98090_rcv_lout_tlv[] = {
419 TLV_DB_RANGE_HEAD(5),
420 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
421 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
422 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
423 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
424 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0),
425};
426
427static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol,
428 struct snd_ctl_elem_value *ucontrol)
429{
ea53bf77 430 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
685e4215
JW		 431 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
432 struct soc_mixer_control *mc =
433 (struct soc_mixer_control *)kcontrol->private_value;
434 unsigned int mask = (1 << fls(mc->max)) - 1;
435 unsigned int val = snd_soc_read(codec, mc->reg);
436 unsigned int *select;
437
438 switch (mc->reg) {
439 case M98090_REG_MIC1_INPUT_LEVEL:
440 select = &(max98090->pa1en);
441 break;
442 case M98090_REG_MIC2_INPUT_LEVEL:
443 select = &(max98090->pa2en);
444 break;
445 case M98090_REG_ADC_SIDETONE:
446 select = &(max98090->sidetone);
447 break;
448 default:
449 return -EINVAL;
450 }
451
452 val = (val >> mc->shift) & mask;
453
454 if (val >= 1) {
455 /* If on, return the volume */
456 val = val - 1;
457 *select = val;
458 } else {
459 /* If off, return last stored value */
460 val = *select;
461 }
462
463 ucontrol->value.integer.value[0] = val;
464 return 0;
465}
466
467static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol,
468 struct snd_ctl_elem_value *ucontrol)
469{
ea53bf77 470 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
685e4215
JW		 471 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
472 struct soc_mixer_control *mc =
473 (struct soc_mixer_control *)kcontrol->private_value;
474 unsigned int mask = (1 << fls(mc->max)) - 1;
475 unsigned int sel = ucontrol->value.integer.value[0];
476 unsigned int val = snd_soc_read(codec, mc->reg);
477 unsigned int *select;
478
479 switch (mc->reg) {
480 case M98090_REG_MIC1_INPUT_LEVEL:
481 select = &(max98090->pa1en);
482 break;
483 case M98090_REG_MIC2_INPUT_LEVEL:
484 select = &(max98090->pa2en);
485 break;
486 case M98090_REG_ADC_SIDETONE:
487 select = &(max98090->sidetone);
488 break;
489 default:
490 return -EINVAL;
491 }
492
493 val = (val >> mc->shift) & mask;
494
495 *select = sel;
496
497 /* Setting a volume is only valid if it is already On */
498 if (val >= 1) {
499 sel = sel + 1;
500 } else {
501 /* Write what was already there */
502 sel = val;
503 }
504
505 snd_soc_update_bits(codec, mc->reg,
506 mask << mc->shift,
507 sel << mc->shift);
508
509 return 0;
510}
511
4ca74feb 512static const char *max98090_perf_pwr_text[] =
685e4215 513 { "High Performance", "Low Power" };
4ca74feb 514static const char *max98090_pwr_perf_text[] =
685e4215
JW		 515 { "Low Power", "High Performance" };
516
2907cbcc
TI		 517static SOC_ENUM_SINGLE_DECL(max98090_vcmbandgap_enum,
518 M98090_REG_BIAS_CONTROL,
519 M98090_VCM_MODE_SHIFT,
520 max98090_pwr_perf_text);
685e4215 521
4ca74feb 522static const char *max98090_osr128_text[] = { "64*fs", "128*fs" };
685e4215 523
2907cbcc
TI		 524static SOC_ENUM_SINGLE_DECL(max98090_osr128_enum,
525 M98090_REG_ADC_CONTROL,
526 M98090_OSR128_SHIFT,
527 max98090_osr128_text);
685e4215
JW		 528
529static const char *max98090_mode_text[] = { "Voice", "Music" };
530
2907cbcc
TI		 531static SOC_ENUM_SINGLE_DECL(max98090_mode_enum,
532 M98090_REG_FILTER_CONFIG,
533 M98090_MODE_SHIFT,
534 max98090_mode_text);
685e4215 535
2907cbcc
TI		 536static SOC_ENUM_SINGLE_DECL(max98090_filter_dmic34mode_enum,
537 M98090_REG_FILTER_CONFIG,
538 M98090_FLT_DMIC34MODE_SHIFT,
539 max98090_mode_text);
685e4215 540
4ca74feb 541static const char *max98090_drcatk_text[] =
685e4215
JW		 542 { "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" };
543
2907cbcc
TI		 544static SOC_ENUM_SINGLE_DECL(max98090_drcatk_enum,
545 M98090_REG_DRC_TIMING,
546 M98090_DRCATK_SHIFT,
547 max98090_drcatk_text);
685e4215 548
4ca74feb 549static const char *max98090_drcrls_text[] =
685e4215
JW		 550 { "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" };
551
2907cbcc
TI		 552static SOC_ENUM_SINGLE_DECL(max98090_drcrls_enum,
553 M98090_REG_DRC_TIMING,
554 M98090_DRCRLS_SHIFT,
555 max98090_drcrls_text);
685e4215 556
4ca74feb 557static const char *max98090_alccmp_text[] =
685e4215
JW		 558 { "1:1", "1:1.5", "1:2", "1:4", "1:INF" };
559
2907cbcc
TI		 560static SOC_ENUM_SINGLE_DECL(max98090_alccmp_enum,
561 M98090_REG_DRC_COMPRESSOR,
562 M98090_DRCCMP_SHIFT,
563 max98090_alccmp_text);
685e4215 564
4ca74feb 565static const char *max98090_drcexp_text[] = { "1:1", "2:1", "3:1" };
685e4215 566
2907cbcc
TI		 567static SOC_ENUM_SINGLE_DECL(max98090_drcexp_enum,
568 M98090_REG_DRC_EXPANDER,
569 M98090_DRCEXP_SHIFT,
570 max98090_drcexp_text);
685e4215 571
2907cbcc
TI		 572static SOC_ENUM_SINGLE_DECL(max98090_dac_perfmode_enum,
573 M98090_REG_DAC_CONTROL,
574 M98090_PERFMODE_SHIFT,
575 max98090_perf_pwr_text);
685e4215 576
2907cbcc
TI		 577static SOC_ENUM_SINGLE_DECL(max98090_dachp_enum,
578 M98090_REG_DAC_CONTROL,
579 M98090_DACHP_SHIFT,
580 max98090_pwr_perf_text);
685e4215 581
2907cbcc
TI		 582static SOC_ENUM_SINGLE_DECL(max98090_adchp_enum,
583 M98090_REG_ADC_CONTROL,
584 M98090_ADCHP_SHIFT,
585 max98090_pwr_perf_text);
685e4215
JW		 586
587static const struct snd_kcontrol_new max98090_snd_controls[] = {
588 SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum),
589
590 SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG,
591 M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0),
592
593 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
594 M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT,
595 M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv,
596 max98090_put_enab_tlv, max98090_micboost_tlv),
597
598 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
599 M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT,
600 M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv,
601 max98090_put_enab_tlv, max98090_micboost_tlv),
602
603 SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL,
604 M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1,
605 max98090_mic_tlv),
606
607 SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL,
608 M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1,
609 max98090_mic_tlv),
610
611 SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume",
612 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG135_SHIFT, 0,
613 M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv),
614
615 SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume",
616 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG246_SHIFT, 0,
617 M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv),
618
619 SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL,
620 M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1,
621 max98090_line_tlv),
622
623 SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL,
624 M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1,
625 max98090_line_tlv),
626
627 SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
628 M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0),
629 SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
630 M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0),
631
632 SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL,
633 M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0,
634 max98090_avg_tlv),
635 SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL,
636 M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0,
637 max98090_avg_tlv),
638
639 SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL,
640 M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1,
641 max98090_av_tlv),
642 SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL,
643 M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1,
644 max98090_av_tlv),
645
646 SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum),
647 SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL,
648 M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0),
649 SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum),
650
651 SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION,
652 M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0),
653 SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION,
654 M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0),
655 SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION,
656 M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0),
657 SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION,
658 M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1),
659 SOC_ENUM("Filter Mode", max98090_mode_enum),
660 SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG,
661 M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0),
662 SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG,
663 M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0),
664 SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL,
665 M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv),
666 SOC_SINGLE_EXT_TLV("Digital Sidetone Volume",
667 M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT,
668 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv,
729af1ce 669 max98090_put_enab_tlv, max98090_sdg_tlv),
685e4215
JW		 670 SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
671 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0,
672 max98090_dvg_tlv),
673 SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
674 M98090_DV_SHIFT, M98090_DV_NUM - 1, 1,
675 max98090_dv_tlv),
676 SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105),
677 SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
678 M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0),
679 SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
680 M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0),
681 SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
682 M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0),
683 SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
684 M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1,
685 1),
686 SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
687 M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1,
688 max98090_dv_tlv),
689
690 SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING,
691 M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0),
692 SOC_ENUM("ALC Attack Time", max98090_drcatk_enum),
693 SOC_ENUM("ALC Release Time", max98090_drcrls_enum),
694 SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN,
695 M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0,
696 max98090_alcmakeup_tlv),
697 SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum),
698 SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum),
699 SOC_SINGLE_TLV("ALC Compression Threshold Volume",
700 M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT,
701 M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv),
702 SOC_SINGLE_TLV("ALC Expansion Threshold Volume",
703 M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT,
704 M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv),
705
706 SOC_ENUM("DAC HP Playback Performance Mode",
707 max98090_dac_perfmode_enum),
708 SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum),
709
710 SOC_SINGLE_TLV("Headphone Left Mixer Volume",
711 M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT,
712 M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv),
713 SOC_SINGLE_TLV("Headphone Right Mixer Volume",
714 M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT,
715 M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv),
716
717 SOC_SINGLE_TLV("Speaker Left Mixer Volume",
718 M98090_REG_SPK_CONTROL, M98090_MIXSPLG_SHIFT,
719 M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv),
720 SOC_SINGLE_TLV("Speaker Right Mixer Volume",
721 M98090_REG_SPK_CONTROL, M98090_MIXSPRG_SHIFT,
722 M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv),
723
724 SOC_SINGLE_TLV("Receiver Left Mixer Volume",
725 M98090_REG_RCV_LOUTL_CONTROL, M98090_MIXRCVLG_SHIFT,
726 M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv),
727 SOC_SINGLE_TLV("Receiver Right Mixer Volume",
728 M98090_REG_LOUTR_CONTROL, M98090_MIXRCVRG_SHIFT,
729 M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv),
730
731 SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME,
732 M98090_REG_RIGHT_HP_VOLUME, M98090_HPVOLL_SHIFT,
733 M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv),
734
735 SOC_DOUBLE_R_RANGE_TLV("Speaker Volume",
736 M98090_REG_LEFT_SPK_VOLUME, M98090_REG_RIGHT_SPK_VOLUME,
737 M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24,
738 0, max98090_spk_tlv),
739
740 SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME,
741 M98090_REG_LOUTR_VOLUME, M98090_RCVLVOL_SHIFT,
742 M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv),
743
744 SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME,
745 M98090_HPLM_SHIFT, 1, 1),
746 SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME,
747 M98090_HPRM_SHIFT, 1, 1),
748
749 SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME,
750 M98090_SPLM_SHIFT, 1, 1),
751 SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME,
752 M98090_SPRM_SHIFT, 1, 1),
753
754 SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME,
755 M98090_RCVLM_SHIFT, 1, 1),
756 SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME,
757 M98090_RCVRM_SHIFT, 1, 1),
758
759 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL,
760 M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1),
761 SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL,
762 M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1),
763 SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL,
764 M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1),
765
766 SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE, 15),
767 SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
768 M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0),
769};
770
771static const struct snd_kcontrol_new max98091_snd_controls[] = {
772
773 SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE,
774 M98090_DMIC34_ZEROPAD_SHIFT,
775 M98090_DMIC34_ZEROPAD_NUM - 1, 0),
776
777 SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum),
778 SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG,
779 M98090_FLT_DMIC34HPF_SHIFT,
780 M98090_FLT_DMIC34HPF_NUM - 1, 0),
781
782 SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME,
783 M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0,
784 max98090_avg_tlv),
785 SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME,
786 M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0,
787 max98090_avg_tlv),
788
789 SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME,
790 M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1,
791 max98090_av_tlv),
792 SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME,
793 M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1,
794 max98090_av_tlv),
795
796 SND_SOC_BYTES("DMIC34 Biquad Coefficients",
797 M98090_REG_DMIC34_BIQUAD_BASE, 15),
798 SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
799 M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0),
800
801 SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume",
802 M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT,
803 M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv),
804};
805
806static int max98090_micinput_event(struct snd_soc_dapm_widget *w,
807 struct snd_kcontrol *kcontrol, int event)
808{
809 struct snd_soc_codec *codec = w->codec;
810 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
811
812 unsigned int val = snd_soc_read(codec, w->reg);
813
814 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
815 val = (val & M98090_MIC_PA1EN_MASK) >> M98090_MIC_PA1EN_SHIFT;
816 else
817 val = (val & M98090_MIC_PA2EN_MASK) >> M98090_MIC_PA2EN_SHIFT;
818
685e4215
JW		 819 if (val >= 1) {
820 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) {
821 max98090->pa1en = val - 1; /* Update for volatile */
822 } else {
823 max98090->pa2en = val - 1; /* Update for volatile */
824 }
825 }
826
827 switch (event) {
828 case SND_SOC_DAPM_POST_PMU:
829 /* If turning on, set to most recently selected volume */
830 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
831 val = max98090->pa1en + 1;
832 else
833 val = max98090->pa2en + 1;
834 break;
835 case SND_SOC_DAPM_POST_PMD:
836 /* If turning off, turn off */
837 val = 0;
838 break;
839 default:
840 return -EINVAL;
841 }
842
843 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
844 snd_soc_update_bits(codec, w->reg, M98090_MIC_PA1EN_MASK,
845 val << M98090_MIC_PA1EN_SHIFT);
846 else
847 snd_soc_update_bits(codec, w->reg, M98090_MIC_PA2EN_MASK,
848 val << M98090_MIC_PA2EN_SHIFT);
849
850 return 0;
851}
852
853static const char *mic1_mux_text[] = { "IN12", "IN56" };
854
2907cbcc
TI		 855static SOC_ENUM_SINGLE_DECL(mic1_mux_enum,
856 M98090_REG_INPUT_MODE,
857 M98090_EXTMIC1_SHIFT,
858 mic1_mux_text);
685e4215
JW		 859
860static const struct snd_kcontrol_new max98090_mic1_mux =
861 SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum);
862
863static const char *mic2_mux_text[] = { "IN34", "IN56" };
864
2907cbcc
TI		 865static SOC_ENUM_SINGLE_DECL(mic2_mux_enum,
866 M98090_REG_INPUT_MODE,
867 M98090_EXTMIC2_SHIFT,
868 mic2_mux_text);
685e4215
JW		 869
870static const struct snd_kcontrol_new max98090_mic2_mux =
871 SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum);
872
fd5f940f
AB		 873static const char *dmic_mux_text[] = { "ADC", "DMIC" };
874
ba513116 875static SOC_ENUM_SINGLE_VIRT_DECL(dmic_mux_enum, dmic_mux_text);
fd5f940f
AB		 876
877static const struct snd_kcontrol_new max98090_dmic_mux =
aae1137b 878 SOC_DAPM_ENUM("DMIC Mux", dmic_mux_enum);
fd5f940f 879
4ca74feb 880static const char *max98090_micpre_text[] = { "Off", "On" };
685e4215 881
2907cbcc
TI		 882static SOC_ENUM_SINGLE_DECL(max98090_pa1en_enum,
883 M98090_REG_MIC1_INPUT_LEVEL,
884 M98090_MIC_PA1EN_SHIFT,
885 max98090_micpre_text);
685e4215 886
2907cbcc
TI		 887static SOC_ENUM_SINGLE_DECL(max98090_pa2en_enum,
888 M98090_REG_MIC2_INPUT_LEVEL,
889 M98090_MIC_PA2EN_SHIFT,
890 max98090_micpre_text);
685e4215
JW		 891
892/* LINEA mixer switch */
893static const struct snd_kcontrol_new max98090_linea_mixer_controls[] = {
894 SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG,
895 M98090_IN1SEEN_SHIFT, 1, 0),
896 SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG,
897 M98090_IN3SEEN_SHIFT, 1, 0),
898 SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG,
899 M98090_IN5SEEN_SHIFT, 1, 0),
900 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG,
901 M98090_IN34DIFF_SHIFT, 1, 0),
902};
903
904/* LINEB mixer switch */
905static const struct snd_kcontrol_new max98090_lineb_mixer_controls[] = {
906 SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG,
907 M98090_IN2SEEN_SHIFT, 1, 0),
908 SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG,
909 M98090_IN4SEEN_SHIFT, 1, 0),
910 SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG,
911 M98090_IN6SEEN_SHIFT, 1, 0),
912 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG,
913 M98090_IN56DIFF_SHIFT, 1, 0),
914};
915
916/* Left ADC mixer switch */
917static const struct snd_kcontrol_new max98090_left_adc_mixer_controls[] = {
918 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER,
919 M98090_MIXADL_IN12DIFF_SHIFT, 1, 0),
920 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER,
921 M98090_MIXADL_IN34DIFF_SHIFT, 1, 0),
922 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER,
923 M98090_MIXADL_IN65DIFF_SHIFT, 1, 0),
924 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER,
925 M98090_MIXADL_LINEA_SHIFT, 1, 0),
926 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER,
927 M98090_MIXADL_LINEB_SHIFT, 1, 0),
928 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER,
929 M98090_MIXADL_MIC1_SHIFT, 1, 0),
930 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER,
931 M98090_MIXADL_MIC2_SHIFT, 1, 0),
932};
933
934/* Right ADC mixer switch */
935static const struct snd_kcontrol_new max98090_right_adc_mixer_controls[] = {
936 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER,
937 M98090_MIXADR_IN12DIFF_SHIFT, 1, 0),
938 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER,
939 M98090_MIXADR_IN34DIFF_SHIFT, 1, 0),
940 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER,
941 M98090_MIXADR_IN65DIFF_SHIFT, 1, 0),
942 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER,
943 M98090_MIXADR_LINEA_SHIFT, 1, 0),
944 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER,
945 M98090_MIXADR_LINEB_SHIFT, 1, 0),
946 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER,
947 M98090_MIXADR_MIC1_SHIFT, 1, 0),
948 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER,
949 M98090_MIXADR_MIC2_SHIFT, 1, 0),
950};
951
952static const char *lten_mux_text[] = { "Normal", "Loopthrough" };
953
2907cbcc
TI		 954static SOC_ENUM_SINGLE_DECL(ltenl_mux_enum,
955 M98090_REG_IO_CONFIGURATION,
956 M98090_LTEN_SHIFT,
957 lten_mux_text);
685e4215 958
2907cbcc
TI		 959static SOC_ENUM_SINGLE_DECL(ltenr_mux_enum,
960 M98090_REG_IO_CONFIGURATION,
961 M98090_LTEN_SHIFT,
962 lten_mux_text);
685e4215
JW		 963
964static const struct snd_kcontrol_new max98090_ltenl_mux =
965 SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum);
966
967static const struct snd_kcontrol_new max98090_ltenr_mux =
968 SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum);
969
970static const char *lben_mux_text[] = { "Normal", "Loopback" };
971
2907cbcc
TI		 972static SOC_ENUM_SINGLE_DECL(lbenl_mux_enum,
973 M98090_REG_IO_CONFIGURATION,
974 M98090_LBEN_SHIFT,
975 lben_mux_text);
685e4215 976
2907cbcc
TI		 977static SOC_ENUM_SINGLE_DECL(lbenr_mux_enum,
978 M98090_REG_IO_CONFIGURATION,
979 M98090_LBEN_SHIFT,
980 lben_mux_text);
685e4215
JW		 981
982static const struct snd_kcontrol_new max98090_lbenl_mux =
983 SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum);
984
985static const struct snd_kcontrol_new max98090_lbenr_mux =
986 SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum);
987
988static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" };
989
990static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" };
991
2907cbcc
TI		 992static SOC_ENUM_SINGLE_DECL(stenl_mux_enum,
993 M98090_REG_ADC_SIDETONE,
994 M98090_DSTSL_SHIFT,
995 stenl_mux_text);
685e4215 996
2907cbcc
TI		 997static SOC_ENUM_SINGLE_DECL(stenr_mux_enum,
998 M98090_REG_ADC_SIDETONE,
999 M98090_DSTSR_SHIFT,
1000 stenr_mux_text);
685e4215
JW		 1001
1002static const struct snd_kcontrol_new max98090_stenl_mux =
1003 SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum);
1004
1005static const struct snd_kcontrol_new max98090_stenr_mux =
1006 SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum);
1007
1008/* Left speaker mixer switch */
1009static const struct
1010 snd_kcontrol_new max98090_left_speaker_mixer_controls[] = {
1011 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER,
1012 M98090_MIXSPL_DACL_SHIFT, 1, 0),
1013 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER,
1014 M98090_MIXSPL_DACR_SHIFT, 1, 0),
1015 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER,
1016 M98090_MIXSPL_LINEA_SHIFT, 1, 0),
1017 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER,
1018 M98090_MIXSPL_LINEB_SHIFT, 1, 0),
1019 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER,
1020 M98090_MIXSPL_MIC1_SHIFT, 1, 0),
1021 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER,
1022 M98090_MIXSPL_MIC2_SHIFT, 1, 0),
1023};
1024
1025/* Right speaker mixer switch */
1026static const struct
1027 snd_kcontrol_new max98090_right_speaker_mixer_controls[] = {
1028 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
1029 M98090_MIXSPR_DACL_SHIFT, 1, 0),
1030 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
1031 M98090_MIXSPR_DACR_SHIFT, 1, 0),
1032 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER,
1033 M98090_MIXSPR_LINEA_SHIFT, 1, 0),
1034 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER,
1035 M98090_MIXSPR_LINEB_SHIFT, 1, 0),
1036 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER,
1037 M98090_MIXSPR_MIC1_SHIFT, 1, 0),
1038 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER,
1039 M98090_MIXSPR_MIC2_SHIFT, 1, 0),
1040};
1041
1042/* Left headphone mixer switch */
1043static const struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = {
1044 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER,
1045 M98090_MIXHPL_DACL_SHIFT, 1, 0),
1046 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER,
1047 M98090_MIXHPL_DACR_SHIFT, 1, 0),
1048 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER,
1049 M98090_MIXHPL_LINEA_SHIFT, 1, 0),
1050 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER,
1051 M98090_MIXHPL_LINEB_SHIFT, 1, 0),
1052 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER,
1053 M98090_MIXHPL_MIC1_SHIFT, 1, 0),
1054 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER,
1055 M98090_MIXHPL_MIC2_SHIFT, 1, 0),
1056};
1057
1058/* Right headphone mixer switch */
1059static const struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = {
1060 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER,
1061 M98090_MIXHPR_DACL_SHIFT, 1, 0),
1062 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER,
1063 M98090_MIXHPR_DACR_SHIFT, 1, 0),
1064 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER,
1065 M98090_MIXHPR_LINEA_SHIFT, 1, 0),
1066 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER,
1067 M98090_MIXHPR_LINEB_SHIFT, 1, 0),
1068 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER,
1069 M98090_MIXHPR_MIC1_SHIFT, 1, 0),
1070 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER,
1071 M98090_MIXHPR_MIC2_SHIFT, 1, 0),
1072};
1073
1074/* Left receiver mixer switch */
1075static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls[] = {
1076 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1077 M98090_MIXRCVL_DACL_SHIFT, 1, 0),
1078 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1079 M98090_MIXRCVL_DACR_SHIFT, 1, 0),
1080 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER,
1081 M98090_MIXRCVL_LINEA_SHIFT, 1, 0),
1082 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER,
1083 M98090_MIXRCVL_LINEB_SHIFT, 1, 0),
1084 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER,
1085 M98090_MIXRCVL_MIC1_SHIFT, 1, 0),
1086 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER,
1087 M98090_MIXRCVL_MIC2_SHIFT, 1, 0),
1088};
1089
1090/* Right receiver mixer switch */
1091static const struct snd_kcontrol_new max98090_right_rcv_mixer_controls[] = {
1092 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER,
1093 M98090_MIXRCVR_DACL_SHIFT, 1, 0),
1094 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER,
1095 M98090_MIXRCVR_DACR_SHIFT, 1, 0),
1096 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER,
1097 M98090_MIXRCVR_LINEA_SHIFT, 1, 0),
1098 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER,
1099 M98090_MIXRCVR_LINEB_SHIFT, 1, 0),
1100 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER,
1101 M98090_MIXRCVR_MIC1_SHIFT, 1, 0),
1102 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER,
1103 M98090_MIXRCVR_MIC2_SHIFT, 1, 0),
1104};
1105
1106static const char *linmod_mux_text[] = { "Left Only", "Left and Right" };
1107
2907cbcc
TI		 1108static SOC_ENUM_SINGLE_DECL(linmod_mux_enum,
1109 M98090_REG_LOUTR_MIXER,
1110 M98090_LINMOD_SHIFT,
1111 linmod_mux_text);
685e4215
JW		 1112
1113static const struct snd_kcontrol_new max98090_linmod_mux =
1114 SOC_DAPM_ENUM("LINMOD Mux", linmod_mux_enum);
1115
1116static const char *mixhpsel_mux_text[] = { "DAC Only", "HP Mixer" };
1117
1118/*
1119 * This is a mux as it selects the HP output, but to DAPM it is a Mixer enable
1120 */
2907cbcc
TI		 1121static SOC_ENUM_SINGLE_DECL(mixhplsel_mux_enum,
1122 M98090_REG_HP_CONTROL,
1123 M98090_MIXHPLSEL_SHIFT,
1124 mixhpsel_mux_text);
685e4215
JW		 1125
1126static const struct snd_kcontrol_new max98090_mixhplsel_mux =
1127 SOC_DAPM_ENUM("MIXHPLSEL Mux", mixhplsel_mux_enum);
1128
2907cbcc
TI		 1129static SOC_ENUM_SINGLE_DECL(mixhprsel_mux_enum,
1130 M98090_REG_HP_CONTROL,
1131 M98090_MIXHPRSEL_SHIFT,
1132 mixhpsel_mux_text);
685e4215
JW		 1133
1134static const struct snd_kcontrol_new max98090_mixhprsel_mux =
1135 SOC_DAPM_ENUM("MIXHPRSEL Mux", mixhprsel_mux_enum);
1136
1137static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = {
685e4215
JW		 1138 SND_SOC_DAPM_INPUT("MIC1"),
1139 SND_SOC_DAPM_INPUT("MIC2"),
1140 SND_SOC_DAPM_INPUT("DMICL"),
1141 SND_SOC_DAPM_INPUT("DMICR"),
1142 SND_SOC_DAPM_INPUT("IN1"),
1143 SND_SOC_DAPM_INPUT("IN2"),
1144 SND_SOC_DAPM_INPUT("IN3"),
1145 SND_SOC_DAPM_INPUT("IN4"),
1146 SND_SOC_DAPM_INPUT("IN5"),
1147 SND_SOC_DAPM_INPUT("IN6"),
1148 SND_SOC_DAPM_INPUT("IN12"),
1149 SND_SOC_DAPM_INPUT("IN34"),
1150 SND_SOC_DAPM_INPUT("IN56"),
1151
1152 SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE,
1153 M98090_MBEN_SHIFT, 0, NULL, 0),
1154 SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN,
1155 M98090_SHDNN_SHIFT, 0, NULL, 0),
1156 SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION,
1157 M98090_SDIEN_SHIFT, 0, NULL, 0),
1158 SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION,
1159 M98090_SDOEN_SHIFT, 0, NULL, 0),
1160 SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1161 M98090_DIGMICL_SHIFT, 0, NULL, 0),
1162 SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1163 M98090_DIGMICR_SHIFT, 0, NULL, 0),
1164 SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG,
1165 M98090_AHPF_SHIFT, 0, NULL, 0),
1166
1167/*
1168 * Note: Sysclk and misc power supplies are taken care of by SHDN
1169 */
1170
1171 SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM,
1172 0, 0, &max98090_mic1_mux),
1173
1174 SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM,
1175 0, 0, &max98090_mic2_mux),
1176
aae1137b 1177 SND_SOC_DAPM_MUX("DMIC Mux", SND_SOC_NOPM, 0, 0, &max98090_dmic_mux),
fd5f940f 1178
685e4215
JW		 1179 SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL,
1180 M98090_MIC_PA1EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1181 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1182
1183 SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL,
1184 M98090_MIC_PA2EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1185 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1186
1187 SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM, 0, 0,
1188 &max98090_linea_mixer_controls[0],
1189 ARRAY_SIZE(max98090_linea_mixer_controls)),
1190
1191 SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM, 0, 0,
1192 &max98090_lineb_mixer_controls[0],
1193 ARRAY_SIZE(max98090_lineb_mixer_controls)),
1194
1195 SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE,
1196 M98090_LINEAEN_SHIFT, 0, NULL, 0),
1197 SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE,
1198 M98090_LINEBEN_SHIFT, 0, NULL, 0),
1199
1200 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
1201 &max98090_left_adc_mixer_controls[0],
1202 ARRAY_SIZE(max98090_left_adc_mixer_controls)),
1203
1204 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
1205 &max98090_right_adc_mixer_controls[0],
1206 ARRAY_SIZE(max98090_right_adc_mixer_controls)),
1207
1208 SND_SOC_DAPM_ADC("ADCL", NULL, M98090_REG_INPUT_ENABLE,
1209 M98090_ADLEN_SHIFT, 0),
1210 SND_SOC_DAPM_ADC("ADCR", NULL, M98090_REG_INPUT_ENABLE,
1211 M98090_ADREN_SHIFT, 0),
1212
1213 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0,
1214 SND_SOC_NOPM, 0, 0),
1215 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1,
1216 SND_SOC_NOPM, 0, 0),
1217
1218 SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM,
1219 0, 0, &max98090_lbenl_mux),
1220
1221 SND_SOC_DAPM_MUX("LBENR Mux", SND_SOC_NOPM,
1222 0, 0, &max98090_lbenr_mux),
1223
1224 SND_SOC_DAPM_MUX("LTENL Mux", SND_SOC_NOPM,
1225 0, 0, &max98090_ltenl_mux),
1226
1227 SND_SOC_DAPM_MUX("LTENR Mux", SND_SOC_NOPM,
1228 0, 0, &max98090_ltenr_mux),
1229
1230 SND_SOC_DAPM_MUX("STENL Mux", SND_SOC_NOPM,
1231 0, 0, &max98090_stenl_mux),
1232
1233 SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM,
1234 0, 0, &max98090_stenr_mux),
1235
1236 SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
1237 SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0),
1238
1239 SND_SOC_DAPM_DAC("DACL", NULL, M98090_REG_OUTPUT_ENABLE,
1240 M98090_DALEN_SHIFT, 0),
1241 SND_SOC_DAPM_DAC("DACR", NULL, M98090_REG_OUTPUT_ENABLE,
1242 M98090_DAREN_SHIFT, 0),
1243
1244 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
1245 &max98090_left_hp_mixer_controls[0],
1246 ARRAY_SIZE(max98090_left_hp_mixer_controls)),
1247
1248 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
1249 &max98090_right_hp_mixer_controls[0],
1250 ARRAY_SIZE(max98090_right_hp_mixer_controls)),
1251
1252 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
1253 &max98090_left_speaker_mixer_controls[0],
1254 ARRAY_SIZE(max98090_left_speaker_mixer_controls)),
1255
1256 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
1257 &max98090_right_speaker_mixer_controls[0],
1258 ARRAY_SIZE(max98090_right_speaker_mixer_controls)),
1259
1260 SND_SOC_DAPM_MIXER("Left Receiver Mixer", SND_SOC_NOPM, 0, 0,
1261 &max98090_left_rcv_mixer_controls[0],
1262 ARRAY_SIZE(max98090_left_rcv_mixer_controls)),
1263
1264 SND_SOC_DAPM_MIXER("Right Receiver Mixer", SND_SOC_NOPM, 0, 0,
1265 &max98090_right_rcv_mixer_controls[0],
1266 ARRAY_SIZE(max98090_right_rcv_mixer_controls)),
1267
1268 SND_SOC_DAPM_MUX("LINMOD Mux", M98090_REG_LOUTR_MIXER,
1269 M98090_LINMOD_SHIFT, 0, &max98090_linmod_mux),
1270
1271 SND_SOC_DAPM_MUX("MIXHPLSEL Mux", M98090_REG_HP_CONTROL,
1272 M98090_MIXHPLSEL_SHIFT, 0, &max98090_mixhplsel_mux),
1273
1274 SND_SOC_DAPM_MUX("MIXHPRSEL Mux", M98090_REG_HP_CONTROL,
1275 M98090_MIXHPRSEL_SHIFT, 0, &max98090_mixhprsel_mux),
1276
1277 SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE,
1278 M98090_HPLEN_SHIFT, 0, NULL, 0),
1279 SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE,
1280 M98090_HPREN_SHIFT, 0, NULL, 0),
1281
1282 SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE,
1283 M98090_SPLEN_SHIFT, 0, NULL, 0),
1284 SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE,
1285 M98090_SPREN_SHIFT, 0, NULL, 0),
1286
1287 SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE,
1288 M98090_RCVLEN_SHIFT, 0, NULL, 0),
1289 SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE,
1290 M98090_RCVREN_SHIFT, 0, NULL, 0),
1291
1292 SND_SOC_DAPM_OUTPUT("HPL"),
1293 SND_SOC_DAPM_OUTPUT("HPR"),
1294 SND_SOC_DAPM_OUTPUT("SPKL"),
1295 SND_SOC_DAPM_OUTPUT("SPKR"),
1296 SND_SOC_DAPM_OUTPUT("RCVL"),
1297 SND_SOC_DAPM_OUTPUT("RCVR"),
1298};
1299
1300static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = {
685e4215
JW		 1301 SND_SOC_DAPM_INPUT("DMIC3"),
1302 SND_SOC_DAPM_INPUT("DMIC4"),
1303
1304 SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1305 M98090_DIGMIC3_SHIFT, 0, NULL, 0),
1306 SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1307 M98090_DIGMIC4_SHIFT, 0, NULL, 0),
1308};
1309
1310static const struct snd_soc_dapm_route max98090_dapm_routes[] = {
685e4215
JW		 1311 {"MIC1 Input", NULL, "MIC1"},
1312 {"MIC2 Input", NULL, "MIC2"},
1313
685e4215
JW		 1314 {"DMICL", NULL, "AHPF"},
1315 {"DMICR", NULL, "AHPF"},
1316
1317 /* MIC1 input mux */
1318 {"MIC1 Mux", "IN12", "IN12"},
1319 {"MIC1 Mux", "IN56", "IN56"},
1320
1321 /* MIC2 input mux */
1322 {"MIC2 Mux", "IN34", "IN34"},
1323 {"MIC2 Mux", "IN56", "IN56"},
1324
1325 {"MIC1 Input", NULL, "MIC1 Mux"},
1326 {"MIC2 Input", NULL, "MIC2 Mux"},
1327
1328 /* Left ADC input mixer */
1329 {"Left ADC Mixer", "IN12 Switch", "IN12"},
1330 {"Left ADC Mixer", "IN34 Switch", "IN34"},
1331 {"Left ADC Mixer", "IN56 Switch", "IN56"},
1332 {"Left ADC Mixer", "LINEA Switch", "LINEA Input"},
1333 {"Left ADC Mixer", "LINEB Switch", "LINEB Input"},
1334 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1335 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1336
1337 /* Right ADC input mixer */
1338 {"Right ADC Mixer", "IN12 Switch", "IN12"},
1339 {"Right ADC Mixer", "IN34 Switch", "IN34"},
1340 {"Right ADC Mixer", "IN56 Switch", "IN56"},
1341 {"Right ADC Mixer", "LINEA Switch", "LINEA Input"},
1342 {"Right ADC Mixer", "LINEB Switch", "LINEB Input"},
1343 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1344 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1345
1346 /* Line A input mixer */
1347 {"LINEA Mixer", "IN1 Switch", "IN1"},
1348 {"LINEA Mixer", "IN3 Switch", "IN3"},
1349 {"LINEA Mixer", "IN5 Switch", "IN5"},
1350 {"LINEA Mixer", "IN34 Switch", "IN34"},
1351
1352 /* Line B input mixer */
1353 {"LINEB Mixer", "IN2 Switch", "IN2"},
1354 {"LINEB Mixer", "IN4 Switch", "IN4"},
1355 {"LINEB Mixer", "IN6 Switch", "IN6"},
1356 {"LINEB Mixer", "IN56 Switch", "IN56"},
1357
1358 {"LINEA Input", NULL, "LINEA Mixer"},
1359 {"LINEB Input", NULL, "LINEB Mixer"},
1360
1361 /* Inputs */
1362 {"ADCL", NULL, "Left ADC Mixer"},
1363 {"ADCR", NULL, "Right ADC Mixer"},
1364 {"ADCL", NULL, "SHDN"},
1365 {"ADCR", NULL, "SHDN"},
1366
fd5f940f
AB		 1367 {"DMIC Mux", "ADC", "ADCL"},
1368 {"DMIC Mux", "ADC", "ADCR"},
1369 {"DMIC Mux", "DMIC", "DMICL"},
1370 {"DMIC Mux", "DMIC", "DMICR"},
f69e3caa
JN		 1371 {"DMIC Mux", "DMIC", "DMICL_ENA"},
1372 {"DMIC Mux", "DMIC", "DMICR_ENA"},
fd5f940f
AB		 1373
1374 {"LBENL Mux", "Normal", "DMIC Mux"},
685e4215 1375 {"LBENL Mux", "Loopback", "LTENL Mux"},
fd5f940f 1376 {"LBENR Mux", "Normal", "DMIC Mux"},
685e4215
JW		 1377 {"LBENR Mux", "Loopback", "LTENR Mux"},
1378
1379 {"AIFOUTL", NULL, "LBENL Mux"},
1380 {"AIFOUTR", NULL, "LBENR Mux"},
1381 {"AIFOUTL", NULL, "SHDN"},
1382 {"AIFOUTR", NULL, "SHDN"},
1383 {"AIFOUTL", NULL, "SDOEN"},
1384 {"AIFOUTR", NULL, "SDOEN"},
1385
1386 {"LTENL Mux", "Normal", "AIFINL"},
1387 {"LTENL Mux", "Loopthrough", "LBENL Mux"},
1388 {"LTENR Mux", "Normal", "AIFINR"},
1389 {"LTENR Mux", "Loopthrough", "LBENR Mux"},
1390
1391 {"DACL", NULL, "LTENL Mux"},
1392 {"DACR", NULL, "LTENR Mux"},
1393
1394 {"STENL Mux", "Sidetone Left", "ADCL"},
1395 {"STENL Mux", "Sidetone Left", "DMICL"},
1396 {"STENR Mux", "Sidetone Right", "ADCR"},
1397 {"STENR Mux", "Sidetone Right", "DMICR"},
1398 {"DACL", "NULL", "STENL Mux"},
1399 {"DACR", "NULL", "STENL Mux"},
1400
1401 {"AIFINL", NULL, "SHDN"},
1402 {"AIFINR", NULL, "SHDN"},
1403 {"AIFINL", NULL, "SDIEN"},
1404 {"AIFINR", NULL, "SDIEN"},
1405 {"DACL", NULL, "SHDN"},
1406 {"DACR", NULL, "SHDN"},
1407
1408 /* Left headphone output mixer */
1409 {"Left Headphone Mixer", "Left DAC Switch", "DACL"},
1410 {"Left Headphone Mixer", "Right DAC Switch", "DACR"},
1411 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1412 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1413 {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"},
1414 {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"},
1415
1416 /* Right headphone output mixer */
1417 {"Right Headphone Mixer", "Left DAC Switch", "DACL"},
1418 {"Right Headphone Mixer", "Right DAC Switch", "DACR"},
1419 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1420 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1421 {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"},
1422 {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"},
1423
1424 /* Left speaker output mixer */
1425 {"Left Speaker Mixer", "Left DAC Switch", "DACL"},
1426 {"Left Speaker Mixer", "Right DAC Switch", "DACR"},
1427 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1428 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1429 {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"},
1430 {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"},
1431
1432 /* Right speaker output mixer */
1433 {"Right Speaker Mixer", "Left DAC Switch", "DACL"},
1434 {"Right Speaker Mixer", "Right DAC Switch", "DACR"},
1435 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1436 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1437 {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"},
1438 {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"},
1439
1440 /* Left Receiver output mixer */
1441 {"Left Receiver Mixer", "Left DAC Switch", "DACL"},
1442 {"Left Receiver Mixer", "Right DAC Switch", "DACR"},
1443 {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1444 {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1445 {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"},
1446 {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"},
1447
1448 /* Right Receiver output mixer */
1449 {"Right Receiver Mixer", "Left DAC Switch", "DACL"},
1450 {"Right Receiver Mixer", "Right DAC Switch", "DACR"},
1451 {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1452 {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1453 {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"},
1454 {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"},
1455
1456 {"MIXHPLSEL Mux", "HP Mixer", "Left Headphone Mixer"},
1457
1458 /*
1459 * Disable this for lowest power if bypassing
1460 * the DAC with an analog signal
1461 */
1462 {"HP Left Out", NULL, "DACL"},
1463 {"HP Left Out", NULL, "MIXHPLSEL Mux"},
1464
1465 {"MIXHPRSEL Mux", "HP Mixer", "Right Headphone Mixer"},
1466
1467 /*
1468 * Disable this for lowest power if bypassing
1469 * the DAC with an analog signal
1470 */
1471 {"HP Right Out", NULL, "DACR"},
1472 {"HP Right Out", NULL, "MIXHPRSEL Mux"},
1473
1474 {"SPK Left Out", NULL, "Left Speaker Mixer"},
1475 {"SPK Right Out", NULL, "Right Speaker Mixer"},
1476 {"RCV Left Out", NULL, "Left Receiver Mixer"},
1477
1478 {"LINMOD Mux", "Left and Right", "Right Receiver Mixer"},
1479 {"LINMOD Mux", "Left Only", "Left Receiver Mixer"},
1480 {"RCV Right Out", NULL, "LINMOD Mux"},
1481
1482 {"HPL", NULL, "HP Left Out"},
1483 {"HPR", NULL, "HP Right Out"},
1484 {"SPKL", NULL, "SPK Left Out"},
1485 {"SPKR", NULL, "SPK Right Out"},
1486 {"RCVL", NULL, "RCV Left Out"},
1487 {"RCVR", NULL, "RCV Right Out"},
685e4215
JW		 1488};
1489
1490static const struct snd_soc_dapm_route max98091_dapm_routes[] = {
685e4215
JW		 1491 /* DMIC inputs */
1492 {"DMIC3", NULL, "DMIC3_ENA"},
1493 {"DMIC4", NULL, "DMIC4_ENA"},
1494 {"DMIC3", NULL, "AHPF"},
1495 {"DMIC4", NULL, "AHPF"},
685e4215
JW		 1496};
1497
1498static int max98090_add_widgets(struct snd_soc_codec *codec)
1499{
1500 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1501 struct snd_soc_dapm_context *dapm = &codec->dapm;
1502
1503 snd_soc_add_codec_controls(codec, max98090_snd_controls,
1504 ARRAY_SIZE(max98090_snd_controls));
1505
1506 if (max98090->devtype == MAX98091) {
1507 snd_soc_add_codec_controls(codec, max98091_snd_controls,
1508 ARRAY_SIZE(max98091_snd_controls));
1509 }
1510
1511 snd_soc_dapm_new_controls(dapm, max98090_dapm_widgets,
1512 ARRAY_SIZE(max98090_dapm_widgets));
1513
1514 snd_soc_dapm_add_routes(dapm, max98090_dapm_routes,
1515 ARRAY_SIZE(max98090_dapm_routes));
1516
1517 if (max98090->devtype == MAX98091) {
1518 snd_soc_dapm_new_controls(dapm, max98091_dapm_widgets,
1519 ARRAY_SIZE(max98091_dapm_widgets));
1520
1521 snd_soc_dapm_add_routes(dapm, max98091_dapm_routes,
1522 ARRAY_SIZE(max98091_dapm_routes));
685e4215
JW		 1523 }
1524
1525 return 0;
1526}
1527
1528static const int pclk_rates[] = {
1529 12000000, 12000000, 13000000, 13000000,
1530 16000000, 16000000, 19200000, 19200000
1531};
1532
1533static const int lrclk_rates[] = {
1534 8000, 16000, 8000, 16000,
1535 8000, 16000, 8000, 16000
1536};
1537
1538static const int user_pclk_rates[] = {
2c81a10a 1539 13000000, 13000000, 19200000, 19200000,
685e4215
JW		 1540};
1541
1542static const int user_lrclk_rates[] = {
2c81a10a 1543 44100, 48000, 44100, 48000,
685e4215
JW		 1544};
1545
1546static const unsigned long long ni_value[] = {
2c81a10a 1547 3528, 768, 441, 8
685e4215
JW		 1548};
1549
1550static const unsigned long long mi_value[] = {
2c81a10a 1551 8125, 1625, 1500, 25
685e4215
JW		 1552};
1553
1554static void max98090_configure_bclk(struct snd_soc_codec *codec)
1555{
1556 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1557 unsigned long long ni;
1558 int i;
1559
1560 if (!max98090->sysclk) {
1561 dev_err(codec->dev, "No SYSCLK configured\n");
1562 return;
1563 }
1564
1565 if (!max98090->bclk || !max98090->lrclk) {
1566 dev_err(codec->dev, "No audio clocks configured\n");
1567 return;
1568 }
1569
1570 /* Skip configuration when operating as slave */
1571 if (!(snd_soc_read(codec, M98090_REG_MASTER_MODE) &
1572 M98090_MAS_MASK)) {
1573 return;
1574 }
1575
1576 /* Check for supported PCLK to LRCLK ratios */
1577 for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) {
1578 if ((pclk_rates[i] == max98090->sysclk) &&
1579 (lrclk_rates[i] == max98090->lrclk)) {
1580 dev_dbg(codec->dev,
1581 "Found supported PCLK to LRCLK rates 0x%x\n",
1582 i + 0x8);
1583
1584 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1585 M98090_FREQ_MASK,
1586 (i + 0x8) << M98090_FREQ_SHIFT);
1587 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1588 M98090_USE_M1_MASK, 0);
1589 return;
1590 }
1591 }
1592
1593 /* Check for user calculated MI and NI ratios */
1594 for (i = 0; i < ARRAY_SIZE(user_pclk_rates); i++) {
1595 if ((user_pclk_rates[i] == max98090->sysclk) &&
1596 (user_lrclk_rates[i] == max98090->lrclk)) {
1597 dev_dbg(codec->dev,
1598 "Found user supported PCLK to LRCLK rates\n");
1599 dev_dbg(codec->dev, "i %d ni %lld mi %lld\n",
1600 i, ni_value[i], mi_value[i]);
1601
1602 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1603 M98090_FREQ_MASK, 0);
1604 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1605 M98090_USE_M1_MASK,
1606 1 << M98090_USE_M1_SHIFT);
1607
1608 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB,
1609 (ni_value[i] >> 8) & 0x7F);
1610 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB,
1611 ni_value[i] & 0xFF);
1612 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_MSB,
1613 (mi_value[i] >> 8) & 0x7F);
1614 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_LSB,
1615 mi_value[i] & 0xFF);
1616
1617 return;
1618 }
1619 }
1620
1621 /*
1622 * Calculate based on MI = 65536 (not as good as either method above)
1623 */
1624 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1625 M98090_FREQ_MASK, 0);
1626 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1627 M98090_USE_M1_MASK, 0);
1628
1629 /*
1630 * Configure NI when operating as master
1631 * Note: There is a small, but significant audio quality improvement
1632 * by calculating ni and mi.
1633 */
1634 ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL)
1635 * (unsigned long long int)max98090->lrclk;
1636 do_div(ni, (unsigned long long int)max98090->sysclk);
1637 dev_info(codec->dev, "No better method found\n");
1638 dev_info(codec->dev, "Calculating ni %lld with mi 65536\n", ni);
1639 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB,
1640 (ni >> 8) & 0x7F);
1641 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB, ni & 0xFF);
1642}
1643
1644static int max98090_dai_set_fmt(struct snd_soc_dai *codec_dai,
1645 unsigned int fmt)
1646{
1647 struct snd_soc_codec *codec = codec_dai->codec;
1648 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1649 struct max98090_cdata *cdata;
1650 u8 regval;
1651
1652 max98090->dai_fmt = fmt;
1653 cdata = &max98090->dai[0];
1654
1655 if (fmt != cdata->fmt) {
1656 cdata->fmt = fmt;
1657
1658 regval = 0;
1659 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1660 case SND_SOC_DAIFMT_CBS_CFS:
1661 /* Set to slave mode PLL - MAS mode off */
1662 snd_soc_write(codec,
1663 M98090_REG_CLOCK_RATIO_NI_MSB, 0x00);
1664 snd_soc_write(codec,
1665 M98090_REG_CLOCK_RATIO_NI_LSB, 0x00);
1666 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1667 M98090_USE_M1_MASK, 0);
541423dd 1668 max98090->master = false;
685e4215
JW		 1669 break;
1670 case SND_SOC_DAIFMT_CBM_CFM:
1671 /* Set to master mode */
1672 if (max98090->tdm_slots == 4) {
1673 /* TDM */
1674 regval |= M98090_MAS_MASK |
1675 M98090_BSEL_64;
1676 } else if (max98090->tdm_slots == 3) {
1677 /* TDM */
1678 regval |= M98090_MAS_MASK |
1679 M98090_BSEL_48;
1680 } else {
1681 /* Few TDM slots, or No TDM */
1682 regval |= M98090_MAS_MASK |
1683 M98090_BSEL_32;
1684 }
541423dd 1685 max98090->master = true;
685e4215
JW		 1686 break;
1687 case SND_SOC_DAIFMT_CBS_CFM:
1688 case SND_SOC_DAIFMT_CBM_CFS:
1689 default:
1690 dev_err(codec->dev, "DAI clock mode unsupported");
1691 return -EINVAL;
1692 }
1693 snd_soc_write(codec, M98090_REG_MASTER_MODE, regval);
1694
1695 regval = 0;
1696 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1697 case SND_SOC_DAIFMT_I2S:
1698 regval |= M98090_DLY_MASK;
1699 break;
1700 case SND_SOC_DAIFMT_LEFT_J:
1701 break;
1702 case SND_SOC_DAIFMT_RIGHT_J:
1703 regval |= M98090_RJ_MASK;
1704 break;
1705 case SND_SOC_DAIFMT_DSP_A:
1706 /* Not supported mode */
1707 default:
1708 dev_err(codec->dev, "DAI format unsupported");
1709 return -EINVAL;
1710 }
1711
1712 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1713 case SND_SOC_DAIFMT_NB_NF:
1714 break;
1715 case SND_SOC_DAIFMT_NB_IF:
1716 regval |= M98090_WCI_MASK;
1717 break;
1718 case SND_SOC_DAIFMT_IB_NF:
1719 regval |= M98090_BCI_MASK;
1720 break;
1721 case SND_SOC_DAIFMT_IB_IF:
1722 regval |= M98090_BCI_MASK|M98090_WCI_MASK;
1723 break;
1724 default:
1725 dev_err(codec->dev, "DAI invert mode unsupported");
1726 return -EINVAL;
1727 }
1728
1729 /*
1730 * This accommodates an inverted logic in the MAX98090 chip
1731 * for Bit Clock Invert (BCI). The inverted logic is only
1732 * seen for the case of TDM mode. The remaining cases have
1733 * normal logic.
1734 */
959b6250 1735 if (max98090->tdm_slots > 1)
685e4215 1736 regval ^= M98090_BCI_MASK;
685e4215
JW		 1737
1738 snd_soc_write(codec,
1739 M98090_REG_INTERFACE_FORMAT, regval);
1740 }
1741
1742 return 0;
1743}
1744
1745static int max98090_set_tdm_slot(struct snd_soc_dai *codec_dai,
1746 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1747{
1748 struct snd_soc_codec *codec = codec_dai->codec;
1749 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1750 struct max98090_cdata *cdata;
1751 cdata = &max98090->dai[0];
1752
1753 if (slots < 0 || slots > 4)
1754 return -EINVAL;
1755
1756 max98090->tdm_slots = slots;
1757 max98090->tdm_width = slot_width;
1758
1759 if (max98090->tdm_slots > 1) {
1760 /* SLOTL SLOTR SLOTDLY */
1761 snd_soc_write(codec, M98090_REG_TDM_FORMAT,
1762 0 << M98090_TDM_SLOTL_SHIFT |
1763 1 << M98090_TDM_SLOTR_SHIFT |
1764 0 << M98090_TDM_SLOTDLY_SHIFT);
1765
1766 /* FSW TDM */
1767 snd_soc_update_bits(codec, M98090_REG_TDM_CONTROL,
1768 M98090_TDM_MASK,
1769 M98090_TDM_MASK);
1770 }
1771
1772 /*
1773 * Normally advisable to set TDM first, but this permits either order
1774 */
1775 cdata->fmt = 0;
1776 max98090_dai_set_fmt(codec_dai, max98090->dai_fmt);
1777
1778 return 0;
1779}
1780
1781static int max98090_set_bias_level(struct snd_soc_codec *codec,
1782 enum snd_soc_bias_level level)
1783{
1784 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1785 int ret;
1786
1787 switch (level) {
1788 case SND_SOC_BIAS_ON:
685e4215
JW		 1789 break;
1790
1791 case SND_SOC_BIAS_PREPARE:
b10ab7b8
TB		 1792 /*
1793 * SND_SOC_BIAS_PREPARE is called while preparing for a
1794 * transition to ON or away from ON. If current bias_level
1795 * is SND_SOC_BIAS_ON, then it is preparing for a transition
1796 * away from ON. Disable the clock in that case, otherwise
1797 * enable it.
1798 */
1799 if (!IS_ERR(max98090->mclk)) {
1800 if (codec->dapm.bias_level == SND_SOC_BIAS_ON)
1801 clk_disable_unprepare(max98090->mclk);
1802 else
1803 clk_prepare_enable(max98090->mclk);
1804 }
685e4215
JW		 1805 break;
1806
1807 case SND_SOC_BIAS_STANDBY:
c42c8922
DR		 1808 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1809 ret = regcache_sync(max98090->regmap);
1810 if (ret != 0) {
1811 dev_err(codec->dev,
1812 "Failed to sync cache: %d\n", ret);
1813 return ret;
1814 }
1815 }
1816 break;
1817
685e4215
JW		 1818 case SND_SOC_BIAS_OFF:
1819 /* Set internal pull-up to lowest power mode */
1820 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
1821 M98090_JDWK_MASK, M98090_JDWK_MASK);
1822 regcache_mark_dirty(max98090->regmap);
1823 break;
1824 }
1825 codec->dapm.bias_level = level;
1826 return 0;
1827}
1828
defcd98b 1829static const int dmic_divisors[] = { 2, 3, 4, 5, 6, 8 };
685e4215
JW		 1830
1831static const int comp_lrclk_rates[] = {
1832 8000, 16000, 32000, 44100, 48000, 96000
1833};
1834
defcd98b
DR		 1835struct dmic_table {
1836 int pclk;
1837 struct {
1838 int freq;
1839 int comp[6]; /* One each for 8, 16, 32, 44.1, 48, and 96 kHz */
1840 } settings[6]; /* One for each dmic divisor. */
685e4215
JW		 1841};
1842
defcd98b
DR		 1843static const struct dmic_table dmic_table[] = { /* One for each pclk freq. */
1844 {
1845 .pclk = 11289600,
1846 .settings = {
1847 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1848 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1849 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1850 { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } },
1851 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1852 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1853 },
1854 },
1855 {
1856 .pclk = 12000000,
1857 .settings = {
1858 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1859 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1860 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1861 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1862 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1863 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1864 }
1865 },
1866 {
1867 .pclk = 12288000,
1868 .settings = {
1869 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1870 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1871 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1872 { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } },
1873 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1874 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1875 }
1876 },
1877 {
1878 .pclk = 13000000,
1879 .settings = {
1880 { .freq = 2, .comp = { 7, 8, 1, 1, 1, 1 } },
1881 { .freq = 1, .comp = { 7, 8, 0, 0, 0, 0 } },
1882 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1883 { .freq = 0, .comp = { 7, 8, 4, 4, 5, 5 } },
1884 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1885 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1886 }
1887 },
1888 {
1889 .pclk = 19200000,
1890 .settings = {
1891 { .freq = 2, .comp = { 0, 0, 0, 0, 0, 0 } },
1892 { .freq = 1, .comp = { 7, 8, 1, 1, 1, 1 } },
1893 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1894 { .freq = 0, .comp = { 7, 8, 2, 2, 3, 3 } },
1895 { .freq = 0, .comp = { 7, 8, 1, 1, 2, 2 } },
1896 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1897 }
1898 },
1899};
1900
1901static int max98090_find_divisor(int target_freq, int pclk)
1902{
1903 int current_diff = INT_MAX;
1904 int test_diff = INT_MAX;
1905 int divisor_index = 0;
1906 int i;
1907
1908 for (i = 0; i < ARRAY_SIZE(dmic_divisors); i++) {
1909 test_diff = abs(target_freq - (pclk / dmic_divisors[i]));
1910 if (test_diff < current_diff) {
1911 current_diff = test_diff;
1912 divisor_index = i;
1913 }
1914 }
1915
1916 return divisor_index;
1917}
1918
1919static int max98090_find_closest_pclk(int pclk)
1920{
1921 int m1;
1922 int m2;
1923 int i;
1924
1925 for (i = 0; i < ARRAY_SIZE(dmic_table); i++) {
1926 if (pclk == dmic_table[i].pclk)
1927 return i;
1928 if (pclk < dmic_table[i].pclk) {
1929 if (i == 0)
1930 return i;
1931 m1 = pclk - dmic_table[i-1].pclk;
1932 m2 = dmic_table[i].pclk - pclk;
1933 if (m1 < m2)
1934 return i - 1;
1935 else
1936 return i;
1937 }
1938 }
1939
1940 return -EINVAL;
1941}
1942
1943static int max98090_configure_dmic(struct max98090_priv *max98090,
1944 int target_dmic_clk, int pclk, int fs)
1945{
1946 int micclk_index;
1947 int pclk_index;
1948 int dmic_freq;
1949 int dmic_comp;
1950 int i;
1951
1952 pclk_index = max98090_find_closest_pclk(pclk);
1953 if (pclk_index < 0)
1954 return pclk_index;
1955
1956 micclk_index = max98090_find_divisor(target_dmic_clk, pclk);
1957
1958 for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) {
1959 if (fs <= (comp_lrclk_rates[i] + comp_lrclk_rates[i+1]) / 2)
1960 break;
1961 }
1962
1963 dmic_freq = dmic_table[pclk_index].settings[micclk_index].freq;
1964 dmic_comp = dmic_table[pclk_index].settings[micclk_index].comp[i];
1965
1966 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_ENABLE,
1967 M98090_MICCLK_MASK,
1968 micclk_index << M98090_MICCLK_SHIFT);
1969
1970 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_CONFIG,
1971 M98090_DMIC_COMP_MASK | M98090_DMIC_FREQ_MASK,
1972 dmic_comp << M98090_DMIC_COMP_SHIFT |
1973 dmic_freq << M98090_DMIC_FREQ_SHIFT);
1974
1975 return 0;
1976}
1977
685e4215
JW		 1978static int max98090_dai_hw_params(struct snd_pcm_substream *substream,
1979 struct snd_pcm_hw_params *params,
1980 struct snd_soc_dai *dai)
1981{
1982 struct snd_soc_codec *codec = dai->codec;
1983 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1984 struct max98090_cdata *cdata;
685e4215
JW		 1985
1986 cdata = &max98090->dai[0];
1987 max98090->bclk = snd_soc_params_to_bclk(params);
1988 if (params_channels(params) == 1)
1989 max98090->bclk *= 2;
1990
1991 max98090->lrclk = params_rate(params);
1992
7821afc4
MB		 1993 switch (params_width(params)) {
1994 case 16:
685e4215
JW		 1995 snd_soc_update_bits(codec, M98090_REG_INTERFACE_FORMAT,
1996 M98090_WS_MASK, 0);
1997 break;
1998 default:
1999 return -EINVAL;
2000 }
2001
541423dd
LG		 2002 if (max98090->master)
2003 max98090_configure_bclk(codec);
685e4215
JW		 2004
2005 cdata->rate = max98090->lrclk;
2006
2007 /* Update filter mode */
2008 if (max98090->lrclk < 24000)
2009 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
2010 M98090_MODE_MASK, 0);
2011 else
2012 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
2013 M98090_MODE_MASK, M98090_MODE_MASK);
2014
2015 /* Update sample rate mode */
2016 if (max98090->lrclk < 50000)
2017 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
2018 M98090_DHF_MASK, 0);
2019 else
2020 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
2021 M98090_DHF_MASK, M98090_DHF_MASK);
2022
defcd98b
DR		 2023 max98090_configure_dmic(max98090, max98090->dmic_freq, max98090->pclk,
2024 max98090->lrclk);
685e4215
JW		 2025
2026 return 0;
2027}
2028
2029/*
2030 * PLL / Sysclk
2031 */
2032static int max98090_dai_set_sysclk(struct snd_soc_dai *dai,
2033 int clk_id, unsigned int freq, int dir)
2034{
2035 struct snd_soc_codec *codec = dai->codec;
2036 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2037
2038 /* Requested clock frequency is already setup */
2039 if (freq == max98090->sysclk)
2040 return 0;
2041
b10ab7b8
TB		 2042 if (!IS_ERR(max98090->mclk)) {
2043 freq = clk_round_rate(max98090->mclk, freq);
2044 clk_set_rate(max98090->mclk, freq);
2045 }
2046
685e4215
JW		 2047 /* Setup clocks for slave mode, and using the PLL
2048 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
2049 * 0x02 (when master clk is 20MHz to 40MHz)..
2050 * 0x03 (when master clk is 40MHz to 60MHz)..
2051 */
ece509c1 2052 if ((freq >= 10000000) && (freq <= 20000000)) {
685e4215
JW		 2053 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
2054 M98090_PSCLK_DIV1);
defcd98b 2055 max98090->pclk = freq;
ece509c1 2056 } else if ((freq > 20000000) && (freq <= 40000000)) {
685e4215
JW		 2057 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
2058 M98090_PSCLK_DIV2);
defcd98b 2059 max98090->pclk = freq >> 1;
ece509c1 2060 } else if ((freq > 40000000) && (freq <= 60000000)) {
685e4215
JW		 2061 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
2062 M98090_PSCLK_DIV4);
defcd98b 2063 max98090->pclk = freq >> 2;
685e4215
JW		 2064 } else {
2065 dev_err(codec->dev, "Invalid master clock frequency\n");
2066 return -EINVAL;
2067 }
2068
2069 max98090->sysclk = freq;
2070
685e4215
JW		 2071 return 0;
2072}
2073
2074static int max98090_dai_digital_mute(struct snd_soc_dai *codec_dai, int mute)
2075{
2076 struct snd_soc_codec *codec = codec_dai->codec;
2077 int regval;
2078
2079 regval = mute ? M98090_DVM_MASK : 0;
2080 snd_soc_update_bits(codec, M98090_REG_DAI_PLAYBACK_LEVEL,
2081 M98090_DVM_MASK, regval);
2082
2083 return 0;
2084}
2085
b8a3ee82
JN		 2086static int max98090_dai_trigger(struct snd_pcm_substream *substream, int cmd,
2087 struct snd_soc_dai *dai)
2088{
2089 struct snd_soc_codec *codec = dai->codec;
2090 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2091
2092 switch (cmd) {
2093 case SNDRV_PCM_TRIGGER_START:
2094 case SNDRV_PCM_TRIGGER_RESUME:
2095 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2096 if (!max98090->master && dai->active == 1)
2097 queue_delayed_work(system_power_efficient_wq,
2098 &max98090->pll_det_enable_work,
2099 msecs_to_jiffies(10));
2100 break;
2101 case SNDRV_PCM_TRIGGER_STOP:
2102 case SNDRV_PCM_TRIGGER_SUSPEND:
2103 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2104 if (!max98090->master && dai->active == 1)
2105 schedule_work(&max98090->pll_det_disable_work);
2106 break;
2107 default:
2108 break;
2109 }
2110
2111 return 0;
2112}
2113
2114static void max98090_pll_det_enable_work(struct work_struct *work)
2115{
2116 struct max98090_priv *max98090 =
2117 container_of(work, struct max98090_priv,
2118 pll_det_enable_work.work);
2119 struct snd_soc_codec *codec = max98090->codec;
2120 unsigned int status, mask;
2121
2122 /*
2123 * Clear status register in order to clear possibly already occurred
2124 * PLL unlock. If PLL hasn't still locked, the status will be set
2125 * again and PLL unlock interrupt will occur.
2126 * Note this will clear all status bits
2127 */
2128 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status);
2129
2130 /*
2131 * Queue jack work in case jack state has just changed but handler
2132 * hasn't run yet
2133 */
2134 regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
2135 status &= mask;
2136 if (status & M98090_JDET_MASK)
2137 queue_delayed_work(system_power_efficient_wq,
2138 &max98090->jack_work,
2139 msecs_to_jiffies(100));
2140
2141 /* Enable PLL unlock interrupt */
2142 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2143 M98090_IULK_MASK,
2144 1 << M98090_IULK_SHIFT);
2145}
2146
2147static void max98090_pll_det_disable_work(struct work_struct *work)
2148{
2149 struct max98090_priv *max98090 =
2150 container_of(work, struct max98090_priv, pll_det_disable_work);
2151 struct snd_soc_codec *codec = max98090->codec;
2152
2153 cancel_delayed_work_sync(&max98090->pll_det_enable_work);
2154
2155 /* Disable PLL unlock interrupt */
2156 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2157 M98090_IULK_MASK, 0);
2158}
2159
2160static void max98090_pll_work(struct work_struct *work)
2161{
2162 struct max98090_priv *max98090 =
2163 container_of(work, struct max98090_priv, pll_work);
2164 struct snd_soc_codec *codec = max98090->codec;
2165
2166 if (!snd_soc_codec_is_active(codec))
2167 return;
2168
2169 dev_info(codec->dev, "PLL unlocked\n");
2170
2171 /* Toggle shutdown OFF then ON */
2172 snd_soc_update_bits(codec, M98090_REG_DEVICE_SHUTDOWN,
2173 M98090_SHDNN_MASK, 0);
2174 msleep(10);
2175 snd_soc_update_bits(codec, M98090_REG_DEVICE_SHUTDOWN,
2176 M98090_SHDNN_MASK, M98090_SHDNN_MASK);
2177
2178 /* Give PLL time to lock */
2179 msleep(10);
2180}
2181
685e4215
JW		 2182static void max98090_jack_work(struct work_struct *work)
2183{
2184 struct max98090_priv *max98090 = container_of(work,
2185 struct max98090_priv,
2186 jack_work.work);
2187 struct snd_soc_codec *codec = max98090->codec;
2188 struct snd_soc_dapm_context *dapm = &codec->dapm;
2189 int status = 0;
2190 int reg;
2191
2192 /* Read a second time */
2193 if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) {
2194
2195 /* Strong pull up allows mic detection */
2196 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
2197 M98090_JDWK_MASK, 0);
2198
2199 msleep(50);
2200
2201 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
2202
2203 /* Weak pull up allows only insertion detection */
2204 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
2205 M98090_JDWK_MASK, M98090_JDWK_MASK);
2206 } else {
2207 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
2208 }
2209
2210 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
2211
2212 switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) {
2213 case M98090_LSNS_MASK | M98090_JKSNS_MASK:
2214 dev_dbg(codec->dev, "No Headset Detected\n");
2215
2216 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
2217
2218 status |= 0;
2219
2220 break;
2221
2222 case 0:
2223 if (max98090->jack_state ==
2224 M98090_JACK_STATE_HEADSET) {
2225
2226 dev_dbg(codec->dev,
2227 "Headset Button Down Detected\n");
2228
2229 /*
2230 * max98090_headset_button_event(codec)
2231 * could be defined, then called here.
2232 */
2233
2234 status |= SND_JACK_HEADSET;
2235 status |= SND_JACK_BTN_0;
2236
2237 break;
2238 }
2239
2240 /* Line is reported as Headphone */
2241 /* Nokia Headset is reported as Headphone */
2242 /* Mono Headphone is reported as Headphone */
2243 dev_dbg(codec->dev, "Headphone Detected\n");
2244
2245 max98090->jack_state = M98090_JACK_STATE_HEADPHONE;
2246
2247 status |= SND_JACK_HEADPHONE;
2248
2249 break;
2250
2251 case M98090_JKSNS_MASK:
2252 dev_dbg(codec->dev, "Headset Detected\n");
2253
2254 max98090->jack_state = M98090_JACK_STATE_HEADSET;
2255
2256 status |= SND_JACK_HEADSET;
2257
2258 break;
2259
2260 default:
2261 dev_dbg(codec->dev, "Unrecognized Jack Status\n");
2262 break;
2263 }
2264
2265 snd_soc_jack_report(max98090->jack, status,
2266 SND_JACK_HEADSET | SND_JACK_BTN_0);
2267
2268 snd_soc_dapm_sync(dapm);
2269}
2270
2271static irqreturn_t max98090_interrupt(int irq, void *data)
2272{
7a7f0ba0
JN		 2273 struct max98090_priv *max98090 = data;
2274 struct snd_soc_codec *codec = max98090->codec;
685e4215
JW		 2275 int ret;
2276 unsigned int mask;
2277 unsigned int active;
2278
7a7f0ba0
JN		 2279 /* Treat interrupt before codec is initialized as spurious */
2280 if (codec == NULL)
2281 return IRQ_NONE;
2282
685e4215
JW		 2283 dev_dbg(codec->dev, "***** max98090_interrupt *****\n");
2284
2285 ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
2286
2287 if (ret != 0) {
2288 dev_err(codec->dev,
2289 "failed to read M98090_REG_INTERRUPT_S: %d\n",
2290 ret);
2291 return IRQ_NONE;
2292 }
2293
2294 ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active);
2295
2296 if (ret != 0) {
2297 dev_err(codec->dev,
2298 "failed to read M98090_REG_DEVICE_STATUS: %d\n",
2299 ret);
2300 return IRQ_NONE;
2301 }
2302
2303 dev_dbg(codec->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n",
2304 active, mask, active & mask);
2305
2306 active &= mask;
2307
2308 if (!active)
2309 return IRQ_NONE;
2310
959b6250 2311 if (active & M98090_CLD_MASK)
685e4215 2312 dev_err(codec->dev, "M98090_CLD_MASK\n");
685e4215 2313
959b6250 2314 if (active & M98090_SLD_MASK)
685e4215 2315 dev_dbg(codec->dev, "M98090_SLD_MASK\n");
685e4215 2316
b8a3ee82
JN		 2317 if (active & M98090_ULK_MASK) {
2318 dev_dbg(codec->dev, "M98090_ULK_MASK\n");
2319 schedule_work(&max98090->pll_work);
2320 }
685e4215
JW		 2321
2322 if (active & M98090_JDET_MASK) {
2323 dev_dbg(codec->dev, "M98090_JDET_MASK\n");
2324
2325 pm_wakeup_event(codec->dev, 100);
2326
2df7c6aa
MB		 2327 queue_delayed_work(system_power_efficient_wq,
2328 &max98090->jack_work,
2329 msecs_to_jiffies(100));
685e4215
JW		 2330 }
2331
959b6250 2332 if (active & M98090_DRCACT_MASK)
685e4215 2333 dev_dbg(codec->dev, "M98090_DRCACT_MASK\n");
685e4215 2334
959b6250 2335 if (active & M98090_DRCCLP_MASK)
685e4215 2336 dev_err(codec->dev, "M98090_DRCCLP_MASK\n");
685e4215
JW		 2337
2338 return IRQ_HANDLED;
2339}
2340
2341/**
2342 * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ
2343 *
2344 * @codec: MAX98090 codec
2345 * @jack: jack to report detection events on
2346 *
2347 * Enable microphone detection via IRQ on the MAX98090. If GPIOs are
2348 * being used to bring out signals to the processor then only platform
2349 * data configuration is needed for MAX98090 and processor GPIOs should
2350 * be configured using snd_soc_jack_add_gpios() instead.
2351 *
2352 * If no jack is supplied detection will be disabled.
2353 */
2354int max98090_mic_detect(struct snd_soc_codec *codec,
2355 struct snd_soc_jack *jack)
2356{
2357 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2358
2359 dev_dbg(codec->dev, "max98090_mic_detect\n");
2360
2361 max98090->jack = jack;
2362 if (jack) {
2363 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2364 M98090_IJDET_MASK,
2365 1 << M98090_IJDET_SHIFT);
2366 } else {
2367 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2368 M98090_IJDET_MASK,
2369 0);
2370 }
2371
2372 /* Send an initial empty report */
2373 snd_soc_jack_report(max98090->jack, 0,
2374 SND_JACK_HEADSET | SND_JACK_BTN_0);
2375
2df7c6aa
MB		 2376 queue_delayed_work(system_power_efficient_wq,
2377 &max98090->jack_work,
2378 msecs_to_jiffies(100));
685e4215
JW		 2379
2380 return 0;
2381}
2382EXPORT_SYMBOL_GPL(max98090_mic_detect);
2383
2384#define MAX98090_RATES SNDRV_PCM_RATE_8000_96000
2385#define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
2386
2387static struct snd_soc_dai_ops max98090_dai_ops = {
2388 .set_sysclk = max98090_dai_set_sysclk,
2389 .set_fmt = max98090_dai_set_fmt,
2390 .set_tdm_slot = max98090_set_tdm_slot,
2391 .hw_params = max98090_dai_hw_params,
2392 .digital_mute = max98090_dai_digital_mute,
b8a3ee82 2393 .trigger = max98090_dai_trigger,
685e4215
JW		 2394};
2395
2396static struct snd_soc_dai_driver max98090_dai[] = {
2397{
2398 .name = "HiFi",
2399 .playback = {
2400 .stream_name = "HiFi Playback",
2401 .channels_min = 2,
2402 .channels_max = 2,
2403 .rates = MAX98090_RATES,
2404 .formats = MAX98090_FORMATS,
2405 },
2406 .capture = {
2407 .stream_name = "HiFi Capture",
2408 .channels_min = 1,
2409 .channels_max = 2,
2410 .rates = MAX98090_RATES,
2411 .formats = MAX98090_FORMATS,
2412 },
2413 .ops = &max98090_dai_ops,
2414}
2415};
2416
685e4215
JW		 2417static int max98090_probe(struct snd_soc_codec *codec)
2418{
2419 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2420 struct max98090_cdata *cdata;
978b641f 2421 enum max98090_type devtype;
685e4215
JW		 2422 int ret = 0;
2423
2424 dev_dbg(codec->dev, "max98090_probe\n");
2425
b10ab7b8
TB		 2426 max98090->mclk = devm_clk_get(codec->dev, "mclk");
2427 if (PTR_ERR(max98090->mclk) == -EPROBE_DEFER)
2428 return -EPROBE_DEFER;
2429
685e4215
JW		 2430 max98090->codec = codec;
2431
685e4215
JW		 2432 /* Reset the codec, the DSP core, and disable all interrupts */
2433 max98090_reset(max98090);
2434
2435 /* Initialize private data */
2436
2437 max98090->sysclk = (unsigned)-1;
defcd98b 2438 max98090->pclk = (unsigned)-1;
541423dd 2439 max98090->master = false;
685e4215
JW		 2440
2441 cdata = &max98090->dai[0];
2442 cdata->rate = (unsigned)-1;
2443 cdata->fmt = (unsigned)-1;
2444
2445 max98090->lin_state = 0;
2446 max98090->pa1en = 0;
2447 max98090->pa2en = 0;
685e4215
JW		 2448
2449 ret = snd_soc_read(codec, M98090_REG_REVISION_ID);
2450 if (ret < 0) {
2451 dev_err(codec->dev, "Failed to read device revision: %d\n",
2452 ret);
2453 goto err_access;
2454 }
2455
2456 if ((ret >= M98090_REVA) && (ret <= M98090_REVA + 0x0f)) {
978b641f 2457 devtype = MAX98090;
685e4215
JW		 2458 dev_info(codec->dev, "MAX98090 REVID=0x%02x\n", ret);
2459 } else if ((ret >= M98091_REVA) && (ret <= M98091_REVA + 0x0f)) {
978b641f 2460 devtype = MAX98091;
685e4215
JW		 2461 dev_info(codec->dev, "MAX98091 REVID=0x%02x\n", ret);
2462 } else {
978b641f 2463 devtype = MAX98090;
685e4215
JW		 2464 dev_err(codec->dev, "Unrecognized revision 0x%02x\n", ret);
2465 }
2466
978b641f
TB		 2467 if (max98090->devtype != devtype) {
2468 dev_warn(codec->dev, "Mismatch in DT specified CODEC type.\n");
2469 max98090->devtype = devtype;
2470 }
2471
685e4215
JW		 2472 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
2473
2474 INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work);
b8a3ee82
JN		 2475 INIT_DELAYED_WORK(&max98090->pll_det_enable_work,
2476 max98090_pll_det_enable_work);
2477 INIT_WORK(&max98090->pll_det_disable_work,
2478 max98090_pll_det_disable_work);
2479 INIT_WORK(&max98090->pll_work, max98090_pll_work);
685e4215
JW		 2480
2481 /* Enable jack detection */
2482 snd_soc_write(codec, M98090_REG_JACK_DETECT,
2483 M98090_JDETEN_MASK | M98090_JDEB_25MS);
2484
685e4215
JW		 2485 /*
2486 * Clear any old interrupts.
2487 * An old interrupt ocurring prior to installing the ISR
2488 * can keep a new interrupt from generating a trigger.
2489 */
2490 snd_soc_read(codec, M98090_REG_DEVICE_STATUS);
2491
2492 /* High Performance is default */
2493 snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL,
2494 M98090_DACHP_MASK,
2495 1 << M98090_DACHP_SHIFT);
2496 snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL,
2497 M98090_PERFMODE_MASK,
2498 0 << M98090_PERFMODE_SHIFT);
2499 snd_soc_update_bits(codec, M98090_REG_ADC_CONTROL,
2500 M98090_ADCHP_MASK,
2501 1 << M98090_ADCHP_SHIFT);
2502
2503 /* Turn on VCM bandgap reference */
2504 snd_soc_write(codec, M98090_REG_BIAS_CONTROL,
2505 M98090_VCM_MODE_MASK);
2506
a735d992
JN		 2507 snd_soc_update_bits(codec, M98090_REG_MIC_BIAS_VOLTAGE,
2508 M98090_MBVSEL_MASK, M98090_MBVSEL_2V8);
2509
685e4215
JW		 2510 max98090_add_widgets(codec);
2511
2512err_access:
2513 return ret;
2514}
2515
2516static int max98090_remove(struct snd_soc_codec *codec)
2517{
2518 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2519
2520 cancel_delayed_work_sync(&max98090->jack_work);
b8a3ee82
JN		 2521 cancel_delayed_work_sync(&max98090->pll_det_enable_work);
2522 cancel_work_sync(&max98090->pll_det_disable_work);
2523 cancel_work_sync(&max98090->pll_work);
7a7f0ba0 2524 max98090->codec = NULL;
685e4215
JW		 2525
2526 return 0;
2527}
2528
2529static struct snd_soc_codec_driver soc_codec_dev_max98090 = {
2530 .probe = max98090_probe,
2531 .remove = max98090_remove,
2532 .set_bias_level = max98090_set_bias_level,
2533};
2534
2535static const struct regmap_config max98090_regmap = {
2536 .reg_bits = 8,
2537 .val_bits = 8,
2538
2539 .max_register = MAX98090_MAX_REGISTER,
2540 .reg_defaults = max98090_reg,
2541 .num_reg_defaults = ARRAY_SIZE(max98090_reg),
2542 .volatile_reg = max98090_volatile_register,
2543 .readable_reg = max98090_readable_register,
2544 .cache_type = REGCACHE_RBTREE,
2545};
2546
2547static int max98090_i2c_probe(struct i2c_client *i2c,
70f29d38 2548 const struct i2c_device_id *i2c_id)
685e4215
JW		 2549{
2550 struct max98090_priv *max98090;
70f29d38
JN		 2551 const struct acpi_device_id *acpi_id;
2552 kernel_ulong_t driver_data = 0;
685e4215
JW		 2553 int ret;
2554
2555 pr_debug("max98090_i2c_probe\n");
2556
2557 max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv),
2558 GFP_KERNEL);
2559 if (max98090 == NULL)
2560 return -ENOMEM;
2561
70f29d38
JN		 2562 if (ACPI_HANDLE(&i2c->dev)) {
2563 acpi_id = acpi_match_device(i2c->dev.driver->acpi_match_table,
2564 &i2c->dev);
2565 if (!acpi_id) {
2566 dev_err(&i2c->dev, "No driver data\n");
2567 return -EINVAL;
2568 }
2569 driver_data = acpi_id->driver_data;
2570 } else if (i2c_id) {
2571 driver_data = i2c_id->driver_data;
2572 }
2573
2574 max98090->devtype = driver_data;
685e4215 2575 i2c_set_clientdata(i2c, max98090);
685e4215 2576 max98090->pdata = i2c->dev.platform_data;
685e4215 2577
defcd98b
DR		 2578 ret = of_property_read_u32(i2c->dev.of_node, "maxim,dmic-freq",
2579 &max98090->dmic_freq);
2580 if (ret < 0)
2581 max98090->dmic_freq = MAX98090_DEFAULT_DMIC_FREQ;
2582
a3a6cc84 2583 max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap);
685e4215
JW		 2584 if (IS_ERR(max98090->regmap)) {
2585 ret = PTR_ERR(max98090->regmap);
2586 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
2587 goto err_enable;
2588 }
2589
ced1933d 2590 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
7a7f0ba0
JN		 2591 max98090_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
2592 "max98090_interrupt", max98090);
2593 if (ret < 0) {
2594 dev_err(&i2c->dev, "request_irq failed: %d\n",
2595 ret);
2596 return ret;
2597 }
2598
685e4215
JW		 2599 ret = snd_soc_register_codec(&i2c->dev,
2600 &soc_codec_dev_max98090, max98090_dai,
2601 ARRAY_SIZE(max98090_dai));
685e4215
JW		 2602err_enable:
2603 return ret;
2604}
2605
2606static int max98090_i2c_remove(struct i2c_client *client)
2607{
685e4215 2608 snd_soc_unregister_codec(&client->dev);
685e4215
JW		 2609 return 0;
2610}
2611
3722dc8e 2612#ifdef CONFIG_PM_RUNTIME
685e4215
JW		 2613static int max98090_runtime_resume(struct device *dev)
2614{
2615 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2616
2617 regcache_cache_only(max98090->regmap, false);
2618
25b4ab43
LG		 2619 max98090_reset(max98090);
2620
685e4215
JW		 2621 regcache_sync(max98090->regmap);
2622
2623 return 0;
2624}
2625
2626static int max98090_runtime_suspend(struct device *dev)
2627{
2628 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2629
2630 regcache_cache_only(max98090->regmap, true);
2631
2632 return 0;
2633}
3722dc8e 2634#endif
685e4215 2635
121eb444 2636#ifdef CONFIG_PM_SLEEP
46b0e97d
LG		 2637static int max98090_resume(struct device *dev)
2638{
2639 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2640 unsigned int status;
2641
f1c0bc91
LG		 2642 regcache_mark_dirty(max98090->regmap);
2643
46b0e97d
LG		 2644 max98090_reset(max98090);
2645
2646 /* clear IRQ status */
2647 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status);
2648
2649 regcache_sync(max98090->regmap);
2650
2651 return 0;
2652}
2653
2654static int max98090_suspend(struct device *dev)
2655{
2656 return 0;
2657}
2658#endif
2659
3e12af7e 2660static const struct dev_pm_ops max98090_pm = {
685e4215
JW		 2661 SET_RUNTIME_PM_OPS(max98090_runtime_suspend,
2662 max98090_runtime_resume, NULL)
46b0e97d 2663 SET_SYSTEM_SLEEP_PM_OPS(max98090_suspend, max98090_resume)
685e4215
JW		 2664};
2665
2666static const struct i2c_device_id max98090_i2c_id[] = {
2667 { "max98090", MAX98090 },
053e69d5 2668 { "max98091", MAX98091 },
685e4215
JW		 2669 { }
2670};
2671MODULE_DEVICE_TABLE(i2c, max98090_i2c_id);
2672
2951f93f
SW		 2673static const struct of_device_id max98090_of_match[] = {
2674 { .compatible = "maxim,max98090", },
053e69d5 2675 { .compatible = "maxim,max98091", },
2951f93f
SW		 2676 { }
2677};
2678MODULE_DEVICE_TABLE(of, max98090_of_match);
2679
70f29d38
JN		 2680#ifdef CONFIG_ACPI
2681static struct acpi_device_id max98090_acpi_match[] = {
2682 { "193C9890", MAX98090 },
2683 { }
2684};
2685MODULE_DEVICE_TABLE(acpi, max98090_acpi_match);
2686#endif
2687
685e4215
JW		 2688static struct i2c_driver max98090_i2c_driver = {
2689 .driver = {
2690 .name = "max98090",
2691 .owner = THIS_MODULE,
2692 .pm = &max98090_pm,
2951f93f 2693 .of_match_table = of_match_ptr(max98090_of_match),
70f29d38 2694 .acpi_match_table = ACPI_PTR(max98090_acpi_match),
685e4215
JW		 2695 },
2696 .probe = max98090_i2c_probe,
2697 .remove = max98090_i2c_remove,
2698 .id_table = max98090_i2c_id,
2699};
2700
2701module_i2c_driver(max98090_i2c_driver);
2702
2703MODULE_DESCRIPTION("ALSA SoC MAX98090 driver");
2704MODULE_AUTHOR("Peter Hsiang, Jesse Marroqin, Jerry Wong");
2705MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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