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ASoC: max98090: Replace direct snd_soc_codec dapm field access
[deliverable/linux.git] / sound / soc / codecs / max98095.c
CommitLineData
82a5a936
PH		 1/*
2 * max98095.c -- MAX98095 ALSA SoC Audio driver
3 *
4 * Copyright 2011 Maxim Integrated Products
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
e3048c3d 18#include <linux/clk.h>
210a5fae 19#include <linux/mutex.h>
82a5a936
PH		 20#include <sound/core.h>
21#include <sound/pcm.h>
22#include <sound/pcm_params.h>
23#include <sound/soc.h>
24#include <sound/initval.h>
25#include <sound/tlv.h>
26#include <linux/slab.h>
27#include <asm/div64.h>
28#include <sound/max98095.h>
9dd90c5d 29#include <sound/jack.h>
82a5a936
PH		 30#include "max98095.h"
31
32enum max98095_type {
33 MAX98095,
34};
35
36struct max98095_cdata {
37 unsigned int rate;
38 unsigned int fmt;
dad31ec1
PH		 39 int eq_sel;
40 int bq_sel;
82a5a936
PH		 41};
42
43struct max98095_priv {
14acbbbb 44 struct regmap *regmap;
82a5a936 45 enum max98095_type devtype;
82a5a936 46 struct max98095_pdata *pdata;
e3048c3d 47 struct clk *mclk;
82a5a936
PH		 48 unsigned int sysclk;
49 struct max98095_cdata dai[3];
dad31ec1
PH		 50 const char **eq_texts;
51 const char **bq_texts;
52 struct soc_enum eq_enum;
53 struct soc_enum bq_enum;
54 int eq_textcnt;
55 int bq_textcnt;
82a5a936
PH		 56 u8 lin_state;
57 unsigned int mic1pre;
58 unsigned int mic2pre;
9dd90c5d
RK		 59 struct snd_soc_jack *headphone_jack;
60 struct snd_soc_jack *mic_jack;
210a5fae 61 struct mutex lock;
82a5a936
PH		 62};
63
14acbbbb
MB		 64static const struct reg_default max98095_reg_def[] = {
65 { 0xf, 0x00 }, /* 0F */
66 { 0x10, 0x00 }, /* 10 */
67 { 0x11, 0x00 }, /* 11 */
68 { 0x12, 0x00 }, /* 12 */
69 { 0x13, 0x00 }, /* 13 */
70 { 0x14, 0x00 }, /* 14 */
71 { 0x15, 0x00 }, /* 15 */
72 { 0x16, 0x00 }, /* 16 */
73 { 0x17, 0x00 }, /* 17 */
74 { 0x18, 0x00 }, /* 18 */
75 { 0x19, 0x00 }, /* 19 */
76 { 0x1a, 0x00 }, /* 1A */
77 { 0x1b, 0x00 }, /* 1B */
78 { 0x1c, 0x00 }, /* 1C */
79 { 0x1d, 0x00 }, /* 1D */
80 { 0x1e, 0x00 }, /* 1E */
81 { 0x1f, 0x00 }, /* 1F */
82 { 0x20, 0x00 }, /* 20 */
83 { 0x21, 0x00 }, /* 21 */
84 { 0x22, 0x00 }, /* 22 */
85 { 0x23, 0x00 }, /* 23 */
86 { 0x24, 0x00 }, /* 24 */
87 { 0x25, 0x00 }, /* 25 */
88 { 0x26, 0x00 }, /* 26 */
89 { 0x27, 0x00 }, /* 27 */
90 { 0x28, 0x00 }, /* 28 */
91 { 0x29, 0x00 }, /* 29 */
92 { 0x2a, 0x00 }, /* 2A */
93 { 0x2b, 0x00 }, /* 2B */
94 { 0x2c, 0x00 }, /* 2C */
95 { 0x2d, 0x00 }, /* 2D */
96 { 0x2e, 0x00 }, /* 2E */
97 { 0x2f, 0x00 }, /* 2F */
98 { 0x30, 0x00 }, /* 30 */
99 { 0x31, 0x00 }, /* 31 */
100 { 0x32, 0x00 }, /* 32 */
101 { 0x33, 0x00 }, /* 33 */
102 { 0x34, 0x00 }, /* 34 */
103 { 0x35, 0x00 }, /* 35 */
104 { 0x36, 0x00 }, /* 36 */
105 { 0x37, 0x00 }, /* 37 */
106 { 0x38, 0x00 }, /* 38 */
107 { 0x39, 0x00 }, /* 39 */
108 { 0x3a, 0x00 }, /* 3A */
109 { 0x3b, 0x00 }, /* 3B */
110 { 0x3c, 0x00 }, /* 3C */
111 { 0x3d, 0x00 }, /* 3D */
112 { 0x3e, 0x00 }, /* 3E */
113 { 0x3f, 0x00 }, /* 3F */
114 { 0x40, 0x00 }, /* 40 */
115 { 0x41, 0x00 }, /* 41 */
116 { 0x42, 0x00 }, /* 42 */
117 { 0x43, 0x00 }, /* 43 */
118 { 0x44, 0x00 }, /* 44 */
119 { 0x45, 0x00 }, /* 45 */
120 { 0x46, 0x00 }, /* 46 */
121 { 0x47, 0x00 }, /* 47 */
122 { 0x48, 0x00 }, /* 48 */
123 { 0x49, 0x00 }, /* 49 */
124 { 0x4a, 0x00 }, /* 4A */
125 { 0x4b, 0x00 }, /* 4B */
126 { 0x4c, 0x00 }, /* 4C */
127 { 0x4d, 0x00 }, /* 4D */
128 { 0x4e, 0x00 }, /* 4E */
129 { 0x4f, 0x00 }, /* 4F */
130 { 0x50, 0x00 }, /* 50 */
131 { 0x51, 0x00 }, /* 51 */
132 { 0x52, 0x00 }, /* 52 */
133 { 0x53, 0x00 }, /* 53 */
134 { 0x54, 0x00 }, /* 54 */
135 { 0x55, 0x00 }, /* 55 */
136 { 0x56, 0x00 }, /* 56 */
137 { 0x57, 0x00 }, /* 57 */
138 { 0x58, 0x00 }, /* 58 */
139 { 0x59, 0x00 }, /* 59 */
140 { 0x5a, 0x00 }, /* 5A */
141 { 0x5b, 0x00 }, /* 5B */
142 { 0x5c, 0x00 }, /* 5C */
143 { 0x5d, 0x00 }, /* 5D */
144 { 0x5e, 0x00 }, /* 5E */
145 { 0x5f, 0x00 }, /* 5F */
146 { 0x60, 0x00 }, /* 60 */
147 { 0x61, 0x00 }, /* 61 */
148 { 0x62, 0x00 }, /* 62 */
149 { 0x63, 0x00 }, /* 63 */
150 { 0x64, 0x00 }, /* 64 */
151 { 0x65, 0x00 }, /* 65 */
152 { 0x66, 0x00 }, /* 66 */
153 { 0x67, 0x00 }, /* 67 */
154 { 0x68, 0x00 }, /* 68 */
155 { 0x69, 0x00 }, /* 69 */
156 { 0x6a, 0x00 }, /* 6A */
157 { 0x6b, 0x00 }, /* 6B */
158 { 0x6c, 0x00 }, /* 6C */
159 { 0x6d, 0x00 }, /* 6D */
160 { 0x6e, 0x00 }, /* 6E */
161 { 0x6f, 0x00 }, /* 6F */
162 { 0x70, 0x00 }, /* 70 */
163 { 0x71, 0x00 }, /* 71 */
164 { 0x72, 0x00 }, /* 72 */
165 { 0x73, 0x00 }, /* 73 */
166 { 0x74, 0x00 }, /* 74 */
167 { 0x75, 0x00 }, /* 75 */
168 { 0x76, 0x00 }, /* 76 */
169 { 0x77, 0x00 }, /* 77 */
170 { 0x78, 0x00 }, /* 78 */
171 { 0x79, 0x00 }, /* 79 */
172 { 0x7a, 0x00 }, /* 7A */
173 { 0x7b, 0x00 }, /* 7B */
174 { 0x7c, 0x00 }, /* 7C */
175 { 0x7d, 0x00 }, /* 7D */
176 { 0x7e, 0x00 }, /* 7E */
177 { 0x7f, 0x00 }, /* 7F */
178 { 0x80, 0x00 }, /* 80 */
179 { 0x81, 0x00 }, /* 81 */
180 { 0x82, 0x00 }, /* 82 */
181 { 0x83, 0x00 }, /* 83 */
182 { 0x84, 0x00 }, /* 84 */
183 { 0x85, 0x00 }, /* 85 */
184 { 0x86, 0x00 }, /* 86 */
185 { 0x87, 0x00 }, /* 87 */
186 { 0x88, 0x00 }, /* 88 */
187 { 0x89, 0x00 }, /* 89 */
188 { 0x8a, 0x00 }, /* 8A */
189 { 0x8b, 0x00 }, /* 8B */
190 { 0x8c, 0x00 }, /* 8C */
191 { 0x8d, 0x00 }, /* 8D */
192 { 0x8e, 0x00 }, /* 8E */
193 { 0x8f, 0x00 }, /* 8F */
194 { 0x90, 0x00 }, /* 90 */
195 { 0x91, 0x00 }, /* 91 */
196 { 0x92, 0x30 }, /* 92 */
197 { 0x93, 0xF0 }, /* 93 */
198 { 0x94, 0x00 }, /* 94 */
199 { 0x95, 0x00 }, /* 95 */
200 { 0x96, 0x3F }, /* 96 */
201 { 0x97, 0x00 }, /* 97 */
202 { 0xff, 0x00 }, /* FF */
82a5a936
PH		 203};
204
205static struct {
206 int readable;
207 int writable;
208} max98095_access[M98095_REG_CNT] = {
209 { 0x00, 0x00 }, /* 00 */
210 { 0xFF, 0x00 }, /* 01 */
211 { 0xFF, 0x00 }, /* 02 */
212 { 0xFF, 0x00 }, /* 03 */
213 { 0xFF, 0x00 }, /* 04 */
214 { 0xFF, 0x00 }, /* 05 */
215 { 0xFF, 0x00 }, /* 06 */
216 { 0xFF, 0x00 }, /* 07 */
217 { 0xFF, 0x00 }, /* 08 */
218 { 0xFF, 0x00 }, /* 09 */
219 { 0xFF, 0x00 }, /* 0A */
220 { 0xFF, 0x00 }, /* 0B */
221 { 0xFF, 0x00 }, /* 0C */
222 { 0xFF, 0x00 }, /* 0D */
223 { 0xFF, 0x00 }, /* 0E */
224 { 0xFF, 0x9F }, /* 0F */
225 { 0xFF, 0xFF }, /* 10 */
226 { 0xFF, 0xFF }, /* 11 */
227 { 0xFF, 0xFF }, /* 12 */
228 { 0xFF, 0xFF }, /* 13 */
229 { 0xFF, 0xFF }, /* 14 */
230 { 0xFF, 0xFF }, /* 15 */
231 { 0xFF, 0xFF }, /* 16 */
232 { 0xFF, 0xFF }, /* 17 */
233 { 0xFF, 0xFF }, /* 18 */
234 { 0xFF, 0xFF }, /* 19 */
235 { 0xFF, 0xFF }, /* 1A */
236 { 0xFF, 0xFF }, /* 1B */
237 { 0xFF, 0xFF }, /* 1C */
238 { 0xFF, 0xFF }, /* 1D */
239 { 0xFF, 0x77 }, /* 1E */
240 { 0xFF, 0x77 }, /* 1F */
241 { 0xFF, 0x77 }, /* 20 */
242 { 0xFF, 0x77 }, /* 21 */
243 { 0xFF, 0x77 }, /* 22 */
244 { 0xFF, 0x77 }, /* 23 */
245 { 0xFF, 0xFF }, /* 24 */
246 { 0xFF, 0x7F }, /* 25 */
247 { 0xFF, 0x31 }, /* 26 */
248 { 0xFF, 0xFF }, /* 27 */
249 { 0xFF, 0xFF }, /* 28 */
250 { 0xFF, 0xFF }, /* 29 */
251 { 0xFF, 0xF7 }, /* 2A */
252 { 0xFF, 0x2F }, /* 2B */
253 { 0xFF, 0xEF }, /* 2C */
254 { 0xFF, 0xFF }, /* 2D */
255 { 0xFF, 0xFF }, /* 2E */
256 { 0xFF, 0xFF }, /* 2F */
257 { 0xFF, 0xFF }, /* 30 */
258 { 0xFF, 0xFF }, /* 31 */
259 { 0xFF, 0xFF }, /* 32 */
260 { 0xFF, 0xFF }, /* 33 */
261 { 0xFF, 0xF7 }, /* 34 */
262 { 0xFF, 0x2F }, /* 35 */
263 { 0xFF, 0xCF }, /* 36 */
264 { 0xFF, 0xFF }, /* 37 */
265 { 0xFF, 0xFF }, /* 38 */
266 { 0xFF, 0xFF }, /* 39 */
267 { 0xFF, 0xFF }, /* 3A */
268 { 0xFF, 0xFF }, /* 3B */
269 { 0xFF, 0xFF }, /* 3C */
270 { 0xFF, 0xFF }, /* 3D */
271 { 0xFF, 0xF7 }, /* 3E */
272 { 0xFF, 0x2F }, /* 3F */
273 { 0xFF, 0xCF }, /* 40 */
274 { 0xFF, 0xFF }, /* 41 */
275 { 0xFF, 0x77 }, /* 42 */
276 { 0xFF, 0xFF }, /* 43 */
277 { 0xFF, 0xFF }, /* 44 */
278 { 0xFF, 0xFF }, /* 45 */
279 { 0xFF, 0xFF }, /* 46 */
280 { 0xFF, 0xFF }, /* 47 */
281 { 0xFF, 0xFF }, /* 48 */
282 { 0xFF, 0x0F }, /* 49 */
283 { 0xFF, 0xFF }, /* 4A */
284 { 0xFF, 0xFF }, /* 4B */
285 { 0xFF, 0x3F }, /* 4C */
286 { 0xFF, 0x3F }, /* 4D */
287 { 0xFF, 0x3F }, /* 4E */
288 { 0xFF, 0xFF }, /* 4F */
289 { 0xFF, 0x7F }, /* 50 */
290 { 0xFF, 0x7F }, /* 51 */
291 { 0xFF, 0x0F }, /* 52 */
292 { 0xFF, 0x3F }, /* 53 */
293 { 0xFF, 0x3F }, /* 54 */
294 { 0xFF, 0x3F }, /* 55 */
295 { 0xFF, 0xFF }, /* 56 */
296 { 0xFF, 0xFF }, /* 57 */
297 { 0xFF, 0xBF }, /* 58 */
298 { 0xFF, 0x1F }, /* 59 */
299 { 0xFF, 0xBF }, /* 5A */
300 { 0xFF, 0x1F }, /* 5B */
301 { 0xFF, 0xBF }, /* 5C */
302 { 0xFF, 0x3F }, /* 5D */
303 { 0xFF, 0x3F }, /* 5E */
304 { 0xFF, 0x7F }, /* 5F */
305 { 0xFF, 0x7F }, /* 60 */
306 { 0xFF, 0x47 }, /* 61 */
307 { 0xFF, 0x9F }, /* 62 */
308 { 0xFF, 0x9F }, /* 63 */
309 { 0xFF, 0x9F }, /* 64 */
310 { 0xFF, 0x9F }, /* 65 */
311 { 0xFF, 0x9F }, /* 66 */
312 { 0xFF, 0xBF }, /* 67 */
313 { 0xFF, 0xBF }, /* 68 */
314 { 0xFF, 0xFF }, /* 69 */
315 { 0xFF, 0xFF }, /* 6A */
316 { 0xFF, 0x7F }, /* 6B */
317 { 0xFF, 0xF7 }, /* 6C */
318 { 0xFF, 0xFF }, /* 6D */
319 { 0xFF, 0xFF }, /* 6E */
320 { 0xFF, 0x1F }, /* 6F */
321 { 0xFF, 0xF7 }, /* 70 */
322 { 0xFF, 0xFF }, /* 71 */
323 { 0xFF, 0xFF }, /* 72 */
324 { 0xFF, 0x1F }, /* 73 */
325 { 0xFF, 0xF7 }, /* 74 */
326 { 0xFF, 0xFF }, /* 75 */
327 { 0xFF, 0xFF }, /* 76 */
328 { 0xFF, 0x1F }, /* 77 */
329 { 0xFF, 0xF7 }, /* 78 */
330 { 0xFF, 0xFF }, /* 79 */
331 { 0xFF, 0xFF }, /* 7A */
332 { 0xFF, 0x1F }, /* 7B */
333 { 0xFF, 0xF7 }, /* 7C */
334 { 0xFF, 0xFF }, /* 7D */
335 { 0xFF, 0xFF }, /* 7E */
336 { 0xFF, 0x1F }, /* 7F */
337 { 0xFF, 0xF7 }, /* 80 */
338 { 0xFF, 0xFF }, /* 81 */
339 { 0xFF, 0xFF }, /* 82 */
340 { 0xFF, 0x1F }, /* 83 */
341 { 0xFF, 0x7F }, /* 84 */
342 { 0xFF, 0x0F }, /* 85 */
343 { 0xFF, 0xD8 }, /* 86 */
344 { 0xFF, 0xFF }, /* 87 */
345 { 0xFF, 0xEF }, /* 88 */
346 { 0xFF, 0xFE }, /* 89 */
347 { 0xFF, 0xFE }, /* 8A */
348 { 0xFF, 0xFF }, /* 8B */
349 { 0xFF, 0xFF }, /* 8C */
350 { 0xFF, 0x3F }, /* 8D */
351 { 0xFF, 0xFF }, /* 8E */
352 { 0xFF, 0x3F }, /* 8F */
353 { 0xFF, 0x8F }, /* 90 */
354 { 0xFF, 0xFF }, /* 91 */
355 { 0xFF, 0x3F }, /* 92 */
356 { 0xFF, 0xFF }, /* 93 */
357 { 0xFF, 0xFF }, /* 94 */
358 { 0xFF, 0x0F }, /* 95 */
359 { 0xFF, 0x3F }, /* 96 */
360 { 0xFF, 0x8C }, /* 97 */
361 { 0x00, 0x00 }, /* 98 */
362 { 0x00, 0x00 }, /* 99 */
363 { 0x00, 0x00 }, /* 9A */
364 { 0x00, 0x00 }, /* 9B */
365 { 0x00, 0x00 }, /* 9C */
366 { 0x00, 0x00 }, /* 9D */
367 { 0x00, 0x00 }, /* 9E */
368 { 0x00, 0x00 }, /* 9F */
369 { 0x00, 0x00 }, /* A0 */
370 { 0x00, 0x00 }, /* A1 */
371 { 0x00, 0x00 }, /* A2 */
372 { 0x00, 0x00 }, /* A3 */
373 { 0x00, 0x00 }, /* A4 */
374 { 0x00, 0x00 }, /* A5 */
375 { 0x00, 0x00 }, /* A6 */
376 { 0x00, 0x00 }, /* A7 */
377 { 0x00, 0x00 }, /* A8 */
378 { 0x00, 0x00 }, /* A9 */
379 { 0x00, 0x00 }, /* AA */
380 { 0x00, 0x00 }, /* AB */
381 { 0x00, 0x00 }, /* AC */
382 { 0x00, 0x00 }, /* AD */
383 { 0x00, 0x00 }, /* AE */
384 { 0x00, 0x00 }, /* AF */
385 { 0x00, 0x00 }, /* B0 */
386 { 0x00, 0x00 }, /* B1 */
387 { 0x00, 0x00 }, /* B2 */
388 { 0x00, 0x00 }, /* B3 */
389 { 0x00, 0x00 }, /* B4 */
390 { 0x00, 0x00 }, /* B5 */
391 { 0x00, 0x00 }, /* B6 */
392 { 0x00, 0x00 }, /* B7 */
393 { 0x00, 0x00 }, /* B8 */
394 { 0x00, 0x00 }, /* B9 */
395 { 0x00, 0x00 }, /* BA */
396 { 0x00, 0x00 }, /* BB */
397 { 0x00, 0x00 }, /* BC */
398 { 0x00, 0x00 }, /* BD */
399 { 0x00, 0x00 }, /* BE */
400 { 0x00, 0x00 }, /* BF */
401 { 0x00, 0x00 }, /* C0 */
402 { 0x00, 0x00 }, /* C1 */
403 { 0x00, 0x00 }, /* C2 */
404 { 0x00, 0x00 }, /* C3 */
405 { 0x00, 0x00 }, /* C4 */
406 { 0x00, 0x00 }, /* C5 */
407 { 0x00, 0x00 }, /* C6 */
408 { 0x00, 0x00 }, /* C7 */
409 { 0x00, 0x00 }, /* C8 */
410 { 0x00, 0x00 }, /* C9 */
411 { 0x00, 0x00 }, /* CA */
412 { 0x00, 0x00 }, /* CB */
413 { 0x00, 0x00 }, /* CC */
414 { 0x00, 0x00 }, /* CD */
415 { 0x00, 0x00 }, /* CE */
416 { 0x00, 0x00 }, /* CF */
417 { 0x00, 0x00 }, /* D0 */
418 { 0x00, 0x00 }, /* D1 */
419 { 0x00, 0x00 }, /* D2 */
420 { 0x00, 0x00 }, /* D3 */
421 { 0x00, 0x00 }, /* D4 */
422 { 0x00, 0x00 }, /* D5 */
423 { 0x00, 0x00 }, /* D6 */
424 { 0x00, 0x00 }, /* D7 */
425 { 0x00, 0x00 }, /* D8 */
426 { 0x00, 0x00 }, /* D9 */
427 { 0x00, 0x00 }, /* DA */
428 { 0x00, 0x00 }, /* DB */
429 { 0x00, 0x00 }, /* DC */
430 { 0x00, 0x00 }, /* DD */
431 { 0x00, 0x00 }, /* DE */
432 { 0x00, 0x00 }, /* DF */
433 { 0x00, 0x00 }, /* E0 */
434 { 0x00, 0x00 }, /* E1 */
435 { 0x00, 0x00 }, /* E2 */
436 { 0x00, 0x00 }, /* E3 */
437 { 0x00, 0x00 }, /* E4 */
438 { 0x00, 0x00 }, /* E5 */
439 { 0x00, 0x00 }, /* E6 */
440 { 0x00, 0x00 }, /* E7 */
441 { 0x00, 0x00 }, /* E8 */
442 { 0x00, 0x00 }, /* E9 */
443 { 0x00, 0x00 }, /* EA */
444 { 0x00, 0x00 }, /* EB */
445 { 0x00, 0x00 }, /* EC */
446 { 0x00, 0x00 }, /* ED */
447 { 0x00, 0x00 }, /* EE */
448 { 0x00, 0x00 }, /* EF */
449 { 0x00, 0x00 }, /* F0 */
450 { 0x00, 0x00 }, /* F1 */
451 { 0x00, 0x00 }, /* F2 */
452 { 0x00, 0x00 }, /* F3 */
453 { 0x00, 0x00 }, /* F4 */
454 { 0x00, 0x00 }, /* F5 */
455 { 0x00, 0x00 }, /* F6 */
456 { 0x00, 0x00 }, /* F7 */
457 { 0x00, 0x00 }, /* F8 */
458 { 0x00, 0x00 }, /* F9 */
459 { 0x00, 0x00 }, /* FA */
460 { 0x00, 0x00 }, /* FB */
461 { 0x00, 0x00 }, /* FC */
462 { 0x00, 0x00 }, /* FD */
463 { 0x00, 0x00 }, /* FE */
464 { 0xFF, 0x00 }, /* FF */
465};
466
14acbbbb 467static bool max98095_readable(struct device *dev, unsigned int reg)
82a5a936
PH		 468{
469 if (reg >= M98095_REG_CNT)
470 return 0;
471 return max98095_access[reg].readable != 0;
472}
473
14acbbbb 474static bool max98095_volatile(struct device *dev, unsigned int reg)
82a5a936
PH		 475{
476 if (reg > M98095_REG_MAX_CACHED)
477 return 1;
478
479 switch (reg) {
480 case M98095_000_HOST_DATA:
481 case M98095_001_HOST_INT_STS:
482 case M98095_002_HOST_RSP_STS:
483 case M98095_003_HOST_CMD_STS:
484 case M98095_004_CODEC_STS:
485 case M98095_005_DAI1_ALC_STS:
486 case M98095_006_DAI2_ALC_STS:
487 case M98095_007_JACK_AUTO_STS:
488 case M98095_008_JACK_MANUAL_STS:
489 case M98095_009_JACK_VBAT_STS:
490 case M98095_00A_ACC_ADC_STS:
491 case M98095_00B_MIC_NG_AGC_STS:
492 case M98095_00C_SPK_L_VOLT_STS:
493 case M98095_00D_SPK_R_VOLT_STS:
494 case M98095_00E_TEMP_SENSOR_STS:
495 return 1;
496 }
497
498 return 0;
499}
500
14acbbbb
MB		 501static const struct regmap_config max98095_regmap = {
502 .reg_bits = 8,
503 .val_bits = 8,
dad31ec1 504
14acbbbb
MB		 505 .reg_defaults = max98095_reg_def,
506 .num_reg_defaults = ARRAY_SIZE(max98095_reg_def),
507 .max_register = M98095_0FF_REV_ID,
508 .cache_type = REGCACHE_RBTREE,
0d8d2938 509
14acbbbb
MB		 510 .readable_reg = max98095_readable,
511 .volatile_reg = max98095_volatile,
512};
dad31ec1
PH		 513
514/*
515 * Load equalizer DSP coefficient configurations registers
516 */
517static void m98095_eq_band(struct snd_soc_codec *codec, unsigned int dai,
518 unsigned int band, u16 *coefs)
519{
520 unsigned int eq_reg;
521 unsigned int i;
522
a922cd71
TI		 523 if (WARN_ON(band > 4) ||
524 WARN_ON(dai > 1))
525 return;
dad31ec1
PH		 526
527 /* Load the base register address */
528 eq_reg = dai ? M98095_142_DAI2_EQ_BASE : M98095_110_DAI1_EQ_BASE;
529
530 /* Add the band address offset, note adjustment for word address */
531 eq_reg += band * (M98095_COEFS_PER_BAND << 1);
532
533 /* Step through the registers and coefs */
534 for (i = 0; i < M98095_COEFS_PER_BAND; i++) {
d36126ac
MB		 535 snd_soc_write(codec, eq_reg++, M98095_BYTE1(coefs[i]));
536 snd_soc_write(codec, eq_reg++, M98095_BYTE0(coefs[i]));
dad31ec1
PH		 537 }
538}
539
540/*
541 * Load biquad filter coefficient configurations registers
542 */
543static void m98095_biquad_band(struct snd_soc_codec *codec, unsigned int dai,
544 unsigned int band, u16 *coefs)
545{
546 unsigned int bq_reg;
547 unsigned int i;
548
a922cd71
TI		 549 if (WARN_ON(band > 1) ||
550 WARN_ON(dai > 1))
551 return;
dad31ec1
PH		 552
553 /* Load the base register address */
554 bq_reg = dai ? M98095_17E_DAI2_BQ_BASE : M98095_174_DAI1_BQ_BASE;
555
556 /* Add the band address offset, note adjustment for word address */
557 bq_reg += band * (M98095_COEFS_PER_BAND << 1);
558
559 /* Step through the registers and coefs */
560 for (i = 0; i < M98095_COEFS_PER_BAND; i++) {
d36126ac
MB		 561 snd_soc_write(codec, bq_reg++, M98095_BYTE1(coefs[i]));
562 snd_soc_write(codec, bq_reg++, M98095_BYTE0(coefs[i]));
dad31ec1
PH		 563 }
564}
565
82a5a936 566static const char * const max98095_fltr_mode[] = { "Voice", "Music" };
af1f0a50
TI		 567static SOC_ENUM_SINGLE_DECL(max98095_dai1_filter_mode_enum,
568 M98095_02E_DAI1_FILTERS, 7,
569 max98095_fltr_mode);
570static SOC_ENUM_SINGLE_DECL(max98095_dai2_filter_mode_enum,
571 M98095_038_DAI2_FILTERS, 7,
572 max98095_fltr_mode);
82a5a936
PH		 573
574static const char * const max98095_extmic_text[] = { "None", "MIC1", "MIC2" };
575
af1f0a50
TI		 576static SOC_ENUM_SINGLE_DECL(max98095_extmic_enum,
577 M98095_087_CFG_MIC, 0,
578 max98095_extmic_text);
82a5a936
PH		 579
580static const struct snd_kcontrol_new max98095_extmic_mux =
581 SOC_DAPM_ENUM("External MIC Mux", max98095_extmic_enum);
582
583static const char * const max98095_linein_text[] = { "INA", "INB" };
584
af1f0a50
TI		 585static SOC_ENUM_SINGLE_DECL(max98095_linein_enum,
586 M98095_086_CFG_LINE, 6,
587 max98095_linein_text);
82a5a936
PH		 588
589static const struct snd_kcontrol_new max98095_linein_mux =
590 SOC_DAPM_ENUM("Linein Input Mux", max98095_linein_enum);
591
592static const char * const max98095_line_mode_text[] = {
593 "Stereo", "Differential"};
594
af1f0a50
TI		 595static SOC_ENUM_SINGLE_DECL(max98095_linein_mode_enum,
596 M98095_086_CFG_LINE, 7,
597 max98095_line_mode_text);
82a5a936 598
af1f0a50
TI		 599static SOC_ENUM_SINGLE_DECL(max98095_lineout_mode_enum,
600 M98095_086_CFG_LINE, 4,
601 max98095_line_mode_text);
82a5a936
PH		 602
603static const char * const max98095_dai_fltr[] = {
604 "Off", "Elliptical-HPF-16k", "Butterworth-HPF-16k",
605 "Elliptical-HPF-8k", "Butterworth-HPF-8k", "Butterworth-HPF-Fs/240"};
af1f0a50
TI		 606static SOC_ENUM_SINGLE_DECL(max98095_dai1_dac_filter_enum,
607 M98095_02E_DAI1_FILTERS, 0,
608 max98095_dai_fltr);
609static SOC_ENUM_SINGLE_DECL(max98095_dai2_dac_filter_enum,
610 M98095_038_DAI2_FILTERS, 0,
611 max98095_dai_fltr);
612static SOC_ENUM_SINGLE_DECL(max98095_dai3_dac_filter_enum,
613 M98095_042_DAI3_FILTERS, 0,
614 max98095_dai_fltr);
82a5a936
PH		 615
616static int max98095_mic1pre_set(struct snd_kcontrol *kcontrol,
617 struct snd_ctl_elem_value *ucontrol)
618{
ea53bf77 619 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
82a5a936
PH		 620 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
621 unsigned int sel = ucontrol->value.integer.value[0];
622
623 max98095->mic1pre = sel;
624 snd_soc_update_bits(codec, M98095_05F_LVL_MIC1, M98095_MICPRE_MASK,
625 (1+sel)<<M98095_MICPRE_SHIFT);
626
627 return 0;
628}
629
630static int max98095_mic1pre_get(struct snd_kcontrol *kcontrol,
631 struct snd_ctl_elem_value *ucontrol)
632{
ea53bf77 633 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
82a5a936
PH		 634 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
635
636 ucontrol->value.integer.value[0] = max98095->mic1pre;
637 return 0;
638}
639
640static int max98095_mic2pre_set(struct snd_kcontrol *kcontrol,
641 struct snd_ctl_elem_value *ucontrol)
642{
ea53bf77 643 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
82a5a936
PH		 644 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
645 unsigned int sel = ucontrol->value.integer.value[0];
646
647 max98095->mic2pre = sel;
648 snd_soc_update_bits(codec, M98095_060_LVL_MIC2, M98095_MICPRE_MASK,
649 (1+sel)<<M98095_MICPRE_SHIFT);
650
651 return 0;
652}
653
654static int max98095_mic2pre_get(struct snd_kcontrol *kcontrol,
655 struct snd_ctl_elem_value *ucontrol)
656{
ea53bf77 657 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
82a5a936
PH		 658 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
659
660 ucontrol->value.integer.value[0] = max98095->mic2pre;
661 return 0;
662}
663
664static const unsigned int max98095_micboost_tlv[] = {
665 TLV_DB_RANGE_HEAD(2),
666 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
667 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0),
668};
669
670static const DECLARE_TLV_DB_SCALE(max98095_mic_tlv, 0, 100, 0);
671static const DECLARE_TLV_DB_SCALE(max98095_adc_tlv, -1200, 100, 0);
672static const DECLARE_TLV_DB_SCALE(max98095_adcboost_tlv, 0, 600, 0);
673
674static const unsigned int max98095_hp_tlv[] = {
675 TLV_DB_RANGE_HEAD(5),
676 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
677 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
678 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
679 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
680 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0),
681};
682
683static const unsigned int max98095_spk_tlv[] = {
684 TLV_DB_RANGE_HEAD(4),
685 0, 10, TLV_DB_SCALE_ITEM(-5900, 400, 0),
686 11, 18, TLV_DB_SCALE_ITEM(-1700, 200, 0),
687 19, 27, TLV_DB_SCALE_ITEM(-200, 100, 0),
688 28, 39, TLV_DB_SCALE_ITEM(650, 50, 0),
689};
690
691static const unsigned int max98095_rcv_lout_tlv[] = {
692 TLV_DB_RANGE_HEAD(5),
693 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
694 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
695 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
696 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
697 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0),
698};
699
700static const unsigned int max98095_lin_tlv[] = {
701 TLV_DB_RANGE_HEAD(3),
702 0, 2, TLV_DB_SCALE_ITEM(-600, 300, 0),
703 3, 3, TLV_DB_SCALE_ITEM(300, 1100, 0),
704 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0),
705};
706
707static const struct snd_kcontrol_new max98095_snd_controls[] = {
708
709 SOC_DOUBLE_R_TLV("Headphone Volume", M98095_064_LVL_HP_L,
710 M98095_065_LVL_HP_R, 0, 31, 0, max98095_hp_tlv),
711
712 SOC_DOUBLE_R_TLV("Speaker Volume", M98095_067_LVL_SPK_L,
713 M98095_068_LVL_SPK_R, 0, 39, 0, max98095_spk_tlv),
714
715 SOC_SINGLE_TLV("Receiver Volume", M98095_066_LVL_RCV,
716 0, 31, 0, max98095_rcv_lout_tlv),
717
718 SOC_DOUBLE_R_TLV("Lineout Volume", M98095_062_LVL_LINEOUT1,
719 M98095_063_LVL_LINEOUT2, 0, 31, 0, max98095_rcv_lout_tlv),
720
721 SOC_DOUBLE_R("Headphone Switch", M98095_064_LVL_HP_L,
722 M98095_065_LVL_HP_R, 7, 1, 1),
723
724 SOC_DOUBLE_R("Speaker Switch", M98095_067_LVL_SPK_L,
725 M98095_068_LVL_SPK_R, 7, 1, 1),
726
727 SOC_SINGLE("Receiver Switch", M98095_066_LVL_RCV, 7, 1, 1),
728
729 SOC_DOUBLE_R("Lineout Switch", M98095_062_LVL_LINEOUT1,
730 M98095_063_LVL_LINEOUT2, 7, 1, 1),
731
732 SOC_SINGLE_TLV("MIC1 Volume", M98095_05F_LVL_MIC1, 0, 20, 1,
733 max98095_mic_tlv),
734
735 SOC_SINGLE_TLV("MIC2 Volume", M98095_060_LVL_MIC2, 0, 20, 1,
736 max98095_mic_tlv),
737
738 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
739 M98095_05F_LVL_MIC1, 5, 2, 0,
740 max98095_mic1pre_get, max98095_mic1pre_set,
741 max98095_micboost_tlv),
742 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
743 M98095_060_LVL_MIC2, 5, 2, 0,
744 max98095_mic2pre_get, max98095_mic2pre_set,
745 max98095_micboost_tlv),
746
747 SOC_SINGLE_TLV("Linein Volume", M98095_061_LVL_LINEIN, 0, 5, 1,
748 max98095_lin_tlv),
749
750 SOC_SINGLE_TLV("ADCL Volume", M98095_05D_LVL_ADC_L, 0, 15, 1,
751 max98095_adc_tlv),
752 SOC_SINGLE_TLV("ADCR Volume", M98095_05E_LVL_ADC_R, 0, 15, 1,
753 max98095_adc_tlv),
754
755 SOC_SINGLE_TLV("ADCL Boost Volume", M98095_05D_LVL_ADC_L, 4, 3, 0,
756 max98095_adcboost_tlv),
757 SOC_SINGLE_TLV("ADCR Boost Volume", M98095_05E_LVL_ADC_R, 4, 3, 0,
758 max98095_adcboost_tlv),
759
dad31ec1
PH		 760 SOC_SINGLE("EQ1 Switch", M98095_088_CFG_LEVEL, 0, 1, 0),
761 SOC_SINGLE("EQ2 Switch", M98095_088_CFG_LEVEL, 1, 1, 0),
762
763 SOC_SINGLE("Biquad1 Switch", M98095_088_CFG_LEVEL, 2, 1, 0),
764 SOC_SINGLE("Biquad2 Switch", M98095_088_CFG_LEVEL, 3, 1, 0),
765
82a5a936
PH		 766 SOC_ENUM("DAI1 Filter Mode", max98095_dai1_filter_mode_enum),
767 SOC_ENUM("DAI2 Filter Mode", max98095_dai2_filter_mode_enum),
768 SOC_ENUM("DAI1 DAC Filter", max98095_dai1_dac_filter_enum),
769 SOC_ENUM("DAI2 DAC Filter", max98095_dai2_dac_filter_enum),
770 SOC_ENUM("DAI3 DAC Filter", max98095_dai3_dac_filter_enum),
771
772 SOC_ENUM("Linein Mode", max98095_linein_mode_enum),
773 SOC_ENUM("Lineout Mode", max98095_lineout_mode_enum),
774};
775
776/* Left speaker mixer switch */
777static const struct snd_kcontrol_new max98095_left_speaker_mixer_controls[] = {
778 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_050_MIX_SPK_LEFT, 0, 1, 0),
779 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_050_MIX_SPK_LEFT, 6, 1, 0),
780 SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0),
781 SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0),
782 SOC_DAPM_SINGLE("MIC1 Switch", M98095_050_MIX_SPK_LEFT, 4, 1, 0),
783 SOC_DAPM_SINGLE("MIC2 Switch", M98095_050_MIX_SPK_LEFT, 5, 1, 0),
784 SOC_DAPM_SINGLE("IN1 Switch", M98095_050_MIX_SPK_LEFT, 1, 1, 0),
785 SOC_DAPM_SINGLE("IN2 Switch", M98095_050_MIX_SPK_LEFT, 2, 1, 0),
786};
787
788/* Right speaker mixer switch */
789static const struct snd_kcontrol_new max98095_right_speaker_mixer_controls[] = {
790 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 6, 1, 0),
791 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 0, 1, 0),
792 SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0),
793 SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0),
794 SOC_DAPM_SINGLE("MIC1 Switch", M98095_051_MIX_SPK_RIGHT, 5, 1, 0),
795 SOC_DAPM_SINGLE("MIC2 Switch", M98095_051_MIX_SPK_RIGHT, 4, 1, 0),
796 SOC_DAPM_SINGLE("IN1 Switch", M98095_051_MIX_SPK_RIGHT, 1, 1, 0),
797 SOC_DAPM_SINGLE("IN2 Switch", M98095_051_MIX_SPK_RIGHT, 2, 1, 0),
798};
799
800/* Left headphone mixer switch */
801static const struct snd_kcontrol_new max98095_left_hp_mixer_controls[] = {
802 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04C_MIX_HP_LEFT, 0, 1, 0),
803 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04C_MIX_HP_LEFT, 5, 1, 0),
804 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04C_MIX_HP_LEFT, 3, 1, 0),
805 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04C_MIX_HP_LEFT, 4, 1, 0),
806 SOC_DAPM_SINGLE("IN1 Switch", M98095_04C_MIX_HP_LEFT, 1, 1, 0),
807 SOC_DAPM_SINGLE("IN2 Switch", M98095_04C_MIX_HP_LEFT, 2, 1, 0),
808};
809
810/* Right headphone mixer switch */
811static const struct snd_kcontrol_new max98095_right_hp_mixer_controls[] = {
812 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 5, 1, 0),
813 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 0, 1, 0),
814 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04D_MIX_HP_RIGHT, 3, 1, 0),
815 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04D_MIX_HP_RIGHT, 4, 1, 0),
816 SOC_DAPM_SINGLE("IN1 Switch", M98095_04D_MIX_HP_RIGHT, 1, 1, 0),
817 SOC_DAPM_SINGLE("IN2 Switch", M98095_04D_MIX_HP_RIGHT, 2, 1, 0),
818};
819
820/* Receiver earpiece mixer switch */
821static const struct snd_kcontrol_new max98095_mono_rcv_mixer_controls[] = {
822 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04F_MIX_RCV, 0, 1, 0),
823 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04F_MIX_RCV, 5, 1, 0),
824 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04F_MIX_RCV, 3, 1, 0),
825 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04F_MIX_RCV, 4, 1, 0),
826 SOC_DAPM_SINGLE("IN1 Switch", M98095_04F_MIX_RCV, 1, 1, 0),
827 SOC_DAPM_SINGLE("IN2 Switch", M98095_04F_MIX_RCV, 2, 1, 0),
828};
829
830/* Left lineout mixer switch */
831static const struct snd_kcontrol_new max98095_left_lineout_mixer_controls[] = {
832 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_053_MIX_LINEOUT1, 5, 1, 0),
833 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_053_MIX_LINEOUT1, 0, 1, 0),
834 SOC_DAPM_SINGLE("MIC1 Switch", M98095_053_MIX_LINEOUT1, 3, 1, 0),
835 SOC_DAPM_SINGLE("MIC2 Switch", M98095_053_MIX_LINEOUT1, 4, 1, 0),
836 SOC_DAPM_SINGLE("IN1 Switch", M98095_053_MIX_LINEOUT1, 1, 1, 0),
837 SOC_DAPM_SINGLE("IN2 Switch", M98095_053_MIX_LINEOUT1, 2, 1, 0),
838};
839
840/* Right lineout mixer switch */
841static const struct snd_kcontrol_new max98095_right_lineout_mixer_controls[] = {
842 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_054_MIX_LINEOUT2, 0, 1, 0),
843 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_054_MIX_LINEOUT2, 5, 1, 0),
844 SOC_DAPM_SINGLE("MIC1 Switch", M98095_054_MIX_LINEOUT2, 3, 1, 0),
845 SOC_DAPM_SINGLE("MIC2 Switch", M98095_054_MIX_LINEOUT2, 4, 1, 0),
846 SOC_DAPM_SINGLE("IN1 Switch", M98095_054_MIX_LINEOUT2, 1, 1, 0),
847 SOC_DAPM_SINGLE("IN2 Switch", M98095_054_MIX_LINEOUT2, 2, 1, 0),
848};
849
850/* Left ADC mixer switch */
851static const struct snd_kcontrol_new max98095_left_ADC_mixer_controls[] = {
852 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04A_MIX_ADC_LEFT, 7, 1, 0),
853 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04A_MIX_ADC_LEFT, 6, 1, 0),
854 SOC_DAPM_SINGLE("IN1 Switch", M98095_04A_MIX_ADC_LEFT, 3, 1, 0),
855 SOC_DAPM_SINGLE("IN2 Switch", M98095_04A_MIX_ADC_LEFT, 2, 1, 0),
856};
857
858/* Right ADC mixer switch */
859static const struct snd_kcontrol_new max98095_right_ADC_mixer_controls[] = {
860 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04B_MIX_ADC_RIGHT, 7, 1, 0),
861 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04B_MIX_ADC_RIGHT, 6, 1, 0),
862 SOC_DAPM_SINGLE("IN1 Switch", M98095_04B_MIX_ADC_RIGHT, 3, 1, 0),
863 SOC_DAPM_SINGLE("IN2 Switch", M98095_04B_MIX_ADC_RIGHT, 2, 1, 0),
864};
865
866static int max98095_mic_event(struct snd_soc_dapm_widget *w,
867 struct snd_kcontrol *kcontrol, int event)
868{
0db5dc94 869 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
82a5a936
PH		 870 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
871
872 switch (event) {
873 case SND_SOC_DAPM_POST_PMU:
874 if (w->reg == M98095_05F_LVL_MIC1) {
875 snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK,
876 (1+max98095->mic1pre)<<M98095_MICPRE_SHIFT);
877 } else {
878 snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK,
879 (1+max98095->mic2pre)<<M98095_MICPRE_SHIFT);
880 }
881 break;
882 case SND_SOC_DAPM_POST_PMD:
883 snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK, 0);
884 break;
885 default:
886 return -EINVAL;
887 }
888
889 return 0;
890}
891
892/*
893 * The line inputs are stereo inputs with the left and right
894 * channels sharing a common PGA power control signal.
895 */
896static int max98095_line_pga(struct snd_soc_dapm_widget *w,
897 int event, u8 channel)
898{
0db5dc94 899 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
82a5a936
PH		 900 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
901 u8 *state;
902
a922cd71
TI		 903 if (WARN_ON(!(channel == 1 || channel == 2)))
904 return -EINVAL;
82a5a936
PH		 905
906 state = &max98095->lin_state;
907
908 switch (event) {
909 case SND_SOC_DAPM_POST_PMU:
910 *state |= channel;
911 snd_soc_update_bits(codec, w->reg,
912 (1 << w->shift), (1 << w->shift));
913 break;
914 case SND_SOC_DAPM_POST_PMD:
915 *state &= ~channel;
916 if (*state == 0) {
917 snd_soc_update_bits(codec, w->reg,
918 (1 << w->shift), 0);
919 }
920 break;
921 default:
922 return -EINVAL;
923 }
924
925 return 0;
926}
927
928static int max98095_pga_in1_event(struct snd_soc_dapm_widget *w,
929 struct snd_kcontrol *k, int event)
930{
931 return max98095_line_pga(w, event, 1);
932}
933
934static int max98095_pga_in2_event(struct snd_soc_dapm_widget *w,
935 struct snd_kcontrol *k, int event)
936{
937 return max98095_line_pga(w, event, 2);
938}
939
940/*
941 * The stereo line out mixer outputs to two stereo line outs.
942 * The 2nd pair has a separate set of enables.
943 */
944static int max98095_lineout_event(struct snd_soc_dapm_widget *w,
945 struct snd_kcontrol *kcontrol, int event)
946{
0db5dc94 947 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
82a5a936
PH		 948
949 switch (event) {
950 case SND_SOC_DAPM_POST_PMU:
951 snd_soc_update_bits(codec, w->reg,
952 (1 << (w->shift+2)), (1 << (w->shift+2)));
953 break;
954 case SND_SOC_DAPM_POST_PMD:
955 snd_soc_update_bits(codec, w->reg,
956 (1 << (w->shift+2)), 0);
957 break;
958 default:
959 return -EINVAL;
960 }
961
962 return 0;
963}
964
965static const struct snd_soc_dapm_widget max98095_dapm_widgets[] = {
966
967 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98095_090_PWR_EN_IN, 0, 0),
968 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98095_090_PWR_EN_IN, 1, 0),
969
970 SND_SOC_DAPM_DAC("DACL1", "HiFi Playback",
971 M98095_091_PWR_EN_OUT, 0, 0),
972 SND_SOC_DAPM_DAC("DACR1", "HiFi Playback",
973 M98095_091_PWR_EN_OUT, 1, 0),
974 SND_SOC_DAPM_DAC("DACM2", "Aux Playback",
975 M98095_091_PWR_EN_OUT, 2, 0),
976 SND_SOC_DAPM_DAC("DACM3", "Voice Playback",
977 M98095_091_PWR_EN_OUT, 2, 0),
978
979 SND_SOC_DAPM_PGA("HP Left Out", M98095_091_PWR_EN_OUT,
980 6, 0, NULL, 0),
981 SND_SOC_DAPM_PGA("HP Right Out", M98095_091_PWR_EN_OUT,
982 7, 0, NULL, 0),
983
984 SND_SOC_DAPM_PGA("SPK Left Out", M98095_091_PWR_EN_OUT,
985 4, 0, NULL, 0),
986 SND_SOC_DAPM_PGA("SPK Right Out", M98095_091_PWR_EN_OUT,
987 5, 0, NULL, 0),
988
989 SND_SOC_DAPM_PGA("RCV Mono Out", M98095_091_PWR_EN_OUT,
990 3, 0, NULL, 0),
991
992 SND_SOC_DAPM_PGA_E("LINE Left Out", M98095_092_PWR_EN_OUT,
993 0, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD),
994 SND_SOC_DAPM_PGA_E("LINE Right Out", M98095_092_PWR_EN_OUT,
995 1, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD),
996
997 SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0,
998 &max98095_extmic_mux),
999
1000 SND_SOC_DAPM_MUX("Linein Mux", SND_SOC_NOPM, 0, 0,
1001 &max98095_linein_mux),
1002
1003 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
1004 &max98095_left_hp_mixer_controls[0],
1005 ARRAY_SIZE(max98095_left_hp_mixer_controls)),
1006
1007 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
1008 &max98095_right_hp_mixer_controls[0],
1009 ARRAY_SIZE(max98095_right_hp_mixer_controls)),
1010
1011 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
1012 &max98095_left_speaker_mixer_controls[0],
1013 ARRAY_SIZE(max98095_left_speaker_mixer_controls)),
1014
1015 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
1016 &max98095_right_speaker_mixer_controls[0],
1017 ARRAY_SIZE(max98095_right_speaker_mixer_controls)),
1018
1019 SND_SOC_DAPM_MIXER("Receiver Mixer", SND_SOC_NOPM, 0, 0,
1020 &max98095_mono_rcv_mixer_controls[0],
1021 ARRAY_SIZE(max98095_mono_rcv_mixer_controls)),
1022
1023 SND_SOC_DAPM_MIXER("Left Lineout Mixer", SND_SOC_NOPM, 0, 0,
1024 &max98095_left_lineout_mixer_controls[0],
1025 ARRAY_SIZE(max98095_left_lineout_mixer_controls)),
1026
1027 SND_SOC_DAPM_MIXER("Right Lineout Mixer", SND_SOC_NOPM, 0, 0,
1028 &max98095_right_lineout_mixer_controls[0],
1029 ARRAY_SIZE(max98095_right_lineout_mixer_controls)),
1030
1031 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
1032 &max98095_left_ADC_mixer_controls[0],
1033 ARRAY_SIZE(max98095_left_ADC_mixer_controls)),
1034
1035 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
1036 &max98095_right_ADC_mixer_controls[0],
1037 ARRAY_SIZE(max98095_right_ADC_mixer_controls)),
1038
1039 SND_SOC_DAPM_PGA_E("MIC1 Input", M98095_05F_LVL_MIC1,
1040 5, 0, NULL, 0, max98095_mic_event,
1041 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1042
1043 SND_SOC_DAPM_PGA_E("MIC2 Input", M98095_060_LVL_MIC2,
1044 5, 0, NULL, 0, max98095_mic_event,
1045 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1046
1047 SND_SOC_DAPM_PGA_E("IN1 Input", M98095_090_PWR_EN_IN,
1048 7, 0, NULL, 0, max98095_pga_in1_event,
1049 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1050
1051 SND_SOC_DAPM_PGA_E("IN2 Input", M98095_090_PWR_EN_IN,
1052 7, 0, NULL, 0, max98095_pga_in2_event,
1053 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1054
1055 SND_SOC_DAPM_MICBIAS("MICBIAS1", M98095_090_PWR_EN_IN, 2, 0),
1056 SND_SOC_DAPM_MICBIAS("MICBIAS2", M98095_090_PWR_EN_IN, 3, 0),
1057
1058 SND_SOC_DAPM_OUTPUT("HPL"),
1059 SND_SOC_DAPM_OUTPUT("HPR"),
1060 SND_SOC_DAPM_OUTPUT("SPKL"),
1061 SND_SOC_DAPM_OUTPUT("SPKR"),
1062 SND_SOC_DAPM_OUTPUT("RCV"),
1063 SND_SOC_DAPM_OUTPUT("OUT1"),
1064 SND_SOC_DAPM_OUTPUT("OUT2"),
1065 SND_SOC_DAPM_OUTPUT("OUT3"),
1066 SND_SOC_DAPM_OUTPUT("OUT4"),
1067
1068 SND_SOC_DAPM_INPUT("MIC1"),
1069 SND_SOC_DAPM_INPUT("MIC2"),
1070 SND_SOC_DAPM_INPUT("INA1"),
1071 SND_SOC_DAPM_INPUT("INA2"),
1072 SND_SOC_DAPM_INPUT("INB1"),
1073 SND_SOC_DAPM_INPUT("INB2"),
1074};
1075
1076static const struct snd_soc_dapm_route max98095_audio_map[] = {
1077 /* Left headphone output mixer */
1078 {"Left Headphone Mixer", "Left DAC1 Switch", "DACL1"},
1079 {"Left Headphone Mixer", "Right DAC1 Switch", "DACR1"},
1080 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1081 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1082 {"Left Headphone Mixer", "IN1 Switch", "IN1 Input"},
1083 {"Left Headphone Mixer", "IN2 Switch", "IN2 Input"},
1084
1085 /* Right headphone output mixer */
1086 {"Right Headphone Mixer", "Left DAC1 Switch", "DACL1"},
1087 {"Right Headphone Mixer", "Right DAC1 Switch", "DACR1"},
1088 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1089 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1090 {"Right Headphone Mixer", "IN1 Switch", "IN1 Input"},
1091 {"Right Headphone Mixer", "IN2 Switch", "IN2 Input"},
1092
1093 /* Left speaker output mixer */
1094 {"Left Speaker Mixer", "Left DAC1 Switch", "DACL1"},
1095 {"Left Speaker Mixer", "Right DAC1 Switch", "DACR1"},
1096 {"Left Speaker Mixer", "Mono DAC2 Switch", "DACM2"},
1097 {"Left Speaker Mixer", "Mono DAC3 Switch", "DACM3"},
1098 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1099 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1100 {"Left Speaker Mixer", "IN1 Switch", "IN1 Input"},
1101 {"Left Speaker Mixer", "IN2 Switch", "IN2 Input"},
1102
1103 /* Right speaker output mixer */
1104 {"Right Speaker Mixer", "Left DAC1 Switch", "DACL1"},
1105 {"Right Speaker Mixer", "Right DAC1 Switch", "DACR1"},
1106 {"Right Speaker Mixer", "Mono DAC2 Switch", "DACM2"},
1107 {"Right Speaker Mixer", "Mono DAC3 Switch", "DACM3"},
1108 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1109 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1110 {"Right Speaker Mixer", "IN1 Switch", "IN1 Input"},
1111 {"Right Speaker Mixer", "IN2 Switch", "IN2 Input"},
1112
1113 /* Earpiece/Receiver output mixer */
1114 {"Receiver Mixer", "Left DAC1 Switch", "DACL1"},
1115 {"Receiver Mixer", "Right DAC1 Switch", "DACR1"},
1116 {"Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1117 {"Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1118 {"Receiver Mixer", "IN1 Switch", "IN1 Input"},
1119 {"Receiver Mixer", "IN2 Switch", "IN2 Input"},
1120
1121 /* Left Lineout output mixer */
1122 {"Left Lineout Mixer", "Left DAC1 Switch", "DACL1"},
1123 {"Left Lineout Mixer", "Right DAC1 Switch", "DACR1"},
1124 {"Left Lineout Mixer", "MIC1 Switch", "MIC1 Input"},
1125 {"Left Lineout Mixer", "MIC2 Switch", "MIC2 Input"},
1126 {"Left Lineout Mixer", "IN1 Switch", "IN1 Input"},
1127 {"Left Lineout Mixer", "IN2 Switch", "IN2 Input"},
1128
1129 /* Right lineout output mixer */
1130 {"Right Lineout Mixer", "Left DAC1 Switch", "DACL1"},
1131 {"Right Lineout Mixer", "Right DAC1 Switch", "DACR1"},
1132 {"Right Lineout Mixer", "MIC1 Switch", "MIC1 Input"},
1133 {"Right Lineout Mixer", "MIC2 Switch", "MIC2 Input"},
1134 {"Right Lineout Mixer", "IN1 Switch", "IN1 Input"},
1135 {"Right Lineout Mixer", "IN2 Switch", "IN2 Input"},
1136
1137 {"HP Left Out", NULL, "Left Headphone Mixer"},
1138 {"HP Right Out", NULL, "Right Headphone Mixer"},
1139 {"SPK Left Out", NULL, "Left Speaker Mixer"},
1140 {"SPK Right Out", NULL, "Right Speaker Mixer"},
1141 {"RCV Mono Out", NULL, "Receiver Mixer"},
1142 {"LINE Left Out", NULL, "Left Lineout Mixer"},
1143 {"LINE Right Out", NULL, "Right Lineout Mixer"},
1144
1145 {"HPL", NULL, "HP Left Out"},
1146 {"HPR", NULL, "HP Right Out"},
1147 {"SPKL", NULL, "SPK Left Out"},
1148 {"SPKR", NULL, "SPK Right Out"},
1149 {"RCV", NULL, "RCV Mono Out"},
1150 {"OUT1", NULL, "LINE Left Out"},
1151 {"OUT2", NULL, "LINE Right Out"},
1152 {"OUT3", NULL, "LINE Left Out"},
1153 {"OUT4", NULL, "LINE Right Out"},
1154
1155 /* Left ADC input mixer */
1156 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1157 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1158 {"Left ADC Mixer", "IN1 Switch", "IN1 Input"},
1159 {"Left ADC Mixer", "IN2 Switch", "IN2 Input"},
1160
1161 /* Right ADC input mixer */
1162 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1163 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1164 {"Right ADC Mixer", "IN1 Switch", "IN1 Input"},
1165 {"Right ADC Mixer", "IN2 Switch", "IN2 Input"},
1166
1167 /* Inputs */
1168 {"ADCL", NULL, "Left ADC Mixer"},
1169 {"ADCR", NULL, "Right ADC Mixer"},
1170
1171 {"IN1 Input", NULL, "INA1"},
1172 {"IN2 Input", NULL, "INA2"},
1173
1174 {"MIC1 Input", NULL, "MIC1"},
1175 {"MIC2 Input", NULL, "MIC2"},
1176};
1177
82a5a936
PH		 1178/* codec mclk clock divider coefficients */
1179static const struct {
1180 u32 rate;
1181 u8 sr;
1182} rate_table[] = {
1183 {8000, 0x01},
1184 {11025, 0x02},
1185 {16000, 0x03},
1186 {22050, 0x04},
1187 {24000, 0x05},
1188 {32000, 0x06},
1189 {44100, 0x07},
1190 {48000, 0x08},
1191 {88200, 0x09},
1192 {96000, 0x0A},
1193};
1194
1195static int rate_value(int rate, u8 *value)
1196{
1197 int i;
1198
1199 for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
1200 if (rate_table[i].rate >= rate) {
1201 *value = rate_table[i].sr;
1202 return 0;
1203 }
1204 }
1205 *value = rate_table[0].sr;
1206 return -EINVAL;
1207}
1208
1209static int max98095_dai1_hw_params(struct snd_pcm_substream *substream,
1210 struct snd_pcm_hw_params *params,
1211 struct snd_soc_dai *dai)
1212{
1213 struct snd_soc_codec *codec = dai->codec;
1214 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1215 struct max98095_cdata *cdata;
1216 unsigned long long ni;
1217 unsigned int rate;
1218 u8 regval;
1219
1220 cdata = &max98095->dai[0];
1221
1222 rate = params_rate(params);
1223
580ce08d
MB		 1224 switch (params_width(params)) {
1225 case 16:
82a5a936
PH		 1226 snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT,
1227 M98095_DAI_WS, 0);
1228 break;
580ce08d 1229 case 24:
82a5a936
PH		 1230 snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT,
1231 M98095_DAI_WS, M98095_DAI_WS);
1232 break;
1233 default:
1234 return -EINVAL;
1235 }
1236
1237 if (rate_value(rate, &regval))
1238 return -EINVAL;
1239
1240 snd_soc_update_bits(codec, M98095_027_DAI1_CLKMODE,
1241 M98095_CLKMODE_MASK, regval);
1242 cdata->rate = rate;
1243
1244 /* Configure NI when operating as master */
1245 if (snd_soc_read(codec, M98095_02A_DAI1_FORMAT) & M98095_DAI_MAS) {
1246 if (max98095->sysclk == 0) {
1247 dev_err(codec->dev, "Invalid system clock frequency\n");
1248 return -EINVAL;
1249 }
1250 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1251 * (unsigned long long int)rate;
1252 do_div(ni, (unsigned long long int)max98095->sysclk);
1253 snd_soc_write(codec, M98095_028_DAI1_CLKCFG_HI,
1254 (ni >> 8) & 0x7F);
1255 snd_soc_write(codec, M98095_029_DAI1_CLKCFG_LO,
1256 ni & 0xFF);
1257 }
1258
1259 /* Update sample rate mode */
1260 if (rate < 50000)
1261 snd_soc_update_bits(codec, M98095_02E_DAI1_FILTERS,
1262 M98095_DAI_DHF, 0);
1263 else
1264 snd_soc_update_bits(codec, M98095_02E_DAI1_FILTERS,
1265 M98095_DAI_DHF, M98095_DAI_DHF);
1266
1267 return 0;
1268}
1269
1270static int max98095_dai2_hw_params(struct snd_pcm_substream *substream,
1271 struct snd_pcm_hw_params *params,
1272 struct snd_soc_dai *dai)
1273{
1274 struct snd_soc_codec *codec = dai->codec;
1275 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1276 struct max98095_cdata *cdata;
1277 unsigned long long ni;
1278 unsigned int rate;
1279 u8 regval;
1280
1281 cdata = &max98095->dai[1];
1282
1283 rate = params_rate(params);
1284
1ae1f3a2
MB		 1285 switch (params_width(params)) {
1286 case 16:
82a5a936
PH		 1287 snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT,
1288 M98095_DAI_WS, 0);
1289 break;
1ae1f3a2 1290 case 24:
82a5a936
PH		 1291 snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT,
1292 M98095_DAI_WS, M98095_DAI_WS);
1293 break;
1294 default:
1295 return -EINVAL;
1296 }
1297
1298 if (rate_value(rate, &regval))
1299 return -EINVAL;
1300
1301 snd_soc_update_bits(codec, M98095_031_DAI2_CLKMODE,
1302 M98095_CLKMODE_MASK, regval);
1303 cdata->rate = rate;
1304
1305 /* Configure NI when operating as master */
1306 if (snd_soc_read(codec, M98095_034_DAI2_FORMAT) & M98095_DAI_MAS) {
1307 if (max98095->sysclk == 0) {
1308 dev_err(codec->dev, "Invalid system clock frequency\n");
1309 return -EINVAL;
1310 }
1311 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1312 * (unsigned long long int)rate;
1313 do_div(ni, (unsigned long long int)max98095->sysclk);
1314 snd_soc_write(codec, M98095_032_DAI2_CLKCFG_HI,
1315 (ni >> 8) & 0x7F);
1316 snd_soc_write(codec, M98095_033_DAI2_CLKCFG_LO,
1317 ni & 0xFF);
1318 }
1319
1320 /* Update sample rate mode */
1321 if (rate < 50000)
1322 snd_soc_update_bits(codec, M98095_038_DAI2_FILTERS,
1323 M98095_DAI_DHF, 0);
1324 else
1325 snd_soc_update_bits(codec, M98095_038_DAI2_FILTERS,
1326 M98095_DAI_DHF, M98095_DAI_DHF);
1327
1328 return 0;
1329}
1330
1331static int max98095_dai3_hw_params(struct snd_pcm_substream *substream,
1332 struct snd_pcm_hw_params *params,
1333 struct snd_soc_dai *dai)
1334{
1335 struct snd_soc_codec *codec = dai->codec;
1336 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1337 struct max98095_cdata *cdata;
1338 unsigned long long ni;
1339 unsigned int rate;
1340 u8 regval;
1341
1342 cdata = &max98095->dai[2];
1343
1344 rate = params_rate(params);
1345
1ae1f3a2
MB		 1346 switch (params_width(params)) {
1347 case 16:
82a5a936
PH		 1348 snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT,
1349 M98095_DAI_WS, 0);
1350 break;
1ae1f3a2 1351 case 24:
82a5a936
PH		 1352 snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT,
1353 M98095_DAI_WS, M98095_DAI_WS);
1354 break;
1355 default:
1356 return -EINVAL;
1357 }
1358
1359 if (rate_value(rate, &regval))
1360 return -EINVAL;
1361
1362 snd_soc_update_bits(codec, M98095_03B_DAI3_CLKMODE,
1363 M98095_CLKMODE_MASK, regval);
1364 cdata->rate = rate;
1365
1366 /* Configure NI when operating as master */
1367 if (snd_soc_read(codec, M98095_03E_DAI3_FORMAT) & M98095_DAI_MAS) {
1368 if (max98095->sysclk == 0) {
1369 dev_err(codec->dev, "Invalid system clock frequency\n");
1370 return -EINVAL;
1371 }
1372 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1373 * (unsigned long long int)rate;
1374 do_div(ni, (unsigned long long int)max98095->sysclk);
1375 snd_soc_write(codec, M98095_03C_DAI3_CLKCFG_HI,
1376 (ni >> 8) & 0x7F);
1377 snd_soc_write(codec, M98095_03D_DAI3_CLKCFG_LO,
1378 ni & 0xFF);
1379 }
1380
1381 /* Update sample rate mode */
1382 if (rate < 50000)
1383 snd_soc_update_bits(codec, M98095_042_DAI3_FILTERS,
1384 M98095_DAI_DHF, 0);
1385 else
1386 snd_soc_update_bits(codec, M98095_042_DAI3_FILTERS,
1387 M98095_DAI_DHF, M98095_DAI_DHF);
1388
1389 return 0;
1390}
1391
1392static int max98095_dai_set_sysclk(struct snd_soc_dai *dai,
1393 int clk_id, unsigned int freq, int dir)
1394{
1395 struct snd_soc_codec *codec = dai->codec;
1396 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1397
1398 /* Requested clock frequency is already setup */
1399 if (freq == max98095->sysclk)
1400 return 0;
1401
e3048c3d
TB		 1402 if (!IS_ERR(max98095->mclk)) {
1403 freq = clk_round_rate(max98095->mclk, freq);
1404 clk_set_rate(max98095->mclk, freq);
1405 }
1406
82a5a936
PH		 1407 /* Setup clocks for slave mode, and using the PLL
1408 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
1409 * 0x02 (when master clk is 20MHz to 40MHz)..
1410 * 0x03 (when master clk is 40MHz to 60MHz)..
1411 */
1412 if ((freq >= 10000000) && (freq < 20000000)) {
1413 snd_soc_write(codec, M98095_026_SYS_CLK, 0x10);
1414 } else if ((freq >= 20000000) && (freq < 40000000)) {
1415 snd_soc_write(codec, M98095_026_SYS_CLK, 0x20);
1416 } else if ((freq >= 40000000) && (freq < 60000000)) {
1417 snd_soc_write(codec, M98095_026_SYS_CLK, 0x30);
1418 } else {
1419 dev_err(codec->dev, "Invalid master clock frequency\n");
1420 return -EINVAL;
1421 }
1422
1423 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
1424
1425 max98095->sysclk = freq;
1426 return 0;
1427}
1428
1429static int max98095_dai1_set_fmt(struct snd_soc_dai *codec_dai,
1430 unsigned int fmt)
1431{
1432 struct snd_soc_codec *codec = codec_dai->codec;
1433 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1434 struct max98095_cdata *cdata;
1435 u8 regval = 0;
1436
1437 cdata = &max98095->dai[0];
1438
1439 if (fmt != cdata->fmt) {
1440 cdata->fmt = fmt;
1441
1442 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1443 case SND_SOC_DAIFMT_CBS_CFS:
1444 /* Slave mode PLL */
1445 snd_soc_write(codec, M98095_028_DAI1_CLKCFG_HI,
1446 0x80);
1447 snd_soc_write(codec, M98095_029_DAI1_CLKCFG_LO,
1448 0x00);
1449 break;
1450 case SND_SOC_DAIFMT_CBM_CFM:
1451 /* Set to master mode */
1452 regval |= M98095_DAI_MAS;
1453 break;
1454 case SND_SOC_DAIFMT_CBS_CFM:
1455 case SND_SOC_DAIFMT_CBM_CFS:
1456 default:
1457 dev_err(codec->dev, "Clock mode unsupported");
1458 return -EINVAL;
1459 }
1460
1461 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1462 case SND_SOC_DAIFMT_I2S:
1463 regval |= M98095_DAI_DLY;
1464 break;
1465 case SND_SOC_DAIFMT_LEFT_J:
1466 break;
1467 default:
1468 return -EINVAL;
1469 }
1470
1471 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1472 case SND_SOC_DAIFMT_NB_NF:
1473 break;
1474 case SND_SOC_DAIFMT_NB_IF:
1475 regval |= M98095_DAI_WCI;
1476 break;
1477 case SND_SOC_DAIFMT_IB_NF:
1478 regval |= M98095_DAI_BCI;
1479 break;
1480 case SND_SOC_DAIFMT_IB_IF:
1481 regval |= M98095_DAI_BCI|M98095_DAI_WCI;
1482 break;
1483 default:
1484 return -EINVAL;
1485 }
1486
1487 snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT,
1488 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
1489 M98095_DAI_WCI, regval);
1490
1491 snd_soc_write(codec, M98095_02B_DAI1_CLOCK, M98095_DAI_BSEL64);
1492 }
1493
1494 return 0;
1495}
1496
1497static int max98095_dai2_set_fmt(struct snd_soc_dai *codec_dai,
1498 unsigned int fmt)
1499{
1500 struct snd_soc_codec *codec = codec_dai->codec;
1501 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1502 struct max98095_cdata *cdata;
1503 u8 regval = 0;
1504
1505 cdata = &max98095->dai[1];
1506
1507 if (fmt != cdata->fmt) {
1508 cdata->fmt = fmt;
1509
1510 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1511 case SND_SOC_DAIFMT_CBS_CFS:
1512 /* Slave mode PLL */
1513 snd_soc_write(codec, M98095_032_DAI2_CLKCFG_HI,
1514 0x80);
1515 snd_soc_write(codec, M98095_033_DAI2_CLKCFG_LO,
1516 0x00);
1517 break;
1518 case SND_SOC_DAIFMT_CBM_CFM:
1519 /* Set to master mode */
1520 regval |= M98095_DAI_MAS;
1521 break;
1522 case SND_SOC_DAIFMT_CBS_CFM:
1523 case SND_SOC_DAIFMT_CBM_CFS:
1524 default:
1525 dev_err(codec->dev, "Clock mode unsupported");
1526 return -EINVAL;
1527 }
1528
1529 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1530 case SND_SOC_DAIFMT_I2S:
1531 regval |= M98095_DAI_DLY;
1532 break;
1533 case SND_SOC_DAIFMT_LEFT_J:
1534 break;
1535 default:
1536 return -EINVAL;
1537 }
1538
1539 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1540 case SND_SOC_DAIFMT_NB_NF:
1541 break;
1542 case SND_SOC_DAIFMT_NB_IF:
1543 regval |= M98095_DAI_WCI;
1544 break;
1545 case SND_SOC_DAIFMT_IB_NF:
1546 regval |= M98095_DAI_BCI;
1547 break;
1548 case SND_SOC_DAIFMT_IB_IF:
1549 regval |= M98095_DAI_BCI|M98095_DAI_WCI;
1550 break;
1551 default:
1552 return -EINVAL;
1553 }
1554
1555 snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT,
1556 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
1557 M98095_DAI_WCI, regval);
1558
1559 snd_soc_write(codec, M98095_035_DAI2_CLOCK,
1560 M98095_DAI_BSEL64);
1561 }
1562
1563 return 0;
1564}
1565
1566static int max98095_dai3_set_fmt(struct snd_soc_dai *codec_dai,
1567 unsigned int fmt)
1568{
1569 struct snd_soc_codec *codec = codec_dai->codec;
1570 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1571 struct max98095_cdata *cdata;
1572 u8 regval = 0;
1573
1574 cdata = &max98095->dai[2];
1575
1576 if (fmt != cdata->fmt) {
1577 cdata->fmt = fmt;
1578
1579 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1580 case SND_SOC_DAIFMT_CBS_CFS:
1581 /* Slave mode PLL */
1582 snd_soc_write(codec, M98095_03C_DAI3_CLKCFG_HI,
1583 0x80);
1584 snd_soc_write(codec, M98095_03D_DAI3_CLKCFG_LO,
1585 0x00);
1586 break;
1587 case SND_SOC_DAIFMT_CBM_CFM:
1588 /* Set to master mode */
1589 regval |= M98095_DAI_MAS;
1590 break;
1591 case SND_SOC_DAIFMT_CBS_CFM:
1592 case SND_SOC_DAIFMT_CBM_CFS:
1593 default:
1594 dev_err(codec->dev, "Clock mode unsupported");
1595 return -EINVAL;
1596 }
1597
1598 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1599 case SND_SOC_DAIFMT_I2S:
1600 regval |= M98095_DAI_DLY;
1601 break;
1602 case SND_SOC_DAIFMT_LEFT_J:
1603 break;
1604 default:
1605 return -EINVAL;
1606 }
1607
1608 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1609 case SND_SOC_DAIFMT_NB_NF:
1610 break;
1611 case SND_SOC_DAIFMT_NB_IF:
1612 regval |= M98095_DAI_WCI;
1613 break;
1614 case SND_SOC_DAIFMT_IB_NF:
1615 regval |= M98095_DAI_BCI;
1616 break;
1617 case SND_SOC_DAIFMT_IB_IF:
1618 regval |= M98095_DAI_BCI|M98095_DAI_WCI;
1619 break;
1620 default:
1621 return -EINVAL;
1622 }
1623
1624 snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT,
1625 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
1626 M98095_DAI_WCI, regval);
1627
1628 snd_soc_write(codec, M98095_03F_DAI3_CLOCK,
1629 M98095_DAI_BSEL64);
1630 }
1631
1632 return 0;
1633}
1634
1635static int max98095_set_bias_level(struct snd_soc_codec *codec,
1636 enum snd_soc_bias_level level)
1637{
14acbbbb 1638 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
82a5a936
PH		 1639 int ret;
1640
1641 switch (level) {
1642 case SND_SOC_BIAS_ON:
1643 break;
1644
1645 case SND_SOC_BIAS_PREPARE:
e3048c3d
TB		 1646 /*
1647 * SND_SOC_BIAS_PREPARE is called while preparing for a
1648 * transition to ON or away from ON. If current bias_level
1649 * is SND_SOC_BIAS_ON, then it is preparing for a transition
1650 * away from ON. Disable the clock in that case, otherwise
1651 * enable it.
1652 */
1653 if (!IS_ERR(max98095->mclk)) {
1654 if (codec->dapm.bias_level == SND_SOC_BIAS_ON)
1655 clk_disable_unprepare(max98095->mclk);
1656 else
1657 clk_prepare_enable(max98095->mclk);
1658 }
82a5a936
PH		 1659 break;
1660
1661 case SND_SOC_BIAS_STANDBY:
1662 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
14acbbbb 1663 ret = regcache_sync(max98095->regmap);
82a5a936
PH		 1664
1665 if (ret != 0) {
1666 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
1667 return ret;
1668 }
1669 }
1670
1671 snd_soc_update_bits(codec, M98095_090_PWR_EN_IN,
1672 M98095_MBEN, M98095_MBEN);
1673 break;
1674
1675 case SND_SOC_BIAS_OFF:
1676 snd_soc_update_bits(codec, M98095_090_PWR_EN_IN,
1677 M98095_MBEN, 0);
14acbbbb 1678 regcache_mark_dirty(max98095->regmap);
82a5a936
PH		 1679 break;
1680 }
82a5a936
PH		 1681 return 0;
1682}
1683
1684#define MAX98095_RATES SNDRV_PCM_RATE_8000_96000
1685#define MAX98095_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
1686
85e7652d 1687static const struct snd_soc_dai_ops max98095_dai1_ops = {
82a5a936
PH		 1688 .set_sysclk = max98095_dai_set_sysclk,
1689 .set_fmt = max98095_dai1_set_fmt,
1690 .hw_params = max98095_dai1_hw_params,
1691};
1692
85e7652d 1693static const struct snd_soc_dai_ops max98095_dai2_ops = {
82a5a936
PH		 1694 .set_sysclk = max98095_dai_set_sysclk,
1695 .set_fmt = max98095_dai2_set_fmt,
1696 .hw_params = max98095_dai2_hw_params,
1697};
1698
85e7652d 1699static const struct snd_soc_dai_ops max98095_dai3_ops = {
82a5a936
PH		 1700 .set_sysclk = max98095_dai_set_sysclk,
1701 .set_fmt = max98095_dai3_set_fmt,
1702 .hw_params = max98095_dai3_hw_params,
1703};
1704
1705static struct snd_soc_dai_driver max98095_dai[] = {
1706{
1707 .name = "HiFi",
1708 .playback = {
1709 .stream_name = "HiFi Playback",
1710 .channels_min = 1,
1711 .channels_max = 2,
1712 .rates = MAX98095_RATES,
1713 .formats = MAX98095_FORMATS,
1714 },
1715 .capture = {
1716 .stream_name = "HiFi Capture",
1717 .channels_min = 1,
1718 .channels_max = 2,
1719 .rates = MAX98095_RATES,
1720 .formats = MAX98095_FORMATS,
1721 },
1722 .ops = &max98095_dai1_ops,
1723},
1724{
1725 .name = "Aux",
1726 .playback = {
1727 .stream_name = "Aux Playback",
1728 .channels_min = 1,
1729 .channels_max = 1,
1730 .rates = MAX98095_RATES,
1731 .formats = MAX98095_FORMATS,
1732 },
1733 .ops = &max98095_dai2_ops,
1734},
1735{
1736 .name = "Voice",
1737 .playback = {
1738 .stream_name = "Voice Playback",
1739 .channels_min = 1,
1740 .channels_max = 1,
1741 .rates = MAX98095_RATES,
1742 .formats = MAX98095_FORMATS,
1743 },
1744 .ops = &max98095_dai3_ops,
1745}
1746
1747};
1748
dad31ec1
PH		 1749static int max98095_get_eq_channel(const char *name)
1750{
1751 if (strcmp(name, "EQ1 Mode") == 0)
1752 return 0;
1753 if (strcmp(name, "EQ2 Mode") == 0)
1754 return 1;
1755 return -EINVAL;
1756}
1757
1758static int max98095_put_eq_enum(struct snd_kcontrol *kcontrol,
1759 struct snd_ctl_elem_value *ucontrol)
1760{
ea53bf77 1761 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
dad31ec1
PH		 1762 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1763 struct max98095_pdata *pdata = max98095->pdata;
1764 int channel = max98095_get_eq_channel(kcontrol->id.name);
1765 struct max98095_cdata *cdata;
f8d7b13e 1766 unsigned int sel = ucontrol->value.integer.value[0];
dad31ec1
PH		 1767 struct max98095_eq_cfg *coef_set;
1768 int fs, best, best_val, i;
1769 int regmask, regsave;
1770
a922cd71
TI		 1771 if (WARN_ON(channel > 1))
1772 return -EINVAL;
dad31ec1 1773
53949425
TH		 1774 if (!pdata || !max98095->eq_textcnt)
1775 return 0;
dad31ec1
PH		 1776
1777 if (sel >= pdata->eq_cfgcnt)
1778 return -EINVAL;
1779
53949425 1780 cdata = &max98095->dai[channel];
dad31ec1 1781 cdata->eq_sel = sel;
dad31ec1
PH		 1782 fs = cdata->rate;
1783
1784 /* Find the selected configuration with nearest sample rate */
1785 best = 0;
1786 best_val = INT_MAX;
1787 for (i = 0; i < pdata->eq_cfgcnt; i++) {
1788 if (strcmp(pdata->eq_cfg[i].name, max98095->eq_texts[sel]) == 0 &&
1789 abs(pdata->eq_cfg[i].rate - fs) < best_val) {
1790 best = i;
1791 best_val = abs(pdata->eq_cfg[i].rate - fs);
1792 }
1793 }
1794
1795 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n",
1796 pdata->eq_cfg[best].name,
1797 pdata->eq_cfg[best].rate, fs);
1798
1799 coef_set = &pdata->eq_cfg[best];
1800
1801 regmask = (channel == 0) ? M98095_EQ1EN : M98095_EQ2EN;
1802
1803 /* Disable filter while configuring, and save current on/off state */
1804 regsave = snd_soc_read(codec, M98095_088_CFG_LEVEL);
1805 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, 0);
1806
210a5fae 1807 mutex_lock(&max98095->lock);
dad31ec1
PH		 1808 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG);
1809 m98095_eq_band(codec, channel, 0, coef_set->band1);
1810 m98095_eq_band(codec, channel, 1, coef_set->band2);
1811 m98095_eq_band(codec, channel, 2, coef_set->band3);
1812 m98095_eq_band(codec, channel, 3, coef_set->band4);
1813 m98095_eq_band(codec, channel, 4, coef_set->band5);
1814 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, 0);
210a5fae 1815 mutex_unlock(&max98095->lock);
dad31ec1
PH		 1816
1817 /* Restore the original on/off state */
1818 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, regsave);
1819 return 0;
1820}
1821
1822static int max98095_get_eq_enum(struct snd_kcontrol *kcontrol,
1823 struct snd_ctl_elem_value *ucontrol)
1824{
ea53bf77 1825 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
dad31ec1
PH		 1826 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1827 int channel = max98095_get_eq_channel(kcontrol->id.name);
1828 struct max98095_cdata *cdata;
1829
1830 cdata = &max98095->dai[channel];
1831 ucontrol->value.enumerated.item[0] = cdata->eq_sel;
1832
1833 return 0;
1834}
1835
1836static void max98095_handle_eq_pdata(struct snd_soc_codec *codec)
1837{
1838 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1839 struct max98095_pdata *pdata = max98095->pdata;
1840 struct max98095_eq_cfg *cfg;
1841 unsigned int cfgcnt;
1842 int i, j;
1843 const char **t;
1844 int ret;
1845
1846 struct snd_kcontrol_new controls[] = {
1847 SOC_ENUM_EXT("EQ1 Mode",
1848 max98095->eq_enum,
1849 max98095_get_eq_enum,
1850 max98095_put_eq_enum),
1851 SOC_ENUM_EXT("EQ2 Mode",
1852 max98095->eq_enum,
1853 max98095_get_eq_enum,
1854 max98095_put_eq_enum),
1855 };
1856
1857 cfg = pdata->eq_cfg;
1858 cfgcnt = pdata->eq_cfgcnt;
1859
1860 /* Setup an array of texts for the equalizer enum.
1861 * This is based on Mark Brown's equalizer driver code.
1862 */
1863 max98095->eq_textcnt = 0;
1864 max98095->eq_texts = NULL;
1865 for (i = 0; i < cfgcnt; i++) {
1866 for (j = 0; j < max98095->eq_textcnt; j++) {
1867 if (strcmp(cfg[i].name, max98095->eq_texts[j]) == 0)
1868 break;
1869 }
1870
1871 if (j != max98095->eq_textcnt)
1872 continue;
1873
1874 /* Expand the array */
1875 t = krealloc(max98095->eq_texts,
1876 sizeof(char *) * (max98095->eq_textcnt + 1),
1877 GFP_KERNEL);
1878 if (t == NULL)
1879 continue;
1880
1881 /* Store the new entry */
1882 t[max98095->eq_textcnt] = cfg[i].name;
1883 max98095->eq_textcnt++;
1884 max98095->eq_texts = t;
1885 }
1886
1887 /* Now point the soc_enum to .texts array items */
1888 max98095->eq_enum.texts = max98095->eq_texts;
9a8d38db 1889 max98095->eq_enum.items = max98095->eq_textcnt;
dad31ec1 1890
022658be 1891 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls));
dad31ec1
PH		 1892 if (ret != 0)
1893 dev_err(codec->dev, "Failed to add EQ control: %d\n", ret);
1894}
1895
c855a1a7
RM		 1896static const char *bq_mode_name[] = {"Biquad1 Mode", "Biquad2 Mode"};
1897
1898static int max98095_get_bq_channel(struct snd_soc_codec *codec,
1899 const char *name)
dad31ec1 1900{
c855a1a7
RM		 1901 int i;
1902
1903 for (i = 0; i < ARRAY_SIZE(bq_mode_name); i++)
1904 if (strcmp(name, bq_mode_name[i]) == 0)
1905 return i;
1906
1907 /* Shouldn't happen */
1908 dev_err(codec->dev, "Bad biquad channel name '%s'\n", name);
dad31ec1
PH		 1909 return -EINVAL;
1910}
1911
1912static int max98095_put_bq_enum(struct snd_kcontrol *kcontrol,
1913 struct snd_ctl_elem_value *ucontrol)
1914{
ea53bf77 1915 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
dad31ec1
PH		 1916 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1917 struct max98095_pdata *pdata = max98095->pdata;
c855a1a7 1918 int channel = max98095_get_bq_channel(codec, kcontrol->id.name);
dad31ec1 1919 struct max98095_cdata *cdata;
f8d7b13e 1920 unsigned int sel = ucontrol->value.integer.value[0];
dad31ec1
PH		 1921 struct max98095_biquad_cfg *coef_set;
1922 int fs, best, best_val, i;
1923 int regmask, regsave;
1924
c855a1a7
RM		 1925 if (channel < 0)
1926 return channel;
dad31ec1 1927
53949425
TH		 1928 if (!pdata || !max98095->bq_textcnt)
1929 return 0;
dad31ec1
PH		 1930
1931 if (sel >= pdata->bq_cfgcnt)
1932 return -EINVAL;
1933
53949425 1934 cdata = &max98095->dai[channel];
dad31ec1 1935 cdata->bq_sel = sel;
dad31ec1
PH		 1936 fs = cdata->rate;
1937
1938 /* Find the selected configuration with nearest sample rate */
1939 best = 0;
1940 best_val = INT_MAX;
1941 for (i = 0; i < pdata->bq_cfgcnt; i++) {
1942 if (strcmp(pdata->bq_cfg[i].name, max98095->bq_texts[sel]) == 0 &&
1943 abs(pdata->bq_cfg[i].rate - fs) < best_val) {
1944 best = i;
1945 best_val = abs(pdata->bq_cfg[i].rate - fs);
1946 }
1947 }
1948
1949 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n",
1950 pdata->bq_cfg[best].name,
1951 pdata->bq_cfg[best].rate, fs);
1952
1953 coef_set = &pdata->bq_cfg[best];
1954
1955 regmask = (channel == 0) ? M98095_BQ1EN : M98095_BQ2EN;
1956
1957 /* Disable filter while configuring, and save current on/off state */
1958 regsave = snd_soc_read(codec, M98095_088_CFG_LEVEL);
1959 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, 0);
1960
210a5fae 1961 mutex_lock(&max98095->lock);
dad31ec1
PH		 1962 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG);
1963 m98095_biquad_band(codec, channel, 0, coef_set->band1);
1964 m98095_biquad_band(codec, channel, 1, coef_set->band2);
1965 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, 0);
210a5fae 1966 mutex_unlock(&max98095->lock);
dad31ec1
PH		 1967
1968 /* Restore the original on/off state */
1969 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, regsave);
1970 return 0;
1971}
1972
1973static int max98095_get_bq_enum(struct snd_kcontrol *kcontrol,
1974 struct snd_ctl_elem_value *ucontrol)
1975{
ea53bf77 1976 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
dad31ec1 1977 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
c855a1a7 1978 int channel = max98095_get_bq_channel(codec, kcontrol->id.name);
dad31ec1
PH		 1979 struct max98095_cdata *cdata;
1980
c855a1a7
RM		 1981 if (channel < 0)
1982 return channel;
1983
dad31ec1
PH		 1984 cdata = &max98095->dai[channel];
1985 ucontrol->value.enumerated.item[0] = cdata->bq_sel;
1986
1987 return 0;
1988}
1989
1990static void max98095_handle_bq_pdata(struct snd_soc_codec *codec)
1991{
1992 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1993 struct max98095_pdata *pdata = max98095->pdata;
1994 struct max98095_biquad_cfg *cfg;
1995 unsigned int cfgcnt;
1996 int i, j;
1997 const char **t;
1998 int ret;
1999
2000 struct snd_kcontrol_new controls[] = {
c855a1a7 2001 SOC_ENUM_EXT((char *)bq_mode_name[0],
dad31ec1
PH		 2002 max98095->bq_enum,
2003 max98095_get_bq_enum,
2004 max98095_put_bq_enum),
c855a1a7 2005 SOC_ENUM_EXT((char *)bq_mode_name[1],
dad31ec1
PH		 2006 max98095->bq_enum,
2007 max98095_get_bq_enum,
2008 max98095_put_bq_enum),
2009 };
c855a1a7 2010 BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(bq_mode_name));
dad31ec1
PH		 2011
2012 cfg = pdata->bq_cfg;
2013 cfgcnt = pdata->bq_cfgcnt;
2014
2015 /* Setup an array of texts for the biquad enum.
2016 * This is based on Mark Brown's equalizer driver code.
2017 */
2018 max98095->bq_textcnt = 0;
2019 max98095->bq_texts = NULL;
2020 for (i = 0; i < cfgcnt; i++) {
2021 for (j = 0; j < max98095->bq_textcnt; j++) {
2022 if (strcmp(cfg[i].name, max98095->bq_texts[j]) == 0)
2023 break;
2024 }
2025
2026 if (j != max98095->bq_textcnt)
2027 continue;
2028
2029 /* Expand the array */
2030 t = krealloc(max98095->bq_texts,
2031 sizeof(char *) * (max98095->bq_textcnt + 1),
2032 GFP_KERNEL);
2033 if (t == NULL)
2034 continue;
2035
2036 /* Store the new entry */
2037 t[max98095->bq_textcnt] = cfg[i].name;
2038 max98095->bq_textcnt++;
2039 max98095->bq_texts = t;
2040 }
2041
2042 /* Now point the soc_enum to .texts array items */
2043 max98095->bq_enum.texts = max98095->bq_texts;
9a8d38db 2044 max98095->bq_enum.items = max98095->bq_textcnt;
dad31ec1 2045
022658be 2046 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls));
dad31ec1
PH		 2047 if (ret != 0)
2048 dev_err(codec->dev, "Failed to add Biquad control: %d\n", ret);
2049}
2050
82a5a936
PH		 2051static void max98095_handle_pdata(struct snd_soc_codec *codec)
2052{
2053 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2054 struct max98095_pdata *pdata = max98095->pdata;
2055 u8 regval = 0;
2056
2057 if (!pdata) {
2058 dev_dbg(codec->dev, "No platform data\n");
2059 return;
2060 }
2061
2062 /* Configure mic for analog/digital mic mode */
2063 if (pdata->digmic_left_mode)
2064 regval |= M98095_DIGMIC_L;
2065
2066 if (pdata->digmic_right_mode)
2067 regval |= M98095_DIGMIC_R;
2068
2069 snd_soc_write(codec, M98095_087_CFG_MIC, regval);
dad31ec1
PH		 2070
2071 /* Configure equalizers */
2072 if (pdata->eq_cfgcnt)
2073 max98095_handle_eq_pdata(codec);
2074
2075 /* Configure bi-quad filters */
2076 if (pdata->bq_cfgcnt)
2077 max98095_handle_bq_pdata(codec);
82a5a936
PH		 2078}
2079
9dd90c5d
RK		 2080static irqreturn_t max98095_report_jack(int irq, void *data)
2081{
2082 struct snd_soc_codec *codec = data;
2083 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2084 unsigned int value;
2085 int hp_report = 0;
2086 int mic_report = 0;
2087
2088 /* Read the Jack Status Register */
2089 value = snd_soc_read(codec, M98095_007_JACK_AUTO_STS);
2090
2091 /* If ddone is not set, then detection isn't finished yet */
2092 if ((value & M98095_DDONE) == 0)
2093 return IRQ_NONE;
2094
2095 /* if hp, check its bit, and if set, clear it */
2096 if ((value & M98095_HP_IN || value & M98095_LO_IN) &&
2097 max98095->headphone_jack)
2098 hp_report |= SND_JACK_HEADPHONE;
2099
2100 /* if mic, check its bit, and if set, clear it */
2101 if ((value & M98095_MIC_IN) && max98095->mic_jack)
2102 mic_report |= SND_JACK_MICROPHONE;
2103
2104 if (max98095->headphone_jack == max98095->mic_jack) {
2105 snd_soc_jack_report(max98095->headphone_jack,
2106 hp_report | mic_report,
2107 SND_JACK_HEADSET);
2108 } else {
2109 if (max98095->headphone_jack)
2110 snd_soc_jack_report(max98095->headphone_jack,
2111 hp_report, SND_JACK_HEADPHONE);
2112 if (max98095->mic_jack)
2113 snd_soc_jack_report(max98095->mic_jack,
2114 mic_report, SND_JACK_MICROPHONE);
2115 }
2116
2117 return IRQ_HANDLED;
2118}
2119
a265367c 2120static int max98095_jack_detect_enable(struct snd_soc_codec *codec)
9dd90c5d
RK		 2121{
2122 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2123 int ret = 0;
2124 int detect_enable = M98095_JDEN;
2125 unsigned int slew = M98095_DEFAULT_SLEW_DELAY;
2126
2127 if (max98095->pdata->jack_detect_pin5en)
2128 detect_enable |= M98095_PIN5EN;
2129
0841b04a
MB		 2130 if (max98095->pdata->jack_detect_delay)
2131 slew = max98095->pdata->jack_detect_delay;
9dd90c5d
RK		 2132
2133 ret = snd_soc_write(codec, M98095_08E_JACK_DC_SLEW, slew);
2134 if (ret < 0) {
2135 dev_err(codec->dev, "Failed to cfg auto detect %d\n", ret);
2136 return ret;
2137 }
2138
2139 /* configure auto detection to be enabled */
2140 ret = snd_soc_write(codec, M98095_089_JACK_DET_AUTO, detect_enable);
2141 if (ret < 0) {
2142 dev_err(codec->dev, "Failed to cfg auto detect %d\n", ret);
2143 return ret;
2144 }
2145
2146 return ret;
2147}
2148
a265367c 2149static int max98095_jack_detect_disable(struct snd_soc_codec *codec)
9dd90c5d
RK		 2150{
2151 int ret = 0;
2152
2153 /* configure auto detection to be disabled */
2154 ret = snd_soc_write(codec, M98095_089_JACK_DET_AUTO, 0x0);
2155 if (ret < 0) {
2156 dev_err(codec->dev, "Failed to cfg auto detect %d\n", ret);
2157 return ret;
2158 }
2159
2160 return ret;
2161}
2162
2163int max98095_jack_detect(struct snd_soc_codec *codec,
2164 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack)
2165{
2166 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2167 struct i2c_client *client = to_i2c_client(codec->dev);
2168 int ret = 0;
2169
2170 max98095->headphone_jack = hp_jack;
2171 max98095->mic_jack = mic_jack;
2172
2173 /* only progress if we have at least 1 jack pointer */
2174 if (!hp_jack && !mic_jack)
2175 return -EINVAL;
2176
2177 max98095_jack_detect_enable(codec);
2178
2179 /* enable interrupts for headphone jack detection */
2180 ret = snd_soc_update_bits(codec, M98095_013_JACK_INT_EN,
2181 M98095_IDDONE, M98095_IDDONE);
2182 if (ret < 0) {
2183 dev_err(codec->dev, "Failed to cfg jack irqs %d\n", ret);
2184 return ret;
2185 }
2186
2187 max98095_report_jack(client->irq, codec);
2188 return 0;
2189}
a265367c 2190EXPORT_SYMBOL_GPL(max98095_jack_detect);
9dd90c5d 2191
82a5a936 2192#ifdef CONFIG_PM
84b315ee 2193static int max98095_suspend(struct snd_soc_codec *codec)
82a5a936 2194{
9dd90c5d
RK		 2195 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2196
2197 if (max98095->headphone_jack || max98095->mic_jack)
2198 max98095_jack_detect_disable(codec);
2199
bd1204cb 2200 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
82a5a936
PH		 2201
2202 return 0;
2203}
2204
2205static int max98095_resume(struct snd_soc_codec *codec)
2206{
9dd90c5d
RK		 2207 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2208 struct i2c_client *client = to_i2c_client(codec->dev);
2209
bd1204cb 2210 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_STANDBY);
82a5a936 2211
9dd90c5d
RK		 2212 if (max98095->headphone_jack || max98095->mic_jack) {
2213 max98095_jack_detect_enable(codec);
2214 max98095_report_jack(client->irq, codec);
2215 }
2216
82a5a936
PH		 2217 return 0;
2218}
2219#else
2220#define max98095_suspend NULL
2221#define max98095_resume NULL
2222#endif
2223
2224static int max98095_reset(struct snd_soc_codec *codec)
2225{
2226 int i, ret;
2227
2228 /* Gracefully reset the DSP core and the codec hardware
2229 * in a proper sequence */
2230 ret = snd_soc_write(codec, M98095_00F_HOST_CFG, 0);
2231 if (ret < 0) {
2232 dev_err(codec->dev, "Failed to reset DSP: %d\n", ret);
2233 return ret;
2234 }
2235
2236 ret = snd_soc_write(codec, M98095_097_PWR_SYS, 0);
2237 if (ret < 0) {
2238 dev_err(codec->dev, "Failed to reset codec: %d\n", ret);
2239 return ret;
2240 }
2241
2242 /* Reset to hardware default for registers, as there is not
2243 * a soft reset hardware control register */
2244 for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) {
14acbbbb 2245 ret = snd_soc_write(codec, i, snd_soc_read(codec, i));
82a5a936
PH		 2246 if (ret < 0) {
2247 dev_err(codec->dev, "Failed to reset: %d\n", ret);
2248 return ret;
2249 }
2250 }
2251
2252 return ret;
2253}
2254
2255static int max98095_probe(struct snd_soc_codec *codec)
2256{
2257 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2258 struct max98095_cdata *cdata;
9dd90c5d 2259 struct i2c_client *client;
82a5a936
PH		 2260 int ret = 0;
2261
e3048c3d
TB		 2262 max98095->mclk = devm_clk_get(codec->dev, "mclk");
2263 if (PTR_ERR(max98095->mclk) == -EPROBE_DEFER)
2264 return -EPROBE_DEFER;
2265
82a5a936
PH		 2266 /* reset the codec, the DSP core, and disable all interrupts */
2267 max98095_reset(codec);
2268
9dd90c5d
RK		 2269 client = to_i2c_client(codec->dev);
2270
82a5a936
PH		 2271 /* initialize private data */
2272
2273 max98095->sysclk = (unsigned)-1;
dad31ec1
PH		 2274 max98095->eq_textcnt = 0;
2275 max98095->bq_textcnt = 0;
82a5a936
PH		 2276
2277 cdata = &max98095->dai[0];
2278 cdata->rate = (unsigned)-1;
2279 cdata->fmt = (unsigned)-1;
dad31ec1
PH		 2280 cdata->eq_sel = 0;
2281 cdata->bq_sel = 0;
82a5a936
PH		 2282
2283 cdata = &max98095->dai[1];
2284 cdata->rate = (unsigned)-1;
2285 cdata->fmt = (unsigned)-1;
dad31ec1
PH		 2286 cdata->eq_sel = 0;
2287 cdata->bq_sel = 0;
82a5a936
PH		 2288
2289 cdata = &max98095->dai[2];
2290 cdata->rate = (unsigned)-1;
2291 cdata->fmt = (unsigned)-1;
dad31ec1
PH		 2292 cdata->eq_sel = 0;
2293 cdata->bq_sel = 0;
82a5a936
PH		 2294
2295 max98095->lin_state = 0;
2296 max98095->mic1pre = 0;
2297 max98095->mic2pre = 0;
2298
9dd90c5d
RK		 2299 if (client->irq) {
2300 /* register an audio interrupt */
2301 ret = request_threaded_irq(client->irq, NULL,
2302 max98095_report_jack,
2303 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
2304 "max98095", codec);
2305 if (ret) {
2306 dev_err(codec->dev, "Failed to request IRQ: %d\n", ret);
2307 goto err_access;
2308 }
2309 }
2310
82a5a936
PH		 2311 ret = snd_soc_read(codec, M98095_0FF_REV_ID);
2312 if (ret < 0) {
bab3b59d 2313 dev_err(codec->dev, "Failure reading hardware revision: %d\n",
82a5a936 2314 ret);
9dd90c5d 2315 goto err_irq;
82a5a936 2316 }
bab3b59d 2317 dev_info(codec->dev, "Hardware revision: %c\n", ret - 0x40 + 'A');
82a5a936
PH		 2318
2319 snd_soc_write(codec, M98095_097_PWR_SYS, M98095_PWRSV);
2320
82a5a936
PH		 2321 snd_soc_write(codec, M98095_048_MIX_DAC_LR,
2322 M98095_DAI1L_TO_DACL|M98095_DAI1R_TO_DACR);
2323
2324 snd_soc_write(codec, M98095_049_MIX_DAC_M,
2325 M98095_DAI2M_TO_DACM|M98095_DAI3M_TO_DACM);
2326
2327 snd_soc_write(codec, M98095_092_PWR_EN_OUT, M98095_SPK_SPREADSPECTRUM);
2328 snd_soc_write(codec, M98095_045_CFG_DSP, M98095_DSPNORMAL);
2329 snd_soc_write(codec, M98095_04E_CFG_HP, M98095_HPNORMAL);
2330
2331 snd_soc_write(codec, M98095_02C_DAI1_IOCFG,
2332 M98095_S1NORMAL|M98095_SDATA);
2333
2334 snd_soc_write(codec, M98095_036_DAI2_IOCFG,
2335 M98095_S2NORMAL|M98095_SDATA);
2336
2337 snd_soc_write(codec, M98095_040_DAI3_IOCFG,
2338 M98095_S3NORMAL|M98095_SDATA);
2339
2340 max98095_handle_pdata(codec);
2341
2342 /* take the codec out of the shut down */
2343 snd_soc_update_bits(codec, M98095_097_PWR_SYS, M98095_SHDNRUN,
2344 M98095_SHDNRUN);
2345
9dd90c5d
RK		 2346 return 0;
2347
2348err_irq:
2349 if (client->irq)
2350 free_irq(client->irq, codec);
82a5a936
PH		 2351err_access:
2352 return ret;
2353}
2354
2355static int max98095_remove(struct snd_soc_codec *codec)
2356{
9dd90c5d
RK		 2357 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2358 struct i2c_client *client = to_i2c_client(codec->dev);
2359
9dd90c5d
RK		 2360 if (max98095->headphone_jack || max98095->mic_jack)
2361 max98095_jack_detect_disable(codec);
2362
2363 if (client->irq)
2364 free_irq(client->irq, codec);
2365
82a5a936
PH		 2366 return 0;
2367}
2368
2369static struct snd_soc_codec_driver soc_codec_dev_max98095 = {
2370 .probe = max98095_probe,
2371 .remove = max98095_remove,
2372 .suspend = max98095_suspend,
2373 .resume = max98095_resume,
2374 .set_bias_level = max98095_set_bias_level,
c6b3283f
MB		 2375 .controls = max98095_snd_controls,
2376 .num_controls = ARRAY_SIZE(max98095_snd_controls),
82a5a936
PH		 2377 .dapm_widgets = max98095_dapm_widgets,
2378 .num_dapm_widgets = ARRAY_SIZE(max98095_dapm_widgets),
2379 .dapm_routes = max98095_audio_map,
2380 .num_dapm_routes = ARRAY_SIZE(max98095_audio_map),
2381};
2382
2383static int max98095_i2c_probe(struct i2c_client *i2c,
2384 const struct i2c_device_id *id)
2385{
2386 struct max98095_priv *max98095;
2387 int ret;
2388
b1b54882
AL		 2389 max98095 = devm_kzalloc(&i2c->dev, sizeof(struct max98095_priv),
2390 GFP_KERNEL);
82a5a936
PH		 2391 if (max98095 == NULL)
2392 return -ENOMEM;
2393
210a5fae
LPC		 2394 mutex_init(&max98095->lock);
2395
14acbbbb
MB		 2396 max98095->regmap = devm_regmap_init_i2c(i2c, &max98095_regmap);
2397 if (IS_ERR(max98095->regmap)) {
2398 ret = PTR_ERR(max98095->regmap);
2399 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
2400 return ret;
2401 }
2402
82a5a936
PH		 2403 max98095->devtype = id->driver_data;
2404 i2c_set_clientdata(i2c, max98095);
82a5a936
PH		 2405 max98095->pdata = i2c->dev.platform_data;
2406
bab3b59d
TH		 2407 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_max98095,
2408 max98095_dai, ARRAY_SIZE(max98095_dai));
82a5a936
PH		 2409 return ret;
2410}
2411
7a79e94e 2412static int max98095_i2c_remove(struct i2c_client *client)
82a5a936
PH		 2413{
2414 snd_soc_unregister_codec(&client->dev);
82a5a936
PH		 2415 return 0;
2416}
2417
2418static const struct i2c_device_id max98095_i2c_id[] = {
2419 { "max98095", MAX98095 },
2420 { }
2421};
2422MODULE_DEVICE_TABLE(i2c, max98095_i2c_id);
2423
c4839c87
TB		 2424static const struct of_device_id max98095_of_match[] = {
2425 { .compatible = "maxim,max98095", },
2426 { }
2427};
2428MODULE_DEVICE_TABLE(of, max98095_of_match);
2429
82a5a936
PH		 2430static struct i2c_driver max98095_i2c_driver = {
2431 .driver = {
2432 .name = "max98095",
2433 .owner = THIS_MODULE,
c4839c87 2434 .of_match_table = of_match_ptr(max98095_of_match),
82a5a936
PH		 2435 },
2436 .probe = max98095_i2c_probe,
7a79e94e 2437 .remove = max98095_i2c_remove,
82a5a936
PH		 2438 .id_table = max98095_i2c_id,
2439};
2440
a8af02cf 2441module_i2c_driver(max98095_i2c_driver);
82a5a936
PH		 2442
2443MODULE_DESCRIPTION("ALSA SoC MAX98095 driver");
2444MODULE_AUTHOR("Peter Hsiang");
2445MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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